libpcsxcore/new_dynarec/new_dynarec.c

   1 /* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
   2  *   Mupen64plus - new_dynarec.c                                           *
   3  *   Copyright (C) 2009-2010 Ari64                                         *
   4  *                                                                         *
   5  *   This program is free software; you can redistribute it and/or modify  *
   6  *   it under the terms of the GNU General Public License as published by  *
   7  *   the Free Software Foundation; either version 2 of the License, or     *
   8  *   (at your option) any later version.                                   *
   9  *                                                                         *
  10  *   This program is distributed in the hope that it will be useful,       *
  11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  13  *   GNU General Public License for more details.                          *
  14  *                                                                         *
  15  *   You should have received a copy of the GNU General Public License     *
  16  *   along with this program; if not, write to the                         *
  17  *   Free Software Foundation, Inc.,                                       *
  18  *   51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.          *
  19  * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
  20
  21 #include <stdlib.h>
  22 #include <stdint.h> //include for uint64_t
  23 #include <assert.h>
  24
  25 #include "emu_if.h" //emulator interface
  26
  27 #include <sys/mman.h>
  28
  29 #ifdef __i386__
  30 #include "assem_x86.h"
  31 #endif
  32 #ifdef __x86_64__
  33 #include "assem_x64.h"
  34 #endif
  35 #ifdef __arm__
  36 #include "assem_arm.h"
  37 #endif
  38
  39 #define MAXBLOCK 4096
  40 #define MAX_OUTPUT_BLOCK_SIZE 262144
  41 #define CLOCK_DIVIDER 2
  42
  43 struct regstat
  44 {
  45   signed char regmap_entry[HOST_REGS];
  46   signed char regmap[HOST_REGS];
  47   uint64_t was32;
  48   uint64_t is32;
  49   uint64_t wasdirty;
  50   uint64_t dirty;
  51   uint64_t u;
  52   uint64_t uu;
  53   u_int wasconst;
  54   u_int isconst;
  55   uint64_t constmap[HOST_REGS];
  56 };
  57
  58 struct ll_entry
  59 {
  60   u_int vaddr;
  61   u_int reg32;
  62   void *addr;
  63   struct ll_entry *next;
  64 };
  65
  66   u_int start;
  67   u_int *source;
  68   u_int pagelimit;
  69   char insn[MAXBLOCK][10];
  70   u_char itype[MAXBLOCK];
  71   u_char opcode[MAXBLOCK];
  72   u_char opcode2[MAXBLOCK];
  73   u_char bt[MAXBLOCK];
  74   u_char rs1[MAXBLOCK];
  75   u_char rs2[MAXBLOCK];
  76   u_char rt1[MAXBLOCK];
  77   u_char rt2[MAXBLOCK];
  78   u_char us1[MAXBLOCK];
  79   u_char us2[MAXBLOCK];
  80   u_char dep1[MAXBLOCK];
  81   u_char dep2[MAXBLOCK];
  82   u_char lt1[MAXBLOCK];
  83   int imm[MAXBLOCK];
  84   u_int ba[MAXBLOCK];
  85   char likely[MAXBLOCK];
  86   char is_ds[MAXBLOCK];
  87   char ooo[MAXBLOCK];
  88   uint64_t unneeded_reg[MAXBLOCK];
  89   uint64_t unneeded_reg_upper[MAXBLOCK];
  90   uint64_t branch_unneeded_reg[MAXBLOCK];
  91   uint64_t branch_unneeded_reg_upper[MAXBLOCK];
  92   uint64_t p32[MAXBLOCK];
  93   uint64_t pr32[MAXBLOCK];
  94   signed char regmap_pre[MAXBLOCK][HOST_REGS];
  95   signed char regmap[MAXBLOCK][HOST_REGS];
  96   signed char regmap_entry[MAXBLOCK][HOST_REGS];
  97   uint64_t constmap[MAXBLOCK][HOST_REGS];
  98   struct regstat regs[MAXBLOCK];
  99   struct regstat branch_regs[MAXBLOCK];
 100   signed char minimum_free_regs[MAXBLOCK];
 101   u_int needed_reg[MAXBLOCK];
 102   uint64_t requires_32bit[MAXBLOCK];
 103   u_int wont_dirty[MAXBLOCK];
 104   u_int will_dirty[MAXBLOCK];
 105   int ccadj[MAXBLOCK];
 106   int slen;
 107   u_int instr_addr[MAXBLOCK];
 108   u_int link_addr[MAXBLOCK][3];
 109   int linkcount;
 110   u_int stubs[MAXBLOCK*3][8];
 111   int stubcount;
 112   u_int literals[1024][2];
 113   int literalcount;
 114   int is_delayslot;
 115   int cop1_usable;
 116   u_char *out;
 117   struct ll_entry *jump_in[4096];
 118   struct ll_entry *jump_out[4096];
 119   struct ll_entry *jump_dirty[4096];
 120   u_int hash_table[65536][4]  __attribute__((aligned(16)));
 121   char shadow[1048576]  __attribute__((aligned(16)));
 122   void *copy;
 123   int expirep;
 124   u_int using_tlb;
 125   u_int stop_after_jal;
 126   extern u_char restore_candidate[512];
 127   extern int cycle_count;
 128
 129   /* registers that may be allocated */
 130   /* 1-31 gpr */
 131 #define HIREG 32 // hi
 132 #define LOREG 33 // lo
 133 #define FSREG 34 // FPU status (FCSR)
 134 #define CSREG 35 // Coprocessor status
 135 #define CCREG 36 // Cycle count
 136 #define INVCP 37 // Pointer to invalid_code
 137 #define TEMPREG 38
 138 #define FTEMP 38 // FPU/LDL/LDR temporary register
 139 #define PTEMP 39 // Prefetch temporary register
 140 #define TLREG 40 // TLB mapping offset
 141 #define RHASH 41 // Return address hash
 142 #define RHTBL 42 // Return address hash table address
 143 #define RTEMP 43 // JR/JALR address register
 144 #define MAXREG 43
 145 #define AGEN1 44 // Address generation temporary register
 146 #define AGEN2 45 // Address generation temporary register
 147 #define MGEN1 46 // Maptable address generation temporary register
 148 #define MGEN2 47 // Maptable address generation temporary register
 149 #define BTREG 48 // Branch target temporary register
 150
 151   /* instruction types */
 152 #define NOP 0     // No operation
 153 #define LOAD 1    // Load
 154 #define STORE 2   // Store
 155 #define LOADLR 3  // Unaligned load
 156 #define STORELR 4 // Unaligned store
 157 #define MOV 5     // Move
 158 #define ALU 6     // Arithmetic/logic
 159 #define MULTDIV 7 // Multiply/divide
 160 #define SHIFT 8   // Shift by register
 161 #define SHIFTIMM 9// Shift by immediate
 162 #define IMM16 10  // 16-bit immediate
 163 #define RJUMP 11  // Unconditional jump to register
 164 #define UJUMP 12  // Unconditional jump
 165 #define CJUMP 13  // Conditional branch (BEQ/BNE/BGTZ/BLEZ)
 166 #define SJUMP 14  // Conditional branch (regimm format)
 167 #define COP0 15   // Coprocessor 0
 168 #define COP1 16   // Coprocessor 1
 169 #define C1LS 17   // Coprocessor 1 load/store
 170 #define FJUMP 18  // Conditional branch (floating point)
 171 #define FLOAT 19  // Floating point unit
 172 #define FCONV 20  // Convert integer to float
 173 #define FCOMP 21  // Floating point compare (sets FSREG)
 174 #define SYSCALL 22// SYSCALL
 175 #define OTHER 23  // Other
 176 #define SPAN 24   // Branch/delay slot spans 2 pages
 177 #define NI 25     // Not implemented
 178 #define HLECALL 26// PCSX fake opcodes for HLE
 179 #define COP2 27   // Coprocessor 2 move
 180 #define C2LS 28   // Coprocessor 2 load/store
 181 #define C2OP 29   // Coprocessor 2 operation
 182 #define INTCALL 30// Call interpreter to handle rare corner cases
 183
 184   /* stubs */
 185 #define CC_STUB 1
 186 #define FP_STUB 2
 187 #define LOADB_STUB 3
 188 #define LOADH_STUB 4
 189 #define LOADW_STUB 5
 190 #define LOADD_STUB 6
 191 #define LOADBU_STUB 7
 192 #define LOADHU_STUB 8
 193 #define STOREB_STUB 9
 194 #define STOREH_STUB 10
 195 #define STOREW_STUB 11
 196 #define STORED_STUB 12
 197 #define STORELR_STUB 13
 198 #define INVCODE_STUB 14
 199
 200   /* branch codes */
 201 #define TAKEN 1
 202 #define NOTTAKEN 2
 203 #define NULLDS 3
 204
 205 // asm linkage
 206 int new_recompile_block(int addr);
 207 void *get_addr_ht(u_int vaddr);
 208 void invalidate_block(u_int block);
 209 void invalidate_addr(u_int addr);
 210 void remove_hash(int vaddr);
 211 void jump_vaddr();
 212 void dyna_linker();
 213 void dyna_linker_ds();
 214 void verify_code();
 215 void verify_code_vm();
 216 void verify_code_ds();
 217 void cc_interrupt();
 218 void fp_exception();
 219 void fp_exception_ds();
 220 void jump_syscall();
 221 void jump_syscall_hle();
 222 void jump_eret();
 223 void jump_hlecall();
 224 void jump_intcall();
 225 void new_dyna_leave();
 226
 227 // TLB
 228 void TLBWI_new();
 229 void TLBWR_new();
 230 void read_nomem_new();
 231 void read_nomemb_new();
 232 void read_nomemh_new();
 233 void read_nomemd_new();
 234 void write_nomem_new();
 235 void write_nomemb_new();
 236 void write_nomemh_new();
 237 void write_nomemd_new();
 238 void write_rdram_new();
 239 void write_rdramb_new();
 240 void write_rdramh_new();
 241 void write_rdramd_new();
 242 extern u_int memory_map[1048576];
 243
 244 // Needed by assembler
 245 void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32);
 246 void wb_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty);
 247 void wb_needed_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr);
 248 void load_all_regs(signed char i_regmap[]);
 249 void load_needed_regs(signed char i_regmap[],signed char next_regmap[]);
 250 void load_regs_entry(int t);
 251 void load_all_consts(signed char regmap[],int is32,u_int dirty,int i);
 252
 253 int tracedebug=0;
 254
 255 //#define DEBUG_CYCLE_COUNT 1
 256
 257 void nullf() {}
 258 //#define assem_debug printf
 259 //#define inv_debug printf
 260 #define assem_debug nullf
 261 #define inv_debug nullf
 262
 263 static void tlb_hacks()
 264 {
 265 #ifndef DISABLE_TLB
 266   // Goldeneye hack
 267   if (strncmp((char *) ROM_HEADER->nom, "GOLDENEYE",9) == 0)
 268   {
 269     u_int addr;
 270     int n;
 271     switch (ROM_HEADER->Country_code&0xFF)
 272     {
 273       case 0x45: // U
 274         addr=0x34b30;
 275         break;
 276       case 0x4A: // J
 277         addr=0x34b70;
 278         break;
 279       case 0x50: // E
 280         addr=0x329f0;
 281         break;
 282       default:
 283         // Unknown country code
 284         addr=0;
 285         break;
 286     }
 287     u_int rom_addr=(u_int)rom;
 288     #ifdef ROM_COPY
 289     // Since memory_map is 32-bit, on 64-bit systems the rom needs to be
 290     // in the lower 4G of memory to use this hack.  Copy it if necessary.
 291     if((void *)rom>(void *)0xffffffff) {
 292       munmap(ROM_COPY, 67108864);
 293       if(mmap(ROM_COPY, 12582912,
 294               PROT_READ | PROT_WRITE,
 295               MAP_FIXED | MAP_PRIVATE | MAP_ANONYMOUS,
 296               -1, 0) <= 0) {printf("mmap() failed\n");}
 297       memcpy(ROM_COPY,rom,12582912);
 298       rom_addr=(u_int)ROM_COPY;
 299     }
 300     #endif
 301     if(addr) {
 302       for(n=0x7F000;n<0x80000;n++) {
 303         memory_map[n]=(((u_int)(rom_addr+addr-0x7F000000))>>2)|0x40000000;
 304       }
 305     }
 306   }
 307 #endif
 308 }
 309
 310 static u_int get_page(u_int vaddr)
 311 {
 312 #ifndef PCSX
 313   u_int page=(vaddr^0x80000000)>>12;
 314 #else
 315   u_int page=vaddr&~0xe0000000;
 316   if (page < 0x1000000)
 317     page &= ~0x0e00000; // RAM mirrors
 318   page>>=12;
 319 #endif
 320 #ifndef DISABLE_TLB
 321   if(page>262143&&tlb_LUT_r[vaddr>>12]) page=(tlb_LUT_r[vaddr>>12]^0x80000000)>>12;
 322 #endif
 323   if(page>2048) page=2048+(page&2047);
 324   return page;
 325 }
 326
 327 static u_int get_vpage(u_int vaddr)
 328 {
 329   u_int vpage=(vaddr^0x80000000)>>12;
 330 #ifndef DISABLE_TLB
 331   if(vpage>262143&&tlb_LUT_r[vaddr>>12]) vpage&=2047; // jump_dirty uses a hash of the virtual address instead
 332 #endif
 333   if(vpage>2048) vpage=2048+(vpage&2047);
 334   return vpage;
 335 }
 336
 337 // Get address from virtual address
 338 // This is called from the recompiled JR/JALR instructions
 339 void *get_addr(u_int vaddr)
 340 {
 341   u_int page=get_page(vaddr);
 342   u_int vpage=get_vpage(vaddr);
 343   struct ll_entry *head;
 344   //printf("TRACE: count=%d next=%d (get_addr %x,page %d)\n",Count,next_interupt,vaddr,page);
 345   head=jump_in[page];
 346   while(head!=NULL) {
 347     if(head->vaddr==vaddr&&head->reg32==0) {
 348   //printf("TRACE: count=%d next=%d (get_addr match %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
 349       int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
 350       ht_bin[3]=ht_bin[1];
 351       ht_bin[2]=ht_bin[0];
 352       ht_bin[1]=(int)head->addr;
 353       ht_bin[0]=vaddr;
 354       return head->addr;
 355     }
 356     head=head->next;
 357   }
 358   head=jump_dirty[vpage];
 359   while(head!=NULL) {
 360     if(head->vaddr==vaddr&&head->reg32==0) {
 361       //printf("TRACE: count=%d next=%d (get_addr match dirty %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
 362       // Don't restore blocks which are about to expire from the cache
 363       if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
 364       if(verify_dirty(head->addr)) {
 365         //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]);
 366         invalid_code[vaddr>>12]=0;
 367         memory_map[vaddr>>12]|=0x40000000;
 368         if(vpage<2048) {
 369 #ifndef DISABLE_TLB
 370           if(tlb_LUT_r[vaddr>>12]) {
 371             invalid_code[tlb_LUT_r[vaddr>>12]>>12]=0;
 372             memory_map[tlb_LUT_r[vaddr>>12]>>12]|=0x40000000;
 373           }
 374 #endif
 375           restore_candidate[vpage>>3]|=1<<(vpage&7);
 376         }
 377         else restore_candidate[page>>3]|=1<<(page&7);
 378         int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
 379         if(ht_bin[0]==vaddr) {
 380           ht_bin[1]=(int)head->addr; // Replace existing entry
 381         }
 382         else
 383         {
 384           ht_bin[3]=ht_bin[1];
 385           ht_bin[2]=ht_bin[0];
 386           ht_bin[1]=(int)head->addr;
 387           ht_bin[0]=vaddr;
 388         }
 389         return head->addr;
 390       }
 391     }
 392     head=head->next;
 393   }
 394   //printf("TRACE: count=%d next=%d (get_addr no-match %x)\n",Count,next_interupt,vaddr);
 395   int r=new_recompile_block(vaddr);
 396   if(r==0) return get_addr(vaddr);
 397   // Execute in unmapped page, generate pagefault execption
 398   Status|=2;
 399   Cause=(vaddr<<31)|0x8;
 400   EPC=(vaddr&1)?vaddr-5:vaddr;
 401   BadVAddr=(vaddr&~1);
 402   Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0);
 403   EntryHi=BadVAddr&0xFFFFE000;
 404   return get_addr_ht(0x80000000);
 405 }
 406 // Look up address in hash table first
 407 void *get_addr_ht(u_int vaddr)
 408 {
 409   //printf("TRACE: count=%d next=%d (get_addr_ht %x)\n",Count,next_interupt,vaddr);
 410   int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
 411   if(ht_bin[0]==vaddr) return (void *)ht_bin[1];
 412   if(ht_bin[2]==vaddr) return (void *)ht_bin[3];
 413   return get_addr(vaddr);
 414 }
 415
 416 void *get_addr_32(u_int vaddr,u_int flags)
 417 {
 418 #ifdef FORCE32
 419   return get_addr(vaddr);
 420 #else
 421   //printf("TRACE: count=%d next=%d (get_addr_32 %x,flags %x)\n",Count,next_interupt,vaddr,flags);
 422   int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
 423   if(ht_bin[0]==vaddr) return (void *)ht_bin[1];
 424   if(ht_bin[2]==vaddr) return (void *)ht_bin[3];
 425   u_int page=get_page(vaddr);
 426   u_int vpage=get_vpage(vaddr);
 427   struct ll_entry *head;
 428   head=jump_in[page];
 429   while(head!=NULL) {
 430     if(head->vaddr==vaddr&&(head->reg32&flags)==0) {
 431       //printf("TRACE: count=%d next=%d (get_addr_32 match %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
 432       if(head->reg32==0) {
 433         int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
 434         if(ht_bin[0]==-1) {
 435           ht_bin[1]=(int)head->addr;
 436           ht_bin[0]=vaddr;
 437         }else if(ht_bin[2]==-1) {
 438           ht_bin[3]=(int)head->addr;
 439           ht_bin[2]=vaddr;
 440         }
 441         //ht_bin[3]=ht_bin[1];
 442         //ht_bin[2]=ht_bin[0];
 443         //ht_bin[1]=(int)head->addr;
 444         //ht_bin[0]=vaddr;
 445       }
 446       return head->addr;
 447     }
 448     head=head->next;
 449   }
 450   head=jump_dirty[vpage];
 451   while(head!=NULL) {
 452     if(head->vaddr==vaddr&&(head->reg32&flags)==0) {
 453       //printf("TRACE: count=%d next=%d (get_addr_32 match dirty %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
 454       // Don't restore blocks which are about to expire from the cache
 455       if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
 456       if(verify_dirty(head->addr)) {
 457         //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]);
 458         invalid_code[vaddr>>12]=0;
 459         memory_map[vaddr>>12]|=0x40000000;
 460         if(vpage<2048) {
 461 #ifndef DISABLE_TLB
 462           if(tlb_LUT_r[vaddr>>12]) {
 463             invalid_code[tlb_LUT_r[vaddr>>12]>>12]=0;
 464             memory_map[tlb_LUT_r[vaddr>>12]>>12]|=0x40000000;
 465           }
 466 #endif
 467           restore_candidate[vpage>>3]|=1<<(vpage&7);
 468         }
 469         else restore_candidate[page>>3]|=1<<(page&7);
 470         if(head->reg32==0) {
 471           int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
 472           if(ht_bin[0]==-1) {
 473             ht_bin[1]=(int)head->addr;
 474             ht_bin[0]=vaddr;
 475           }else if(ht_bin[2]==-1) {
 476             ht_bin[3]=(int)head->addr;
 477             ht_bin[2]=vaddr;
 478           }
 479           //ht_bin[3]=ht_bin[1];
 480           //ht_bin[2]=ht_bin[0];
 481           //ht_bin[1]=(int)head->addr;
 482           //ht_bin[0]=vaddr;
 483         }
 484         return head->addr;
 485       }
 486     }
 487     head=head->next;
 488   }
 489   //printf("TRACE: count=%d next=%d (get_addr_32 no-match %x,flags %x)\n",Count,next_interupt,vaddr,flags);
 490   int r=new_recompile_block(vaddr);
 491   if(r==0) return get_addr(vaddr);
 492   // Execute in unmapped page, generate pagefault execption
 493   Status|=2;
 494   Cause=(vaddr<<31)|0x8;
 495   EPC=(vaddr&1)?vaddr-5:vaddr;
 496   BadVAddr=(vaddr&~1);
 497   Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0);
 498   EntryHi=BadVAddr&0xFFFFE000;
 499   return get_addr_ht(0x80000000);
 500 #endif
 501 }
 502
 503 void clear_all_regs(signed char regmap[])
 504 {
 505   int hr;
 506   for (hr=0;hr<HOST_REGS;hr++) regmap[hr]=-1;
 507 }
 508
 509 signed char get_reg(signed char regmap[],int r)
 510 {
 511   int hr;
 512   for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&&regmap[hr]==r) return hr;
 513   return -1;
 514 }
 515
 516 // Find a register that is available for two consecutive cycles
 517 signed char get_reg2(signed char regmap1[],signed char regmap2[],int r)
 518 {
 519   int hr;
 520   for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&&regmap1[hr]==r&&regmap2[hr]==r) return hr;
 521   return -1;
 522 }
 523
 524 int count_free_regs(signed char regmap[])
 525 {
 526   int count=0;
 527   int hr;
 528   for(hr=0;hr<HOST_REGS;hr++)
 529   {
 530     if(hr!=EXCLUDE_REG) {
 531       if(regmap[hr]<0) count++;
 532     }
 533   }
 534   return count;
 535 }
 536
 537 void dirty_reg(struct regstat *cur,signed char reg)
 538 {
 539   int hr;
 540   if(!reg) return;
 541   for (hr=0;hr<HOST_REGS;hr++) {
 542     if((cur->regmap[hr]&63)==reg) {
 543       cur->dirty|=1<<hr;
 544     }
 545   }
 546 }
 547
 548 // If we dirty the lower half of a 64 bit register which is now being
 549 // sign-extended, we need to dump the upper half.
 550 // Note: Do this only after completion of the instruction, because
 551 // some instructions may need to read the full 64-bit value even if
 552 // overwriting it (eg SLTI, DSRA32).
 553 static void flush_dirty_uppers(struct regstat *cur)
 554 {
 555   int hr,reg;
 556   for (hr=0;hr<HOST_REGS;hr++) {
 557     if((cur->dirty>>hr)&1) {
 558       reg=cur->regmap[hr];
 559       if(reg>=64)
 560         if((cur->is32>>(reg&63))&1) cur->regmap[hr]=-1;
 561     }
 562   }
 563 }
 564
 565 void set_const(struct regstat *cur,signed char reg,uint64_t value)
 566 {
 567   int hr;
 568   if(!reg) return;
 569   for (hr=0;hr<HOST_REGS;hr++) {
 570     if(cur->regmap[hr]==reg) {
 571       cur->isconst|=1<<hr;
 572       cur->constmap[hr]=value;
 573     }
 574     else if((cur->regmap[hr]^64)==reg) {
 575       cur->isconst|=1<<hr;
 576       cur->constmap[hr]=value>>32;
 577     }
 578   }
 579 }
 580
 581 void clear_const(struct regstat *cur,signed char reg)
 582 {
 583   int hr;
 584   if(!reg) return;
 585   for (hr=0;hr<HOST_REGS;hr++) {
 586     if((cur->regmap[hr]&63)==reg) {
 587       cur->isconst&=~(1<<hr);
 588     }
 589   }
 590 }
 591
 592 int is_const(struct regstat *cur,signed char reg)
 593 {
 594   int hr;
 595   if(!reg) return 1;
 596   for (hr=0;hr<HOST_REGS;hr++) {
 597     if((cur->regmap[hr]&63)==reg) {
 598       return (cur->isconst>>hr)&1;
 599     }
 600   }
 601   return 0;
 602 }
 603 uint64_t get_const(struct regstat *cur,signed char reg)
 604 {
 605   int hr;
 606   if(!reg) return 0;
 607   for (hr=0;hr<HOST_REGS;hr++) {
 608     if(cur->regmap[hr]==reg) {
 609       return cur->constmap[hr];
 610     }
 611   }
 612   printf("Unknown constant in r%d\n",reg);
 613   exit(1);
 614 }
 615
 616 // Least soon needed registers
 617 // Look at the next ten instructions and see which registers
 618 // will be used.  Try not to reallocate these.
 619 void lsn(u_char hsn[], int i, int *preferred_reg)
 620 {
 621   int j;
 622   int b=-1;
 623   for(j=0;j<9;j++)
 624   {
 625     if(i+j>=slen) {
 626       j=slen-i-1;
 627       break;
 628     }
 629     if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
 630     {
 631       // Don't go past an unconditonal jump
 632       j++;
 633       break;
 634     }
 635   }
 636   for(;j>=0;j--)
 637   {
 638     if(rs1[i+j]) hsn[rs1[i+j]]=j;
 639     if(rs2[i+j]) hsn[rs2[i+j]]=j;
 640     if(rt1[i+j]) hsn[rt1[i+j]]=j;
 641     if(rt2[i+j]) hsn[rt2[i+j]]=j;
 642     if(itype[i+j]==STORE || itype[i+j]==STORELR) {
 643       // Stores can allocate zero
 644       hsn[rs1[i+j]]=j;
 645       hsn[rs2[i+j]]=j;
 646     }
 647     // On some architectures stores need invc_ptr
 648     #if defined(HOST_IMM8)
 649     if(itype[i+j]==STORE || itype[i+j]==STORELR || (opcode[i+j]&0x3b)==0x39 || (opcode[i+j]&0x3b)==0x3a) {
 650       hsn[INVCP]=j;
 651     }
 652     #endif
 653     if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP))
 654     {
 655       hsn[CCREG]=j;
 656       b=j;
 657     }
 658   }
 659   if(b>=0)
 660   {
 661     if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
 662     {
 663       // Follow first branch
 664       int t=(ba[i+b]-start)>>2;
 665       j=7-b;if(t+j>=slen) j=slen-t-1;
 666       for(;j>=0;j--)
 667       {
 668         if(rs1[t+j]) if(hsn[rs1[t+j]]>j+b+2) hsn[rs1[t+j]]=j+b+2;
 669         if(rs2[t+j]) if(hsn[rs2[t+j]]>j+b+2) hsn[rs2[t+j]]=j+b+2;
 670         //if(rt1[t+j]) if(hsn[rt1[t+j]]>j+b+2) hsn[rt1[t+j]]=j+b+2;
 671         //if(rt2[t+j]) if(hsn[rt2[t+j]]>j+b+2) hsn[rt2[t+j]]=j+b+2;
 672       }
 673     }
 674     // TODO: preferred register based on backward branch
 675   }
 676   // Delay slot should preferably not overwrite branch conditions or cycle count
 677   if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)) {
 678     if(rs1[i-1]) if(hsn[rs1[i-1]]>1) hsn[rs1[i-1]]=1;
 679     if(rs2[i-1]) if(hsn[rs2[i-1]]>1) hsn[rs2[i-1]]=1;
 680     hsn[CCREG]=1;
 681     // ...or hash tables
 682     hsn[RHASH]=1;
 683     hsn[RHTBL]=1;
 684   }
 685   // Coprocessor load/store needs FTEMP, even if not declared
 686   if(itype[i]==C1LS||itype[i]==C2LS) {
 687     hsn[FTEMP]=0;
 688   }
 689   // Load L/R also uses FTEMP as a temporary register
 690   if(itype[i]==LOADLR) {
 691     hsn[FTEMP]=0;
 692   }
 693   // Also SWL/SWR/SDL/SDR
 694   if(opcode[i]==0x2a||opcode[i]==0x2e||opcode[i]==0x2c||opcode[i]==0x2d) {
 695     hsn[FTEMP]=0;
 696   }
 697   // Don't remove the TLB registers either
 698   if(itype[i]==LOAD || itype[i]==LOADLR || itype[i]==STORE || itype[i]==STORELR || itype[i]==C1LS || itype[i]==C2LS) {
 699     hsn[TLREG]=0;
 700   }
 701   // Don't remove the miniht registers
 702   if(itype[i]==UJUMP||itype[i]==RJUMP)
 703   {
 704     hsn[RHASH]=0;
 705     hsn[RHTBL]=0;
 706   }
 707 }
 708
 709 // We only want to allocate registers if we're going to use them again soon
 710 int needed_again(int r, int i)
 711 {
 712   int j;
 713   int b=-1;
 714   int rn=10;
 715   int hr;
 716   u_char hsn[MAXREG+1];
 717   int preferred_reg;
 718
 719   memset(hsn,10,sizeof(hsn));
 720   lsn(hsn,i,&preferred_reg);
 721
 722   if(i>0&&(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000))
 723   {
 724     if(ba[i-1]<start || ba[i-1]>start+slen*4-4)
 725       return 0; // Don't need any registers if exiting the block
 726   }
 727   for(j=0;j<9;j++)
 728   {
 729     if(i+j>=slen) {
 730       j=slen-i-1;
 731       break;
 732     }
 733     if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
 734     {
 735       // Don't go past an unconditonal jump
 736       j++;
 737       break;
 738     }
 739     if(itype[i+j]==SYSCALL||itype[i+j]==HLECALL||itype[i+j]==INTCALL||((source[i+j]&0xfc00003f)==0x0d))
 740     {
 741       break;
 742     }
 743   }
 744   for(;j>=1;j--)
 745   {
 746     if(rs1[i+j]==r) rn=j;
 747     if(rs2[i+j]==r) rn=j;
 748     if((unneeded_reg[i+j]>>r)&1) rn=10;
 749     if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP))
 750     {
 751       b=j;
 752     }
 753   }
 754   /*
 755   if(b>=0)
 756   {
 757     if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
 758     {
 759       // Follow first branch
 760       int o=rn;
 761       int t=(ba[i+b]-start)>>2;
 762       j=7-b;if(t+j>=slen) j=slen-t-1;
 763       for(;j>=0;j--)
 764       {
 765         if(!((unneeded_reg[t+j]>>r)&1)) {
 766           if(rs1[t+j]==r) if(rn>j+b+2) rn=j+b+2;
 767           if(rs2[t+j]==r) if(rn>j+b+2) rn=j+b+2;
 768         }
 769         else rn=o;
 770       }
 771     }
 772   }*/
 773   for(hr=0;hr<HOST_REGS;hr++) {
 774     if(hr!=EXCLUDE_REG) {
 775       if(rn<hsn[hr]) return 1;
 776     }
 777   }
 778   return 0;
 779 }
 780
 781 // Try to match register allocations at the end of a loop with those
 782 // at the beginning
 783 int loop_reg(int i, int r, int hr)
 784 {
 785   int j,k;
 786   for(j=0;j<9;j++)
 787   {
 788     if(i+j>=slen) {
 789       j=slen-i-1;
 790       break;
 791     }
 792     if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
 793     {
 794       // Don't go past an unconditonal jump
 795       j++;
 796       break;
 797     }
 798   }
 799   k=0;
 800   if(i>0){
 801     if(itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)
 802       k--;
 803   }
 804   for(;k<j;k++)
 805   {
 806     if(r<64&&((unneeded_reg[i+k]>>r)&1)) return hr;
 807     if(r>64&&((unneeded_reg_upper[i+k]>>r)&1)) return hr;
 808     if(i+k>=0&&(itype[i+k]==UJUMP||itype[i+k]==CJUMP||itype[i+k]==SJUMP||itype[i+k]==FJUMP))
 809     {
 810       if(ba[i+k]>=start && ba[i+k]<(start+i*4))
 811       {
 812         int t=(ba[i+k]-start)>>2;
 813         int reg=get_reg(regs[t].regmap_entry,r);
 814         if(reg>=0) return reg;
 815         //reg=get_reg(regs[t+1].regmap_entry,r);
 816         //if(reg>=0) return reg;
 817       }
 818     }
 819   }
 820   return hr;
 821 }
 822
 823
 824 // Allocate every register, preserving source/target regs
 825 void alloc_all(struct regstat *cur,int i)
 826 {
 827   int hr;
 828
 829   for(hr=0;hr<HOST_REGS;hr++) {
 830     if(hr!=EXCLUDE_REG) {
 831       if(((cur->regmap[hr]&63)!=rs1[i])&&((cur->regmap[hr]&63)!=rs2[i])&&
 832          ((cur->regmap[hr]&63)!=rt1[i])&&((cur->regmap[hr]&63)!=rt2[i]))
 833       {
 834         cur->regmap[hr]=-1;
 835         cur->dirty&=~(1<<hr);
 836       }
 837       // Don't need zeros
 838       if((cur->regmap[hr]&63)==0)
 839       {
 840         cur->regmap[hr]=-1;
 841         cur->dirty&=~(1<<hr);
 842       }
 843     }
 844   }
 845 }
 846
 847
 848 void div64(int64_t dividend,int64_t divisor)
 849 {
 850   lo=dividend/divisor;
 851   hi=dividend%divisor;
 852   //printf("TRACE: ddiv %8x%8x %8x%8x\n" ,(int)reg[HIREG],(int)(reg[HIREG]>>32)
 853   //                                     ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
 854 }
 855 void divu64(uint64_t dividend,uint64_t divisor)
 856 {
 857   lo=dividend/divisor;
 858   hi=dividend%divisor;
 859   //printf("TRACE: ddivu %8x%8x %8x%8x\n",(int)reg[HIREG],(int)(reg[HIREG]>>32)
 860   //                                     ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
 861 }
 862
 863 void mult64(uint64_t m1,uint64_t m2)
 864 {
 865    unsigned long long int op1, op2, op3, op4;
 866    unsigned long long int result1, result2, result3, result4;
 867    unsigned long long int temp1, temp2, temp3, temp4;
 868    int sign = 0;
 869
 870    if (m1 < 0)
 871      {
 872     op2 = -m1;
 873     sign = 1 - sign;
 874      }
 875    else op2 = m1;
 876    if (m2 < 0)
 877      {
 878     op4 = -m2;
 879     sign = 1 - sign;
 880      }
 881    else op4 = m2;
 882
 883    op1 = op2 & 0xFFFFFFFF;
 884    op2 = (op2 >> 32) & 0xFFFFFFFF;
 885    op3 = op4 & 0xFFFFFFFF;
 886    op4 = (op4 >> 32) & 0xFFFFFFFF;
 887
 888    temp1 = op1 * op3;
 889    temp2 = (temp1 >> 32) + op1 * op4;
 890    temp3 = op2 * op3;
 891    temp4 = (temp3 >> 32) + op2 * op4;
 892
 893    result1 = temp1 & 0xFFFFFFFF;
 894    result2 = temp2 + (temp3 & 0xFFFFFFFF);
 895    result3 = (result2 >> 32) + temp4;
 896    result4 = (result3 >> 32);
 897
 898    lo = result1 | (result2 << 32);
 899    hi = (result3 & 0xFFFFFFFF) | (result4 << 32);
 900    if (sign)
 901      {
 902     hi = ~hi;
 903     if (!lo) hi++;
 904     else lo = ~lo + 1;
 905      }
 906 }
 907
 908 void multu64(uint64_t m1,uint64_t m2)
 909 {
 910    unsigned long long int op1, op2, op3, op4;
 911    unsigned long long int result1, result2, result3, result4;
 912    unsigned long long int temp1, temp2, temp3, temp4;
 913
 914    op1 = m1 & 0xFFFFFFFF;
 915    op2 = (m1 >> 32) & 0xFFFFFFFF;
 916    op3 = m2 & 0xFFFFFFFF;
 917    op4 = (m2 >> 32) & 0xFFFFFFFF;
 918
 919    temp1 = op1 * op3;
 920    temp2 = (temp1 >> 32) + op1 * op4;
 921    temp3 = op2 * op3;
 922    temp4 = (temp3 >> 32) + op2 * op4;
 923
 924    result1 = temp1 & 0xFFFFFFFF;
 925    result2 = temp2 + (temp3 & 0xFFFFFFFF);
 926    result3 = (result2 >> 32) + temp4;
 927    result4 = (result3 >> 32);
 928
 929    lo = result1 | (result2 << 32);
 930    hi = (result3 & 0xFFFFFFFF) | (result4 << 32);
 931
 932   //printf("TRACE: dmultu %8x%8x %8x%8x\n",(int)reg[HIREG],(int)(reg[HIREG]>>32)
 933   //                                      ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
 934 }
 935
 936 uint64_t ldl_merge(uint64_t original,uint64_t loaded,u_int bits)
 937 {
 938   if(bits) {
 939     original<<=64-bits;
 940     original>>=64-bits;
 941     loaded<<=bits;
 942     original|=loaded;
 943   }
 944   else original=loaded;
 945   return original;
 946 }
 947 uint64_t ldr_merge(uint64_t original,uint64_t loaded,u_int bits)
 948 {
 949   if(bits^56) {
 950     original>>=64-(bits^56);
 951     original<<=64-(bits^56);
 952     loaded>>=bits^56;
 953     original|=loaded;
 954   }
 955   else original=loaded;
 956   return original;
 957 }
 958
 959 #ifdef __i386__
 960 #include "assem_x86.c"
 961 #endif
 962 #ifdef __x86_64__
 963 #include "assem_x64.c"
 964 #endif
 965 #ifdef __arm__
 966 #include "assem_arm.c"
 967 #endif
 968
 969 // Add virtual address mapping to linked list
 970 void ll_add(struct ll_entry **head,int vaddr,void *addr)
 971 {
 972   struct ll_entry *new_entry;
 973   new_entry=malloc(sizeof(struct ll_entry));
 974   assert(new_entry!=NULL);
 975   new_entry->vaddr=vaddr;
 976   new_entry->reg32=0;
 977   new_entry->addr=addr;
 978   new_entry->next=*head;
 979   *head=new_entry;
 980 }
 981
 982 // Add virtual address mapping for 32-bit compiled block
 983 void ll_add_32(struct ll_entry **head,int vaddr,u_int reg32,void *addr)
 984 {
 985   ll_add(head,vaddr,addr);
 986 #ifndef FORCE32
 987   (*head)->reg32=reg32;
 988 #endif
 989 }
 990
 991 // Check if an address is already compiled
 992 // but don't return addresses which are about to expire from the cache
 993 void *check_addr(u_int vaddr)
 994 {
 995   u_int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
 996   if(ht_bin[0]==vaddr) {
 997     if(((ht_bin[1]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
 998       if(isclean(ht_bin[1])) return (void *)ht_bin[1];
 999   }
1000   if(ht_bin[2]==vaddr) {
1001     if(((ht_bin[3]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
1002       if(isclean(ht_bin[3])) return (void *)ht_bin[3];
1003   }
1004   u_int page=get_page(vaddr);
1005   struct ll_entry *head;
1006   head=jump_in[page];
1007   while(head!=NULL) {
1008     if(head->vaddr==vaddr&&head->reg32==0) {
1009       if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1010         // Update existing entry with current address
1011         if(ht_bin[0]==vaddr) {
1012           ht_bin[1]=(int)head->addr;
1013           return head->addr;
1014         }
1015         if(ht_bin[2]==vaddr) {
1016           ht_bin[3]=(int)head->addr;
1017           return head->addr;
1018         }
1019         // Insert into hash table with low priority.
1020         // Don't evict existing entries, as they are probably
1021         // addresses that are being accessed frequently.
1022         if(ht_bin[0]==-1) {
1023           ht_bin[1]=(int)head->addr;
1024           ht_bin[0]=vaddr;
1025         }else if(ht_bin[2]==-1) {
1026           ht_bin[3]=(int)head->addr;
1027           ht_bin[2]=vaddr;
1028         }
1029         return head->addr;
1030       }
1031     }
1032     head=head->next;
1033   }
1034   return 0;
1035 }
1036
1037 void remove_hash(int vaddr)
1038 {
1039   //printf("remove hash: %x\n",vaddr);
1040   int *ht_bin=hash_table[(((vaddr)>>16)^vaddr)&0xFFFF];
1041   if(ht_bin[2]==vaddr) {
1042     ht_bin[2]=ht_bin[3]=-1;
1043   }
1044   if(ht_bin[0]==vaddr) {
1045     ht_bin[0]=ht_bin[2];
1046     ht_bin[1]=ht_bin[3];
1047     ht_bin[2]=ht_bin[3]=-1;
1048   }
1049 }
1050
1051 void ll_remove_matching_addrs(struct ll_entry **head,int addr,int shift)
1052 {
1053   struct ll_entry *next;
1054   while(*head) {
1055     if(((u_int)((*head)->addr)>>shift)==(addr>>shift) ||
1056        ((u_int)((*head)->addr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift))
1057     {
1058       inv_debug("EXP: Remove pointer to %x (%x)\n",(int)(*head)->addr,(*head)->vaddr);
1059       remove_hash((*head)->vaddr);
1060       next=(*head)->next;
1061       free(*head);
1062       *head=next;
1063     }
1064     else
1065     {
1066       head=&((*head)->next);
1067     }
1068   }
1069 }
1070
1071 // Remove all entries from linked list
1072 void ll_clear(struct ll_entry **head)
1073 {
1074   struct ll_entry *cur;
1075   struct ll_entry *next;
1076   if(cur=*head) {
1077     *head=0;
1078     while(cur) {
1079       next=cur->next;
1080       free(cur);
1081       cur=next;
1082     }
1083   }
1084 }
1085
1086 // Dereference the pointers and remove if it matches
1087 void ll_kill_pointers(struct ll_entry *head,int addr,int shift)
1088 {
1089   while(head) {
1090     int ptr=get_pointer(head->addr);
1091     inv_debug("EXP: Lookup pointer to %x at %x (%x)\n",(int)ptr,(int)head->addr,head->vaddr);
1092     if(((ptr>>shift)==(addr>>shift)) ||
1093        (((ptr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift)))
1094     {
1095       inv_debug("EXP: Kill pointer at %x (%x)\n",(int)head->addr,head->vaddr);
1096       u_int host_addr=(u_int)kill_pointer(head->addr);
1097       #ifdef __arm__
1098         needs_clear_cache[(host_addr-(u_int)BASE_ADDR)>>17]|=1<<(((host_addr-(u_int)BASE_ADDR)>>12)&31);
1099       #endif
1100     }
1101     head=head->next;
1102   }
1103 }
1104
1105 // This is called when we write to a compiled block (see do_invstub)
1106 void invalidate_page(u_int page)
1107 {
1108   struct ll_entry *head;
1109   struct ll_entry *next;
1110   head=jump_in[page];
1111   jump_in[page]=0;
1112   while(head!=NULL) {
1113     inv_debug("INVALIDATE: %x\n",head->vaddr);
1114     remove_hash(head->vaddr);
1115     next=head->next;
1116     free(head);
1117     head=next;
1118   }
1119   head=jump_out[page];
1120   jump_out[page]=0;
1121   while(head!=NULL) {
1122     inv_debug("INVALIDATE: kill pointer to %x (%x)\n",head->vaddr,(int)head->addr);
1123     u_int host_addr=(u_int)kill_pointer(head->addr);
1124     #ifdef __arm__
1125       needs_clear_cache[(host_addr-(u_int)BASE_ADDR)>>17]|=1<<(((host_addr-(u_int)BASE_ADDR)>>12)&31);
1126     #endif
1127     next=head->next;
1128     free(head);
1129     head=next;
1130   }
1131 }
1132 void invalidate_block(u_int block)
1133 {
1134   u_int page=get_page(block<<12);
1135   u_int vpage=get_vpage(block<<12);
1136   inv_debug("INVALIDATE: %x (%d)\n",block<<12,page);
1137   //inv_debug("invalid_code[block]=%d\n",invalid_code[block]);
1138   u_int first,last;
1139   first=last=page;
1140   struct ll_entry *head;
1141   head=jump_dirty[vpage];
1142   //printf("page=%d vpage=%d\n",page,vpage);
1143   while(head!=NULL) {
1144     u_int start,end;
1145     if(vpage>2047||(head->vaddr>>12)==block) { // Ignore vaddr hash collision
1146       get_bounds((int)head->addr,&start,&end);
1147       //printf("start: %x end: %x\n",start,end);
1148       if(page<2048&&start>=0x80000000&&end<0x80000000+RAM_SIZE) {
1149         if(((start-(u_int)rdram)>>12)<=page&&((end-1-(u_int)rdram)>>12)>=page) {
1150           if((((start-(u_int)rdram)>>12)&2047)<first) first=((start-(u_int)rdram)>>12)&2047;
1151           if((((end-1-(u_int)rdram)>>12)&2047)>last) last=((end-1-(u_int)rdram)>>12)&2047;
1152         }
1153       }
1154 #ifndef DISABLE_TLB
1155       if(page<2048&&(signed int)start>=(signed int)0xC0000000&&(signed int)end>=(signed int)0xC0000000) {
1156         if(((start+memory_map[start>>12]-(u_int)rdram)>>12)<=page&&((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)>=page) {
1157           if((((start+memory_map[start>>12]-(u_int)rdram)>>12)&2047)<first) first=((start+memory_map[start>>12]-(u_int)rdram)>>12)&2047;
1158           if((((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)&2047)>last) last=((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)&2047;
1159         }
1160       }
1161 #endif
1162     }
1163     head=head->next;
1164   }
1165   //printf("first=%d last=%d\n",first,last);
1166   invalidate_page(page);
1167   assert(first+5>page); // NB: this assumes MAXBLOCK<=4096 (4 pages)
1168   assert(last<page+5);
1169   // Invalidate the adjacent pages if a block crosses a 4K boundary
1170   while(first<page) {
1171     invalidate_page(first);
1172     first++;
1173   }
1174   for(first=page+1;first<last;first++) {
1175     invalidate_page(first);
1176   }
1177   #ifdef __arm__
1178     do_clear_cache();
1179   #endif
1180
1181   // Don't trap writes
1182   invalid_code[block]=1;
1183 #ifndef DISABLE_TLB
1184   // If there is a valid TLB entry for this page, remove write protect
1185   if(tlb_LUT_w[block]) {
1186     assert(tlb_LUT_r[block]==tlb_LUT_w[block]);
1187     // CHECK: Is this right?
1188     memory_map[block]=((tlb_LUT_w[block]&0xFFFFF000)-(block<<12)+(unsigned int)rdram-0x80000000)>>2;
1189     u_int real_block=tlb_LUT_w[block]>>12;
1190     invalid_code[real_block]=1;
1191     if(real_block>=0x80000&&real_block<0x80800) memory_map[real_block]=((u_int)rdram-0x80000000)>>2;
1192   }
1193   else if(block>=0x80000&&block<0x80800) memory_map[block]=((u_int)rdram-0x80000000)>>2;
1194 #endif
1195
1196   #ifdef USE_MINI_HT
1197   memset(mini_ht,-1,sizeof(mini_ht));
1198   #endif
1199 }
1200 void invalidate_addr(u_int addr)
1201 {
1202   invalidate_block(addr>>12);
1203 }
1204 // This is called when loading a save state.
1205 // Anything could have changed, so invalidate everything.
1206 void invalidate_all_pages()
1207 {
1208   u_int page,n;
1209   for(page=0;page<4096;page++)
1210     invalidate_page(page);
1211   for(page=0;page<1048576;page++)
1212     if(!invalid_code[page]) {
1213       restore_candidate[(page&2047)>>3]|=1<<(page&7);
1214       restore_candidate[((page&2047)>>3)+256]|=1<<(page&7);
1215     }
1216   #ifdef __arm__
1217   __clear_cache((void *)BASE_ADDR,(void *)BASE_ADDR+(1<<TARGET_SIZE_2));
1218   #endif
1219   #ifdef USE_MINI_HT
1220   memset(mini_ht,-1,sizeof(mini_ht));
1221   #endif
1222   #ifndef DISABLE_TLB
1223   // TLB
1224   for(page=0;page<0x100000;page++) {
1225     if(tlb_LUT_r[page]) {
1226       memory_map[page]=((tlb_LUT_r[page]&0xFFFFF000)-(page<<12)+(unsigned int)rdram-0x80000000)>>2;
1227       if(!tlb_LUT_w[page]||!invalid_code[page])
1228         memory_map[page]|=0x40000000; // Write protect
1229     }
1230     else memory_map[page]=-1;
1231     if(page==0x80000) page=0xC0000;
1232   }
1233   tlb_hacks();
1234   #endif
1235 }
1236
1237 // Add an entry to jump_out after making a link
1238 void add_link(u_int vaddr,void *src)
1239 {
1240   u_int page=get_page(vaddr);
1241   inv_debug("add_link: %x -> %x (%d)\n",(int)src,vaddr,page);
1242   ll_add(jump_out+page,vaddr,src);
1243   //int ptr=get_pointer(src);
1244   //inv_debug("add_link: Pointer is to %x\n",(int)ptr);
1245 }
1246
1247 // If a code block was found to be unmodified (bit was set in
1248 // restore_candidate) and it remains unmodified (bit is clear
1249 // in invalid_code) then move the entries for that 4K page from
1250 // the dirty list to the clean list.
1251 void clean_blocks(u_int page)
1252 {
1253   struct ll_entry *head;
1254   inv_debug("INV: clean_blocks page=%d\n",page);
1255   head=jump_dirty[page];
1256   while(head!=NULL) {
1257     if(!invalid_code[head->vaddr>>12]) {
1258       // Don't restore blocks which are about to expire from the cache
1259       if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1260         u_int start,end;
1261         if(verify_dirty((int)head->addr)) {
1262           //printf("Possibly Restore %x (%x)\n",head->vaddr, (int)head->addr);
1263           u_int i;
1264           u_int inv=0;
1265           get_bounds((int)head->addr,&start,&end);
1266           if(start-(u_int)rdram<RAM_SIZE) {
1267             for(i=(start-(u_int)rdram+0x80000000)>>12;i<=(end-1-(u_int)rdram+0x80000000)>>12;i++) {
1268               inv|=invalid_code[i];
1269             }
1270           }
1271           if((signed int)head->vaddr>=(signed int)0xC0000000) {
1272             u_int addr = (head->vaddr+(memory_map[head->vaddr>>12]<<2));
1273             //printf("addr=%x start=%x end=%x\n",addr,start,end);
1274             if(addr<start||addr>=end) inv=1;
1275           }
1276           else if((signed int)head->vaddr>=(signed int)0x80000000+RAM_SIZE) {
1277             inv=1;
1278           }
1279           if(!inv) {
1280             void * clean_addr=(void *)get_clean_addr((int)head->addr);
1281             if((((u_int)clean_addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1282               u_int ppage=page;
1283 #ifndef DISABLE_TLB
1284               if(page<2048&&tlb_LUT_r[head->vaddr>>12]) ppage=(tlb_LUT_r[head->vaddr>>12]^0x80000000)>>12;
1285 #endif
1286               inv_debug("INV: Restored %x (%x/%x)\n",head->vaddr, (int)head->addr, (int)clean_addr);
1287               //printf("page=%x, addr=%x\n",page,head->vaddr);
1288               //assert(head->vaddr>>12==(page|0x80000));
1289               ll_add_32(jump_in+ppage,head->vaddr,head->reg32,clean_addr);
1290               int *ht_bin=hash_table[((head->vaddr>>16)^head->vaddr)&0xFFFF];
1291               if(!head->reg32) {
1292                 if(ht_bin[0]==head->vaddr) {
1293                   ht_bin[1]=(int)clean_addr; // Replace existing entry
1294                 }
1295                 if(ht_bin[2]==head->vaddr) {
1296                   ht_bin[3]=(int)clean_addr; // Replace existing entry
1297                 }
1298               }
1299             }
1300           }
1301         }
1302       }
1303     }
1304     head=head->next;
1305   }
1306 }
1307
1308
1309 void mov_alloc(struct regstat *current,int i)
1310 {
1311   // Note: Don't need to actually alloc the source registers
1312   if((~current->is32>>rs1[i])&1) {
1313     //alloc_reg64(current,i,rs1[i]);
1314     alloc_reg64(current,i,rt1[i]);
1315     current->is32&=~(1LL<<rt1[i]);
1316   } else {
1317     //alloc_reg(current,i,rs1[i]);
1318     alloc_reg(current,i,rt1[i]);
1319     current->is32|=(1LL<<rt1[i]);
1320   }
1321   clear_const(current,rs1[i]);
1322   clear_const(current,rt1[i]);
1323   dirty_reg(current,rt1[i]);
1324 }
1325
1326 void shiftimm_alloc(struct regstat *current,int i)
1327 {
1328   clear_const(current,rs1[i]);
1329   clear_const(current,rt1[i]);
1330   if(opcode2[i]<=0x3) // SLL/SRL/SRA
1331   {
1332     if(rt1[i]) {
1333       if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1334       else lt1[i]=rs1[i];
1335       alloc_reg(current,i,rt1[i]);
1336       current->is32|=1LL<<rt1[i];
1337       dirty_reg(current,rt1[i]);
1338     }
1339   }
1340   if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA
1341   {
1342     if(rt1[i]) {
1343       if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1344       alloc_reg64(current,i,rt1[i]);
1345       current->is32&=~(1LL<<rt1[i]);
1346       dirty_reg(current,rt1[i]);
1347     }
1348   }
1349   if(opcode2[i]==0x3c) // DSLL32
1350   {
1351     if(rt1[i]) {
1352       if(rs1[i]) alloc_reg(current,i,rs1[i]);
1353       alloc_reg64(current,i,rt1[i]);
1354       current->is32&=~(1LL<<rt1[i]);
1355       dirty_reg(current,rt1[i]);
1356     }
1357   }
1358   if(opcode2[i]==0x3e) // DSRL32
1359   {
1360     if(rt1[i]) {
1361       alloc_reg64(current,i,rs1[i]);
1362       if(imm[i]==32) {
1363         alloc_reg64(current,i,rt1[i]);
1364         current->is32&=~(1LL<<rt1[i]);
1365       } else {
1366         alloc_reg(current,i,rt1[i]);
1367         current->is32|=1LL<<rt1[i];
1368       }
1369       dirty_reg(current,rt1[i]);
1370     }
1371   }
1372   if(opcode2[i]==0x3f) // DSRA32
1373   {
1374     if(rt1[i]) {
1375       alloc_reg64(current,i,rs1[i]);
1376       alloc_reg(current,i,rt1[i]);
1377       current->is32|=1LL<<rt1[i];
1378       dirty_reg(current,rt1[i]);
1379     }
1380   }
1381 }
1382
1383 void shift_alloc(struct regstat *current,int i)
1384 {
1385   if(rt1[i]) {
1386     if(opcode2[i]<=0x07) // SLLV/SRLV/SRAV
1387     {
1388       if(rs1[i]) alloc_reg(current,i,rs1[i]);
1389       if(rs2[i]) alloc_reg(current,i,rs2[i]);
1390       alloc_reg(current,i,rt1[i]);
1391       if(rt1[i]==rs2[i]) {
1392         alloc_reg_temp(current,i,-1);
1393         minimum_free_regs[i]=1;
1394       }
1395       current->is32|=1LL<<rt1[i];
1396     } else { // DSLLV/DSRLV/DSRAV
1397       if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1398       if(rs2[i]) alloc_reg(current,i,rs2[i]);
1399       alloc_reg64(current,i,rt1[i]);
1400       current->is32&=~(1LL<<rt1[i]);
1401       if(opcode2[i]==0x16||opcode2[i]==0x17) // DSRLV and DSRAV need a temporary register
1402       {
1403         alloc_reg_temp(current,i,-1);
1404         minimum_free_regs[i]=1;
1405       }
1406     }
1407     clear_const(current,rs1[i]);
1408     clear_const(current,rs2[i]);
1409     clear_const(current,rt1[i]);
1410     dirty_reg(current,rt1[i]);
1411   }
1412 }
1413
1414 void alu_alloc(struct regstat *current,int i)
1415 {
1416   if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
1417     if(rt1[i]) {
1418       if(rs1[i]&&rs2[i]) {
1419         alloc_reg(current,i,rs1[i]);
1420         alloc_reg(current,i,rs2[i]);
1421       }
1422       else {
1423         if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1424         if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]);
1425       }
1426       alloc_reg(current,i,rt1[i]);
1427     }
1428     current->is32|=1LL<<rt1[i];
1429   }
1430   if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU
1431     if(rt1[i]) {
1432       if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1433       {
1434         alloc_reg64(current,i,rs1[i]);
1435         alloc_reg64(current,i,rs2[i]);
1436         alloc_reg(current,i,rt1[i]);
1437       } else {
1438         alloc_reg(current,i,rs1[i]);
1439         alloc_reg(current,i,rs2[i]);
1440         alloc_reg(current,i,rt1[i]);
1441       }
1442     }
1443     current->is32|=1LL<<rt1[i];
1444   }
1445   if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR
1446     if(rt1[i]) {
1447       if(rs1[i]&&rs2[i]) {
1448         alloc_reg(current,i,rs1[i]);
1449         alloc_reg(current,i,rs2[i]);
1450       }
1451       else
1452       {
1453         if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1454         if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]);
1455       }
1456       alloc_reg(current,i,rt1[i]);
1457       if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1458       {
1459         if(!((current->uu>>rt1[i])&1)) {
1460           alloc_reg64(current,i,rt1[i]);
1461         }
1462         if(get_reg(current->regmap,rt1[i]|64)>=0) {
1463           if(rs1[i]&&rs2[i]) {
1464             alloc_reg64(current,i,rs1[i]);
1465             alloc_reg64(current,i,rs2[i]);
1466           }
1467           else
1468           {
1469             // Is is really worth it to keep 64-bit values in registers?
1470             #ifdef NATIVE_64BIT
1471             if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]);
1472             if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg64(current,i,rs2[i]);
1473             #endif
1474           }
1475         }
1476         current->is32&=~(1LL<<rt1[i]);
1477       } else {
1478         current->is32|=1LL<<rt1[i];
1479       }
1480     }
1481   }
1482   if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU
1483     if(rt1[i]) {
1484       if(rs1[i]&&rs2[i]) {
1485         if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1486           alloc_reg64(current,i,rs1[i]);
1487           alloc_reg64(current,i,rs2[i]);
1488           alloc_reg64(current,i,rt1[i]);
1489         } else {
1490           alloc_reg(current,i,rs1[i]);
1491           alloc_reg(current,i,rs2[i]);
1492           alloc_reg(current,i,rt1[i]);
1493         }
1494       }
1495       else {
1496         alloc_reg(current,i,rt1[i]);
1497         if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1498           // DADD used as move, or zeroing
1499           // If we have a 64-bit source, then make the target 64 bits too
1500           if(rs1[i]&&!((current->is32>>rs1[i])&1)) {
1501             if(get_reg(current->regmap,rs1[i])>=0) alloc_reg64(current,i,rs1[i]);
1502             alloc_reg64(current,i,rt1[i]);
1503           } else if(rs2[i]&&!((current->is32>>rs2[i])&1)) {
1504             if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]);
1505             alloc_reg64(current,i,rt1[i]);
1506           }
1507           if(opcode2[i]>=0x2e&&rs2[i]) {
1508             // DSUB used as negation - 64-bit result
1509             // If we have a 32-bit register, extend it to 64 bits
1510             if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]);
1511             alloc_reg64(current,i,rt1[i]);
1512           }
1513         }
1514       }
1515       if(rs1[i]&&rs2[i]) {
1516         current->is32&=~(1LL<<rt1[i]);
1517       } else if(rs1[i]) {
1518         current->is32&=~(1LL<<rt1[i]);
1519         if((current->is32>>rs1[i])&1)
1520           current->is32|=1LL<<rt1[i];
1521       } else if(rs2[i]) {
1522         current->is32&=~(1LL<<rt1[i]);
1523         if((current->is32>>rs2[i])&1)
1524           current->is32|=1LL<<rt1[i];
1525       } else {
1526         current->is32|=1LL<<rt1[i];
1527       }
1528     }
1529   }
1530   clear_const(current,rs1[i]);
1531   clear_const(current,rs2[i]);
1532   clear_const(current,rt1[i]);
1533   dirty_reg(current,rt1[i]);
1534 }
1535
1536 void imm16_alloc(struct regstat *current,int i)
1537 {
1538   if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1539   else lt1[i]=rs1[i];
1540   if(rt1[i]) alloc_reg(current,i,rt1[i]);
1541   if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU
1542     current->is32&=~(1LL<<rt1[i]);
1543     if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1544       // TODO: Could preserve the 32-bit flag if the immediate is zero
1545       alloc_reg64(current,i,rt1[i]);
1546       alloc_reg64(current,i,rs1[i]);
1547     }
1548     clear_const(current,rs1[i]);
1549     clear_const(current,rt1[i]);
1550   }
1551   else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU
1552     if((~current->is32>>rs1[i])&1) alloc_reg64(current,i,rs1[i]);
1553     current->is32|=1LL<<rt1[i];
1554     clear_const(current,rs1[i]);
1555     clear_const(current,rt1[i]);
1556   }
1557   else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI
1558     if(((~current->is32>>rs1[i])&1)&&opcode[i]>0x0c) {
1559       if(rs1[i]!=rt1[i]) {
1560         if(needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]);
1561         alloc_reg64(current,i,rt1[i]);
1562         current->is32&=~(1LL<<rt1[i]);
1563       }
1564     }
1565     else current->is32|=1LL<<rt1[i]; // ANDI clears upper bits
1566     if(is_const(current,rs1[i])) {
1567       int v=get_const(current,rs1[i]);
1568       if(opcode[i]==0x0c) set_const(current,rt1[i],v&imm[i]);
1569       if(opcode[i]==0x0d) set_const(current,rt1[i],v|imm[i]);
1570       if(opcode[i]==0x0e) set_const(current,rt1[i],v^imm[i]);
1571     }
1572     else clear_const(current,rt1[i]);
1573   }
1574   else if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU
1575     if(is_const(current,rs1[i])) {
1576       int v=get_const(current,rs1[i]);
1577       set_const(current,rt1[i],v+imm[i]);
1578     }
1579     else clear_const(current,rt1[i]);
1580     current->is32|=1LL<<rt1[i];
1581   }
1582   else {
1583     set_const(current,rt1[i],((long long)((short)imm[i]))<<16); // LUI
1584     current->is32|=1LL<<rt1[i];
1585   }
1586   dirty_reg(current,rt1[i]);
1587 }
1588
1589 void load_alloc(struct regstat *current,int i)
1590 {
1591   clear_const(current,rt1[i]);
1592   //if(rs1[i]!=rt1[i]&&needed_again(rs1[i],i)) clear_const(current,rs1[i]); // Does this help or hurt?
1593   if(!rs1[i]) current->u&=~1LL; // Allow allocating r0 if it's the source register
1594   if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1595   if(rt1[i]) {
1596     alloc_reg(current,i,rt1[i]);
1597     if(get_reg(current->regmap,rt1[i])<0) {
1598       // dummy load, but we still need a register to calculate the address
1599       alloc_reg_temp(current,i,-1);
1600       minimum_free_regs[i]=1;
1601     }
1602     if(opcode[i]==0x27||opcode[i]==0x37) // LWU/LD
1603     {
1604       current->is32&=~(1LL<<rt1[i]);
1605       alloc_reg64(current,i,rt1[i]);
1606     }
1607     else if(opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
1608     {
1609       current->is32&=~(1LL<<rt1[i]);
1610       alloc_reg64(current,i,rt1[i]);
1611       alloc_all(current,i);
1612       alloc_reg64(current,i,FTEMP);
1613       minimum_free_regs[i]=HOST_REGS;
1614     }
1615     else current->is32|=1LL<<rt1[i];
1616     dirty_reg(current,rt1[i]);
1617     // If using TLB, need a register for pointer to the mapping table
1618     if(using_tlb) alloc_reg(current,i,TLREG);
1619     // LWL/LWR need a temporary register for the old value
1620     if(opcode[i]==0x22||opcode[i]==0x26)
1621     {
1622       alloc_reg(current,i,FTEMP);
1623       alloc_reg_temp(current,i,-1);
1624       minimum_free_regs[i]=1;
1625     }
1626   }
1627   else
1628   {
1629     // Load to r0 (dummy load)
1630     // but we still need a register to calculate the address
1631     if(opcode[i]==0x22||opcode[i]==0x26)
1632     {
1633       alloc_reg(current,i,FTEMP); // LWL/LWR need another temporary
1634     }
1635     alloc_reg_temp(current,i,-1);
1636     minimum_free_regs[i]=1;
1637     if(opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
1638     {
1639       alloc_all(current,i);
1640       alloc_reg64(current,i,FTEMP);
1641       minimum_free_regs[i]=HOST_REGS;
1642     }
1643   }
1644 }
1645
1646 void store_alloc(struct regstat *current,int i)
1647 {
1648   clear_const(current,rs2[i]);
1649   if(!(rs2[i])) current->u&=~1LL; // Allow allocating r0 if necessary
1650   if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1651   alloc_reg(current,i,rs2[i]);
1652   if(opcode[i]==0x2c||opcode[i]==0x2d||opcode[i]==0x3f) { // 64-bit SDL/SDR/SD
1653     alloc_reg64(current,i,rs2[i]);
1654     if(rs2[i]) alloc_reg(current,i,FTEMP);
1655   }
1656   // If using TLB, need a register for pointer to the mapping table
1657   if(using_tlb) alloc_reg(current,i,TLREG);
1658   #if defined(HOST_IMM8)
1659   // On CPUs without 32-bit immediates we need a pointer to invalid_code
1660   else alloc_reg(current,i,INVCP);
1661   #endif
1662   if(opcode[i]==0x2a||opcode[i]==0x2e||opcode[i]==0x2c||opcode[i]==0x2d) { // SWL/SWL/SDL/SDR
1663     alloc_reg(current,i,FTEMP);
1664   }
1665   // We need a temporary register for address generation
1666   alloc_reg_temp(current,i,-1);
1667   minimum_free_regs[i]=1;
1668 }
1669
1670 void c1ls_alloc(struct regstat *current,int i)
1671 {
1672   //clear_const(current,rs1[i]); // FIXME
1673   clear_const(current,rt1[i]);
1674   if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1675   alloc_reg(current,i,CSREG); // Status
1676   alloc_reg(current,i,FTEMP);
1677   if(opcode[i]==0x35||opcode[i]==0x3d) { // 64-bit LDC1/SDC1
1678     alloc_reg64(current,i,FTEMP);
1679   }
1680   // If using TLB, need a register for pointer to the mapping table
1681   if(using_tlb) alloc_reg(current,i,TLREG);
1682   #if defined(HOST_IMM8)
1683   // On CPUs without 32-bit immediates we need a pointer to invalid_code
1684   else if((opcode[i]&0x3b)==0x39) // SWC1/SDC1
1685     alloc_reg(current,i,INVCP);
1686   #endif
1687   // We need a temporary register for address generation
1688   alloc_reg_temp(current,i,-1);
1689 }
1690
1691 void c2ls_alloc(struct regstat *current,int i)
1692 {
1693   clear_const(current,rt1[i]);
1694   if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1695   alloc_reg(current,i,FTEMP);
1696   // If using TLB, need a register for pointer to the mapping table
1697   if(using_tlb) alloc_reg(current,i,TLREG);
1698   #if defined(HOST_IMM8)
1699   // On CPUs without 32-bit immediates we need a pointer to invalid_code
1700   else if((opcode[i]&0x3b)==0x3a) // SWC2/SDC2
1701     alloc_reg(current,i,INVCP);
1702   #endif
1703   // We need a temporary register for address generation
1704   alloc_reg_temp(current,i,-1);
1705   minimum_free_regs[i]=1;
1706 }
1707
1708 #ifndef multdiv_alloc
1709 void multdiv_alloc(struct regstat *current,int i)
1710 {
1711   //  case 0x18: MULT
1712   //  case 0x19: MULTU
1713   //  case 0x1A: DIV
1714   //  case 0x1B: DIVU
1715   //  case 0x1C: DMULT
1716   //  case 0x1D: DMULTU
1717   //  case 0x1E: DDIV
1718   //  case 0x1F: DDIVU
1719   clear_const(current,rs1[i]);
1720   clear_const(current,rs2[i]);
1721   if(rs1[i]&&rs2[i])
1722   {
1723     if((opcode2[i]&4)==0) // 32-bit
1724     {
1725       current->u&=~(1LL<<HIREG);
1726       current->u&=~(1LL<<LOREG);
1727       alloc_reg(current,i,HIREG);
1728       alloc_reg(current,i,LOREG);
1729       alloc_reg(current,i,rs1[i]);
1730       alloc_reg(current,i,rs2[i]);
1731       current->is32|=1LL<<HIREG;
1732       current->is32|=1LL<<LOREG;
1733       dirty_reg(current,HIREG);
1734       dirty_reg(current,LOREG);
1735     }
1736     else // 64-bit
1737     {
1738       current->u&=~(1LL<<HIREG);
1739       current->u&=~(1LL<<LOREG);
1740       current->uu&=~(1LL<<HIREG);
1741       current->uu&=~(1LL<<LOREG);
1742       alloc_reg64(current,i,HIREG);
1743       //if(HOST_REGS>10) alloc_reg64(current,i,LOREG);
1744       alloc_reg64(current,i,rs1[i]);
1745       alloc_reg64(current,i,rs2[i]);
1746       alloc_all(current,i);
1747       current->is32&=~(1LL<<HIREG);
1748       current->is32&=~(1LL<<LOREG);
1749       dirty_reg(current,HIREG);
1750       dirty_reg(current,LOREG);
1751       minimum_free_regs[i]=HOST_REGS;
1752     }
1753   }
1754   else
1755   {
1756     // Multiply by zero is zero.
1757     // MIPS does not have a divide by zero exception.
1758     // The result is undefined, we return zero.
1759     alloc_reg(current,i,HIREG);
1760     alloc_reg(current,i,LOREG);
1761     current->is32|=1LL<<HIREG;
1762     current->is32|=1LL<<LOREG;
1763     dirty_reg(current,HIREG);
1764     dirty_reg(current,LOREG);
1765   }
1766 }
1767 #endif
1768
1769 void cop0_alloc(struct regstat *current,int i)
1770 {
1771   if(opcode2[i]==0) // MFC0
1772   {
1773     if(rt1[i]) {
1774       clear_const(current,rt1[i]);
1775       alloc_all(current,i);
1776       alloc_reg(current,i,rt1[i]);
1777       current->is32|=1LL<<rt1[i];
1778       dirty_reg(current,rt1[i]);
1779     }
1780   }
1781   else if(opcode2[i]==4) // MTC0
1782   {
1783     if(rs1[i]){
1784       clear_const(current,rs1[i]);
1785       alloc_reg(current,i,rs1[i]);
1786       alloc_all(current,i);
1787     }
1788     else {
1789       alloc_all(current,i); // FIXME: Keep r0
1790       current->u&=~1LL;
1791       alloc_reg(current,i,0);
1792     }
1793   }
1794   else
1795   {
1796     // TLBR/TLBWI/TLBWR/TLBP/ERET
1797     assert(opcode2[i]==0x10);
1798     alloc_all(current,i);
1799   }
1800   minimum_free_regs[i]=HOST_REGS;
1801 }
1802
1803 void cop1_alloc(struct regstat *current,int i)
1804 {
1805   alloc_reg(current,i,CSREG); // Load status
1806   if(opcode2[i]<3) // MFC1/DMFC1/CFC1
1807   {
1808     if(rt1[i]){
1809       clear_const(current,rt1[i]);
1810       if(opcode2[i]==1) {
1811         alloc_reg64(current,i,rt1[i]); // DMFC1
1812         current->is32&=~(1LL<<rt1[i]);
1813       }else{
1814         alloc_reg(current,i,rt1[i]); // MFC1/CFC1
1815         current->is32|=1LL<<rt1[i];
1816       }
1817       dirty_reg(current,rt1[i]);
1818     }
1819     alloc_reg_temp(current,i,-1);
1820   }
1821   else if(opcode2[i]>3) // MTC1/DMTC1/CTC1
1822   {
1823     if(rs1[i]){
1824       clear_const(current,rs1[i]);
1825       if(opcode2[i]==5)
1826         alloc_reg64(current,i,rs1[i]); // DMTC1
1827       else
1828         alloc_reg(current,i,rs1[i]); // MTC1/CTC1
1829       alloc_reg_temp(current,i,-1);
1830     }
1831     else {
1832       current->u&=~1LL;
1833       alloc_reg(current,i,0);
1834       alloc_reg_temp(current,i,-1);
1835     }
1836   }
1837   minimum_free_regs[i]=1;
1838 }
1839 void fconv_alloc(struct regstat *current,int i)
1840 {
1841   alloc_reg(current,i,CSREG); // Load status
1842   alloc_reg_temp(current,i,-1);
1843   minimum_free_regs[i]=1;
1844 }
1845 void float_alloc(struct regstat *current,int i)
1846 {
1847   alloc_reg(current,i,CSREG); // Load status
1848   alloc_reg_temp(current,i,-1);
1849   minimum_free_regs[i]=1;
1850 }
1851 void c2op_alloc(struct regstat *current,int i)
1852 {
1853   alloc_reg_temp(current,i,-1);
1854 }
1855 void fcomp_alloc(struct regstat *current,int i)
1856 {
1857   alloc_reg(current,i,CSREG); // Load status
1858   alloc_reg(current,i,FSREG); // Load flags
1859   dirty_reg(current,FSREG); // Flag will be modified
1860   alloc_reg_temp(current,i,-1);
1861   minimum_free_regs[i]=1;
1862 }
1863
1864 void syscall_alloc(struct regstat *current,int i)
1865 {
1866   alloc_cc(current,i);
1867   dirty_reg(current,CCREG);
1868   alloc_all(current,i);
1869   minimum_free_regs[i]=HOST_REGS;
1870   current->isconst=0;
1871 }
1872
1873 void delayslot_alloc(struct regstat *current,int i)
1874 {
1875   switch(itype[i]) {
1876     case UJUMP:
1877     case CJUMP:
1878     case SJUMP:
1879     case RJUMP:
1880     case FJUMP:
1881     case SYSCALL:
1882     case HLECALL:
1883     case SPAN:
1884       assem_debug("jump in the delay slot.  this shouldn't happen.\n");//exit(1);
1885       printf("Disabled speculative precompilation\n");
1886       stop_after_jal=1;
1887       break;
1888     case IMM16:
1889       imm16_alloc(current,i);
1890       break;
1891     case LOAD:
1892     case LOADLR:
1893       load_alloc(current,i);
1894       break;
1895     case STORE:
1896     case STORELR:
1897       store_alloc(current,i);
1898       break;
1899     case ALU:
1900       alu_alloc(current,i);
1901       break;
1902     case SHIFT:
1903       shift_alloc(current,i);
1904       break;
1905     case MULTDIV:
1906       multdiv_alloc(current,i);
1907       break;
1908     case SHIFTIMM:
1909       shiftimm_alloc(current,i);
1910       break;
1911     case MOV:
1912       mov_alloc(current,i);
1913       break;
1914     case COP0:
1915       cop0_alloc(current,i);
1916       break;
1917     case COP1:
1918     case COP2:
1919       cop1_alloc(current,i);
1920       break;
1921     case C1LS:
1922       c1ls_alloc(current,i);
1923       break;
1924     case C2LS:
1925       c2ls_alloc(current,i);
1926       break;
1927     case FCONV:
1928       fconv_alloc(current,i);
1929       break;
1930     case FLOAT:
1931       float_alloc(current,i);
1932       break;
1933     case FCOMP:
1934       fcomp_alloc(current,i);
1935       break;
1936     case C2OP:
1937       c2op_alloc(current,i);
1938       break;
1939   }
1940 }
1941
1942 // Special case where a branch and delay slot span two pages in virtual memory
1943 static void pagespan_alloc(struct regstat *current,int i)
1944 {
1945   current->isconst=0;
1946   current->wasconst=0;
1947   regs[i].wasconst=0;
1948   minimum_free_regs[i]=HOST_REGS;
1949   alloc_all(current,i);
1950   alloc_cc(current,i);
1951   dirty_reg(current,CCREG);
1952   if(opcode[i]==3) // JAL
1953   {
1954     alloc_reg(current,i,31);
1955     dirty_reg(current,31);
1956   }
1957   if(opcode[i]==0&&(opcode2[i]&0x3E)==8) // JR/JALR
1958   {
1959     alloc_reg(current,i,rs1[i]);
1960     if (rt1[i]!=0) {
1961       alloc_reg(current,i,rt1[i]);
1962       dirty_reg(current,rt1[i]);
1963     }
1964   }
1965   if((opcode[i]&0x2E)==4) // BEQ/BNE/BEQL/BNEL
1966   {
1967     if(rs1[i]) alloc_reg(current,i,rs1[i]);
1968     if(rs2[i]) alloc_reg(current,i,rs2[i]);
1969     if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1970     {
1971       if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1972       if(rs2[i]) alloc_reg64(current,i,rs2[i]);
1973     }
1974   }
1975   else
1976   if((opcode[i]&0x2E)==6) // BLEZ/BGTZ/BLEZL/BGTZL
1977   {
1978     if(rs1[i]) alloc_reg(current,i,rs1[i]);
1979     if(!((current->is32>>rs1[i])&1))
1980     {
1981       if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1982     }
1983   }
1984   else
1985   if(opcode[i]==0x11) // BC1
1986   {
1987     alloc_reg(current,i,FSREG);
1988     alloc_reg(current,i,CSREG);
1989   }
1990   //else ...
1991 }
1992
1993 add_stub(int type,int addr,int retaddr,int a,int b,int c,int d,int e)
1994 {
1995   stubs[stubcount][0]=type;
1996   stubs[stubcount][1]=addr;
1997   stubs[stubcount][2]=retaddr;
1998   stubs[stubcount][3]=a;
1999   stubs[stubcount][4]=b;
2000   stubs[stubcount][5]=c;
2001   stubs[stubcount][6]=d;
2002   stubs[stubcount][7]=e;
2003   stubcount++;
2004 }
2005
2006 // Write out a single register
2007 void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32)
2008 {
2009   int hr;
2010   for(hr=0;hr<HOST_REGS;hr++) {
2011     if(hr!=EXCLUDE_REG) {
2012       if((regmap[hr]&63)==r) {
2013         if((dirty>>hr)&1) {
2014           if(regmap[hr]<64) {
2015             emit_storereg(r,hr);
2016 #ifndef FORCE32
2017             if((is32>>regmap[hr])&1) {
2018               emit_sarimm(hr,31,hr);
2019               emit_storereg(r|64,hr);
2020             }
2021 #endif
2022           }else{
2023             emit_storereg(r|64,hr);
2024           }
2025         }
2026       }
2027     }
2028   }
2029 }
2030
2031 int mchecksum()
2032 {
2033   //if(!tracedebug) return 0;
2034   int i;
2035   int sum=0;
2036   for(i=0;i<2097152;i++) {
2037     unsigned int temp=sum;
2038     sum<<=1;
2039     sum|=(~temp)>>31;
2040     sum^=((u_int *)rdram)[i];
2041   }
2042   return sum;
2043 }
2044 int rchecksum()
2045 {
2046   int i;
2047   int sum=0;
2048   for(i=0;i<64;i++)
2049     sum^=((u_int *)reg)[i];
2050   return sum;
2051 }
2052 void rlist()
2053 {
2054   int i;
2055   printf("TRACE: ");
2056   for(i=0;i<32;i++)
2057     printf("r%d:%8x%8x ",i,((int *)(reg+i))[1],((int *)(reg+i))[0]);
2058   printf("\n");
2059 #ifndef DISABLE_COP1
2060   printf("TRACE: ");
2061   for(i=0;i<32;i++)
2062     printf("f%d:%8x%8x ",i,((int*)reg_cop1_simple[i])[1],*((int*)reg_cop1_simple[i]));
2063   printf("\n");
2064 #endif
2065 }
2066
2067 void enabletrace()
2068 {
2069   tracedebug=1;
2070 }
2071
2072 void memdebug(int i)
2073 {
2074   //printf("TRACE: count=%d next=%d (checksum %x) lo=%8x%8x\n",Count,next_interupt,mchecksum(),(int)(reg[LOREG]>>32),(int)reg[LOREG]);
2075   //printf("TRACE: count=%d next=%d (rchecksum %x)\n",Count,next_interupt,rchecksum());
2076   //rlist();
2077   //if(tracedebug) {
2078   //if(Count>=-2084597794) {
2079   if((signed int)Count>=-2084597794&&(signed int)Count<0) {
2080   //if(0) {
2081     printf("TRACE: count=%d next=%d (checksum %x)\n",Count,next_interupt,mchecksum());
2082     //printf("TRACE: count=%d next=%d (checksum %x) Status=%x\n",Count,next_interupt,mchecksum(),Status);
2083     //printf("TRACE: count=%d next=%d (checksum %x) hi=%8x%8x\n",Count,next_interupt,mchecksum(),(int)(reg[HIREG]>>32),(int)reg[HIREG]);
2084     rlist();
2085     #ifdef __i386__
2086     printf("TRACE: %x\n",(&i)[-1]);
2087     #endif
2088     #ifdef __arm__
2089     int j;
2090     printf("TRACE: %x \n",(&j)[10]);
2091     printf("TRACE: %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x\n",(&j)[1],(&j)[2],(&j)[3],(&j)[4],(&j)[5],(&j)[6],(&j)[7],(&j)[8],(&j)[9],(&j)[10],(&j)[11],(&j)[12],(&j)[13],(&j)[14],(&j)[15],(&j)[16],(&j)[17],(&j)[18],(&j)[19],(&j)[20]);
2092     #endif
2093     //fflush(stdout);
2094   }
2095   //printf("TRACE: %x\n",(&i)[-1]);
2096 }
2097
2098 void tlb_debug(u_int cause, u_int addr, u_int iaddr)
2099 {
2100   printf("TLB Exception: instruction=%x addr=%x cause=%x\n",iaddr, addr, cause);
2101 }
2102
2103 void alu_assemble(int i,struct regstat *i_regs)
2104 {
2105   if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
2106     if(rt1[i]) {
2107       signed char s1,s2,t;
2108       t=get_reg(i_regs->regmap,rt1[i]);
2109       if(t>=0) {
2110         s1=get_reg(i_regs->regmap,rs1[i]);
2111         s2=get_reg(i_regs->regmap,rs2[i]);
2112         if(rs1[i]&&rs2[i]) {
2113           assert(s1>=0);
2114           assert(s2>=0);
2115           if(opcode2[i]&2) emit_sub(s1,s2,t);
2116           else emit_add(s1,s2,t);
2117         }
2118         else if(rs1[i]) {
2119           if(s1>=0) emit_mov(s1,t);
2120           else emit_loadreg(rs1[i],t);
2121         }
2122         else if(rs2[i]) {
2123           if(s2>=0) {
2124             if(opcode2[i]&2) emit_neg(s2,t);
2125             else emit_mov(s2,t);
2126           }
2127           else {
2128             emit_loadreg(rs2[i],t);
2129             if(opcode2[i]&2) emit_neg(t,t);
2130           }
2131         }
2132         else emit_zeroreg(t);
2133       }
2134     }
2135   }
2136   if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU
2137     if(rt1[i]) {
2138       signed char s1l,s2l,s1h,s2h,tl,th;
2139       tl=get_reg(i_regs->regmap,rt1[i]);
2140       th=get_reg(i_regs->regmap,rt1[i]|64);
2141       if(tl>=0) {
2142         s1l=get_reg(i_regs->regmap,rs1[i]);
2143         s2l=get_reg(i_regs->regmap,rs2[i]);
2144         s1h=get_reg(i_regs->regmap,rs1[i]|64);
2145         s2h=get_reg(i_regs->regmap,rs2[i]|64);
2146         if(rs1[i]&&rs2[i]) {
2147           assert(s1l>=0);
2148           assert(s2l>=0);
2149           if(opcode2[i]&2) emit_subs(s1l,s2l,tl);
2150           else emit_adds(s1l,s2l,tl);
2151           if(th>=0) {
2152             #ifdef INVERTED_CARRY
2153             if(opcode2[i]&2) {if(s1h!=th) emit_mov(s1h,th);emit_sbb(th,s2h);}
2154             #else
2155             if(opcode2[i]&2) emit_sbc(s1h,s2h,th);
2156             #endif
2157             else emit_add(s1h,s2h,th);
2158           }
2159         }
2160         else if(rs1[i]) {
2161           if(s1l>=0) emit_mov(s1l,tl);
2162           else emit_loadreg(rs1[i],tl);
2163           if(th>=0) {
2164             if(s1h>=0) emit_mov(s1h,th);
2165             else emit_loadreg(rs1[i]|64,th);
2166           }
2167         }
2168         else if(rs2[i]) {
2169           if(s2l>=0) {
2170             if(opcode2[i]&2) emit_negs(s2l,tl);
2171             else emit_mov(s2l,tl);
2172           }
2173           else {
2174             emit_loadreg(rs2[i],tl);
2175             if(opcode2[i]&2) emit_negs(tl,tl);
2176           }
2177           if(th>=0) {
2178             #ifdef INVERTED_CARRY
2179             if(s2h>=0) emit_mov(s2h,th);
2180             else emit_loadreg(rs2[i]|64,th);
2181             if(opcode2[i]&2) {
2182               emit_adcimm(-1,th); // x86 has inverted carry flag
2183               emit_not(th,th);
2184             }
2185             #else
2186             if(opcode2[i]&2) {
2187               if(s2h>=0) emit_rscimm(s2h,0,th);
2188               else {
2189                 emit_loadreg(rs2[i]|64,th);
2190                 emit_rscimm(th,0,th);
2191               }
2192             }else{
2193               if(s2h>=0) emit_mov(s2h,th);
2194               else emit_loadreg(rs2[i]|64,th);
2195             }
2196             #endif
2197           }
2198         }
2199         else {
2200           emit_zeroreg(tl);
2201           if(th>=0) emit_zeroreg(th);
2202         }
2203       }
2204     }
2205   }
2206   if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU
2207     if(rt1[i]) {
2208       signed char s1l,s1h,s2l,s2h,t;
2209       if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1))
2210       {
2211         t=get_reg(i_regs->regmap,rt1[i]);
2212         //assert(t>=0);
2213         if(t>=0) {
2214           s1l=get_reg(i_regs->regmap,rs1[i]);
2215           s1h=get_reg(i_regs->regmap,rs1[i]|64);
2216           s2l=get_reg(i_regs->regmap,rs2[i]);
2217           s2h=get_reg(i_regs->regmap,rs2[i]|64);
2218           if(rs2[i]==0) // rx<r0
2219           {
2220             assert(s1h>=0);
2221             if(opcode2[i]==0x2a) // SLT
2222               emit_shrimm(s1h,31,t);
2223             else // SLTU (unsigned can not be less than zero)
2224               emit_zeroreg(t);
2225           }
2226           else if(rs1[i]==0) // r0<rx
2227           {
2228             assert(s2h>=0);
2229             if(opcode2[i]==0x2a) // SLT
2230               emit_set_gz64_32(s2h,s2l,t);
2231             else // SLTU (set if not zero)
2232               emit_set_nz64_32(s2h,s2l,t);
2233           }
2234           else {
2235             assert(s1l>=0);assert(s1h>=0);
2236             assert(s2l>=0);assert(s2h>=0);
2237             if(opcode2[i]==0x2a) // SLT
2238               emit_set_if_less64_32(s1h,s1l,s2h,s2l,t);
2239             else // SLTU
2240               emit_set_if_carry64_32(s1h,s1l,s2h,s2l,t);
2241           }
2242         }
2243       } else {
2244         t=get_reg(i_regs->regmap,rt1[i]);
2245         //assert(t>=0);
2246         if(t>=0) {
2247           s1l=get_reg(i_regs->regmap,rs1[i]);
2248           s2l=get_reg(i_regs->regmap,rs2[i]);
2249           if(rs2[i]==0) // rx<r0
2250           {
2251             assert(s1l>=0);
2252             if(opcode2[i]==0x2a) // SLT
2253               emit_shrimm(s1l,31,t);
2254             else // SLTU (unsigned can not be less than zero)
2255               emit_zeroreg(t);
2256           }
2257           else if(rs1[i]==0) // r0<rx
2258           {
2259             assert(s2l>=0);
2260             if(opcode2[i]==0x2a) // SLT
2261               emit_set_gz32(s2l,t);
2262             else // SLTU (set if not zero)
2263               emit_set_nz32(s2l,t);
2264           }
2265           else{
2266             assert(s1l>=0);assert(s2l>=0);
2267             if(opcode2[i]==0x2a) // SLT
2268               emit_set_if_less32(s1l,s2l,t);
2269             else // SLTU
2270               emit_set_if_carry32(s1l,s2l,t);
2271           }
2272         }
2273       }
2274     }
2275   }
2276   if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR
2277     if(rt1[i]) {
2278       signed char s1l,s1h,s2l,s2h,th,tl;
2279       tl=get_reg(i_regs->regmap,rt1[i]);
2280       th=get_reg(i_regs->regmap,rt1[i]|64);
2281       if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1)&&th>=0)
2282       {
2283         assert(tl>=0);
2284         if(tl>=0) {
2285           s1l=get_reg(i_regs->regmap,rs1[i]);
2286           s1h=get_reg(i_regs->regmap,rs1[i]|64);
2287           s2l=get_reg(i_regs->regmap,rs2[i]);
2288           s2h=get_reg(i_regs->regmap,rs2[i]|64);
2289           if(rs1[i]&&rs2[i]) {
2290             assert(s1l>=0);assert(s1h>=0);
2291             assert(s2l>=0);assert(s2h>=0);
2292             if(opcode2[i]==0x24) { // AND
2293               emit_and(s1l,s2l,tl);
2294               emit_and(s1h,s2h,th);
2295             } else
2296             if(opcode2[i]==0x25) { // OR
2297               emit_or(s1l,s2l,tl);
2298               emit_or(s1h,s2h,th);
2299             } else
2300             if(opcode2[i]==0x26) { // XOR
2301               emit_xor(s1l,s2l,tl);
2302               emit_xor(s1h,s2h,th);
2303             } else
2304             if(opcode2[i]==0x27) { // NOR
2305               emit_or(s1l,s2l,tl);
2306               emit_or(s1h,s2h,th);
2307               emit_not(tl,tl);
2308               emit_not(th,th);
2309             }
2310           }
2311           else
2312           {
2313             if(opcode2[i]==0x24) { // AND
2314               emit_zeroreg(tl);
2315               emit_zeroreg(th);
2316             } else
2317             if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR
2318               if(rs1[i]){
2319                 if(s1l>=0) emit_mov(s1l,tl);
2320                 else emit_loadreg(rs1[i],tl);
2321                 if(s1h>=0) emit_mov(s1h,th);
2322                 else emit_loadreg(rs1[i]|64,th);
2323               }
2324               else
2325               if(rs2[i]){
2326                 if(s2l>=0) emit_mov(s2l,tl);
2327                 else emit_loadreg(rs2[i],tl);
2328                 if(s2h>=0) emit_mov(s2h,th);
2329                 else emit_loadreg(rs2[i]|64,th);
2330               }
2331               else{
2332                 emit_zeroreg(tl);
2333                 emit_zeroreg(th);
2334               }
2335             } else
2336             if(opcode2[i]==0x27) { // NOR
2337               if(rs1[i]){
2338                 if(s1l>=0) emit_not(s1l,tl);
2339                 else{
2340                   emit_loadreg(rs1[i],tl);
2341                   emit_not(tl,tl);
2342                 }
2343                 if(s1h>=0) emit_not(s1h,th);
2344                 else{
2345                   emit_loadreg(rs1[i]|64,th);
2346                   emit_not(th,th);
2347                 }
2348               }
2349               else
2350               if(rs2[i]){
2351                 if(s2l>=0) emit_not(s2l,tl);
2352                 else{
2353                   emit_loadreg(rs2[i],tl);
2354                   emit_not(tl,tl);
2355                 }
2356                 if(s2h>=0) emit_not(s2h,th);
2357                 else{
2358                   emit_loadreg(rs2[i]|64,th);
2359                   emit_not(th,th);
2360                 }
2361               }
2362               else {
2363                 emit_movimm(-1,tl);
2364                 emit_movimm(-1,th);
2365               }
2366             }
2367           }
2368         }
2369       }
2370       else
2371       {
2372         // 32 bit
2373         if(tl>=0) {
2374           s1l=get_reg(i_regs->regmap,rs1[i]);
2375           s2l=get_reg(i_regs->regmap,rs2[i]);
2376           if(rs1[i]&&rs2[i]) {
2377             assert(s1l>=0);
2378             assert(s2l>=0);
2379             if(opcode2[i]==0x24) { // AND
2380               emit_and(s1l,s2l,tl);
2381             } else
2382             if(opcode2[i]==0x25) { // OR
2383               emit_or(s1l,s2l,tl);
2384             } else
2385             if(opcode2[i]==0x26) { // XOR
2386               emit_xor(s1l,s2l,tl);
2387             } else
2388             if(opcode2[i]==0x27) { // NOR
2389               emit_or(s1l,s2l,tl);
2390               emit_not(tl,tl);
2391             }
2392           }
2393           else
2394           {
2395             if(opcode2[i]==0x24) { // AND
2396               emit_zeroreg(tl);
2397             } else
2398             if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR
2399               if(rs1[i]){
2400                 if(s1l>=0) emit_mov(s1l,tl);
2401                 else emit_loadreg(rs1[i],tl); // CHECK: regmap_entry?
2402               }
2403               else
2404               if(rs2[i]){
2405                 if(s2l>=0) emit_mov(s2l,tl);
2406                 else emit_loadreg(rs2[i],tl); // CHECK: regmap_entry?
2407               }
2408               else emit_zeroreg(tl);
2409             } else
2410             if(opcode2[i]==0x27) { // NOR
2411               if(rs1[i]){
2412                 if(s1l>=0) emit_not(s1l,tl);
2413                 else {
2414                   emit_loadreg(rs1[i],tl);
2415                   emit_not(tl,tl);
2416                 }
2417               }
2418               else
2419               if(rs2[i]){
2420                 if(s2l>=0) emit_not(s2l,tl);
2421                 else {
2422                   emit_loadreg(rs2[i],tl);
2423                   emit_not(tl,tl);
2424                 }
2425               }
2426               else emit_movimm(-1,tl);
2427             }
2428           }
2429         }
2430       }
2431     }
2432   }
2433 }
2434
2435 void imm16_assemble(int i,struct regstat *i_regs)
2436 {
2437   if (opcode[i]==0x0f) { // LUI
2438     if(rt1[i]) {
2439       signed char t;
2440       t=get_reg(i_regs->regmap,rt1[i]);
2441       //assert(t>=0);
2442       if(t>=0) {
2443         if(!((i_regs->isconst>>t)&1))
2444           emit_movimm(imm[i]<<16,t);
2445       }
2446     }
2447   }
2448   if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU
2449     if(rt1[i]) {
2450       signed char s,t;
2451       t=get_reg(i_regs->regmap,rt1[i]);
2452       s=get_reg(i_regs->regmap,rs1[i]);
2453       if(rs1[i]) {
2454         //assert(t>=0);
2455         //assert(s>=0);
2456         if(t>=0) {
2457           if(!((i_regs->isconst>>t)&1)) {
2458             if(s<0) {
2459               if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2460               emit_addimm(t,imm[i],t);
2461             }else{
2462               if(!((i_regs->wasconst>>s)&1))
2463                 emit_addimm(s,imm[i],t);
2464               else
2465                 emit_movimm(constmap[i][s]+imm[i],t);
2466             }
2467           }
2468         }
2469       } else {
2470         if(t>=0) {
2471           if(!((i_regs->isconst>>t)&1))
2472             emit_movimm(imm[i],t);
2473         }
2474       }
2475     }
2476   }
2477   if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU
2478     if(rt1[i]) {
2479       signed char sh,sl,th,tl;
2480       th=get_reg(i_regs->regmap,rt1[i]|64);
2481       tl=get_reg(i_regs->regmap,rt1[i]);
2482       sh=get_reg(i_regs->regmap,rs1[i]|64);
2483       sl=get_reg(i_regs->regmap,rs1[i]);
2484       if(tl>=0) {
2485         if(rs1[i]) {
2486           assert(sh>=0);
2487           assert(sl>=0);
2488           if(th>=0) {
2489             emit_addimm64_32(sh,sl,imm[i],th,tl);
2490           }
2491           else {
2492             emit_addimm(sl,imm[i],tl);
2493           }
2494         } else {
2495           emit_movimm(imm[i],tl);
2496           if(th>=0) emit_movimm(((signed int)imm[i])>>31,th);
2497         }
2498       }
2499     }
2500   }
2501   else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU
2502     if(rt1[i]) {
2503       //assert(rs1[i]!=0); // r0 might be valid, but it's probably a bug
2504       signed char sh,sl,t;
2505       t=get_reg(i_regs->regmap,rt1[i]);
2506       sh=get_reg(i_regs->regmap,rs1[i]|64);
2507       sl=get_reg(i_regs->regmap,rs1[i]);
2508       //assert(t>=0);
2509       if(t>=0) {
2510         if(rs1[i]>0) {
2511           if(sh<0) assert((i_regs->was32>>rs1[i])&1);
2512           if(sh<0||((i_regs->was32>>rs1[i])&1)) {
2513             if(opcode[i]==0x0a) { // SLTI
2514               if(sl<0) {
2515                 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2516                 emit_slti32(t,imm[i],t);
2517               }else{
2518                 emit_slti32(sl,imm[i],t);
2519               }
2520             }
2521             else { // SLTIU
2522               if(sl<0) {
2523                 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2524                 emit_sltiu32(t,imm[i],t);
2525               }else{
2526                 emit_sltiu32(sl,imm[i],t);
2527               }
2528             }
2529           }else{ // 64-bit
2530             assert(sl>=0);
2531             if(opcode[i]==0x0a) // SLTI
2532               emit_slti64_32(sh,sl,imm[i],t);
2533             else // SLTIU
2534               emit_sltiu64_32(sh,sl,imm[i],t);
2535           }
2536         }else{
2537           // SLTI(U) with r0 is just stupid,
2538           // nonetheless examples can be found
2539           if(opcode[i]==0x0a) // SLTI
2540             if(0<imm[i]) emit_movimm(1,t);
2541             else emit_zeroreg(t);
2542           else // SLTIU
2543           {
2544             if(imm[i]) emit_movimm(1,t);
2545             else emit_zeroreg(t);
2546           }
2547         }
2548       }
2549     }
2550   }
2551   else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI
2552     if(rt1[i]) {
2553       signed char sh,sl,th,tl;
2554       th=get_reg(i_regs->regmap,rt1[i]|64);
2555       tl=get_reg(i_regs->regmap,rt1[i]);
2556       sh=get_reg(i_regs->regmap,rs1[i]|64);
2557       sl=get_reg(i_regs->regmap,rs1[i]);
2558       if(tl>=0 && !((i_regs->isconst>>tl)&1)) {
2559         if(opcode[i]==0x0c) //ANDI
2560         {
2561           if(rs1[i]) {
2562             if(sl<0) {
2563               if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl);
2564               emit_andimm(tl,imm[i],tl);
2565             }else{
2566               if(!((i_regs->wasconst>>sl)&1))
2567                 emit_andimm(sl,imm[i],tl);
2568               else
2569                 emit_movimm(constmap[i][sl]&imm[i],tl);
2570             }
2571           }
2572           else
2573             emit_zeroreg(tl);
2574           if(th>=0) emit_zeroreg(th);
2575         }
2576         else
2577         {
2578           if(rs1[i]) {
2579             if(sl<0) {
2580               if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl);
2581             }
2582             if(th>=0) {
2583               if(sh<0) {
2584                 emit_loadreg(rs1[i]|64,th);
2585               }else{
2586                 emit_mov(sh,th);
2587               }
2588             }
2589             if(opcode[i]==0x0d) //ORI
2590             if(sl<0) {
2591               emit_orimm(tl,imm[i],tl);
2592             }else{
2593               if(!((i_regs->wasconst>>sl)&1))
2594                 emit_orimm(sl,imm[i],tl);
2595               else
2596                 emit_movimm(constmap[i][sl]|imm[i],tl);
2597             }
2598             if(opcode[i]==0x0e) //XORI
2599             if(sl<0) {
2600               emit_xorimm(tl,imm[i],tl);
2601             }else{
2602               if(!((i_regs->wasconst>>sl)&1))
2603                 emit_xorimm(sl,imm[i],tl);
2604               else
2605                 emit_movimm(constmap[i][sl]^imm[i],tl);
2606             }
2607           }
2608           else {
2609             emit_movimm(imm[i],tl);
2610             if(th>=0) emit_zeroreg(th);
2611           }
2612         }
2613       }
2614     }
2615   }
2616 }
2617
2618 void shiftimm_assemble(int i,struct regstat *i_regs)
2619 {
2620   if(opcode2[i]<=0x3) // SLL/SRL/SRA
2621   {
2622     if(rt1[i]) {
2623       signed char s,t;
2624       t=get_reg(i_regs->regmap,rt1[i]);
2625       s=get_reg(i_regs->regmap,rs1[i]);
2626       //assert(t>=0);
2627       if(t>=0){
2628         if(rs1[i]==0)
2629         {
2630           emit_zeroreg(t);
2631         }
2632         else
2633         {
2634           if(s<0&&i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2635           if(imm[i]) {
2636             if(opcode2[i]==0) // SLL
2637             {
2638               emit_shlimm(s<0?t:s,imm[i],t);
2639             }
2640             if(opcode2[i]==2) // SRL
2641             {
2642               emit_shrimm(s<0?t:s,imm[i],t);
2643             }
2644             if(opcode2[i]==3) // SRA
2645             {
2646               emit_sarimm(s<0?t:s,imm[i],t);
2647             }
2648           }else{
2649             // Shift by zero
2650             if(s>=0 && s!=t) emit_mov(s,t);
2651           }
2652         }
2653       }
2654       //emit_storereg(rt1[i],t); //DEBUG
2655     }
2656   }
2657   if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA
2658   {
2659     if(rt1[i]) {
2660       signed char sh,sl,th,tl;
2661       th=get_reg(i_regs->regmap,rt1[i]|64);
2662       tl=get_reg(i_regs->regmap,rt1[i]);
2663       sh=get_reg(i_regs->regmap,rs1[i]|64);
2664       sl=get_reg(i_regs->regmap,rs1[i]);
2665       if(tl>=0) {
2666         if(rs1[i]==0)
2667         {
2668           emit_zeroreg(tl);
2669           if(th>=0) emit_zeroreg(th);
2670         }
2671         else
2672         {
2673           assert(sl>=0);
2674           assert(sh>=0);
2675           if(imm[i]) {
2676             if(opcode2[i]==0x38) // DSLL
2677             {
2678               if(th>=0) emit_shldimm(sh,sl,imm[i],th);
2679               emit_shlimm(sl,imm[i],tl);
2680             }
2681             if(opcode2[i]==0x3a) // DSRL
2682             {
2683               emit_shrdimm(sl,sh,imm[i],tl);
2684               if(th>=0) emit_shrimm(sh,imm[i],th);
2685             }
2686             if(opcode2[i]==0x3b) // DSRA
2687             {
2688               emit_shrdimm(sl,sh,imm[i],tl);
2689               if(th>=0) emit_sarimm(sh,imm[i],th);
2690             }
2691           }else{
2692             // Shift by zero
2693             if(sl!=tl) emit_mov(sl,tl);
2694             if(th>=0&&sh!=th) emit_mov(sh,th);
2695           }
2696         }
2697       }
2698     }
2699   }
2700   if(opcode2[i]==0x3c) // DSLL32
2701   {
2702     if(rt1[i]) {
2703       signed char sl,tl,th;
2704       tl=get_reg(i_regs->regmap,rt1[i]);
2705       th=get_reg(i_regs->regmap,rt1[i]|64);
2706       sl=get_reg(i_regs->regmap,rs1[i]);
2707       if(th>=0||tl>=0){
2708         assert(tl>=0);
2709         assert(th>=0);
2710         assert(sl>=0);
2711         emit_mov(sl,th);
2712         emit_zeroreg(tl);
2713         if(imm[i]>32)
2714         {
2715           emit_shlimm(th,imm[i]&31,th);
2716         }
2717       }
2718     }
2719   }
2720   if(opcode2[i]==0x3e) // DSRL32
2721   {
2722     if(rt1[i]) {
2723       signed char sh,tl,th;
2724       tl=get_reg(i_regs->regmap,rt1[i]);
2725       th=get_reg(i_regs->regmap,rt1[i]|64);
2726       sh=get_reg(i_regs->regmap,rs1[i]|64);
2727       if(tl>=0){
2728         assert(sh>=0);
2729         emit_mov(sh,tl);
2730         if(th>=0) emit_zeroreg(th);
2731         if(imm[i]>32)
2732         {
2733           emit_shrimm(tl,imm[i]&31,tl);
2734         }
2735       }
2736     }
2737   }
2738   if(opcode2[i]==0x3f) // DSRA32
2739   {
2740     if(rt1[i]) {
2741       signed char sh,tl;
2742       tl=get_reg(i_regs->regmap,rt1[i]);
2743       sh=get_reg(i_regs->regmap,rs1[i]|64);
2744       if(tl>=0){
2745         assert(sh>=0);
2746         emit_mov(sh,tl);
2747         if(imm[i]>32)
2748         {
2749           emit_sarimm(tl,imm[i]&31,tl);
2750         }
2751       }
2752     }
2753   }
2754 }
2755
2756 #ifndef shift_assemble
2757 void shift_assemble(int i,struct regstat *i_regs)
2758 {
2759   printf("Need shift_assemble for this architecture.\n");
2760   exit(1);
2761 }
2762 #endif
2763
2764 void load_assemble(int i,struct regstat *i_regs)
2765 {
2766   int s,th,tl,addr,map=-1;
2767   int offset;
2768   int jaddr=0;
2769   int memtarget=0,c=0;
2770   u_int hr,reglist=0;
2771   th=get_reg(i_regs->regmap,rt1[i]|64);
2772   tl=get_reg(i_regs->regmap,rt1[i]);
2773   s=get_reg(i_regs->regmap,rs1[i]);
2774   offset=imm[i];
2775   for(hr=0;hr<HOST_REGS;hr++) {
2776     if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
2777   }
2778   if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
2779   if(s>=0) {
2780     c=(i_regs->wasconst>>s)&1;
2781     memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
2782     if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
2783   }
2784   //printf("load_assemble: c=%d\n",c);
2785   //if(c) printf("load_assemble: const=%x\n",(int)constmap[i][s]+offset);
2786   // FIXME: Even if the load is a NOP, we should check for pagefaults...
2787 #ifdef PCSX
2788   if(tl<0&&(!c||(((u_int)constmap[i][s]+offset)>>16)==0x1f80)
2789     ||rt1[i]==0) {
2790       // could be FIFO, must perform the read
2791       // ||dummy read
2792       assem_debug("(forced read)\n");
2793       tl=get_reg(i_regs->regmap,-1);
2794       assert(tl>=0);
2795   }
2796 #endif
2797   if(offset||s<0||c) addr=tl;
2798   else addr=s;
2799   //if(tl<0) tl=get_reg(i_regs->regmap,-1);
2800  if(tl>=0) {
2801   //printf("load_assemble: c=%d\n",c);
2802   //if(c) printf("load_assemble: const=%x\n",(int)constmap[i][s]+offset);
2803   assert(tl>=0); // Even if the load is a NOP, we must check for pagefaults and I/O
2804   reglist&=~(1<<tl);
2805   if(th>=0) reglist&=~(1<<th);
2806   if(!using_tlb) {
2807     if(!c) {
2808       #ifdef RAM_OFFSET
2809       map=get_reg(i_regs->regmap,ROREG);
2810       if(map<0) emit_loadreg(ROREG,map=HOST_TEMPREG);
2811       #endif
2812 //#define R29_HACK 1
2813       #ifdef R29_HACK
2814       // Strmnnrmn's speed hack
2815       if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
2816       #endif
2817       {
2818         emit_cmpimm(addr,RAM_SIZE);
2819         jaddr=(int)out;
2820         #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
2821         // Hint to branch predictor that the branch is unlikely to be taken
2822         if(rs1[i]>=28)
2823           emit_jno_unlikely(0);
2824         else
2825         #endif
2826         emit_jno(0);
2827       }
2828     }
2829   }else{ // using tlb
2830     int x=0;
2831     if (opcode[i]==0x20||opcode[i]==0x24) x=3; // LB/LBU
2832     if (opcode[i]==0x21||opcode[i]==0x25) x=2; // LH/LHU
2833     map=get_reg(i_regs->regmap,TLREG);
2834     assert(map>=0);
2835     map=do_tlb_r(addr,tl,map,x,-1,-1,c,constmap[i][s]+offset);
2836     do_tlb_r_branch(map,c,constmap[i][s]+offset,&jaddr);
2837   }
2838   int dummy=(rt1[i]==0)||(tl!=get_reg(i_regs->regmap,rt1[i])); // ignore loads to r0 and unneeded reg
2839   if (opcode[i]==0x20) { // LB
2840     if(!c||memtarget) {
2841       if(!dummy) {
2842         #ifdef HOST_IMM_ADDR32
2843         if(c)
2844           emit_movsbl_tlb((constmap[i][s]+offset)^3,map,tl);
2845         else
2846         #endif
2847         {
2848           //emit_xorimm(addr,3,tl);
2849           //gen_tlb_addr_r(tl,map);
2850           //emit_movsbl_indexed((int)rdram-0x80000000,tl,tl);
2851           int x=0,a=tl;
2852 #ifdef BIG_ENDIAN_MIPS
2853           if(!c) emit_xorimm(addr,3,tl);
2854           else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2855 #else
2856           if(!c) a=addr;
2857 #endif
2858           emit_movsbl_indexed_tlb(x,a,map,tl);
2859         }
2860       }
2861       if(jaddr)
2862         add_stub(LOADB_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2863     }
2864     else
2865       inline_readstub(LOADB_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2866   }
2867   if (opcode[i]==0x21) { // LH
2868     if(!c||memtarget) {
2869       if(!dummy) {
2870         #ifdef HOST_IMM_ADDR32
2871         if(c)
2872           emit_movswl_tlb((constmap[i][s]+offset)^2,map,tl);
2873         else
2874         #endif
2875         {
2876           int x=0,a=tl;
2877 #ifdef BIG_ENDIAN_MIPS
2878           if(!c) emit_xorimm(addr,2,tl);
2879           else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
2880 #else
2881           if(!c) a=addr;
2882 #endif
2883           //#ifdef
2884           //emit_movswl_indexed_tlb(x,tl,map,tl);
2885           //else
2886           if(map>=0) {
2887             gen_tlb_addr_r(a,map);
2888             emit_movswl_indexed(x,a,tl);
2889           }else{
2890             #ifdef RAM_OFFSET
2891             emit_movswl_indexed(x,a,tl);
2892             #else
2893             emit_movswl_indexed((int)rdram-0x80000000+x,a,tl);
2894             #endif
2895           }
2896         }
2897       }
2898       if(jaddr)
2899         add_stub(LOADH_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2900     }
2901     else
2902       inline_readstub(LOADH_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2903   }
2904   if (opcode[i]==0x23) { // LW
2905     if(!c||memtarget) {
2906       if(!dummy) {
2907         //emit_readword_indexed((int)rdram-0x80000000,addr,tl);
2908         #ifdef HOST_IMM_ADDR32
2909         if(c)
2910           emit_readword_tlb(constmap[i][s]+offset,map,tl);
2911         else
2912         #endif
2913         emit_readword_indexed_tlb(0,addr,map,tl);
2914       }
2915       if(jaddr)
2916         add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2917     }
2918     else
2919       inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2920   }
2921   if (opcode[i]==0x24) { // LBU
2922     if(!c||memtarget) {
2923       if(!dummy) {
2924         #ifdef HOST_IMM_ADDR32
2925         if(c)
2926           emit_movzbl_tlb((constmap[i][s]+offset)^3,map,tl);
2927         else
2928         #endif
2929         {
2930           //emit_xorimm(addr,3,tl);
2931           //gen_tlb_addr_r(tl,map);
2932           //emit_movzbl_indexed((int)rdram-0x80000000,tl,tl);
2933           int x=0,a=tl;
2934 #ifdef BIG_ENDIAN_MIPS
2935           if(!c) emit_xorimm(addr,3,tl);
2936           else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2937 #else
2938           if(!c) a=addr;
2939 #endif
2940           emit_movzbl_indexed_tlb(x,a,map,tl);
2941         }
2942       }
2943       if(jaddr)
2944         add_stub(LOADBU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2945     }
2946     else
2947       inline_readstub(LOADBU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2948   }
2949   if (opcode[i]==0x25) { // LHU
2950     if(!c||memtarget) {
2951       if(!dummy) {
2952         #ifdef HOST_IMM_ADDR32
2953         if(c)
2954           emit_movzwl_tlb((constmap[i][s]+offset)^2,map,tl);
2955         else
2956         #endif
2957         {
2958           int x=0,a=tl;
2959 #ifdef BIG_ENDIAN_MIPS
2960           if(!c) emit_xorimm(addr,2,tl);
2961           else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
2962 #else
2963           if(!c) a=addr;
2964 #endif
2965           //#ifdef
2966           //emit_movzwl_indexed_tlb(x,tl,map,tl);
2967           //#else
2968           if(map>=0) {
2969             gen_tlb_addr_r(a,map);
2970             emit_movzwl_indexed(x,a,tl);
2971           }else{
2972             #ifdef RAM_OFFSET
2973             emit_movzwl_indexed(x,a,tl);
2974             #else
2975             emit_movzwl_indexed((int)rdram-0x80000000+x,a,tl);
2976             #endif
2977           }
2978         }
2979       }
2980       if(jaddr)
2981         add_stub(LOADHU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2982     }
2983     else
2984       inline_readstub(LOADHU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2985   }
2986   if (opcode[i]==0x27) { // LWU
2987     assert(th>=0);
2988     if(!c||memtarget) {
2989       if(!dummy) {
2990         //emit_readword_indexed((int)rdram-0x80000000,addr,tl);
2991         #ifdef HOST_IMM_ADDR32
2992         if(c)
2993           emit_readword_tlb(constmap[i][s]+offset,map,tl);
2994         else
2995         #endif
2996         emit_readword_indexed_tlb(0,addr,map,tl);
2997       }
2998       if(jaddr)
2999         add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3000     }
3001     else {
3002       inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3003     }
3004     emit_zeroreg(th);
3005   }
3006   if (opcode[i]==0x37) { // LD
3007     if(!c||memtarget) {
3008       if(!dummy) {
3009         //gen_tlb_addr_r(tl,map);
3010         //if(th>=0) emit_readword_indexed((int)rdram-0x80000000,addr,th);
3011         //emit_readword_indexed((int)rdram-0x7FFFFFFC,addr,tl);
3012         #ifdef HOST_IMM_ADDR32
3013         if(c)
3014           emit_readdword_tlb(constmap[i][s]+offset,map,th,tl);
3015         else
3016         #endif
3017         emit_readdword_indexed_tlb(0,addr,map,th,tl);
3018       }
3019       if(jaddr)
3020         add_stub(LOADD_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3021     }
3022     else
3023       inline_readstub(LOADD_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3024   }
3025  }
3026   //emit_storereg(rt1[i],tl); // DEBUG
3027   //if(opcode[i]==0x23)
3028   //if(opcode[i]==0x24)
3029   //if(opcode[i]==0x23||opcode[i]==0x24)
3030   /*if(opcode[i]==0x21||opcode[i]==0x23||opcode[i]==0x24)
3031   {
3032     //emit_pusha();
3033     save_regs(0x100f);
3034         emit_readword((int)&last_count,ECX);
3035         #ifdef __i386__
3036         if(get_reg(i_regs->regmap,CCREG)<0)
3037           emit_loadreg(CCREG,HOST_CCREG);
3038         emit_add(HOST_CCREG,ECX,HOST_CCREG);
3039         emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3040         emit_writeword(HOST_CCREG,(int)&Count);
3041         #endif
3042         #ifdef __arm__
3043         if(get_reg(i_regs->regmap,CCREG)<0)
3044           emit_loadreg(CCREG,0);
3045         else
3046           emit_mov(HOST_CCREG,0);
3047         emit_add(0,ECX,0);
3048         emit_addimm(0,2*ccadj[i],0);
3049         emit_writeword(0,(int)&Count);
3050         #endif
3051     emit_call((int)memdebug);
3052     //emit_popa();
3053     restore_regs(0x100f);
3054   }/**/
3055 }
3056
3057 #ifndef loadlr_assemble
3058 void loadlr_assemble(int i,struct regstat *i_regs)
3059 {
3060   printf("Need loadlr_assemble for this architecture.\n");
3061   exit(1);
3062 }
3063 #endif
3064
3065 void store_assemble(int i,struct regstat *i_regs)
3066 {
3067   int s,th,tl,map=-1;
3068   int addr,temp;
3069   int offset;
3070   int jaddr=0,jaddr2,type;
3071   int memtarget=0,c=0;
3072   int agr=AGEN1+(i&1);
3073   u_int hr,reglist=0;
3074   th=get_reg(i_regs->regmap,rs2[i]|64);
3075   tl=get_reg(i_regs->regmap,rs2[i]);
3076   s=get_reg(i_regs->regmap,rs1[i]);
3077   temp=get_reg(i_regs->regmap,agr);
3078   if(temp<0) temp=get_reg(i_regs->regmap,-1);
3079   offset=imm[i];
3080   if(s>=0) {
3081     c=(i_regs->wasconst>>s)&1;
3082     memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
3083     if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
3084   }
3085   assert(tl>=0);
3086   assert(temp>=0);
3087   for(hr=0;hr<HOST_REGS;hr++) {
3088     if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3089   }
3090   if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
3091   if(offset||s<0||c) addr=temp;
3092   else addr=s;
3093   if(!using_tlb) {
3094     if(!c) {
3095       #ifdef R29_HACK
3096       // Strmnnrmn's speed hack
3097       memtarget=1;
3098       if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
3099       #endif
3100       emit_cmpimm(addr,RAM_SIZE);
3101       #ifdef DESTRUCTIVE_SHIFT
3102       if(s==addr) emit_mov(s,temp);
3103       #endif
3104       #ifdef R29_HACK
3105       if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
3106       #endif
3107       {
3108         jaddr=(int)out;
3109         #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
3110         // Hint to branch predictor that the branch is unlikely to be taken
3111         if(rs1[i]>=28)
3112           emit_jno_unlikely(0);
3113         else
3114         #endif
3115         emit_jno(0);
3116       }
3117     }
3118   }else{ // using tlb
3119     int x=0;
3120     if (opcode[i]==0x28) x=3; // SB
3121     if (opcode[i]==0x29) x=2; // SH
3122     map=get_reg(i_regs->regmap,TLREG);
3123     assert(map>=0);
3124     map=do_tlb_w(addr,temp,map,x,c,constmap[i][s]+offset);
3125     do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr);
3126   }
3127
3128   if (opcode[i]==0x28) { // SB
3129     if(!c||memtarget) {
3130       int x=0;
3131 #ifdef BIG_ENDIAN_MIPS
3132       if(!c) emit_xorimm(addr,3,temp);
3133       else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
3134 #else
3135       if(c) x=(constmap[i][s]+offset)-(constmap[i][s]+offset);
3136       else if (addr!=temp) emit_mov(addr,temp);
3137 #endif
3138       //gen_tlb_addr_w(temp,map);
3139       //emit_writebyte_indexed(tl,(int)rdram-0x80000000,temp);
3140       emit_writebyte_indexed_tlb(tl,x,temp,map,temp);
3141     }
3142     type=STOREB_STUB;
3143   }
3144   if (opcode[i]==0x29) { // SH
3145     if(!c||memtarget) {
3146       int x=0;
3147 #ifdef BIG_ENDIAN_MIPS
3148       if(!c) emit_xorimm(addr,2,temp);
3149       else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
3150 #else
3151       if(c) x=(constmap[i][s]+offset)-(constmap[i][s]+offset);
3152       else if (addr!=temp) emit_mov(addr,temp);
3153 #endif
3154       //#ifdef
3155       //emit_writehword_indexed_tlb(tl,x,temp,map,temp);
3156       //#else
3157       if(map>=0) {
3158         gen_tlb_addr_w(temp,map);
3159         emit_writehword_indexed(tl,x,temp);
3160       }else
3161         emit_writehword_indexed(tl,(int)rdram-0x80000000+x,temp);
3162     }
3163     type=STOREH_STUB;
3164   }
3165   if (opcode[i]==0x2B) { // SW
3166     if(!c||memtarget)
3167       //emit_writeword_indexed(tl,(int)rdram-0x80000000,addr);
3168       emit_writeword_indexed_tlb(tl,0,addr,map,temp);
3169     type=STOREW_STUB;
3170   }
3171   if (opcode[i]==0x3F) { // SD
3172     if(!c||memtarget) {
3173       if(rs2[i]) {
3174         assert(th>=0);
3175         //emit_writeword_indexed(th,(int)rdram-0x80000000,addr);
3176         //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,addr);
3177         emit_writedword_indexed_tlb(th,tl,0,addr,map,temp);
3178       }else{
3179         // Store zero
3180         //emit_writeword_indexed(tl,(int)rdram-0x80000000,temp);
3181         //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,temp);
3182         emit_writedword_indexed_tlb(tl,tl,0,addr,map,temp);
3183       }
3184     }
3185     type=STORED_STUB;
3186   }
3187   if(!using_tlb) {
3188     if(!c||memtarget) {
3189       #ifdef DESTRUCTIVE_SHIFT
3190       // The x86 shift operation is 'destructive'; it overwrites the
3191       // source register, so we need to make a copy first and use that.
3192       addr=temp;
3193       #endif
3194       #if defined(HOST_IMM8)
3195       int ir=get_reg(i_regs->regmap,INVCP);
3196       assert(ir>=0);
3197       emit_cmpmem_indexedsr12_reg(ir,addr,1);
3198       #else
3199       emit_cmpmem_indexedsr12_imm((int)invalid_code,addr,1);
3200       #endif
3201       #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3202       emit_callne(invalidate_addr_reg[addr]);
3203       #else
3204       jaddr2=(int)out;
3205       emit_jne(0);
3206       add_stub(INVCODE_STUB,jaddr2,(int)out,reglist|(1<<HOST_CCREG),addr,0,0,0);
3207       #endif
3208     }
3209   }
3210   if(jaddr) {
3211     add_stub(type,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3212   } else if(c&&!memtarget) {
3213     inline_writestub(type,i,constmap[i][s]+offset,i_regs->regmap,rs2[i],ccadj[i],reglist);
3214   }
3215   //if(opcode[i]==0x2B || opcode[i]==0x3F)
3216   //if(opcode[i]==0x2B || opcode[i]==0x28)
3217   //if(opcode[i]==0x2B || opcode[i]==0x29)
3218   //if(opcode[i]==0x2B)
3219   /*if(opcode[i]==0x2B || opcode[i]==0x28 || opcode[i]==0x29 || opcode[i]==0x3F)
3220   {
3221     //emit_pusha();
3222     save_regs(0x100f);
3223         emit_readword((int)&last_count,ECX);
3224         #ifdef __i386__
3225         if(get_reg(i_regs->regmap,CCREG)<0)
3226           emit_loadreg(CCREG,HOST_CCREG);
3227         emit_add(HOST_CCREG,ECX,HOST_CCREG);
3228         emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3229         emit_writeword(HOST_CCREG,(int)&Count);
3230         #endif
3231         #ifdef __arm__
3232         if(get_reg(i_regs->regmap,CCREG)<0)
3233           emit_loadreg(CCREG,0);
3234         else
3235           emit_mov(HOST_CCREG,0);
3236         emit_add(0,ECX,0);
3237         emit_addimm(0,2*ccadj[i],0);
3238         emit_writeword(0,(int)&Count);
3239         #endif
3240     emit_call((int)memdebug);
3241     //emit_popa();
3242     restore_regs(0x100f);
3243   }/**/
3244 }
3245
3246 void storelr_assemble(int i,struct regstat *i_regs)
3247 {
3248   int s,th,tl;
3249   int temp;
3250   int temp2;
3251   int offset;
3252   int jaddr=0,jaddr2;
3253   int case1,case2,case3;
3254   int done0,done1,done2;
3255   int memtarget,c=0;
3256   int agr=AGEN1+(i&1);
3257   u_int hr,reglist=0;
3258   th=get_reg(i_regs->regmap,rs2[i]|64);
3259   tl=get_reg(i_regs->regmap,rs2[i]);
3260   s=get_reg(i_regs->regmap,rs1[i]);
3261   temp=get_reg(i_regs->regmap,agr);
3262   if(temp<0) temp=get_reg(i_regs->regmap,-1);
3263   offset=imm[i];
3264   if(s>=0) {
3265     c=(i_regs->isconst>>s)&1;
3266     memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
3267     if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
3268   }
3269   assert(tl>=0);
3270   for(hr=0;hr<HOST_REGS;hr++) {
3271     if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3272   }
3273   assert(temp>=0);
3274   if(!using_tlb) {
3275     if(!c) {
3276       emit_cmpimm(s<0||offset?temp:s,RAM_SIZE);
3277       if(!offset&&s!=temp) emit_mov(s,temp);
3278       jaddr=(int)out;
3279       emit_jno(0);
3280     }
3281     else
3282     {
3283       if(!memtarget||!rs1[i]) {
3284         jaddr=(int)out;
3285         emit_jmp(0);
3286       }
3287     }
3288     #ifdef RAM_OFFSET
3289     int map=get_reg(i_regs->regmap,ROREG);
3290     if(map<0) emit_loadreg(ROREG,map=HOST_TEMPREG);
3291     gen_tlb_addr_w(temp,map);
3292     #else
3293     if((u_int)rdram!=0x80000000)
3294       emit_addimm_no_flags((u_int)rdram-(u_int)0x80000000,temp);
3295     #endif
3296   }else{ // using tlb
3297     int map=get_reg(i_regs->regmap,TLREG);
3298     assert(map>=0);
3299     map=do_tlb_w(c||s<0||offset?temp:s,temp,map,0,c,constmap[i][s]+offset);
3300     if(!c&&!offset&&s>=0) emit_mov(s,temp);
3301     do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr);
3302     if(!jaddr&&!memtarget) {
3303       jaddr=(int)out;
3304       emit_jmp(0);
3305     }
3306     gen_tlb_addr_w(temp,map);
3307   }
3308
3309   if (opcode[i]==0x2C||opcode[i]==0x2D) { // SDL/SDR
3310     temp2=get_reg(i_regs->regmap,FTEMP);
3311     if(!rs2[i]) temp2=th=tl;
3312   }
3313
3314 #ifndef BIG_ENDIAN_MIPS
3315     emit_xorimm(temp,3,temp);
3316 #endif
3317   emit_testimm(temp,2);
3318   case2=(int)out;
3319   emit_jne(0);
3320   emit_testimm(temp,1);
3321   case1=(int)out;
3322   emit_jne(0);
3323   // 0
3324   if (opcode[i]==0x2A) { // SWL
3325     emit_writeword_indexed(tl,0,temp);
3326   }
3327   if (opcode[i]==0x2E) { // SWR
3328     emit_writebyte_indexed(tl,3,temp);
3329   }
3330   if (opcode[i]==0x2C) { // SDL
3331     emit_writeword_indexed(th,0,temp);
3332     if(rs2[i]) emit_mov(tl,temp2);
3333   }
3334   if (opcode[i]==0x2D) { // SDR
3335     emit_writebyte_indexed(tl,3,temp);
3336     if(rs2[i]) emit_shldimm(th,tl,24,temp2);
3337   }
3338   done0=(int)out;
3339   emit_jmp(0);
3340   // 1
3341   set_jump_target(case1,(int)out);
3342   if (opcode[i]==0x2A) { // SWL
3343     // Write 3 msb into three least significant bytes
3344     if(rs2[i]) emit_rorimm(tl,8,tl);
3345     emit_writehword_indexed(tl,-1,temp);
3346     if(rs2[i]) emit_rorimm(tl,16,tl);
3347     emit_writebyte_indexed(tl,1,temp);
3348     if(rs2[i]) emit_rorimm(tl,8,tl);
3349   }
3350   if (opcode[i]==0x2E) { // SWR
3351     // Write two lsb into two most significant bytes
3352     emit_writehword_indexed(tl,1,temp);
3353   }
3354   if (opcode[i]==0x2C) { // SDL
3355     if(rs2[i]) emit_shrdimm(tl,th,8,temp2);
3356     // Write 3 msb into three least significant bytes
3357     if(rs2[i]) emit_rorimm(th,8,th);
3358     emit_writehword_indexed(th,-1,temp);
3359     if(rs2[i]) emit_rorimm(th,16,th);
3360     emit_writebyte_indexed(th,1,temp);
3361     if(rs2[i]) emit_rorimm(th,8,th);
3362   }
3363   if (opcode[i]==0x2D) { // SDR
3364     if(rs2[i]) emit_shldimm(th,tl,16,temp2);
3365     // Write two lsb into two most significant bytes
3366     emit_writehword_indexed(tl,1,temp);
3367   }
3368   done1=(int)out;
3369   emit_jmp(0);
3370   // 2
3371   set_jump_target(case2,(int)out);
3372   emit_testimm(temp,1);
3373   case3=(int)out;
3374   emit_jne(0);
3375   if (opcode[i]==0x2A) { // SWL
3376     // Write two msb into two least significant bytes
3377     if(rs2[i]) emit_rorimm(tl,16,tl);
3378     emit_writehword_indexed(tl,-2,temp);
3379     if(rs2[i]) emit_rorimm(tl,16,tl);
3380   }
3381   if (opcode[i]==0x2E) { // SWR
3382     // Write 3 lsb into three most significant bytes
3383     emit_writebyte_indexed(tl,-1,temp);
3384     if(rs2[i]) emit_rorimm(tl,8,tl);
3385     emit_writehword_indexed(tl,0,temp);
3386     if(rs2[i]) emit_rorimm(tl,24,tl);
3387   }
3388   if (opcode[i]==0x2C) { // SDL
3389     if(rs2[i]) emit_shrdimm(tl,th,16,temp2);
3390     // Write two msb into two least significant bytes
3391     if(rs2[i]) emit_rorimm(th,16,th);
3392     emit_writehword_indexed(th,-2,temp);
3393     if(rs2[i]) emit_rorimm(th,16,th);
3394   }
3395   if (opcode[i]==0x2D) { // SDR
3396     if(rs2[i]) emit_shldimm(th,tl,8,temp2);
3397     // Write 3 lsb into three most significant bytes
3398     emit_writebyte_indexed(tl,-1,temp);
3399     if(rs2[i]) emit_rorimm(tl,8,tl);
3400     emit_writehword_indexed(tl,0,temp);
3401     if(rs2[i]) emit_rorimm(tl,24,tl);
3402   }
3403   done2=(int)out;
3404   emit_jmp(0);
3405   // 3
3406   set_jump_target(case3,(int)out);
3407   if (opcode[i]==0x2A) { // SWL
3408     // Write msb into least significant byte
3409     if(rs2[i]) emit_rorimm(tl,24,tl);
3410     emit_writebyte_indexed(tl,-3,temp);
3411     if(rs2[i]) emit_rorimm(tl,8,tl);
3412   }
3413   if (opcode[i]==0x2E) { // SWR
3414     // Write entire word
3415     emit_writeword_indexed(tl,-3,temp);
3416   }
3417   if (opcode[i]==0x2C) { // SDL
3418     if(rs2[i]) emit_shrdimm(tl,th,24,temp2);
3419     // Write msb into least significant byte
3420     if(rs2[i]) emit_rorimm(th,24,th);
3421     emit_writebyte_indexed(th,-3,temp);
3422     if(rs2[i]) emit_rorimm(th,8,th);
3423   }
3424   if (opcode[i]==0x2D) { // SDR
3425     if(rs2[i]) emit_mov(th,temp2);
3426     // Write entire word
3427     emit_writeword_indexed(tl,-3,temp);
3428   }
3429   set_jump_target(done0,(int)out);
3430   set_jump_target(done1,(int)out);
3431   set_jump_target(done2,(int)out);
3432   if (opcode[i]==0x2C) { // SDL
3433     emit_testimm(temp,4);
3434     done0=(int)out;
3435     emit_jne(0);
3436     emit_andimm(temp,~3,temp);
3437     emit_writeword_indexed(temp2,4,temp);
3438     set_jump_target(done0,(int)out);
3439   }
3440   if (opcode[i]==0x2D) { // SDR
3441     emit_testimm(temp,4);
3442     done0=(int)out;
3443     emit_jeq(0);
3444     emit_andimm(temp,~3,temp);
3445     emit_writeword_indexed(temp2,-4,temp);
3446     set_jump_target(done0,(int)out);
3447   }
3448   if(!c||!memtarget)
3449     add_stub(STORELR_STUB,jaddr,(int)out,i,(int)i_regs,temp,ccadj[i],reglist);
3450   if(!using_tlb) {
3451     #ifdef RAM_OFFSET
3452     int map=get_reg(i_regs->regmap,ROREG);
3453     if(map<0) map=HOST_TEMPREG;
3454     gen_orig_addr_w(temp,map);
3455     #else
3456     emit_addimm_no_flags((u_int)0x80000000-(u_int)rdram,temp);
3457     #endif
3458     #if defined(HOST_IMM8)
3459     int ir=get_reg(i_regs->regmap,INVCP);
3460     assert(ir>=0);
3461     emit_cmpmem_indexedsr12_reg(ir,temp,1);
3462     #else
3463     emit_cmpmem_indexedsr12_imm((int)invalid_code,temp,1);
3464     #endif
3465     #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3466     emit_callne(invalidate_addr_reg[temp]);
3467     #else
3468     jaddr2=(int)out;
3469     emit_jne(0);
3470     add_stub(INVCODE_STUB,jaddr2,(int)out,reglist|(1<<HOST_CCREG),temp,0,0,0);
3471     #endif
3472   }
3473   /*
3474     emit_pusha();
3475     //save_regs(0x100f);
3476         emit_readword((int)&last_count,ECX);
3477         if(get_reg(i_regs->regmap,CCREG)<0)
3478           emit_loadreg(CCREG,HOST_CCREG);
3479         emit_add(HOST_CCREG,ECX,HOST_CCREG);
3480         emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3481         emit_writeword(HOST_CCREG,(int)&Count);
3482     emit_call((int)memdebug);
3483     emit_popa();
3484     //restore_regs(0x100f);
3485   /**/
3486 }
3487
3488 void c1ls_assemble(int i,struct regstat *i_regs)
3489 {
3490 #ifndef DISABLE_COP1
3491   int s,th,tl;
3492   int temp,ar;
3493   int map=-1;
3494   int offset;
3495   int c=0;
3496   int jaddr,jaddr2=0,jaddr3,type;
3497   int agr=AGEN1+(i&1);
3498   u_int hr,reglist=0;
3499   th=get_reg(i_regs->regmap,FTEMP|64);
3500   tl=get_reg(i_regs->regmap,FTEMP);
3501   s=get_reg(i_regs->regmap,rs1[i]);
3502   temp=get_reg(i_regs->regmap,agr);
3503   if(temp<0) temp=get_reg(i_regs->regmap,-1);
3504   offset=imm[i];
3505   assert(tl>=0);
3506   assert(rs1[i]>0);
3507   assert(temp>=0);
3508   for(hr=0;hr<HOST_REGS;hr++) {
3509     if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3510   }
3511   if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
3512   if (opcode[i]==0x31||opcode[i]==0x35) // LWC1/LDC1
3513   {
3514     // Loads use a temporary register which we need to save
3515     reglist|=1<<temp;
3516   }
3517   if (opcode[i]==0x39||opcode[i]==0x3D) // SWC1/SDC1
3518     ar=temp;
3519   else // LWC1/LDC1
3520     ar=tl;
3521   //if(s<0) emit_loadreg(rs1[i],ar); //address_generation does this now
3522   //else c=(i_regs->wasconst>>s)&1;
3523   if(s>=0) c=(i_regs->wasconst>>s)&1;
3524   // Check cop1 unusable
3525   if(!cop1_usable) {
3526     signed char rs=get_reg(i_regs->regmap,CSREG);
3527     assert(rs>=0);
3528     emit_testimm(rs,0x20000000);
3529     jaddr=(int)out;
3530     emit_jeq(0);
3531     add_stub(FP_STUB,jaddr,(int)out,i,rs,(int)i_regs,is_delayslot,0);
3532     cop1_usable=1;
3533   }
3534   if (opcode[i]==0x39) { // SWC1 (get float address)
3535     emit_readword((int)&reg_cop1_simple[(source[i]>>16)&0x1f],tl);
3536   }
3537   if (opcode[i]==0x3D) { // SDC1 (get double address)
3538     emit_readword((int)&reg_cop1_double[(source[i]>>16)&0x1f],tl);
3539   }
3540   // Generate address + offset
3541   if(!using_tlb) {
3542     if(!c)
3543       emit_cmpimm(offset||c||s<0?ar:s,RAM_SIZE);
3544   }
3545   else
3546   {
3547     map=get_reg(i_regs->regmap,TLREG);
3548     assert(map>=0);
3549     if (opcode[i]==0x31||opcode[i]==0x35) { // LWC1/LDC1
3550       map=do_tlb_r(offset||c||s<0?ar:s,ar,map,0,-1,-1,c,constmap[i][s]+offset);
3551     }
3552     if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3553       map=do_tlb_w(offset||c||s<0?ar:s,ar,map,0,c,constmap[i][s]+offset);
3554     }
3555   }
3556   if (opcode[i]==0x39) { // SWC1 (read float)
3557     emit_readword_indexed(0,tl,tl);
3558   }
3559   if (opcode[i]==0x3D) { // SDC1 (read double)
3560     emit_readword_indexed(4,tl,th);
3561     emit_readword_indexed(0,tl,tl);
3562   }
3563   if (opcode[i]==0x31) { // LWC1 (get target address)
3564     emit_readword((int)&reg_cop1_simple[(source[i]>>16)&0x1f],temp);
3565   }
3566   if (opcode[i]==0x35) { // LDC1 (get target address)
3567     emit_readword((int)&reg_cop1_double[(source[i]>>16)&0x1f],temp);
3568   }
3569   if(!using_tlb) {
3570     if(!c) {
3571       jaddr2=(int)out;
3572       emit_jno(0);
3573     }
3574     else if(((signed int)(constmap[i][s]+offset))>=(signed int)0x80000000+RAM_SIZE) {
3575       jaddr2=(int)out;
3576       emit_jmp(0); // inline_readstub/inline_writestub?  Very rare case
3577     }
3578     #ifdef DESTRUCTIVE_SHIFT
3579     if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3580       if(!offset&&!c&&s>=0) emit_mov(s,ar);
3581     }
3582     #endif
3583   }else{
3584     if (opcode[i]==0x31||opcode[i]==0x35) { // LWC1/LDC1
3585       do_tlb_r_branch(map,c,constmap[i][s]+offset,&jaddr2);
3586     }
3587     if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3588       do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr2);
3589     }
3590   }
3591   if (opcode[i]==0x31) { // LWC1
3592     //if(s>=0&&!c&&!offset) emit_mov(s,tl);
3593     //gen_tlb_addr_r(ar,map);
3594     //emit_readword_indexed((int)rdram-0x80000000,tl,tl);
3595     #ifdef HOST_IMM_ADDR32
3596     if(c) emit_readword_tlb(constmap[i][s]+offset,map,tl);
3597     else
3598     #endif
3599     emit_readword_indexed_tlb(0,offset||c||s<0?tl:s,map,tl);
3600     type=LOADW_STUB;
3601   }
3602   if (opcode[i]==0x35) { // LDC1
3603     assert(th>=0);
3604     //if(s>=0&&!c&&!offset) emit_mov(s,tl);
3605     //gen_tlb_addr_r(ar,map);
3606     //emit_readword_indexed((int)rdram-0x80000000,tl,th);
3607     //emit_readword_indexed((int)rdram-0x7FFFFFFC,tl,tl);
3608     #ifdef HOST_IMM_ADDR32
3609     if(c) emit_readdword_tlb(constmap[i][s]+offset,map,th,tl);
3610     else
3611     #endif
3612     emit_readdword_indexed_tlb(0,offset||c||s<0?tl:s,map,th,tl);
3613     type=LOADD_STUB;
3614   }
3615   if (opcode[i]==0x39) { // SWC1
3616     //emit_writeword_indexed(tl,(int)rdram-0x80000000,temp);
3617     emit_writeword_indexed_tlb(tl,0,offset||c||s<0?temp:s,map,temp);
3618     type=STOREW_STUB;
3619   }
3620   if (opcode[i]==0x3D) { // SDC1
3621     assert(th>=0);
3622     //emit_writeword_indexed(th,(int)rdram-0x80000000,temp);
3623     //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,temp);
3624     emit_writedword_indexed_tlb(th,tl,0,offset||c||s<0?temp:s,map,temp);
3625     type=STORED_STUB;
3626   }
3627   if(!using_tlb) {
3628     if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3629       #ifndef DESTRUCTIVE_SHIFT
3630       temp=offset||c||s<0?ar:s;
3631       #endif
3632       #if defined(HOST_IMM8)
3633       int ir=get_reg(i_regs->regmap,INVCP);
3634       assert(ir>=0);
3635       emit_cmpmem_indexedsr12_reg(ir,temp,1);
3636       #else
3637       emit_cmpmem_indexedsr12_imm((int)invalid_code,temp,1);
3638       #endif
3639       #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3640       emit_callne(invalidate_addr_reg[temp]);
3641       #else
3642       jaddr3=(int)out;
3643       emit_jne(0);
3644       add_stub(INVCODE_STUB,jaddr3,(int)out,reglist|(1<<HOST_CCREG),temp,0,0,0);
3645       #endif
3646     }
3647   }
3648   if(jaddr2) add_stub(type,jaddr2,(int)out,i,offset||c||s<0?ar:s,(int)i_regs,ccadj[i],reglist);
3649   if (opcode[i]==0x31) { // LWC1 (write float)
3650     emit_writeword_indexed(tl,0,temp);
3651   }
3652   if (opcode[i]==0x35) { // LDC1 (write double)
3653     emit_writeword_indexed(th,4,temp);
3654     emit_writeword_indexed(tl,0,temp);
3655   }
3656   //if(opcode[i]==0x39)
3657   /*if(opcode[i]==0x39||opcode[i]==0x31)
3658   {
3659     emit_pusha();
3660         emit_readword((int)&last_count,ECX);
3661         if(get_reg(i_regs->regmap,CCREG)<0)
3662           emit_loadreg(CCREG,HOST_CCREG);
3663         emit_add(HOST_CCREG,ECX,HOST_CCREG);
3664         emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3665         emit_writeword(HOST_CCREG,(int)&Count);
3666     emit_call((int)memdebug);
3667     emit_popa();
3668   }/**/
3669 #else
3670   cop1_unusable(i, i_regs);
3671 #endif
3672 }
3673
3674 void c2ls_assemble(int i,struct regstat *i_regs)
3675 {
3676   int s,tl;
3677   int ar;
3678   int offset;
3679   int memtarget=0,c=0;
3680   int jaddr,jaddr2=0,jaddr3,type;
3681   int agr=AGEN1+(i&1);
3682   u_int hr,reglist=0;
3683   u_int copr=(source[i]>>16)&0x1f;
3684   s=get_reg(i_regs->regmap,rs1[i]);
3685   tl=get_reg(i_regs->regmap,FTEMP);
3686   offset=imm[i];
3687   assert(rs1[i]>0);
3688   assert(tl>=0);
3689   assert(!using_tlb);
3690
3691   for(hr=0;hr<HOST_REGS;hr++) {
3692     if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3693   }
3694   if(i_regs->regmap[HOST_CCREG]==CCREG)
3695     reglist&=~(1<<HOST_CCREG);
3696
3697   // get the address
3698   if (opcode[i]==0x3a) { // SWC2
3699     ar=get_reg(i_regs->regmap,agr);
3700     if(ar<0) ar=get_reg(i_regs->regmap,-1);
3701     reglist|=1<<ar;
3702   } else { // LWC2
3703     ar=tl;
3704   }
3705   if(s>=0) c=(i_regs->wasconst>>s)&1;
3706   memtarget=c&&(((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE);
3707   if (!offset&&!c&&s>=0) ar=s;
3708   assert(ar>=0);
3709
3710   if (opcode[i]==0x3a) { // SWC2
3711     cop2_get_dreg(copr,tl,HOST_TEMPREG);
3712     type=STOREW_STUB;
3713   }
3714   else
3715     type=LOADW_STUB;
3716
3717   if(c&&!memtarget) {
3718     jaddr2=(int)out;
3719     emit_jmp(0); // inline_readstub/inline_writestub?
3720   }
3721   else {
3722     if(!c) {
3723       emit_cmpimm(offset||c||s<0?ar:s,RAM_SIZE);
3724       jaddr2=(int)out;
3725       emit_jno(0);
3726     }
3727     if (opcode[i]==0x32) { // LWC2
3728       #ifdef HOST_IMM_ADDR32
3729       if(c) emit_readword_tlb(constmap[i][s]+offset,-1,tl);
3730       else
3731       #endif
3732       emit_readword_indexed(0,ar,tl);
3733     }
3734     if (opcode[i]==0x3a) { // SWC2
3735       #ifdef DESTRUCTIVE_SHIFT
3736       if(!offset&&!c&&s>=0) emit_mov(s,ar);
3737       #endif
3738       emit_writeword_indexed(tl,0,ar);
3739     }
3740   }
3741   if(jaddr2)
3742     add_stub(type,jaddr2,(int)out,i,ar,(int)i_regs,ccadj[i],reglist);
3743   if (opcode[i]==0x3a) { // SWC2
3744 #if defined(HOST_IMM8)
3745     int ir=get_reg(i_regs->regmap,INVCP);
3746     assert(ir>=0);
3747     emit_cmpmem_indexedsr12_reg(ir,ar,1);
3748 #else
3749     emit_cmpmem_indexedsr12_imm((int)invalid_code,ar,1);
3750 #endif
3751     #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3752     emit_callne(invalidate_addr_reg[ar]);
3753     #else
3754     jaddr3=(int)out;
3755     emit_jne(0);
3756     add_stub(INVCODE_STUB,jaddr3,(int)out,reglist|(1<<HOST_CCREG),ar,0,0,0);
3757     #endif
3758   }
3759   if (opcode[i]==0x32) { // LWC2
3760     cop2_put_dreg(copr,tl,HOST_TEMPREG);
3761   }
3762 }
3763
3764 #ifndef multdiv_assemble
3765 void multdiv_assemble(int i,struct regstat *i_regs)
3766 {
3767   printf("Need multdiv_assemble for this architecture.\n");
3768   exit(1);
3769 }
3770 #endif
3771
3772 void mov_assemble(int i,struct regstat *i_regs)
3773 {
3774   //if(opcode2[i]==0x10||opcode2[i]==0x12) { // MFHI/MFLO
3775   //if(opcode2[i]==0x11||opcode2[i]==0x13) { // MTHI/MTLO
3776   if(rt1[i]) {
3777     signed char sh,sl,th,tl;
3778     th=get_reg(i_regs->regmap,rt1[i]|64);
3779     tl=get_reg(i_regs->regmap,rt1[i]);
3780     //assert(tl>=0);
3781     if(tl>=0) {
3782       sh=get_reg(i_regs->regmap,rs1[i]|64);
3783       sl=get_reg(i_regs->regmap,rs1[i]);
3784       if(sl>=0) emit_mov(sl,tl);
3785       else emit_loadreg(rs1[i],tl);
3786       if(th>=0) {
3787         if(sh>=0) emit_mov(sh,th);
3788         else emit_loadreg(rs1[i]|64,th);
3789       }
3790     }
3791   }
3792 }
3793
3794 #ifndef fconv_assemble
3795 void fconv_assemble(int i,struct regstat *i_regs)
3796 {
3797   printf("Need fconv_assemble for this architecture.\n");
3798   exit(1);
3799 }
3800 #endif
3801
3802 #if 0
3803 void float_assemble(int i,struct regstat *i_regs)
3804 {
3805   printf("Need float_assemble for this architecture.\n");
3806   exit(1);
3807 }
3808 #endif
3809
3810 void syscall_assemble(int i,struct regstat *i_regs)
3811 {
3812   signed char ccreg=get_reg(i_regs->regmap,CCREG);
3813   assert(ccreg==HOST_CCREG);
3814   assert(!is_delayslot);
3815   emit_movimm(start+i*4,EAX); // Get PC
3816   emit_addimm(HOST_CCREG,CLOCK_DIVIDER*ccadj[i],HOST_CCREG); // CHECK: is this right?  There should probably be an extra cycle...
3817   emit_jmp((int)jump_syscall_hle); // XXX
3818 }
3819
3820 void hlecall_assemble(int i,struct regstat *i_regs)
3821 {
3822   signed char ccreg=get_reg(i_regs->regmap,CCREG);
3823   assert(ccreg==HOST_CCREG);
3824   assert(!is_delayslot);
3825   emit_movimm(start+i*4+4,0); // Get PC
3826   emit_movimm((int)psxHLEt[source[i]&7],1);
3827   emit_addimm(HOST_CCREG,CLOCK_DIVIDER*ccadj[i],HOST_CCREG); // XXX
3828   emit_jmp((int)jump_hlecall);
3829 }
3830
3831 void intcall_assemble(int i,struct regstat *i_regs)
3832 {
3833   signed char ccreg=get_reg(i_regs->regmap,CCREG);
3834   assert(ccreg==HOST_CCREG);
3835   assert(!is_delayslot);
3836   emit_movimm(start+i*4,0); // Get PC
3837   emit_addimm(HOST_CCREG,CLOCK_DIVIDER*ccadj[i],HOST_CCREG);
3838   emit_jmp((int)jump_intcall);
3839 }
3840
3841 void ds_assemble(int i,struct regstat *i_regs)
3842 {
3843   is_delayslot=1;
3844   switch(itype[i]) {
3845     case ALU:
3846       alu_assemble(i,i_regs);break;
3847     case IMM16:
3848       imm16_assemble(i,i_regs);break;
3849     case SHIFT:
3850       shift_assemble(i,i_regs);break;
3851     case SHIFTIMM:
3852       shiftimm_assemble(i,i_regs);break;
3853     case LOAD:
3854       load_assemble(i,i_regs);break;
3855     case LOADLR:
3856       loadlr_assemble(i,i_regs);break;
3857     case STORE:
3858       store_assemble(i,i_regs);break;
3859     case STORELR:
3860       storelr_assemble(i,i_regs);break;
3861     case COP0:
3862       cop0_assemble(i,i_regs);break;
3863     case COP1:
3864       cop1_assemble(i,i_regs);break;
3865     case C1LS:
3866       c1ls_assemble(i,i_regs);break;
3867     case COP2:
3868       cop2_assemble(i,i_regs);break;
3869     case C2LS:
3870       c2ls_assemble(i,i_regs);break;
3871     case C2OP:
3872       c2op_assemble(i,i_regs);break;
3873     case FCONV:
3874       fconv_assemble(i,i_regs);break;
3875     case FLOAT:
3876       float_assemble(i,i_regs);break;
3877     case FCOMP:
3878       fcomp_assemble(i,i_regs);break;
3879     case MULTDIV:
3880       multdiv_assemble(i,i_regs);break;
3881     case MOV:
3882       mov_assemble(i,i_regs);break;
3883     case SYSCALL:
3884     case HLECALL:
3885     case INTCALL:
3886     case SPAN:
3887     case UJUMP:
3888     case RJUMP:
3889     case CJUMP:
3890     case SJUMP:
3891     case FJUMP:
3892       printf("Jump in the delay slot.  This is probably a bug.\n");
3893   }
3894   is_delayslot=0;
3895 }
3896
3897 // Is the branch target a valid internal jump?
3898 int internal_branch(uint64_t i_is32,int addr)
3899 {
3900   if(addr&1) return 0; // Indirect (register) jump
3901   if(addr>=start && addr<start+slen*4-4)
3902   {
3903     int t=(addr-start)>>2;
3904     // Delay slots are not valid branch targets
3905     //if(t>0&&(itype[t-1]==RJUMP||itype[t-1]==UJUMP||itype[t-1]==CJUMP||itype[t-1]==SJUMP||itype[t-1]==FJUMP)) return 0;
3906     // 64 -> 32 bit transition requires a recompile
3907     /*if(is32[t]&~unneeded_reg_upper[t]&~i_is32)
3908     {
3909       if(requires_32bit[t]&~i_is32) printf("optimizable: no\n");
3910       else printf("optimizable: yes\n");
3911     }*/
3912     //if(is32[t]&~unneeded_reg_upper[t]&~i_is32) return 0;
3913 #ifndef FORCE32
3914     if(requires_32bit[t]&~i_is32) return 0;
3915     else
3916 #endif
3917       return 1;
3918   }
3919   return 0;
3920 }
3921
3922 #ifndef wb_invalidate
3923 void wb_invalidate(signed char pre[],signed char entry[],uint64_t dirty,uint64_t is32,
3924   uint64_t u,uint64_t uu)
3925 {
3926   int hr;
3927   for(hr=0;hr<HOST_REGS;hr++) {
3928     if(hr!=EXCLUDE_REG) {
3929       if(pre[hr]!=entry[hr]) {
3930         if(pre[hr]>=0) {
3931           if((dirty>>hr)&1) {
3932             if(get_reg(entry,pre[hr])<0) {
3933               if(pre[hr]<64) {
3934                 if(!((u>>pre[hr])&1)) {
3935                   emit_storereg(pre[hr],hr);
3936                   if( ((is32>>pre[hr])&1) && !((uu>>pre[hr])&1) ) {
3937                     emit_sarimm(hr,31,hr);
3938                     emit_storereg(pre[hr]|64,hr);
3939                   }
3940                 }
3941               }else{
3942                 if(!((uu>>(pre[hr]&63))&1) && !((is32>>(pre[hr]&63))&1)) {
3943                   emit_storereg(pre[hr],hr);
3944                 }
3945               }
3946             }
3947           }
3948         }
3949       }
3950     }
3951   }
3952   // Move from one register to another (no writeback)
3953   for(hr=0;hr<HOST_REGS;hr++) {
3954     if(hr!=EXCLUDE_REG) {
3955       if(pre[hr]!=entry[hr]) {
3956         if(pre[hr]>=0&&(pre[hr]&63)<TEMPREG) {
3957           int nr;
3958           if((nr=get_reg(entry,pre[hr]))>=0) {
3959             emit_mov(hr,nr);
3960           }
3961         }
3962       }
3963     }
3964   }
3965 }
3966 #endif
3967
3968 // Load the specified registers
3969 // This only loads the registers given as arguments because
3970 // we don't want to load things that will be overwritten
3971 void load_regs(signed char entry[],signed char regmap[],int is32,int rs1,int rs2)
3972 {
3973   int hr;
3974   // Load 32-bit regs
3975   for(hr=0;hr<HOST_REGS;hr++) {
3976     if(hr!=EXCLUDE_REG&&regmap[hr]>=0) {
3977       if(entry[hr]!=regmap[hr]) {
3978         if(regmap[hr]==rs1||regmap[hr]==rs2)
3979         {
3980           if(regmap[hr]==0) {
3981             emit_zeroreg(hr);
3982           }
3983           else
3984           {
3985             emit_loadreg(regmap[hr],hr);
3986           }
3987         }
3988       }
3989     }
3990   }
3991   //Load 64-bit regs
3992   for(hr=0;hr<HOST_REGS;hr++) {
3993     if(hr!=EXCLUDE_REG&&regmap[hr]>=0) {
3994       if(entry[hr]!=regmap[hr]) {
3995         if(regmap[hr]-64==rs1||regmap[hr]-64==rs2)
3996         {
3997           assert(regmap[hr]!=64);
3998           if((is32>>(regmap[hr]&63))&1) {
3999             int lr=get_reg(regmap,regmap[hr]-64);
4000             if(lr>=0)
4001               emit_sarimm(lr,31,hr);
4002             else
4003               emit_loadreg(regmap[hr],hr);
4004           }
4005           else
4006           {
4007             emit_loadreg(regmap[hr],hr);
4008           }
4009         }
4010       }
4011     }
4012   }
4013 }
4014
4015 // Load registers prior to the start of a loop
4016 // so that they are not loaded within the loop
4017 static void loop_preload(signed char pre[],signed char entry[])
4018 {
4019   int hr;
4020   for(hr=0;hr<HOST_REGS;hr++) {
4021     if(hr!=EXCLUDE_REG) {
4022       if(pre[hr]!=entry[hr]) {
4023         if(entry[hr]>=0) {
4024           if(get_reg(pre,entry[hr])<0) {
4025             assem_debug("loop preload:\n");
4026             //printf("loop preload: %d\n",hr);
4027             if(entry[hr]==0) {
4028               emit_zeroreg(hr);
4029             }
4030             else if(entry[hr]<TEMPREG)
4031             {
4032               emit_loadreg(entry[hr],hr);
4033             }
4034             else if(entry[hr]-64<TEMPREG)
4035             {
4036               emit_loadreg(entry[hr],hr);
4037             }
4038           }
4039         }
4040       }
4041     }
4042   }
4043 }
4044
4045 // Generate address for load/store instruction
4046 // goes to AGEN for writes, FTEMP for LOADLR and cop1/2 loads
4047 void address_generation(int i,struct regstat *i_regs,signed char entry[])
4048 {
4049   if(itype[i]==LOAD||itype[i]==LOADLR||itype[i]==STORE||itype[i]==STORELR||itype[i]==C1LS||itype[i]==C2LS) {
4050     int ra;
4051     int agr=AGEN1+(i&1);
4052     int mgr=MGEN1+(i&1);
4053     if(itype[i]==LOAD) {
4054       ra=get_reg(i_regs->regmap,rt1[i]);
4055       if(ra<0) ra=get_reg(i_regs->regmap,-1);
4056       assert(ra>=0);
4057     }
4058     if(itype[i]==LOADLR) {
4059       ra=get_reg(i_regs->regmap,FTEMP);
4060     }
4061     if(itype[i]==STORE||itype[i]==STORELR) {
4062       ra=get_reg(i_regs->regmap,agr);
4063       if(ra<0) ra=get_reg(i_regs->regmap,-1);
4064     }
4065     if(itype[i]==C1LS||itype[i]==C2LS) {
4066       if ((opcode[i]&0x3b)==0x31||(opcode[i]&0x3b)==0x32) // LWC1/LDC1/LWC2/LDC2
4067         ra=get_reg(i_regs->regmap,FTEMP);
4068       else { // SWC1/SDC1/SWC2/SDC2
4069         ra=get_reg(i_regs->regmap,agr);
4070         if(ra<0) ra=get_reg(i_regs->regmap,-1);
4071       }
4072     }
4073     int rs=get_reg(i_regs->regmap,rs1[i]);
4074     int rm=get_reg(i_regs->regmap,TLREG);
4075     if(ra>=0) {
4076       int offset=imm[i];
4077       int c=(i_regs->wasconst>>rs)&1;
4078       if(rs1[i]==0) {
4079         // Using r0 as a base address
4080         /*if(rm>=0) {
4081           if(!entry||entry[rm]!=mgr) {
4082             generate_map_const(offset,rm);
4083           } // else did it in the previous cycle
4084         }*/
4085         if(!entry||entry[ra]!=agr) {
4086           if (opcode[i]==0x22||opcode[i]==0x26) {
4087             emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR
4088           }else if (opcode[i]==0x1a||opcode[i]==0x1b) {
4089             emit_movimm(offset&0xFFFFFFF8,ra); // LDL/LDR
4090           }else{
4091             emit_movimm(offset,ra);
4092           }
4093         } // else did it in the previous cycle
4094       }
4095       else if(rs<0) {
4096         if(!entry||entry[ra]!=rs1[i])
4097           emit_loadreg(rs1[i],ra);
4098         //if(!entry||entry[ra]!=rs1[i])
4099         //  printf("poor load scheduling!\n");
4100       }
4101       else if(c) {
4102         if(rm>=0) {
4103           if(!entry||entry[rm]!=mgr) {
4104             if(itype[i]==STORE||itype[i]==STORELR||(opcode[i]&0x3b)==0x39||(opcode[i]&0x3b)==0x3a) {
4105               // Stores to memory go thru the mapper to detect self-modifying
4106               // code, loads don't.
4107               if((unsigned int)(constmap[i][rs]+offset)>=0xC0000000 ||
4108                  (unsigned int)(constmap[i][rs]+offset)<0x80000000+RAM_SIZE )
4109                 generate_map_const(constmap[i][rs]+offset,rm);
4110             }else{
4111               if((signed int)(constmap[i][rs]+offset)>=(signed int)0xC0000000)
4112                 generate_map_const(constmap[i][rs]+offset,rm);
4113             }
4114           }
4115         }
4116         if(rs1[i]!=rt1[i]||itype[i]!=LOAD) {
4117           if(!entry||entry[ra]!=agr) {
4118             if (opcode[i]==0x22||opcode[i]==0x26) {
4119               emit_movimm((constmap[i][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR
4120             }else if (opcode[i]==0x1a||opcode[i]==0x1b) {
4121               emit_movimm((constmap[i][rs]+offset)&0xFFFFFFF8,ra); // LDL/LDR
4122             }else{
4123               #ifdef HOST_IMM_ADDR32
4124               if((itype[i]!=LOAD&&(opcode[i]&0x3b)!=0x31&&(opcode[i]&0x3b)!=0x32) || // LWC1/LDC1/LWC2/LDC2
4125                  (using_tlb&&((signed int)constmap[i][rs]+offset)>=(signed int)0xC0000000))
4126               #endif
4127               emit_movimm(constmap[i][rs]+offset,ra);
4128             }
4129           } // else did it in the previous cycle
4130         } // else load_consts already did it
4131       }
4132       if(offset&&!c&&rs1[i]) {
4133         if(rs>=0) {
4134           emit_addimm(rs,offset,ra);
4135         }else{
4136           emit_addimm(ra,offset,ra);
4137         }
4138       }
4139     }
4140   }
4141   // Preload constants for next instruction
4142   if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS||itype[i+1]==C2LS) {
4143     int agr,ra;
4144     #ifndef HOST_IMM_ADDR32
4145     // Mapper entry
4146     agr=MGEN1+((i+1)&1);
4147     ra=get_reg(i_regs->regmap,agr);
4148     if(ra>=0) {
4149       int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
4150       int offset=imm[i+1];
4151       int c=(regs[i+1].wasconst>>rs)&1;
4152       if(c) {
4153         if(itype[i+1]==STORE||itype[i+1]==STORELR
4154            ||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a) { // SWC1/SDC1, SWC2/SDC2
4155           // Stores to memory go thru the mapper to detect self-modifying
4156           // code, loads don't.
4157           if((unsigned int)(constmap[i+1][rs]+offset)>=0xC0000000 ||
4158              (unsigned int)(constmap[i+1][rs]+offset)<0x80000000+RAM_SIZE )
4159             generate_map_const(constmap[i+1][rs]+offset,ra);
4160         }else{
4161           if((signed int)(constmap[i+1][rs]+offset)>=(signed int)0xC0000000)
4162             generate_map_const(constmap[i+1][rs]+offset,ra);
4163         }
4164       }
4165       /*else if(rs1[i]==0) {
4166         generate_map_const(offset,ra);
4167       }*/
4168     }
4169     #endif
4170     // Actual address
4171     agr=AGEN1+((i+1)&1);
4172     ra=get_reg(i_regs->regmap,agr);
4173     if(ra>=0) {
4174       int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
4175       int offset=imm[i+1];
4176       int c=(regs[i+1].wasconst>>rs)&1;
4177       if(c&&(rs1[i+1]!=rt1[i+1]||itype[i+1]!=LOAD)) {
4178         if (opcode[i+1]==0x22||opcode[i+1]==0x26) {
4179           emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR
4180         }else if (opcode[i+1]==0x1a||opcode[i+1]==0x1b) {
4181           emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFF8,ra); // LDL/LDR
4182         }else{
4183           #ifdef HOST_IMM_ADDR32
4184           if((itype[i+1]!=LOAD&&(opcode[i+1]&0x3b)!=0x31&&(opcode[i+1]&0x3b)!=0x32) || // LWC1/LDC1/LWC2/LDC2
4185              (using_tlb&&((signed int)constmap[i+1][rs]+offset)>=(signed int)0xC0000000))
4186           #endif
4187           emit_movimm(constmap[i+1][rs]+offset,ra);
4188         }
4189       }
4190       else if(rs1[i+1]==0) {
4191         // Using r0 as a base address
4192         if (opcode[i+1]==0x22||opcode[i+1]==0x26) {
4193           emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR
4194         }else if (opcode[i+1]==0x1a||opcode[i+1]==0x1b) {
4195           emit_movimm(offset&0xFFFFFFF8,ra); // LDL/LDR
4196         }else{
4197           emit_movimm(offset,ra);
4198         }
4199       }
4200     }
4201   }
4202 }
4203
4204 int get_final_value(int hr, int i, int *value)
4205 {
4206   int reg=regs[i].regmap[hr];
4207   while(i<slen-1) {
4208     if(regs[i+1].regmap[hr]!=reg) break;
4209     if(!((regs[i+1].isconst>>hr)&1)) break;
4210     if(bt[i+1]) break;
4211     i++;
4212   }
4213   if(i<slen-1) {
4214     if(itype[i]==UJUMP||itype[i]==RJUMP||itype[i]==CJUMP||itype[i]==SJUMP) {
4215       *value=constmap[i][hr];
4216       return 1;
4217     }
4218     if(!bt[i+1]) {
4219       if(itype[i+1]==UJUMP||itype[i+1]==RJUMP||itype[i+1]==CJUMP||itype[i+1]==SJUMP) {
4220         // Load in delay slot, out-of-order execution
4221         if(itype[i+2]==LOAD&&rs1[i+2]==reg&&rt1[i+2]==reg&&((regs[i+1].wasconst>>hr)&1))
4222         {
4223           #ifdef HOST_IMM_ADDR32
4224           if(!using_tlb||((signed int)constmap[i][hr]+imm[i+2])<(signed int)0xC0000000) return 0;
4225           #endif
4226           // Precompute load address
4227           *value=constmap[i][hr]+imm[i+2];
4228           return 1;
4229         }
4230       }
4231       if(itype[i+1]==LOAD&&rs1[i+1]==reg&&rt1[i+1]==reg)
4232       {
4233         #ifdef HOST_IMM_ADDR32
4234         if(!using_tlb||((signed int)constmap[i][hr]+imm[i+1])<(signed int)0xC0000000) return 0;
4235         #endif
4236         // Precompute load address
4237         *value=constmap[i][hr]+imm[i+1];
4238         //printf("c=%x imm=%x\n",(int)constmap[i][hr],imm[i+1]);
4239         return 1;
4240       }
4241     }
4242   }
4243   *value=constmap[i][hr];
4244   //printf("c=%x\n",(int)constmap[i][hr]);
4245   if(i==slen-1) return 1;
4246   if(reg<64) {
4247     return !((unneeded_reg[i+1]>>reg)&1);
4248   }else{
4249     return !((unneeded_reg_upper[i+1]>>reg)&1);
4250   }
4251 }
4252
4253 // Load registers with known constants
4254 void load_consts(signed char pre[],signed char regmap[],int is32,int i)
4255 {
4256   int hr;
4257   // Load 32-bit regs
4258   for(hr=0;hr<HOST_REGS;hr++) {
4259     if(hr!=EXCLUDE_REG&&regmap[hr]>=0) {
4260       //if(entry[hr]!=regmap[hr]) {
4261       if(i==0||!((regs[i-1].isconst>>hr)&1)||pre[hr]!=regmap[hr]||bt[i]) {
4262         if(((regs[i].isconst>>hr)&1)&&regmap[hr]<64&&regmap[hr]>0) {
4263           int value;
4264           if(get_final_value(hr,i,&value)) {
4265             if(value==0) {
4266               emit_zeroreg(hr);
4267             }
4268             else {
4269               emit_movimm(value,hr);
4270             }
4271           }
4272         }
4273       }
4274     }
4275   }
4276   // Load 64-bit regs
4277   for(hr=0;hr<HOST_REGS;hr++) {
4278     if(hr!=EXCLUDE_REG&&regmap[hr]>=0) {
4279       //if(entry[hr]!=regmap[hr]) {
4280       if(i==0||!((regs[i-1].isconst>>hr)&1)||pre[hr]!=regmap[hr]||bt[i]) {
4281         if(((regs[i].isconst>>hr)&1)&&regmap[hr]>64) {
4282           if((is32>>(regmap[hr]&63))&1) {
4283             int lr=get_reg(regmap,regmap[hr]-64);
4284             assert(lr>=0);
4285             emit_sarimm(lr,31,hr);
4286           }
4287           else
4288           {
4289             int value;
4290             if(get_final_value(hr,i,&value)) {
4291               if(value==0) {
4292                 emit_zeroreg(hr);
4293               }
4294               else {
4295                 emit_movimm(value,hr);
4296               }
4297             }
4298           }
4299         }
4300       }
4301     }
4302   }
4303 }
4304 void load_all_consts(signed char regmap[],int is32,u_int dirty,int i)
4305 {
4306   int hr;
4307   // Load 32-bit regs
4308   for(hr=0;hr<HOST_REGS;hr++) {
4309     if(hr!=EXCLUDE_REG&&regmap[hr]>=0&&((dirty>>hr)&1)) {
4310       if(((regs[i].isconst>>hr)&1)&&regmap[hr]<64&&regmap[hr]>0) {
4311         int value=constmap[i][hr];
4312         if(value==0) {
4313           emit_zeroreg(hr);
4314         }
4315         else {
4316           emit_movimm(value,hr);
4317         }
4318       }
4319     }
4320   }
4321   // Load 64-bit regs
4322   for(hr=0;hr<HOST_REGS;hr++) {
4323     if(hr!=EXCLUDE_REG&&regmap[hr]>=0&&((dirty>>hr)&1)) {
4324       if(((regs[i].isconst>>hr)&1)&&regmap[hr]>64) {
4325         if((is32>>(regmap[hr]&63))&1) {
4326           int lr=get_reg(regmap,regmap[hr]-64);
4327           assert(lr>=0);
4328           emit_sarimm(lr,31,hr);
4329         }
4330         else
4331         {
4332           int value=constmap[i][hr];
4333           if(value==0) {
4334             emit_zeroreg(hr);
4335           }
4336           else {
4337             emit_movimm(value,hr);
4338           }
4339         }
4340       }
4341     }
4342   }
4343 }
4344
4345 // Write out all dirty registers (except cycle count)
4346 void wb_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty)
4347 {
4348   int hr;
4349   for(hr=0;hr<HOST_REGS;hr++) {
4350     if(hr!=EXCLUDE_REG) {
4351       if(i_regmap[hr]>0) {
4352         if(i_regmap[hr]!=CCREG) {
4353           if((i_dirty>>hr)&1) {
4354             if(i_regmap[hr]<64) {
4355               emit_storereg(i_regmap[hr],hr);
4356 #ifndef FORCE32
4357               if( ((i_is32>>i_regmap[hr])&1) ) {
4358                 #ifdef DESTRUCTIVE_WRITEBACK
4359                 emit_sarimm(hr,31,hr);
4360                 emit_storereg(i_regmap[hr]|64,hr);
4361                 #else
4362                 emit_sarimm(hr,31,HOST_TEMPREG);
4363                 emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
4364                 #endif
4365               }
4366 #endif
4367             }else{
4368               if( !((i_is32>>(i_regmap[hr]&63))&1) ) {
4369                 emit_storereg(i_regmap[hr],hr);
4370               }
4371             }
4372           }
4373         }
4374       }
4375     }
4376   }
4377 }
4378 // Write out dirty registers that we need to reload (pair with load_needed_regs)
4379 // This writes the registers not written by store_regs_bt
4380 void wb_needed_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4381 {
4382   int hr;
4383   int t=(addr-start)>>2;
4384   for(hr=0;hr<HOST_REGS;hr++) {
4385     if(hr!=EXCLUDE_REG) {
4386       if(i_regmap[hr]>0) {
4387         if(i_regmap[hr]!=CCREG) {
4388           if(i_regmap[hr]==regs[t].regmap_entry[hr] && ((regs[t].dirty>>hr)&1) && !(((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) {
4389             if((i_dirty>>hr)&1) {
4390               if(i_regmap[hr]<64) {
4391                 emit_storereg(i_regmap[hr],hr);
4392 #ifndef FORCE32
4393                 if( ((i_is32>>i_regmap[hr])&1) ) {
4394                   #ifdef DESTRUCTIVE_WRITEBACK
4395                   emit_sarimm(hr,31,hr);
4396                   emit_storereg(i_regmap[hr]|64,hr);
4397                   #else
4398                   emit_sarimm(hr,31,HOST_TEMPREG);
4399                   emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
4400                   #endif
4401                 }
4402 #endif
4403               }else{
4404                 if( !((i_is32>>(i_regmap[hr]&63))&1) ) {
4405                   emit_storereg(i_regmap[hr],hr);
4406                 }
4407               }
4408             }
4409           }
4410         }
4411       }
4412     }
4413   }
4414 }
4415
4416 // Load all registers (except cycle count)
4417 void load_all_regs(signed char i_regmap[])
4418 {
4419   int hr;
4420   for(hr=0;hr<HOST_REGS;hr++) {
4421     if(hr!=EXCLUDE_REG) {
4422       if(i_regmap[hr]==0) {
4423         emit_zeroreg(hr);
4424       }
4425       else
4426       if(i_regmap[hr]>0 && i_regmap[hr]!=CCREG)
4427       {
4428         emit_loadreg(i_regmap[hr],hr);
4429       }
4430     }
4431   }
4432 }
4433
4434 // Load all current registers also needed by next instruction
4435 void load_needed_regs(signed char i_regmap[],signed char next_regmap[])
4436 {
4437   int hr;
4438   for(hr=0;hr<HOST_REGS;hr++) {
4439     if(hr!=EXCLUDE_REG) {
4440       if(get_reg(next_regmap,i_regmap[hr])>=0) {
4441         if(i_regmap[hr]==0) {
4442           emit_zeroreg(hr);
4443         }
4444         else
4445         if(i_regmap[hr]>0 && i_regmap[hr]!=CCREG)
4446         {
4447           emit_loadreg(i_regmap[hr],hr);
4448         }
4449       }
4450     }
4451   }
4452 }
4453
4454 // Load all regs, storing cycle count if necessary
4455 void load_regs_entry(int t)
4456 {
4457   int hr;
4458   if(is_ds[t]) emit_addimm(HOST_CCREG,CLOCK_DIVIDER,HOST_CCREG);
4459   else if(ccadj[t]) emit_addimm(HOST_CCREG,-ccadj[t]*CLOCK_DIVIDER,HOST_CCREG);
4460   if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) {
4461     emit_storereg(CCREG,HOST_CCREG);
4462   }
4463   // Load 32-bit regs
4464   for(hr=0;hr<HOST_REGS;hr++) {
4465     if(regs[t].regmap_entry[hr]>=0&&regs[t].regmap_entry[hr]<64) {
4466       if(regs[t].regmap_entry[hr]==0) {
4467         emit_zeroreg(hr);
4468       }
4469       else if(regs[t].regmap_entry[hr]!=CCREG)
4470       {
4471         emit_loadreg(regs[t].regmap_entry[hr],hr);
4472       }
4473     }
4474   }
4475   // Load 64-bit regs
4476   for(hr=0;hr<HOST_REGS;hr++) {
4477     if(regs[t].regmap_entry[hr]>=64) {
4478       assert(regs[t].regmap_entry[hr]!=64);
4479       if((regs[t].was32>>(regs[t].regmap_entry[hr]&63))&1) {
4480         int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64);
4481         if(lr<0) {
4482           emit_loadreg(regs[t].regmap_entry[hr],hr);
4483         }
4484         else
4485         {
4486           emit_sarimm(lr,31,hr);
4487         }
4488       }
4489       else
4490       {
4491         emit_loadreg(regs[t].regmap_entry[hr],hr);
4492       }
4493     }
4494   }
4495 }
4496
4497 // Store dirty registers prior to branch
4498 void store_regs_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4499 {
4500   if(internal_branch(i_is32,addr))
4501   {
4502     int t=(addr-start)>>2;
4503     int hr;
4504     for(hr=0;hr<HOST_REGS;hr++) {
4505       if(hr!=EXCLUDE_REG) {
4506         if(i_regmap[hr]>0 && i_regmap[hr]!=CCREG) {
4507           if(i_regmap[hr]!=regs[t].regmap_entry[hr] || !((regs[t].dirty>>hr)&1) || (((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) {
4508             if((i_dirty>>hr)&1) {
4509               if(i_regmap[hr]<64) {
4510                 if(!((unneeded_reg[t]>>i_regmap[hr])&1)) {
4511                   emit_storereg(i_regmap[hr],hr);
4512                   if( ((i_is32>>i_regmap[hr])&1) && !((unneeded_reg_upper[t]>>i_regmap[hr])&1) ) {
4513                     #ifdef DESTRUCTIVE_WRITEBACK
4514                     emit_sarimm(hr,31,hr);
4515                     emit_storereg(i_regmap[hr]|64,hr);
4516                     #else
4517                     emit_sarimm(hr,31,HOST_TEMPREG);
4518                     emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
4519                     #endif
4520                   }
4521                 }
4522               }else{
4523                 if( !((i_is32>>(i_regmap[hr]&63))&1) && !((unneeded_reg_upper[t]>>(i_regmap[hr]&63))&1) ) {
4524                   emit_storereg(i_regmap[hr],hr);
4525                 }
4526               }
4527             }
4528           }
4529         }
4530       }
4531     }
4532   }
4533   else
4534   {
4535     // Branch out of this block, write out all dirty regs
4536     wb_dirtys(i_regmap,i_is32,i_dirty);
4537   }
4538 }
4539
4540 // Load all needed registers for branch target
4541 void load_regs_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4542 {
4543   //if(addr>=start && addr<(start+slen*4))
4544   if(internal_branch(i_is32,addr))
4545   {
4546     int t=(addr-start)>>2;
4547     int hr;
4548     // Store the cycle count before loading something else
4549     if(i_regmap[HOST_CCREG]!=CCREG) {
4550       assert(i_regmap[HOST_CCREG]==-1);
4551     }
4552     if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) {
4553       emit_storereg(CCREG,HOST_CCREG);
4554     }
4555     // Load 32-bit regs
4556     for(hr=0;hr<HOST_REGS;hr++) {
4557       if(hr!=EXCLUDE_REG&&regs[t].regmap_entry[hr]>=0&&regs[t].regmap_entry[hr]<64) {
4558         #ifdef DESTRUCTIVE_WRITEBACK
4559         if(i_regmap[hr]!=regs[t].regmap_entry[hr] || ( !((regs[t].dirty>>hr)&1) && ((i_dirty>>hr)&1) && (((i_is32&~unneeded_reg_upper[t])>>i_regmap[hr])&1) ) || (((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) {
4560         #else
4561         if(i_regmap[hr]!=regs[t].regmap_entry[hr] ) {
4562         #endif
4563           if(regs[t].regmap_entry[hr]==0) {
4564             emit_zeroreg(hr);
4565           }
4566           else if(regs[t].regmap_entry[hr]!=CCREG)
4567           {
4568             emit_loadreg(regs[t].regmap_entry[hr],hr);
4569           }
4570         }
4571       }
4572     }
4573     //Load 64-bit regs
4574     for(hr=0;hr<HOST_REGS;hr++) {
4575       if(hr!=EXCLUDE_REG&&regs[t].regmap_entry[hr]>=64) {
4576         if(i_regmap[hr]!=regs[t].regmap_entry[hr]) {
4577           assert(regs[t].regmap_entry[hr]!=64);
4578           if((i_is32>>(regs[t].regmap_entry[hr]&63))&1) {
4579             int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64);
4580             if(lr<0) {
4581               emit_loadreg(regs[t].regmap_entry[hr],hr);
4582             }
4583             else
4584             {
4585               emit_sarimm(lr,31,hr);
4586             }
4587           }
4588           else
4589           {
4590             emit_loadreg(regs[t].regmap_entry[hr],hr);
4591           }
4592         }
4593         else if((i_is32>>(regs[t].regmap_entry[hr]&63))&1) {
4594           int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64);
4595           assert(lr>=0);
4596           emit_sarimm(lr,31,hr);
4597         }
4598       }
4599     }
4600   }
4601 }
4602
4603 int match_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4604 {
4605   if(addr>=start && addr<start+slen*4-4)
4606   {
4607     int t=(addr-start)>>2;
4608     int hr;
4609     if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) return 0;
4610     for(hr=0;hr<HOST_REGS;hr++)
4611     {
4612       if(hr!=EXCLUDE_REG)
4613       {
4614         if(i_regmap[hr]!=regs[t].regmap_entry[hr])
4615         {
4616           if(regs[t].regmap_entry[hr]!=-1)
4617           {
4618             return 0;
4619           }
4620           else
4621           if((i_dirty>>hr)&1)
4622           {
4623             if(i_regmap[hr]<64)
4624             {
4625               if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4626                 return 0;
4627             }
4628             else
4629             {
4630               if(!((unneeded_reg_upper[t]>>(i_regmap[hr]&63))&1))
4631                 return 0;
4632             }
4633           }
4634         }
4635         else // Same register but is it 32-bit or dirty?
4636         if(i_regmap[hr]>=0)
4637         {
4638           if(!((regs[t].dirty>>hr)&1))
4639           {
4640             if((i_dirty>>hr)&1)
4641             {
4642               if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4643               {
4644                 //printf("%x: dirty no match\n",addr);
4645                 return 0;
4646               }
4647             }
4648           }
4649           if((((regs[t].was32^i_is32)&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)
4650           {
4651             //printf("%x: is32 no match\n",addr);
4652             return 0;
4653           }
4654         }
4655       }
4656     }
4657     //if(is32[t]&~unneeded_reg_upper[t]&~i_is32) return 0;
4658 #ifndef FORCE32
4659     if(requires_32bit[t]&~i_is32) return 0;
4660 #endif
4661     // Delay slots are not valid branch targets
4662     //if(t>0&&(itype[t-1]==RJUMP||itype[t-1]==UJUMP||itype[t-1]==CJUMP||itype[t-1]==SJUMP||itype[t-1]==FJUMP)) return 0;
4663     // Delay slots require additional processing, so do not match
4664     if(is_ds[t]) return 0;
4665   }
4666   else
4667   {
4668     int hr;
4669     for(hr=0;hr<HOST_REGS;hr++)
4670     {
4671       if(hr!=EXCLUDE_REG)
4672       {
4673         if(i_regmap[hr]>=0)
4674         {
4675           if(hr!=HOST_CCREG||i_regmap[hr]!=CCREG)
4676           {
4677             if((i_dirty>>hr)&1)
4678             {
4679               return 0;
4680             }
4681           }
4682         }
4683       }
4684     }
4685   }
4686   return 1;
4687 }
4688
4689 // Used when a branch jumps into the delay slot of another branch
4690 void ds_assemble_entry(int i)
4691 {
4692   int t=(ba[i]-start)>>2;
4693   if(!instr_addr[t]) instr_addr[t]=(u_int)out;
4694   assem_debug("Assemble delay slot at %x\n",ba[i]);
4695   assem_debug("<->\n");
4696   if(regs[t].regmap_entry[HOST_CCREG]==CCREG&&regs[t].regmap[HOST_CCREG]!=CCREG)
4697     wb_register(CCREG,regs[t].regmap_entry,regs[t].wasdirty,regs[t].was32);
4698   load_regs(regs[t].regmap_entry,regs[t].regmap,regs[t].was32,rs1[t],rs2[t]);
4699   address_generation(t,&regs[t],regs[t].regmap_entry);
4700   if(itype[t]==STORE||itype[t]==STORELR||(opcode[t]&0x3b)==0x39||(opcode[t]&0x3b)==0x3a)
4701     load_regs(regs[t].regmap_entry,regs[t].regmap,regs[t].was32,INVCP,INVCP);
4702   cop1_usable=0;
4703   is_delayslot=0;
4704   switch(itype[t]) {
4705     case ALU:
4706       alu_assemble(t,&regs[t]);break;
4707     case IMM16:
4708       imm16_assemble(t,&regs[t]);break;
4709     case SHIFT:
4710       shift_assemble(t,&regs[t]);break;
4711     case SHIFTIMM:
4712       shiftimm_assemble(t,&regs[t]);break;
4713     case LOAD:
4714       load_assemble(t,&regs[t]);break;
4715     case LOADLR:
4716       loadlr_assemble(t,&regs[t]);break;
4717     case STORE:
4718       store_assemble(t,&regs[t]);break;
4719     case STORELR:
4720       storelr_assemble(t,&regs[t]);break;
4721     case COP0:
4722       cop0_assemble(t,&regs[t]);break;
4723     case COP1:
4724       cop1_assemble(t,&regs[t]);break;
4725     case C1LS:
4726       c1ls_assemble(t,&regs[t]);break;
4727     case COP2:
4728       cop2_assemble(t,&regs[t]);break;
4729     case C2LS:
4730       c2ls_assemble(t,&regs[t]);break;
4731     case C2OP:
4732       c2op_assemble(t,&regs[t]);break;
4733     case FCONV:
4734       fconv_assemble(t,&regs[t]);break;
4735     case FLOAT:
4736       float_assemble(t,&regs[t]);break;
4737     case FCOMP:
4738       fcomp_assemble(t,&regs[t]);break;
4739     case MULTDIV:
4740       multdiv_assemble(t,&regs[t]);break;
4741     case MOV:
4742       mov_assemble(t,&regs[t]);break;
4743     case SYSCALL:
4744     case HLECALL:
4745     case INTCALL:
4746     case SPAN:
4747     case UJUMP:
4748     case RJUMP:
4749     case CJUMP:
4750     case SJUMP:
4751     case FJUMP:
4752       printf("Jump in the delay slot.  This is probably a bug.\n");
4753   }
4754   store_regs_bt(regs[t].regmap,regs[t].is32,regs[t].dirty,ba[i]+4);
4755   load_regs_bt(regs[t].regmap,regs[t].is32,regs[t].dirty,ba[i]+4);
4756   if(internal_branch(regs[t].is32,ba[i]+4))
4757     assem_debug("branch: internal\n");
4758   else
4759     assem_debug("branch: external\n");
4760   assert(internal_branch(regs[t].is32,ba[i]+4));
4761   add_to_linker((int)out,ba[i]+4,internal_branch(regs[t].is32,ba[i]+4));
4762   emit_jmp(0);
4763 }
4764
4765 void do_cc(int i,signed char i_regmap[],int *adj,int addr,int taken,int invert)
4766 {
4767   int count;
4768   int jaddr;
4769   int idle=0;
4770   if(itype[i]==RJUMP)
4771   {
4772     *adj=0;
4773   }
4774   //if(ba[i]>=start && ba[i]<(start+slen*4))
4775   if(internal_branch(branch_regs[i].is32,ba[i]))
4776   {
4777     int t=(ba[i]-start)>>2;
4778     if(is_ds[t]) *adj=-1; // Branch into delay slot adds an extra cycle
4779     else *adj=ccadj[t];
4780   }
4781   else
4782   {
4783     *adj=0;
4784   }
4785   count=ccadj[i];
4786   if(taken==TAKEN && i==(ba[i]-start)>>2 && source[i+1]==0) {
4787     // Idle loop
4788     if(count&1) emit_addimm_and_set_flags(2*(count+2),HOST_CCREG);
4789     idle=(int)out;
4790     //emit_subfrommem(&idlecount,HOST_CCREG); // Count idle cycles
4791     emit_andimm(HOST_CCREG,3,HOST_CCREG);
4792     jaddr=(int)out;
4793     emit_jmp(0);
4794   }
4795   else if(*adj==0||invert) {
4796     emit_addimm_and_set_flags(CLOCK_DIVIDER*(count+2),HOST_CCREG);
4797     jaddr=(int)out;
4798     emit_jns(0);
4799   }
4800   else
4801   {
4802     emit_cmpimm(HOST_CCREG,-2*(count+2));
4803     jaddr=(int)out;
4804     emit_jns(0);
4805   }
4806   add_stub(CC_STUB,jaddr,idle?idle:(int)out,(*adj==0||invert||idle)?0:(count+2),i,addr,taken,0);
4807 }
4808
4809 void do_ccstub(int n)
4810 {
4811   literal_pool(256);
4812   assem_debug("do_ccstub %x\n",start+stubs[n][4]*4);
4813   set_jump_target(stubs[n][1],(int)out);
4814   int i=stubs[n][4];
4815   if(stubs[n][6]==NULLDS) {
4816     // Delay slot instruction is nullified ("likely" branch)
4817     wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty);
4818   }
4819   else if(stubs[n][6]!=TAKEN) {
4820     wb_dirtys(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty);
4821   }
4822   else {
4823     if(internal_branch(branch_regs[i].is32,ba[i]))
4824       wb_needed_dirtys(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
4825   }
4826   if(stubs[n][5]!=-1)
4827   {
4828     // Save PC as return address
4829     emit_movimm(stubs[n][5],EAX);
4830     emit_writeword(EAX,(int)&pcaddr);
4831   }
4832   else
4833   {
4834     // Return address depends on which way the branch goes
4835     if(itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
4836     {
4837       int s1l=get_reg(branch_regs[i].regmap,rs1[i]);
4838       int s1h=get_reg(branch_regs[i].regmap,rs1[i]|64);
4839       int s2l=get_reg(branch_regs[i].regmap,rs2[i]);
4840       int s2h=get_reg(branch_regs[i].regmap,rs2[i]|64);
4841       if(rs1[i]==0)
4842       {
4843         s1l=s2l;s1h=s2h;
4844         s2l=s2h=-1;
4845       }
4846       else if(rs2[i]==0)
4847       {
4848         s2l=s2h=-1;
4849       }
4850       if((branch_regs[i].is32>>rs1[i])&(branch_regs[i].is32>>rs2[i])&1) {
4851         s1h=s2h=-1;
4852       }
4853       assert(s1l>=0);
4854       #ifdef DESTRUCTIVE_WRITEBACK
4855       if(rs1[i]) {
4856         if((branch_regs[i].dirty>>s1l)&(branch_regs[i].is32>>rs1[i])&1)
4857           emit_loadreg(rs1[i],s1l);
4858       }
4859       else {
4860         if((branch_regs[i].dirty>>s1l)&(branch_regs[i].is32>>rs2[i])&1)
4861           emit_loadreg(rs2[i],s1l);
4862       }
4863       if(s2l>=0)
4864         if((branch_regs[i].dirty>>s2l)&(branch_regs[i].is32>>rs2[i])&1)
4865           emit_loadreg(rs2[i],s2l);
4866       #endif
4867       int hr=0;
4868       int addr,alt,ntaddr;
4869       while(hr<HOST_REGS)
4870       {
4871         if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
4872            (branch_regs[i].regmap[hr]&63)!=rs1[i] &&
4873            (branch_regs[i].regmap[hr]&63)!=rs2[i] )
4874         {
4875           addr=hr++;break;
4876         }
4877         hr++;
4878       }
4879       while(hr<HOST_REGS)
4880       {
4881         if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
4882            (branch_regs[i].regmap[hr]&63)!=rs1[i] &&
4883            (branch_regs[i].regmap[hr]&63)!=rs2[i] )
4884         {
4885           alt=hr++;break;
4886         }
4887         hr++;
4888       }
4889       if((opcode[i]&0x2E)==6) // BLEZ/BGTZ needs another register
4890       {
4891         while(hr<HOST_REGS)
4892         {
4893           if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
4894              (branch_regs[i].regmap[hr]&63)!=rs1[i] &&
4895              (branch_regs[i].regmap[hr]&63)!=rs2[i] )
4896           {
4897             ntaddr=hr;break;
4898           }
4899           hr++;
4900         }
4901         assert(hr<HOST_REGS);
4902       }
4903       if((opcode[i]&0x2f)==4) // BEQ
4904       {
4905         #ifdef HAVE_CMOV_IMM
4906         if(s1h<0) {
4907           if(s2l>=0) emit_cmp(s1l,s2l);
4908           else emit_test(s1l,s1l);
4909           emit_cmov2imm_e_ne_compact(ba[i],start+i*4+8,addr);
4910         }
4911         else
4912         #endif
4913         {
4914           emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
4915           if(s1h>=0) {
4916             if(s2h>=0) emit_cmp(s1h,s2h);
4917             else emit_test(s1h,s1h);
4918             emit_cmovne_reg(alt,addr);
4919           }
4920           if(s2l>=0) emit_cmp(s1l,s2l);
4921           else emit_test(s1l,s1l);
4922           emit_cmovne_reg(alt,addr);
4923         }
4924       }
4925       if((opcode[i]&0x2f)==5) // BNE
4926       {
4927         #ifdef HAVE_CMOV_IMM
4928         if(s1h<0) {
4929           if(s2l>=0) emit_cmp(s1l,s2l);
4930           else emit_test(s1l,s1l);
4931           emit_cmov2imm_e_ne_compact(start+i*4+8,ba[i],addr);
4932         }
4933         else
4934         #endif
4935         {
4936           emit_mov2imm_compact(start+i*4+8,addr,ba[i],alt);
4937           if(s1h>=0) {
4938             if(s2h>=0) emit_cmp(s1h,s2h);
4939             else emit_test(s1h,s1h);
4940             emit_cmovne_reg(alt,addr);
4941           }
4942           if(s2l>=0) emit_cmp(s1l,s2l);
4943           else emit_test(s1l,s1l);
4944           emit_cmovne_reg(alt,addr);
4945         }
4946       }
4947       if((opcode[i]&0x2f)==6) // BLEZ
4948       {
4949         //emit_movimm(ba[i],alt);
4950         //emit_movimm(start+i*4+8,addr);
4951         emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
4952         emit_cmpimm(s1l,1);
4953         if(s1h>=0) emit_mov(addr,ntaddr);
4954         emit_cmovl_reg(alt,addr);
4955         if(s1h>=0) {
4956           emit_test(s1h,s1h);
4957           emit_cmovne_reg(ntaddr,addr);
4958           emit_cmovs_reg(alt,addr);
4959         }
4960       }
4961       if((opcode[i]&0x2f)==7) // BGTZ
4962       {
4963         //emit_movimm(ba[i],addr);
4964         //emit_movimm(start+i*4+8,ntaddr);
4965         emit_mov2imm_compact(ba[i],addr,start+i*4+8,ntaddr);
4966         emit_cmpimm(s1l,1);
4967         if(s1h>=0) emit_mov(addr,alt);
4968         emit_cmovl_reg(ntaddr,addr);
4969         if(s1h>=0) {
4970           emit_test(s1h,s1h);
4971           emit_cmovne_reg(alt,addr);
4972           emit_cmovs_reg(ntaddr,addr);
4973         }
4974       }
4975       if((opcode[i]==1)&&(opcode2[i]&0x2D)==0) // BLTZ
4976       {
4977         //emit_movimm(ba[i],alt);
4978         //emit_movimm(start+i*4+8,addr);
4979         emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
4980         if(s1h>=0) emit_test(s1h,s1h);
4981         else emit_test(s1l,s1l);
4982         emit_cmovs_reg(alt,addr);
4983       }
4984       if((opcode[i]==1)&&(opcode2[i]&0x2D)==1) // BGEZ
4985       {
4986         //emit_movimm(ba[i],addr);
4987         //emit_movimm(start+i*4+8,alt);
4988         emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
4989         if(s1h>=0) emit_test(s1h,s1h);
4990         else emit_test(s1l,s1l);
4991         emit_cmovs_reg(alt,addr);
4992       }
4993       if(opcode[i]==0x11 && opcode2[i]==0x08 ) {
4994         if(source[i]&0x10000) // BC1T
4995         {
4996           //emit_movimm(ba[i],alt);
4997           //emit_movimm(start+i*4+8,addr);
4998           emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
4999           emit_testimm(s1l,0x800000);
5000           emit_cmovne_reg(alt,addr);
5001         }
5002         else // BC1F
5003         {
5004           //emit_movimm(ba[i],addr);
5005           //emit_movimm(start+i*4+8,alt);
5006           emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
5007           emit_testimm(s1l,0x800000);
5008           emit_cmovne_reg(alt,addr);
5009         }
5010       }
5011       emit_writeword(addr,(int)&pcaddr);
5012     }
5013     else
5014     if(itype[i]==RJUMP)
5015     {
5016       int r=get_reg(branch_regs[i].regmap,rs1[i]);
5017       if(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]) {
5018         r=get_reg(branch_regs[i].regmap,RTEMP);
5019       }
5020       emit_writeword(r,(int)&pcaddr);
5021     }
5022     else {printf("Unknown branch type in do_ccstub\n");exit(1);}
5023   }
5024   // Update cycle count
5025   assert(branch_regs[i].regmap[HOST_CCREG]==CCREG||branch_regs[i].regmap[HOST_CCREG]==-1);
5026   if(stubs[n][3]) emit_addimm(HOST_CCREG,CLOCK_DIVIDER*stubs[n][3],HOST_CCREG);
5027   emit_call((int)cc_interrupt);
5028   if(stubs[n][3]) emit_addimm(HOST_CCREG,-CLOCK_DIVIDER*stubs[n][3],HOST_CCREG);
5029   if(stubs[n][6]==TAKEN) {
5030     if(internal_branch(branch_regs[i].is32,ba[i]))
5031       load_needed_regs(branch_regs[i].regmap,regs[(ba[i]-start)>>2].regmap_entry);
5032     else if(itype[i]==RJUMP) {
5033       if(get_reg(branch_regs[i].regmap,RTEMP)>=0)
5034         emit_readword((int)&pcaddr,get_reg(branch_regs[i].regmap,RTEMP));
5035       else
5036         emit_loadreg(rs1[i],get_reg(branch_regs[i].regmap,rs1[i]));
5037     }
5038   }else if(stubs[n][6]==NOTTAKEN) {
5039     if(i<slen-2) load_needed_regs(branch_regs[i].regmap,regmap_pre[i+2]);
5040     else load_all_regs(branch_regs[i].regmap);
5041   }else if(stubs[n][6]==NULLDS) {
5042     // Delay slot instruction is nullified ("likely" branch)
5043     if(i<slen-2) load_needed_regs(regs[i].regmap,regmap_pre[i+2]);
5044     else load_all_regs(regs[i].regmap);
5045   }else{
5046     load_all_regs(branch_regs[i].regmap);
5047   }
5048   emit_jmp(stubs[n][2]); // return address
5049
5050   /* This works but uses a lot of memory...
5051   emit_readword((int)&last_count,ECX);
5052   emit_add(HOST_CCREG,ECX,EAX);
5053   emit_writeword(EAX,(int)&Count);
5054   emit_call((int)gen_interupt);
5055   emit_readword((int)&Count,HOST_CCREG);
5056   emit_readword((int)&next_interupt,EAX);
5057   emit_readword((int)&pending_exception,EBX);
5058   emit_writeword(EAX,(int)&last_count);
5059   emit_sub(HOST_CCREG,EAX,HOST_CCREG);
5060   emit_test(EBX,EBX);
5061   int jne_instr=(int)out;
5062   emit_jne(0);
5063   if(stubs[n][3]) emit_addimm(HOST_CCREG,-2*stubs[n][3],HOST_CCREG);
5064   load_all_regs(branch_regs[i].regmap);
5065   emit_jmp(stubs[n][2]); // return address
5066   set_jump_target(jne_instr,(int)out);
5067   emit_readword((int)&pcaddr,EAX);
5068   // Call get_addr_ht instead of doing the hash table here.
5069   // This code is executed infrequently and takes up a lot of space
5070   // so smaller is better.
5071   emit_storereg(CCREG,HOST_CCREG);
5072   emit_pushreg(EAX);
5073   emit_call((int)get_addr_ht);
5074   emit_loadreg(CCREG,HOST_CCREG);
5075   emit_addimm(ESP,4,ESP);
5076   emit_jmpreg(EAX);*/
5077 }
5078
5079 add_to_linker(int addr,int target,int ext)
5080 {
5081   link_addr[linkcount][0]=addr;
5082   link_addr[linkcount][1]=target;
5083   link_addr[linkcount][2]=ext;
5084   linkcount++;
5085 }
5086
5087 void ujump_assemble(int i,struct regstat *i_regs)
5088 {
5089   signed char *i_regmap=i_regs->regmap;
5090   if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
5091   address_generation(i+1,i_regs,regs[i].regmap_entry);
5092   #ifdef REG_PREFETCH
5093   int temp=get_reg(branch_regs[i].regmap,PTEMP);
5094   if(rt1[i]==31&&temp>=0)
5095   {
5096     int return_address=start+i*4+8;
5097     if(get_reg(branch_regs[i].regmap,31)>0)
5098     if(i_regmap[temp]==PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5099   }
5100   #endif
5101   ds_assemble(i+1,i_regs);
5102   uint64_t bc_unneeded=branch_regs[i].u;
5103   uint64_t bc_unneeded_upper=branch_regs[i].uu;
5104   bc_unneeded|=1|(1LL<<rt1[i]);
5105   bc_unneeded_upper|=1|(1LL<<rt1[i]);
5106   wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5107                 bc_unneeded,bc_unneeded_upper);
5108   load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5109   if(rt1[i]==31) {
5110     int rt;
5111     unsigned int return_address;
5112     assert(rt1[i+1]!=31);
5113     assert(rt2[i+1]!=31);
5114     rt=get_reg(branch_regs[i].regmap,31);
5115     assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5116     //assert(rt>=0);
5117     return_address=start+i*4+8;
5118     if(rt>=0) {
5119       #ifdef USE_MINI_HT
5120       if(internal_branch(branch_regs[i].is32,return_address)) {
5121         int temp=rt+1;
5122         if(temp==EXCLUDE_REG||temp>=HOST_REGS||
5123            branch_regs[i].regmap[temp]>=0)
5124         {
5125           temp=get_reg(branch_regs[i].regmap,-1);
5126         }
5127         #ifdef HOST_TEMPREG
5128         if(temp<0) temp=HOST_TEMPREG;
5129         #endif
5130         if(temp>=0) do_miniht_insert(return_address,rt,temp);
5131         else emit_movimm(return_address,rt);
5132       }
5133       else
5134       #endif
5135       {
5136         #ifdef REG_PREFETCH
5137         if(temp>=0)
5138         {
5139           if(i_regmap[temp]!=PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5140         }
5141         #endif
5142         emit_movimm(return_address,rt); // PC into link register
5143         #ifdef IMM_PREFETCH
5144         emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
5145         #endif
5146       }
5147     }
5148   }
5149   int cc,adj;
5150   cc=get_reg(branch_regs[i].regmap,CCREG);
5151   assert(cc==HOST_CCREG);
5152   store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5153   #ifdef REG_PREFETCH
5154   if(rt1[i]==31&&temp>=0) emit_prefetchreg(temp);
5155   #endif
5156   do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5157   if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5158   load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5159   if(internal_branch(branch_regs[i].is32,ba[i]))
5160     assem_debug("branch: internal\n");
5161   else
5162     assem_debug("branch: external\n");
5163   if(internal_branch(branch_regs[i].is32,ba[i])&&is_ds[(ba[i]-start)>>2]) {
5164     ds_assemble_entry(i);
5165   }
5166   else {
5167     add_to_linker((int)out,ba[i],internal_branch(branch_regs[i].is32,ba[i]));
5168     emit_jmp(0);
5169   }
5170 }
5171
5172 void rjump_assemble(int i,struct regstat *i_regs)
5173 {
5174   signed char *i_regmap=i_regs->regmap;
5175   int temp;
5176   int rs,cc,adj;
5177   rs=get_reg(branch_regs[i].regmap,rs1[i]);
5178   assert(rs>=0);
5179   if(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]) {
5180     // Delay slot abuse, make a copy of the branch address register
5181     temp=get_reg(branch_regs[i].regmap,RTEMP);
5182     assert(temp>=0);
5183     assert(regs[i].regmap[temp]==RTEMP);
5184     emit_mov(rs,temp);
5185     rs=temp;
5186   }
5187   address_generation(i+1,i_regs,regs[i].regmap_entry);
5188   #ifdef REG_PREFETCH
5189   if(rt1[i]==31)
5190   {
5191     if((temp=get_reg(branch_regs[i].regmap,PTEMP))>=0) {
5192       int return_address=start+i*4+8;
5193       if(i_regmap[temp]==PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5194     }
5195   }
5196   #endif
5197   #ifdef USE_MINI_HT
5198   if(rs1[i]==31) {
5199     int rh=get_reg(regs[i].regmap,RHASH);
5200     if(rh>=0) do_preload_rhash(rh);
5201   }
5202   #endif
5203   ds_assemble(i+1,i_regs);
5204   uint64_t bc_unneeded=branch_regs[i].u;
5205   uint64_t bc_unneeded_upper=branch_regs[i].uu;
5206   bc_unneeded|=1|(1LL<<rt1[i]);
5207   bc_unneeded_upper|=1|(1LL<<rt1[i]);
5208   bc_unneeded&=~(1LL<<rs1[i]);
5209   wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5210                 bc_unneeded,bc_unneeded_upper);
5211   load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],CCREG);
5212   if(rt1[i]!=0) {
5213     int rt,return_address;
5214     assert(rt1[i+1]!=rt1[i]);
5215     assert(rt2[i+1]!=rt1[i]);
5216     rt=get_reg(branch_regs[i].regmap,rt1[i]);
5217     assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5218     assert(rt>=0);
5219     return_address=start+i*4+8;
5220     #ifdef REG_PREFETCH
5221     if(temp>=0)
5222     {
5223       if(i_regmap[temp]!=PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5224     }
5225     #endif
5226     emit_movimm(return_address,rt); // PC into link register
5227     #ifdef IMM_PREFETCH
5228     emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
5229     #endif
5230   }
5231   cc=get_reg(branch_regs[i].regmap,CCREG);
5232   assert(cc==HOST_CCREG);
5233   #ifdef USE_MINI_HT
5234   int rh=get_reg(branch_regs[i].regmap,RHASH);
5235   int ht=get_reg(branch_regs[i].regmap,RHTBL);
5236   if(rs1[i]==31) {
5237     if(regs[i].regmap[rh]!=RHASH) do_preload_rhash(rh);
5238     do_preload_rhtbl(ht);
5239     do_rhash(rs,rh);
5240   }
5241   #endif
5242   store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,-1);
5243   #ifdef DESTRUCTIVE_WRITEBACK
5244   if((branch_regs[i].dirty>>rs)&(branch_regs[i].is32>>rs1[i])&1) {
5245     if(rs1[i]!=rt1[i+1]&&rs1[i]!=rt2[i+1]) {
5246       emit_loadreg(rs1[i],rs);
5247     }
5248   }
5249   #endif
5250   #ifdef REG_PREFETCH
5251   if(rt1[i]==31&&temp>=0) emit_prefetchreg(temp);
5252   #endif
5253   #ifdef USE_MINI_HT
5254   if(rs1[i]==31) {
5255     do_miniht_load(ht,rh);
5256   }
5257   #endif
5258   //do_cc(i,branch_regs[i].regmap,&adj,-1,TAKEN);
5259   //if(adj) emit_addimm(cc,2*(ccadj[i]+2-adj),cc); // ??? - Shouldn't happen
5260   //assert(adj==0);
5261   emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG);
5262   add_stub(CC_STUB,(int)out,jump_vaddr_reg[rs],0,i,-1,TAKEN,0);
5263   emit_jns(0);
5264   //load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,-1);
5265   #ifdef USE_MINI_HT
5266   if(rs1[i]==31) {
5267     do_miniht_jump(rs,rh,ht);
5268   }
5269   else
5270   #endif
5271   {
5272     //if(rs!=EAX) emit_mov(rs,EAX);
5273     //emit_jmp((int)jump_vaddr_eax);
5274     emit_jmp(jump_vaddr_reg[rs]);
5275   }
5276   /* Check hash table
5277   temp=!rs;
5278   emit_mov(rs,temp);
5279   emit_shrimm(rs,16,rs);
5280   emit_xor(temp,rs,rs);
5281   emit_movzwl_reg(rs,rs);
5282   emit_shlimm(rs,4,rs);
5283   emit_cmpmem_indexed((int)hash_table,rs,temp);
5284   emit_jne((int)out+14);
5285   emit_readword_indexed((int)hash_table+4,rs,rs);
5286   emit_jmpreg(rs);
5287   emit_cmpmem_indexed((int)hash_table+8,rs,temp);
5288   emit_addimm_no_flags(8,rs);
5289   emit_jeq((int)out-17);
5290   // No hit on hash table, call compiler
5291   emit_pushreg(temp);
5292 //DEBUG >
5293 #ifdef DEBUG_CYCLE_COUNT
5294   emit_readword((int)&last_count,ECX);
5295   emit_add(HOST_CCREG,ECX,HOST_CCREG);
5296   emit_readword((int)&next_interupt,ECX);
5297   emit_writeword(HOST_CCREG,(int)&Count);
5298   emit_sub(HOST_CCREG,ECX,HOST_CCREG);
5299   emit_writeword(ECX,(int)&last_count);
5300 #endif
5301 //DEBUG <
5302   emit_storereg(CCREG,HOST_CCREG);
5303   emit_call((int)get_addr);
5304   emit_loadreg(CCREG,HOST_CCREG);
5305   emit_addimm(ESP,4,ESP);
5306   emit_jmpreg(EAX);*/
5307   #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5308   if(rt1[i]!=31&&i<slen-2&&(((u_int)out)&7)) emit_mov(13,13);
5309   #endif
5310 }
5311
5312 void cjump_assemble(int i,struct regstat *i_regs)
5313 {
5314   signed char *i_regmap=i_regs->regmap;
5315   int cc;
5316   int match;
5317   match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5318   assem_debug("match=%d\n",match);
5319   int s1h,s1l,s2h,s2l;
5320   int prev_cop1_usable=cop1_usable;
5321   int unconditional=0,nop=0;
5322   int only32=0;
5323   int invert=0;
5324   int internal=internal_branch(branch_regs[i].is32,ba[i]);
5325   if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
5326   if(!match) invert=1;
5327   #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5328   if(i>(ba[i]-start)>>2) invert=1;
5329   #endif
5330
5331   if(ooo[i]) {
5332     s1l=get_reg(branch_regs[i].regmap,rs1[i]);
5333     s1h=get_reg(branch_regs[i].regmap,rs1[i]|64);
5334     s2l=get_reg(branch_regs[i].regmap,rs2[i]);
5335     s2h=get_reg(branch_regs[i].regmap,rs2[i]|64);
5336   }
5337   else {
5338     s1l=get_reg(i_regmap,rs1[i]);
5339     s1h=get_reg(i_regmap,rs1[i]|64);
5340     s2l=get_reg(i_regmap,rs2[i]);
5341     s2h=get_reg(i_regmap,rs2[i]|64);
5342   }
5343   if(rs1[i]==0&&rs2[i]==0)
5344   {
5345     if(opcode[i]&1) nop=1;
5346     else unconditional=1;
5347     //assert(opcode[i]!=5);
5348     //assert(opcode[i]!=7);
5349     //assert(opcode[i]!=0x15);
5350     //assert(opcode[i]!=0x17);
5351   }
5352   else if(rs1[i]==0)
5353   {
5354     s1l=s2l;s1h=s2h;
5355     s2l=s2h=-1;
5356     only32=(regs[i].was32>>rs2[i])&1;
5357   }
5358   else if(rs2[i]==0)
5359   {
5360     s2l=s2h=-1;
5361     only32=(regs[i].was32>>rs1[i])&1;
5362   }
5363   else {
5364     only32=(regs[i].was32>>rs1[i])&(regs[i].was32>>rs2[i])&1;
5365   }
5366
5367   if(ooo[i]) {
5368     // Out of order execution (delay slot first)
5369     //printf("OOOE\n");
5370     address_generation(i+1,i_regs,regs[i].regmap_entry);
5371     ds_assemble(i+1,i_regs);
5372     int adj;
5373     uint64_t bc_unneeded=branch_regs[i].u;
5374     uint64_t bc_unneeded_upper=branch_regs[i].uu;
5375     bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
5376     bc_unneeded_upper&=~((1LL<<us1[i])|(1LL<<us2[i]));
5377     bc_unneeded|=1;
5378     bc_unneeded_upper|=1;
5379     wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5380                   bc_unneeded,bc_unneeded_upper);
5381     load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],rs2[i]);
5382     load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5383     cc=get_reg(branch_regs[i].regmap,CCREG);
5384     assert(cc==HOST_CCREG);
5385     if(unconditional)
5386       store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5387     //do_cc(i,branch_regs[i].regmap,&adj,unconditional?ba[i]:-1,unconditional);
5388     //assem_debug("cycle count (adj)\n");
5389     if(unconditional) {
5390       do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5391       if(i!=(ba[i]-start)>>2 || source[i+1]!=0) {
5392         if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5393         load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5394         if(internal)
5395           assem_debug("branch: internal\n");
5396         else
5397           assem_debug("branch: external\n");
5398         if(internal&&is_ds[(ba[i]-start)>>2]) {
5399           ds_assemble_entry(i);
5400         }
5401         else {
5402           add_to_linker((int)out,ba[i],internal);
5403           emit_jmp(0);
5404         }
5405         #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5406         if(((u_int)out)&7) emit_addnop(0);
5407         #endif
5408       }
5409     }
5410     else if(nop) {
5411       emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc);
5412       int jaddr=(int)out;
5413       emit_jns(0);
5414       add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
5415     }
5416     else {
5417       int taken=0,nottaken=0,nottaken1=0;
5418       do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
5419       if(adj&&!invert) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5420       if(!only32)
5421       {
5422         assert(s1h>=0);
5423         if(opcode[i]==4) // BEQ
5424         {
5425           if(s2h>=0) emit_cmp(s1h,s2h);
5426           else emit_test(s1h,s1h);
5427           nottaken1=(int)out;
5428           emit_jne(1);
5429         }
5430         if(opcode[i]==5) // BNE
5431         {
5432           if(s2h>=0) emit_cmp(s1h,s2h);
5433           else emit_test(s1h,s1h);
5434           if(invert) taken=(int)out;
5435           else add_to_linker((int)out,ba[i],internal);
5436           emit_jne(0);
5437         }
5438         if(opcode[i]==6) // BLEZ
5439         {
5440           emit_test(s1h,s1h);
5441           if(invert) taken=(int)out;
5442           else add_to_linker((int)out,ba[i],internal);
5443           emit_js(0);
5444           nottaken1=(int)out;
5445           emit_jne(1);
5446         }
5447         if(opcode[i]==7) // BGTZ
5448         {
5449           emit_test(s1h,s1h);
5450           nottaken1=(int)out;
5451           emit_js(1);
5452           if(invert) taken=(int)out;
5453           else add_to_linker((int)out,ba[i],internal);
5454           emit_jne(0);
5455         }
5456       } // if(!only32)
5457
5458       //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5459       assert(s1l>=0);
5460       if(opcode[i]==4) // BEQ
5461       {
5462         if(s2l>=0) emit_cmp(s1l,s2l);
5463         else emit_test(s1l,s1l);
5464         if(invert){
5465           nottaken=(int)out;
5466           emit_jne(1);
5467         }else{
5468           add_to_linker((int)out,ba[i],internal);
5469           emit_jeq(0);
5470         }
5471       }
5472       if(opcode[i]==5) // BNE
5473       {
5474         if(s2l>=0) emit_cmp(s1l,s2l);
5475         else emit_test(s1l,s1l);
5476         if(invert){
5477           nottaken=(int)out;
5478           emit_jeq(1);
5479         }else{
5480           add_to_linker((int)out,ba[i],internal);
5481           emit_jne(0);
5482         }
5483       }
5484       if(opcode[i]==6) // BLEZ
5485       {
5486         emit_cmpimm(s1l,1);
5487         if(invert){
5488           nottaken=(int)out;
5489           emit_jge(1);
5490         }else{
5491           add_to_linker((int)out,ba[i],internal);
5492           emit_jl(0);
5493         }
5494       }
5495       if(opcode[i]==7) // BGTZ
5496       {
5497         emit_cmpimm(s1l,1);
5498         if(invert){
5499           nottaken=(int)out;
5500           emit_jl(1);
5501         }else{
5502           add_to_linker((int)out,ba[i],internal);
5503           emit_jge(0);
5504         }
5505       }
5506       if(invert) {
5507         if(taken) set_jump_target(taken,(int)out);
5508         #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5509         if(match&&(!internal||!is_ds[(ba[i]-start)>>2])) {
5510           if(adj) {
5511             emit_addimm(cc,-CLOCK_DIVIDER*adj,cc);
5512             add_to_linker((int)out,ba[i],internal);
5513           }else{
5514             emit_addnop(13);
5515             add_to_linker((int)out,ba[i],internal*2);
5516           }
5517           emit_jmp(0);
5518         }else
5519         #endif
5520         {
5521           if(adj) emit_addimm(cc,-CLOCK_DIVIDER*adj,cc);
5522           store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5523           load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5524           if(internal)
5525             assem_debug("branch: internal\n");
5526           else
5527             assem_debug("branch: external\n");
5528           if(internal&&is_ds[(ba[i]-start)>>2]) {
5529             ds_assemble_entry(i);
5530           }
5531           else {
5532             add_to_linker((int)out,ba[i],internal);
5533             emit_jmp(0);
5534           }
5535         }
5536         set_jump_target(nottaken,(int)out);
5537       }
5538
5539       if(nottaken1) set_jump_target(nottaken1,(int)out);
5540       if(adj) {
5541         if(!invert) emit_addimm(cc,CLOCK_DIVIDER*adj,cc);
5542       }
5543     } // (!unconditional)
5544   } // if(ooo)
5545   else
5546   {
5547     // In-order execution (branch first)
5548     //if(likely[i]) printf("IOL\n");
5549     //else
5550     //printf("IOE\n");
5551     int taken=0,nottaken=0,nottaken1=0;
5552     if(!unconditional&&!nop) {
5553       if(!only32)
5554       {
5555         assert(s1h>=0);
5556         if((opcode[i]&0x2f)==4) // BEQ
5557         {
5558           if(s2h>=0) emit_cmp(s1h,s2h);
5559           else emit_test(s1h,s1h);
5560           nottaken1=(int)out;
5561           emit_jne(2);
5562         }
5563         if((opcode[i]&0x2f)==5) // BNE
5564         {
5565           if(s2h>=0) emit_cmp(s1h,s2h);
5566           else emit_test(s1h,s1h);
5567           taken=(int)out;
5568           emit_jne(1);
5569         }
5570         if((opcode[i]&0x2f)==6) // BLEZ
5571         {
5572           emit_test(s1h,s1h);
5573           taken=(int)out;
5574           emit_js(1);
5575           nottaken1=(int)out;
5576           emit_jne(2);
5577         }
5578         if((opcode[i]&0x2f)==7) // BGTZ
5579         {
5580           emit_test(s1h,s1h);
5581           nottaken1=(int)out;
5582           emit_js(2);
5583           taken=(int)out;
5584           emit_jne(1);
5585         }
5586       } // if(!only32)
5587
5588       //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5589       assert(s1l>=0);
5590       if((opcode[i]&0x2f)==4) // BEQ
5591       {
5592         if(s2l>=0) emit_cmp(s1l,s2l);
5593         else emit_test(s1l,s1l);
5594         nottaken=(int)out;
5595         emit_jne(2);
5596       }
5597       if((opcode[i]&0x2f)==5) // BNE
5598       {
5599         if(s2l>=0) emit_cmp(s1l,s2l);
5600         else emit_test(s1l,s1l);
5601         nottaken=(int)out;
5602         emit_jeq(2);
5603       }
5604       if((opcode[i]&0x2f)==6) // BLEZ
5605       {
5606         emit_cmpimm(s1l,1);
5607         nottaken=(int)out;
5608         emit_jge(2);
5609       }
5610       if((opcode[i]&0x2f)==7) // BGTZ
5611       {
5612         emit_cmpimm(s1l,1);
5613         nottaken=(int)out;
5614         emit_jl(2);
5615       }
5616     } // if(!unconditional)
5617     int adj;
5618     uint64_t ds_unneeded=branch_regs[i].u;
5619     uint64_t ds_unneeded_upper=branch_regs[i].uu;
5620     ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
5621     ds_unneeded_upper&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
5622     if((~ds_unneeded_upper>>rt1[i+1])&1) ds_unneeded_upper&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
5623     ds_unneeded|=1;
5624     ds_unneeded_upper|=1;
5625     // branch taken
5626     if(!nop) {
5627       if(taken) set_jump_target(taken,(int)out);
5628       assem_debug("1:\n");
5629       wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5630                     ds_unneeded,ds_unneeded_upper);
5631       // load regs
5632       load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
5633       address_generation(i+1,&branch_regs[i],0);
5634       load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,INVCP);
5635       ds_assemble(i+1,&branch_regs[i]);
5636       cc=get_reg(branch_regs[i].regmap,CCREG);
5637       if(cc==-1) {
5638         emit_loadreg(CCREG,cc=HOST_CCREG);
5639         // CHECK: Is the following instruction (fall thru) allocated ok?
5640       }
5641       assert(cc==HOST_CCREG);
5642       store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5643       do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
5644       assem_debug("cycle count (adj)\n");
5645       if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5646       load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5647       if(internal)
5648         assem_debug("branch: internal\n");
5649       else
5650         assem_debug("branch: external\n");
5651       if(internal&&is_ds[(ba[i]-start)>>2]) {
5652         ds_assemble_entry(i);
5653       }
5654       else {
5655         add_to_linker((int)out,ba[i],internal);
5656         emit_jmp(0);
5657       }
5658     }
5659     // branch not taken
5660     cop1_usable=prev_cop1_usable;
5661     if(!unconditional) {
5662       if(nottaken1) set_jump_target(nottaken1,(int)out);
5663       set_jump_target(nottaken,(int)out);
5664       assem_debug("2:\n");
5665       if(!likely[i]) {
5666         wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5667                       ds_unneeded,ds_unneeded_upper);
5668         load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
5669         address_generation(i+1,&branch_regs[i],0);
5670         load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5671         ds_assemble(i+1,&branch_regs[i]);
5672       }
5673       cc=get_reg(branch_regs[i].regmap,CCREG);
5674       if(cc==-1&&!likely[i]) {
5675         // Cycle count isn't in a register, temporarily load it then write it out
5676         emit_loadreg(CCREG,HOST_CCREG);
5677         emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG);
5678         int jaddr=(int)out;
5679         emit_jns(0);
5680         add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
5681         emit_storereg(CCREG,HOST_CCREG);
5682       }
5683       else{
5684         cc=get_reg(i_regmap,CCREG);
5685         assert(cc==HOST_CCREG);
5686         emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc);
5687         int jaddr=(int)out;
5688         emit_jns(0);
5689         add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
5690       }
5691     }
5692   }
5693 }
5694
5695 void sjump_assemble(int i,struct regstat *i_regs)
5696 {
5697   signed char *i_regmap=i_regs->regmap;
5698   int cc;
5699   int match;
5700   match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5701   assem_debug("smatch=%d\n",match);
5702   int s1h,s1l;
5703   int prev_cop1_usable=cop1_usable;
5704   int unconditional=0,nevertaken=0;
5705   int only32=0;
5706   int invert=0;
5707   int internal=internal_branch(branch_regs[i].is32,ba[i]);
5708   if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
5709   if(!match) invert=1;
5710   #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5711   if(i>(ba[i]-start)>>2) invert=1;
5712   #endif
5713
5714   //if(opcode2[i]>=0x10) return; // FIXME (BxxZAL)
5715   //assert(opcode2[i]<0x10||rs1[i]==0); // FIXME (BxxZAL)
5716
5717   if(ooo[i]) {
5718     s1l=get_reg(branch_regs[i].regmap,rs1[i]);
5719     s1h=get_reg(branch_regs[i].regmap,rs1[i]|64);
5720   }
5721   else {
5722     s1l=get_reg(i_regmap,rs1[i]);
5723     s1h=get_reg(i_regmap,rs1[i]|64);
5724   }
5725   if(rs1[i]==0)
5726   {
5727     if(opcode2[i]&1) unconditional=1;
5728     else nevertaken=1;
5729     // These are never taken (r0 is never less than zero)
5730     //assert(opcode2[i]!=0);
5731     //assert(opcode2[i]!=2);
5732     //assert(opcode2[i]!=0x10);
5733     //assert(opcode2[i]!=0x12);
5734   }
5735   else {
5736     only32=(regs[i].was32>>rs1[i])&1;
5737   }
5738
5739   if(ooo[i]) {
5740     // Out of order execution (delay slot first)
5741     //printf("OOOE\n");
5742     address_generation(i+1,i_regs,regs[i].regmap_entry);
5743     ds_assemble(i+1,i_regs);
5744     int adj;
5745     uint64_t bc_unneeded=branch_regs[i].u;
5746     uint64_t bc_unneeded_upper=branch_regs[i].uu;
5747     bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
5748     bc_unneeded_upper&=~((1LL<<us1[i])|(1LL<<us2[i]));
5749     bc_unneeded|=1;
5750     bc_unneeded_upper|=1;
5751     wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5752                   bc_unneeded,bc_unneeded_upper);
5753     load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],rs1[i]);
5754     load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5755     if(rt1[i]==31) {
5756       int rt,return_address;
5757       rt=get_reg(branch_regs[i].regmap,31);
5758       assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5759       if(rt>=0) {
5760         // Save the PC even if the branch is not taken
5761         return_address=start+i*4+8;
5762         emit_movimm(return_address,rt); // PC into link register
5763         #ifdef IMM_PREFETCH
5764         if(!nevertaken) emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
5765         #endif
5766       }
5767     }
5768     cc=get_reg(branch_regs[i].regmap,CCREG);
5769     assert(cc==HOST_CCREG);
5770     if(unconditional)
5771       store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5772     //do_cc(i,branch_regs[i].regmap,&adj,unconditional?ba[i]:-1,unconditional);
5773     assem_debug("cycle count (adj)\n");
5774     if(unconditional) {
5775       do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5776       if(i!=(ba[i]-start)>>2 || source[i+1]!=0) {
5777         if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5778         load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5779         if(internal)
5780           assem_debug("branch: internal\n");
5781         else
5782           assem_debug("branch: external\n");
5783         if(internal&&is_ds[(ba[i]-start)>>2]) {
5784           ds_assemble_entry(i);
5785         }
5786         else {
5787           add_to_linker((int)out,ba[i],internal);
5788           emit_jmp(0);
5789         }
5790         #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5791         if(((u_int)out)&7) emit_addnop(0);
5792         #endif
5793       }
5794     }
5795     else if(nevertaken) {
5796       emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc);
5797       int jaddr=(int)out;
5798       emit_jns(0);
5799       add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
5800     }
5801     else {
5802       int nottaken=0;
5803       do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
5804       if(adj&&!invert) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5805       if(!only32)
5806       {
5807         assert(s1h>=0);
5808         if((opcode2[i]&0xf)==0) // BLTZ/BLTZAL
5809         {
5810           emit_test(s1h,s1h);
5811           if(invert){
5812             nottaken=(int)out;
5813             emit_jns(1);
5814           }else{
5815             add_to_linker((int)out,ba[i],internal);
5816             emit_js(0);
5817           }
5818         }
5819         if((opcode2[i]&0xf)==1) // BGEZ/BLTZAL
5820         {
5821           emit_test(s1h,s1h);
5822           if(invert){
5823             nottaken=(int)out;
5824             emit_js(1);
5825           }else{
5826             add_to_linker((int)out,ba[i],internal);
5827             emit_jns(0);
5828           }
5829         }
5830       } // if(!only32)
5831       else
5832       {
5833         assert(s1l>=0);
5834         if((opcode2[i]&0xf)==0) // BLTZ/BLTZAL
5835         {
5836           emit_test(s1l,s1l);
5837           if(invert){
5838             nottaken=(int)out;
5839             emit_jns(1);
5840           }else{
5841             add_to_linker((int)out,ba[i],internal);
5842             emit_js(0);
5843           }
5844         }
5845         if((opcode2[i]&0xf)==1) // BGEZ/BLTZAL
5846         {
5847           emit_test(s1l,s1l);
5848           if(invert){
5849             nottaken=(int)out;
5850             emit_js(1);
5851           }else{
5852             add_to_linker((int)out,ba[i],internal);
5853             emit_jns(0);
5854           }
5855         }
5856       } // if(!only32)
5857
5858       if(invert) {
5859         #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5860         if(match&&(!internal||!is_ds[(ba[i]-start)>>2])) {
5861           if(adj) {
5862             emit_addimm(cc,-CLOCK_DIVIDER*adj,cc);
5863             add_to_linker((int)out,ba[i],internal);
5864           }else{
5865             emit_addnop(13);
5866             add_to_linker((int)out,ba[i],internal*2);
5867           }
5868           emit_jmp(0);
5869         }else
5870         #endif
5871         {
5872           if(adj) emit_addimm(cc,-CLOCK_DIVIDER*adj,cc);
5873           store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5874           load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5875           if(internal)
5876             assem_debug("branch: internal\n");
5877           else
5878             assem_debug("branch: external\n");
5879           if(internal&&is_ds[(ba[i]-start)>>2]) {
5880             ds_assemble_entry(i);
5881           }
5882           else {
5883             add_to_linker((int)out,ba[i],internal);
5884             emit_jmp(0);
5885           }
5886         }
5887         set_jump_target(nottaken,(int)out);
5888       }
5889
5890       if(adj) {
5891         if(!invert) emit_addimm(cc,CLOCK_DIVIDER*adj,cc);
5892       }
5893     } // (!unconditional)
5894   } // if(ooo)
5895   else
5896   {
5897     // In-order execution (branch first)
5898     //printf("IOE\n");
5899     int nottaken=0;
5900     if(rt1[i]==31) {
5901       int rt,return_address;
5902       rt=get_reg(branch_regs[i].regmap,31);
5903       if(rt>=0) {
5904         // Save the PC even if the branch is not taken
5905         return_address=start+i*4+8;
5906         emit_movimm(return_address,rt); // PC into link register
5907         #ifdef IMM_PREFETCH
5908         emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
5909         #endif
5910       }
5911     }
5912     if(!unconditional) {
5913       //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5914       if(!only32)
5915       {
5916         assert(s1h>=0);
5917         if((opcode2[i]&0x0d)==0) // BLTZ/BLTZL/BLTZAL/BLTZALL
5918         {
5919           emit_test(s1h,s1h);
5920           nottaken=(int)out;
5921           emit_jns(1);
5922         }
5923         if((opcode2[i]&0x0d)==1) // BGEZ/BGEZL/BGEZAL/BGEZALL
5924         {
5925           emit_test(s1h,s1h);
5926           nottaken=(int)out;
5927           emit_js(1);
5928         }
5929       } // if(!only32)
5930       else
5931       {
5932         assert(s1l>=0);
5933         if((opcode2[i]&0x0d)==0) // BLTZ/BLTZL/BLTZAL/BLTZALL
5934         {
5935           emit_test(s1l,s1l);
5936           nottaken=(int)out;
5937           emit_jns(1);
5938         }
5939         if((opcode2[i]&0x0d)==1) // BGEZ/BGEZL/BGEZAL/BGEZALL
5940         {
5941           emit_test(s1l,s1l);
5942           nottaken=(int)out;
5943           emit_js(1);
5944         }
5945       }
5946     } // if(!unconditional)
5947     int adj;
5948     uint64_t ds_unneeded=branch_regs[i].u;
5949     uint64_t ds_unneeded_upper=branch_regs[i].uu;
5950     ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
5951     ds_unneeded_upper&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
5952     if((~ds_unneeded_upper>>rt1[i+1])&1) ds_unneeded_upper&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
5953     ds_unneeded|=1;
5954     ds_unneeded_upper|=1;
5955     // branch taken
5956     if(!nevertaken) {
5957       //assem_debug("1:\n");
5958       wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5959                     ds_unneeded,ds_unneeded_upper);
5960       // load regs
5961       load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
5962       address_generation(i+1,&branch_regs[i],0);
5963       load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,INVCP);
5964       ds_assemble(i+1,&branch_regs[i]);
5965       cc=get_reg(branch_regs[i].regmap,CCREG);
5966       if(cc==-1) {
5967         emit_loadreg(CCREG,cc=HOST_CCREG);
5968         // CHECK: Is the following instruction (fall thru) allocated ok?
5969       }
5970       assert(cc==HOST_CCREG);
5971       store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5972       do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
5973       assem_debug("cycle count (adj)\n");
5974       if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5975       load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5976       if(internal)
5977         assem_debug("branch: internal\n");
5978       else
5979         assem_debug("branch: external\n");
5980       if(internal&&is_ds[(ba[i]-start)>>2]) {
5981         ds_assemble_entry(i);
5982       }
5983       else {
5984         add_to_linker((int)out,ba[i],internal);
5985         emit_jmp(0);
5986       }
5987     }
5988     // branch not taken
5989     cop1_usable=prev_cop1_usable;
5990     if(!unconditional) {
5991       set_jump_target(nottaken,(int)out);
5992       assem_debug("1:\n");
5993       if(!likely[i]) {
5994         wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5995                       ds_unneeded,ds_unneeded_upper);
5996         load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
5997         address_generation(i+1,&branch_regs[i],0);
5998         load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5999         ds_assemble(i+1,&branch_regs[i]);
6000       }
6001       cc=get_reg(branch_regs[i].regmap,CCREG);
6002       if(cc==-1&&!likely[i]) {
6003         // Cycle count isn't in a register, temporarily load it then write it out
6004         emit_loadreg(CCREG,HOST_CCREG);
6005         emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG);
6006         int jaddr=(int)out;
6007         emit_jns(0);
6008         add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
6009         emit_storereg(CCREG,HOST_CCREG);
6010       }
6011       else{
6012         cc=get_reg(i_regmap,CCREG);
6013         assert(cc==HOST_CCREG);
6014         emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc);
6015         int jaddr=(int)out;
6016         emit_jns(0);
6017         add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
6018       }
6019     }
6020   }
6021 }
6022
6023 void fjump_assemble(int i,struct regstat *i_regs)
6024 {
6025   signed char *i_regmap=i_regs->regmap;
6026   int cc;
6027   int match;
6028   match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6029   assem_debug("fmatch=%d\n",match);
6030   int fs,cs;
6031   int eaddr;
6032   int invert=0;
6033   int internal=internal_branch(branch_regs[i].is32,ba[i]);
6034   if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
6035   if(!match) invert=1;
6036   #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
6037   if(i>(ba[i]-start)>>2) invert=1;
6038   #endif
6039
6040   if(ooo[i]) {
6041     fs=get_reg(branch_regs[i].regmap,FSREG);
6042     address_generation(i+1,i_regs,regs[i].regmap_entry); // Is this okay?
6043   }
6044   else {
6045     fs=get_reg(i_regmap,FSREG);
6046   }
6047
6048   // Check cop1 unusable
6049   if(!cop1_usable) {
6050     cs=get_reg(i_regmap,CSREG);
6051     assert(cs>=0);
6052     emit_testimm(cs,0x20000000);
6053     eaddr=(int)out;
6054     emit_jeq(0);
6055     add_stub(FP_STUB,eaddr,(int)out,i,cs,(int)i_regs,0,0);
6056     cop1_usable=1;
6057   }
6058
6059   if(ooo[i]) {
6060     // Out of order execution (delay slot first)
6061     //printf("OOOE\n");
6062     ds_assemble(i+1,i_regs);
6063     int adj;
6064     uint64_t bc_unneeded=branch_regs[i].u;
6065     uint64_t bc_unneeded_upper=branch_regs[i].uu;
6066     bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
6067     bc_unneeded_upper&=~((1LL<<us1[i])|(1LL<<us2[i]));
6068     bc_unneeded|=1;
6069     bc_unneeded_upper|=1;
6070     wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6071                   bc_unneeded,bc_unneeded_upper);
6072     load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],rs1[i]);
6073     load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
6074     cc=get_reg(branch_regs[i].regmap,CCREG);
6075     assert(cc==HOST_CCREG);
6076     do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
6077     assem_debug("cycle count (adj)\n");
6078     if(1) {
6079       int nottaken=0;
6080       if(adj&&!invert) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
6081       if(1) {
6082         assert(fs>=0);
6083         emit_testimm(fs,0x800000);
6084         if(source[i]&0x10000) // BC1T
6085         {
6086           if(invert){
6087             nottaken=(int)out;
6088             emit_jeq(1);
6089           }else{
6090             add_to_linker((int)out,ba[i],internal);
6091             emit_jne(0);
6092           }
6093         }
6094         else // BC1F
6095           if(invert){
6096             nottaken=(int)out;
6097             emit_jne(1);
6098           }else{
6099             add_to_linker((int)out,ba[i],internal);
6100             emit_jeq(0);
6101           }
6102         {
6103         }
6104       } // if(!only32)
6105
6106       if(invert) {
6107         if(adj) emit_addimm(cc,-CLOCK_DIVIDER*adj,cc);
6108         #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
6109         else if(match) emit_addnop(13);
6110         #endif
6111         store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6112         load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6113         if(internal)
6114           assem_debug("branch: internal\n");
6115         else
6116           assem_debug("branch: external\n");
6117         if(internal&&is_ds[(ba[i]-start)>>2]) {
6118           ds_assemble_entry(i);
6119         }
6120         else {
6121           add_to_linker((int)out,ba[i],internal);
6122           emit_jmp(0);
6123         }
6124         set_jump_target(nottaken,(int)out);
6125       }
6126
6127       if(adj) {
6128         if(!invert) emit_addimm(cc,CLOCK_DIVIDER*adj,cc);
6129       }
6130     } // (!unconditional)
6131   } // if(ooo)
6132   else
6133   {
6134     // In-order execution (branch first)
6135     //printf("IOE\n");
6136     int nottaken=0;
6137     if(1) {
6138       //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
6139       if(1) {
6140         assert(fs>=0);
6141         emit_testimm(fs,0x800000);
6142         if(source[i]&0x10000) // BC1T
6143         {
6144           nottaken=(int)out;
6145           emit_jeq(1);
6146         }
6147         else // BC1F
6148         {
6149           nottaken=(int)out;
6150           emit_jne(1);
6151         }
6152       }
6153     } // if(!unconditional)
6154     int adj;
6155     uint64_t ds_unneeded=branch_regs[i].u;
6156     uint64_t ds_unneeded_upper=branch_regs[i].uu;
6157     ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6158     ds_unneeded_upper&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6159     if((~ds_unneeded_upper>>rt1[i+1])&1) ds_unneeded_upper&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
6160     ds_unneeded|=1;
6161     ds_unneeded_upper|=1;
6162     // branch taken
6163     //assem_debug("1:\n");
6164     wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6165                   ds_unneeded,ds_unneeded_upper);
6166     // load regs
6167     load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
6168     address_generation(i+1,&branch_regs[i],0);
6169     load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,INVCP);
6170     ds_assemble(i+1,&branch_regs[i]);
6171     cc=get_reg(branch_regs[i].regmap,CCREG);
6172     if(cc==-1) {
6173       emit_loadreg(CCREG,cc=HOST_CCREG);
6174       // CHECK: Is the following instruction (fall thru) allocated ok?
6175     }
6176     assert(cc==HOST_CCREG);
6177     store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6178     do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
6179     assem_debug("cycle count (adj)\n");
6180     if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
6181     load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6182     if(internal)
6183       assem_debug("branch: internal\n");
6184     else
6185       assem_debug("branch: external\n");
6186     if(internal&&is_ds[(ba[i]-start)>>2]) {
6187       ds_assemble_entry(i);
6188     }
6189     else {
6190       add_to_linker((int)out,ba[i],internal);
6191       emit_jmp(0);
6192     }
6193
6194     // branch not taken
6195     if(1) { // <- FIXME (don't need this)
6196       set_jump_target(nottaken,(int)out);
6197       assem_debug("1:\n");
6198       if(!likely[i]) {
6199         wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6200                       ds_unneeded,ds_unneeded_upper);
6201         load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
6202         address_generation(i+1,&branch_regs[i],0);
6203         load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
6204         ds_assemble(i+1,&branch_regs[i]);
6205       }
6206       cc=get_reg(branch_regs[i].regmap,CCREG);
6207       if(cc==-1&&!likely[i]) {
6208         // Cycle count isn't in a register, temporarily load it then write it out
6209         emit_loadreg(CCREG,HOST_CCREG);
6210         emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG);
6211         int jaddr=(int)out;
6212         emit_jns(0);
6213         add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
6214         emit_storereg(CCREG,HOST_CCREG);
6215       }
6216       else{
6217         cc=get_reg(i_regmap,CCREG);
6218         assert(cc==HOST_CCREG);
6219         emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc);
6220         int jaddr=(int)out;
6221         emit_jns(0);
6222         add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
6223       }
6224     }
6225   }
6226 }
6227
6228 static void pagespan_assemble(int i,struct regstat *i_regs)
6229 {
6230   int s1l=get_reg(i_regs->regmap,rs1[i]);
6231   int s1h=get_reg(i_regs->regmap,rs1[i]|64);
6232   int s2l=get_reg(i_regs->regmap,rs2[i]);
6233   int s2h=get_reg(i_regs->regmap,rs2[i]|64);
6234   void *nt_branch=NULL;
6235   int taken=0;
6236   int nottaken=0;
6237   int unconditional=0;
6238   if(rs1[i]==0)
6239   {
6240     s1l=s2l;s1h=s2h;
6241     s2l=s2h=-1;
6242   }
6243   else if(rs2[i]==0)
6244   {
6245     s2l=s2h=-1;
6246   }
6247   if((i_regs->is32>>rs1[i])&(i_regs->is32>>rs2[i])&1) {
6248     s1h=s2h=-1;
6249   }
6250   int hr=0;
6251   int addr,alt,ntaddr;
6252   if(i_regs->regmap[HOST_BTREG]<0) {addr=HOST_BTREG;}
6253   else {
6254     while(hr<HOST_REGS)
6255     {
6256       if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
6257          (i_regs->regmap[hr]&63)!=rs1[i] &&
6258          (i_regs->regmap[hr]&63)!=rs2[i] )
6259       {
6260         addr=hr++;break;
6261       }
6262       hr++;
6263     }
6264   }
6265   while(hr<HOST_REGS)
6266   {
6267     if(hr!=EXCLUDE_REG && hr!=HOST_CCREG && hr!=HOST_BTREG &&
6268        (i_regs->regmap[hr]&63)!=rs1[i] &&
6269        (i_regs->regmap[hr]&63)!=rs2[i] )
6270     {
6271       alt=hr++;break;
6272     }
6273     hr++;
6274   }
6275   if((opcode[i]&0x2E)==6) // BLEZ/BGTZ needs another register
6276   {
6277     while(hr<HOST_REGS)
6278     {
6279       if(hr!=EXCLUDE_REG && hr!=HOST_CCREG && hr!=HOST_BTREG &&
6280          (i_regs->regmap[hr]&63)!=rs1[i] &&
6281          (i_regs->regmap[hr]&63)!=rs2[i] )
6282       {
6283         ntaddr=hr;break;
6284       }
6285       hr++;
6286     }
6287   }
6288   assert(hr<HOST_REGS);
6289   if((opcode[i]&0x2e)==4||opcode[i]==0x11) { // BEQ/BNE/BEQL/BNEL/BC1
6290     load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,CCREG,CCREG);
6291   }
6292   emit_addimm(HOST_CCREG,CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG);
6293   if(opcode[i]==2) // J
6294   {
6295     unconditional=1;
6296   }
6297   if(opcode[i]==3) // JAL
6298   {
6299     // TODO: mini_ht
6300     int rt=get_reg(i_regs->regmap,31);
6301     emit_movimm(start+i*4+8,rt);
6302     unconditional=1;
6303   }
6304   if(opcode[i]==0&&(opcode2[i]&0x3E)==8) // JR/JALR
6305   {
6306     emit_mov(s1l,addr);
6307     if(opcode2[i]==9) // JALR
6308     {
6309       int rt=get_reg(i_regs->regmap,rt1[i]);
6310       emit_movimm(start+i*4+8,rt);
6311     }
6312   }
6313   if((opcode[i]&0x3f)==4) // BEQ
6314   {
6315     if(rs1[i]==rs2[i])
6316     {
6317       unconditional=1;
6318     }
6319     else
6320     #ifdef HAVE_CMOV_IMM
6321     if(s1h<0) {
6322       if(s2l>=0) emit_cmp(s1l,s2l);
6323       else emit_test(s1l,s1l);
6324       emit_cmov2imm_e_ne_compact(ba[i],start+i*4+8,addr);
6325     }
6326     else
6327     #endif
6328     {
6329       assert(s1l>=0);
6330       emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
6331       if(s1h>=0) {
6332         if(s2h>=0) emit_cmp(s1h,s2h);
6333         else emit_test(s1h,s1h);
6334         emit_cmovne_reg(alt,addr);
6335       }
6336       if(s2l>=0) emit_cmp(s1l,s2l);
6337       else emit_test(s1l,s1l);
6338       emit_cmovne_reg(alt,addr);
6339     }
6340   }
6341   if((opcode[i]&0x3f)==5) // BNE
6342   {
6343     #ifdef HAVE_CMOV_IMM
6344     if(s1h<0) {
6345       if(s2l>=0) emit_cmp(s1l,s2l);
6346       else emit_test(s1l,s1l);
6347       emit_cmov2imm_e_ne_compact(start+i*4+8,ba[i],addr);
6348     }
6349     else
6350     #endif
6351     {
6352       assert(s1l>=0);
6353       emit_mov2imm_compact(start+i*4+8,addr,ba[i],alt);
6354       if(s1h>=0) {
6355         if(s2h>=0) emit_cmp(s1h,s2h);
6356         else emit_test(s1h,s1h);
6357         emit_cmovne_reg(alt,addr);
6358       }
6359       if(s2l>=0) emit_cmp(s1l,s2l);
6360       else emit_test(s1l,s1l);
6361       emit_cmovne_reg(alt,addr);
6362     }
6363   }
6364   if((opcode[i]&0x3f)==0x14) // BEQL
6365   {
6366     if(s1h>=0) {
6367       if(s2h>=0) emit_cmp(s1h,s2h);
6368       else emit_test(s1h,s1h);
6369       nottaken=(int)out;
6370       emit_jne(0);
6371     }
6372     if(s2l>=0) emit_cmp(s1l,s2l);
6373     else emit_test(s1l,s1l);
6374     if(nottaken) set_jump_target(nottaken,(int)out);
6375     nottaken=(int)out;
6376     emit_jne(0);
6377   }
6378   if((opcode[i]&0x3f)==0x15) // BNEL
6379   {
6380     if(s1h>=0) {
6381       if(s2h>=0) emit_cmp(s1h,s2h);
6382       else emit_test(s1h,s1h);
6383       taken=(int)out;
6384       emit_jne(0);
6385     }
6386     if(s2l>=0) emit_cmp(s1l,s2l);
6387     else emit_test(s1l,s1l);
6388     nottaken=(int)out;
6389     emit_jeq(0);
6390     if(taken) set_jump_target(taken,(int)out);
6391   }
6392   if((opcode[i]&0x3f)==6) // BLEZ
6393   {
6394     emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
6395     emit_cmpimm(s1l,1);
6396     if(s1h>=0) emit_mov(addr,ntaddr);
6397     emit_cmovl_reg(alt,addr);
6398     if(s1h>=0) {
6399       emit_test(s1h,s1h);
6400       emit_cmovne_reg(ntaddr,addr);
6401       emit_cmovs_reg(alt,addr);
6402     }
6403   }
6404   if((opcode[i]&0x3f)==7) // BGTZ
6405   {
6406     emit_mov2imm_compact(ba[i],addr,start+i*4+8,ntaddr);
6407     emit_cmpimm(s1l,1);
6408     if(s1h>=0) emit_mov(addr,alt);
6409     emit_cmovl_reg(ntaddr,addr);
6410     if(s1h>=0) {
6411       emit_test(s1h,s1h);
6412       emit_cmovne_reg(alt,addr);
6413       emit_cmovs_reg(ntaddr,addr);
6414     }
6415   }
6416   if((opcode[i]&0x3f)==0x16) // BLEZL
6417   {
6418     assert((opcode[i]&0x3f)!=0x16);
6419   }
6420   if((opcode[i]&0x3f)==0x17) // BGTZL
6421   {
6422     assert((opcode[i]&0x3f)!=0x17);
6423   }
6424   assert(opcode[i]!=1); // BLTZ/BGEZ
6425
6426   //FIXME: Check CSREG
6427   if(opcode[i]==0x11 && opcode2[i]==0x08 ) {
6428     if((source[i]&0x30000)==0) // BC1F
6429     {
6430       emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
6431       emit_testimm(s1l,0x800000);
6432       emit_cmovne_reg(alt,addr);
6433     }
6434     if((source[i]&0x30000)==0x10000) // BC1T
6435     {
6436       emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
6437       emit_testimm(s1l,0x800000);
6438       emit_cmovne_reg(alt,addr);
6439     }
6440     if((source[i]&0x30000)==0x20000) // BC1FL
6441     {
6442       emit_testimm(s1l,0x800000);
6443       nottaken=(int)out;
6444       emit_jne(0);
6445     }
6446     if((source[i]&0x30000)==0x30000) // BC1TL
6447     {
6448       emit_testimm(s1l,0x800000);
6449       nottaken=(int)out;
6450       emit_jeq(0);
6451     }
6452   }
6453
6454   assert(i_regs->regmap[HOST_CCREG]==CCREG);
6455   wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty);
6456   if(likely[i]||unconditional)
6457   {
6458     emit_movimm(ba[i],HOST_BTREG);
6459   }
6460   else if(addr!=HOST_BTREG)
6461   {
6462     emit_mov(addr,HOST_BTREG);
6463   }
6464   void *branch_addr=out;
6465   emit_jmp(0);
6466   int target_addr=start+i*4+5;
6467   void *stub=out;
6468   void *compiled_target_addr=check_addr(target_addr);
6469   emit_extjump_ds((int)branch_addr,target_addr);
6470   if(compiled_target_addr) {
6471     set_jump_target((int)branch_addr,(int)compiled_target_addr);
6472     add_link(target_addr,stub);
6473   }
6474   else set_jump_target((int)branch_addr,(int)stub);
6475   if(likely[i]) {
6476     // Not-taken path
6477     set_jump_target((int)nottaken,(int)out);
6478     wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty);
6479     void *branch_addr=out;
6480     emit_jmp(0);
6481     int target_addr=start+i*4+8;
6482     void *stub=out;
6483     void *compiled_target_addr=check_addr(target_addr);
6484     emit_extjump_ds((int)branch_addr,target_addr);
6485     if(compiled_target_addr) {
6486       set_jump_target((int)branch_addr,(int)compiled_target_addr);
6487       add_link(target_addr,stub);
6488     }
6489     else set_jump_target((int)branch_addr,(int)stub);
6490   }
6491 }
6492
6493 // Assemble the delay slot for the above
6494 static void pagespan_ds()
6495 {
6496   assem_debug("initial delay slot:\n");
6497   u_int vaddr=start+1;
6498   u_int page=get_page(vaddr);
6499   u_int vpage=get_vpage(vaddr);
6500   ll_add(jump_dirty+vpage,vaddr,(void *)out);
6501   do_dirty_stub_ds();
6502   ll_add(jump_in+page,vaddr,(void *)out);
6503   assert(regs[0].regmap_entry[HOST_CCREG]==CCREG);
6504   if(regs[0].regmap[HOST_CCREG]!=CCREG)
6505     wb_register(CCREG,regs[0].regmap_entry,regs[0].wasdirty,regs[0].was32);
6506   if(regs[0].regmap[HOST_BTREG]!=BTREG)
6507     emit_writeword(HOST_BTREG,(int)&branch_target);
6508   load_regs(regs[0].regmap_entry,regs[0].regmap,regs[0].was32,rs1[0],rs2[0]);
6509   address_generation(0,&regs[0],regs[0].regmap_entry);
6510   if(itype[0]==STORE||itype[0]==STORELR||(opcode[0]&0x3b)==0x39||(opcode[0]&0x3b)==0x3a)
6511     load_regs(regs[0].regmap_entry,regs[0].regmap,regs[0].was32,INVCP,INVCP);
6512   cop1_usable=0;
6513   is_delayslot=0;
6514   switch(itype[0]) {
6515     case ALU:
6516       alu_assemble(0,&regs[0]);break;
6517     case IMM16:
6518       imm16_assemble(0,&regs[0]);break;
6519     case SHIFT:
6520       shift_assemble(0,&regs[0]);break;
6521     case SHIFTIMM:
6522       shiftimm_assemble(0,&regs[0]);break;
6523     case LOAD:
6524       load_assemble(0,&regs[0]);break;
6525     case LOADLR:
6526       loadlr_assemble(0,&regs[0]);break;
6527     case STORE:
6528       store_assemble(0,&regs[0]);break;
6529     case STORELR:
6530       storelr_assemble(0,&regs[0]);break;
6531     case COP0:
6532       cop0_assemble(0,&regs[0]);break;
6533     case COP1:
6534       cop1_assemble(0,&regs[0]);break;
6535     case C1LS:
6536       c1ls_assemble(0,&regs[0]);break;
6537     case COP2:
6538       cop2_assemble(0,&regs[0]);break;
6539     case C2LS:
6540       c2ls_assemble(0,&regs[0]);break;
6541     case C2OP:
6542       c2op_assemble(0,&regs[0]);break;
6543     case FCONV:
6544       fconv_assemble(0,&regs[0]);break;
6545     case FLOAT:
6546       float_assemble(0,&regs[0]);break;
6547     case FCOMP:
6548       fcomp_assemble(0,&regs[0]);break;
6549     case MULTDIV:
6550       multdiv_assemble(0,&regs[0]);break;
6551     case MOV:
6552       mov_assemble(0,&regs[0]);break;
6553     case SYSCALL:
6554     case HLECALL:
6555     case INTCALL:
6556     case SPAN:
6557     case UJUMP:
6558     case RJUMP:
6559     case CJUMP:
6560     case SJUMP:
6561     case FJUMP:
6562       printf("Jump in the delay slot.  This is probably a bug.\n");
6563   }
6564   int btaddr=get_reg(regs[0].regmap,BTREG);
6565   if(btaddr<0) {
6566     btaddr=get_reg(regs[0].regmap,-1);
6567     emit_readword((int)&branch_target,btaddr);
6568   }
6569   assert(btaddr!=HOST_CCREG);
6570   if(regs[0].regmap[HOST_CCREG]!=CCREG) emit_loadreg(CCREG,HOST_CCREG);
6571 #ifdef HOST_IMM8
6572   emit_movimm(start+4,HOST_TEMPREG);
6573   emit_cmp(btaddr,HOST_TEMPREG);
6574 #else
6575   emit_cmpimm(btaddr,start+4);
6576 #endif
6577   int branch=(int)out;
6578   emit_jeq(0);
6579   store_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,-1);
6580   emit_jmp(jump_vaddr_reg[btaddr]);
6581   set_jump_target(branch,(int)out);
6582   store_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,start+4);
6583   load_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,start+4);
6584 }
6585
6586 // Basic liveness analysis for MIPS registers
6587 void unneeded_registers(int istart,int iend,int r)
6588 {
6589   int i;
6590   uint64_t u,uu,b,bu;
6591   uint64_t temp_u,temp_uu;
6592   uint64_t tdep;
6593   if(iend==slen-1) {
6594     u=1;uu=1;
6595   }else{
6596     u=unneeded_reg[iend+1];
6597     uu=unneeded_reg_upper[iend+1];
6598     u=1;uu=1;
6599   }
6600   for (i=iend;i>=istart;i--)
6601   {
6602     //printf("unneeded registers i=%d (%d,%d) r=%d\n",i,istart,iend,r);
6603     if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
6604     {
6605       // If subroutine call, flag return address as a possible branch target
6606       if(rt1[i]==31 && i<slen-2) bt[i+2]=1;
6607
6608       if(ba[i]<start || ba[i]>=(start+slen*4))
6609       {
6610         // Branch out of this block, flush all regs
6611         u=1;
6612         uu=1;
6613         /* Hexagon hack
6614         if(itype[i]==UJUMP&&rt1[i]==31)
6615         {
6616           uu=u=0x300C00F; // Discard at, v0-v1, t6-t9
6617         }
6618         if(itype[i]==RJUMP&&rs1[i]==31)
6619         {
6620           uu=u=0x300C0F3; // Discard at, a0-a3, t6-t9
6621         }
6622         if(start>0x80000400&&start<0x80000000+RAM_SIZE) {
6623           if(itype[i]==UJUMP&&rt1[i]==31)
6624           {
6625             //uu=u=0x30300FF0FLL; // Discard at, v0-v1, t0-t9, lo, hi
6626             uu=u=0x300FF0F; // Discard at, v0-v1, t0-t9
6627           }
6628           if(itype[i]==RJUMP&&rs1[i]==31)
6629           {
6630             //uu=u=0x30300FFF3LL; // Discard at, a0-a3, t0-t9, lo, hi
6631             uu=u=0x300FFF3; // Discard at, a0-a3, t0-t9
6632           }
6633         }*/
6634         branch_unneeded_reg[i]=u;
6635         branch_unneeded_reg_upper[i]=uu;
6636         // Merge in delay slot
6637         tdep=(~uu>>rt1[i+1])&1;
6638         u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6639         uu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6640         u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6641         uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6642         uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6643         u|=1;uu|=1;
6644         // If branch is "likely" (and conditional)
6645         // then we skip the delay slot on the fall-thru path
6646         if(likely[i]) {
6647           if(i<slen-1) {
6648             u&=unneeded_reg[i+2];
6649             uu&=unneeded_reg_upper[i+2];
6650           }
6651           else
6652           {
6653             u=1;
6654             uu=1;
6655           }
6656         }
6657       }
6658       else
6659       {
6660         // Internal branch, flag target
6661         bt[(ba[i]-start)>>2]=1;
6662         if(ba[i]<=start+i*4) {
6663           // Backward branch
6664           if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
6665           {
6666             // Unconditional branch
6667             temp_u=1;temp_uu=1;
6668           } else {
6669             // Conditional branch (not taken case)
6670             temp_u=unneeded_reg[i+2];
6671             temp_uu=unneeded_reg_upper[i+2];
6672           }
6673           // Merge in delay slot
6674           tdep=(~temp_uu>>rt1[i+1])&1;
6675           temp_u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6676           temp_uu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6677           temp_u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6678           temp_uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6679           temp_uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6680           temp_u|=1;temp_uu|=1;
6681           // If branch is "likely" (and conditional)
6682           // then we skip the delay slot on the fall-thru path
6683           if(likely[i]) {
6684             if(i<slen-1) {
6685               temp_u&=unneeded_reg[i+2];
6686               temp_uu&=unneeded_reg_upper[i+2];
6687             }
6688             else
6689             {
6690               temp_u=1;
6691               temp_uu=1;
6692             }
6693           }
6694           tdep=(~temp_uu>>rt1[i])&1;
6695           temp_u|=(1LL<<rt1[i])|(1LL<<rt2[i]);
6696           temp_uu|=(1LL<<rt1[i])|(1LL<<rt2[i]);
6697           temp_u&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
6698           temp_uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
6699           temp_uu&=~((tdep<<dep1[i])|(tdep<<dep2[i]));
6700           temp_u|=1;temp_uu|=1;
6701           unneeded_reg[i]=temp_u;
6702           unneeded_reg_upper[i]=temp_uu;
6703           // Only go three levels deep.  This recursion can take an
6704           // excessive amount of time if there are a lot of nested loops.
6705           if(r<2) {
6706             unneeded_registers((ba[i]-start)>>2,i-1,r+1);
6707           }else{
6708             unneeded_reg[(ba[i]-start)>>2]=1;
6709             unneeded_reg_upper[(ba[i]-start)>>2]=1;
6710           }
6711         } /*else*/ if(1) {
6712           if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
6713           {
6714             // Unconditional branch
6715             u=unneeded_reg[(ba[i]-start)>>2];
6716             uu=unneeded_reg_upper[(ba[i]-start)>>2];
6717             branch_unneeded_reg[i]=u;
6718             branch_unneeded_reg_upper[i]=uu;
6719         //u=1;
6720         //uu=1;
6721         //branch_unneeded_reg[i]=u;
6722         //branch_unneeded_reg_upper[i]=uu;
6723             // Merge in delay slot
6724             tdep=(~uu>>rt1[i+1])&1;
6725             u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6726             uu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6727             u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6728             uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6729             uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6730             u|=1;uu|=1;
6731           } else {
6732             // Conditional branch
6733             b=unneeded_reg[(ba[i]-start)>>2];
6734             bu=unneeded_reg_upper[(ba[i]-start)>>2];
6735             branch_unneeded_reg[i]=b;
6736             branch_unneeded_reg_upper[i]=bu;
6737         //b=1;
6738         //bu=1;
6739         //branch_unneeded_reg[i]=b;
6740         //branch_unneeded_reg_upper[i]=bu;
6741             // Branch delay slot
6742             tdep=(~uu>>rt1[i+1])&1;
6743             b|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6744             bu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6745             b&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6746             bu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6747             bu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6748             b|=1;bu|=1;
6749             // If branch is "likely" then we skip the
6750             // delay slot on the fall-thru path
6751             if(likely[i]) {
6752               u=b;
6753               uu=bu;
6754               if(i<slen-1) {
6755                 u&=unneeded_reg[i+2];
6756                 uu&=unneeded_reg_upper[i+2];
6757         //u=1;
6758         //uu=1;
6759               }
6760             } else {
6761               u&=b;
6762               uu&=bu;
6763         //u=1;
6764         //uu=1;
6765             }
6766             if(i<slen-1) {
6767               branch_unneeded_reg[i]&=unneeded_reg[i+2];
6768               branch_unneeded_reg_upper[i]&=unneeded_reg_upper[i+2];
6769         //branch_unneeded_reg[i]=1;
6770         //branch_unneeded_reg_upper[i]=1;
6771             } else {
6772               branch_unneeded_reg[i]=1;
6773               branch_unneeded_reg_upper[i]=1;
6774             }
6775           }
6776         }
6777       }
6778     }
6779     else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
6780     {
6781       // SYSCALL instruction (software interrupt)
6782       u=1;
6783       uu=1;
6784     }
6785     else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
6786     {
6787       // ERET instruction (return from interrupt)
6788       u=1;
6789       uu=1;
6790     }
6791     //u=uu=1; // DEBUG
6792     tdep=(~uu>>rt1[i])&1;
6793     // Written registers are unneeded
6794     u|=1LL<<rt1[i];
6795     u|=1LL<<rt2[i];
6796     uu|=1LL<<rt1[i];
6797     uu|=1LL<<rt2[i];
6798     // Accessed registers are needed
6799     u&=~(1LL<<rs1[i]);
6800     u&=~(1LL<<rs2[i]);
6801     uu&=~(1LL<<us1[i]);
6802     uu&=~(1LL<<us2[i]);
6803     // Source-target dependencies
6804     uu&=~(tdep<<dep1[i]);
6805     uu&=~(tdep<<dep2[i]);
6806     // R0 is always unneeded
6807     u|=1;uu|=1;
6808     // Save it
6809     unneeded_reg[i]=u;
6810     unneeded_reg_upper[i]=uu;
6811     /*
6812     printf("ur (%d,%d) %x: ",istart,iend,start+i*4);
6813     printf("U:");
6814     int r;
6815     for(r=1;r<=CCREG;r++) {
6816       if((unneeded_reg[i]>>r)&1) {
6817         if(r==HIREG) printf(" HI");
6818         else if(r==LOREG) printf(" LO");
6819         else printf(" r%d",r);
6820       }
6821     }
6822     printf(" UU:");
6823     for(r=1;r<=CCREG;r++) {
6824       if(((unneeded_reg_upper[i]&~unneeded_reg[i])>>r)&1) {
6825         if(r==HIREG) printf(" HI");
6826         else if(r==LOREG) printf(" LO");
6827         else printf(" r%d",r);
6828       }
6829     }
6830     printf("\n");*/
6831   }
6832 #ifdef FORCE32
6833   for (i=iend;i>=istart;i--)
6834   {
6835     unneeded_reg_upper[i]=branch_unneeded_reg_upper[i]=-1LL;
6836   }
6837 #endif
6838 }
6839
6840 // Identify registers which are likely to contain 32-bit values
6841 // This is used to predict whether any branches will jump to a
6842 // location with 64-bit values in registers.
6843 static void provisional_32bit()
6844 {
6845   int i,j;
6846   uint64_t is32=1;
6847   uint64_t lastbranch=1;
6848
6849   for(i=0;i<slen;i++)
6850   {
6851     if(i>0) {
6852       if(itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP) {
6853         if(i>1) is32=lastbranch;
6854         else is32=1;
6855       }
6856     }
6857     if(i>1)
6858     {
6859       if(itype[i-2]==CJUMP||itype[i-2]==SJUMP||itype[i-2]==FJUMP) {
6860         if(likely[i-2]) {
6861           if(i>2) is32=lastbranch;
6862           else is32=1;
6863         }
6864       }
6865       if((opcode[i-2]&0x2f)==0x05) // BNE/BNEL
6866       {
6867         if(rs1[i-2]==0||rs2[i-2]==0)
6868         {
6869           if(rs1[i-2]) {
6870             is32|=1LL<<rs1[i-2];
6871           }
6872           if(rs2[i-2]) {
6873             is32|=1LL<<rs2[i-2];
6874           }
6875         }
6876       }
6877     }
6878     // If something jumps here with 64-bit values
6879     // then promote those registers to 64 bits
6880     if(bt[i])
6881     {
6882       uint64_t temp_is32=is32;
6883       for(j=i-1;j>=0;j--)
6884       {
6885         if(ba[j]==start+i*4)
6886           //temp_is32&=branch_regs[j].is32;
6887           temp_is32&=p32[j];
6888       }
6889       for(j=i;j<slen;j++)
6890       {
6891         if(ba[j]==start+i*4)
6892           temp_is32=1;
6893       }
6894       is32=temp_is32;
6895     }
6896     int type=itype[i];
6897     int op=opcode[i];
6898     int op2=opcode2[i];
6899     int rt=rt1[i];
6900     int s1=rs1[i];
6901     int s2=rs2[i];
6902     if(type==UJUMP||type==RJUMP||type==CJUMP||type==SJUMP||type==FJUMP) {
6903       // Branches don't write registers, consider the delay slot instead.
6904       type=itype[i+1];
6905       op=opcode[i+1];
6906       op2=opcode2[i+1];
6907       rt=rt1[i+1];
6908       s1=rs1[i+1];
6909       s2=rs2[i+1];
6910       lastbranch=is32;
6911     }
6912     switch(type) {
6913       case LOAD:
6914         if(opcode[i]==0x27||opcode[i]==0x37|| // LWU/LD
6915            opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
6916           is32&=~(1LL<<rt);
6917         else
6918           is32|=1LL<<rt;
6919         break;
6920       case STORE:
6921       case STORELR:
6922         break;
6923       case LOADLR:
6924         if(op==0x1a||op==0x1b) is32&=~(1LL<<rt); // LDR/LDL
6925         if(op==0x22) is32|=1LL<<rt; // LWL
6926         break;
6927       case IMM16:
6928         if (op==0x08||op==0x09|| // ADDI/ADDIU
6929             op==0x0a||op==0x0b|| // SLTI/SLTIU
6930             op==0x0c|| // ANDI
6931             op==0x0f)  // LUI
6932         {
6933           is32|=1LL<<rt;
6934         }
6935         if(op==0x18||op==0x19) { // DADDI/DADDIU
6936           is32&=~(1LL<<rt);
6937           //if(imm[i]==0)
6938           //  is32|=((is32>>s1)&1LL)<<rt;
6939         }
6940         if(op==0x0d||op==0x0e) { // ORI/XORI
6941           uint64_t sr=((is32>>s1)&1LL);
6942           is32&=~(1LL<<rt);
6943           is32|=sr<<rt;
6944         }
6945         break;
6946       case UJUMP:
6947         break;
6948       case RJUMP:
6949         break;
6950       case CJUMP:
6951         break;
6952       case SJUMP:
6953         break;
6954       case FJUMP:
6955         break;
6956       case ALU:
6957         if(op2>=0x20&&op2<=0x23) { // ADD/ADDU/SUB/SUBU
6958           is32|=1LL<<rt;
6959         }
6960         if(op2==0x2a||op2==0x2b) { // SLT/SLTU
6961           is32|=1LL<<rt;
6962         }
6963         else if(op2>=0x24&&op2<=0x27) { // AND/OR/XOR/NOR
6964           uint64_t sr=((is32>>s1)&(is32>>s2)&1LL);
6965           is32&=~(1LL<<rt);
6966           is32|=sr<<rt;
6967         }
6968         else if(op2>=0x2c&&op2<=0x2d) { // DADD/DADDU
6969           if(s1==0&&s2==0) {
6970             is32|=1LL<<rt;
6971           }
6972           else if(s2==0) {
6973             uint64_t sr=((is32>>s1)&1LL);
6974             is32&=~(1LL<<rt);
6975             is32|=sr<<rt;
6976           }
6977           else if(s1==0) {
6978             uint64_t sr=((is32>>s2)&1LL);
6979             is32&=~(1LL<<rt);
6980             is32|=sr<<rt;
6981           }
6982           else {
6983             is32&=~(1LL<<rt);
6984           }
6985         }
6986         else if(op2>=0x2e&&op2<=0x2f) { // DSUB/DSUBU
6987           if(s1==0&&s2==0) {
6988             is32|=1LL<<rt;
6989           }
6990           else if(s2==0) {
6991             uint64_t sr=((is32>>s1)&1LL);
6992             is32&=~(1LL<<rt);
6993             is32|=sr<<rt;
6994           }
6995           else {
6996             is32&=~(1LL<<rt);
6997           }
6998         }
6999         break;
7000       case MULTDIV:
7001         if (op2>=0x1c&&op2<=0x1f) { // DMULT/DMULTU/DDIV/DDIVU
7002           is32&=~((1LL<<HIREG)|(1LL<<LOREG));
7003         }
7004         else {
7005           is32|=(1LL<<HIREG)|(1LL<<LOREG);
7006         }
7007         break;
7008       case MOV:
7009         {
7010           uint64_t sr=((is32>>s1)&1LL);
7011           is32&=~(1LL<<rt);
7012           is32|=sr<<rt;
7013         }
7014         break;
7015       case SHIFT:
7016         if(op2>=0x14&&op2<=0x17) is32&=~(1LL<<rt); // DSLLV/DSRLV/DSRAV
7017         else is32|=1LL<<rt; // SLLV/SRLV/SRAV
7018         break;
7019       case SHIFTIMM:
7020         is32|=1LL<<rt;
7021         // DSLL/DSRL/DSRA/DSLL32/DSRL32 but not DSRA32 have 64-bit result
7022         if(op2>=0x38&&op2<0x3f) is32&=~(1LL<<rt);
7023         break;
7024       case COP0:
7025         if(op2==0) is32|=1LL<<rt; // MFC0
7026         break;
7027       case COP1:
7028       case COP2:
7029         if(op2==0) is32|=1LL<<rt; // MFC1
7030         if(op2==1) is32&=~(1LL<<rt); // DMFC1
7031         if(op2==2) is32|=1LL<<rt; // CFC1
7032         break;
7033       case C1LS:
7034       case C2LS:
7035         break;
7036       case FLOAT:
7037       case FCONV:
7038         break;
7039       case FCOMP:
7040         break;
7041       case C2OP:
7042       case SYSCALL:
7043       case HLECALL:
7044         break;
7045       default:
7046         break;
7047     }
7048     is32|=1;
7049     p32[i]=is32;
7050
7051     if(i>0)
7052     {
7053       if(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)
7054       {
7055         if(rt1[i-1]==31) // JAL/JALR
7056         {
7057           // Subroutine call will return here, don't alloc any registers
7058           is32=1;
7059         }
7060         else if(i+1<slen)
7061         {
7062           // Internal branch will jump here, match registers to caller
7063           is32=0x3FFFFFFFFLL;
7064         }
7065       }
7066     }
7067   }
7068 }
7069
7070 // Identify registers which may be assumed to contain 32-bit values
7071 // and where optimizations will rely on this.
7072 // This is used to determine whether backward branches can safely
7073 // jump to a location with 64-bit values in registers.
7074 static void provisional_r32()
7075 {
7076   u_int r32=0;
7077   int i;
7078
7079   for (i=slen-1;i>=0;i--)
7080   {
7081     int hr;
7082     if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
7083     {
7084       if(ba[i]<start || ba[i]>=(start+slen*4))
7085       {
7086         // Branch out of this block, don't need anything
7087         r32=0;
7088       }
7089       else
7090       {
7091         // Internal branch
7092         // Need whatever matches the target
7093         // (and doesn't get overwritten by the delay slot instruction)
7094         r32=0;
7095         int t=(ba[i]-start)>>2;
7096         if(ba[i]>start+i*4) {
7097           // Forward branch
7098           //if(!(requires_32bit[t]&~regs[i].was32))
7099           //  r32|=requires_32bit[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
7100           if(!(pr32[t]&~regs[i].was32))
7101             r32|=pr32[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
7102         }else{
7103           // Backward branch
7104           if(!(regs[t].was32&~unneeded_reg_upper[t]&~regs[i].was32))
7105             r32|=regs[t].was32&~unneeded_reg_upper[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
7106         }
7107       }
7108       // Conditional branch may need registers for following instructions
7109       if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
7110       {
7111         if(i<slen-2) {
7112           //r32|=requires_32bit[i+2];
7113           r32|=pr32[i+2];
7114           r32&=regs[i].was32;
7115           // Mark this address as a branch target since it may be called
7116           // upon return from interrupt
7117           //bt[i+2]=1;
7118         }
7119       }
7120       // Merge in delay slot
7121       if(!likely[i]) {
7122         // These are overwritten unless the branch is "likely"
7123         // and the delay slot is nullified if not taken
7124         r32&=~(1LL<<rt1[i+1]);
7125         r32&=~(1LL<<rt2[i+1]);
7126       }
7127       // Assume these are needed (delay slot)
7128       if(us1[i+1]>0)
7129       {
7130         if((regs[i].was32>>us1[i+1])&1) r32|=1LL<<us1[i+1];
7131       }
7132       if(us2[i+1]>0)
7133       {
7134         if((regs[i].was32>>us2[i+1])&1) r32|=1LL<<us2[i+1];
7135       }
7136       if(dep1[i+1]&&!((unneeded_reg_upper[i]>>dep1[i+1])&1))
7137       {
7138         if((regs[i].was32>>dep1[i+1])&1) r32|=1LL<<dep1[i+1];
7139       }
7140       if(dep2[i+1]&&!((unneeded_reg_upper[i]>>dep2[i+1])&1))
7141       {
7142         if((regs[i].was32>>dep2[i+1])&1) r32|=1LL<<dep2[i+1];
7143       }
7144     }
7145     else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
7146     {
7147       // SYSCALL instruction (software interrupt)
7148       r32=0;
7149     }
7150     else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
7151     {
7152       // ERET instruction (return from interrupt)
7153       r32=0;
7154     }
7155     // Check 32 bits
7156     r32&=~(1LL<<rt1[i]);
7157     r32&=~(1LL<<rt2[i]);
7158     if(us1[i]>0)
7159     {
7160       if((regs[i].was32>>us1[i])&1) r32|=1LL<<us1[i];
7161     }
7162     if(us2[i]>0)
7163     {
7164       if((regs[i].was32>>us2[i])&1) r32|=1LL<<us2[i];
7165     }
7166     if(dep1[i]&&!((unneeded_reg_upper[i]>>dep1[i])&1))
7167     {
7168       if((regs[i].was32>>dep1[i])&1) r32|=1LL<<dep1[i];
7169     }
7170     if(dep2[i]&&!((unneeded_reg_upper[i]>>dep2[i])&1))
7171     {
7172       if((regs[i].was32>>dep2[i])&1) r32|=1LL<<dep2[i];
7173     }
7174     //requires_32bit[i]=r32;
7175     pr32[i]=r32;
7176
7177     // Dirty registers which are 32-bit, require 32-bit input
7178     // as they will be written as 32-bit values
7179     for(hr=0;hr<HOST_REGS;hr++)
7180     {
7181       if(regs[i].regmap_entry[hr]>0&&regs[i].regmap_entry[hr]<64) {
7182         if((regs[i].was32>>regs[i].regmap_entry[hr])&(regs[i].wasdirty>>hr)&1) {
7183           if(!((unneeded_reg_upper[i]>>regs[i].regmap_entry[hr])&1))
7184           pr32[i]|=1LL<<regs[i].regmap_entry[hr];
7185           //requires_32bit[i]|=1LL<<regs[i].regmap_entry[hr];
7186         }
7187       }
7188     }
7189   }
7190 }
7191
7192 // Write back dirty registers as soon as we will no longer modify them,
7193 // so that we don't end up with lots of writes at the branches.
7194 void clean_registers(int istart,int iend,int wr)
7195 {
7196   int i;
7197   int r;
7198   u_int will_dirty_i,will_dirty_next,temp_will_dirty;
7199   u_int wont_dirty_i,wont_dirty_next,temp_wont_dirty;
7200   if(iend==slen-1) {
7201     will_dirty_i=will_dirty_next=0;
7202     wont_dirty_i=wont_dirty_next=0;
7203   }else{
7204     will_dirty_i=will_dirty_next=will_dirty[iend+1];
7205     wont_dirty_i=wont_dirty_next=wont_dirty[iend+1];
7206   }
7207   for (i=iend;i>=istart;i--)
7208   {
7209     if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
7210     {
7211       if(ba[i]<start || ba[i]>=(start+slen*4))
7212       {
7213         // Branch out of this block, flush all regs
7214         if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
7215         {
7216           // Unconditional branch
7217           will_dirty_i=0;
7218           wont_dirty_i=0;
7219           // Merge in delay slot (will dirty)
7220           for(r=0;r<HOST_REGS;r++) {
7221             if(r!=EXCLUDE_REG) {
7222               if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7223               if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7224               if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7225               if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7226               if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7227               if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7228               if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7229               if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7230               if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7231               if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7232               if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7233               if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7234               if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7235               if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7236             }
7237           }
7238         }
7239         else
7240         {
7241           // Conditional branch
7242           will_dirty_i=0;
7243           wont_dirty_i=wont_dirty_next;
7244           // Merge in delay slot (will dirty)
7245           for(r=0;r<HOST_REGS;r++) {
7246             if(r!=EXCLUDE_REG) {
7247               if(!likely[i]) {
7248                 // Might not dirty if likely branch is not taken
7249                 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7250                 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7251                 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7252                 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7253                 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7254                 if(branch_regs[i].regmap[r]==0) will_dirty_i&=~(1<<r);
7255                 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7256                 //if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7257                 //if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7258                 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7259                 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7260                 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7261                 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7262                 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7263               }
7264             }
7265           }
7266         }
7267         // Merge in delay slot (wont dirty)
7268         for(r=0;r<HOST_REGS;r++) {
7269           if(r!=EXCLUDE_REG) {
7270             if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7271             if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7272             if((regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7273             if((regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7274             if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7275             if((branch_regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7276             if((branch_regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7277             if((branch_regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7278             if((branch_regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7279             if(branch_regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7280           }
7281         }
7282         if(wr) {
7283           #ifndef DESTRUCTIVE_WRITEBACK
7284           branch_regs[i].dirty&=wont_dirty_i;
7285           #endif
7286           branch_regs[i].dirty|=will_dirty_i;
7287         }
7288       }
7289       else
7290       {
7291         // Internal branch
7292         if(ba[i]<=start+i*4) {
7293           // Backward branch
7294           if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
7295           {
7296             // Unconditional branch
7297             temp_will_dirty=0;
7298             temp_wont_dirty=0;
7299             // Merge in delay slot (will dirty)
7300             for(r=0;r<HOST_REGS;r++) {
7301               if(r!=EXCLUDE_REG) {
7302                 if((branch_regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7303                 if((branch_regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7304                 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7305                 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7306                 if((branch_regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7307                 if(branch_regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
7308                 if(branch_regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7309                 if((regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7310                 if((regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7311                 if((regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7312                 if((regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7313                 if((regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7314                 if(regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
7315                 if(regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7316               }
7317             }
7318           } else {
7319             // Conditional branch (not taken case)
7320             temp_will_dirty=will_dirty_next;
7321             temp_wont_dirty=wont_dirty_next;
7322             // Merge in delay slot (will dirty)
7323             for(r=0;r<HOST_REGS;r++) {
7324               if(r!=EXCLUDE_REG) {
7325                 if(!likely[i]) {
7326                   // Will not dirty if likely branch is not taken
7327                   if((branch_regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7328                   if((branch_regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7329                   if((branch_regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7330                   if((branch_regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7331                   if((branch_regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7332                   if(branch_regs[i].regmap[r]==0) temp_will_dirty&=~(1<<r);
7333                   if(branch_regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7334                   //if((regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7335                   //if((regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7336                   if((regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7337                   if((regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7338                   if((regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7339                   if(regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
7340                   if(regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7341                 }
7342               }
7343             }
7344           }
7345           // Merge in delay slot (wont dirty)
7346           for(r=0;r<HOST_REGS;r++) {
7347             if(r!=EXCLUDE_REG) {
7348               if((regs[i].regmap[r]&63)==rt1[i]) temp_wont_dirty|=1<<r;
7349               if((regs[i].regmap[r]&63)==rt2[i]) temp_wont_dirty|=1<<r;
7350               if((regs[i].regmap[r]&63)==rt1[i+1]) temp_wont_dirty|=1<<r;
7351               if((regs[i].regmap[r]&63)==rt2[i+1]) temp_wont_dirty|=1<<r;
7352               if(regs[i].regmap[r]==CCREG) temp_wont_dirty|=1<<r;
7353               if((branch_regs[i].regmap[r]&63)==rt1[i]) temp_wont_dirty|=1<<r;
7354               if((branch_regs[i].regmap[r]&63)==rt2[i]) temp_wont_dirty|=1<<r;
7355               if((branch_regs[i].regmap[r]&63)==rt1[i+1]) temp_wont_dirty|=1<<r;
7356               if((branch_regs[i].regmap[r]&63)==rt2[i+1]) temp_wont_dirty|=1<<r;
7357               if(branch_regs[i].regmap[r]==CCREG) temp_wont_dirty|=1<<r;
7358             }
7359           }
7360           // Deal with changed mappings
7361           if(i<iend) {
7362             for(r=0;r<HOST_REGS;r++) {
7363               if(r!=EXCLUDE_REG) {
7364                 if(regs[i].regmap[r]!=regmap_pre[i][r]) {
7365                   temp_will_dirty&=~(1<<r);
7366                   temp_wont_dirty&=~(1<<r);
7367                   if((regmap_pre[i][r]&63)>0 && (regmap_pre[i][r]&63)<34) {
7368                     temp_will_dirty|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7369                     temp_wont_dirty|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7370                   } else {
7371                     temp_will_dirty|=1<<r;
7372                     temp_wont_dirty|=1<<r;
7373                   }
7374                 }
7375               }
7376             }
7377           }
7378           if(wr) {
7379             will_dirty[i]=temp_will_dirty;
7380             wont_dirty[i]=temp_wont_dirty;
7381             clean_registers((ba[i]-start)>>2,i-1,0);
7382           }else{
7383             // Limit recursion.  It can take an excessive amount
7384             // of time if there are a lot of nested loops.
7385             will_dirty[(ba[i]-start)>>2]=0;
7386             wont_dirty[(ba[i]-start)>>2]=-1;
7387           }
7388         }
7389         /*else*/ if(1)
7390         {
7391           if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
7392           {
7393             // Unconditional branch
7394             will_dirty_i=0;
7395             wont_dirty_i=0;
7396           //if(ba[i]>start+i*4) { // Disable recursion (for debugging)
7397             for(r=0;r<HOST_REGS;r++) {
7398               if(r!=EXCLUDE_REG) {
7399                 if(branch_regs[i].regmap[r]==regs[(ba[i]-start)>>2].regmap_entry[r]) {
7400                   will_dirty_i|=will_dirty[(ba[i]-start)>>2]&(1<<r);
7401                   wont_dirty_i|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
7402                 }
7403               }
7404             }
7405           //}
7406             // Merge in delay slot
7407             for(r=0;r<HOST_REGS;r++) {
7408               if(r!=EXCLUDE_REG) {
7409                 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7410                 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7411                 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7412                 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7413                 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7414                 if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7415                 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7416                 if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7417                 if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7418                 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7419                 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7420                 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7421                 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7422                 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7423               }
7424             }
7425           } else {
7426             // Conditional branch
7427             will_dirty_i=will_dirty_next;
7428             wont_dirty_i=wont_dirty_next;
7429           //if(ba[i]>start+i*4) { // Disable recursion (for debugging)
7430             for(r=0;r<HOST_REGS;r++) {
7431               if(r!=EXCLUDE_REG) {
7432                 if(branch_regs[i].regmap[r]==regs[(ba[i]-start)>>2].regmap_entry[r]) {
7433                   will_dirty_i&=will_dirty[(ba[i]-start)>>2]&(1<<r);
7434                   wont_dirty_i|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
7435                 }
7436                 else
7437                 {
7438                   will_dirty_i&=~(1<<r);
7439                 }
7440                 // Treat delay slot as part of branch too
7441                 /*if(regs[i+1].regmap[r]==regs[(ba[i]-start)>>2].regmap_entry[r]) {
7442                   will_dirty[i+1]&=will_dirty[(ba[i]-start)>>2]&(1<<r);
7443                   wont_dirty[i+1]|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
7444                 }
7445                 else
7446                 {
7447                   will_dirty[i+1]&=~(1<<r);
7448                 }*/
7449               }
7450             }
7451           //}
7452             // Merge in delay slot
7453             for(r=0;r<HOST_REGS;r++) {
7454               if(r!=EXCLUDE_REG) {
7455                 if(!likely[i]) {
7456                   // Might not dirty if likely branch is not taken
7457                   if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7458                   if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7459                   if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7460                   if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7461                   if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7462                   if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7463                   if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7464                   //if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7465                   //if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7466                   if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7467                   if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7468                   if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7469                   if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7470                   if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7471                 }
7472               }
7473             }
7474           }
7475           // Merge in delay slot
7476           for(r=0;r<HOST_REGS;r++) {
7477             if(r!=EXCLUDE_REG) {
7478               if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7479               if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7480               if((regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7481               if((regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7482               if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7483               if((branch_regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7484               if((branch_regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7485               if((branch_regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7486               if((branch_regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7487               if(branch_regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7488             }
7489           }
7490           if(wr) {
7491             #ifndef DESTRUCTIVE_WRITEBACK
7492             branch_regs[i].dirty&=wont_dirty_i;
7493             #endif
7494             branch_regs[i].dirty|=will_dirty_i;
7495           }
7496         }
7497       }
7498     }
7499     else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
7500     {
7501       // SYSCALL instruction (software interrupt)
7502       will_dirty_i=0;
7503       wont_dirty_i=0;
7504     }
7505     else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
7506     {
7507       // ERET instruction (return from interrupt)
7508       will_dirty_i=0;
7509       wont_dirty_i=0;
7510     }
7511     will_dirty_next=will_dirty_i;
7512     wont_dirty_next=wont_dirty_i;
7513     for(r=0;r<HOST_REGS;r++) {
7514       if(r!=EXCLUDE_REG) {
7515         if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7516         if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7517         if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7518         if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7519         if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7520         if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7521         if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7522         if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7523         if(i>istart) {
7524           if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=FJUMP)
7525           {
7526             // Don't store a register immediately after writing it,
7527             // may prevent dual-issue.
7528             if((regs[i].regmap[r]&63)==rt1[i-1]) wont_dirty_i|=1<<r;
7529             if((regs[i].regmap[r]&63)==rt2[i-1]) wont_dirty_i|=1<<r;
7530           }
7531         }
7532       }
7533     }
7534     // Save it
7535     will_dirty[i]=will_dirty_i;
7536     wont_dirty[i]=wont_dirty_i;
7537     // Mark registers that won't be dirtied as not dirty
7538     if(wr) {
7539       /*printf("wr (%d,%d) %x will:",istart,iend,start+i*4);
7540       for(r=0;r<HOST_REGS;r++) {
7541         if((will_dirty_i>>r)&1) {
7542           printf(" r%d",r);
7543         }
7544       }
7545       printf("\n");*/
7546
7547       //if(i==istart||(itype[i-1]!=RJUMP&&itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=FJUMP)) {
7548         regs[i].dirty|=will_dirty_i;
7549         #ifndef DESTRUCTIVE_WRITEBACK
7550         regs[i].dirty&=wont_dirty_i;
7551         if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
7552         {
7553           if(i<iend-1&&itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000) {
7554             for(r=0;r<HOST_REGS;r++) {
7555               if(r!=EXCLUDE_REG) {
7556                 if(regs[i].regmap[r]==regmap_pre[i+2][r]) {
7557                   regs[i+2].wasdirty&=wont_dirty_i|~(1<<r);
7558                 }else {/*printf("i: %x (%d) mismatch(+2): %d\n",start+i*4,i,r);/*assert(!((wont_dirty_i>>r)&1));*/}
7559               }
7560             }
7561           }
7562         }
7563         else
7564         {
7565           if(i<iend) {
7566             for(r=0;r<HOST_REGS;r++) {
7567               if(r!=EXCLUDE_REG) {
7568                 if(regs[i].regmap[r]==regmap_pre[i+1][r]) {
7569                   regs[i+1].wasdirty&=wont_dirty_i|~(1<<r);
7570                 }else {/*printf("i: %x (%d) mismatch(+1): %d\n",start+i*4,i,r);/*assert(!((wont_dirty_i>>r)&1));*/}
7571               }
7572             }
7573           }
7574         }
7575         #endif
7576       //}
7577     }
7578     // Deal with changed mappings
7579     temp_will_dirty=will_dirty_i;
7580     temp_wont_dirty=wont_dirty_i;
7581     for(r=0;r<HOST_REGS;r++) {
7582       if(r!=EXCLUDE_REG) {
7583         int nr;
7584         if(regs[i].regmap[r]==regmap_pre[i][r]) {
7585           if(wr) {
7586             #ifndef DESTRUCTIVE_WRITEBACK
7587             regs[i].wasdirty&=wont_dirty_i|~(1<<r);
7588             #endif
7589             regs[i].wasdirty|=will_dirty_i&(1<<r);
7590           }
7591         }
7592         else if((nr=get_reg(regs[i].regmap,regmap_pre[i][r]))>=0) {
7593           // Register moved to a different register
7594           will_dirty_i&=~(1<<r);
7595           wont_dirty_i&=~(1<<r);
7596           will_dirty_i|=((temp_will_dirty>>nr)&1)<<r;
7597           wont_dirty_i|=((temp_wont_dirty>>nr)&1)<<r;
7598           if(wr) {
7599             #ifndef DESTRUCTIVE_WRITEBACK
7600             regs[i].wasdirty&=wont_dirty_i|~(1<<r);
7601             #endif
7602             regs[i].wasdirty|=will_dirty_i&(1<<r);
7603           }
7604         }
7605         else {
7606           will_dirty_i&=~(1<<r);
7607           wont_dirty_i&=~(1<<r);
7608           if((regmap_pre[i][r]&63)>0 && (regmap_pre[i][r]&63)<34) {
7609             will_dirty_i|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7610             wont_dirty_i|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7611           } else {
7612             wont_dirty_i|=1<<r;
7613             /*printf("i: %x (%d) mismatch: %d\n",start+i*4,i,r);/*assert(!((will_dirty>>r)&1));*/
7614           }
7615         }
7616       }
7617     }
7618   }
7619 }
7620
7621   /* disassembly */
7622 void disassemble_inst(int i)
7623 {
7624     if (bt[i]) printf("*"); else printf(" ");
7625     switch(itype[i]) {
7626       case UJUMP:
7627         printf (" %x: %s %8x\n",start+i*4,insn[i],ba[i]);break;
7628       case CJUMP:
7629         printf (" %x: %s r%d,r%d,%8x\n",start+i*4,insn[i],rs1[i],rs2[i],i?start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14):*ba);break;
7630       case SJUMP:
7631         printf (" %x: %s r%d,%8x\n",start+i*4,insn[i],rs1[i],start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14));break;
7632       case FJUMP:
7633         printf (" %x: %s %8x\n",start+i*4,insn[i],ba[i]);break;
7634       case RJUMP:
7635         if (opcode[i]==0x9&&rt1[i]!=31)
7636           printf (" %x: %s r%d,r%d\n",start+i*4,insn[i],rt1[i],rs1[i]);
7637         else
7638           printf (" %x: %s r%d\n",start+i*4,insn[i],rs1[i]);
7639         break;
7640       case SPAN:
7641         printf (" %x: %s (pagespan) r%d,r%d,%8x\n",start+i*4,insn[i],rs1[i],rs2[i],ba[i]);break;
7642       case IMM16:
7643         if(opcode[i]==0xf) //LUI
7644           printf (" %x: %s r%d,%4x0000\n",start+i*4,insn[i],rt1[i],imm[i]&0xffff);
7645         else
7646           printf (" %x: %s r%d,r%d,%d\n",start+i*4,insn[i],rt1[i],rs1[i],imm[i]);
7647         break;
7648       case LOAD:
7649       case LOADLR:
7650         printf (" %x: %s r%d,r%d+%x\n",start+i*4,insn[i],rt1[i],rs1[i],imm[i]);
7651         break;
7652       case STORE:
7653       case STORELR:
7654         printf (" %x: %s r%d,r%d+%x\n",start+i*4,insn[i],rs2[i],rs1[i],imm[i]);
7655         break;
7656       case ALU:
7657       case SHIFT:
7658         printf (" %x: %s r%d,r%d,r%d\n",start+i*4,insn[i],rt1[i],rs1[i],rs2[i]);
7659         break;
7660       case MULTDIV:
7661         printf (" %x: %s r%d,r%d\n",start+i*4,insn[i],rs1[i],rs2[i]);
7662         break;
7663       case SHIFTIMM:
7664         printf (" %x: %s r%d,r%d,%d\n",start+i*4,insn[i],rt1[i],rs1[i],imm[i]);
7665         break;
7666       case MOV:
7667         if((opcode2[i]&0x1d)==0x10)
7668           printf (" %x: %s r%d\n",start+i*4,insn[i],rt1[i]);
7669         else if((opcode2[i]&0x1d)==0x11)
7670           printf (" %x: %s r%d\n",start+i*4,insn[i],rs1[i]);
7671         else
7672           printf (" %x: %s\n",start+i*4,insn[i]);
7673         break;
7674       case COP0:
7675         if(opcode2[i]==0)
7676           printf (" %x: %s r%d,cpr0[%d]\n",start+i*4,insn[i],rt1[i],(source[i]>>11)&0x1f); // MFC0
7677         else if(opcode2[i]==4)
7678           printf (" %x: %s r%d,cpr0[%d]\n",start+i*4,insn[i],rs1[i],(source[i]>>11)&0x1f); // MTC0
7679         else printf (" %x: %s\n",start+i*4,insn[i]);
7680         break;
7681       case COP1:
7682         if(opcode2[i]<3)
7683           printf (" %x: %s r%d,cpr1[%d]\n",start+i*4,insn[i],rt1[i],(source[i]>>11)&0x1f); // MFC1
7684         else if(opcode2[i]>3)
7685           printf (" %x: %s r%d,cpr1[%d]\n",start+i*4,insn[i],rs1[i],(source[i]>>11)&0x1f); // MTC1
7686         else printf (" %x: %s\n",start+i*4,insn[i]);
7687         break;
7688       case COP2:
7689         if(opcode2[i]<3)
7690           printf (" %x: %s r%d,cpr2[%d]\n",start+i*4,insn[i],rt1[i],(source[i]>>11)&0x1f); // MFC2
7691         else if(opcode2[i]>3)
7692           printf (" %x: %s r%d,cpr2[%d]\n",start+i*4,insn[i],rs1[i],(source[i]>>11)&0x1f); // MTC2
7693         else printf (" %x: %s\n",start+i*4,insn[i]);
7694         break;
7695       case C1LS:
7696         printf (" %x: %s cpr1[%d],r%d+%x\n",start+i*4,insn[i],(source[i]>>16)&0x1f,rs1[i],imm[i]);
7697         break;
7698       case C2LS:
7699         printf (" %x: %s cpr2[%d],r%d+%x\n",start+i*4,insn[i],(source[i]>>16)&0x1f,rs1[i],imm[i]);
7700         break;
7701       case INTCALL:
7702         printf (" %x: %s (INTCALL)\n",start+i*4,insn[i]);
7703         break;
7704       default:
7705         //printf (" %s %8x\n",insn[i],source[i]);
7706         printf (" %x: %s\n",start+i*4,insn[i]);
7707     }
7708 }
7709
7710 void new_dynarec_init()
7711 {
7712   printf("Init new dynarec\n");
7713   out=(u_char *)BASE_ADDR;
7714   if (mmap (out, 1<<TARGET_SIZE_2,
7715             PROT_READ | PROT_WRITE | PROT_EXEC,
7716             MAP_FIXED | MAP_PRIVATE | MAP_ANONYMOUS,
7717             -1, 0) <= 0) {printf("mmap() failed\n");}
7718 #ifdef MUPEN64
7719   rdword=&readmem_dword;
7720   fake_pc.f.r.rs=&readmem_dword;
7721   fake_pc.f.r.rt=&readmem_dword;
7722   fake_pc.f.r.rd=&readmem_dword;
7723 #endif
7724   int n;
7725   for(n=0x80000;n<0x80800;n++)
7726     invalid_code[n]=1;
7727   for(n=0;n<65536;n++)
7728     hash_table[n][0]=hash_table[n][2]=-1;
7729   memset(mini_ht,-1,sizeof(mini_ht));
7730   memset(restore_candidate,0,sizeof(restore_candidate));
7731   copy=shadow;
7732   expirep=16384; // Expiry pointer, +2 blocks
7733   pending_exception=0;
7734   literalcount=0;
7735 #ifdef HOST_IMM8
7736   // Copy this into local area so we don't have to put it in every literal pool
7737   invc_ptr=invalid_code;
7738 #endif
7739   stop_after_jal=0;
7740   // TLB
7741   using_tlb=0;
7742   for(n=0;n<524288;n++) // 0 .. 0x7FFFFFFF
7743     memory_map[n]=-1;
7744   for(n=524288;n<526336;n++) // 0x80000000 .. 0x807FFFFF
7745     memory_map[n]=((u_int)rdram-0x80000000)>>2;
7746   for(n=526336;n<1048576;n++) // 0x80800000 .. 0xFFFFFFFF
7747     memory_map[n]=-1;
7748 #ifdef MUPEN64
7749   for(n=0;n<0x8000;n++) { // 0 .. 0x7FFFFFFF
7750     writemem[n] = write_nomem_new;
7751     writememb[n] = write_nomemb_new;
7752     writememh[n] = write_nomemh_new;
7753 #ifndef FORCE32
7754     writememd[n] = write_nomemd_new;
7755 #endif
7756     readmem[n] = read_nomem_new;
7757     readmemb[n] = read_nomemb_new;
7758     readmemh[n] = read_nomemh_new;
7759 #ifndef FORCE32
7760     readmemd[n] = read_nomemd_new;
7761 #endif
7762   }
7763   for(n=0x8000;n<0x8080;n++) { // 0x80000000 .. 0x807FFFFF
7764     writemem[n] = write_rdram_new;
7765     writememb[n] = write_rdramb_new;
7766     writememh[n] = write_rdramh_new;
7767 #ifndef FORCE32
7768     writememd[n] = write_rdramd_new;
7769 #endif
7770   }
7771   for(n=0xC000;n<0x10000;n++) { // 0xC0000000 .. 0xFFFFFFFF
7772     writemem[n] = write_nomem_new;
7773     writememb[n] = write_nomemb_new;
7774     writememh[n] = write_nomemh_new;
7775 #ifndef FORCE32
7776     writememd[n] = write_nomemd_new;
7777 #endif
7778     readmem[n] = read_nomem_new;
7779     readmemb[n] = read_nomemb_new;
7780     readmemh[n] = read_nomemh_new;
7781 #ifndef FORCE32
7782     readmemd[n] = read_nomemd_new;
7783 #endif
7784   }
7785 #endif
7786   tlb_hacks();
7787   arch_init();
7788 }
7789
7790 void new_dynarec_cleanup()
7791 {
7792   int n;
7793   if (munmap ((void *)BASE_ADDR, 1<<TARGET_SIZE_2) < 0) {printf("munmap() failed\n");}
7794   for(n=0;n<4096;n++) ll_clear(jump_in+n);
7795   for(n=0;n<4096;n++) ll_clear(jump_out+n);
7796   for(n=0;n<4096;n++) ll_clear(jump_dirty+n);
7797   #ifdef ROM_COPY
7798   if (munmap (ROM_COPY, 67108864) < 0) {printf("munmap() failed\n");}
7799   #endif
7800 }
7801
7802 int new_recompile_block(int addr)
7803 {
7804 /*
7805   if(addr==0x800cd050) {
7806     int block;
7807     for(block=0x80000;block<0x80800;block++) invalidate_block(block);
7808     int n;
7809     for(n=0;n<=2048;n++) ll_clear(jump_dirty+n);
7810   }
7811 */
7812   //if(Count==365117028) tracedebug=1;
7813   assem_debug("NOTCOMPILED: addr = %x -> %x\n", (int)addr, (int)out);
7814   //printf("NOTCOMPILED: addr = %x -> %x\n", (int)addr, (int)out);
7815   //printf("TRACE: count=%d next=%d (compile %x)\n",Count,next_interupt,addr);
7816   //if(debug)
7817   //printf("TRACE: count=%d next=%d (checksum %x)\n",Count,next_interupt,mchecksum());
7818   //printf("fpu mapping=%x enabled=%x\n",(Status & 0x04000000)>>26,(Status & 0x20000000)>>29);
7819   /*if(Count>=312978186) {
7820     rlist();
7821   }*/
7822   //rlist();
7823   start = (u_int)addr&~3;
7824   //assert(((u_int)addr&1)==0);
7825 #ifdef PCSX
7826   if (Config.HLE && start == 0x80001000) // hlecall
7827   {
7828     // XXX: is this enough? Maybe check hleSoftCall?
7829     u_int beginning=(u_int)out;
7830     u_int page=get_page(start);
7831     invalid_code[start>>12]=0;
7832     emit_movimm(start,0);
7833     emit_writeword(0,(int)&pcaddr);
7834     emit_jmp((int)new_dyna_leave);
7835 #ifdef __arm__
7836     __clear_cache((void *)beginning,out);
7837 #endif
7838     ll_add(jump_in+page,start,(void *)beginning);
7839     return 0;
7840   }
7841   else if ((u_int)addr < 0x00200000 ||
7842     (0xa0000000 <= addr && addr < 0xa0200000)) {
7843     // used for BIOS calls mostly?
7844     source = (u_int *)((u_int)rdram+(start&0x1fffff));
7845     pagelimit = (addr&0xa0000000)|0x00200000;
7846   }
7847   else if (!Config.HLE && (
7848 /*    (0x9fc00000 <= addr && addr < 0x9fc80000) ||*/
7849     (0xbfc00000 <= addr && addr < 0xbfc80000))) {
7850     // BIOS
7851     source = (u_int *)((u_int)psxR+(start&0x7ffff));
7852     pagelimit = (addr&0xfff00000)|0x80000;
7853   }
7854   else
7855 #endif
7856 #ifdef MUPEN64
7857   if ((int)addr >= 0xa4000000 && (int)addr < 0xa4001000) {
7858     source = (u_int *)((u_int)SP_DMEM+start-0xa4000000);
7859     pagelimit = 0xa4001000;
7860   }
7861   else
7862 #endif
7863   if ((int)addr >= 0x80000000 && (int)addr < 0x80000000+RAM_SIZE) {
7864     source = (u_int *)((u_int)rdram+start-0x80000000);
7865     pagelimit = 0x80000000+RAM_SIZE;
7866   }
7867 #ifndef DISABLE_TLB
7868   else if ((signed int)addr >= (signed int)0xC0000000) {
7869     //printf("addr=%x mm=%x\n",(u_int)addr,(memory_map[start>>12]<<2));
7870     //if(tlb_LUT_r[start>>12])
7871       //source = (u_int *)(((int)rdram)+(tlb_LUT_r[start>>12]&0xFFFFF000)+(((int)addr)&0xFFF)-0x80000000);
7872     if((signed int)memory_map[start>>12]>=0) {
7873       source = (u_int *)((u_int)(start+(memory_map[start>>12]<<2)));
7874       pagelimit=(start+4096)&0xFFFFF000;
7875       int map=memory_map[start>>12];
7876       int i;
7877       for(i=0;i<5;i++) {
7878         //printf("start: %x next: %x\n",map,memory_map[pagelimit>>12]);
7879         if((map&0xBFFFFFFF)==(memory_map[pagelimit>>12]&0xBFFFFFFF)) pagelimit+=4096;
7880       }
7881       assem_debug("pagelimit=%x\n",pagelimit);
7882       assem_debug("mapping=%x (%x)\n",memory_map[start>>12],(memory_map[start>>12]<<2)+start);
7883     }
7884     else {
7885       assem_debug("Compile at unmapped memory address: %x \n", (int)addr);
7886       //assem_debug("start: %x next: %x\n",memory_map[start>>12],memory_map[(start+4096)>>12]);
7887       return -1; // Caller will invoke exception handler
7888     }
7889     //printf("source= %x\n",(int)source);
7890   }
7891 #endif
7892   else {
7893     printf("Compile at bogus memory address: %x \n", (int)addr);
7894     exit(1);
7895   }
7896
7897   /* Pass 1: disassemble */
7898   /* Pass 2: register dependencies, branch targets */
7899   /* Pass 3: register allocation */
7900   /* Pass 4: branch dependencies */
7901   /* Pass 5: pre-alloc */
7902   /* Pass 6: optimize clean/dirty state */
7903   /* Pass 7: flag 32-bit registers */
7904   /* Pass 8: assembly */
7905   /* Pass 9: linker */
7906   /* Pass 10: garbage collection / free memory */
7907
7908   int i,j;
7909   int done=0;
7910   unsigned int type,op,op2;
7911
7912   //printf("addr = %x source = %x %x\n", addr,source,source[0]);
7913
7914   /* Pass 1 disassembly */
7915
7916   for(i=0;!done;i++) {
7917     bt[i]=0;likely[i]=0;ooo[i]=0;op2=0;
7918     minimum_free_regs[i]=0;
7919     opcode[i]=op=source[i]>>26;
7920     switch(op)
7921     {
7922       case 0x00: strcpy(insn[i],"special"); type=NI;
7923         op2=source[i]&0x3f;
7924         switch(op2)
7925         {
7926           case 0x00: strcpy(insn[i],"SLL"); type=SHIFTIMM; break;
7927           case 0x02: strcpy(insn[i],"SRL"); type=SHIFTIMM; break;
7928           case 0x03: strcpy(insn[i],"SRA"); type=SHIFTIMM; break;
7929           case 0x04: strcpy(insn[i],"SLLV"); type=SHIFT; break;
7930           case 0x06: strcpy(insn[i],"SRLV"); type=SHIFT; break;
7931           case 0x07: strcpy(insn[i],"SRAV"); type=SHIFT; break;
7932           case 0x08: strcpy(insn[i],"JR"); type=RJUMP; break;
7933           case 0x09: strcpy(insn[i],"JALR"); type=RJUMP; break;
7934           case 0x0C: strcpy(insn[i],"SYSCALL"); type=SYSCALL; break;
7935           case 0x0D: strcpy(insn[i],"BREAK"); type=OTHER; break;
7936           case 0x0F: strcpy(insn[i],"SYNC"); type=OTHER; break;
7937           case 0x10: strcpy(insn[i],"MFHI"); type=MOV; break;
7938           case 0x11: strcpy(insn[i],"MTHI"); type=MOV; break;
7939           case 0x12: strcpy(insn[i],"MFLO"); type=MOV; break;
7940           case 0x13: strcpy(insn[i],"MTLO"); type=MOV; break;
7941           case 0x14: strcpy(insn[i],"DSLLV"); type=SHIFT; break;
7942           case 0x16: strcpy(insn[i],"DSRLV"); type=SHIFT; break;
7943           case 0x17: strcpy(insn[i],"DSRAV"); type=SHIFT; break;
7944           case 0x18: strcpy(insn[i],"MULT"); type=MULTDIV; break;
7945           case 0x19: strcpy(insn[i],"MULTU"); type=MULTDIV; break;
7946           case 0x1A: strcpy(insn[i],"DIV"); type=MULTDIV; break;
7947           case 0x1B: strcpy(insn[i],"DIVU"); type=MULTDIV; break;
7948           case 0x1C: strcpy(insn[i],"DMULT"); type=MULTDIV; break;
7949           case 0x1D: strcpy(insn[i],"DMULTU"); type=MULTDIV; break;
7950           case 0x1E: strcpy(insn[i],"DDIV"); type=MULTDIV; break;
7951           case 0x1F: strcpy(insn[i],"DDIVU"); type=MULTDIV; break;
7952           case 0x20: strcpy(insn[i],"ADD"); type=ALU; break;
7953           case 0x21: strcpy(insn[i],"ADDU"); type=ALU; break;
7954           case 0x22: strcpy(insn[i],"SUB"); type=ALU; break;
7955           case 0x23: strcpy(insn[i],"SUBU"); type=ALU; break;
7956           case 0x24: strcpy(insn[i],"AND"); type=ALU; break;
7957           case 0x25: strcpy(insn[i],"OR"); type=ALU; break;
7958           case 0x26: strcpy(insn[i],"XOR"); type=ALU; break;
7959           case 0x27: strcpy(insn[i],"NOR"); type=ALU; break;
7960           case 0x2A: strcpy(insn[i],"SLT"); type=ALU; break;
7961           case 0x2B: strcpy(insn[i],"SLTU"); type=ALU; break;
7962           case 0x2C: strcpy(insn[i],"DADD"); type=ALU; break;
7963           case 0x2D: strcpy(insn[i],"DADDU"); type=ALU; break;
7964           case 0x2E: strcpy(insn[i],"DSUB"); type=ALU; break;
7965           case 0x2F: strcpy(insn[i],"DSUBU"); type=ALU; break;
7966           case 0x30: strcpy(insn[i],"TGE"); type=NI; break;
7967           case 0x31: strcpy(insn[i],"TGEU"); type=NI; break;
7968           case 0x32: strcpy(insn[i],"TLT"); type=NI; break;
7969           case 0x33: strcpy(insn[i],"TLTU"); type=NI; break;
7970           case 0x34: strcpy(insn[i],"TEQ"); type=NI; break;
7971           case 0x36: strcpy(insn[i],"TNE"); type=NI; break;
7972           case 0x38: strcpy(insn[i],"DSLL"); type=SHIFTIMM; break;
7973           case 0x3A: strcpy(insn[i],"DSRL"); type=SHIFTIMM; break;
7974           case 0x3B: strcpy(insn[i],"DSRA"); type=SHIFTIMM; break;
7975           case 0x3C: strcpy(insn[i],"DSLL32"); type=SHIFTIMM; break;
7976           case 0x3E: strcpy(insn[i],"DSRL32"); type=SHIFTIMM; break;
7977           case 0x3F: strcpy(insn[i],"DSRA32"); type=SHIFTIMM; break;
7978         }
7979         break;
7980       case 0x01: strcpy(insn[i],"regimm"); type=NI;
7981         op2=(source[i]>>16)&0x1f;
7982         switch(op2)
7983         {
7984           case 0x00: strcpy(insn[i],"BLTZ"); type=SJUMP; break;
7985           case 0x01: strcpy(insn[i],"BGEZ"); type=SJUMP; break;
7986           case 0x02: strcpy(insn[i],"BLTZL"); type=SJUMP; break;
7987           case 0x03: strcpy(insn[i],"BGEZL"); type=SJUMP; break;
7988           case 0x08: strcpy(insn[i],"TGEI"); type=NI; break;
7989           case 0x09: strcpy(insn[i],"TGEIU"); type=NI; break;
7990           case 0x0A: strcpy(insn[i],"TLTI"); type=NI; break;
7991           case 0x0B: strcpy(insn[i],"TLTIU"); type=NI; break;
7992           case 0x0C: strcpy(insn[i],"TEQI"); type=NI; break;
7993           case 0x0E: strcpy(insn[i],"TNEI"); type=NI; break;
7994           case 0x10: strcpy(insn[i],"BLTZAL"); type=SJUMP; break;
7995           case 0x11: strcpy(insn[i],"BGEZAL"); type=SJUMP; break;
7996           case 0x12: strcpy(insn[i],"BLTZALL"); type=SJUMP; break;
7997           case 0x13: strcpy(insn[i],"BGEZALL"); type=SJUMP; break;
7998         }
7999         break;
8000       case 0x02: strcpy(insn[i],"J"); type=UJUMP; break;
8001       case 0x03: strcpy(insn[i],"JAL"); type=UJUMP; break;
8002       case 0x04: strcpy(insn[i],"BEQ"); type=CJUMP; break;
8003       case 0x05: strcpy(insn[i],"BNE"); type=CJUMP; break;
8004       case 0x06: strcpy(insn[i],"BLEZ"); type=CJUMP; break;
8005       case 0x07: strcpy(insn[i],"BGTZ"); type=CJUMP; break;
8006       case 0x08: strcpy(insn[i],"ADDI"); type=IMM16; break;
8007       case 0x09: strcpy(insn[i],"ADDIU"); type=IMM16; break;
8008       case 0x0A: strcpy(insn[i],"SLTI"); type=IMM16; break;
8009       case 0x0B: strcpy(insn[i],"SLTIU"); type=IMM16; break;
8010       case 0x0C: strcpy(insn[i],"ANDI"); type=IMM16; break;
8011       case 0x0D: strcpy(insn[i],"ORI"); type=IMM16; break;
8012       case 0x0E: strcpy(insn[i],"XORI"); type=IMM16; break;
8013       case 0x0F: strcpy(insn[i],"LUI"); type=IMM16; break;
8014       case 0x10: strcpy(insn[i],"cop0"); type=NI;
8015         op2=(source[i]>>21)&0x1f;
8016         switch(op2)
8017         {
8018           case 0x00: strcpy(insn[i],"MFC0"); type=COP0; break;
8019           case 0x04: strcpy(insn[i],"MTC0"); type=COP0; break;
8020           case 0x10: strcpy(insn[i],"tlb"); type=NI;
8021           switch(source[i]&0x3f)
8022           {
8023             case 0x01: strcpy(insn[i],"TLBR"); type=COP0; break;
8024             case 0x02: strcpy(insn[i],"TLBWI"); type=COP0; break;
8025             case 0x06: strcpy(insn[i],"TLBWR"); type=COP0; break;
8026             case 0x08: strcpy(insn[i],"TLBP"); type=COP0; break;
8027 #ifdef PCSX
8028             case 0x10: strcpy(insn[i],"RFE"); type=COP0; break;
8029 #else
8030             case 0x18: strcpy(insn[i],"ERET"); type=COP0; break;
8031 #endif
8032           }
8033         }
8034         break;
8035       case 0x11: strcpy(insn[i],"cop1"); type=NI;
8036         op2=(source[i]>>21)&0x1f;
8037         switch(op2)
8038         {
8039           case 0x00: strcpy(insn[i],"MFC1"); type=COP1; break;
8040           case 0x01: strcpy(insn[i],"DMFC1"); type=COP1; break;
8041           case 0x02: strcpy(insn[i],"CFC1"); type=COP1; break;
8042           case 0x04: strcpy(insn[i],"MTC1"); type=COP1; break;
8043           case 0x05: strcpy(insn[i],"DMTC1"); type=COP1; break;
8044           case 0x06: strcpy(insn[i],"CTC1"); type=COP1; break;
8045           case 0x08: strcpy(insn[i],"BC1"); type=FJUMP;
8046           switch((source[i]>>16)&0x3)
8047           {
8048             case 0x00: strcpy(insn[i],"BC1F"); break;
8049             case 0x01: strcpy(insn[i],"BC1T"); break;
8050             case 0x02: strcpy(insn[i],"BC1FL"); break;
8051             case 0x03: strcpy(insn[i],"BC1TL"); break;
8052           }
8053           break;
8054           case 0x10: strcpy(insn[i],"C1.S"); type=NI;
8055           switch(source[i]&0x3f)
8056           {
8057             case 0x00: strcpy(insn[i],"ADD.S"); type=FLOAT; break;
8058             case 0x01: strcpy(insn[i],"SUB.S"); type=FLOAT; break;
8059             case 0x02: strcpy(insn[i],"MUL.S"); type=FLOAT; break;
8060             case 0x03: strcpy(insn[i],"DIV.S"); type=FLOAT; break;
8061             case 0x04: strcpy(insn[i],"SQRT.S"); type=FLOAT; break;
8062             case 0x05: strcpy(insn[i],"ABS.S"); type=FLOAT; break;
8063             case 0x06: strcpy(insn[i],"MOV.S"); type=FLOAT; break;
8064             case 0x07: strcpy(insn[i],"NEG.S"); type=FLOAT; break;
8065             case 0x08: strcpy(insn[i],"ROUND.L.S"); type=FCONV; break;
8066             case 0x09: strcpy(insn[i],"TRUNC.L.S"); type=FCONV; break;
8067             case 0x0A: strcpy(insn[i],"CEIL.L.S"); type=FCONV; break;
8068             case 0x0B: strcpy(insn[i],"FLOOR.L.S"); type=FCONV; break;
8069             case 0x0C: strcpy(insn[i],"ROUND.W.S"); type=FCONV; break;
8070             case 0x0D: strcpy(insn[i],"TRUNC.W.S"); type=FCONV; break;
8071             case 0x0E: strcpy(insn[i],"CEIL.W.S"); type=FCONV; break;
8072             case 0x0F: strcpy(insn[i],"FLOOR.W.S"); type=FCONV; break;
8073             case 0x21: strcpy(insn[i],"CVT.D.S"); type=FCONV; break;
8074             case 0x24: strcpy(insn[i],"CVT.W.S"); type=FCONV; break;
8075             case 0x25: strcpy(insn[i],"CVT.L.S"); type=FCONV; break;
8076             case 0x30: strcpy(insn[i],"C.F.S"); type=FCOMP; break;
8077             case 0x31: strcpy(insn[i],"C.UN.S"); type=FCOMP; break;
8078             case 0x32: strcpy(insn[i],"C.EQ.S"); type=FCOMP; break;
8079             case 0x33: strcpy(insn[i],"C.UEQ.S"); type=FCOMP; break;
8080             case 0x34: strcpy(insn[i],"C.OLT.S"); type=FCOMP; break;
8081             case 0x35: strcpy(insn[i],"C.ULT.S"); type=FCOMP; break;
8082             case 0x36: strcpy(insn[i],"C.OLE.S"); type=FCOMP; break;
8083             case 0x37: strcpy(insn[i],"C.ULE.S"); type=FCOMP; break;
8084             case 0x38: strcpy(insn[i],"C.SF.S"); type=FCOMP; break;
8085             case 0x39: strcpy(insn[i],"C.NGLE.S"); type=FCOMP; break;
8086             case 0x3A: strcpy(insn[i],"C.SEQ.S"); type=FCOMP; break;
8087             case 0x3B: strcpy(insn[i],"C.NGL.S"); type=FCOMP; break;
8088             case 0x3C: strcpy(insn[i],"C.LT.S"); type=FCOMP; break;
8089             case 0x3D: strcpy(insn[i],"C.NGE.S"); type=FCOMP; break;
8090             case 0x3E: strcpy(insn[i],"C.LE.S"); type=FCOMP; break;
8091             case 0x3F: strcpy(insn[i],"C.NGT.S"); type=FCOMP; break;
8092           }
8093           break;
8094           case 0x11: strcpy(insn[i],"C1.D"); type=NI;
8095           switch(source[i]&0x3f)
8096           {
8097             case 0x00: strcpy(insn[i],"ADD.D"); type=FLOAT; break;
8098             case 0x01: strcpy(insn[i],"SUB.D"); type=FLOAT; break;
8099             case 0x02: strcpy(insn[i],"MUL.D"); type=FLOAT; break;
8100             case 0x03: strcpy(insn[i],"DIV.D"); type=FLOAT; break;
8101             case 0x04: strcpy(insn[i],"SQRT.D"); type=FLOAT; break;
8102             case 0x05: strcpy(insn[i],"ABS.D"); type=FLOAT; break;
8103             case 0x06: strcpy(insn[i],"MOV.D"); type=FLOAT; break;
8104             case 0x07: strcpy(insn[i],"NEG.D"); type=FLOAT; break;
8105             case 0x08: strcpy(insn[i],"ROUND.L.D"); type=FCONV; break;
8106             case 0x09: strcpy(insn[i],"TRUNC.L.D"); type=FCONV; break;
8107             case 0x0A: strcpy(insn[i],"CEIL.L.D"); type=FCONV; break;
8108             case 0x0B: strcpy(insn[i],"FLOOR.L.D"); type=FCONV; break;
8109             case 0x0C: strcpy(insn[i],"ROUND.W.D"); type=FCONV; break;
8110             case 0x0D: strcpy(insn[i],"TRUNC.W.D"); type=FCONV; break;
8111             case 0x0E: strcpy(insn[i],"CEIL.W.D"); type=FCONV; break;
8112             case 0x0F: strcpy(insn[i],"FLOOR.W.D"); type=FCONV; break;
8113             case 0x20: strcpy(insn[i],"CVT.S.D"); type=FCONV; break;
8114             case 0x24: strcpy(insn[i],"CVT.W.D"); type=FCONV; break;
8115             case 0x25: strcpy(insn[i],"CVT.L.D"); type=FCONV; break;
8116             case 0x30: strcpy(insn[i],"C.F.D"); type=FCOMP; break;
8117             case 0x31: strcpy(insn[i],"C.UN.D"); type=FCOMP; break;
8118             case 0x32: strcpy(insn[i],"C.EQ.D"); type=FCOMP; break;
8119             case 0x33: strcpy(insn[i],"C.UEQ.D"); type=FCOMP; break;
8120             case 0x34: strcpy(insn[i],"C.OLT.D"); type=FCOMP; break;
8121             case 0x35: strcpy(insn[i],"C.ULT.D"); type=FCOMP; break;
8122             case 0x36: strcpy(insn[i],"C.OLE.D"); type=FCOMP; break;
8123             case 0x37: strcpy(insn[i],"C.ULE.D"); type=FCOMP; break;
8124             case 0x38: strcpy(insn[i],"C.SF.D"); type=FCOMP; break;
8125             case 0x39: strcpy(insn[i],"C.NGLE.D"); type=FCOMP; break;
8126             case 0x3A: strcpy(insn[i],"C.SEQ.D"); type=FCOMP; break;
8127             case 0x3B: strcpy(insn[i],"C.NGL.D"); type=FCOMP; break;
8128             case 0x3C: strcpy(insn[i],"C.LT.D"); type=FCOMP; break;
8129             case 0x3D: strcpy(insn[i],"C.NGE.D"); type=FCOMP; break;
8130             case 0x3E: strcpy(insn[i],"C.LE.D"); type=FCOMP; break;
8131             case 0x3F: strcpy(insn[i],"C.NGT.D"); type=FCOMP; break;
8132           }
8133           break;
8134           case 0x14: strcpy(insn[i],"C1.W"); type=NI;
8135           switch(source[i]&0x3f)
8136           {
8137             case 0x20: strcpy(insn[i],"CVT.S.W"); type=FCONV; break;
8138             case 0x21: strcpy(insn[i],"CVT.D.W"); type=FCONV; break;
8139           }
8140           break;
8141           case 0x15: strcpy(insn[i],"C1.L"); type=NI;
8142           switch(source[i]&0x3f)
8143           {
8144             case 0x20: strcpy(insn[i],"CVT.S.L"); type=FCONV; break;
8145             case 0x21: strcpy(insn[i],"CVT.D.L"); type=FCONV; break;
8146           }
8147           break;
8148         }
8149         break;
8150 #ifndef FORCE32
8151       case 0x14: strcpy(insn[i],"BEQL"); type=CJUMP; break;
8152       case 0x15: strcpy(insn[i],"BNEL"); type=CJUMP; break;
8153       case 0x16: strcpy(insn[i],"BLEZL"); type=CJUMP; break;
8154       case 0x17: strcpy(insn[i],"BGTZL"); type=CJUMP; break;
8155       case 0x18: strcpy(insn[i],"DADDI"); type=IMM16; break;
8156       case 0x19: strcpy(insn[i],"DADDIU"); type=IMM16; break;
8157       case 0x1A: strcpy(insn[i],"LDL"); type=LOADLR; break;
8158       case 0x1B: strcpy(insn[i],"LDR"); type=LOADLR; break;
8159 #endif
8160       case 0x20: strcpy(insn[i],"LB"); type=LOAD; break;
8161       case 0x21: strcpy(insn[i],"LH"); type=LOAD; break;
8162       case 0x22: strcpy(insn[i],"LWL"); type=LOADLR; break;
8163       case 0x23: strcpy(insn[i],"LW"); type=LOAD; break;
8164       case 0x24: strcpy(insn[i],"LBU"); type=LOAD; break;
8165       case 0x25: strcpy(insn[i],"LHU"); type=LOAD; break;
8166       case 0x26: strcpy(insn[i],"LWR"); type=LOADLR; break;
8167       case 0x27: strcpy(insn[i],"LWU"); type=LOAD; break;
8168       case 0x28: strcpy(insn[i],"SB"); type=STORE; break;
8169       case 0x29: strcpy(insn[i],"SH"); type=STORE; break;
8170       case 0x2A: strcpy(insn[i],"SWL"); type=STORELR; break;
8171       case 0x2B: strcpy(insn[i],"SW"); type=STORE; break;
8172 #ifndef FORCE32
8173       case 0x2C: strcpy(insn[i],"SDL"); type=STORELR; break;
8174       case 0x2D: strcpy(insn[i],"SDR"); type=STORELR; break;
8175 #endif
8176       case 0x2E: strcpy(insn[i],"SWR"); type=STORELR; break;
8177       case 0x2F: strcpy(insn[i],"CACHE"); type=NOP; break;
8178       case 0x30: strcpy(insn[i],"LL"); type=NI; break;
8179       case 0x31: strcpy(insn[i],"LWC1"); type=C1LS; break;
8180 #ifndef FORCE32
8181       case 0x34: strcpy(insn[i],"LLD"); type=NI; break;
8182       case 0x35: strcpy(insn[i],"LDC1"); type=C1LS; break;
8183       case 0x37: strcpy(insn[i],"LD"); type=LOAD; break;
8184 #endif
8185       case 0x38: strcpy(insn[i],"SC"); type=NI; break;
8186       case 0x39: strcpy(insn[i],"SWC1"); type=C1LS; break;
8187 #ifndef FORCE32
8188       case 0x3C: strcpy(insn[i],"SCD"); type=NI; break;
8189       case 0x3D: strcpy(insn[i],"SDC1"); type=C1LS; break;
8190       case 0x3F: strcpy(insn[i],"SD"); type=STORE; break;
8191 #endif
8192 #ifdef PCSX
8193       case 0x12: strcpy(insn[i],"COP2"); type=NI;
8194         // note: COP MIPS-1 encoding differs from MIPS32
8195         op2=(source[i]>>21)&0x1f;
8196         if (source[i]&0x3f) {
8197           if (gte_handlers[source[i]&0x3f]!=NULL) {
8198             snprintf(insn[i], sizeof(insn[i]), "COP2 %x", source[i]&0x3f);
8199             type=C2OP;
8200           }
8201         }
8202         else switch(op2)
8203         {
8204           case 0x00: strcpy(insn[i],"MFC2"); type=COP2; break;
8205           case 0x02: strcpy(insn[i],"CFC2"); type=COP2; break;
8206           case 0x04: strcpy(insn[i],"MTC2"); type=COP2; break;
8207           case 0x06: strcpy(insn[i],"CTC2"); type=COP2; break;
8208         }
8209         break;
8210       case 0x32: strcpy(insn[i],"LWC2"); type=C2LS; break;
8211       case 0x3A: strcpy(insn[i],"SWC2"); type=C2LS; break;
8212       case 0x3B: strcpy(insn[i],"HLECALL"); type=HLECALL; break;
8213 #endif
8214       default: strcpy(insn[i],"???"); type=NI;
8215         printf("NI %08x @%08x (%08x)\n", source[i], addr + i*4, addr);
8216         break;
8217     }
8218 #ifdef PCSX
8219     /* detect branch in delay slot early */
8220     if(type==RJUMP||type==UJUMP||type==CJUMP||type==SJUMP||type==FJUMP) {
8221       opcode[i+1]=source[i+1]>>26;
8222       opcode2[i+1]=source[i+1]&0x3f;
8223       if((0<opcode[i+1]&&opcode[i+1]<8)||(opcode[i+1]==0&&(opcode2[i+1]==8||opcode2[i+1]==9))) {
8224         printf("branch in delay slot @%08x (%08x)\n", addr + i*4+4, addr);
8225         // don't handle first branch and call interpreter if it's hit
8226         type=INTCALL;
8227       }
8228     }
8229 #endif
8230     itype[i]=type;
8231     opcode2[i]=op2;
8232     /* Get registers/immediates */
8233     lt1[i]=0;
8234     us1[i]=0;
8235     us2[i]=0;
8236     dep1[i]=0;
8237     dep2[i]=0;
8238     switch(type) {
8239       case LOAD:
8240         rs1[i]=(source[i]>>21)&0x1f;
8241         rs2[i]=0;
8242         rt1[i]=(source[i]>>16)&0x1f;
8243         rt2[i]=0;
8244         imm[i]=(short)source[i];
8245         break;
8246       case STORE:
8247       case STORELR:
8248         rs1[i]=(source[i]>>21)&0x1f;
8249         rs2[i]=(source[i]>>16)&0x1f;
8250         rt1[i]=0;
8251         rt2[i]=0;
8252         imm[i]=(short)source[i];
8253         if(op==0x2c||op==0x2d||op==0x3f) us1[i]=rs2[i]; // 64-bit SDL/SDR/SD
8254         break;
8255       case LOADLR:
8256         // LWL/LWR only load part of the register,
8257         // therefore the target register must be treated as a source too
8258         rs1[i]=(source[i]>>21)&0x1f;
8259         rs2[i]=(source[i]>>16)&0x1f;
8260         rt1[i]=(source[i]>>16)&0x1f;
8261         rt2[i]=0;
8262         imm[i]=(short)source[i];
8263         if(op==0x1a||op==0x1b) us1[i]=rs2[i]; // LDR/LDL
8264         if(op==0x26) dep1[i]=rt1[i]; // LWR
8265         break;
8266       case IMM16:
8267         if (op==0x0f) rs1[i]=0; // LUI instruction has no source register
8268         else rs1[i]=(source[i]>>21)&0x1f;
8269         rs2[i]=0;
8270         rt1[i]=(source[i]>>16)&0x1f;
8271         rt2[i]=0;
8272         if(op>=0x0c&&op<=0x0e) { // ANDI/ORI/XORI
8273           imm[i]=(unsigned short)source[i];
8274         }else{
8275           imm[i]=(short)source[i];
8276         }
8277         if(op==0x18||op==0x19) us1[i]=rs1[i]; // DADDI/DADDIU
8278         if(op==0x0a||op==0x0b) us1[i]=rs1[i]; // SLTI/SLTIU
8279         if(op==0x0d||op==0x0e) dep1[i]=rs1[i]; // ORI/XORI
8280         break;
8281       case UJUMP:
8282         rs1[i]=0;
8283         rs2[i]=0;
8284         rt1[i]=0;
8285         rt2[i]=0;
8286         // The JAL instruction writes to r31.
8287         if (op&1) {
8288           rt1[i]=31;
8289         }
8290         rs2[i]=CCREG;
8291         break;
8292       case RJUMP:
8293         rs1[i]=(source[i]>>21)&0x1f;
8294         rs2[i]=0;
8295         rt1[i]=0;
8296         rt2[i]=0;
8297         // The JALR instruction writes to rd.
8298         if (op2&1) {
8299           rt1[i]=(source[i]>>11)&0x1f;
8300         }
8301         rs2[i]=CCREG;
8302         break;
8303       case CJUMP:
8304         rs1[i]=(source[i]>>21)&0x1f;
8305         rs2[i]=(source[i]>>16)&0x1f;
8306         rt1[i]=0;
8307         rt2[i]=0;
8308         if(op&2) { // BGTZ/BLEZ
8309           rs2[i]=0;
8310         }
8311         us1[i]=rs1[i];
8312         us2[i]=rs2[i];
8313         likely[i]=op>>4;
8314         break;
8315       case SJUMP:
8316         rs1[i]=(source[i]>>21)&0x1f;
8317         rs2[i]=CCREG;
8318         rt1[i]=0;
8319         rt2[i]=0;
8320         us1[i]=rs1[i];
8321         if(op2&0x10) { // BxxAL
8322           rt1[i]=31;
8323           // NOTE: If the branch is not taken, r31 is still overwritten
8324         }
8325         likely[i]=(op2&2)>>1;
8326         break;
8327       case FJUMP:
8328         rs1[i]=FSREG;
8329         rs2[i]=CSREG;
8330         rt1[i]=0;
8331         rt2[i]=0;
8332         likely[i]=((source[i])>>17)&1;
8333         break;
8334       case ALU:
8335         rs1[i]=(source[i]>>21)&0x1f; // source
8336         rs2[i]=(source[i]>>16)&0x1f; // subtract amount
8337         rt1[i]=(source[i]>>11)&0x1f; // destination
8338         rt2[i]=0;
8339         if(op2==0x2a||op2==0x2b) { // SLT/SLTU
8340           us1[i]=rs1[i];us2[i]=rs2[i];
8341         }
8342         else if(op2>=0x24&&op2<=0x27) { // AND/OR/XOR/NOR
8343           dep1[i]=rs1[i];dep2[i]=rs2[i];
8344         }
8345         else if(op2>=0x2c&&op2<=0x2f) { // DADD/DSUB
8346           dep1[i]=rs1[i];dep2[i]=rs2[i];
8347         }
8348         break;
8349       case MULTDIV:
8350         rs1[i]=(source[i]>>21)&0x1f; // source
8351         rs2[i]=(source[i]>>16)&0x1f; // divisor
8352         rt1[i]=HIREG;
8353         rt2[i]=LOREG;
8354         if (op2>=0x1c&&op2<=0x1f) { // DMULT/DMULTU/DDIV/DDIVU
8355           us1[i]=rs1[i];us2[i]=rs2[i];
8356         }
8357         break;
8358       case MOV:
8359         rs1[i]=0;
8360         rs2[i]=0;
8361         rt1[i]=0;
8362         rt2[i]=0;
8363         if(op2==0x10) rs1[i]=HIREG; // MFHI
8364         if(op2==0x11) rt1[i]=HIREG; // MTHI
8365         if(op2==0x12) rs1[i]=LOREG; // MFLO
8366         if(op2==0x13) rt1[i]=LOREG; // MTLO
8367         if((op2&0x1d)==0x10) rt1[i]=(source[i]>>11)&0x1f; // MFxx
8368         if((op2&0x1d)==0x11) rs1[i]=(source[i]>>21)&0x1f; // MTxx
8369         dep1[i]=rs1[i];
8370         break;
8371       case SHIFT:
8372         rs1[i]=(source[i]>>16)&0x1f; // target of shift
8373         rs2[i]=(source[i]>>21)&0x1f; // shift amount
8374         rt1[i]=(source[i]>>11)&0x1f; // destination
8375         rt2[i]=0;
8376         // DSLLV/DSRLV/DSRAV are 64-bit
8377         if(op2>=0x14&&op2<=0x17) us1[i]=rs1[i];
8378         break;
8379       case SHIFTIMM:
8380         rs1[i]=(source[i]>>16)&0x1f;
8381         rs2[i]=0;
8382         rt1[i]=(source[i]>>11)&0x1f;
8383         rt2[i]=0;
8384         imm[i]=(source[i]>>6)&0x1f;
8385         // DSxx32 instructions
8386         if(op2>=0x3c) imm[i]|=0x20;
8387         // DSLL/DSRL/DSRA/DSRA32/DSRL32 but not DSLL32 require 64-bit source
8388         if(op2>=0x38&&op2!=0x3c) us1[i]=rs1[i];
8389         break;
8390       case COP0:
8391         rs1[i]=0;
8392         rs2[i]=0;
8393         rt1[i]=0;
8394         rt2[i]=0;
8395         if(op2==0) rt1[i]=(source[i]>>16)&0x1F; // MFC0
8396         if(op2==4) rs1[i]=(source[i]>>16)&0x1F; // MTC0
8397         if(op2==4&&((source[i]>>11)&0x1f)==12) rt2[i]=CSREG; // Status
8398         if(op2==16) if((source[i]&0x3f)==0x18) rs2[i]=CCREG; // ERET
8399         break;
8400       case COP1:
8401       case COP2:
8402         rs1[i]=0;
8403         rs2[i]=0;
8404         rt1[i]=0;
8405         rt2[i]=0;
8406         if(op2<3) rt1[i]=(source[i]>>16)&0x1F; // MFC1/DMFC1/CFC1
8407         if(op2>3) rs1[i]=(source[i]>>16)&0x1F; // MTC1/DMTC1/CTC1
8408         if(op2==5) us1[i]=rs1[i]; // DMTC1
8409         rs2[i]=CSREG;
8410         break;
8411       case C1LS:
8412         rs1[i]=(source[i]>>21)&0x1F;
8413         rs2[i]=CSREG;
8414         rt1[i]=0;
8415         rt2[i]=0;
8416         imm[i]=(short)source[i];
8417         break;
8418       case C2LS:
8419         rs1[i]=(source[i]>>21)&0x1F;
8420         rs2[i]=0;
8421         rt1[i]=0;
8422         rt2[i]=0;
8423         imm[i]=(short)source[i];
8424         break;
8425       case FLOAT:
8426       case FCONV:
8427         rs1[i]=0;
8428         rs2[i]=CSREG;
8429         rt1[i]=0;
8430         rt2[i]=0;
8431         break;
8432       case FCOMP:
8433         rs1[i]=FSREG;
8434         rs2[i]=CSREG;
8435         rt1[i]=FSREG;
8436         rt2[i]=0;
8437         break;
8438       case SYSCALL:
8439       case HLECALL:
8440       case INTCALL:
8441         rs1[i]=CCREG;
8442         rs2[i]=0;
8443         rt1[i]=0;
8444         rt2[i]=0;
8445         break;
8446       default:
8447         rs1[i]=0;
8448         rs2[i]=0;
8449         rt1[i]=0;
8450         rt2[i]=0;
8451     }
8452     /* Calculate branch target addresses */
8453     if(type==UJUMP)
8454       ba[i]=((start+i*4+4)&0xF0000000)|(((unsigned int)source[i]<<6)>>4);
8455     else if(type==CJUMP&&rs1[i]==rs2[i]&&(op&1))
8456       ba[i]=start+i*4+8; // Ignore never taken branch
8457     else if(type==SJUMP&&rs1[i]==0&&!(op2&1))
8458       ba[i]=start+i*4+8; // Ignore never taken branch
8459     else if(type==CJUMP||type==SJUMP||type==FJUMP)
8460       ba[i]=start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14);
8461     else ba[i]=-1;
8462     /* Is this the end of the block? */
8463     if(i>0&&(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)) {
8464 #ifdef PCSX
8465       // check for link register access in delay slot
8466       int rt1_=rt1[i-1];
8467       if(rt1_!=0&&(rs1[i]==rt1_||rs2[i]==rt1_||rt1[i]==rt1_||rt2[i]==rt1_)) {
8468         printf("link access in delay slot @%08x (%08x)\n", addr + i*4, addr);
8469         ba[i-1]=-1;
8470         itype[i-1]=INTCALL;
8471         done=2;
8472       }
8473       else
8474 #endif
8475       if(rt1[i-1]==0) { // Continue past subroutine call (JAL)
8476         done=2;
8477       }
8478       else {
8479         if(stop_after_jal) done=1;
8480         // Stop on BREAK
8481         if((source[i+1]&0xfc00003f)==0x0d) done=1;
8482       }
8483       // Don't recompile stuff that's already compiled
8484       if(check_addr(start+i*4+4)) done=1;
8485       // Don't get too close to the limit
8486       if(i>MAXBLOCK/2) done=1;
8487     }
8488     if(itype[i]==SYSCALL&&stop_after_jal) done=1;
8489     if(itype[i]==HLECALL||itype[i]==INTCALL) done=2;
8490     if(done==2) {
8491       // Does the block continue due to a branch?
8492       for(j=i-1;j>=0;j--)
8493       {
8494         if(ba[j]==start+i*4+4) done=j=0;
8495         if(ba[j]==start+i*4+8) done=j=0;
8496       }
8497     }
8498     //assert(i<MAXBLOCK-1);
8499     if(start+i*4==pagelimit-4) done=1;
8500     assert(start+i*4<pagelimit);
8501     if (i==MAXBLOCK-1) done=1;
8502     // Stop if we're compiling junk
8503     if(itype[i]==NI&&opcode[i]==0x11) {
8504       done=stop_after_jal=1;
8505       printf("Disabled speculative precompilation\n");
8506     }
8507   }
8508   slen=i;
8509   if(itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==RJUMP||itype[i-1]==FJUMP) {
8510     if(start+i*4==pagelimit) {
8511       itype[i-1]=SPAN;
8512     }
8513   }
8514   assert(slen>0);
8515
8516   /* Pass 2 - Register dependencies and branch targets */
8517
8518   unneeded_registers(0,slen-1,0);
8519
8520   /* Pass 3 - Register allocation */
8521
8522   struct regstat current; // Current register allocations/status
8523   current.is32=1;
8524   current.dirty=0;
8525   current.u=unneeded_reg[0];
8526   current.uu=unneeded_reg_upper[0];
8527   clear_all_regs(current.regmap);
8528   alloc_reg(&current,0,CCREG);
8529   dirty_reg(&current,CCREG);
8530   current.isconst=0;
8531   current.wasconst=0;
8532   int ds=0;
8533   int cc=0;
8534   int hr;
8535
8536 #ifndef FORCE32
8537   provisional_32bit();
8538 #endif
8539   if((u_int)addr&1) {
8540     // First instruction is delay slot
8541     cc=-1;
8542     bt[1]=1;
8543     ds=1;
8544     unneeded_reg[0]=1;
8545     unneeded_reg_upper[0]=1;
8546     current.regmap[HOST_BTREG]=BTREG;
8547   }
8548
8549   for(i=0;i<slen;i++)
8550   {
8551     if(bt[i])
8552     {
8553       int hr;
8554       for(hr=0;hr<HOST_REGS;hr++)
8555       {
8556         // Is this really necessary?
8557         if(current.regmap[hr]==0) current.regmap[hr]=-1;
8558       }
8559       current.isconst=0;
8560     }
8561     if(i>1)
8562     {
8563       if((opcode[i-2]&0x2f)==0x05) // BNE/BNEL
8564       {
8565         if(rs1[i-2]==0||rs2[i-2]==0)
8566         {
8567           if(rs1[i-2]) {
8568             current.is32|=1LL<<rs1[i-2];
8569             int hr=get_reg(current.regmap,rs1[i-2]|64);
8570             if(hr>=0) current.regmap[hr]=-1;
8571           }
8572           if(rs2[i-2]) {
8573             current.is32|=1LL<<rs2[i-2];
8574             int hr=get_reg(current.regmap,rs2[i-2]|64);
8575             if(hr>=0) current.regmap[hr]=-1;
8576           }
8577         }
8578       }
8579     }
8580 #ifndef FORCE32
8581     // If something jumps here with 64-bit values
8582     // then promote those registers to 64 bits
8583     if(bt[i])
8584     {
8585       uint64_t temp_is32=current.is32;
8586       for(j=i-1;j>=0;j--)
8587       {
8588         if(ba[j]==start+i*4)
8589           temp_is32&=branch_regs[j].is32;
8590       }
8591       for(j=i;j<slen;j++)
8592       {
8593         if(ba[j]==start+i*4)
8594           //temp_is32=1;
8595           temp_is32&=p32[j];
8596       }
8597       if(temp_is32!=current.is32) {
8598         //printf("dumping 32-bit regs (%x)\n",start+i*4);
8599         #ifdef DESTRUCTIVE_WRITEBACK
8600         for(hr=0;hr<HOST_REGS;hr++)
8601         {
8602           int r=current.regmap[hr];
8603           if(r>0&&r<64)
8604           {
8605             if((current.dirty>>hr)&((current.is32&~temp_is32)>>r)&1) {
8606               temp_is32|=1LL<<r;
8607               //printf("restore %d\n",r);
8608             }
8609           }
8610         }
8611         #endif
8612         current.is32=temp_is32;
8613       }
8614     }
8615 #else
8616     current.is32=-1LL;
8617 #endif
8618
8619     memcpy(regmap_pre[i],current.regmap,sizeof(current.regmap));
8620     regs[i].wasconst=current.isconst;
8621     regs[i].was32=current.is32;
8622     regs[i].wasdirty=current.dirty;
8623     #if defined(DESTRUCTIVE_WRITEBACK) && !defined(FORCE32)
8624     // To change a dirty register from 32 to 64 bits, we must write
8625     // it out during the previous cycle (for branches, 2 cycles)
8626     if(i<slen-1&&bt[i+1]&&itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP)
8627     {
8628       uint64_t temp_is32=current.is32;
8629       for(j=i-1;j>=0;j--)
8630       {
8631         if(ba[j]==start+i*4+4)
8632           temp_is32&=branch_regs[j].is32;
8633       }
8634       for(j=i;j<slen;j++)
8635       {
8636         if(ba[j]==start+i*4+4)
8637           //temp_is32=1;
8638           temp_is32&=p32[j];
8639       }
8640       if(temp_is32!=current.is32) {
8641         //printf("pre-dumping 32-bit regs (%x)\n",start+i*4);
8642         for(hr=0;hr<HOST_REGS;hr++)
8643         {
8644           int r=current.regmap[hr];
8645           if(r>0)
8646           {
8647             if((current.dirty>>hr)&((current.is32&~temp_is32)>>(r&63))&1) {
8648               if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP)
8649               {
8650                 if(rs1[i]!=(r&63)&&rs2[i]!=(r&63))
8651                 {
8652                   //printf("dump %d/r%d\n",hr,r);
8653                   current.regmap[hr]=-1;
8654                   if(get_reg(current.regmap,r|64)>=0)
8655                     current.regmap[get_reg(current.regmap,r|64)]=-1;
8656                 }
8657               }
8658             }
8659           }
8660         }
8661       }
8662     }
8663     else if(i<slen-2&&bt[i+2]&&(source[i-1]>>16)!=0x1000&&(itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP))
8664     {
8665       uint64_t temp_is32=current.is32;
8666       for(j=i-1;j>=0;j--)
8667       {
8668         if(ba[j]==start+i*4+8)
8669           temp_is32&=branch_regs[j].is32;
8670       }
8671       for(j=i;j<slen;j++)
8672       {
8673         if(ba[j]==start+i*4+8)
8674           //temp_is32=1;
8675           temp_is32&=p32[j];
8676       }
8677       if(temp_is32!=current.is32) {
8678         //printf("pre-dumping 32-bit regs (%x)\n",start+i*4);
8679         for(hr=0;hr<HOST_REGS;hr++)
8680         {
8681           int r=current.regmap[hr];
8682           if(r>0)
8683           {
8684             if((current.dirty>>hr)&((current.is32&~temp_is32)>>(r&63))&1) {
8685               if(rs1[i]!=(r&63)&&rs2[i]!=(r&63)&&rs1[i+1]!=(r&63)&&rs2[i+1]!=(r&63))
8686               {
8687                 //printf("dump %d/r%d\n",hr,r);
8688                 current.regmap[hr]=-1;
8689                 if(get_reg(current.regmap,r|64)>=0)
8690                   current.regmap[get_reg(current.regmap,r|64)]=-1;
8691               }
8692             }
8693           }
8694         }
8695       }
8696     }
8697     #endif
8698     if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP) {
8699       if(i+1<slen) {
8700         current.u=unneeded_reg[i+1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
8701         current.uu=unneeded_reg_upper[i+1]&~((1LL<<us1[i])|(1LL<<us2[i]));
8702         if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
8703         current.u|=1;
8704         current.uu|=1;
8705       } else {
8706         current.u=1;
8707         current.uu=1;
8708       }
8709     } else {
8710       if(i+1<slen) {
8711         current.u=branch_unneeded_reg[i]&~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
8712         current.uu=branch_unneeded_reg_upper[i]&~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
8713         if((~current.uu>>rt1[i+1])&1) current.uu&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
8714         current.u&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
8715         current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
8716         current.u|=1;
8717         current.uu|=1;
8718       } else { printf("oops, branch at end of block with no delay slot\n");exit(1); }
8719     }
8720     is_ds[i]=ds;
8721     if(ds) {
8722       ds=0; // Skip delay slot, already allocated as part of branch
8723       // ...but we need to alloc it in case something jumps here
8724       if(i+1<slen) {
8725         current.u=branch_unneeded_reg[i-1]&unneeded_reg[i+1];
8726         current.uu=branch_unneeded_reg_upper[i-1]&unneeded_reg_upper[i+1];
8727       }else{
8728         current.u=branch_unneeded_reg[i-1];
8729         current.uu=branch_unneeded_reg_upper[i-1];
8730       }
8731       current.u&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
8732       current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
8733       if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
8734       current.u|=1;
8735       current.uu|=1;
8736       struct regstat temp;
8737       memcpy(&temp,&current,sizeof(current));
8738       temp.wasdirty=temp.dirty;
8739       temp.was32=temp.is32;
8740       // TODO: Take into account unconditional branches, as below
8741       delayslot_alloc(&temp,i);
8742       memcpy(regs[i].regmap,temp.regmap,sizeof(temp.regmap));
8743       regs[i].wasdirty=temp.wasdirty;
8744       regs[i].was32=temp.was32;
8745       regs[i].dirty=temp.dirty;
8746       regs[i].is32=temp.is32;
8747       regs[i].isconst=0;
8748       regs[i].wasconst=0;
8749       current.isconst=0;
8750       // Create entry (branch target) regmap
8751       for(hr=0;hr<HOST_REGS;hr++)
8752       {
8753         int r=temp.regmap[hr];
8754         if(r>=0) {
8755           if(r!=regmap_pre[i][hr]) {
8756             regs[i].regmap_entry[hr]=-1;
8757           }
8758           else
8759           {
8760             if(r<64){
8761               if((current.u>>r)&1) {
8762                 regs[i].regmap_entry[hr]=-1;
8763                 regs[i].regmap[hr]=-1;
8764                 //Don't clear regs in the delay slot as the branch might need them
8765                 //current.regmap[hr]=-1;
8766               }else
8767                 regs[i].regmap_entry[hr]=r;
8768             }
8769             else {
8770               if((current.uu>>(r&63))&1) {
8771                 regs[i].regmap_entry[hr]=-1;
8772                 regs[i].regmap[hr]=-1;
8773                 //Don't clear regs in the delay slot as the branch might need them
8774                 //current.regmap[hr]=-1;
8775               }else
8776                 regs[i].regmap_entry[hr]=r;
8777             }
8778           }
8779         } else {
8780           // First instruction expects CCREG to be allocated
8781           if(i==0&&hr==HOST_CCREG)
8782             regs[i].regmap_entry[hr]=CCREG;
8783           else
8784             regs[i].regmap_entry[hr]=-1;
8785         }
8786       }
8787     }
8788     else { // Not delay slot
8789       switch(itype[i]) {
8790         case UJUMP:
8791           //current.isconst=0; // DEBUG
8792           //current.wasconst=0; // DEBUG
8793           //regs[i].wasconst=0; // DEBUG
8794           clear_const(&current,rt1[i]);
8795           alloc_cc(&current,i);
8796           dirty_reg(&current,CCREG);
8797           if (rt1[i]==31) {
8798             alloc_reg(&current,i,31);
8799             dirty_reg(&current,31);
8800             assert(rs1[i+1]!=31&&rs2[i+1]!=31);
8801             assert(rt1[i+1]!=rt1[i]);
8802             #ifdef REG_PREFETCH
8803             alloc_reg(&current,i,PTEMP);
8804             #endif
8805             //current.is32|=1LL<<rt1[i];
8806           }
8807           ooo[i]=1;
8808           delayslot_alloc(&current,i+1);
8809           //current.isconst=0; // DEBUG
8810           ds=1;
8811           //printf("i=%d, isconst=%x\n",i,current.isconst);
8812           break;
8813         case RJUMP:
8814           //current.isconst=0;
8815           //current.wasconst=0;
8816           //regs[i].wasconst=0;
8817           clear_const(&current,rs1[i]);
8818           clear_const(&current,rt1[i]);
8819           alloc_cc(&current,i);
8820           dirty_reg(&current,CCREG);
8821           if(rs1[i]!=rt1[i+1]&&rs1[i]!=rt2[i+1]) {
8822             alloc_reg(&current,i,rs1[i]);
8823             if (rt1[i]!=0) {
8824               alloc_reg(&current,i,rt1[i]);
8825               dirty_reg(&current,rt1[i]);
8826               assert(rs1[i+1]!=rt1[i]&&rs2[i+1]!=rt1[i]);
8827               assert(rt1[i+1]!=rt1[i]);
8828               #ifdef REG_PREFETCH
8829               alloc_reg(&current,i,PTEMP);
8830               #endif
8831             }
8832             #ifdef USE_MINI_HT
8833             if(rs1[i]==31) { // JALR
8834               alloc_reg(&current,i,RHASH);
8835               #ifndef HOST_IMM_ADDR32
8836               alloc_reg(&current,i,RHTBL);
8837               #endif
8838             }
8839             #endif
8840             delayslot_alloc(&current,i+1);
8841           } else {
8842             // The delay slot overwrites our source register,
8843             // allocate a temporary register to hold the old value.
8844             current.isconst=0;
8845             current.wasconst=0;
8846             regs[i].wasconst=0;
8847             delayslot_alloc(&current,i+1);
8848             current.isconst=0;
8849             alloc_reg(&current,i,RTEMP);
8850           }
8851           //current.isconst=0; // DEBUG
8852           ooo[i]=1;
8853           ds=1;
8854           break;
8855         case CJUMP:
8856           //current.isconst=0;
8857           //current.wasconst=0;
8858           //regs[i].wasconst=0;
8859           clear_const(&current,rs1[i]);
8860           clear_const(&current,rs2[i]);
8861           if((opcode[i]&0x3E)==4) // BEQ/BNE
8862           {
8863             alloc_cc(&current,i);
8864             dirty_reg(&current,CCREG);
8865             if(rs1[i]) alloc_reg(&current,i,rs1[i]);
8866             if(rs2[i]) alloc_reg(&current,i,rs2[i]);
8867             if(!((current.is32>>rs1[i])&(current.is32>>rs2[i])&1))
8868             {
8869               if(rs1[i]) alloc_reg64(&current,i,rs1[i]);
8870               if(rs2[i]) alloc_reg64(&current,i,rs2[i]);
8871             }
8872             if((rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]))||
8873                (rs2[i]&&(rs2[i]==rt1[i+1]||rs2[i]==rt2[i+1]))) {
8874               // The delay slot overwrites one of our conditions.
8875               // Allocate the branch condition registers instead.
8876               current.isconst=0;
8877               current.wasconst=0;
8878               regs[i].wasconst=0;
8879               if(rs1[i]) alloc_reg(&current,i,rs1[i]);
8880               if(rs2[i]) alloc_reg(&current,i,rs2[i]);
8881               if(!((current.is32>>rs1[i])&(current.is32>>rs2[i])&1))
8882               {
8883                 if(rs1[i]) alloc_reg64(&current,i,rs1[i]);
8884                 if(rs2[i]) alloc_reg64(&current,i,rs2[i]);
8885               }
8886             }
8887             else
8888             {
8889               ooo[i]=1;
8890               delayslot_alloc(&current,i+1);
8891             }
8892           }
8893           else
8894           if((opcode[i]&0x3E)==6) // BLEZ/BGTZ
8895           {
8896             alloc_cc(&current,i);
8897             dirty_reg(&current,CCREG);
8898             alloc_reg(&current,i,rs1[i]);
8899             if(!(current.is32>>rs1[i]&1))
8900             {
8901               alloc_reg64(&current,i,rs1[i]);
8902             }
8903             if(rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1])) {
8904               // The delay slot overwrites one of our conditions.
8905               // Allocate the branch condition registers instead.
8906               current.isconst=0;
8907               current.wasconst=0;
8908               regs[i].wasconst=0;
8909               if(rs1[i]) alloc_reg(&current,i,rs1[i]);
8910               if(!((current.is32>>rs1[i])&1))
8911               {
8912                 if(rs1[i]) alloc_reg64(&current,i,rs1[i]);
8913               }
8914             }
8915             else
8916             {
8917               ooo[i]=1;
8918               delayslot_alloc(&current,i+1);
8919             }
8920           }
8921           else
8922           // Don't alloc the delay slot yet because we might not execute it
8923           if((opcode[i]&0x3E)==0x14) // BEQL/BNEL
8924           {
8925             current.isconst=0;
8926             current.wasconst=0;
8927             regs[i].wasconst=0;
8928             alloc_cc(&current,i);
8929             dirty_reg(&current,CCREG);
8930             alloc_reg(&current,i,rs1[i]);
8931             alloc_reg(&current,i,rs2[i]);
8932             if(!((current.is32>>rs1[i])&(current.is32>>rs2[i])&1))
8933             {
8934               alloc_reg64(&current,i,rs1[i]);
8935               alloc_reg64(&current,i,rs2[i]);
8936             }
8937           }
8938           else
8939           if((opcode[i]&0x3E)==0x16) // BLEZL/BGTZL
8940           {
8941             current.isconst=0;
8942             current.wasconst=0;
8943             regs[i].wasconst=0;
8944             alloc_cc(&current,i);
8945             dirty_reg(&current,CCREG);
8946             alloc_reg(&current,i,rs1[i]);
8947             if(!(current.is32>>rs1[i]&1))
8948             {
8949               alloc_reg64(&current,i,rs1[i]);
8950             }
8951           }
8952           ds=1;
8953           //current.isconst=0;
8954           break;
8955         case SJUMP:
8956           //current.isconst=0;
8957           //current.wasconst=0;
8958           //regs[i].wasconst=0;
8959           clear_const(&current,rs1[i]);
8960           clear_const(&current,rt1[i]);
8961           //if((opcode2[i]&0x1E)==0x0) // BLTZ/BGEZ
8962           if((opcode2[i]&0x0E)==0x0) // BLTZ/BGEZ
8963           {
8964             alloc_cc(&current,i);
8965             dirty_reg(&current,CCREG);
8966             alloc_reg(&current,i,rs1[i]);
8967             if(!(current.is32>>rs1[i]&1))
8968             {
8969               alloc_reg64(&current,i,rs1[i]);
8970             }
8971             if (rt1[i]==31) { // BLTZAL/BGEZAL
8972               alloc_reg(&current,i,31);
8973               dirty_reg(&current,31);
8974               //#ifdef REG_PREFETCH
8975               //alloc_reg(&current,i,PTEMP);
8976               //#endif
8977               //current.is32|=1LL<<rt1[i];
8978             }
8979             if((rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1])) // The delay slot overwrites the branch condition.
8980                ||(rt1[i]==31&&(rs1[i+1]==31||rs2[i+1]==31||rt1[i+1]==31||rt2[i+1]==31))) { // DS touches $ra
8981               // Allocate the branch condition registers instead.
8982               current.isconst=0;
8983               current.wasconst=0;
8984               regs[i].wasconst=0;
8985               if(rs1[i]) alloc_reg(&current,i,rs1[i]);
8986               if(!((current.is32>>rs1[i])&1))
8987               {
8988                 if(rs1[i]) alloc_reg64(&current,i,rs1[i]);
8989               }
8990             }
8991             else
8992             {
8993               ooo[i]=1;
8994               delayslot_alloc(&current,i+1);
8995             }
8996           }
8997           else
8998           // Don't alloc the delay slot yet because we might not execute it
8999           if((opcode2[i]&0x1E)==0x2) // BLTZL/BGEZL
9000           {
9001             current.isconst=0;
9002             current.wasconst=0;
9003             regs[i].wasconst=0;
9004             alloc_cc(&current,i);
9005             dirty_reg(&current,CCREG);
9006             alloc_reg(&current,i,rs1[i]);
9007             if(!(current.is32>>rs1[i]&1))
9008             {
9009               alloc_reg64(&current,i,rs1[i]);
9010             }
9011           }
9012           ds=1;
9013           //current.isconst=0;
9014           break;
9015         case FJUMP:
9016           current.isconst=0;
9017           current.wasconst=0;
9018           regs[i].wasconst=0;
9019           if(likely[i]==0) // BC1F/BC1T
9020           {
9021             // TODO: Theoretically we can run out of registers here on x86.
9022             // The delay slot can allocate up to six, and we need to check
9023             // CSREG before executing the delay slot.  Possibly we can drop
9024             // the cycle count and then reload it after checking that the
9025             // FPU is in a usable state, or don't do out-of-order execution.
9026             alloc_cc(&current,i);
9027             dirty_reg(&current,CCREG);
9028             alloc_reg(&current,i,FSREG);
9029             alloc_reg(&current,i,CSREG);
9030             if(itype[i+1]==FCOMP) {
9031               // The delay slot overwrites the branch condition.
9032               // Allocate the branch condition registers instead.
9033               alloc_cc(&current,i);
9034               dirty_reg(&current,CCREG);
9035               alloc_reg(&current,i,CSREG);
9036               alloc_reg(&current,i,FSREG);
9037             }
9038             else {
9039               ooo[i]=1;
9040               delayslot_alloc(&current,i+1);
9041               alloc_reg(&current,i+1,CSREG);
9042             }
9043           }
9044           else
9045           // Don't alloc the delay slot yet because we might not execute it
9046           if(likely[i]) // BC1FL/BC1TL
9047           {
9048             alloc_cc(&current,i);
9049             dirty_reg(&current,CCREG);
9050             alloc_reg(&current,i,CSREG);
9051             alloc_reg(&current,i,FSREG);
9052           }
9053           ds=1;
9054           current.isconst=0;
9055           break;
9056         case IMM16:
9057           imm16_alloc(&current,i);
9058           break;
9059         case LOAD:
9060         case LOADLR:
9061           load_alloc(&current,i);
9062           break;
9063         case STORE:
9064         case STORELR:
9065           store_alloc(&current,i);
9066           break;
9067         case ALU:
9068           alu_alloc(&current,i);
9069           break;
9070         case SHIFT:
9071           shift_alloc(&current,i);
9072           break;
9073         case MULTDIV:
9074           multdiv_alloc(&current,i);
9075           break;
9076         case SHIFTIMM:
9077           shiftimm_alloc(&current,i);
9078           break;
9079         case MOV:
9080           mov_alloc(&current,i);
9081           break;
9082         case COP0:
9083           cop0_alloc(&current,i);
9084           break;
9085         case COP1:
9086         case COP2:
9087           cop1_alloc(&current,i);
9088           break;
9089         case C1LS:
9090           c1ls_alloc(&current,i);
9091           break;
9092         case C2LS:
9093           c2ls_alloc(&current,i);
9094           break;
9095         case C2OP:
9096           c2op_alloc(&current,i);
9097           break;
9098         case FCONV:
9099           fconv_alloc(&current,i);
9100           break;
9101         case FLOAT:
9102           float_alloc(&current,i);
9103           break;
9104         case FCOMP:
9105           fcomp_alloc(&current,i);
9106           break;
9107         case SYSCALL:
9108         case HLECALL:
9109         case INTCALL:
9110           syscall_alloc(&current,i);
9111           break;
9112         case SPAN:
9113           pagespan_alloc(&current,i);
9114           break;
9115       }
9116
9117       // Drop the upper half of registers that have become 32-bit
9118       current.uu|=current.is32&((1LL<<rt1[i])|(1LL<<rt2[i]));
9119       if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP) {
9120         current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
9121         if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9122         current.uu|=1;
9123       } else {
9124         current.uu|=current.is32&((1LL<<rt1[i+1])|(1LL<<rt2[i+1]));
9125         current.uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
9126         if((~current.uu>>rt1[i+1])&1) current.uu&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
9127         current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
9128         current.uu|=1;
9129       }
9130
9131       // Create entry (branch target) regmap
9132       for(hr=0;hr<HOST_REGS;hr++)
9133       {
9134         int r,or,er;
9135         r=current.regmap[hr];
9136         if(r>=0) {
9137           if(r!=regmap_pre[i][hr]) {
9138             // TODO: delay slot (?)
9139             or=get_reg(regmap_pre[i],r); // Get old mapping for this register
9140             if(or<0||(r&63)>=TEMPREG){
9141               regs[i].regmap_entry[hr]=-1;
9142             }
9143             else
9144             {
9145               // Just move it to a different register
9146               regs[i].regmap_entry[hr]=r;
9147               // If it was dirty before, it's still dirty
9148               if((regs[i].wasdirty>>or)&1) dirty_reg(&current,r&63);
9149             }
9150           }
9151           else
9152           {
9153             // Unneeded
9154             if(r==0){
9155               regs[i].regmap_entry[hr]=0;
9156             }
9157             else
9158             if(r<64){
9159               if((current.u>>r)&1) {
9160                 regs[i].regmap_entry[hr]=-1;
9161                 //regs[i].regmap[hr]=-1;
9162                 current.regmap[hr]=-1;
9163               }else
9164                 regs[i].regmap_entry[hr]=r;
9165             }
9166             else {
9167               if((current.uu>>(r&63))&1) {
9168                 regs[i].regmap_entry[hr]=-1;
9169                 //regs[i].regmap[hr]=-1;
9170                 current.regmap[hr]=-1;
9171               }else
9172                 regs[i].regmap_entry[hr]=r;
9173             }
9174           }
9175         } else {
9176           // Branches expect CCREG to be allocated at the target
9177           if(regmap_pre[i][hr]==CCREG)
9178             regs[i].regmap_entry[hr]=CCREG;
9179           else
9180             regs[i].regmap_entry[hr]=-1;
9181         }
9182       }
9183       memcpy(regs[i].regmap,current.regmap,sizeof(current.regmap));
9184     }
9185     /* Branch post-alloc */
9186     if(i>0)
9187     {
9188       current.was32=current.is32;
9189       current.wasdirty=current.dirty;
9190       switch(itype[i-1]) {
9191         case UJUMP:
9192           memcpy(&branch_regs[i-1],&current,sizeof(current));
9193           branch_regs[i-1].isconst=0;
9194           branch_regs[i-1].wasconst=0;
9195           branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1]));
9196           branch_regs[i-1].uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i-1])|(1LL<<us2[i-1]));
9197           alloc_cc(&branch_regs[i-1],i-1);
9198           dirty_reg(&branch_regs[i-1],CCREG);
9199           if(rt1[i-1]==31) { // JAL
9200             alloc_reg(&branch_regs[i-1],i-1,31);
9201             dirty_reg(&branch_regs[i-1],31);
9202             branch_regs[i-1].is32|=1LL<<31;
9203           }
9204           memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9205           memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9206           break;
9207         case RJUMP:
9208           memcpy(&branch_regs[i-1],&current,sizeof(current));
9209           branch_regs[i-1].isconst=0;
9210           branch_regs[i-1].wasconst=0;
9211           branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1]));
9212           branch_regs[i-1].uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i-1])|(1LL<<us2[i-1]));
9213           alloc_cc(&branch_regs[i-1],i-1);
9214           dirty_reg(&branch_regs[i-1],CCREG);
9215           alloc_reg(&branch_regs[i-1],i-1,rs1[i-1]);
9216           if(rt1[i-1]!=0) { // JALR
9217             alloc_reg(&branch_regs[i-1],i-1,rt1[i-1]);
9218             dirty_reg(&branch_regs[i-1],rt1[i-1]);
9219             branch_regs[i-1].is32|=1LL<<rt1[i-1];
9220           }
9221           #ifdef USE_MINI_HT
9222           if(rs1[i-1]==31) { // JALR
9223             alloc_reg(&branch_regs[i-1],i-1,RHASH);
9224             #ifndef HOST_IMM_ADDR32
9225             alloc_reg(&branch_regs[i-1],i-1,RHTBL);
9226             #endif
9227           }
9228           #endif
9229           memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9230           memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9231           break;
9232         case CJUMP:
9233           if((opcode[i-1]&0x3E)==4) // BEQ/BNE
9234           {
9235             alloc_cc(&current,i-1);
9236             dirty_reg(&current,CCREG);
9237             if((rs1[i-1]&&(rs1[i-1]==rt1[i]||rs1[i-1]==rt2[i]))||
9238                (rs2[i-1]&&(rs2[i-1]==rt1[i]||rs2[i-1]==rt2[i]))) {
9239               // The delay slot overwrote one of our conditions
9240               // Delay slot goes after the test (in order)
9241               current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
9242               current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i]));
9243               if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9244               current.u|=1;
9245               current.uu|=1;
9246               delayslot_alloc(&current,i);
9247               current.isconst=0;
9248             }
9249             else
9250             {
9251               current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1]));
9252               current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i-1])|(1LL<<us2[i-1]));
9253               // Alloc the branch condition registers
9254               if(rs1[i-1]) alloc_reg(&current,i-1,rs1[i-1]);
9255               if(rs2[i-1]) alloc_reg(&current,i-1,rs2[i-1]);
9256               if(!((current.is32>>rs1[i-1])&(current.is32>>rs2[i-1])&1))
9257               {
9258                 if(rs1[i-1]) alloc_reg64(&current,i-1,rs1[i-1]);
9259                 if(rs2[i-1]) alloc_reg64(&current,i-1,rs2[i-1]);
9260               }
9261             }
9262             memcpy(&branch_regs[i-1],&current,sizeof(current));
9263             branch_regs[i-1].isconst=0;
9264             branch_regs[i-1].wasconst=0;
9265             memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
9266             memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9267           }
9268           else
9269           if((opcode[i-1]&0x3E)==6) // BLEZ/BGTZ
9270           {
9271             alloc_cc(&current,i-1);
9272             dirty_reg(&current,CCREG);
9273             if(rs1[i-1]==rt1[i]||rs1[i-1]==rt2[i]) {
9274               // The delay slot overwrote the branch condition
9275               // Delay slot goes after the test (in order)
9276               current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
9277               current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i]));
9278               if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9279               current.u|=1;
9280               current.uu|=1;
9281               delayslot_alloc(&current,i);
9282               current.isconst=0;
9283             }
9284             else
9285             {
9286               current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]);
9287               current.uu=branch_unneeded_reg_upper[i-1]&~(1LL<<us1[i-1]);
9288               // Alloc the branch condition register
9289               alloc_reg(&current,i-1,rs1[i-1]);
9290               if(!(current.is32>>rs1[i-1]&1))
9291               {
9292                 alloc_reg64(&current,i-1,rs1[i-1]);
9293               }
9294             }
9295             memcpy(&branch_regs[i-1],&current,sizeof(current));
9296             branch_regs[i-1].isconst=0;
9297             branch_regs[i-1].wasconst=0;
9298             memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
9299             memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9300           }
9301           else
9302           // Alloc the delay slot in case the branch is taken
9303           if((opcode[i-1]&0x3E)==0x14) // BEQL/BNEL
9304           {
9305             memcpy(&branch_regs[i-1],&current,sizeof(current));
9306             branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9307             branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9308             if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9309             alloc_cc(&branch_regs[i-1],i);
9310             dirty_reg(&branch_regs[i-1],CCREG);
9311             delayslot_alloc(&branch_regs[i-1],i);
9312             branch_regs[i-1].isconst=0;
9313             alloc_reg(&current,i,CCREG); // Not taken path
9314             dirty_reg(&current,CCREG);
9315             memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9316           }
9317           else
9318           if((opcode[i-1]&0x3E)==0x16) // BLEZL/BGTZL
9319           {
9320             memcpy(&branch_regs[i-1],&current,sizeof(current));
9321             branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9322             branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9323             if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9324             alloc_cc(&branch_regs[i-1],i);
9325             dirty_reg(&branch_regs[i-1],CCREG);
9326             delayslot_alloc(&branch_regs[i-1],i);
9327             branch_regs[i-1].isconst=0;
9328             alloc_reg(&current,i,CCREG); // Not taken path
9329             dirty_reg(&current,CCREG);
9330             memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9331           }
9332           break;
9333         case SJUMP:
9334           //if((opcode2[i-1]&0x1E)==0) // BLTZ/BGEZ
9335           if((opcode2[i-1]&0x0E)==0) // BLTZ/BGEZ
9336           {
9337             alloc_cc(&current,i-1);
9338             dirty_reg(&current,CCREG);
9339             if(rs1[i-1]==rt1[i]||rs1[i-1]==rt2[i]) {
9340               // The delay slot overwrote the branch condition
9341               // Delay slot goes after the test (in order)
9342               current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
9343               current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i]));
9344               if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9345               current.u|=1;
9346               current.uu|=1;
9347               delayslot_alloc(&current,i);
9348               current.isconst=0;
9349             }
9350             else
9351             {
9352               current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]);
9353               current.uu=branch_unneeded_reg_upper[i-1]&~(1LL<<us1[i-1]);
9354               // Alloc the branch condition register
9355               alloc_reg(&current,i-1,rs1[i-1]);
9356               if(!(current.is32>>rs1[i-1]&1))
9357               {
9358                 alloc_reg64(&current,i-1,rs1[i-1]);
9359               }
9360             }
9361             memcpy(&branch_regs[i-1],&current,sizeof(current));
9362             branch_regs[i-1].isconst=0;
9363             branch_regs[i-1].wasconst=0;
9364             memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
9365             memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9366           }
9367           else
9368           // Alloc the delay slot in case the branch is taken
9369           if((opcode2[i-1]&0x1E)==2) // BLTZL/BGEZL
9370           {
9371             memcpy(&branch_regs[i-1],&current,sizeof(current));
9372             branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9373             branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9374             if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9375             alloc_cc(&branch_regs[i-1],i);
9376             dirty_reg(&branch_regs[i-1],CCREG);
9377             delayslot_alloc(&branch_regs[i-1],i);
9378             branch_regs[i-1].isconst=0;
9379             alloc_reg(&current,i,CCREG); // Not taken path
9380             dirty_reg(&current,CCREG);
9381             memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9382           }
9383           // FIXME: BLTZAL/BGEZAL
9384           if(opcode2[i-1]&0x10) { // BxxZAL
9385             alloc_reg(&branch_regs[i-1],i-1,31);
9386             dirty_reg(&branch_regs[i-1],31);
9387             branch_regs[i-1].is32|=1LL<<31;
9388           }
9389           break;
9390         case FJUMP:
9391           if(likely[i-1]==0) // BC1F/BC1T
9392           {
9393             alloc_cc(&current,i-1);
9394             dirty_reg(&current,CCREG);
9395             if(itype[i]==FCOMP) {
9396               // The delay slot overwrote the branch condition
9397               // Delay slot goes after the test (in order)
9398               delayslot_alloc(&current,i);
9399               current.isconst=0;
9400             }
9401             else
9402             {
9403               current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]);
9404               current.uu=branch_unneeded_reg_upper[i-1]&~(1LL<<us1[i-1]);
9405               // Alloc the branch condition register
9406               alloc_reg(&current,i-1,FSREG);
9407             }
9408             memcpy(&branch_regs[i-1],&current,sizeof(current));
9409             memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
9410           }
9411           else // BC1FL/BC1TL
9412           {
9413             // Alloc the delay slot in case the branch is taken
9414             memcpy(&branch_regs[i-1],&current,sizeof(current));
9415             branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9416             branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9417             if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9418             alloc_cc(&branch_regs[i-1],i);
9419             dirty_reg(&branch_regs[i-1],CCREG);
9420             delayslot_alloc(&branch_regs[i-1],i);
9421             branch_regs[i-1].isconst=0;
9422             alloc_reg(&current,i,CCREG); // Not taken path
9423             dirty_reg(&current,CCREG);
9424             memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9425           }
9426           break;
9427       }
9428
9429       if(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)
9430       {
9431         if(rt1[i-1]==31) // JAL/JALR
9432         {
9433           // Subroutine call will return here, don't alloc any registers
9434           current.is32=1;
9435           current.dirty=0;
9436           clear_all_regs(current.regmap);
9437           alloc_reg(&current,i,CCREG);
9438           dirty_reg(&current,CCREG);
9439         }
9440         else if(i+1<slen)
9441         {
9442           // Internal branch will jump here, match registers to caller
9443           current.is32=0x3FFFFFFFFLL;
9444           current.dirty=0;
9445           clear_all_regs(current.regmap);
9446           alloc_reg(&current,i,CCREG);
9447           dirty_reg(&current,CCREG);
9448           for(j=i-1;j>=0;j--)
9449           {
9450             if(ba[j]==start+i*4+4) {
9451               memcpy(current.regmap,branch_regs[j].regmap,sizeof(current.regmap));
9452               current.is32=branch_regs[j].is32;
9453               current.dirty=branch_regs[j].dirty;
9454               break;
9455             }
9456           }
9457           while(j>=0) {
9458             if(ba[j]==start+i*4+4) {
9459               for(hr=0;hr<HOST_REGS;hr++) {
9460                 if(current.regmap[hr]!=branch_regs[j].regmap[hr]) {
9461                   current.regmap[hr]=-1;
9462                 }
9463                 current.is32&=branch_regs[j].is32;
9464                 current.dirty&=branch_regs[j].dirty;
9465               }
9466             }
9467             j--;
9468           }
9469         }
9470       }
9471     }
9472
9473     // Count cycles in between branches
9474     ccadj[i]=cc;
9475     if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP||itype[i]==SYSCALL||itype[i]==HLECALL))
9476     {
9477       cc=0;
9478     }
9479     else
9480     {
9481       cc++;
9482     }
9483
9484     flush_dirty_uppers(&current);
9485     if(!is_ds[i]) {
9486       regs[i].is32=current.is32;
9487       regs[i].dirty=current.dirty;
9488       regs[i].isconst=current.isconst;
9489       memcpy(constmap[i],current.constmap,sizeof(current.constmap));
9490     }
9491     for(hr=0;hr<HOST_REGS;hr++) {
9492       if(hr!=EXCLUDE_REG&&regs[i].regmap[hr]>=0) {
9493         if(regmap_pre[i][hr]!=regs[i].regmap[hr]) {
9494           regs[i].wasconst&=~(1<<hr);
9495         }
9496       }
9497     }
9498     if(current.regmap[HOST_BTREG]==BTREG) current.regmap[HOST_BTREG]=-1;
9499   }
9500
9501   /* Pass 4 - Cull unused host registers */
9502
9503   uint64_t nr=0;
9504
9505   for (i=slen-1;i>=0;i--)
9506   {
9507     int hr;
9508     if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
9509     {
9510       if(ba[i]<start || ba[i]>=(start+slen*4))
9511       {
9512         // Branch out of this block, don't need anything
9513         nr=0;
9514       }
9515       else
9516       {
9517         // Internal branch
9518         // Need whatever matches the target
9519         nr=0;
9520         int t=(ba[i]-start)>>2;
9521         for(hr=0;hr<HOST_REGS;hr++)
9522         {
9523           if(regs[i].regmap_entry[hr]>=0) {
9524             if(regs[i].regmap_entry[hr]==regs[t].regmap_entry[hr]) nr|=1<<hr;
9525           }
9526         }
9527       }
9528       // Conditional branch may need registers for following instructions
9529       if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
9530       {
9531         if(i<slen-2) {
9532           nr|=needed_reg[i+2];
9533           for(hr=0;hr<HOST_REGS;hr++)
9534           {
9535             if(regmap_pre[i+2][hr]>=0&&get_reg(regs[i+2].regmap_entry,regmap_pre[i+2][hr])<0) nr&=~(1<<hr);
9536             //if((regmap_entry[i+2][hr])>=0) if(!((nr>>hr)&1)) printf("%x-bogus(%d=%d)\n",start+i*4,hr,regmap_entry[i+2][hr]);
9537           }
9538         }
9539       }
9540       // Don't need stuff which is overwritten
9541       if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr);
9542       if(regs[i].regmap[hr]<0) nr&=~(1<<hr);
9543       // Merge in delay slot
9544       for(hr=0;hr<HOST_REGS;hr++)
9545       {
9546         if(!likely[i]) {
9547           // These are overwritten unless the branch is "likely"
9548           // and the delay slot is nullified if not taken
9549           if(rt1[i+1]&&rt1[i+1]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9550           if(rt2[i+1]&&rt2[i+1]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9551         }
9552         if(us1[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9553         if(us2[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9554         if(rs1[i+1]==regmap_pre[i][hr]) nr|=1<<hr;
9555         if(rs2[i+1]==regmap_pre[i][hr]) nr|=1<<hr;
9556         if(us1[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9557         if(us2[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9558         if(rs1[i+1]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9559         if(rs2[i+1]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9560         if(dep1[i+1]&&!((unneeded_reg_upper[i]>>dep1[i+1])&1)) {
9561           if(dep1[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9562           if(dep2[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9563         }
9564         if(dep2[i+1]&&!((unneeded_reg_upper[i]>>dep2[i+1])&1)) {
9565           if(dep1[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9566           if(dep2[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9567         }
9568         if(itype[i+1]==STORE || itype[i+1]==STORELR || (opcode[i+1]&0x3b)==0x39 || (opcode[i+1]&0x3b)==0x3a) {
9569           if(regmap_pre[i][hr]==INVCP) nr|=1<<hr;
9570           if(regs[i].regmap_entry[hr]==INVCP) nr|=1<<hr;
9571         }
9572       }
9573     }
9574     else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
9575     {
9576       // SYSCALL instruction (software interrupt)
9577       nr=0;
9578     }
9579     else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
9580     {
9581       // ERET instruction (return from interrupt)
9582       nr=0;
9583     }
9584     else // Non-branch
9585     {
9586       if(i<slen-1) {
9587         for(hr=0;hr<HOST_REGS;hr++) {
9588           if(regmap_pre[i+1][hr]>=0&&get_reg(regs[i+1].regmap_entry,regmap_pre[i+1][hr])<0) nr&=~(1<<hr);
9589           if(regs[i].regmap[hr]!=regmap_pre[i+1][hr]) nr&=~(1<<hr);
9590           if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr);
9591           if(regs[i].regmap[hr]<0) nr&=~(1<<hr);
9592         }
9593       }
9594     }
9595     for(hr=0;hr<HOST_REGS;hr++)
9596     {
9597       // Overwritten registers are not needed
9598       if(rt1[i]&&rt1[i]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9599       if(rt2[i]&&rt2[i]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9600       if(FTEMP==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9601       // Source registers are needed
9602       if(us1[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9603       if(us2[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9604       if(rs1[i]==regmap_pre[i][hr]) nr|=1<<hr;
9605       if(rs2[i]==regmap_pre[i][hr]) nr|=1<<hr;
9606       if(us1[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9607       if(us2[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9608       if(rs1[i]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9609       if(rs2[i]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9610       if(dep1[i]&&!((unneeded_reg_upper[i]>>dep1[i])&1)) {
9611         if(dep1[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9612         if(dep1[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9613       }
9614       if(dep2[i]&&!((unneeded_reg_upper[i]>>dep2[i])&1)) {
9615         if(dep2[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9616         if(dep2[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9617       }
9618       if(itype[i]==STORE || itype[i]==STORELR || (opcode[i]&0x3b)==0x39 || (opcode[i]&0x3b)==0x3a) {
9619         if(regmap_pre[i][hr]==INVCP) nr|=1<<hr;
9620         if(regs[i].regmap_entry[hr]==INVCP) nr|=1<<hr;
9621       }
9622       // Don't store a register immediately after writing it,
9623       // may prevent dual-issue.
9624       // But do so if this is a branch target, otherwise we
9625       // might have to load the register before the branch.
9626       if(i>0&&!bt[i]&&((regs[i].wasdirty>>hr)&1)) {
9627         if((regmap_pre[i][hr]>0&&regmap_pre[i][hr]<64&&!((unneeded_reg[i]>>regmap_pre[i][hr])&1)) ||
9628            (regmap_pre[i][hr]>64&&!((unneeded_reg_upper[i]>>(regmap_pre[i][hr]&63))&1)) ) {
9629           if(rt1[i-1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9630           if(rt2[i-1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9631         }
9632         if((regs[i].regmap_entry[hr]>0&&regs[i].regmap_entry[hr]<64&&!((unneeded_reg[i]>>regs[i].regmap_entry[hr])&1)) ||
9633            (regs[i].regmap_entry[hr]>64&&!((unneeded_reg_upper[i]>>(regs[i].regmap_entry[hr]&63))&1)) ) {
9634           if(rt1[i-1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9635           if(rt2[i-1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9636         }
9637       }
9638     }
9639     // Cycle count is needed at branches.  Assume it is needed at the target too.
9640     if(i==0||bt[i]||itype[i]==CJUMP||itype[i]==FJUMP||itype[i]==SPAN) {
9641       if(regmap_pre[i][HOST_CCREG]==CCREG) nr|=1<<HOST_CCREG;
9642       if(regs[i].regmap_entry[HOST_CCREG]==CCREG) nr|=1<<HOST_CCREG;
9643     }
9644     // Save it
9645     needed_reg[i]=nr;
9646
9647     // Deallocate unneeded registers
9648     for(hr=0;hr<HOST_REGS;hr++)
9649     {
9650       if(!((nr>>hr)&1)) {
9651         if(regs[i].regmap_entry[hr]!=CCREG) regs[i].regmap_entry[hr]=-1;
9652         if((regs[i].regmap[hr]&63)!=rs1[i] && (regs[i].regmap[hr]&63)!=rs2[i] &&
9653            (regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] &&
9654            (regs[i].regmap[hr]&63)!=PTEMP && (regs[i].regmap[hr]&63)!=CCREG)
9655         {
9656           if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
9657           {
9658             if(likely[i]) {
9659               regs[i].regmap[hr]=-1;
9660               regs[i].isconst&=~(1<<hr);
9661               if(i<slen-2) regmap_pre[i+2][hr]=-1;
9662             }
9663           }
9664         }
9665         if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
9666         {
9667           int d1=0,d2=0,map=0,temp=0;
9668           if(get_reg(regs[i].regmap,rt1[i+1]|64)>=0||get_reg(branch_regs[i].regmap,rt1[i+1]|64)>=0)
9669           {
9670             d1=dep1[i+1];
9671             d2=dep2[i+1];
9672           }
9673           if(using_tlb) {
9674             if(itype[i+1]==LOAD || itype[i+1]==LOADLR ||
9675                itype[i+1]==STORE || itype[i+1]==STORELR ||
9676                itype[i+1]==C1LS || itype[i+1]==C2LS)
9677             map=TLREG;
9678           } else
9679           if(itype[i+1]==STORE || itype[i+1]==STORELR ||
9680              (opcode[i+1]&0x3b)==0x39 || (opcode[i+1]&0x3b)==0x3a) { // SWC1/SDC1 || SWC2/SDC2
9681             map=INVCP;
9682           }
9683           if(itype[i+1]==LOADLR || itype[i+1]==STORELR ||
9684              itype[i+1]==C1LS || itype[i+1]==C2LS)
9685             temp=FTEMP;
9686           if((regs[i].regmap[hr]&63)!=rs1[i] && (regs[i].regmap[hr]&63)!=rs2[i] &&
9687              (regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] &&
9688              (regs[i].regmap[hr]&63)!=rt1[i+1] && (regs[i].regmap[hr]&63)!=rt2[i+1] &&
9689              (regs[i].regmap[hr]^64)!=us1[i+1] && (regs[i].regmap[hr]^64)!=us2[i+1] &&
9690              (regs[i].regmap[hr]^64)!=d1 && (regs[i].regmap[hr]^64)!=d2 &&
9691              regs[i].regmap[hr]!=rs1[i+1] && regs[i].regmap[hr]!=rs2[i+1] &&
9692              (regs[i].regmap[hr]&63)!=temp && regs[i].regmap[hr]!=PTEMP &&
9693              regs[i].regmap[hr]!=RHASH && regs[i].regmap[hr]!=RHTBL &&
9694              regs[i].regmap[hr]!=RTEMP && regs[i].regmap[hr]!=CCREG &&
9695              regs[i].regmap[hr]!=map )
9696           {
9697             regs[i].regmap[hr]=-1;
9698             regs[i].isconst&=~(1<<hr);
9699             if((branch_regs[i].regmap[hr]&63)!=rs1[i] && (branch_regs[i].regmap[hr]&63)!=rs2[i] &&
9700                (branch_regs[i].regmap[hr]&63)!=rt1[i] && (branch_regs[i].regmap[hr]&63)!=rt2[i] &&
9701                (branch_regs[i].regmap[hr]&63)!=rt1[i+1] && (branch_regs[i].regmap[hr]&63)!=rt2[i+1] &&
9702                (branch_regs[i].regmap[hr]^64)!=us1[i+1] && (branch_regs[i].regmap[hr]^64)!=us2[i+1] &&
9703                (branch_regs[i].regmap[hr]^64)!=d1 && (branch_regs[i].regmap[hr]^64)!=d2 &&
9704                branch_regs[i].regmap[hr]!=rs1[i+1] && branch_regs[i].regmap[hr]!=rs2[i+1] &&
9705                (branch_regs[i].regmap[hr]&63)!=temp && branch_regs[i].regmap[hr]!=PTEMP &&
9706                branch_regs[i].regmap[hr]!=RHASH && branch_regs[i].regmap[hr]!=RHTBL &&
9707                branch_regs[i].regmap[hr]!=RTEMP && branch_regs[i].regmap[hr]!=CCREG &&
9708                branch_regs[i].regmap[hr]!=map)
9709             {
9710               branch_regs[i].regmap[hr]=-1;
9711               branch_regs[i].regmap_entry[hr]=-1;
9712               if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
9713               {
9714                 if(!likely[i]&&i<slen-2) {
9715                   regmap_pre[i+2][hr]=-1;
9716                 }
9717               }
9718             }
9719           }
9720         }
9721         else
9722         {
9723           // Non-branch
9724           if(i>0)
9725           {
9726             int d1=0,d2=0,map=-1,temp=-1;
9727             if(get_reg(regs[i].regmap,rt1[i]|64)>=0)
9728             {
9729               d1=dep1[i];
9730               d2=dep2[i];
9731             }
9732             if(using_tlb) {
9733               if(itype[i]==LOAD || itype[i]==LOADLR ||
9734                  itype[i]==STORE || itype[i]==STORELR ||
9735                  itype[i]==C1LS || itype[i]==C2LS)
9736               map=TLREG;
9737             } else if(itype[i]==STORE || itype[i]==STORELR ||
9738                       (opcode[i]&0x3b)==0x39 || (opcode[i]&0x3b)==0x3a) { // SWC1/SDC1 || SWC2/SDC2
9739               map=INVCP;
9740             }
9741             if(itype[i]==LOADLR || itype[i]==STORELR ||
9742                itype[i]==C1LS || itype[i]==C2LS)
9743               temp=FTEMP;
9744             if((regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] &&
9745                (regs[i].regmap[hr]^64)!=us1[i] && (regs[i].regmap[hr]^64)!=us2[i] &&
9746                (regs[i].regmap[hr]^64)!=d1 && (regs[i].regmap[hr]^64)!=d2 &&
9747                regs[i].regmap[hr]!=rs1[i] && regs[i].regmap[hr]!=rs2[i] &&
9748                (regs[i].regmap[hr]&63)!=temp && regs[i].regmap[hr]!=map &&
9749                (itype[i]!=SPAN||regs[i].regmap[hr]!=CCREG))
9750             {
9751               if(i<slen-1&&!is_ds[i]) {
9752                 if(regmap_pre[i+1][hr]!=-1 || regs[i].regmap[hr]!=-1)
9753                 if(regmap_pre[i+1][hr]!=regs[i].regmap[hr])
9754                 if(regs[i].regmap[hr]<64||!((regs[i].was32>>(regs[i].regmap[hr]&63))&1))
9755                 {
9756                   printf("fail: %x (%d %d!=%d)\n",start+i*4,hr,regmap_pre[i+1][hr],regs[i].regmap[hr]);
9757                   assert(regmap_pre[i+1][hr]==regs[i].regmap[hr]);
9758                 }
9759                 regmap_pre[i+1][hr]=-1;
9760                 if(regs[i+1].regmap_entry[hr]==CCREG) regs[i+1].regmap_entry[hr]=-1;
9761               }
9762               regs[i].regmap[hr]=-1;
9763               regs[i].isconst&=~(1<<hr);
9764             }
9765           }
9766         }
9767       }
9768     }
9769   }
9770
9771   /* Pass 5 - Pre-allocate registers */
9772
9773   // If a register is allocated during a loop, try to allocate it for the
9774   // entire loop, if possible.  This avoids loading/storing registers
9775   // inside of the loop.
9776
9777   signed char f_regmap[HOST_REGS];
9778   clear_all_regs(f_regmap);
9779   for(i=0;i<slen-1;i++)
9780   {
9781     if(itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
9782     {
9783       if(ba[i]>=start && ba[i]<(start+i*4))
9784       if(itype[i+1]==NOP||itype[i+1]==MOV||itype[i+1]==ALU
9785       ||itype[i+1]==SHIFTIMM||itype[i+1]==IMM16||itype[i+1]==LOAD
9786       ||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS
9787       ||itype[i+1]==SHIFT||itype[i+1]==COP1||itype[i+1]==FLOAT
9788       ||itype[i+1]==FCOMP||itype[i+1]==FCONV
9789       ||itype[i+1]==COP2||itype[i+1]==C2LS||itype[i+1]==C2OP)
9790       {
9791         int t=(ba[i]-start)>>2;
9792         if(t>0&&(itype[t-1]!=UJUMP&&itype[t-1]!=RJUMP&&itype[t-1]!=CJUMP&&itype[t-1]!=SJUMP&&itype[t-1]!=FJUMP)) // loop_preload can't handle jumps into delay slots
9793         if(t<2||(itype[t-2]!=UJUMP)) // call/ret assumes no registers allocated
9794         for(hr=0;hr<HOST_REGS;hr++)
9795         {
9796           if(regs[i].regmap[hr]>64) {
9797             if(!((regs[i].dirty>>hr)&1))
9798               f_regmap[hr]=regs[i].regmap[hr];
9799             else f_regmap[hr]=-1;
9800           }
9801           else if(regs[i].regmap[hr]>=0) {
9802             if(f_regmap[hr]!=regs[i].regmap[hr]) {
9803               // dealloc old register
9804               int n;
9805               for(n=0;n<HOST_REGS;n++)
9806               {
9807                 if(f_regmap[n]==regs[i].regmap[hr]) {f_regmap[n]=-1;}
9808               }
9809               // and alloc new one
9810               f_regmap[hr]=regs[i].regmap[hr];
9811             }
9812           }
9813           if(branch_regs[i].regmap[hr]>64) {
9814             if(!((branch_regs[i].dirty>>hr)&1))
9815               f_regmap[hr]=branch_regs[i].regmap[hr];
9816             else f_regmap[hr]=-1;
9817           }
9818           else if(branch_regs[i].regmap[hr]>=0) {
9819             if(f_regmap[hr]!=branch_regs[i].regmap[hr]) {
9820               // dealloc old register
9821               int n;
9822               for(n=0;n<HOST_REGS;n++)
9823               {
9824                 if(f_regmap[n]==branch_regs[i].regmap[hr]) {f_regmap[n]=-1;}
9825               }
9826               // and alloc new one
9827               f_regmap[hr]=branch_regs[i].regmap[hr];
9828             }
9829           }
9830           if(ooo[i]) {
9831             if(count_free_regs(regs[i].regmap)<=minimum_free_regs[i+1])
9832               f_regmap[hr]=branch_regs[i].regmap[hr];
9833           }else{
9834             if(count_free_regs(branch_regs[i].regmap)<=minimum_free_regs[i+1])
9835               f_regmap[hr]=branch_regs[i].regmap[hr];
9836           }
9837           // Avoid dirty->clean transition
9838           #ifdef DESTRUCTIVE_WRITEBACK
9839           if(t>0) if(get_reg(regmap_pre[t],f_regmap[hr])>=0) if((regs[t].wasdirty>>get_reg(regmap_pre[t],f_regmap[hr]))&1) f_regmap[hr]=-1;
9840           #endif
9841           // This check is only strictly required in the DESTRUCTIVE_WRITEBACK
9842           // case above, however it's always a good idea.  We can't hoist the
9843           // load if the register was already allocated, so there's no point
9844           // wasting time analyzing most of these cases.  It only "succeeds"
9845           // when the mapping was different and the load can be replaced with
9846           // a mov, which is of negligible benefit.  So such cases are
9847           // skipped below.
9848           if(f_regmap[hr]>0) {
9849             if(regs[t].regmap_entry[hr]<0&&get_reg(regmap_pre[t],f_regmap[hr])<0) {
9850               int r=f_regmap[hr];
9851               for(j=t;j<=i;j++)
9852               {
9853                 //printf("Test %x -> %x, %x %d/%d\n",start+i*4,ba[i],start+j*4,hr,r);
9854                 if(r<34&&((unneeded_reg[j]>>r)&1)) break;
9855                 if(r>63&&((unneeded_reg_upper[j]>>(r&63))&1)) break;
9856                 if(r>63) {
9857                   // NB This can exclude the case where the upper-half
9858                   // register is lower numbered than the lower-half
9859                   // register.  Not sure if it's worth fixing...
9860                   if(get_reg(regs[j].regmap,r&63)<0) break;
9861                   if(get_reg(regs[j].regmap_entry,r&63)<0) break;
9862                   if(regs[j].is32&(1LL<<(r&63))) break;
9863                 }
9864                 if(regs[j].regmap[hr]==f_regmap[hr]&&(f_regmap[hr]&63)<TEMPREG) {
9865                   //printf("Hit %x -> %x, %x %d/%d\n",start+i*4,ba[i],start+j*4,hr,r);
9866                   int k;
9867                   if(regs[i].regmap[hr]==-1&&branch_regs[i].regmap[hr]==-1) {
9868                     if(get_reg(regs[i+2].regmap,f_regmap[hr])>=0) break;
9869                     if(r>63) {
9870                       if(get_reg(regs[i].regmap,r&63)<0) break;
9871                       if(get_reg(branch_regs[i].regmap,r&63)<0) break;
9872                     }
9873                     k=i;
9874                     while(k>1&&regs[k-1].regmap[hr]==-1) {
9875                       if(count_free_regs(regs[k-1].regmap)<=minimum_free_regs[k-1]) {
9876                         //printf("no free regs for store %x\n",start+(k-1)*4);
9877                         break;
9878                       }
9879                       if(get_reg(regs[k-1].regmap,f_regmap[hr])>=0) {
9880                         //printf("no-match due to different register\n");
9881                         break;
9882                       }
9883                       if(itype[k-2]==UJUMP||itype[k-2]==RJUMP||itype[k-2]==CJUMP||itype[k-2]==SJUMP||itype[k-2]==FJUMP) {
9884                         //printf("no-match due to branch\n");
9885                         break;
9886                       }
9887                       // call/ret fast path assumes no registers allocated
9888                       if(k>2&&(itype[k-3]==UJUMP||itype[k-3]==RJUMP)) {
9889                         break;
9890                       }
9891                       if(r>63) {
9892                         // NB This can exclude the case where the upper-half
9893                         // register is lower numbered than the lower-half
9894                         // register.  Not sure if it's worth fixing...
9895                         if(get_reg(regs[k-1].regmap,r&63)<0) break;
9896                         if(regs[k-1].is32&(1LL<<(r&63))) break;
9897                       }
9898                       k--;
9899                     }
9900                     if(i<slen-1) {
9901                       if((regs[k].is32&(1LL<<f_regmap[hr]))!=
9902                         (regs[i+2].was32&(1LL<<f_regmap[hr]))) {
9903                         //printf("bad match after branch\n");
9904                         break;
9905                       }
9906                     }
9907                     if(regs[k-1].regmap[hr]==f_regmap[hr]&&regmap_pre[k][hr]==f_regmap[hr]) {
9908                       //printf("Extend r%d, %x ->\n",hr,start+k*4);
9909                       while(k<i) {
9910                         regs[k].regmap_entry[hr]=f_regmap[hr];
9911                         regs[k].regmap[hr]=f_regmap[hr];
9912                         regmap_pre[k+1][hr]=f_regmap[hr];
9913                         regs[k].wasdirty&=~(1<<hr);
9914                         regs[k].dirty&=~(1<<hr);
9915                         regs[k].wasdirty|=(1<<hr)&regs[k-1].dirty;
9916                         regs[k].dirty|=(1<<hr)&regs[k].wasdirty;
9917                         regs[k].wasconst&=~(1<<hr);
9918                         regs[k].isconst&=~(1<<hr);
9919                         k++;
9920                       }
9921                     }
9922                     else {
9923                       //printf("Fail Extend r%d, %x ->\n",hr,start+k*4);
9924                       break;
9925                     }
9926                     assert(regs[i-1].regmap[hr]==f_regmap[hr]);
9927                     if(regs[i-1].regmap[hr]==f_regmap[hr]&&regmap_pre[i][hr]==f_regmap[hr]) {
9928                       //printf("OK fill %x (r%d)\n",start+i*4,hr);
9929                       regs[i].regmap_entry[hr]=f_regmap[hr];
9930                       regs[i].regmap[hr]=f_regmap[hr];
9931                       regs[i].wasdirty&=~(1<<hr);
9932                       regs[i].dirty&=~(1<<hr);
9933                       regs[i].wasdirty|=(1<<hr)&regs[i-1].dirty;
9934                       regs[i].dirty|=(1<<hr)&regs[i-1].dirty;
9935                       regs[i].wasconst&=~(1<<hr);
9936                       regs[i].isconst&=~(1<<hr);
9937                       branch_regs[i].regmap_entry[hr]=f_regmap[hr];
9938                       branch_regs[i].wasdirty&=~(1<<hr);
9939                       branch_regs[i].wasdirty|=(1<<hr)&regs[i].dirty;
9940                       branch_regs[i].regmap[hr]=f_regmap[hr];
9941                       branch_regs[i].dirty&=~(1<<hr);
9942                       branch_regs[i].dirty|=(1<<hr)&regs[i].dirty;
9943                       branch_regs[i].wasconst&=~(1<<hr);
9944                       branch_regs[i].isconst&=~(1<<hr);
9945                       if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000) {
9946                         regmap_pre[i+2][hr]=f_regmap[hr];
9947                         regs[i+2].wasdirty&=~(1<<hr);
9948                         regs[i+2].wasdirty|=(1<<hr)&regs[i].dirty;
9949                         assert((branch_regs[i].is32&(1LL<<f_regmap[hr]))==
9950                           (regs[i+2].was32&(1LL<<f_regmap[hr])));
9951                       }
9952                     }
9953                   }
9954                   for(k=t;k<j;k++) {
9955                     // Alloc register clean at beginning of loop,
9956                     // but may dirty it in pass 6
9957                     regs[k].regmap_entry[hr]=f_regmap[hr];
9958                     regs[k].regmap[hr]=f_regmap[hr];
9959                     regs[k].dirty&=~(1<<hr);
9960                     regs[k].wasconst&=~(1<<hr);
9961                     regs[k].isconst&=~(1<<hr);
9962                     if(itype[k]==UJUMP||itype[k]==RJUMP||itype[k]==CJUMP||itype[k]==SJUMP||itype[k]==FJUMP) {
9963                       branch_regs[k].regmap_entry[hr]=f_regmap[hr];
9964                       branch_regs[k].regmap[hr]=f_regmap[hr];
9965                       branch_regs[k].dirty&=~(1<<hr);
9966                       branch_regs[k].wasconst&=~(1<<hr);
9967                       branch_regs[k].isconst&=~(1<<hr);
9968                       if(itype[k]!=RJUMP&&itype[k]!=UJUMP&&(source[k]>>16)!=0x1000) {
9969                         regmap_pre[k+2][hr]=f_regmap[hr];
9970                         regs[k+2].wasdirty&=~(1<<hr);
9971                         assert((branch_regs[k].is32&(1LL<<f_regmap[hr]))==
9972                           (regs[k+2].was32&(1LL<<f_regmap[hr])));
9973                       }
9974                     }
9975                     else
9976                     {
9977                       regmap_pre[k+1][hr]=f_regmap[hr];
9978                       regs[k+1].wasdirty&=~(1<<hr);
9979                     }
9980                   }
9981                   if(regs[j].regmap[hr]==f_regmap[hr])
9982                     regs[j].regmap_entry[hr]=f_regmap[hr];
9983                   break;
9984                 }
9985                 if(j==i) break;
9986                 if(regs[j].regmap[hr]>=0)
9987                   break;
9988                 if(get_reg(regs[j].regmap,f_regmap[hr])>=0) {
9989                   //printf("no-match due to different register\n");
9990                   break;
9991                 }
9992                 if((regs[j+1].is32&(1LL<<f_regmap[hr]))!=(regs[j].is32&(1LL<<f_regmap[hr]))) {
9993                   //printf("32/64 mismatch %x %d\n",start+j*4,hr);
9994                   break;
9995                 }
9996                 if(itype[j]==UJUMP||itype[j]==RJUMP||(source[j]>>16)==0x1000)
9997                 {
9998                   // Stop on unconditional branch
9999                   break;
10000                 }
10001                 if(itype[j]==CJUMP||itype[j]==SJUMP||itype[j]==FJUMP)
10002                 {
10003                   if(ooo[j]) {
10004                     if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j+1])
10005                       break;
10006                   }else{
10007                     if(count_free_regs(branch_regs[j].regmap)<=minimum_free_regs[j+1])
10008                       break;
10009                   }
10010                   if(get_reg(branch_regs[j].regmap,f_regmap[hr])>=0) {
10011                     //printf("no-match due to different register (branch)\n");
10012                     break;
10013                   }
10014                 }
10015                 if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j]) {
10016                   //printf("No free regs for store %x\n",start+j*4);
10017                   break;
10018                 }
10019                 if(f_regmap[hr]>=64) {
10020                   if(regs[j].is32&(1LL<<(f_regmap[hr]&63))) {
10021                     break;
10022                   }
10023                   else
10024                   {
10025                     if(get_reg(regs[j].regmap,f_regmap[hr]&63)<0) {
10026                       break;
10027                     }
10028                   }
10029                 }
10030               }
10031             }
10032           }
10033         }
10034       }
10035     }else{
10036       int count=0;
10037       for(hr=0;hr<HOST_REGS;hr++)
10038       {
10039         if(hr!=EXCLUDE_REG) {
10040           if(regs[i].regmap[hr]>64) {
10041             if(!((regs[i].dirty>>hr)&1))
10042               f_regmap[hr]=regs[i].regmap[hr];
10043           }
10044           else if(regs[i].regmap[hr]>=0) {
10045             if(f_regmap[hr]!=regs[i].regmap[hr]) {
10046               // dealloc old register
10047               int n;
10048               for(n=0;n<HOST_REGS;n++)
10049               {
10050                 if(f_regmap[n]==regs[i].regmap[hr]) {f_regmap[n]=-1;}
10051               }
10052               // and alloc new one
10053               f_regmap[hr]=regs[i].regmap[hr];
10054             }
10055           }
10056           else if(regs[i].regmap[hr]<0) count++;
10057         }
10058       }
10059       // Try to restore cycle count at branch targets
10060       if(bt[i]) {
10061         for(j=i;j<slen-1;j++) {
10062           if(regs[j].regmap[HOST_CCREG]!=-1) break;
10063           if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j]) {
10064             //printf("no free regs for store %x\n",start+j*4);
10065             break;
10066           }
10067         }
10068         if(regs[j].regmap[HOST_CCREG]==CCREG) {
10069           int k=i;
10070           //printf("Extend CC, %x -> %x\n",start+k*4,start+j*4);
10071           while(k<j) {
10072             regs[k].regmap_entry[HOST_CCREG]=CCREG;
10073             regs[k].regmap[HOST_CCREG]=CCREG;
10074             regmap_pre[k+1][HOST_CCREG]=CCREG;
10075             regs[k+1].wasdirty|=1<<HOST_CCREG;
10076             regs[k].dirty|=1<<HOST_CCREG;
10077             regs[k].wasconst&=~(1<<HOST_CCREG);
10078             regs[k].isconst&=~(1<<HOST_CCREG);
10079             k++;
10080           }
10081           regs[j].regmap_entry[HOST_CCREG]=CCREG;
10082         }
10083         // Work backwards from the branch target
10084         if(j>i&&f_regmap[HOST_CCREG]==CCREG)
10085         {
10086           //printf("Extend backwards\n");
10087           int k;
10088           k=i;
10089           while(regs[k-1].regmap[HOST_CCREG]==-1) {
10090             if(count_free_regs(regs[k-1].regmap)<=minimum_free_regs[k-1]) {
10091               //printf("no free regs for store %x\n",start+(k-1)*4);
10092               break;
10093             }
10094             k--;
10095           }
10096           if(regs[k-1].regmap[HOST_CCREG]==CCREG) {
10097             //printf("Extend CC, %x ->\n",start+k*4);
10098             while(k<=i) {
10099               regs[k].regmap_entry[HOST_CCREG]=CCREG;
10100               regs[k].regmap[HOST_CCREG]=CCREG;
10101               regmap_pre[k+1][HOST_CCREG]=CCREG;
10102               regs[k+1].wasdirty|=1<<HOST_CCREG;
10103               regs[k].dirty|=1<<HOST_CCREG;
10104               regs[k].wasconst&=~(1<<HOST_CCREG);
10105               regs[k].isconst&=~(1<<HOST_CCREG);
10106               k++;
10107             }
10108           }
10109           else {
10110             //printf("Fail Extend CC, %x ->\n",start+k*4);
10111           }
10112         }
10113       }
10114       if(itype[i]!=STORE&&itype[i]!=STORELR&&itype[i]!=C1LS&&itype[i]!=SHIFT&&
10115          itype[i]!=NOP&&itype[i]!=MOV&&itype[i]!=ALU&&itype[i]!=SHIFTIMM&&
10116          itype[i]!=IMM16&&itype[i]!=LOAD&&itype[i]!=COP1&&itype[i]!=FLOAT&&
10117          itype[i]!=FCONV&&itype[i]!=FCOMP)
10118       {
10119         memcpy(f_regmap,regs[i].regmap,sizeof(f_regmap));
10120       }
10121     }
10122   }
10123
10124   // This allocates registers (if possible) one instruction prior
10125   // to use, which can avoid a load-use penalty on certain CPUs.
10126   for(i=0;i<slen-1;i++)
10127   {
10128     if(!i||(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP))
10129     {
10130       if(!bt[i+1])
10131       {
10132         if(itype[i]==ALU||itype[i]==MOV||itype[i]==LOAD||itype[i]==SHIFTIMM||itype[i]==IMM16
10133            ||((itype[i]==COP1||itype[i]==COP2)&&opcode2[i]<3))
10134         {
10135           if(rs1[i+1]) {
10136             if((hr=get_reg(regs[i+1].regmap,rs1[i+1]))>=0)
10137             {
10138               if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10139               {
10140                 regs[i].regmap[hr]=regs[i+1].regmap[hr];
10141                 regmap_pre[i+1][hr]=regs[i+1].regmap[hr];
10142                 regs[i+1].regmap_entry[hr]=regs[i+1].regmap[hr];
10143                 regs[i].isconst&=~(1<<hr);
10144                 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10145                 constmap[i][hr]=constmap[i+1][hr];
10146                 regs[i+1].wasdirty&=~(1<<hr);
10147                 regs[i].dirty&=~(1<<hr);
10148               }
10149             }
10150           }
10151           if(rs2[i+1]) {
10152             if((hr=get_reg(regs[i+1].regmap,rs2[i+1]))>=0)
10153             {
10154               if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10155               {
10156                 regs[i].regmap[hr]=regs[i+1].regmap[hr];
10157                 regmap_pre[i+1][hr]=regs[i+1].regmap[hr];
10158                 regs[i+1].regmap_entry[hr]=regs[i+1].regmap[hr];
10159                 regs[i].isconst&=~(1<<hr);
10160                 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10161                 constmap[i][hr]=constmap[i+1][hr];
10162                 regs[i+1].wasdirty&=~(1<<hr);
10163                 regs[i].dirty&=~(1<<hr);
10164               }
10165             }
10166           }
10167           if(itype[i+1]==LOAD&&rs1[i+1]&&get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10168             if((hr=get_reg(regs[i+1].regmap,rt1[i+1]))>=0)
10169             {
10170               if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10171               {
10172                 regs[i].regmap[hr]=rs1[i+1];
10173                 regmap_pre[i+1][hr]=rs1[i+1];
10174                 regs[i+1].regmap_entry[hr]=rs1[i+1];
10175                 regs[i].isconst&=~(1<<hr);
10176                 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10177                 constmap[i][hr]=constmap[i+1][hr];
10178                 regs[i+1].wasdirty&=~(1<<hr);
10179                 regs[i].dirty&=~(1<<hr);
10180               }
10181             }
10182           }
10183           if(lt1[i+1]&&get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10184             if((hr=get_reg(regs[i+1].regmap,rt1[i+1]))>=0)
10185             {
10186               if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10187               {
10188                 regs[i].regmap[hr]=rs1[i+1];
10189                 regmap_pre[i+1][hr]=rs1[i+1];
10190                 regs[i+1].regmap_entry[hr]=rs1[i+1];
10191                 regs[i].isconst&=~(1<<hr);
10192                 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10193                 constmap[i][hr]=constmap[i+1][hr];
10194                 regs[i+1].wasdirty&=~(1<<hr);
10195                 regs[i].dirty&=~(1<<hr);
10196               }
10197             }
10198           }
10199           #ifndef HOST_IMM_ADDR32
10200           if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS||itype[i+1]==C2LS) {
10201             hr=get_reg(regs[i+1].regmap,TLREG);
10202             if(hr>=0) {
10203               int sr=get_reg(regs[i+1].regmap,rs1[i+1]);
10204               if(sr>=0&&((regs[i+1].wasconst>>sr)&1)) {
10205                 int nr;
10206                 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10207                 {
10208                   regs[i].regmap[hr]=MGEN1+((i+1)&1);
10209                   regmap_pre[i+1][hr]=MGEN1+((i+1)&1);
10210                   regs[i+1].regmap_entry[hr]=MGEN1+((i+1)&1);
10211                   regs[i].isconst&=~(1<<hr);
10212                   regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10213                   constmap[i][hr]=constmap[i+1][hr];
10214                   regs[i+1].wasdirty&=~(1<<hr);
10215                   regs[i].dirty&=~(1<<hr);
10216                 }
10217                 else if((nr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1))>=0)
10218                 {
10219                   // move it to another register
10220                   regs[i+1].regmap[hr]=-1;
10221                   regmap_pre[i+2][hr]=-1;
10222                   regs[i+1].regmap[nr]=TLREG;
10223                   regmap_pre[i+2][nr]=TLREG;
10224                   regs[i].regmap[nr]=MGEN1+((i+1)&1);
10225                   regmap_pre[i+1][nr]=MGEN1+((i+1)&1);
10226                   regs[i+1].regmap_entry[nr]=MGEN1+((i+1)&1);
10227                   regs[i].isconst&=~(1<<nr);
10228                   regs[i+1].isconst&=~(1<<nr);
10229                   regs[i].dirty&=~(1<<nr);
10230                   regs[i+1].wasdirty&=~(1<<nr);
10231                   regs[i+1].dirty&=~(1<<nr);
10232                   regs[i+2].wasdirty&=~(1<<nr);
10233                 }
10234               }
10235             }
10236           }
10237           #endif
10238           if(itype[i+1]==STORE||itype[i+1]==STORELR
10239              ||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a) { // SB/SH/SW/SD/SWC1/SDC1/SWC2/SDC2
10240             if(get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10241               hr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1);
10242               if(hr<0) hr=get_reg(regs[i+1].regmap,-1);
10243               else {regs[i+1].regmap[hr]=AGEN1+((i+1)&1);regs[i+1].isconst&=~(1<<hr);}
10244               assert(hr>=0);
10245               if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10246               {
10247                 regs[i].regmap[hr]=rs1[i+1];
10248                 regmap_pre[i+1][hr]=rs1[i+1];
10249                 regs[i+1].regmap_entry[hr]=rs1[i+1];
10250                 regs[i].isconst&=~(1<<hr);
10251                 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10252                 constmap[i][hr]=constmap[i+1][hr];
10253                 regs[i+1].wasdirty&=~(1<<hr);
10254                 regs[i].dirty&=~(1<<hr);
10255               }
10256             }
10257           }
10258           if(itype[i+1]==LOADLR||(opcode[i+1]&0x3b)==0x31||(opcode[i+1]&0x3b)==0x32) { // LWC1/LDC1, LWC2/LDC2
10259             if(get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10260               int nr;
10261               hr=get_reg(regs[i+1].regmap,FTEMP);
10262               assert(hr>=0);
10263               if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10264               {
10265                 regs[i].regmap[hr]=rs1[i+1];
10266                 regmap_pre[i+1][hr]=rs1[i+1];
10267                 regs[i+1].regmap_entry[hr]=rs1[i+1];
10268                 regs[i].isconst&=~(1<<hr);
10269                 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10270                 constmap[i][hr]=constmap[i+1][hr];
10271                 regs[i+1].wasdirty&=~(1<<hr);
10272                 regs[i].dirty&=~(1<<hr);
10273               }
10274               else if((nr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1))>=0)
10275               {
10276                 // move it to another register
10277                 regs[i+1].regmap[hr]=-1;
10278                 regmap_pre[i+2][hr]=-1;
10279                 regs[i+1].regmap[nr]=FTEMP;
10280                 regmap_pre[i+2][nr]=FTEMP;
10281                 regs[i].regmap[nr]=rs1[i+1];
10282                 regmap_pre[i+1][nr]=rs1[i+1];
10283                 regs[i+1].regmap_entry[nr]=rs1[i+1];
10284                 regs[i].isconst&=~(1<<nr);
10285                 regs[i+1].isconst&=~(1<<nr);
10286                 regs[i].dirty&=~(1<<nr);
10287                 regs[i+1].wasdirty&=~(1<<nr);
10288                 regs[i+1].dirty&=~(1<<nr);
10289                 regs[i+2].wasdirty&=~(1<<nr);
10290               }
10291             }
10292           }
10293           if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR/*||itype[i+1]==C1LS||||itype[i+1]==C2LS*/) {
10294             if(itype[i+1]==LOAD)
10295               hr=get_reg(regs[i+1].regmap,rt1[i+1]);
10296             if(itype[i+1]==LOADLR||(opcode[i+1]&0x3b)==0x31||(opcode[i+1]&0x3b)==0x32) // LWC1/LDC1, LWC2/LDC2
10297               hr=get_reg(regs[i+1].regmap,FTEMP);
10298             if(itype[i+1]==STORE||itype[i+1]==STORELR||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a) { // SWC1/SDC1/SWC2/SDC2
10299               hr=get_reg(regs[i+1].regmap,AGEN1+((i+1)&1));
10300               if(hr<0) hr=get_reg(regs[i+1].regmap,-1);
10301             }
10302             if(hr>=0&&regs[i].regmap[hr]<0) {
10303               int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
10304               if(rs>=0&&((regs[i+1].wasconst>>rs)&1)) {
10305                 regs[i].regmap[hr]=AGEN1+((i+1)&1);
10306                 regmap_pre[i+1][hr]=AGEN1+((i+1)&1);
10307                 regs[i+1].regmap_entry[hr]=AGEN1+((i+1)&1);
10308                 regs[i].isconst&=~(1<<hr);
10309                 regs[i+1].wasdirty&=~(1<<hr);
10310                 regs[i].dirty&=~(1<<hr);
10311               }
10312             }
10313           }
10314         }
10315       }
10316     }
10317   }
10318
10319   /* Pass 6 - Optimize clean/dirty state */
10320   clean_registers(0,slen-1,1);
10321
10322   /* Pass 7 - Identify 32-bit registers */
10323 #ifndef FORCE32
10324   provisional_r32();
10325
10326   u_int r32=0;
10327
10328   for (i=slen-1;i>=0;i--)
10329   {
10330     int hr;
10331     if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
10332     {
10333       if(ba[i]<start || ba[i]>=(start+slen*4))
10334       {
10335         // Branch out of this block, don't need anything
10336         r32=0;
10337       }
10338       else
10339       {
10340         // Internal branch
10341         // Need whatever matches the target
10342         // (and doesn't get overwritten by the delay slot instruction)
10343         r32=0;
10344         int t=(ba[i]-start)>>2;
10345         if(ba[i]>start+i*4) {
10346           // Forward branch
10347           if(!(requires_32bit[t]&~regs[i].was32))
10348             r32|=requires_32bit[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
10349         }else{
10350           // Backward branch
10351           //if(!(regs[t].was32&~unneeded_reg_upper[t]&~regs[i].was32))
10352           //  r32|=regs[t].was32&~unneeded_reg_upper[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
10353           if(!(pr32[t]&~regs[i].was32))
10354             r32|=pr32[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
10355         }
10356       }
10357       // Conditional branch may need registers for following instructions
10358       if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
10359       {
10360         if(i<slen-2) {
10361           r32|=requires_32bit[i+2];
10362           r32&=regs[i].was32;
10363           // Mark this address as a branch target since it may be called
10364           // upon return from interrupt
10365           bt[i+2]=1;
10366         }
10367       }
10368       // Merge in delay slot
10369       if(!likely[i]) {
10370         // These are overwritten unless the branch is "likely"
10371         // and the delay slot is nullified if not taken
10372         r32&=~(1LL<<rt1[i+1]);
10373         r32&=~(1LL<<rt2[i+1]);
10374       }
10375       // Assume these are needed (delay slot)
10376       if(us1[i+1]>0)
10377       {
10378         if((regs[i].was32>>us1[i+1])&1) r32|=1LL<<us1[i+1];
10379       }
10380       if(us2[i+1]>0)
10381       {
10382         if((regs[i].was32>>us2[i+1])&1) r32|=1LL<<us2[i+1];
10383       }
10384       if(dep1[i+1]&&!((unneeded_reg_upper[i]>>dep1[i+1])&1))
10385       {
10386         if((regs[i].was32>>dep1[i+1])&1) r32|=1LL<<dep1[i+1];
10387       }
10388       if(dep2[i+1]&&!((unneeded_reg_upper[i]>>dep2[i+1])&1))
10389       {
10390         if((regs[i].was32>>dep2[i+1])&1) r32|=1LL<<dep2[i+1];
10391       }
10392     }
10393     else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
10394     {
10395       // SYSCALL instruction (software interrupt)
10396       r32=0;
10397     }
10398     else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
10399     {
10400       // ERET instruction (return from interrupt)
10401       r32=0;
10402     }
10403     // Check 32 bits
10404     r32&=~(1LL<<rt1[i]);
10405     r32&=~(1LL<<rt2[i]);
10406     if(us1[i]>0)
10407     {
10408       if((regs[i].was32>>us1[i])&1) r32|=1LL<<us1[i];
10409     }
10410     if(us2[i]>0)
10411     {
10412       if((regs[i].was32>>us2[i])&1) r32|=1LL<<us2[i];
10413     }
10414     if(dep1[i]&&!((unneeded_reg_upper[i]>>dep1[i])&1))
10415     {
10416       if((regs[i].was32>>dep1[i])&1) r32|=1LL<<dep1[i];
10417     }
10418     if(dep2[i]&&!((unneeded_reg_upper[i]>>dep2[i])&1))
10419     {
10420       if((regs[i].was32>>dep2[i])&1) r32|=1LL<<dep2[i];
10421     }
10422     requires_32bit[i]=r32;
10423
10424     // Dirty registers which are 32-bit, require 32-bit input
10425     // as they will be written as 32-bit values
10426     for(hr=0;hr<HOST_REGS;hr++)
10427     {
10428       if(regs[i].regmap_entry[hr]>0&&regs[i].regmap_entry[hr]<64) {
10429         if((regs[i].was32>>regs[i].regmap_entry[hr])&(regs[i].wasdirty>>hr)&1) {
10430           if(!((unneeded_reg_upper[i]>>regs[i].regmap_entry[hr])&1))
10431           requires_32bit[i]|=1LL<<regs[i].regmap_entry[hr];
10432         }
10433       }
10434     }
10435     //requires_32bit[i]=is32[i]&~unneeded_reg_upper[i]; // DEBUG
10436   }
10437 #endif
10438
10439   if(itype[slen-1]==SPAN) {
10440     bt[slen-1]=1; // Mark as a branch target so instruction can restart after exception
10441   }
10442
10443   /* Debug/disassembly */
10444   if((void*)assem_debug==(void*)printf)
10445   for(i=0;i<slen;i++)
10446   {
10447     printf("U:");
10448     int r;
10449     for(r=1;r<=CCREG;r++) {
10450       if((unneeded_reg[i]>>r)&1) {
10451         if(r==HIREG) printf(" HI");
10452         else if(r==LOREG) printf(" LO");
10453         else printf(" r%d",r);
10454       }
10455     }
10456 #ifndef FORCE32
10457     printf(" UU:");
10458     for(r=1;r<=CCREG;r++) {
10459       if(((unneeded_reg_upper[i]&~unneeded_reg[i])>>r)&1) {
10460         if(r==HIREG) printf(" HI");
10461         else if(r==LOREG) printf(" LO");
10462         else printf(" r%d",r);
10463       }
10464     }
10465     printf(" 32:");
10466     for(r=0;r<=CCREG;r++) {
10467       //if(((is32[i]>>r)&(~unneeded_reg[i]>>r))&1) {
10468       if((regs[i].was32>>r)&1) {
10469         if(r==CCREG) printf(" CC");
10470         else if(r==HIREG) printf(" HI");
10471         else if(r==LOREG) printf(" LO");
10472         else printf(" r%d",r);
10473       }
10474     }
10475 #endif
10476     printf("\n");
10477     #if defined(__i386__) || defined(__x86_64__)
10478     printf("pre: eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",regmap_pre[i][0],regmap_pre[i][1],regmap_pre[i][2],regmap_pre[i][3],regmap_pre[i][5],regmap_pre[i][6],regmap_pre[i][7]);
10479     #endif
10480     #ifdef __arm__
10481     printf("pre: r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d\n",regmap_pre[i][0],regmap_pre[i][1],regmap_pre[i][2],regmap_pre[i][3],regmap_pre[i][4],regmap_pre[i][5],regmap_pre[i][6],regmap_pre[i][7],regmap_pre[i][8],regmap_pre[i][9],regmap_pre[i][10],regmap_pre[i][12]);
10482     #endif
10483     printf("needs: ");
10484     if(needed_reg[i]&1) printf("eax ");
10485     if((needed_reg[i]>>1)&1) printf("ecx ");
10486     if((needed_reg[i]>>2)&1) printf("edx ");
10487     if((needed_reg[i]>>3)&1) printf("ebx ");
10488     if((needed_reg[i]>>5)&1) printf("ebp ");
10489     if((needed_reg[i]>>6)&1) printf("esi ");
10490     if((needed_reg[i]>>7)&1) printf("edi ");
10491     printf("r:");
10492     for(r=0;r<=CCREG;r++) {
10493       //if(((requires_32bit[i]>>r)&(~unneeded_reg[i]>>r))&1) {
10494       if((requires_32bit[i]>>r)&1) {
10495         if(r==CCREG) printf(" CC");
10496         else if(r==HIREG) printf(" HI");
10497         else if(r==LOREG) printf(" LO");
10498         else printf(" r%d",r);
10499       }
10500     }
10501     printf("\n");
10502     /*printf("pr:");
10503     for(r=0;r<=CCREG;r++) {
10504       //if(((requires_32bit[i]>>r)&(~unneeded_reg[i]>>r))&1) {
10505       if((pr32[i]>>r)&1) {
10506         if(r==CCREG) printf(" CC");
10507         else if(r==HIREG) printf(" HI");
10508         else if(r==LOREG) printf(" LO");
10509         else printf(" r%d",r);
10510       }
10511     }
10512     if(pr32[i]!=requires_32bit[i]) printf(" OOPS");
10513     printf("\n");*/
10514     #if defined(__i386__) || defined(__x86_64__)
10515     printf("entry: eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",regs[i].regmap_entry[0],regs[i].regmap_entry[1],regs[i].regmap_entry[2],regs[i].regmap_entry[3],regs[i].regmap_entry[5],regs[i].regmap_entry[6],regs[i].regmap_entry[7]);
10516     printf("dirty: ");
10517     if(regs[i].wasdirty&1) printf("eax ");
10518     if((regs[i].wasdirty>>1)&1) printf("ecx ");
10519     if((regs[i].wasdirty>>2)&1) printf("edx ");
10520     if((regs[i].wasdirty>>3)&1) printf("ebx ");
10521     if((regs[i].wasdirty>>5)&1) printf("ebp ");
10522     if((regs[i].wasdirty>>6)&1) printf("esi ");
10523     if((regs[i].wasdirty>>7)&1) printf("edi ");
10524     #endif
10525     #ifdef __arm__
10526     printf("entry: r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d\n",regs[i].regmap_entry[0],regs[i].regmap_entry[1],regs[i].regmap_entry[2],regs[i].regmap_entry[3],regs[i].regmap_entry[4],regs[i].regmap_entry[5],regs[i].regmap_entry[6],regs[i].regmap_entry[7],regs[i].regmap_entry[8],regs[i].regmap_entry[9],regs[i].regmap_entry[10],regs[i].regmap_entry[12]);
10527     printf("dirty: ");
10528     if(regs[i].wasdirty&1) printf("r0 ");
10529     if((regs[i].wasdirty>>1)&1) printf("r1 ");
10530     if((regs[i].wasdirty>>2)&1) printf("r2 ");
10531     if((regs[i].wasdirty>>3)&1) printf("r3 ");
10532     if((regs[i].wasdirty>>4)&1) printf("r4 ");
10533     if((regs[i].wasdirty>>5)&1) printf("r5 ");
10534     if((regs[i].wasdirty>>6)&1) printf("r6 ");
10535     if((regs[i].wasdirty>>7)&1) printf("r7 ");
10536     if((regs[i].wasdirty>>8)&1) printf("r8 ");
10537     if((regs[i].wasdirty>>9)&1) printf("r9 ");
10538     if((regs[i].wasdirty>>10)&1) printf("r10 ");
10539     if((regs[i].wasdirty>>12)&1) printf("r12 ");
10540     #endif
10541     printf("\n");
10542     disassemble_inst(i);
10543     //printf ("ccadj[%d] = %d\n",i,ccadj[i]);
10544     #if defined(__i386__) || defined(__x86_64__)
10545     printf("eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d dirty: ",regs[i].regmap[0],regs[i].regmap[1],regs[i].regmap[2],regs[i].regmap[3],regs[i].regmap[5],regs[i].regmap[6],regs[i].regmap[7]);
10546     if(regs[i].dirty&1) printf("eax ");
10547     if((regs[i].dirty>>1)&1) printf("ecx ");
10548     if((regs[i].dirty>>2)&1) printf("edx ");
10549     if((regs[i].dirty>>3)&1) printf("ebx ");
10550     if((regs[i].dirty>>5)&1) printf("ebp ");
10551     if((regs[i].dirty>>6)&1) printf("esi ");
10552     if((regs[i].dirty>>7)&1) printf("edi ");
10553     #endif
10554     #ifdef __arm__
10555     printf("r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d dirty: ",regs[i].regmap[0],regs[i].regmap[1],regs[i].regmap[2],regs[i].regmap[3],regs[i].regmap[4],regs[i].regmap[5],regs[i].regmap[6],regs[i].regmap[7],regs[i].regmap[8],regs[i].regmap[9],regs[i].regmap[10],regs[i].regmap[12]);
10556     if(regs[i].dirty&1) printf("r0 ");
10557     if((regs[i].dirty>>1)&1) printf("r1 ");
10558     if((regs[i].dirty>>2)&1) printf("r2 ");
10559     if((regs[i].dirty>>3)&1) printf("r3 ");
10560     if((regs[i].dirty>>4)&1) printf("r4 ");
10561     if((regs[i].dirty>>5)&1) printf("r5 ");
10562     if((regs[i].dirty>>6)&1) printf("r6 ");
10563     if((regs[i].dirty>>7)&1) printf("r7 ");
10564     if((regs[i].dirty>>8)&1) printf("r8 ");
10565     if((regs[i].dirty>>9)&1) printf("r9 ");
10566     if((regs[i].dirty>>10)&1) printf("r10 ");
10567     if((regs[i].dirty>>12)&1) printf("r12 ");
10568     #endif
10569     printf("\n");
10570     if(regs[i].isconst) {
10571       printf("constants: ");
10572       #if defined(__i386__) || defined(__x86_64__)
10573       if(regs[i].isconst&1) printf("eax=%x ",(int)constmap[i][0]);
10574       if((regs[i].isconst>>1)&1) printf("ecx=%x ",(int)constmap[i][1]);
10575       if((regs[i].isconst>>2)&1) printf("edx=%x ",(int)constmap[i][2]);
10576       if((regs[i].isconst>>3)&1) printf("ebx=%x ",(int)constmap[i][3]);
10577       if((regs[i].isconst>>5)&1) printf("ebp=%x ",(int)constmap[i][5]);
10578       if((regs[i].isconst>>6)&1) printf("esi=%x ",(int)constmap[i][6]);
10579       if((regs[i].isconst>>7)&1) printf("edi=%x ",(int)constmap[i][7]);
10580       #endif
10581       #ifdef __arm__
10582       if(regs[i].isconst&1) printf("r0=%x ",(int)constmap[i][0]);
10583       if((regs[i].isconst>>1)&1) printf("r1=%x ",(int)constmap[i][1]);
10584       if((regs[i].isconst>>2)&1) printf("r2=%x ",(int)constmap[i][2]);
10585       if((regs[i].isconst>>3)&1) printf("r3=%x ",(int)constmap[i][3]);
10586       if((regs[i].isconst>>4)&1) printf("r4=%x ",(int)constmap[i][4]);
10587       if((regs[i].isconst>>5)&1) printf("r5=%x ",(int)constmap[i][5]);
10588       if((regs[i].isconst>>6)&1) printf("r6=%x ",(int)constmap[i][6]);
10589       if((regs[i].isconst>>7)&1) printf("r7=%x ",(int)constmap[i][7]);
10590       if((regs[i].isconst>>8)&1) printf("r8=%x ",(int)constmap[i][8]);
10591       if((regs[i].isconst>>9)&1) printf("r9=%x ",(int)constmap[i][9]);
10592       if((regs[i].isconst>>10)&1) printf("r10=%x ",(int)constmap[i][10]);
10593       if((regs[i].isconst>>12)&1) printf("r12=%x ",(int)constmap[i][12]);
10594       #endif
10595       printf("\n");
10596     }
10597 #ifndef FORCE32
10598     printf(" 32:");
10599     for(r=0;r<=CCREG;r++) {
10600       if((regs[i].is32>>r)&1) {
10601         if(r==CCREG) printf(" CC");
10602         else if(r==HIREG) printf(" HI");
10603         else if(r==LOREG) printf(" LO");
10604         else printf(" r%d",r);
10605       }
10606     }
10607     printf("\n");
10608 #endif
10609     /*printf(" p32:");
10610     for(r=0;r<=CCREG;r++) {
10611       if((p32[i]>>r)&1) {
10612         if(r==CCREG) printf(" CC");
10613         else if(r==HIREG) printf(" HI");
10614         else if(r==LOREG) printf(" LO");
10615         else printf(" r%d",r);
10616       }
10617     }
10618     if(p32[i]!=regs[i].is32) printf(" NO MATCH\n");
10619     else printf("\n");*/
10620     if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP) {
10621       #if defined(__i386__) || defined(__x86_64__)
10622       printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d dirty: ",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
10623       if(branch_regs[i].dirty&1) printf("eax ");
10624       if((branch_regs[i].dirty>>1)&1) printf("ecx ");
10625       if((branch_regs[i].dirty>>2)&1) printf("edx ");
10626       if((branch_regs[i].dirty>>3)&1) printf("ebx ");
10627       if((branch_regs[i].dirty>>5)&1) printf("ebp ");
10628       if((branch_regs[i].dirty>>6)&1) printf("esi ");
10629       if((branch_regs[i].dirty>>7)&1) printf("edi ");
10630       #endif
10631       #ifdef __arm__
10632       printf("branch(%d): r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d dirty: ",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[4],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7],branch_regs[i].regmap[8],branch_regs[i].regmap[9],branch_regs[i].regmap[10],branch_regs[i].regmap[12]);
10633       if(branch_regs[i].dirty&1) printf("r0 ");
10634       if((branch_regs[i].dirty>>1)&1) printf("r1 ");
10635       if((branch_regs[i].dirty>>2)&1) printf("r2 ");
10636       if((branch_regs[i].dirty>>3)&1) printf("r3 ");
10637       if((branch_regs[i].dirty>>4)&1) printf("r4 ");
10638       if((branch_regs[i].dirty>>5)&1) printf("r5 ");
10639       if((branch_regs[i].dirty>>6)&1) printf("r6 ");
10640       if((branch_regs[i].dirty>>7)&1) printf("r7 ");
10641       if((branch_regs[i].dirty>>8)&1) printf("r8 ");
10642       if((branch_regs[i].dirty>>9)&1) printf("r9 ");
10643       if((branch_regs[i].dirty>>10)&1) printf("r10 ");
10644       if((branch_regs[i].dirty>>12)&1) printf("r12 ");
10645       #endif
10646 #ifndef FORCE32
10647       printf(" 32:");
10648       for(r=0;r<=CCREG;r++) {
10649         if((branch_regs[i].is32>>r)&1) {
10650           if(r==CCREG) printf(" CC");
10651           else if(r==HIREG) printf(" HI");
10652           else if(r==LOREG) printf(" LO");
10653           else printf(" r%d",r);
10654         }
10655       }
10656       printf("\n");
10657 #endif
10658     }
10659   }
10660
10661   /* Pass 8 - Assembly */
10662   linkcount=0;stubcount=0;
10663   ds=0;is_delayslot=0;
10664   cop1_usable=0;
10665   uint64_t is32_pre=0;
10666   u_int dirty_pre=0;
10667   u_int beginning=(u_int)out;
10668   if((u_int)addr&1) {
10669     ds=1;
10670     pagespan_ds();
10671   }
10672   u_int instr_addr0_override=0;
10673
10674 #ifdef PCSX
10675   if (start == 0x80030000) {
10676     // nasty hack for fastbios thing
10677     instr_addr0_override=(u_int)out;
10678     emit_movimm(start,0);
10679     emit_readword((int)&pcaddr,1);
10680     emit_writeword(0,(int)&pcaddr);
10681     emit_cmp(0,1);
10682     emit_jne((int)new_dyna_leave);
10683   }
10684 #endif
10685   for(i=0;i<slen;i++)
10686   {
10687     //if(ds) printf("ds: ");
10688     if((void*)assem_debug==(void*)printf) disassemble_inst(i);
10689     if(ds) {
10690       ds=0; // Skip delay slot
10691       if(bt[i]) assem_debug("OOPS - branch into delay slot\n");
10692       instr_addr[i]=0;
10693     } else {
10694       #ifndef DESTRUCTIVE_WRITEBACK
10695       if(i<2||(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000))
10696       {
10697         wb_sx(regmap_pre[i],regs[i].regmap_entry,regs[i].wasdirty,is32_pre,regs[i].was32,
10698               unneeded_reg[i],unneeded_reg_upper[i]);
10699         wb_valid(regmap_pre[i],regs[i].regmap_entry,dirty_pre,regs[i].wasdirty,is32_pre,
10700               unneeded_reg[i],unneeded_reg_upper[i]);
10701       }
10702       is32_pre=regs[i].is32;
10703       dirty_pre=regs[i].dirty;
10704       #endif
10705       // write back
10706       if(i<2||(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000))
10707       {
10708         wb_invalidate(regmap_pre[i],regs[i].regmap_entry,regs[i].wasdirty,regs[i].was32,
10709                       unneeded_reg[i],unneeded_reg_upper[i]);
10710         loop_preload(regmap_pre[i],regs[i].regmap_entry);
10711       }
10712       // branch target entry point
10713       instr_addr[i]=(u_int)out;
10714       assem_debug("<->\n");
10715       // load regs
10716       if(regs[i].regmap_entry[HOST_CCREG]==CCREG&&regs[i].regmap[HOST_CCREG]!=CCREG)
10717         wb_register(CCREG,regs[i].regmap_entry,regs[i].wasdirty,regs[i].was32);
10718       load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs1[i],rs2[i]);
10719       address_generation(i,&regs[i],regs[i].regmap_entry);
10720       load_consts(regmap_pre[i],regs[i].regmap,regs[i].was32,i);
10721       if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
10722       {
10723         // Load the delay slot registers if necessary
10724         if(rs1[i+1]!=rs1[i]&&rs1[i+1]!=rs2[i])
10725           load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs1[i+1],rs1[i+1]);
10726         if(rs2[i+1]!=rs1[i+1]&&rs2[i+1]!=rs1[i]&&rs2[i+1]!=rs2[i])
10727           load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs2[i+1],rs2[i+1]);
10728         if(itype[i+1]==STORE||itype[i+1]==STORELR||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a)
10729           load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,INVCP,INVCP);
10730       }
10731       else if(i+1<slen)
10732       {
10733         // Preload registers for following instruction
10734         if(rs1[i+1]!=rs1[i]&&rs1[i+1]!=rs2[i])
10735           if(rs1[i+1]!=rt1[i]&&rs1[i+1]!=rt2[i])
10736             load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs1[i+1],rs1[i+1]);
10737         if(rs2[i+1]!=rs1[i+1]&&rs2[i+1]!=rs1[i]&&rs2[i+1]!=rs2[i])
10738           if(rs2[i+1]!=rt1[i]&&rs2[i+1]!=rt2[i])
10739             load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs2[i+1],rs2[i+1]);
10740       }
10741       // TODO: if(is_ooo(i)) address_generation(i+1);
10742       if(itype[i]==CJUMP||itype[i]==FJUMP)
10743         load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,CCREG,CCREG);
10744       if(itype[i]==STORE||itype[i]==STORELR||(opcode[i]&0x3b)==0x39||(opcode[i]&0x3b)==0x3a)
10745         load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,INVCP,INVCP);
10746       if(bt[i]) cop1_usable=0;
10747       // assemble
10748       switch(itype[i]) {
10749         case ALU:
10750           alu_assemble(i,&regs[i]);break;
10751         case IMM16:
10752           imm16_assemble(i,&regs[i]);break;
10753         case SHIFT:
10754           shift_assemble(i,&regs[i]);break;
10755         case SHIFTIMM:
10756           shiftimm_assemble(i,&regs[i]);break;
10757         case LOAD:
10758           load_assemble(i,&regs[i]);break;
10759         case LOADLR:
10760           loadlr_assemble(i,&regs[i]);break;
10761         case STORE:
10762           store_assemble(i,&regs[i]);break;
10763         case STORELR:
10764           storelr_assemble(i,&regs[i]);break;
10765         case COP0:
10766           cop0_assemble(i,&regs[i]);break;
10767         case COP1:
10768           cop1_assemble(i,&regs[i]);break;
10769         case C1LS:
10770           c1ls_assemble(i,&regs[i]);break;
10771         case COP2:
10772           cop2_assemble(i,&regs[i]);break;
10773         case C2LS:
10774           c2ls_assemble(i,&regs[i]);break;
10775         case C2OP:
10776           c2op_assemble(i,&regs[i]);break;
10777         case FCONV:
10778           fconv_assemble(i,&regs[i]);break;
10779         case FLOAT:
10780           float_assemble(i,&regs[i]);break;
10781         case FCOMP:
10782           fcomp_assemble(i,&regs[i]);break;
10783         case MULTDIV:
10784           multdiv_assemble(i,&regs[i]);break;
10785         case MOV:
10786           mov_assemble(i,&regs[i]);break;
10787         case SYSCALL:
10788           syscall_assemble(i,&regs[i]);break;
10789         case HLECALL:
10790           hlecall_assemble(i,&regs[i]);break;
10791         case INTCALL:
10792           intcall_assemble(i,&regs[i]);break;
10793         case UJUMP:
10794           ujump_assemble(i,&regs[i]);ds=1;break;
10795         case RJUMP:
10796           rjump_assemble(i,&regs[i]);ds=1;break;
10797         case CJUMP:
10798           cjump_assemble(i,&regs[i]);ds=1;break;
10799         case SJUMP:
10800           sjump_assemble(i,&regs[i]);ds=1;break;
10801         case FJUMP:
10802           fjump_assemble(i,&regs[i]);ds=1;break;
10803         case SPAN:
10804           pagespan_assemble(i,&regs[i]);break;
10805       }
10806       if(itype[i]==UJUMP||itype[i]==RJUMP||(source[i]>>16)==0x1000)
10807         literal_pool(1024);
10808       else
10809         literal_pool_jumpover(256);
10810     }
10811   }
10812   //assert(itype[i-2]==UJUMP||itype[i-2]==RJUMP||(source[i-2]>>16)==0x1000);
10813   // If the block did not end with an unconditional branch,
10814   // add a jump to the next instruction.
10815   if(i>1) {
10816     if(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000&&itype[i-1]!=SPAN) {
10817       assert(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP);
10818       assert(i==slen);
10819       if(itype[i-2]!=CJUMP&&itype[i-2]!=SJUMP&&itype[i-2]!=FJUMP) {
10820         store_regs_bt(regs[i-1].regmap,regs[i-1].is32,regs[i-1].dirty,start+i*4);
10821         if(regs[i-1].regmap[HOST_CCREG]!=CCREG)
10822           emit_loadreg(CCREG,HOST_CCREG);
10823         emit_addimm(HOST_CCREG,CLOCK_DIVIDER*(ccadj[i-1]+1),HOST_CCREG);
10824       }
10825       else if(!likely[i-2])
10826       {
10827         store_regs_bt(branch_regs[i-2].regmap,branch_regs[i-2].is32,branch_regs[i-2].dirty,start+i*4);
10828         assert(branch_regs[i-2].regmap[HOST_CCREG]==CCREG);
10829       }
10830       else
10831       {
10832         store_regs_bt(regs[i-2].regmap,regs[i-2].is32,regs[i-2].dirty,start+i*4);
10833         assert(regs[i-2].regmap[HOST_CCREG]==CCREG);
10834       }
10835       add_to_linker((int)out,start+i*4,0);
10836       emit_jmp(0);
10837     }
10838   }
10839   else
10840   {
10841     assert(i>0);
10842     assert(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP);
10843     store_regs_bt(regs[i-1].regmap,regs[i-1].is32,regs[i-1].dirty,start+i*4);
10844     if(regs[i-1].regmap[HOST_CCREG]!=CCREG)
10845       emit_loadreg(CCREG,HOST_CCREG);
10846     emit_addimm(HOST_CCREG,CLOCK_DIVIDER*(ccadj[i-1]+1),HOST_CCREG);
10847     add_to_linker((int)out,start+i*4,0);
10848     emit_jmp(0);
10849   }
10850
10851   // TODO: delay slot stubs?
10852   // Stubs
10853   for(i=0;i<stubcount;i++)
10854   {
10855     switch(stubs[i][0])
10856     {
10857       case LOADB_STUB:
10858       case LOADH_STUB:
10859       case LOADW_STUB:
10860       case LOADD_STUB:
10861       case LOADBU_STUB:
10862       case LOADHU_STUB:
10863         do_readstub(i);break;
10864       case STOREB_STUB:
10865       case STOREH_STUB:
10866       case STOREW_STUB:
10867       case STORED_STUB:
10868         do_writestub(i);break;
10869       case CC_STUB:
10870         do_ccstub(i);break;
10871       case INVCODE_STUB:
10872         do_invstub(i);break;
10873       case FP_STUB:
10874         do_cop1stub(i);break;
10875       case STORELR_STUB:
10876         do_unalignedwritestub(i);break;
10877     }
10878   }
10879
10880   if (instr_addr0_override)
10881     instr_addr[0] = instr_addr0_override;
10882
10883   /* Pass 9 - Linker */
10884   for(i=0;i<linkcount;i++)
10885   {
10886     assem_debug("%8x -> %8x\n",link_addr[i][0],link_addr[i][1]);
10887     literal_pool(64);
10888     if(!link_addr[i][2])
10889     {
10890       void *stub=out;
10891       void *addr=check_addr(link_addr[i][1]);
10892       emit_extjump(link_addr[i][0],link_addr[i][1]);
10893       if(addr) {
10894         set_jump_target(link_addr[i][0],(int)addr);
10895         add_link(link_addr[i][1],stub);
10896       }
10897       else set_jump_target(link_addr[i][0],(int)stub);
10898     }
10899     else
10900     {
10901       // Internal branch
10902       int target=(link_addr[i][1]-start)>>2;
10903       assert(target>=0&&target<slen);
10904       assert(instr_addr[target]);
10905       //#ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
10906       //set_jump_target_fillslot(link_addr[i][0],instr_addr[target],link_addr[i][2]>>1);
10907       //#else
10908       set_jump_target(link_addr[i][0],instr_addr[target]);
10909       //#endif
10910     }
10911   }
10912   // External Branch Targets (jump_in)
10913   if(copy+slen*4>(void *)shadow+sizeof(shadow)) copy=shadow;
10914   for(i=0;i<slen;i++)
10915   {
10916     if(bt[i]||i==0)
10917     {
10918       if(instr_addr[i]) // TODO - delay slots (=null)
10919       {
10920         u_int vaddr=start+i*4;
10921         u_int page=get_page(vaddr);
10922         u_int vpage=get_vpage(vaddr);
10923         literal_pool(256);
10924         //if(!(is32[i]&(~unneeded_reg_upper[i])&~(1LL<<CCREG)))
10925 #ifndef FORCE32
10926         if(!requires_32bit[i])
10927 #else
10928         if(1)
10929 #endif
10930         {
10931           assem_debug("%8x (%d) <- %8x\n",instr_addr[i],i,start+i*4);
10932           assem_debug("jump_in: %x\n",start+i*4);
10933           ll_add(jump_dirty+vpage,vaddr,(void *)out);
10934           int entry_point=do_dirty_stub(i);
10935           ll_add(jump_in+page,vaddr,(void *)entry_point);
10936           // If there was an existing entry in the hash table,
10937           // replace it with the new address.
10938           // Don't add new entries.  We'll insert the
10939           // ones that actually get used in check_addr().
10940           int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
10941           if(ht_bin[0]==vaddr) {
10942             ht_bin[1]=entry_point;
10943           }
10944           if(ht_bin[2]==vaddr) {
10945             ht_bin[3]=entry_point;
10946           }
10947         }
10948         else
10949         {
10950           u_int r=requires_32bit[i]|!!(requires_32bit[i]>>32);
10951           assem_debug("%8x (%d) <- %8x\n",instr_addr[i],i,start+i*4);
10952           assem_debug("jump_in: %x (restricted - %x)\n",start+i*4,r);
10953           //int entry_point=(int)out;
10954           ////assem_debug("entry_point: %x\n",entry_point);
10955           //load_regs_entry(i);
10956           //if(entry_point==(int)out)
10957           //  entry_point=instr_addr[i];
10958           //else
10959           //  emit_jmp(instr_addr[i]);
10960           //ll_add_32(jump_in+page,vaddr,r,(void *)entry_point);
10961           ll_add_32(jump_dirty+vpage,vaddr,r,(void *)out);
10962           int entry_point=do_dirty_stub(i);
10963           ll_add_32(jump_in+page,vaddr,r,(void *)entry_point);
10964         }
10965       }
10966     }
10967   }
10968   // Write out the literal pool if necessary
10969   literal_pool(0);
10970   #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
10971   // Align code
10972   if(((u_int)out)&7) emit_addnop(13);
10973   #endif
10974   assert((u_int)out-beginning<MAX_OUTPUT_BLOCK_SIZE);
10975   //printf("shadow buffer: %x-%x\n",(int)copy,(int)copy+slen*4);
10976   memcpy(copy,source,slen*4);
10977   copy+=slen*4;
10978
10979   #ifdef __arm__
10980   __clear_cache((void *)beginning,out);
10981   #endif
10982
10983   // If we're within 256K of the end of the buffer,
10984   // start over from the beginning. (Is 256K enough?)
10985   if((int)out>BASE_ADDR+(1<<TARGET_SIZE_2)-MAX_OUTPUT_BLOCK_SIZE) out=(u_char *)BASE_ADDR;
10986
10987   // Trap writes to any of the pages we compiled
10988   for(i=start>>12;i<=(start+slen*4)>>12;i++) {
10989     invalid_code[i]=0;
10990 #ifndef DISABLE_TLB
10991     memory_map[i]|=0x40000000;
10992     if((signed int)start>=(signed int)0xC0000000) {
10993       assert(using_tlb);
10994       j=(((u_int)i<<12)+(memory_map[i]<<2)-(u_int)rdram+(u_int)0x80000000)>>12;
10995       invalid_code[j]=0;
10996       memory_map[j]|=0x40000000;
10997       //printf("write protect physical page: %x (virtual %x)\n",j<<12,start);
10998     }
10999 #endif
11000   }
11001
11002   /* Pass 10 - Free memory by expiring oldest blocks */
11003
11004   int end=((((int)out-BASE_ADDR)>>(TARGET_SIZE_2-16))+16384)&65535;
11005   while(expirep!=end)
11006   {
11007     int shift=TARGET_SIZE_2-3; // Divide into 8 blocks
11008     int base=BASE_ADDR+((expirep>>13)<<shift); // Base address of this block
11009     inv_debug("EXP: Phase %d\n",expirep);
11010     switch((expirep>>11)&3)
11011     {
11012       case 0:
11013         // Clear jump_in and jump_dirty
11014         ll_remove_matching_addrs(jump_in+(expirep&2047),base,shift);
11015         ll_remove_matching_addrs(jump_dirty+(expirep&2047),base,shift);
11016         ll_remove_matching_addrs(jump_in+2048+(expirep&2047),base,shift);
11017         ll_remove_matching_addrs(jump_dirty+2048+(expirep&2047),base,shift);
11018         break;
11019       case 1:
11020         // Clear pointers
11021         ll_kill_pointers(jump_out[expirep&2047],base,shift);
11022         ll_kill_pointers(jump_out[(expirep&2047)+2048],base,shift);
11023         break;
11024       case 2:
11025         // Clear hash table
11026         for(i=0;i<32;i++) {
11027           int *ht_bin=hash_table[((expirep&2047)<<5)+i];
11028           if((ht_bin[3]>>shift)==(base>>shift) ||
11029              ((ht_bin[3]-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(base>>shift)) {
11030             inv_debug("EXP: Remove hash %x -> %x\n",ht_bin[2],ht_bin[3]);
11031             ht_bin[2]=ht_bin[3]=-1;
11032           }
11033           if((ht_bin[1]>>shift)==(base>>shift) ||
11034              ((ht_bin[1]-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(base>>shift)) {
11035             inv_debug("EXP: Remove hash %x -> %x\n",ht_bin[0],ht_bin[1]);
11036             ht_bin[0]=ht_bin[2];
11037             ht_bin[1]=ht_bin[3];
11038             ht_bin[2]=ht_bin[3]=-1;
11039           }
11040         }
11041         break;
11042       case 3:
11043         // Clear jump_out
11044         #ifdef __arm__
11045         if((expirep&2047)==0)
11046           do_clear_cache();
11047         #endif
11048         ll_remove_matching_addrs(jump_out+(expirep&2047),base,shift);
11049         ll_remove_matching_addrs(jump_out+2048+(expirep&2047),base,shift);
11050         break;
11051     }
11052     expirep=(expirep+1)&65535;
11053   }
11054   return 0;
11055 }
11056
11057 // vim:shiftwidth=2:expandtab