1 /* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
2 * Mupen64plus - new_dynarec.c *
3 * Copyright (C) 2009-2011 Ari64 *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. *
19 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
22 #include <stdint.h> //include for uint64_t
26 #include "emu_if.h" //emulator interface
29 //#define assem_debug printf
30 //#define inv_debug printf
31 #define assem_debug(...)
32 #define inv_debug(...)
35 #include "assem_x86.h"
38 #include "assem_x64.h"
41 #include "assem_arm.h"
45 #define MAX_OUTPUT_BLOCK_SIZE 262144
46 #define CLOCK_DIVIDER 2
50 signed char regmap_entry[HOST_REGS];
51 signed char regmap[HOST_REGS];
60 uint64_t constmap[HOST_REGS];
68 struct ll_entry *next;
74 char insn[MAXBLOCK][10];
75 u_char itype[MAXBLOCK];
76 u_char opcode[MAXBLOCK];
77 u_char opcode2[MAXBLOCK];
85 u_char dep1[MAXBLOCK];
86 u_char dep2[MAXBLOCK];
88 static uint64_t gte_rs[MAXBLOCK]; // gte: 32 data and 32 ctl regs
89 static uint64_t gte_rt[MAXBLOCK];
90 static uint64_t gte_unneeded[MAXBLOCK];
91 static int gte_reads_flags; // gte flag read encountered
94 char likely[MAXBLOCK];
97 uint64_t unneeded_reg[MAXBLOCK];
98 uint64_t unneeded_reg_upper[MAXBLOCK];
99 uint64_t branch_unneeded_reg[MAXBLOCK];
100 uint64_t branch_unneeded_reg_upper[MAXBLOCK];
101 uint64_t p32[MAXBLOCK];
102 uint64_t pr32[MAXBLOCK];
103 signed char regmap_pre[MAXBLOCK][HOST_REGS];
104 signed char regmap[MAXBLOCK][HOST_REGS];
105 signed char regmap_entry[MAXBLOCK][HOST_REGS];
106 uint64_t constmap[MAXBLOCK][HOST_REGS];
107 struct regstat regs[MAXBLOCK];
108 struct regstat branch_regs[MAXBLOCK];
109 signed char minimum_free_regs[MAXBLOCK];
110 u_int needed_reg[MAXBLOCK];
111 uint64_t requires_32bit[MAXBLOCK];
112 u_int wont_dirty[MAXBLOCK];
113 u_int will_dirty[MAXBLOCK];
116 u_int instr_addr[MAXBLOCK];
117 u_int link_addr[MAXBLOCK][3];
119 u_int stubs[MAXBLOCK*3][8];
121 u_int literals[1024][2];
126 struct ll_entry *jump_in[4096];
127 struct ll_entry *jump_out[4096];
128 struct ll_entry *jump_dirty[4096];
129 u_int hash_table[65536][4] __attribute__((aligned(16)));
130 char shadow[1048576] __attribute__((aligned(16)));
136 static const u_int using_tlb=0;
138 static u_int sp_in_mirror;
139 int new_dynarec_did_compile;
140 u_int stop_after_jal;
141 extern u_char restore_candidate[512];
142 extern int cycle_count;
144 /* registers that may be allocated */
146 #define HIREG 32 // hi
147 #define LOREG 33 // lo
148 #define FSREG 34 // FPU status (FCSR)
149 #define CSREG 35 // Coprocessor status
150 #define CCREG 36 // Cycle count
151 #define INVCP 37 // Pointer to invalid_code
152 #define MMREG 38 // Pointer to memory_map
153 #define ROREG 39 // ram offset (if rdram!=0x80000000)
155 #define FTEMP 40 // FPU temporary register
156 #define PTEMP 41 // Prefetch temporary register
157 #define TLREG 42 // TLB mapping offset
158 #define RHASH 43 // Return address hash
159 #define RHTBL 44 // Return address hash table address
160 #define RTEMP 45 // JR/JALR address register
162 #define AGEN1 46 // Address generation temporary register
163 #define AGEN2 47 // Address generation temporary register
164 #define MGEN1 48 // Maptable address generation temporary register
165 #define MGEN2 49 // Maptable address generation temporary register
166 #define BTREG 50 // Branch target temporary register
168 /* instruction types */
169 #define NOP 0 // No operation
170 #define LOAD 1 // Load
171 #define STORE 2 // Store
172 #define LOADLR 3 // Unaligned load
173 #define STORELR 4 // Unaligned store
174 #define MOV 5 // Move
175 #define ALU 6 // Arithmetic/logic
176 #define MULTDIV 7 // Multiply/divide
177 #define SHIFT 8 // Shift by register
178 #define SHIFTIMM 9// Shift by immediate
179 #define IMM16 10 // 16-bit immediate
180 #define RJUMP 11 // Unconditional jump to register
181 #define UJUMP 12 // Unconditional jump
182 #define CJUMP 13 // Conditional branch (BEQ/BNE/BGTZ/BLEZ)
183 #define SJUMP 14 // Conditional branch (regimm format)
184 #define COP0 15 // Coprocessor 0
185 #define COP1 16 // Coprocessor 1
186 #define C1LS 17 // Coprocessor 1 load/store
187 #define FJUMP 18 // Conditional branch (floating point)
188 #define FLOAT 19 // Floating point unit
189 #define FCONV 20 // Convert integer to float
190 #define FCOMP 21 // Floating point compare (sets FSREG)
191 #define SYSCALL 22// SYSCALL
192 #define OTHER 23 // Other
193 #define SPAN 24 // Branch/delay slot spans 2 pages
194 #define NI 25 // Not implemented
195 #define HLECALL 26// PCSX fake opcodes for HLE
196 #define COP2 27 // Coprocessor 2 move
197 #define C2LS 28 // Coprocessor 2 load/store
198 #define C2OP 29 // Coprocessor 2 operation
199 #define INTCALL 30// Call interpreter to handle rare corner cases
208 #define LOADBU_STUB 7
209 #define LOADHU_STUB 8
210 #define STOREB_STUB 9
211 #define STOREH_STUB 10
212 #define STOREW_STUB 11
213 #define STORED_STUB 12
214 #define STORELR_STUB 13
215 #define INVCODE_STUB 14
223 int new_recompile_block(int addr);
224 void *get_addr_ht(u_int vaddr);
225 void invalidate_block(u_int block);
226 void invalidate_addr(u_int addr);
227 void remove_hash(int vaddr);
230 void dyna_linker_ds();
232 void verify_code_vm();
233 void verify_code_ds();
236 void fp_exception_ds();
238 void jump_syscall_hle();
242 void new_dyna_leave();
247 void read_nomem_new();
248 void read_nomemb_new();
249 void read_nomemh_new();
250 void read_nomemd_new();
251 void write_nomem_new();
252 void write_nomemb_new();
253 void write_nomemh_new();
254 void write_nomemd_new();
255 void write_rdram_new();
256 void write_rdramb_new();
257 void write_rdramh_new();
258 void write_rdramd_new();
259 extern u_int memory_map[1048576];
261 // Needed by assembler
262 void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32);
263 void wb_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty);
264 void wb_needed_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr);
265 void load_all_regs(signed char i_regmap[]);
266 void load_needed_regs(signed char i_regmap[],signed char next_regmap[]);
267 void load_regs_entry(int t);
268 void load_all_consts(signed char regmap[],int is32,u_int dirty,int i);
272 //#define DEBUG_CYCLE_COUNT 1
274 static void tlb_hacks()
278 if (strncmp((char *) ROM_HEADER->nom, "GOLDENEYE",9) == 0)
282 switch (ROM_HEADER->Country_code&0xFF)
294 // Unknown country code
298 u_int rom_addr=(u_int)rom;
300 // Since memory_map is 32-bit, on 64-bit systems the rom needs to be
301 // in the lower 4G of memory to use this hack. Copy it if necessary.
302 if((void *)rom>(void *)0xffffffff) {
303 munmap(ROM_COPY, 67108864);
304 if(mmap(ROM_COPY, 12582912,
305 PROT_READ | PROT_WRITE,
306 MAP_FIXED | MAP_PRIVATE | MAP_ANONYMOUS,
307 -1, 0) <= 0) {printf("mmap() failed\n");}
308 memcpy(ROM_COPY,rom,12582912);
309 rom_addr=(u_int)ROM_COPY;
313 for(n=0x7F000;n<0x80000;n++) {
314 memory_map[n]=(((u_int)(rom_addr+addr-0x7F000000))>>2)|0x40000000;
321 static u_int get_page(u_int vaddr)
324 u_int page=(vaddr^0x80000000)>>12;
326 u_int page=vaddr&~0xe0000000;
327 if (page < 0x1000000)
328 page &= ~0x0e00000; // RAM mirrors
332 if(page>262143&&tlb_LUT_r[vaddr>>12]) page=(tlb_LUT_r[vaddr>>12]^0x80000000)>>12;
334 if(page>2048) page=2048+(page&2047);
338 static u_int get_vpage(u_int vaddr)
340 u_int vpage=(vaddr^0x80000000)>>12;
342 if(vpage>262143&&tlb_LUT_r[vaddr>>12]) vpage&=2047; // jump_dirty uses a hash of the virtual address instead
344 if(vpage>2048) vpage=2048+(vpage&2047);
348 // Get address from virtual address
349 // This is called from the recompiled JR/JALR instructions
350 void *get_addr(u_int vaddr)
352 u_int page=get_page(vaddr);
353 u_int vpage=get_vpage(vaddr);
354 struct ll_entry *head;
355 //printf("TRACE: count=%d next=%d (get_addr %x,page %d)\n",Count,next_interupt,vaddr,page);
358 if(head->vaddr==vaddr&&head->reg32==0) {
359 //printf("TRACE: count=%d next=%d (get_addr match %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
360 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
363 ht_bin[1]=(int)head->addr;
369 head=jump_dirty[vpage];
371 if(head->vaddr==vaddr&&head->reg32==0) {
372 //printf("TRACE: count=%d next=%d (get_addr match dirty %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
373 // Don't restore blocks which are about to expire from the cache
374 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
375 if(verify_dirty(head->addr)) {
376 //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]);
377 invalid_code[vaddr>>12]=0;
378 inv_code_start=inv_code_end=~0;
379 memory_map[vaddr>>12]|=0x40000000;
382 if(tlb_LUT_r[vaddr>>12]) {
383 invalid_code[tlb_LUT_r[vaddr>>12]>>12]=0;
384 memory_map[tlb_LUT_r[vaddr>>12]>>12]|=0x40000000;
387 restore_candidate[vpage>>3]|=1<<(vpage&7);
389 else restore_candidate[page>>3]|=1<<(page&7);
390 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
391 if(ht_bin[0]==vaddr) {
392 ht_bin[1]=(int)head->addr; // Replace existing entry
398 ht_bin[1]=(int)head->addr;
406 //printf("TRACE: count=%d next=%d (get_addr no-match %x)\n",Count,next_interupt,vaddr);
407 int r=new_recompile_block(vaddr);
408 if(r==0) return get_addr(vaddr);
409 // Execute in unmapped page, generate pagefault execption
411 Cause=(vaddr<<31)|0x8;
412 EPC=(vaddr&1)?vaddr-5:vaddr;
414 Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0);
415 EntryHi=BadVAddr&0xFFFFE000;
416 return get_addr_ht(0x80000000);
418 // Look up address in hash table first
419 void *get_addr_ht(u_int vaddr)
421 //printf("TRACE: count=%d next=%d (get_addr_ht %x)\n",Count,next_interupt,vaddr);
422 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
423 if(ht_bin[0]==vaddr) return (void *)ht_bin[1];
424 if(ht_bin[2]==vaddr) return (void *)ht_bin[3];
425 return get_addr(vaddr);
428 void *get_addr_32(u_int vaddr,u_int flags)
431 return get_addr(vaddr);
433 //printf("TRACE: count=%d next=%d (get_addr_32 %x,flags %x)\n",Count,next_interupt,vaddr,flags);
434 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
435 if(ht_bin[0]==vaddr) return (void *)ht_bin[1];
436 if(ht_bin[2]==vaddr) return (void *)ht_bin[3];
437 u_int page=get_page(vaddr);
438 u_int vpage=get_vpage(vaddr);
439 struct ll_entry *head;
442 if(head->vaddr==vaddr&&(head->reg32&flags)==0) {
443 //printf("TRACE: count=%d next=%d (get_addr_32 match %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
445 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
447 ht_bin[1]=(int)head->addr;
449 }else if(ht_bin[2]==-1) {
450 ht_bin[3]=(int)head->addr;
453 //ht_bin[3]=ht_bin[1];
454 //ht_bin[2]=ht_bin[0];
455 //ht_bin[1]=(int)head->addr;
462 head=jump_dirty[vpage];
464 if(head->vaddr==vaddr&&(head->reg32&flags)==0) {
465 //printf("TRACE: count=%d next=%d (get_addr_32 match dirty %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
466 // Don't restore blocks which are about to expire from the cache
467 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
468 if(verify_dirty(head->addr)) {
469 //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]);
470 invalid_code[vaddr>>12]=0;
471 inv_code_start=inv_code_end=~0;
472 memory_map[vaddr>>12]|=0x40000000;
475 if(tlb_LUT_r[vaddr>>12]) {
476 invalid_code[tlb_LUT_r[vaddr>>12]>>12]=0;
477 memory_map[tlb_LUT_r[vaddr>>12]>>12]|=0x40000000;
480 restore_candidate[vpage>>3]|=1<<(vpage&7);
482 else restore_candidate[page>>3]|=1<<(page&7);
484 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
486 ht_bin[1]=(int)head->addr;
488 }else if(ht_bin[2]==-1) {
489 ht_bin[3]=(int)head->addr;
492 //ht_bin[3]=ht_bin[1];
493 //ht_bin[2]=ht_bin[0];
494 //ht_bin[1]=(int)head->addr;
502 //printf("TRACE: count=%d next=%d (get_addr_32 no-match %x,flags %x)\n",Count,next_interupt,vaddr,flags);
503 int r=new_recompile_block(vaddr);
504 if(r==0) return get_addr(vaddr);
505 // Execute in unmapped page, generate pagefault execption
507 Cause=(vaddr<<31)|0x8;
508 EPC=(vaddr&1)?vaddr-5:vaddr;
510 Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0);
511 EntryHi=BadVAddr&0xFFFFE000;
512 return get_addr_ht(0x80000000);
516 void clear_all_regs(signed char regmap[])
519 for (hr=0;hr<HOST_REGS;hr++) regmap[hr]=-1;
522 signed char get_reg(signed char regmap[],int r)
525 for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&®map[hr]==r) return hr;
529 // Find a register that is available for two consecutive cycles
530 signed char get_reg2(signed char regmap1[],signed char regmap2[],int r)
533 for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&®map1[hr]==r&®map2[hr]==r) return hr;
537 int count_free_regs(signed char regmap[])
541 for(hr=0;hr<HOST_REGS;hr++)
543 if(hr!=EXCLUDE_REG) {
544 if(regmap[hr]<0) count++;
550 void dirty_reg(struct regstat *cur,signed char reg)
554 for (hr=0;hr<HOST_REGS;hr++) {
555 if((cur->regmap[hr]&63)==reg) {
561 // If we dirty the lower half of a 64 bit register which is now being
562 // sign-extended, we need to dump the upper half.
563 // Note: Do this only after completion of the instruction, because
564 // some instructions may need to read the full 64-bit value even if
565 // overwriting it (eg SLTI, DSRA32).
566 static void flush_dirty_uppers(struct regstat *cur)
569 for (hr=0;hr<HOST_REGS;hr++) {
570 if((cur->dirty>>hr)&1) {
573 if((cur->is32>>(reg&63))&1) cur->regmap[hr]=-1;
578 void set_const(struct regstat *cur,signed char reg,uint64_t value)
582 for (hr=0;hr<HOST_REGS;hr++) {
583 if(cur->regmap[hr]==reg) {
585 cur->constmap[hr]=value;
587 else if((cur->regmap[hr]^64)==reg) {
589 cur->constmap[hr]=value>>32;
594 void clear_const(struct regstat *cur,signed char reg)
598 for (hr=0;hr<HOST_REGS;hr++) {
599 if((cur->regmap[hr]&63)==reg) {
600 cur->isconst&=~(1<<hr);
605 int is_const(struct regstat *cur,signed char reg)
610 for (hr=0;hr<HOST_REGS;hr++) {
611 if((cur->regmap[hr]&63)==reg) {
612 return (cur->isconst>>hr)&1;
617 uint64_t get_const(struct regstat *cur,signed char reg)
621 for (hr=0;hr<HOST_REGS;hr++) {
622 if(cur->regmap[hr]==reg) {
623 return cur->constmap[hr];
626 printf("Unknown constant in r%d\n",reg);
630 // Least soon needed registers
631 // Look at the next ten instructions and see which registers
632 // will be used. Try not to reallocate these.
633 void lsn(u_char hsn[], int i, int *preferred_reg)
643 if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
645 // Don't go past an unconditonal jump
652 if(rs1[i+j]) hsn[rs1[i+j]]=j;
653 if(rs2[i+j]) hsn[rs2[i+j]]=j;
654 if(rt1[i+j]) hsn[rt1[i+j]]=j;
655 if(rt2[i+j]) hsn[rt2[i+j]]=j;
656 if(itype[i+j]==STORE || itype[i+j]==STORELR) {
657 // Stores can allocate zero
661 // On some architectures stores need invc_ptr
662 #if defined(HOST_IMM8)
663 if(itype[i+j]==STORE || itype[i+j]==STORELR || (opcode[i+j]&0x3b)==0x39 || (opcode[i+j]&0x3b)==0x3a) {
667 if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP))
675 if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
677 // Follow first branch
678 int t=(ba[i+b]-start)>>2;
679 j=7-b;if(t+j>=slen) j=slen-t-1;
682 if(rs1[t+j]) if(hsn[rs1[t+j]]>j+b+2) hsn[rs1[t+j]]=j+b+2;
683 if(rs2[t+j]) if(hsn[rs2[t+j]]>j+b+2) hsn[rs2[t+j]]=j+b+2;
684 //if(rt1[t+j]) if(hsn[rt1[t+j]]>j+b+2) hsn[rt1[t+j]]=j+b+2;
685 //if(rt2[t+j]) if(hsn[rt2[t+j]]>j+b+2) hsn[rt2[t+j]]=j+b+2;
688 // TODO: preferred register based on backward branch
690 // Delay slot should preferably not overwrite branch conditions or cycle count
691 if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)) {
692 if(rs1[i-1]) if(hsn[rs1[i-1]]>1) hsn[rs1[i-1]]=1;
693 if(rs2[i-1]) if(hsn[rs2[i-1]]>1) hsn[rs2[i-1]]=1;
699 // Coprocessor load/store needs FTEMP, even if not declared
700 if(itype[i]==C1LS||itype[i]==C2LS) {
703 // Load L/R also uses FTEMP as a temporary register
704 if(itype[i]==LOADLR) {
707 // Also SWL/SWR/SDL/SDR
708 if(opcode[i]==0x2a||opcode[i]==0x2e||opcode[i]==0x2c||opcode[i]==0x2d) {
711 // Don't remove the TLB registers either
712 if(itype[i]==LOAD || itype[i]==LOADLR || itype[i]==STORE || itype[i]==STORELR || itype[i]==C1LS || itype[i]==C2LS) {
715 // Don't remove the miniht registers
716 if(itype[i]==UJUMP||itype[i]==RJUMP)
723 // We only want to allocate registers if we're going to use them again soon
724 int needed_again(int r, int i)
730 if(i>0&&(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000))
732 if(ba[i-1]<start || ba[i-1]>start+slen*4-4)
733 return 0; // Don't need any registers if exiting the block
741 if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
743 // Don't go past an unconditonal jump
747 if(itype[i+j]==SYSCALL||itype[i+j]==HLECALL||itype[i+j]==INTCALL||((source[i+j]&0xfc00003f)==0x0d))
754 if(rs1[i+j]==r) rn=j;
755 if(rs2[i+j]==r) rn=j;
756 if((unneeded_reg[i+j]>>r)&1) rn=10;
757 if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP))
765 if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
767 // Follow first branch
769 int t=(ba[i+b]-start)>>2;
770 j=7-b;if(t+j>=slen) j=slen-t-1;
773 if(!((unneeded_reg[t+j]>>r)&1)) {
774 if(rs1[t+j]==r) if(rn>j+b+2) rn=j+b+2;
775 if(rs2[t+j]==r) if(rn>j+b+2) rn=j+b+2;
785 // Try to match register allocations at the end of a loop with those
787 int loop_reg(int i, int r, int hr)
796 if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
798 // Don't go past an unconditonal jump
805 if(itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)
810 if(r<64&&((unneeded_reg[i+k]>>r)&1)) return hr;
811 if(r>64&&((unneeded_reg_upper[i+k]>>r)&1)) return hr;
812 if(i+k>=0&&(itype[i+k]==UJUMP||itype[i+k]==CJUMP||itype[i+k]==SJUMP||itype[i+k]==FJUMP))
814 if(ba[i+k]>=start && ba[i+k]<(start+i*4))
816 int t=(ba[i+k]-start)>>2;
817 int reg=get_reg(regs[t].regmap_entry,r);
818 if(reg>=0) return reg;
819 //reg=get_reg(regs[t+1].regmap_entry,r);
820 //if(reg>=0) return reg;
828 // Allocate every register, preserving source/target regs
829 void alloc_all(struct regstat *cur,int i)
833 for(hr=0;hr<HOST_REGS;hr++) {
834 if(hr!=EXCLUDE_REG) {
835 if(((cur->regmap[hr]&63)!=rs1[i])&&((cur->regmap[hr]&63)!=rs2[i])&&
836 ((cur->regmap[hr]&63)!=rt1[i])&&((cur->regmap[hr]&63)!=rt2[i]))
839 cur->dirty&=~(1<<hr);
842 if((cur->regmap[hr]&63)==0)
845 cur->dirty&=~(1<<hr);
852 void div64(int64_t dividend,int64_t divisor)
856 //printf("TRACE: ddiv %8x%8x %8x%8x\n" ,(int)reg[HIREG],(int)(reg[HIREG]>>32)
857 // ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
859 void divu64(uint64_t dividend,uint64_t divisor)
863 //printf("TRACE: ddivu %8x%8x %8x%8x\n",(int)reg[HIREG],(int)(reg[HIREG]>>32)
864 // ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
867 void mult64(uint64_t m1,uint64_t m2)
869 unsigned long long int op1, op2, op3, op4;
870 unsigned long long int result1, result2, result3, result4;
871 unsigned long long int temp1, temp2, temp3, temp4;
887 op1 = op2 & 0xFFFFFFFF;
888 op2 = (op2 >> 32) & 0xFFFFFFFF;
889 op3 = op4 & 0xFFFFFFFF;
890 op4 = (op4 >> 32) & 0xFFFFFFFF;
893 temp2 = (temp1 >> 32) + op1 * op4;
895 temp4 = (temp3 >> 32) + op2 * op4;
897 result1 = temp1 & 0xFFFFFFFF;
898 result2 = temp2 + (temp3 & 0xFFFFFFFF);
899 result3 = (result2 >> 32) + temp4;
900 result4 = (result3 >> 32);
902 lo = result1 | (result2 << 32);
903 hi = (result3 & 0xFFFFFFFF) | (result4 << 32);
912 void multu64(uint64_t m1,uint64_t m2)
914 unsigned long long int op1, op2, op3, op4;
915 unsigned long long int result1, result2, result3, result4;
916 unsigned long long int temp1, temp2, temp3, temp4;
918 op1 = m1 & 0xFFFFFFFF;
919 op2 = (m1 >> 32) & 0xFFFFFFFF;
920 op3 = m2 & 0xFFFFFFFF;
921 op4 = (m2 >> 32) & 0xFFFFFFFF;
924 temp2 = (temp1 >> 32) + op1 * op4;
926 temp4 = (temp3 >> 32) + op2 * op4;
928 result1 = temp1 & 0xFFFFFFFF;
929 result2 = temp2 + (temp3 & 0xFFFFFFFF);
930 result3 = (result2 >> 32) + temp4;
931 result4 = (result3 >> 32);
933 lo = result1 | (result2 << 32);
934 hi = (result3 & 0xFFFFFFFF) | (result4 << 32);
936 //printf("TRACE: dmultu %8x%8x %8x%8x\n",(int)reg[HIREG],(int)(reg[HIREG]>>32)
937 // ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
940 uint64_t ldl_merge(uint64_t original,uint64_t loaded,u_int bits)
948 else original=loaded;
951 uint64_t ldr_merge(uint64_t original,uint64_t loaded,u_int bits)
954 original>>=64-(bits^56);
955 original<<=64-(bits^56);
959 else original=loaded;
965 #include "assem_x86.c"
968 #include "assem_x64.c"
971 #include "assem_arm.c"
974 // Add virtual address mapping to linked list
975 void ll_add(struct ll_entry **head,int vaddr,void *addr)
977 struct ll_entry *new_entry;
978 new_entry=malloc(sizeof(struct ll_entry));
979 assert(new_entry!=NULL);
980 new_entry->vaddr=vaddr;
982 new_entry->addr=addr;
983 new_entry->next=*head;
987 // Add virtual address mapping for 32-bit compiled block
988 void ll_add_32(struct ll_entry **head,int vaddr,u_int reg32,void *addr)
990 ll_add(head,vaddr,addr);
992 (*head)->reg32=reg32;
996 // Check if an address is already compiled
997 // but don't return addresses which are about to expire from the cache
998 void *check_addr(u_int vaddr)
1000 u_int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
1001 if(ht_bin[0]==vaddr) {
1002 if(((ht_bin[1]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
1003 if(isclean(ht_bin[1])) return (void *)ht_bin[1];
1005 if(ht_bin[2]==vaddr) {
1006 if(((ht_bin[3]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
1007 if(isclean(ht_bin[3])) return (void *)ht_bin[3];
1009 u_int page=get_page(vaddr);
1010 struct ll_entry *head;
1013 if(head->vaddr==vaddr&&head->reg32==0) {
1014 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1015 // Update existing entry with current address
1016 if(ht_bin[0]==vaddr) {
1017 ht_bin[1]=(int)head->addr;
1020 if(ht_bin[2]==vaddr) {
1021 ht_bin[3]=(int)head->addr;
1024 // Insert into hash table with low priority.
1025 // Don't evict existing entries, as they are probably
1026 // addresses that are being accessed frequently.
1028 ht_bin[1]=(int)head->addr;
1030 }else if(ht_bin[2]==-1) {
1031 ht_bin[3]=(int)head->addr;
1042 void remove_hash(int vaddr)
1044 //printf("remove hash: %x\n",vaddr);
1045 int *ht_bin=hash_table[(((vaddr)>>16)^vaddr)&0xFFFF];
1046 if(ht_bin[2]==vaddr) {
1047 ht_bin[2]=ht_bin[3]=-1;
1049 if(ht_bin[0]==vaddr) {
1050 ht_bin[0]=ht_bin[2];
1051 ht_bin[1]=ht_bin[3];
1052 ht_bin[2]=ht_bin[3]=-1;
1056 void ll_remove_matching_addrs(struct ll_entry **head,int addr,int shift)
1058 struct ll_entry *next;
1060 if(((u_int)((*head)->addr)>>shift)==(addr>>shift) ||
1061 ((u_int)((*head)->addr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift))
1063 inv_debug("EXP: Remove pointer to %x (%x)\n",(int)(*head)->addr,(*head)->vaddr);
1064 remove_hash((*head)->vaddr);
1071 head=&((*head)->next);
1076 // Remove all entries from linked list
1077 void ll_clear(struct ll_entry **head)
1079 struct ll_entry *cur;
1080 struct ll_entry *next;
1091 // Dereference the pointers and remove if it matches
1092 void ll_kill_pointers(struct ll_entry *head,int addr,int shift)
1095 int ptr=get_pointer(head->addr);
1096 inv_debug("EXP: Lookup pointer to %x at %x (%x)\n",(int)ptr,(int)head->addr,head->vaddr);
1097 if(((ptr>>shift)==(addr>>shift)) ||
1098 (((ptr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift)))
1100 inv_debug("EXP: Kill pointer at %x (%x)\n",(int)head->addr,head->vaddr);
1101 u_int host_addr=(u_int)kill_pointer(head->addr);
1103 needs_clear_cache[(host_addr-(u_int)BASE_ADDR)>>17]|=1<<(((host_addr-(u_int)BASE_ADDR)>>12)&31);
1110 // This is called when we write to a compiled block (see do_invstub)
1111 void invalidate_page(u_int page)
1113 struct ll_entry *head;
1114 struct ll_entry *next;
1118 inv_debug("INVALIDATE: %x\n",head->vaddr);
1119 remove_hash(head->vaddr);
1124 head=jump_out[page];
1127 inv_debug("INVALIDATE: kill pointer to %x (%x)\n",head->vaddr,(int)head->addr);
1128 u_int host_addr=(u_int)kill_pointer(head->addr);
1130 needs_clear_cache[(host_addr-(u_int)BASE_ADDR)>>17]|=1<<(((host_addr-(u_int)BASE_ADDR)>>12)&31);
1138 static void invalidate_block_range(u_int block, u_int first, u_int last)
1140 u_int page=get_page(block<<12);
1141 //printf("first=%d last=%d\n",first,last);
1142 invalidate_page(page);
1143 assert(first+5>page); // NB: this assumes MAXBLOCK<=4096 (4 pages)
1144 assert(last<page+5);
1145 // Invalidate the adjacent pages if a block crosses a 4K boundary
1147 invalidate_page(first);
1150 for(first=page+1;first<last;first++) {
1151 invalidate_page(first);
1157 // Don't trap writes
1158 invalid_code[block]=1;
1160 // If there is a valid TLB entry for this page, remove write protect
1161 if(tlb_LUT_w[block]) {
1162 assert(tlb_LUT_r[block]==tlb_LUT_w[block]);
1163 // CHECK: Is this right?
1164 memory_map[block]=((tlb_LUT_w[block]&0xFFFFF000)-(block<<12)+(unsigned int)rdram-0x80000000)>>2;
1165 u_int real_block=tlb_LUT_w[block]>>12;
1166 invalid_code[real_block]=1;
1167 if(real_block>=0x80000&&real_block<0x80800) memory_map[real_block]=((u_int)rdram-0x80000000)>>2;
1169 else if(block>=0x80000&&block<0x80800) memory_map[block]=((u_int)rdram-0x80000000)>>2;
1173 memset(mini_ht,-1,sizeof(mini_ht));
1177 void invalidate_block(u_int block)
1179 u_int page=get_page(block<<12);
1180 u_int vpage=get_vpage(block<<12);
1181 inv_debug("INVALIDATE: %x (%d)\n",block<<12,page);
1182 //inv_debug("invalid_code[block]=%d\n",invalid_code[block]);
1185 struct ll_entry *head;
1186 head=jump_dirty[vpage];
1187 //printf("page=%d vpage=%d\n",page,vpage);
1190 if(vpage>2047||(head->vaddr>>12)==block) { // Ignore vaddr hash collision
1191 get_bounds((int)head->addr,&start,&end);
1192 //printf("start: %x end: %x\n",start,end);
1193 if(page<2048&&start>=0x80000000&&end<0x80000000+RAM_SIZE) {
1194 if(((start-(u_int)rdram)>>12)<=page&&((end-1-(u_int)rdram)>>12)>=page) {
1195 if((((start-(u_int)rdram)>>12)&2047)<first) first=((start-(u_int)rdram)>>12)&2047;
1196 if((((end-1-(u_int)rdram)>>12)&2047)>last) last=((end-1-(u_int)rdram)>>12)&2047;
1200 if(page<2048&&(signed int)start>=(signed int)0xC0000000&&(signed int)end>=(signed int)0xC0000000) {
1201 if(((start+memory_map[start>>12]-(u_int)rdram)>>12)<=page&&((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)>=page) {
1202 if((((start+memory_map[start>>12]-(u_int)rdram)>>12)&2047)<first) first=((start+memory_map[start>>12]-(u_int)rdram)>>12)&2047;
1203 if((((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)&2047)>last) last=((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)&2047;
1210 invalidate_block_range(block,first,last);
1213 void invalidate_addr(u_int addr)
1217 // this check is done by the caller
1218 //if (inv_code_start<=addr&&addr<=inv_code_end) { rhits++; return; }
1219 u_int page=get_page(addr);
1220 if(page<2048) { // RAM
1221 struct ll_entry *head;
1222 u_int addr_min=~0, addr_max=0;
1223 int mask=RAM_SIZE-1;
1225 inv_code_start=addr&~0xfff;
1226 inv_code_end=addr|0xfff;
1229 // must check previous page too because of spans..
1231 inv_code_start-=0x1000;
1233 for(;pg1<=page;pg1++) {
1234 for(head=jump_dirty[pg1];head!=NULL;head=head->next) {
1236 get_bounds((int)head->addr,&start,&end);
1237 if((start&mask)<=(addr&mask)&&(addr&mask)<(end&mask)) {
1238 if(start<addr_min) addr_min=start;
1239 if(end>addr_max) addr_max=end;
1241 else if(addr<start) {
1242 if(start<inv_code_end)
1243 inv_code_end=start-1;
1246 if(end>inv_code_start)
1252 inv_debug("INV ADDR: %08x hit %08x-%08x\n", addr, addr_min, addr_max);
1253 inv_code_start=inv_code_end=~0;
1254 invalidate_block_range(addr>>12,(addr_min&mask)>>12,(addr_max&mask)>>12);
1258 inv_debug("INV ADDR: %08x miss, inv %08x-%08x, sk %d\n", addr, inv_code_start, inv_code_end, 0);//rhits);
1261 if(page!=0) // FIXME: don't know what's up with page 0 (Klonoa)
1265 invalidate_block(addr>>12);
1268 // This is called when loading a save state.
1269 // Anything could have changed, so invalidate everything.
1270 void invalidate_all_pages()
1273 for(page=0;page<4096;page++)
1274 invalidate_page(page);
1275 for(page=0;page<1048576;page++)
1276 if(!invalid_code[page]) {
1277 restore_candidate[(page&2047)>>3]|=1<<(page&7);
1278 restore_candidate[((page&2047)>>3)+256]|=1<<(page&7);
1281 __clear_cache((void *)BASE_ADDR,(void *)BASE_ADDR+(1<<TARGET_SIZE_2));
1284 memset(mini_ht,-1,sizeof(mini_ht));
1288 for(page=0;page<0x100000;page++) {
1289 if(tlb_LUT_r[page]) {
1290 memory_map[page]=((tlb_LUT_r[page]&0xFFFFF000)-(page<<12)+(unsigned int)rdram-0x80000000)>>2;
1291 if(!tlb_LUT_w[page]||!invalid_code[page])
1292 memory_map[page]|=0x40000000; // Write protect
1294 else memory_map[page]=-1;
1295 if(page==0x80000) page=0xC0000;
1301 // Add an entry to jump_out after making a link
1302 void add_link(u_int vaddr,void *src)
1304 u_int page=get_page(vaddr);
1305 inv_debug("add_link: %x -> %x (%d)\n",(int)src,vaddr,page);
1306 int *ptr=(int *)(src+4);
1307 assert((*ptr&0x0fff0000)==0x059f0000);
1308 ll_add(jump_out+page,vaddr,src);
1309 //int ptr=get_pointer(src);
1310 //inv_debug("add_link: Pointer is to %x\n",(int)ptr);
1313 // If a code block was found to be unmodified (bit was set in
1314 // restore_candidate) and it remains unmodified (bit is clear
1315 // in invalid_code) then move the entries for that 4K page from
1316 // the dirty list to the clean list.
1317 void clean_blocks(u_int page)
1319 struct ll_entry *head;
1320 inv_debug("INV: clean_blocks page=%d\n",page);
1321 head=jump_dirty[page];
1323 if(!invalid_code[head->vaddr>>12]) {
1324 // Don't restore blocks which are about to expire from the cache
1325 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1327 if(verify_dirty((int)head->addr)) {
1328 //printf("Possibly Restore %x (%x)\n",head->vaddr, (int)head->addr);
1331 get_bounds((int)head->addr,&start,&end);
1332 if(start-(u_int)rdram<RAM_SIZE) {
1333 for(i=(start-(u_int)rdram+0x80000000)>>12;i<=(end-1-(u_int)rdram+0x80000000)>>12;i++) {
1334 inv|=invalid_code[i];
1337 if((signed int)head->vaddr>=(signed int)0xC0000000) {
1338 u_int addr = (head->vaddr+(memory_map[head->vaddr>>12]<<2));
1339 //printf("addr=%x start=%x end=%x\n",addr,start,end);
1340 if(addr<start||addr>=end) inv=1;
1342 else if((signed int)head->vaddr>=(signed int)0x80000000+RAM_SIZE) {
1346 void * clean_addr=(void *)get_clean_addr((int)head->addr);
1347 if((((u_int)clean_addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1350 if(page<2048&&tlb_LUT_r[head->vaddr>>12]) ppage=(tlb_LUT_r[head->vaddr>>12]^0x80000000)>>12;
1352 inv_debug("INV: Restored %x (%x/%x)\n",head->vaddr, (int)head->addr, (int)clean_addr);
1353 //printf("page=%x, addr=%x\n",page,head->vaddr);
1354 //assert(head->vaddr>>12==(page|0x80000));
1355 ll_add_32(jump_in+ppage,head->vaddr,head->reg32,clean_addr);
1356 int *ht_bin=hash_table[((head->vaddr>>16)^head->vaddr)&0xFFFF];
1358 if(ht_bin[0]==head->vaddr) {
1359 ht_bin[1]=(int)clean_addr; // Replace existing entry
1361 if(ht_bin[2]==head->vaddr) {
1362 ht_bin[3]=(int)clean_addr; // Replace existing entry
1375 void mov_alloc(struct regstat *current,int i)
1377 // Note: Don't need to actually alloc the source registers
1378 if((~current->is32>>rs1[i])&1) {
1379 //alloc_reg64(current,i,rs1[i]);
1380 alloc_reg64(current,i,rt1[i]);
1381 current->is32&=~(1LL<<rt1[i]);
1383 //alloc_reg(current,i,rs1[i]);
1384 alloc_reg(current,i,rt1[i]);
1385 current->is32|=(1LL<<rt1[i]);
1387 clear_const(current,rs1[i]);
1388 clear_const(current,rt1[i]);
1389 dirty_reg(current,rt1[i]);
1392 void shiftimm_alloc(struct regstat *current,int i)
1394 clear_const(current,rs1[i]);
1395 clear_const(current,rt1[i]);
1396 if(opcode2[i]<=0x3) // SLL/SRL/SRA
1399 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1401 alloc_reg(current,i,rt1[i]);
1402 current->is32|=1LL<<rt1[i];
1403 dirty_reg(current,rt1[i]);
1406 if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA
1409 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1410 alloc_reg64(current,i,rt1[i]);
1411 current->is32&=~(1LL<<rt1[i]);
1412 dirty_reg(current,rt1[i]);
1415 if(opcode2[i]==0x3c) // DSLL32
1418 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1419 alloc_reg64(current,i,rt1[i]);
1420 current->is32&=~(1LL<<rt1[i]);
1421 dirty_reg(current,rt1[i]);
1424 if(opcode2[i]==0x3e) // DSRL32
1427 alloc_reg64(current,i,rs1[i]);
1429 alloc_reg64(current,i,rt1[i]);
1430 current->is32&=~(1LL<<rt1[i]);
1432 alloc_reg(current,i,rt1[i]);
1433 current->is32|=1LL<<rt1[i];
1435 dirty_reg(current,rt1[i]);
1438 if(opcode2[i]==0x3f) // DSRA32
1441 alloc_reg64(current,i,rs1[i]);
1442 alloc_reg(current,i,rt1[i]);
1443 current->is32|=1LL<<rt1[i];
1444 dirty_reg(current,rt1[i]);
1449 void shift_alloc(struct regstat *current,int i)
1452 if(opcode2[i]<=0x07) // SLLV/SRLV/SRAV
1454 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1455 if(rs2[i]) alloc_reg(current,i,rs2[i]);
1456 alloc_reg(current,i,rt1[i]);
1457 if(rt1[i]==rs2[i]) {
1458 alloc_reg_temp(current,i,-1);
1459 minimum_free_regs[i]=1;
1461 current->is32|=1LL<<rt1[i];
1462 } else { // DSLLV/DSRLV/DSRAV
1463 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1464 if(rs2[i]) alloc_reg(current,i,rs2[i]);
1465 alloc_reg64(current,i,rt1[i]);
1466 current->is32&=~(1LL<<rt1[i]);
1467 if(opcode2[i]==0x16||opcode2[i]==0x17) // DSRLV and DSRAV need a temporary register
1469 alloc_reg_temp(current,i,-1);
1470 minimum_free_regs[i]=1;
1473 clear_const(current,rs1[i]);
1474 clear_const(current,rs2[i]);
1475 clear_const(current,rt1[i]);
1476 dirty_reg(current,rt1[i]);
1480 void alu_alloc(struct regstat *current,int i)
1482 if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
1484 if(rs1[i]&&rs2[i]) {
1485 alloc_reg(current,i,rs1[i]);
1486 alloc_reg(current,i,rs2[i]);
1489 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1490 if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]);
1492 alloc_reg(current,i,rt1[i]);
1494 current->is32|=1LL<<rt1[i];
1496 if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU
1498 if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1500 alloc_reg64(current,i,rs1[i]);
1501 alloc_reg64(current,i,rs2[i]);
1502 alloc_reg(current,i,rt1[i]);
1504 alloc_reg(current,i,rs1[i]);
1505 alloc_reg(current,i,rs2[i]);
1506 alloc_reg(current,i,rt1[i]);
1509 current->is32|=1LL<<rt1[i];
1511 if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR
1513 if(rs1[i]&&rs2[i]) {
1514 alloc_reg(current,i,rs1[i]);
1515 alloc_reg(current,i,rs2[i]);
1519 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1520 if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]);
1522 alloc_reg(current,i,rt1[i]);
1523 if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1525 if(!((current->uu>>rt1[i])&1)) {
1526 alloc_reg64(current,i,rt1[i]);
1528 if(get_reg(current->regmap,rt1[i]|64)>=0) {
1529 if(rs1[i]&&rs2[i]) {
1530 alloc_reg64(current,i,rs1[i]);
1531 alloc_reg64(current,i,rs2[i]);
1535 // Is is really worth it to keep 64-bit values in registers?
1537 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]);
1538 if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg64(current,i,rs2[i]);
1542 current->is32&=~(1LL<<rt1[i]);
1544 current->is32|=1LL<<rt1[i];
1548 if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU
1550 if(rs1[i]&&rs2[i]) {
1551 if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1552 alloc_reg64(current,i,rs1[i]);
1553 alloc_reg64(current,i,rs2[i]);
1554 alloc_reg64(current,i,rt1[i]);
1556 alloc_reg(current,i,rs1[i]);
1557 alloc_reg(current,i,rs2[i]);
1558 alloc_reg(current,i,rt1[i]);
1562 alloc_reg(current,i,rt1[i]);
1563 if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1564 // DADD used as move, or zeroing
1565 // If we have a 64-bit source, then make the target 64 bits too
1566 if(rs1[i]&&!((current->is32>>rs1[i])&1)) {
1567 if(get_reg(current->regmap,rs1[i])>=0) alloc_reg64(current,i,rs1[i]);
1568 alloc_reg64(current,i,rt1[i]);
1569 } else if(rs2[i]&&!((current->is32>>rs2[i])&1)) {
1570 if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]);
1571 alloc_reg64(current,i,rt1[i]);
1573 if(opcode2[i]>=0x2e&&rs2[i]) {
1574 // DSUB used as negation - 64-bit result
1575 // If we have a 32-bit register, extend it to 64 bits
1576 if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]);
1577 alloc_reg64(current,i,rt1[i]);
1581 if(rs1[i]&&rs2[i]) {
1582 current->is32&=~(1LL<<rt1[i]);
1584 current->is32&=~(1LL<<rt1[i]);
1585 if((current->is32>>rs1[i])&1)
1586 current->is32|=1LL<<rt1[i];
1588 current->is32&=~(1LL<<rt1[i]);
1589 if((current->is32>>rs2[i])&1)
1590 current->is32|=1LL<<rt1[i];
1592 current->is32|=1LL<<rt1[i];
1596 clear_const(current,rs1[i]);
1597 clear_const(current,rs2[i]);
1598 clear_const(current,rt1[i]);
1599 dirty_reg(current,rt1[i]);
1602 void imm16_alloc(struct regstat *current,int i)
1604 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1606 if(rt1[i]) alloc_reg(current,i,rt1[i]);
1607 if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU
1608 current->is32&=~(1LL<<rt1[i]);
1609 if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1610 // TODO: Could preserve the 32-bit flag if the immediate is zero
1611 alloc_reg64(current,i,rt1[i]);
1612 alloc_reg64(current,i,rs1[i]);
1614 clear_const(current,rs1[i]);
1615 clear_const(current,rt1[i]);
1617 else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU
1618 if((~current->is32>>rs1[i])&1) alloc_reg64(current,i,rs1[i]);
1619 current->is32|=1LL<<rt1[i];
1620 clear_const(current,rs1[i]);
1621 clear_const(current,rt1[i]);
1623 else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI
1624 if(((~current->is32>>rs1[i])&1)&&opcode[i]>0x0c) {
1625 if(rs1[i]!=rt1[i]) {
1626 if(needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]);
1627 alloc_reg64(current,i,rt1[i]);
1628 current->is32&=~(1LL<<rt1[i]);
1631 else current->is32|=1LL<<rt1[i]; // ANDI clears upper bits
1632 if(is_const(current,rs1[i])) {
1633 int v=get_const(current,rs1[i]);
1634 if(opcode[i]==0x0c) set_const(current,rt1[i],v&imm[i]);
1635 if(opcode[i]==0x0d) set_const(current,rt1[i],v|imm[i]);
1636 if(opcode[i]==0x0e) set_const(current,rt1[i],v^imm[i]);
1638 else clear_const(current,rt1[i]);
1640 else if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU
1641 if(is_const(current,rs1[i])) {
1642 int v=get_const(current,rs1[i]);
1643 set_const(current,rt1[i],v+imm[i]);
1645 else clear_const(current,rt1[i]);
1646 current->is32|=1LL<<rt1[i];
1649 set_const(current,rt1[i],((long long)((short)imm[i]))<<16); // LUI
1650 current->is32|=1LL<<rt1[i];
1652 dirty_reg(current,rt1[i]);
1655 void load_alloc(struct regstat *current,int i)
1657 clear_const(current,rt1[i]);
1658 //if(rs1[i]!=rt1[i]&&needed_again(rs1[i],i)) clear_const(current,rs1[i]); // Does this help or hurt?
1659 if(!rs1[i]) current->u&=~1LL; // Allow allocating r0 if it's the source register
1660 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1661 if(rt1[i]&&!((current->u>>rt1[i])&1)) {
1662 alloc_reg(current,i,rt1[i]);
1663 assert(get_reg(current->regmap,rt1[i])>=0);
1664 if(opcode[i]==0x27||opcode[i]==0x37) // LWU/LD
1666 current->is32&=~(1LL<<rt1[i]);
1667 alloc_reg64(current,i,rt1[i]);
1669 else if(opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
1671 current->is32&=~(1LL<<rt1[i]);
1672 alloc_reg64(current,i,rt1[i]);
1673 alloc_all(current,i);
1674 alloc_reg64(current,i,FTEMP);
1675 minimum_free_regs[i]=HOST_REGS;
1677 else current->is32|=1LL<<rt1[i];
1678 dirty_reg(current,rt1[i]);
1679 // If using TLB, need a register for pointer to the mapping table
1680 if(using_tlb) alloc_reg(current,i,TLREG);
1681 // LWL/LWR need a temporary register for the old value
1682 if(opcode[i]==0x22||opcode[i]==0x26)
1684 alloc_reg(current,i,FTEMP);
1685 alloc_reg_temp(current,i,-1);
1686 minimum_free_regs[i]=1;
1691 // Load to r0 or unneeded register (dummy load)
1692 // but we still need a register to calculate the address
1693 if(opcode[i]==0x22||opcode[i]==0x26)
1695 alloc_reg(current,i,FTEMP); // LWL/LWR need another temporary
1697 // If using TLB, need a register for pointer to the mapping table
1698 if(using_tlb) alloc_reg(current,i,TLREG);
1699 alloc_reg_temp(current,i,-1);
1700 minimum_free_regs[i]=1;
1701 if(opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
1703 alloc_all(current,i);
1704 alloc_reg64(current,i,FTEMP);
1705 minimum_free_regs[i]=HOST_REGS;
1710 void store_alloc(struct regstat *current,int i)
1712 clear_const(current,rs2[i]);
1713 if(!(rs2[i])) current->u&=~1LL; // Allow allocating r0 if necessary
1714 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1715 alloc_reg(current,i,rs2[i]);
1716 if(opcode[i]==0x2c||opcode[i]==0x2d||opcode[i]==0x3f) { // 64-bit SDL/SDR/SD
1717 alloc_reg64(current,i,rs2[i]);
1718 if(rs2[i]) alloc_reg(current,i,FTEMP);
1720 // If using TLB, need a register for pointer to the mapping table
1721 if(using_tlb) alloc_reg(current,i,TLREG);
1722 #if defined(HOST_IMM8)
1723 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1724 else alloc_reg(current,i,INVCP);
1726 if(opcode[i]==0x2a||opcode[i]==0x2e||opcode[i]==0x2c||opcode[i]==0x2d) { // SWL/SWL/SDL/SDR
1727 alloc_reg(current,i,FTEMP);
1729 // We need a temporary register for address generation
1730 alloc_reg_temp(current,i,-1);
1731 minimum_free_regs[i]=1;
1734 void c1ls_alloc(struct regstat *current,int i)
1736 //clear_const(current,rs1[i]); // FIXME
1737 clear_const(current,rt1[i]);
1738 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1739 alloc_reg(current,i,CSREG); // Status
1740 alloc_reg(current,i,FTEMP);
1741 if(opcode[i]==0x35||opcode[i]==0x3d) { // 64-bit LDC1/SDC1
1742 alloc_reg64(current,i,FTEMP);
1744 // If using TLB, need a register for pointer to the mapping table
1745 if(using_tlb) alloc_reg(current,i,TLREG);
1746 #if defined(HOST_IMM8)
1747 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1748 else if((opcode[i]&0x3b)==0x39) // SWC1/SDC1
1749 alloc_reg(current,i,INVCP);
1751 // We need a temporary register for address generation
1752 alloc_reg_temp(current,i,-1);
1755 void c2ls_alloc(struct regstat *current,int i)
1757 clear_const(current,rt1[i]);
1758 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1759 alloc_reg(current,i,FTEMP);
1760 // If using TLB, need a register for pointer to the mapping table
1761 if(using_tlb) alloc_reg(current,i,TLREG);
1762 #if defined(HOST_IMM8)
1763 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1764 else if((opcode[i]&0x3b)==0x3a) // SWC2/SDC2
1765 alloc_reg(current,i,INVCP);
1767 // We need a temporary register for address generation
1768 alloc_reg_temp(current,i,-1);
1769 minimum_free_regs[i]=1;
1772 #ifndef multdiv_alloc
1773 void multdiv_alloc(struct regstat *current,int i)
1780 // case 0x1D: DMULTU
1783 clear_const(current,rs1[i]);
1784 clear_const(current,rs2[i]);
1787 if((opcode2[i]&4)==0) // 32-bit
1789 current->u&=~(1LL<<HIREG);
1790 current->u&=~(1LL<<LOREG);
1791 alloc_reg(current,i,HIREG);
1792 alloc_reg(current,i,LOREG);
1793 alloc_reg(current,i,rs1[i]);
1794 alloc_reg(current,i,rs2[i]);
1795 current->is32|=1LL<<HIREG;
1796 current->is32|=1LL<<LOREG;
1797 dirty_reg(current,HIREG);
1798 dirty_reg(current,LOREG);
1802 current->u&=~(1LL<<HIREG);
1803 current->u&=~(1LL<<LOREG);
1804 current->uu&=~(1LL<<HIREG);
1805 current->uu&=~(1LL<<LOREG);
1806 alloc_reg64(current,i,HIREG);
1807 //if(HOST_REGS>10) alloc_reg64(current,i,LOREG);
1808 alloc_reg64(current,i,rs1[i]);
1809 alloc_reg64(current,i,rs2[i]);
1810 alloc_all(current,i);
1811 current->is32&=~(1LL<<HIREG);
1812 current->is32&=~(1LL<<LOREG);
1813 dirty_reg(current,HIREG);
1814 dirty_reg(current,LOREG);
1815 minimum_free_regs[i]=HOST_REGS;
1820 // Multiply by zero is zero.
1821 // MIPS does not have a divide by zero exception.
1822 // The result is undefined, we return zero.
1823 alloc_reg(current,i,HIREG);
1824 alloc_reg(current,i,LOREG);
1825 current->is32|=1LL<<HIREG;
1826 current->is32|=1LL<<LOREG;
1827 dirty_reg(current,HIREG);
1828 dirty_reg(current,LOREG);
1833 void cop0_alloc(struct regstat *current,int i)
1835 if(opcode2[i]==0) // MFC0
1838 clear_const(current,rt1[i]);
1839 alloc_all(current,i);
1840 alloc_reg(current,i,rt1[i]);
1841 current->is32|=1LL<<rt1[i];
1842 dirty_reg(current,rt1[i]);
1845 else if(opcode2[i]==4) // MTC0
1848 clear_const(current,rs1[i]);
1849 alloc_reg(current,i,rs1[i]);
1850 alloc_all(current,i);
1853 alloc_all(current,i); // FIXME: Keep r0
1855 alloc_reg(current,i,0);
1860 // TLBR/TLBWI/TLBWR/TLBP/ERET
1861 assert(opcode2[i]==0x10);
1862 alloc_all(current,i);
1864 minimum_free_regs[i]=HOST_REGS;
1867 void cop1_alloc(struct regstat *current,int i)
1869 alloc_reg(current,i,CSREG); // Load status
1870 if(opcode2[i]<3) // MFC1/DMFC1/CFC1
1873 clear_const(current,rt1[i]);
1875 alloc_reg64(current,i,rt1[i]); // DMFC1
1876 current->is32&=~(1LL<<rt1[i]);
1878 alloc_reg(current,i,rt1[i]); // MFC1/CFC1
1879 current->is32|=1LL<<rt1[i];
1881 dirty_reg(current,rt1[i]);
1883 alloc_reg_temp(current,i,-1);
1885 else if(opcode2[i]>3) // MTC1/DMTC1/CTC1
1888 clear_const(current,rs1[i]);
1890 alloc_reg64(current,i,rs1[i]); // DMTC1
1892 alloc_reg(current,i,rs1[i]); // MTC1/CTC1
1893 alloc_reg_temp(current,i,-1);
1897 alloc_reg(current,i,0);
1898 alloc_reg_temp(current,i,-1);
1901 minimum_free_regs[i]=1;
1903 void fconv_alloc(struct regstat *current,int i)
1905 alloc_reg(current,i,CSREG); // Load status
1906 alloc_reg_temp(current,i,-1);
1907 minimum_free_regs[i]=1;
1909 void float_alloc(struct regstat *current,int i)
1911 alloc_reg(current,i,CSREG); // Load status
1912 alloc_reg_temp(current,i,-1);
1913 minimum_free_regs[i]=1;
1915 void c2op_alloc(struct regstat *current,int i)
1917 alloc_reg_temp(current,i,-1);
1919 void fcomp_alloc(struct regstat *current,int i)
1921 alloc_reg(current,i,CSREG); // Load status
1922 alloc_reg(current,i,FSREG); // Load flags
1923 dirty_reg(current,FSREG); // Flag will be modified
1924 alloc_reg_temp(current,i,-1);
1925 minimum_free_regs[i]=1;
1928 void syscall_alloc(struct regstat *current,int i)
1930 alloc_cc(current,i);
1931 dirty_reg(current,CCREG);
1932 alloc_all(current,i);
1933 minimum_free_regs[i]=HOST_REGS;
1937 void delayslot_alloc(struct regstat *current,int i)
1948 assem_debug("jump in the delay slot. this shouldn't happen.\n");//exit(1);
1949 printf("Disabled speculative precompilation\n");
1953 imm16_alloc(current,i);
1957 load_alloc(current,i);
1961 store_alloc(current,i);
1964 alu_alloc(current,i);
1967 shift_alloc(current,i);
1970 multdiv_alloc(current,i);
1973 shiftimm_alloc(current,i);
1976 mov_alloc(current,i);
1979 cop0_alloc(current,i);
1983 cop1_alloc(current,i);
1986 c1ls_alloc(current,i);
1989 c2ls_alloc(current,i);
1992 fconv_alloc(current,i);
1995 float_alloc(current,i);
1998 fcomp_alloc(current,i);
2001 c2op_alloc(current,i);
2006 // Special case where a branch and delay slot span two pages in virtual memory
2007 static void pagespan_alloc(struct regstat *current,int i)
2010 current->wasconst=0;
2012 minimum_free_regs[i]=HOST_REGS;
2013 alloc_all(current,i);
2014 alloc_cc(current,i);
2015 dirty_reg(current,CCREG);
2016 if(opcode[i]==3) // JAL
2018 alloc_reg(current,i,31);
2019 dirty_reg(current,31);
2021 if(opcode[i]==0&&(opcode2[i]&0x3E)==8) // JR/JALR
2023 alloc_reg(current,i,rs1[i]);
2025 alloc_reg(current,i,rt1[i]);
2026 dirty_reg(current,rt1[i]);
2029 if((opcode[i]&0x2E)==4) // BEQ/BNE/BEQL/BNEL
2031 if(rs1[i]) alloc_reg(current,i,rs1[i]);
2032 if(rs2[i]) alloc_reg(current,i,rs2[i]);
2033 if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
2035 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
2036 if(rs2[i]) alloc_reg64(current,i,rs2[i]);
2040 if((opcode[i]&0x2E)==6) // BLEZ/BGTZ/BLEZL/BGTZL
2042 if(rs1[i]) alloc_reg(current,i,rs1[i]);
2043 if(!((current->is32>>rs1[i])&1))
2045 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
2049 if(opcode[i]==0x11) // BC1
2051 alloc_reg(current,i,FSREG);
2052 alloc_reg(current,i,CSREG);
2057 add_stub(int type,int addr,int retaddr,int a,int b,int c,int d,int e)
2059 stubs[stubcount][0]=type;
2060 stubs[stubcount][1]=addr;
2061 stubs[stubcount][2]=retaddr;
2062 stubs[stubcount][3]=a;
2063 stubs[stubcount][4]=b;
2064 stubs[stubcount][5]=c;
2065 stubs[stubcount][6]=d;
2066 stubs[stubcount][7]=e;
2070 // Write out a single register
2071 void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32)
2074 for(hr=0;hr<HOST_REGS;hr++) {
2075 if(hr!=EXCLUDE_REG) {
2076 if((regmap[hr]&63)==r) {
2079 emit_storereg(r,hr);
2081 if((is32>>regmap[hr])&1) {
2082 emit_sarimm(hr,31,hr);
2083 emit_storereg(r|64,hr);
2087 emit_storereg(r|64,hr);
2097 //if(!tracedebug) return 0;
2100 for(i=0;i<2097152;i++) {
2101 unsigned int temp=sum;
2104 sum^=((u_int *)rdram)[i];
2113 sum^=((u_int *)reg)[i];
2121 printf("r%d:%8x%8x ",i,((int *)(reg+i))[1],((int *)(reg+i))[0]);
2123 #ifndef DISABLE_COP1
2126 printf("f%d:%8x%8x ",i,((int*)reg_cop1_simple[i])[1],*((int*)reg_cop1_simple[i]));
2136 void memdebug(int i)
2138 //printf("TRACE: count=%d next=%d (checksum %x) lo=%8x%8x\n",Count,next_interupt,mchecksum(),(int)(reg[LOREG]>>32),(int)reg[LOREG]);
2139 //printf("TRACE: count=%d next=%d (rchecksum %x)\n",Count,next_interupt,rchecksum());
2142 //if(Count>=-2084597794) {
2143 if((signed int)Count>=-2084597794&&(signed int)Count<0) {
2145 printf("TRACE: count=%d next=%d (checksum %x)\n",Count,next_interupt,mchecksum());
2146 //printf("TRACE: count=%d next=%d (checksum %x) Status=%x\n",Count,next_interupt,mchecksum(),Status);
2147 //printf("TRACE: count=%d next=%d (checksum %x) hi=%8x%8x\n",Count,next_interupt,mchecksum(),(int)(reg[HIREG]>>32),(int)reg[HIREG]);
2150 printf("TRACE: %x\n",(&i)[-1]);
2154 printf("TRACE: %x \n",(&j)[10]);
2155 printf("TRACE: %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x\n",(&j)[1],(&j)[2],(&j)[3],(&j)[4],(&j)[5],(&j)[6],(&j)[7],(&j)[8],(&j)[9],(&j)[10],(&j)[11],(&j)[12],(&j)[13],(&j)[14],(&j)[15],(&j)[16],(&j)[17],(&j)[18],(&j)[19],(&j)[20]);
2159 //printf("TRACE: %x\n",(&i)[-1]);
2162 void tlb_debug(u_int cause, u_int addr, u_int iaddr)
2164 printf("TLB Exception: instruction=%x addr=%x cause=%x\n",iaddr, addr, cause);
2167 void alu_assemble(int i,struct regstat *i_regs)
2169 if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
2171 signed char s1,s2,t;
2172 t=get_reg(i_regs->regmap,rt1[i]);
2174 s1=get_reg(i_regs->regmap,rs1[i]);
2175 s2=get_reg(i_regs->regmap,rs2[i]);
2176 if(rs1[i]&&rs2[i]) {
2179 if(opcode2[i]&2) emit_sub(s1,s2,t);
2180 else emit_add(s1,s2,t);
2183 if(s1>=0) emit_mov(s1,t);
2184 else emit_loadreg(rs1[i],t);
2188 if(opcode2[i]&2) emit_neg(s2,t);
2189 else emit_mov(s2,t);
2192 emit_loadreg(rs2[i],t);
2193 if(opcode2[i]&2) emit_neg(t,t);
2196 else emit_zeroreg(t);
2200 if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU
2202 signed char s1l,s2l,s1h,s2h,tl,th;
2203 tl=get_reg(i_regs->regmap,rt1[i]);
2204 th=get_reg(i_regs->regmap,rt1[i]|64);
2206 s1l=get_reg(i_regs->regmap,rs1[i]);
2207 s2l=get_reg(i_regs->regmap,rs2[i]);
2208 s1h=get_reg(i_regs->regmap,rs1[i]|64);
2209 s2h=get_reg(i_regs->regmap,rs2[i]|64);
2210 if(rs1[i]&&rs2[i]) {
2213 if(opcode2[i]&2) emit_subs(s1l,s2l,tl);
2214 else emit_adds(s1l,s2l,tl);
2216 #ifdef INVERTED_CARRY
2217 if(opcode2[i]&2) {if(s1h!=th) emit_mov(s1h,th);emit_sbb(th,s2h);}
2219 if(opcode2[i]&2) emit_sbc(s1h,s2h,th);
2221 else emit_add(s1h,s2h,th);
2225 if(s1l>=0) emit_mov(s1l,tl);
2226 else emit_loadreg(rs1[i],tl);
2228 if(s1h>=0) emit_mov(s1h,th);
2229 else emit_loadreg(rs1[i]|64,th);
2234 if(opcode2[i]&2) emit_negs(s2l,tl);
2235 else emit_mov(s2l,tl);
2238 emit_loadreg(rs2[i],tl);
2239 if(opcode2[i]&2) emit_negs(tl,tl);
2242 #ifdef INVERTED_CARRY
2243 if(s2h>=0) emit_mov(s2h,th);
2244 else emit_loadreg(rs2[i]|64,th);
2246 emit_adcimm(-1,th); // x86 has inverted carry flag
2251 if(s2h>=0) emit_rscimm(s2h,0,th);
2253 emit_loadreg(rs2[i]|64,th);
2254 emit_rscimm(th,0,th);
2257 if(s2h>=0) emit_mov(s2h,th);
2258 else emit_loadreg(rs2[i]|64,th);
2265 if(th>=0) emit_zeroreg(th);
2270 if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU
2272 signed char s1l,s1h,s2l,s2h,t;
2273 if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1))
2275 t=get_reg(i_regs->regmap,rt1[i]);
2278 s1l=get_reg(i_regs->regmap,rs1[i]);
2279 s1h=get_reg(i_regs->regmap,rs1[i]|64);
2280 s2l=get_reg(i_regs->regmap,rs2[i]);
2281 s2h=get_reg(i_regs->regmap,rs2[i]|64);
2282 if(rs2[i]==0) // rx<r0
2285 if(opcode2[i]==0x2a) // SLT
2286 emit_shrimm(s1h,31,t);
2287 else // SLTU (unsigned can not be less than zero)
2290 else if(rs1[i]==0) // r0<rx
2293 if(opcode2[i]==0x2a) // SLT
2294 emit_set_gz64_32(s2h,s2l,t);
2295 else // SLTU (set if not zero)
2296 emit_set_nz64_32(s2h,s2l,t);
2299 assert(s1l>=0);assert(s1h>=0);
2300 assert(s2l>=0);assert(s2h>=0);
2301 if(opcode2[i]==0x2a) // SLT
2302 emit_set_if_less64_32(s1h,s1l,s2h,s2l,t);
2304 emit_set_if_carry64_32(s1h,s1l,s2h,s2l,t);
2308 t=get_reg(i_regs->regmap,rt1[i]);
2311 s1l=get_reg(i_regs->regmap,rs1[i]);
2312 s2l=get_reg(i_regs->regmap,rs2[i]);
2313 if(rs2[i]==0) // rx<r0
2316 if(opcode2[i]==0x2a) // SLT
2317 emit_shrimm(s1l,31,t);
2318 else // SLTU (unsigned can not be less than zero)
2321 else if(rs1[i]==0) // r0<rx
2324 if(opcode2[i]==0x2a) // SLT
2325 emit_set_gz32(s2l,t);
2326 else // SLTU (set if not zero)
2327 emit_set_nz32(s2l,t);
2330 assert(s1l>=0);assert(s2l>=0);
2331 if(opcode2[i]==0x2a) // SLT
2332 emit_set_if_less32(s1l,s2l,t);
2334 emit_set_if_carry32(s1l,s2l,t);
2340 if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR
2342 signed char s1l,s1h,s2l,s2h,th,tl;
2343 tl=get_reg(i_regs->regmap,rt1[i]);
2344 th=get_reg(i_regs->regmap,rt1[i]|64);
2345 if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1)&&th>=0)
2349 s1l=get_reg(i_regs->regmap,rs1[i]);
2350 s1h=get_reg(i_regs->regmap,rs1[i]|64);
2351 s2l=get_reg(i_regs->regmap,rs2[i]);
2352 s2h=get_reg(i_regs->regmap,rs2[i]|64);
2353 if(rs1[i]&&rs2[i]) {
2354 assert(s1l>=0);assert(s1h>=0);
2355 assert(s2l>=0);assert(s2h>=0);
2356 if(opcode2[i]==0x24) { // AND
2357 emit_and(s1l,s2l,tl);
2358 emit_and(s1h,s2h,th);
2360 if(opcode2[i]==0x25) { // OR
2361 emit_or(s1l,s2l,tl);
2362 emit_or(s1h,s2h,th);
2364 if(opcode2[i]==0x26) { // XOR
2365 emit_xor(s1l,s2l,tl);
2366 emit_xor(s1h,s2h,th);
2368 if(opcode2[i]==0x27) { // NOR
2369 emit_or(s1l,s2l,tl);
2370 emit_or(s1h,s2h,th);
2377 if(opcode2[i]==0x24) { // AND
2381 if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR
2383 if(s1l>=0) emit_mov(s1l,tl);
2384 else emit_loadreg(rs1[i],tl);
2385 if(s1h>=0) emit_mov(s1h,th);
2386 else emit_loadreg(rs1[i]|64,th);
2390 if(s2l>=0) emit_mov(s2l,tl);
2391 else emit_loadreg(rs2[i],tl);
2392 if(s2h>=0) emit_mov(s2h,th);
2393 else emit_loadreg(rs2[i]|64,th);
2400 if(opcode2[i]==0x27) { // NOR
2402 if(s1l>=0) emit_not(s1l,tl);
2404 emit_loadreg(rs1[i],tl);
2407 if(s1h>=0) emit_not(s1h,th);
2409 emit_loadreg(rs1[i]|64,th);
2415 if(s2l>=0) emit_not(s2l,tl);
2417 emit_loadreg(rs2[i],tl);
2420 if(s2h>=0) emit_not(s2h,th);
2422 emit_loadreg(rs2[i]|64,th);
2438 s1l=get_reg(i_regs->regmap,rs1[i]);
2439 s2l=get_reg(i_regs->regmap,rs2[i]);
2440 if(rs1[i]&&rs2[i]) {
2443 if(opcode2[i]==0x24) { // AND
2444 emit_and(s1l,s2l,tl);
2446 if(opcode2[i]==0x25) { // OR
2447 emit_or(s1l,s2l,tl);
2449 if(opcode2[i]==0x26) { // XOR
2450 emit_xor(s1l,s2l,tl);
2452 if(opcode2[i]==0x27) { // NOR
2453 emit_or(s1l,s2l,tl);
2459 if(opcode2[i]==0x24) { // AND
2462 if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR
2464 if(s1l>=0) emit_mov(s1l,tl);
2465 else emit_loadreg(rs1[i],tl); // CHECK: regmap_entry?
2469 if(s2l>=0) emit_mov(s2l,tl);
2470 else emit_loadreg(rs2[i],tl); // CHECK: regmap_entry?
2472 else emit_zeroreg(tl);
2474 if(opcode2[i]==0x27) { // NOR
2476 if(s1l>=0) emit_not(s1l,tl);
2478 emit_loadreg(rs1[i],tl);
2484 if(s2l>=0) emit_not(s2l,tl);
2486 emit_loadreg(rs2[i],tl);
2490 else emit_movimm(-1,tl);
2499 void imm16_assemble(int i,struct regstat *i_regs)
2501 if (opcode[i]==0x0f) { // LUI
2504 t=get_reg(i_regs->regmap,rt1[i]);
2507 if(!((i_regs->isconst>>t)&1))
2508 emit_movimm(imm[i]<<16,t);
2512 if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU
2515 t=get_reg(i_regs->regmap,rt1[i]);
2516 s=get_reg(i_regs->regmap,rs1[i]);
2521 if(!((i_regs->isconst>>t)&1)) {
2523 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2524 emit_addimm(t,imm[i],t);
2526 if(!((i_regs->wasconst>>s)&1))
2527 emit_addimm(s,imm[i],t);
2529 emit_movimm(constmap[i][s]+imm[i],t);
2535 if(!((i_regs->isconst>>t)&1))
2536 emit_movimm(imm[i],t);
2541 if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU
2543 signed char sh,sl,th,tl;
2544 th=get_reg(i_regs->regmap,rt1[i]|64);
2545 tl=get_reg(i_regs->regmap,rt1[i]);
2546 sh=get_reg(i_regs->regmap,rs1[i]|64);
2547 sl=get_reg(i_regs->regmap,rs1[i]);
2553 emit_addimm64_32(sh,sl,imm[i],th,tl);
2556 emit_addimm(sl,imm[i],tl);
2559 emit_movimm(imm[i],tl);
2560 if(th>=0) emit_movimm(((signed int)imm[i])>>31,th);
2565 else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU
2567 //assert(rs1[i]!=0); // r0 might be valid, but it's probably a bug
2568 signed char sh,sl,t;
2569 t=get_reg(i_regs->regmap,rt1[i]);
2570 sh=get_reg(i_regs->regmap,rs1[i]|64);
2571 sl=get_reg(i_regs->regmap,rs1[i]);
2575 if(sh<0) assert((i_regs->was32>>rs1[i])&1);
2576 if(sh<0||((i_regs->was32>>rs1[i])&1)) {
2577 if(opcode[i]==0x0a) { // SLTI
2579 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2580 emit_slti32(t,imm[i],t);
2582 emit_slti32(sl,imm[i],t);
2587 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2588 emit_sltiu32(t,imm[i],t);
2590 emit_sltiu32(sl,imm[i],t);
2595 if(opcode[i]==0x0a) // SLTI
2596 emit_slti64_32(sh,sl,imm[i],t);
2598 emit_sltiu64_32(sh,sl,imm[i],t);
2601 // SLTI(U) with r0 is just stupid,
2602 // nonetheless examples can be found
2603 if(opcode[i]==0x0a) // SLTI
2604 if(0<imm[i]) emit_movimm(1,t);
2605 else emit_zeroreg(t);
2608 if(imm[i]) emit_movimm(1,t);
2609 else emit_zeroreg(t);
2615 else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI
2617 signed char sh,sl,th,tl;
2618 th=get_reg(i_regs->regmap,rt1[i]|64);
2619 tl=get_reg(i_regs->regmap,rt1[i]);
2620 sh=get_reg(i_regs->regmap,rs1[i]|64);
2621 sl=get_reg(i_regs->regmap,rs1[i]);
2622 if(tl>=0 && !((i_regs->isconst>>tl)&1)) {
2623 if(opcode[i]==0x0c) //ANDI
2627 if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl);
2628 emit_andimm(tl,imm[i],tl);
2630 if(!((i_regs->wasconst>>sl)&1))
2631 emit_andimm(sl,imm[i],tl);
2633 emit_movimm(constmap[i][sl]&imm[i],tl);
2638 if(th>=0) emit_zeroreg(th);
2644 if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl);
2648 emit_loadreg(rs1[i]|64,th);
2653 if(opcode[i]==0x0d) //ORI
2655 emit_orimm(tl,imm[i],tl);
2657 if(!((i_regs->wasconst>>sl)&1))
2658 emit_orimm(sl,imm[i],tl);
2660 emit_movimm(constmap[i][sl]|imm[i],tl);
2662 if(opcode[i]==0x0e) //XORI
2664 emit_xorimm(tl,imm[i],tl);
2666 if(!((i_regs->wasconst>>sl)&1))
2667 emit_xorimm(sl,imm[i],tl);
2669 emit_movimm(constmap[i][sl]^imm[i],tl);
2673 emit_movimm(imm[i],tl);
2674 if(th>=0) emit_zeroreg(th);
2682 void shiftimm_assemble(int i,struct regstat *i_regs)
2684 if(opcode2[i]<=0x3) // SLL/SRL/SRA
2688 t=get_reg(i_regs->regmap,rt1[i]);
2689 s=get_reg(i_regs->regmap,rs1[i]);
2698 if(s<0&&i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2700 if(opcode2[i]==0) // SLL
2702 emit_shlimm(s<0?t:s,imm[i],t);
2704 if(opcode2[i]==2) // SRL
2706 emit_shrimm(s<0?t:s,imm[i],t);
2708 if(opcode2[i]==3) // SRA
2710 emit_sarimm(s<0?t:s,imm[i],t);
2714 if(s>=0 && s!=t) emit_mov(s,t);
2718 //emit_storereg(rt1[i],t); //DEBUG
2721 if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA
2724 signed char sh,sl,th,tl;
2725 th=get_reg(i_regs->regmap,rt1[i]|64);
2726 tl=get_reg(i_regs->regmap,rt1[i]);
2727 sh=get_reg(i_regs->regmap,rs1[i]|64);
2728 sl=get_reg(i_regs->regmap,rs1[i]);
2733 if(th>=0) emit_zeroreg(th);
2740 if(opcode2[i]==0x38) // DSLL
2742 if(th>=0) emit_shldimm(sh,sl,imm[i],th);
2743 emit_shlimm(sl,imm[i],tl);
2745 if(opcode2[i]==0x3a) // DSRL
2747 emit_shrdimm(sl,sh,imm[i],tl);
2748 if(th>=0) emit_shrimm(sh,imm[i],th);
2750 if(opcode2[i]==0x3b) // DSRA
2752 emit_shrdimm(sl,sh,imm[i],tl);
2753 if(th>=0) emit_sarimm(sh,imm[i],th);
2757 if(sl!=tl) emit_mov(sl,tl);
2758 if(th>=0&&sh!=th) emit_mov(sh,th);
2764 if(opcode2[i]==0x3c) // DSLL32
2767 signed char sl,tl,th;
2768 tl=get_reg(i_regs->regmap,rt1[i]);
2769 th=get_reg(i_regs->regmap,rt1[i]|64);
2770 sl=get_reg(i_regs->regmap,rs1[i]);
2779 emit_shlimm(th,imm[i]&31,th);
2784 if(opcode2[i]==0x3e) // DSRL32
2787 signed char sh,tl,th;
2788 tl=get_reg(i_regs->regmap,rt1[i]);
2789 th=get_reg(i_regs->regmap,rt1[i]|64);
2790 sh=get_reg(i_regs->regmap,rs1[i]|64);
2794 if(th>=0) emit_zeroreg(th);
2797 emit_shrimm(tl,imm[i]&31,tl);
2802 if(opcode2[i]==0x3f) // DSRA32
2806 tl=get_reg(i_regs->regmap,rt1[i]);
2807 sh=get_reg(i_regs->regmap,rs1[i]|64);
2813 emit_sarimm(tl,imm[i]&31,tl);
2820 #ifndef shift_assemble
2821 void shift_assemble(int i,struct regstat *i_regs)
2823 printf("Need shift_assemble for this architecture.\n");
2828 void load_assemble(int i,struct regstat *i_regs)
2830 int s,th,tl,addr,map=-1;
2833 int memtarget=0,c=0;
2834 int fastload_reg_override=0;
2836 th=get_reg(i_regs->regmap,rt1[i]|64);
2837 tl=get_reg(i_regs->regmap,rt1[i]);
2838 s=get_reg(i_regs->regmap,rs1[i]);
2840 for(hr=0;hr<HOST_REGS;hr++) {
2841 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
2843 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
2845 c=(i_regs->wasconst>>s)&1;
2847 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
2848 if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
2851 //printf("load_assemble: c=%d\n",c);
2852 //if(c) printf("load_assemble: const=%x\n",(int)constmap[i][s]+offset);
2853 // FIXME: Even if the load is a NOP, we should check for pagefaults...
2855 if(tl<0&&(!c||(((u_int)constmap[i][s]+offset)>>16)==0x1f80)
2857 // could be FIFO, must perform the read
2859 assem_debug("(forced read)\n");
2860 tl=get_reg(i_regs->regmap,-1);
2864 if(offset||s<0||c) addr=tl;
2866 //if(tl<0) tl=get_reg(i_regs->regmap,-1);
2868 //printf("load_assemble: c=%d\n",c);
2869 //if(c) printf("load_assemble: const=%x\n",(int)constmap[i][s]+offset);
2870 assert(tl>=0); // Even if the load is a NOP, we must check for pagefaults and I/O
2872 if(th>=0) reglist&=~(1<<th);
2876 map=get_reg(i_regs->regmap,ROREG);
2877 if(map<0) emit_loadreg(ROREG,map=HOST_TEMPREG);
2879 //#define R29_HACK 1
2881 // Strmnnrmn's speed hack
2882 if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
2886 if(sp_in_mirror&&rs1[i]==29) {
2887 emit_andimm(addr,~0x00e00000,HOST_TEMPREG);
2888 emit_cmpimm(HOST_TEMPREG,RAM_SIZE);
2889 fastload_reg_override=HOST_TEMPREG;
2893 emit_cmpimm(addr,RAM_SIZE);
2895 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
2896 // Hint to branch predictor that the branch is unlikely to be taken
2898 emit_jno_unlikely(0);
2906 if (opcode[i]==0x20||opcode[i]==0x24) x=3; // LB/LBU
2907 if (opcode[i]==0x21||opcode[i]==0x25) x=2; // LH/LHU
2908 map=get_reg(i_regs->regmap,TLREG);
2911 map=do_tlb_r(addr,tl,map,x,-1,-1,c,constmap[i][s]+offset);
2912 do_tlb_r_branch(map,c,constmap[i][s]+offset,&jaddr);
2914 int dummy=(rt1[i]==0)||(tl!=get_reg(i_regs->regmap,rt1[i])); // ignore loads to r0 and unneeded reg
2915 if (opcode[i]==0x20) { // LB
2918 #ifdef HOST_IMM_ADDR32
2920 emit_movsbl_tlb((constmap[i][s]+offset)^3,map,tl);
2924 //emit_xorimm(addr,3,tl);
2925 //gen_tlb_addr_r(tl,map);
2926 //emit_movsbl_indexed((int)rdram-0x80000000,tl,tl);
2928 #ifdef BIG_ENDIAN_MIPS
2929 if(!c) emit_xorimm(addr,3,tl);
2930 else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2934 if(fastload_reg_override) a=fastload_reg_override;
2936 emit_movsbl_indexed_tlb(x,a,map,tl);
2940 add_stub(LOADB_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2943 inline_readstub(LOADB_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2945 if (opcode[i]==0x21) { // LH
2948 #ifdef HOST_IMM_ADDR32
2950 emit_movswl_tlb((constmap[i][s]+offset)^2,map,tl);
2955 #ifdef BIG_ENDIAN_MIPS
2956 if(!c) emit_xorimm(addr,2,tl);
2957 else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
2961 if(fastload_reg_override) a=fastload_reg_override;
2963 //emit_movswl_indexed_tlb(x,tl,map,tl);
2966 gen_tlb_addr_r(a,map);
2967 emit_movswl_indexed(x,a,tl);
2970 emit_movswl_indexed(x,a,tl);
2972 emit_movswl_indexed((int)rdram-0x80000000+x,a,tl);
2978 add_stub(LOADH_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2981 inline_readstub(LOADH_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2983 if (opcode[i]==0x23) { // LW
2987 if(fastload_reg_override) a=fastload_reg_override;
2988 //emit_readword_indexed((int)rdram-0x80000000,addr,tl);
2989 #ifdef HOST_IMM_ADDR32
2991 emit_readword_tlb(constmap[i][s]+offset,map,tl);
2994 emit_readword_indexed_tlb(0,a,map,tl);
2997 add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3000 inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3002 if (opcode[i]==0x24) { // LBU
3005 #ifdef HOST_IMM_ADDR32
3007 emit_movzbl_tlb((constmap[i][s]+offset)^3,map,tl);
3011 //emit_xorimm(addr,3,tl);
3012 //gen_tlb_addr_r(tl,map);
3013 //emit_movzbl_indexed((int)rdram-0x80000000,tl,tl);
3015 #ifdef BIG_ENDIAN_MIPS
3016 if(!c) emit_xorimm(addr,3,tl);
3017 else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
3021 if(fastload_reg_override) a=fastload_reg_override;
3023 emit_movzbl_indexed_tlb(x,a,map,tl);
3027 add_stub(LOADBU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3030 inline_readstub(LOADBU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3032 if (opcode[i]==0x25) { // LHU
3035 #ifdef HOST_IMM_ADDR32
3037 emit_movzwl_tlb((constmap[i][s]+offset)^2,map,tl);
3042 #ifdef BIG_ENDIAN_MIPS
3043 if(!c) emit_xorimm(addr,2,tl);
3044 else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
3048 if(fastload_reg_override) a=fastload_reg_override;
3050 //emit_movzwl_indexed_tlb(x,tl,map,tl);
3053 gen_tlb_addr_r(a,map);
3054 emit_movzwl_indexed(x,a,tl);
3057 emit_movzwl_indexed(x,a,tl);
3059 emit_movzwl_indexed((int)rdram-0x80000000+x,a,tl);
3065 add_stub(LOADHU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3068 inline_readstub(LOADHU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3070 if (opcode[i]==0x27) { // LWU
3075 if(fastload_reg_override) a=fastload_reg_override;
3076 //emit_readword_indexed((int)rdram-0x80000000,addr,tl);
3077 #ifdef HOST_IMM_ADDR32
3079 emit_readword_tlb(constmap[i][s]+offset,map,tl);
3082 emit_readword_indexed_tlb(0,a,map,tl);
3085 add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3088 inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3092 if (opcode[i]==0x37) { // LD
3096 if(fastload_reg_override) a=fastload_reg_override;
3097 //gen_tlb_addr_r(tl,map);
3098 //if(th>=0) emit_readword_indexed((int)rdram-0x80000000,addr,th);
3099 //emit_readword_indexed((int)rdram-0x7FFFFFFC,addr,tl);
3100 #ifdef HOST_IMM_ADDR32
3102 emit_readdword_tlb(constmap[i][s]+offset,map,th,tl);
3105 emit_readdword_indexed_tlb(0,a,map,th,tl);
3108 add_stub(LOADD_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3111 inline_readstub(LOADD_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3114 //emit_storereg(rt1[i],tl); // DEBUG
3115 //if(opcode[i]==0x23)
3116 //if(opcode[i]==0x24)
3117 //if(opcode[i]==0x23||opcode[i]==0x24)
3118 /*if(opcode[i]==0x21||opcode[i]==0x23||opcode[i]==0x24)
3122 emit_readword((int)&last_count,ECX);
3124 if(get_reg(i_regs->regmap,CCREG)<0)
3125 emit_loadreg(CCREG,HOST_CCREG);
3126 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3127 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3128 emit_writeword(HOST_CCREG,(int)&Count);
3131 if(get_reg(i_regs->regmap,CCREG)<0)
3132 emit_loadreg(CCREG,0);
3134 emit_mov(HOST_CCREG,0);
3136 emit_addimm(0,2*ccadj[i],0);
3137 emit_writeword(0,(int)&Count);
3139 emit_call((int)memdebug);
3141 restore_regs(0x100f);
3145 #ifndef loadlr_assemble
3146 void loadlr_assemble(int i,struct regstat *i_regs)
3148 printf("Need loadlr_assemble for this architecture.\n");
3153 void store_assemble(int i,struct regstat *i_regs)
3158 int jaddr=0,jaddr2,type;
3159 int memtarget=0,c=0;
3160 int agr=AGEN1+(i&1);
3161 int faststore_reg_override=0;
3163 th=get_reg(i_regs->regmap,rs2[i]|64);
3164 tl=get_reg(i_regs->regmap,rs2[i]);
3165 s=get_reg(i_regs->regmap,rs1[i]);
3166 temp=get_reg(i_regs->regmap,agr);
3167 if(temp<0) temp=get_reg(i_regs->regmap,-1);
3170 c=(i_regs->wasconst>>s)&1;
3172 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
3173 if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
3178 for(hr=0;hr<HOST_REGS;hr++) {
3179 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3181 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
3182 if(offset||s<0||c) addr=temp;
3187 if(sp_in_mirror&&rs1[i]==29) {
3188 emit_andimm(addr,~0x00e00000,HOST_TEMPREG);
3189 emit_cmpimm(HOST_TEMPREG,RAM_SIZE);
3190 faststore_reg_override=HOST_TEMPREG;
3195 // Strmnnrmn's speed hack
3196 if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
3198 emit_cmpimm(addr,RAM_SIZE);
3199 #ifdef DESTRUCTIVE_SHIFT
3200 if(s==addr) emit_mov(s,temp);
3204 if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
3208 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
3209 // Hint to branch predictor that the branch is unlikely to be taken
3211 emit_jno_unlikely(0);
3219 if (opcode[i]==0x28) x=3; // SB
3220 if (opcode[i]==0x29) x=2; // SH
3221 map=get_reg(i_regs->regmap,TLREG);
3224 map=do_tlb_w(addr,temp,map,x,c,constmap[i][s]+offset);
3225 do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr);
3228 if (opcode[i]==0x28) { // SB
3231 #ifdef BIG_ENDIAN_MIPS
3232 if(!c) emit_xorimm(addr,3,temp);
3233 else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
3237 if(faststore_reg_override) a=faststore_reg_override;
3238 //gen_tlb_addr_w(temp,map);
3239 //emit_writebyte_indexed(tl,(int)rdram-0x80000000,temp);
3240 emit_writebyte_indexed_tlb(tl,x,a,map,a);
3244 if (opcode[i]==0x29) { // SH
3247 #ifdef BIG_ENDIAN_MIPS
3248 if(!c) emit_xorimm(addr,2,temp);
3249 else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
3253 if(faststore_reg_override) a=faststore_reg_override;
3255 //emit_writehword_indexed_tlb(tl,x,temp,map,temp);
3258 gen_tlb_addr_w(a,map);
3259 emit_writehword_indexed(tl,x,a);
3261 emit_writehword_indexed(tl,(int)rdram-0x80000000+x,a);
3265 if (opcode[i]==0x2B) { // SW
3268 if(faststore_reg_override) a=faststore_reg_override;
3269 //emit_writeword_indexed(tl,(int)rdram-0x80000000,addr);
3270 emit_writeword_indexed_tlb(tl,0,a,map,temp);
3274 if (opcode[i]==0x3F) { // SD
3277 if(faststore_reg_override) a=faststore_reg_override;
3280 //emit_writeword_indexed(th,(int)rdram-0x80000000,addr);
3281 //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,addr);
3282 emit_writedword_indexed_tlb(th,tl,0,a,map,temp);
3285 //emit_writeword_indexed(tl,(int)rdram-0x80000000,temp);
3286 //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,temp);
3287 emit_writedword_indexed_tlb(tl,tl,0,a,map,temp);
3294 // PCSX store handlers don't check invcode again
3296 add_stub(type,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3302 #ifdef DESTRUCTIVE_SHIFT
3303 // The x86 shift operation is 'destructive'; it overwrites the
3304 // source register, so we need to make a copy first and use that.
3307 #if defined(HOST_IMM8)
3308 int ir=get_reg(i_regs->regmap,INVCP);
3310 emit_cmpmem_indexedsr12_reg(ir,addr,1);
3312 emit_cmpmem_indexedsr12_imm((int)invalid_code,addr,1);
3314 #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3315 emit_callne(invalidate_addr_reg[addr]);
3319 add_stub(INVCODE_STUB,jaddr2,(int)out,reglist|(1<<HOST_CCREG),addr,0,0,0);
3324 add_stub(type,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3325 } else if(c&&!memtarget) {
3326 inline_writestub(type,i,constmap[i][s]+offset,i_regs->regmap,rs2[i],ccadj[i],reglist);
3328 //if(opcode[i]==0x2B || opcode[i]==0x3F)
3329 //if(opcode[i]==0x2B || opcode[i]==0x28)
3330 //if(opcode[i]==0x2B || opcode[i]==0x29)
3331 //if(opcode[i]==0x2B)
3332 /*if(opcode[i]==0x2B || opcode[i]==0x28 || opcode[i]==0x29 || opcode[i]==0x3F)
3340 emit_readword((int)&last_count,ECX);
3342 if(get_reg(i_regs->regmap,CCREG)<0)
3343 emit_loadreg(CCREG,HOST_CCREG);
3344 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3345 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3346 emit_writeword(HOST_CCREG,(int)&Count);
3349 if(get_reg(i_regs->regmap,CCREG)<0)
3350 emit_loadreg(CCREG,0);
3352 emit_mov(HOST_CCREG,0);
3354 emit_addimm(0,2*ccadj[i],0);
3355 emit_writeword(0,(int)&Count);
3357 emit_call((int)memdebug);
3362 restore_regs(0x100f);
3367 void storelr_assemble(int i,struct regstat *i_regs)
3374 int case1,case2,case3;
3375 int done0,done1,done2;
3376 int memtarget=0,c=0;
3377 int agr=AGEN1+(i&1);
3379 th=get_reg(i_regs->regmap,rs2[i]|64);
3380 tl=get_reg(i_regs->regmap,rs2[i]);
3381 s=get_reg(i_regs->regmap,rs1[i]);
3382 temp=get_reg(i_regs->regmap,agr);
3383 if(temp<0) temp=get_reg(i_regs->regmap,-1);
3386 c=(i_regs->isconst>>s)&1;
3388 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
3389 if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
3393 for(hr=0;hr<HOST_REGS;hr++) {
3394 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3399 emit_cmpimm(s<0||offset?temp:s,RAM_SIZE);
3400 if(!offset&&s!=temp) emit_mov(s,temp);
3406 if(!memtarget||!rs1[i]) {
3412 int map=get_reg(i_regs->regmap,ROREG);
3413 if(map<0) emit_loadreg(ROREG,map=HOST_TEMPREG);
3414 gen_tlb_addr_w(temp,map);
3416 if((u_int)rdram!=0x80000000)
3417 emit_addimm_no_flags((u_int)rdram-(u_int)0x80000000,temp);
3420 int map=get_reg(i_regs->regmap,TLREG);
3423 map=do_tlb_w(c||s<0||offset?temp:s,temp,map,0,c,constmap[i][s]+offset);
3424 if(!c&&!offset&&s>=0) emit_mov(s,temp);
3425 do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr);
3426 if(!jaddr&&!memtarget) {
3430 gen_tlb_addr_w(temp,map);
3433 if (opcode[i]==0x2C||opcode[i]==0x2D) { // SDL/SDR
3434 temp2=get_reg(i_regs->regmap,FTEMP);
3435 if(!rs2[i]) temp2=th=tl;
3438 #ifndef BIG_ENDIAN_MIPS
3439 emit_xorimm(temp,3,temp);
3441 emit_testimm(temp,2);
3444 emit_testimm(temp,1);
3448 if (opcode[i]==0x2A) { // SWL
3449 emit_writeword_indexed(tl,0,temp);
3451 if (opcode[i]==0x2E) { // SWR
3452 emit_writebyte_indexed(tl,3,temp);
3454 if (opcode[i]==0x2C) { // SDL
3455 emit_writeword_indexed(th,0,temp);
3456 if(rs2[i]) emit_mov(tl,temp2);
3458 if (opcode[i]==0x2D) { // SDR
3459 emit_writebyte_indexed(tl,3,temp);
3460 if(rs2[i]) emit_shldimm(th,tl,24,temp2);
3465 set_jump_target(case1,(int)out);
3466 if (opcode[i]==0x2A) { // SWL
3467 // Write 3 msb into three least significant bytes
3468 if(rs2[i]) emit_rorimm(tl,8,tl);
3469 emit_writehword_indexed(tl,-1,temp);
3470 if(rs2[i]) emit_rorimm(tl,16,tl);
3471 emit_writebyte_indexed(tl,1,temp);
3472 if(rs2[i]) emit_rorimm(tl,8,tl);
3474 if (opcode[i]==0x2E) { // SWR
3475 // Write two lsb into two most significant bytes
3476 emit_writehword_indexed(tl,1,temp);
3478 if (opcode[i]==0x2C) { // SDL
3479 if(rs2[i]) emit_shrdimm(tl,th,8,temp2);
3480 // Write 3 msb into three least significant bytes
3481 if(rs2[i]) emit_rorimm(th,8,th);
3482 emit_writehword_indexed(th,-1,temp);
3483 if(rs2[i]) emit_rorimm(th,16,th);
3484 emit_writebyte_indexed(th,1,temp);
3485 if(rs2[i]) emit_rorimm(th,8,th);
3487 if (opcode[i]==0x2D) { // SDR
3488 if(rs2[i]) emit_shldimm(th,tl,16,temp2);
3489 // Write two lsb into two most significant bytes
3490 emit_writehword_indexed(tl,1,temp);
3495 set_jump_target(case2,(int)out);
3496 emit_testimm(temp,1);
3499 if (opcode[i]==0x2A) { // SWL
3500 // Write two msb into two least significant bytes
3501 if(rs2[i]) emit_rorimm(tl,16,tl);
3502 emit_writehword_indexed(tl,-2,temp);
3503 if(rs2[i]) emit_rorimm(tl,16,tl);
3505 if (opcode[i]==0x2E) { // SWR
3506 // Write 3 lsb into three most significant bytes
3507 emit_writebyte_indexed(tl,-1,temp);
3508 if(rs2[i]) emit_rorimm(tl,8,tl);
3509 emit_writehword_indexed(tl,0,temp);
3510 if(rs2[i]) emit_rorimm(tl,24,tl);
3512 if (opcode[i]==0x2C) { // SDL
3513 if(rs2[i]) emit_shrdimm(tl,th,16,temp2);
3514 // Write two msb into two least significant bytes
3515 if(rs2[i]) emit_rorimm(th,16,th);
3516 emit_writehword_indexed(th,-2,temp);
3517 if(rs2[i]) emit_rorimm(th,16,th);
3519 if (opcode[i]==0x2D) { // SDR
3520 if(rs2[i]) emit_shldimm(th,tl,8,temp2);
3521 // Write 3 lsb into three most significant bytes
3522 emit_writebyte_indexed(tl,-1,temp);
3523 if(rs2[i]) emit_rorimm(tl,8,tl);
3524 emit_writehword_indexed(tl,0,temp);
3525 if(rs2[i]) emit_rorimm(tl,24,tl);
3530 set_jump_target(case3,(int)out);
3531 if (opcode[i]==0x2A) { // SWL
3532 // Write msb into least significant byte
3533 if(rs2[i]) emit_rorimm(tl,24,tl);
3534 emit_writebyte_indexed(tl,-3,temp);
3535 if(rs2[i]) emit_rorimm(tl,8,tl);
3537 if (opcode[i]==0x2E) { // SWR
3538 // Write entire word
3539 emit_writeword_indexed(tl,-3,temp);
3541 if (opcode[i]==0x2C) { // SDL
3542 if(rs2[i]) emit_shrdimm(tl,th,24,temp2);
3543 // Write msb into least significant byte
3544 if(rs2[i]) emit_rorimm(th,24,th);
3545 emit_writebyte_indexed(th,-3,temp);
3546 if(rs2[i]) emit_rorimm(th,8,th);
3548 if (opcode[i]==0x2D) { // SDR
3549 if(rs2[i]) emit_mov(th,temp2);
3550 // Write entire word
3551 emit_writeword_indexed(tl,-3,temp);
3553 set_jump_target(done0,(int)out);
3554 set_jump_target(done1,(int)out);
3555 set_jump_target(done2,(int)out);
3556 if (opcode[i]==0x2C) { // SDL
3557 emit_testimm(temp,4);
3560 emit_andimm(temp,~3,temp);
3561 emit_writeword_indexed(temp2,4,temp);
3562 set_jump_target(done0,(int)out);
3564 if (opcode[i]==0x2D) { // SDR
3565 emit_testimm(temp,4);
3568 emit_andimm(temp,~3,temp);
3569 emit_writeword_indexed(temp2,-4,temp);
3570 set_jump_target(done0,(int)out);
3573 add_stub(STORELR_STUB,jaddr,(int)out,i,(int)i_regs,temp,ccadj[i],reglist);
3576 int map=get_reg(i_regs->regmap,ROREG);
3577 if(map<0) map=HOST_TEMPREG;
3578 gen_orig_addr_w(temp,map);
3580 emit_addimm_no_flags((u_int)0x80000000-(u_int)rdram,temp);
3582 #if defined(HOST_IMM8)
3583 int ir=get_reg(i_regs->regmap,INVCP);
3585 emit_cmpmem_indexedsr12_reg(ir,temp,1);
3587 emit_cmpmem_indexedsr12_imm((int)invalid_code,temp,1);
3589 #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3590 emit_callne(invalidate_addr_reg[temp]);
3594 add_stub(INVCODE_STUB,jaddr2,(int)out,reglist|(1<<HOST_CCREG),temp,0,0,0);
3599 //save_regs(0x100f);
3600 emit_readword((int)&last_count,ECX);
3601 if(get_reg(i_regs->regmap,CCREG)<0)
3602 emit_loadreg(CCREG,HOST_CCREG);
3603 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3604 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3605 emit_writeword(HOST_CCREG,(int)&Count);
3606 emit_call((int)memdebug);
3608 //restore_regs(0x100f);
3612 void c1ls_assemble(int i,struct regstat *i_regs)
3614 #ifndef DISABLE_COP1
3620 int jaddr,jaddr2=0,jaddr3,type;
3621 int agr=AGEN1+(i&1);
3623 th=get_reg(i_regs->regmap,FTEMP|64);
3624 tl=get_reg(i_regs->regmap,FTEMP);
3625 s=get_reg(i_regs->regmap,rs1[i]);
3626 temp=get_reg(i_regs->regmap,agr);
3627 if(temp<0) temp=get_reg(i_regs->regmap,-1);
3632 for(hr=0;hr<HOST_REGS;hr++) {
3633 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3635 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
3636 if (opcode[i]==0x31||opcode[i]==0x35) // LWC1/LDC1
3638 // Loads use a temporary register which we need to save
3641 if (opcode[i]==0x39||opcode[i]==0x3D) // SWC1/SDC1
3645 //if(s<0) emit_loadreg(rs1[i],ar); //address_generation does this now
3646 //else c=(i_regs->wasconst>>s)&1;
3647 if(s>=0) c=(i_regs->wasconst>>s)&1;
3648 // Check cop1 unusable
3650 signed char rs=get_reg(i_regs->regmap,CSREG);
3652 emit_testimm(rs,0x20000000);
3655 add_stub(FP_STUB,jaddr,(int)out,i,rs,(int)i_regs,is_delayslot,0);
3658 if (opcode[i]==0x39) { // SWC1 (get float address)
3659 emit_readword((int)®_cop1_simple[(source[i]>>16)&0x1f],tl);
3661 if (opcode[i]==0x3D) { // SDC1 (get double address)
3662 emit_readword((int)®_cop1_double[(source[i]>>16)&0x1f],tl);
3664 // Generate address + offset
3667 emit_cmpimm(offset||c||s<0?ar:s,RAM_SIZE);
3671 map=get_reg(i_regs->regmap,TLREG);
3674 if (opcode[i]==0x31||opcode[i]==0x35) { // LWC1/LDC1
3675 map=do_tlb_r(offset||c||s<0?ar:s,ar,map,0,-1,-1,c,constmap[i][s]+offset);
3677 if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3678 map=do_tlb_w(offset||c||s<0?ar:s,ar,map,0,c,constmap[i][s]+offset);
3681 if (opcode[i]==0x39) { // SWC1 (read float)
3682 emit_readword_indexed(0,tl,tl);
3684 if (opcode[i]==0x3D) { // SDC1 (read double)
3685 emit_readword_indexed(4,tl,th);
3686 emit_readword_indexed(0,tl,tl);
3688 if (opcode[i]==0x31) { // LWC1 (get target address)
3689 emit_readword((int)®_cop1_simple[(source[i]>>16)&0x1f],temp);
3691 if (opcode[i]==0x35) { // LDC1 (get target address)
3692 emit_readword((int)®_cop1_double[(source[i]>>16)&0x1f],temp);
3699 else if(((signed int)(constmap[i][s]+offset))>=(signed int)0x80000000+RAM_SIZE) {
3701 emit_jmp(0); // inline_readstub/inline_writestub? Very rare case
3703 #ifdef DESTRUCTIVE_SHIFT
3704 if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3705 if(!offset&&!c&&s>=0) emit_mov(s,ar);
3709 if (opcode[i]==0x31||opcode[i]==0x35) { // LWC1/LDC1
3710 do_tlb_r_branch(map,c,constmap[i][s]+offset,&jaddr2);
3712 if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3713 do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr2);
3716 if (opcode[i]==0x31) { // LWC1
3717 //if(s>=0&&!c&&!offset) emit_mov(s,tl);
3718 //gen_tlb_addr_r(ar,map);
3719 //emit_readword_indexed((int)rdram-0x80000000,tl,tl);
3720 #ifdef HOST_IMM_ADDR32
3721 if(c) emit_readword_tlb(constmap[i][s]+offset,map,tl);
3724 emit_readword_indexed_tlb(0,offset||c||s<0?tl:s,map,tl);
3727 if (opcode[i]==0x35) { // LDC1
3729 //if(s>=0&&!c&&!offset) emit_mov(s,tl);
3730 //gen_tlb_addr_r(ar,map);
3731 //emit_readword_indexed((int)rdram-0x80000000,tl,th);
3732 //emit_readword_indexed((int)rdram-0x7FFFFFFC,tl,tl);
3733 #ifdef HOST_IMM_ADDR32
3734 if(c) emit_readdword_tlb(constmap[i][s]+offset,map,th,tl);
3737 emit_readdword_indexed_tlb(0,offset||c||s<0?tl:s,map,th,tl);
3740 if (opcode[i]==0x39) { // SWC1
3741 //emit_writeword_indexed(tl,(int)rdram-0x80000000,temp);
3742 emit_writeword_indexed_tlb(tl,0,offset||c||s<0?temp:s,map,temp);
3745 if (opcode[i]==0x3D) { // SDC1
3747 //emit_writeword_indexed(th,(int)rdram-0x80000000,temp);
3748 //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,temp);
3749 emit_writedword_indexed_tlb(th,tl,0,offset||c||s<0?temp:s,map,temp);
3753 if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3754 #ifndef DESTRUCTIVE_SHIFT
3755 temp=offset||c||s<0?ar:s;
3757 #if defined(HOST_IMM8)
3758 int ir=get_reg(i_regs->regmap,INVCP);
3760 emit_cmpmem_indexedsr12_reg(ir,temp,1);
3762 emit_cmpmem_indexedsr12_imm((int)invalid_code,temp,1);
3764 #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3765 emit_callne(invalidate_addr_reg[temp]);
3769 add_stub(INVCODE_STUB,jaddr3,(int)out,reglist|(1<<HOST_CCREG),temp,0,0,0);
3773 if(jaddr2) add_stub(type,jaddr2,(int)out,i,offset||c||s<0?ar:s,(int)i_regs,ccadj[i],reglist);
3774 if (opcode[i]==0x31) { // LWC1 (write float)
3775 emit_writeword_indexed(tl,0,temp);
3777 if (opcode[i]==0x35) { // LDC1 (write double)
3778 emit_writeword_indexed(th,4,temp);
3779 emit_writeword_indexed(tl,0,temp);
3781 //if(opcode[i]==0x39)
3782 /*if(opcode[i]==0x39||opcode[i]==0x31)
3785 emit_readword((int)&last_count,ECX);
3786 if(get_reg(i_regs->regmap,CCREG)<0)
3787 emit_loadreg(CCREG,HOST_CCREG);
3788 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3789 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3790 emit_writeword(HOST_CCREG,(int)&Count);
3791 emit_call((int)memdebug);
3795 cop1_unusable(i, i_regs);
3799 void c2ls_assemble(int i,struct regstat *i_regs)
3804 int memtarget=0,c=0;
3805 int jaddr2=0,jaddr3,type;
3806 int agr=AGEN1+(i&1);
3808 u_int copr=(source[i]>>16)&0x1f;
3809 s=get_reg(i_regs->regmap,rs1[i]);
3810 tl=get_reg(i_regs->regmap,FTEMP);
3816 for(hr=0;hr<HOST_REGS;hr++) {
3817 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3819 if(i_regs->regmap[HOST_CCREG]==CCREG)
3820 reglist&=~(1<<HOST_CCREG);
3823 if (opcode[i]==0x3a) { // SWC2
3824 ar=get_reg(i_regs->regmap,agr);
3825 if(ar<0) ar=get_reg(i_regs->regmap,-1);
3830 if(s>=0) c=(i_regs->wasconst>>s)&1;
3831 memtarget=c&&(((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE);
3832 if (!offset&&!c&&s>=0) ar=s;
3835 if (opcode[i]==0x3a) { // SWC2
3836 cop2_get_dreg(copr,tl,HOST_TEMPREG);
3844 emit_jmp(0); // inline_readstub/inline_writestub?
3848 emit_cmpimm(offset||c||s<0?ar:s,RAM_SIZE);
3852 if (opcode[i]==0x32) { // LWC2
3853 #ifdef HOST_IMM_ADDR32
3854 if(c) emit_readword_tlb(constmap[i][s]+offset,-1,tl);
3857 emit_readword_indexed(0,ar,tl);
3859 if (opcode[i]==0x3a) { // SWC2
3860 #ifdef DESTRUCTIVE_SHIFT
3861 if(!offset&&!c&&s>=0) emit_mov(s,ar);
3863 emit_writeword_indexed(tl,0,ar);
3867 add_stub(type,jaddr2,(int)out,i,ar,(int)i_regs,ccadj[i],reglist);
3868 if (opcode[i]==0x3a) { // SWC2
3869 #if defined(HOST_IMM8)
3870 int ir=get_reg(i_regs->regmap,INVCP);
3872 emit_cmpmem_indexedsr12_reg(ir,ar,1);
3874 emit_cmpmem_indexedsr12_imm((int)invalid_code,ar,1);
3876 #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3877 emit_callne(invalidate_addr_reg[ar]);
3881 add_stub(INVCODE_STUB,jaddr3,(int)out,reglist|(1<<HOST_CCREG),ar,0,0,0);
3884 if (opcode[i]==0x32) { // LWC2
3885 cop2_put_dreg(copr,tl,HOST_TEMPREG);
3889 #ifndef multdiv_assemble
3890 void multdiv_assemble(int i,struct regstat *i_regs)
3892 printf("Need multdiv_assemble for this architecture.\n");
3897 void mov_assemble(int i,struct regstat *i_regs)
3899 //if(opcode2[i]==0x10||opcode2[i]==0x12) { // MFHI/MFLO
3900 //if(opcode2[i]==0x11||opcode2[i]==0x13) { // MTHI/MTLO
3902 signed char sh,sl,th,tl;
3903 th=get_reg(i_regs->regmap,rt1[i]|64);
3904 tl=get_reg(i_regs->regmap,rt1[i]);
3907 sh=get_reg(i_regs->regmap,rs1[i]|64);
3908 sl=get_reg(i_regs->regmap,rs1[i]);
3909 if(sl>=0) emit_mov(sl,tl);
3910 else emit_loadreg(rs1[i],tl);
3912 if(sh>=0) emit_mov(sh,th);
3913 else emit_loadreg(rs1[i]|64,th);
3919 #ifndef fconv_assemble
3920 void fconv_assemble(int i,struct regstat *i_regs)
3922 printf("Need fconv_assemble for this architecture.\n");
3928 void float_assemble(int i,struct regstat *i_regs)
3930 printf("Need float_assemble for this architecture.\n");
3935 void syscall_assemble(int i,struct regstat *i_regs)
3937 signed char ccreg=get_reg(i_regs->regmap,CCREG);
3938 assert(ccreg==HOST_CCREG);
3939 assert(!is_delayslot);
3940 emit_movimm(start+i*4,EAX); // Get PC
3941 emit_addimm(HOST_CCREG,CLOCK_DIVIDER*ccadj[i],HOST_CCREG); // CHECK: is this right? There should probably be an extra cycle...
3942 emit_jmp((int)jump_syscall_hle); // XXX
3945 void hlecall_assemble(int i,struct regstat *i_regs)
3947 signed char ccreg=get_reg(i_regs->regmap,CCREG);
3948 assert(ccreg==HOST_CCREG);
3949 assert(!is_delayslot);
3950 emit_movimm(start+i*4+4,0); // Get PC
3951 emit_movimm((int)psxHLEt[source[i]&7],1);
3952 emit_addimm(HOST_CCREG,CLOCK_DIVIDER*ccadj[i],HOST_CCREG); // XXX
3953 emit_jmp((int)jump_hlecall);
3956 void intcall_assemble(int i,struct regstat *i_regs)
3958 signed char ccreg=get_reg(i_regs->regmap,CCREG);
3959 assert(ccreg==HOST_CCREG);
3960 assert(!is_delayslot);
3961 emit_movimm(start+i*4,0); // Get PC
3962 emit_addimm(HOST_CCREG,CLOCK_DIVIDER*ccadj[i],HOST_CCREG);
3963 emit_jmp((int)jump_intcall);
3966 void ds_assemble(int i,struct regstat *i_regs)
3971 alu_assemble(i,i_regs);break;
3973 imm16_assemble(i,i_regs);break;
3975 shift_assemble(i,i_regs);break;
3977 shiftimm_assemble(i,i_regs);break;
3979 load_assemble(i,i_regs);break;
3981 loadlr_assemble(i,i_regs);break;
3983 store_assemble(i,i_regs);break;
3985 storelr_assemble(i,i_regs);break;
3987 cop0_assemble(i,i_regs);break;
3989 cop1_assemble(i,i_regs);break;
3991 c1ls_assemble(i,i_regs);break;
3993 cop2_assemble(i,i_regs);break;
3995 c2ls_assemble(i,i_regs);break;
3997 c2op_assemble(i,i_regs);break;
3999 fconv_assemble(i,i_regs);break;
4001 float_assemble(i,i_regs);break;
4003 fcomp_assemble(i,i_regs);break;
4005 multdiv_assemble(i,i_regs);break;
4007 mov_assemble(i,i_regs);break;
4017 printf("Jump in the delay slot. This is probably a bug.\n");
4022 // Is the branch target a valid internal jump?
4023 int internal_branch(uint64_t i_is32,int addr)
4025 if(addr&1) return 0; // Indirect (register) jump
4026 if(addr>=start && addr<start+slen*4-4)
4028 int t=(addr-start)>>2;
4029 // Delay slots are not valid branch targets
4030 //if(t>0&&(itype[t-1]==RJUMP||itype[t-1]==UJUMP||itype[t-1]==CJUMP||itype[t-1]==SJUMP||itype[t-1]==FJUMP)) return 0;
4031 // 64 -> 32 bit transition requires a recompile
4032 /*if(is32[t]&~unneeded_reg_upper[t]&~i_is32)
4034 if(requires_32bit[t]&~i_is32) printf("optimizable: no\n");
4035 else printf("optimizable: yes\n");
4037 //if(is32[t]&~unneeded_reg_upper[t]&~i_is32) return 0;
4039 if(requires_32bit[t]&~i_is32) return 0;
4047 #ifndef wb_invalidate
4048 void wb_invalidate(signed char pre[],signed char entry[],uint64_t dirty,uint64_t is32,
4049 uint64_t u,uint64_t uu)
4052 for(hr=0;hr<HOST_REGS;hr++) {
4053 if(hr!=EXCLUDE_REG) {
4054 if(pre[hr]!=entry[hr]) {
4057 if(get_reg(entry,pre[hr])<0) {
4059 if(!((u>>pre[hr])&1)) {
4060 emit_storereg(pre[hr],hr);
4061 if( ((is32>>pre[hr])&1) && !((uu>>pre[hr])&1) ) {
4062 emit_sarimm(hr,31,hr);
4063 emit_storereg(pre[hr]|64,hr);
4067 if(!((uu>>(pre[hr]&63))&1) && !((is32>>(pre[hr]&63))&1)) {
4068 emit_storereg(pre[hr],hr);
4077 // Move from one register to another (no writeback)
4078 for(hr=0;hr<HOST_REGS;hr++) {
4079 if(hr!=EXCLUDE_REG) {
4080 if(pre[hr]!=entry[hr]) {
4081 if(pre[hr]>=0&&(pre[hr]&63)<TEMPREG) {
4083 if((nr=get_reg(entry,pre[hr]))>=0) {
4093 // Load the specified registers
4094 // This only loads the registers given as arguments because
4095 // we don't want to load things that will be overwritten
4096 void load_regs(signed char entry[],signed char regmap[],int is32,int rs1,int rs2)
4100 for(hr=0;hr<HOST_REGS;hr++) {
4101 if(hr!=EXCLUDE_REG&®map[hr]>=0) {
4102 if(entry[hr]!=regmap[hr]) {
4103 if(regmap[hr]==rs1||regmap[hr]==rs2)
4110 emit_loadreg(regmap[hr],hr);
4117 for(hr=0;hr<HOST_REGS;hr++) {
4118 if(hr!=EXCLUDE_REG&®map[hr]>=0) {
4119 if(entry[hr]!=regmap[hr]) {
4120 if(regmap[hr]-64==rs1||regmap[hr]-64==rs2)
4122 assert(regmap[hr]!=64);
4123 if((is32>>(regmap[hr]&63))&1) {
4124 int lr=get_reg(regmap,regmap[hr]-64);
4126 emit_sarimm(lr,31,hr);
4128 emit_loadreg(regmap[hr],hr);
4132 emit_loadreg(regmap[hr],hr);
4140 // Load registers prior to the start of a loop
4141 // so that they are not loaded within the loop
4142 static void loop_preload(signed char pre[],signed char entry[])
4145 for(hr=0;hr<HOST_REGS;hr++) {
4146 if(hr!=EXCLUDE_REG) {
4147 if(pre[hr]!=entry[hr]) {
4149 if(get_reg(pre,entry[hr])<0) {
4150 assem_debug("loop preload:\n");
4151 //printf("loop preload: %d\n",hr);
4155 else if(entry[hr]<TEMPREG)
4157 emit_loadreg(entry[hr],hr);
4159 else if(entry[hr]-64<TEMPREG)
4161 emit_loadreg(entry[hr],hr);
4170 // Generate address for load/store instruction
4171 // goes to AGEN for writes, FTEMP for LOADLR and cop1/2 loads
4172 void address_generation(int i,struct regstat *i_regs,signed char entry[])
4174 if(itype[i]==LOAD||itype[i]==LOADLR||itype[i]==STORE||itype[i]==STORELR||itype[i]==C1LS||itype[i]==C2LS) {
4176 int agr=AGEN1+(i&1);
4177 int mgr=MGEN1+(i&1);
4178 if(itype[i]==LOAD) {
4179 ra=get_reg(i_regs->regmap,rt1[i]);
4180 if(ra<0) ra=get_reg(i_regs->regmap,-1);
4183 if(itype[i]==LOADLR) {
4184 ra=get_reg(i_regs->regmap,FTEMP);
4186 if(itype[i]==STORE||itype[i]==STORELR) {
4187 ra=get_reg(i_regs->regmap,agr);
4188 if(ra<0) ra=get_reg(i_regs->regmap,-1);
4190 if(itype[i]==C1LS||itype[i]==C2LS) {
4191 if ((opcode[i]&0x3b)==0x31||(opcode[i]&0x3b)==0x32) // LWC1/LDC1/LWC2/LDC2
4192 ra=get_reg(i_regs->regmap,FTEMP);
4193 else { // SWC1/SDC1/SWC2/SDC2
4194 ra=get_reg(i_regs->regmap,agr);
4195 if(ra<0) ra=get_reg(i_regs->regmap,-1);
4198 int rs=get_reg(i_regs->regmap,rs1[i]);
4199 int rm=get_reg(i_regs->regmap,TLREG);
4202 int c=(i_regs->wasconst>>rs)&1;
4204 // Using r0 as a base address
4206 if(!entry||entry[rm]!=mgr) {
4207 generate_map_const(offset,rm);
4208 } // else did it in the previous cycle
4210 if(!entry||entry[ra]!=agr) {
4211 if (opcode[i]==0x22||opcode[i]==0x26) {
4212 emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR
4213 }else if (opcode[i]==0x1a||opcode[i]==0x1b) {
4214 emit_movimm(offset&0xFFFFFFF8,ra); // LDL/LDR
4216 emit_movimm(offset,ra);
4218 } // else did it in the previous cycle
4221 if(!entry||entry[ra]!=rs1[i])
4222 emit_loadreg(rs1[i],ra);
4223 //if(!entry||entry[ra]!=rs1[i])
4224 // printf("poor load scheduling!\n");
4228 if(!entry||entry[rm]!=mgr) {
4229 if(itype[i]==STORE||itype[i]==STORELR||(opcode[i]&0x3b)==0x39||(opcode[i]&0x3b)==0x3a) {
4230 // Stores to memory go thru the mapper to detect self-modifying
4231 // code, loads don't.
4232 if((unsigned int)(constmap[i][rs]+offset)>=0xC0000000 ||
4233 (unsigned int)(constmap[i][rs]+offset)<0x80000000+RAM_SIZE )
4234 generate_map_const(constmap[i][rs]+offset,rm);
4236 if((signed int)(constmap[i][rs]+offset)>=(signed int)0xC0000000)
4237 generate_map_const(constmap[i][rs]+offset,rm);
4241 if(rs1[i]!=rt1[i]||itype[i]!=LOAD) {
4242 if(!entry||entry[ra]!=agr) {
4243 if (opcode[i]==0x22||opcode[i]==0x26) {
4244 emit_movimm((constmap[i][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR
4245 }else if (opcode[i]==0x1a||opcode[i]==0x1b) {
4246 emit_movimm((constmap[i][rs]+offset)&0xFFFFFFF8,ra); // LDL/LDR
4248 #ifdef HOST_IMM_ADDR32
4249 if((itype[i]!=LOAD&&(opcode[i]&0x3b)!=0x31&&(opcode[i]&0x3b)!=0x32) || // LWC1/LDC1/LWC2/LDC2
4250 (using_tlb&&((signed int)constmap[i][rs]+offset)>=(signed int)0xC0000000))
4252 emit_movimm(constmap[i][rs]+offset,ra);
4254 } // else did it in the previous cycle
4255 } // else load_consts already did it
4257 if(offset&&!c&&rs1[i]) {
4259 emit_addimm(rs,offset,ra);
4261 emit_addimm(ra,offset,ra);
4266 // Preload constants for next instruction
4267 if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS||itype[i+1]==C2LS) {
4269 #ifndef HOST_IMM_ADDR32
4271 agr=MGEN1+((i+1)&1);
4272 ra=get_reg(i_regs->regmap,agr);
4274 int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
4275 int offset=imm[i+1];
4276 int c=(regs[i+1].wasconst>>rs)&1;
4278 if(itype[i+1]==STORE||itype[i+1]==STORELR
4279 ||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a) { // SWC1/SDC1, SWC2/SDC2
4280 // Stores to memory go thru the mapper to detect self-modifying
4281 // code, loads don't.
4282 if((unsigned int)(constmap[i+1][rs]+offset)>=0xC0000000 ||
4283 (unsigned int)(constmap[i+1][rs]+offset)<0x80000000+RAM_SIZE )
4284 generate_map_const(constmap[i+1][rs]+offset,ra);
4286 if((signed int)(constmap[i+1][rs]+offset)>=(signed int)0xC0000000)
4287 generate_map_const(constmap[i+1][rs]+offset,ra);
4290 /*else if(rs1[i]==0) {
4291 generate_map_const(offset,ra);
4296 agr=AGEN1+((i+1)&1);
4297 ra=get_reg(i_regs->regmap,agr);
4299 int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
4300 int offset=imm[i+1];
4301 int c=(regs[i+1].wasconst>>rs)&1;
4302 if(c&&(rs1[i+1]!=rt1[i+1]||itype[i+1]!=LOAD)) {
4303 if (opcode[i+1]==0x22||opcode[i+1]==0x26) {
4304 emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR
4305 }else if (opcode[i+1]==0x1a||opcode[i+1]==0x1b) {
4306 emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFF8,ra); // LDL/LDR
4308 #ifdef HOST_IMM_ADDR32
4309 if((itype[i+1]!=LOAD&&(opcode[i+1]&0x3b)!=0x31&&(opcode[i+1]&0x3b)!=0x32) || // LWC1/LDC1/LWC2/LDC2
4310 (using_tlb&&((signed int)constmap[i+1][rs]+offset)>=(signed int)0xC0000000))
4312 emit_movimm(constmap[i+1][rs]+offset,ra);
4315 else if(rs1[i+1]==0) {
4316 // Using r0 as a base address
4317 if (opcode[i+1]==0x22||opcode[i+1]==0x26) {
4318 emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR
4319 }else if (opcode[i+1]==0x1a||opcode[i+1]==0x1b) {
4320 emit_movimm(offset&0xFFFFFFF8,ra); // LDL/LDR
4322 emit_movimm(offset,ra);
4329 int get_final_value(int hr, int i, int *value)
4331 int reg=regs[i].regmap[hr];
4333 if(regs[i+1].regmap[hr]!=reg) break;
4334 if(!((regs[i+1].isconst>>hr)&1)) break;
4339 if(itype[i]==UJUMP||itype[i]==RJUMP||itype[i]==CJUMP||itype[i]==SJUMP) {
4340 *value=constmap[i][hr];
4344 if(itype[i+1]==UJUMP||itype[i+1]==RJUMP||itype[i+1]==CJUMP||itype[i+1]==SJUMP) {
4345 // Load in delay slot, out-of-order execution
4346 if(itype[i+2]==LOAD&&rs1[i+2]==reg&&rt1[i+2]==reg&&((regs[i+1].wasconst>>hr)&1))
4348 #ifdef HOST_IMM_ADDR32
4349 if(!using_tlb||((signed int)constmap[i][hr]+imm[i+2])<(signed int)0xC0000000) return 0;
4351 // Precompute load address
4352 *value=constmap[i][hr]+imm[i+2];
4356 if(itype[i+1]==LOAD&&rs1[i+1]==reg&&rt1[i+1]==reg)
4358 #ifdef HOST_IMM_ADDR32
4359 if(!using_tlb||((signed int)constmap[i][hr]+imm[i+1])<(signed int)0xC0000000) return 0;
4361 // Precompute load address
4362 *value=constmap[i][hr]+imm[i+1];
4363 //printf("c=%x imm=%x\n",(int)constmap[i][hr],imm[i+1]);
4368 *value=constmap[i][hr];
4369 //printf("c=%x\n",(int)constmap[i][hr]);
4370 if(i==slen-1) return 1;
4372 return !((unneeded_reg[i+1]>>reg)&1);
4374 return !((unneeded_reg_upper[i+1]>>reg)&1);
4378 // Load registers with known constants
4379 void load_consts(signed char pre[],signed char regmap[],int is32,int i)
4383 for(hr=0;hr<HOST_REGS;hr++) {
4384 if(hr!=EXCLUDE_REG&®map[hr]>=0) {
4385 //if(entry[hr]!=regmap[hr]) {
4386 if(i==0||!((regs[i-1].isconst>>hr)&1)||pre[hr]!=regmap[hr]||bt[i]) {
4387 if(((regs[i].isconst>>hr)&1)&®map[hr]<64&®map[hr]>0) {
4389 if(get_final_value(hr,i,&value)) {
4394 emit_movimm(value,hr);
4402 for(hr=0;hr<HOST_REGS;hr++) {
4403 if(hr!=EXCLUDE_REG&®map[hr]>=0) {
4404 //if(entry[hr]!=regmap[hr]) {
4405 if(i==0||!((regs[i-1].isconst>>hr)&1)||pre[hr]!=regmap[hr]||bt[i]) {
4406 if(((regs[i].isconst>>hr)&1)&®map[hr]>64) {
4407 if((is32>>(regmap[hr]&63))&1) {
4408 int lr=get_reg(regmap,regmap[hr]-64);
4410 emit_sarimm(lr,31,hr);
4415 if(get_final_value(hr,i,&value)) {
4420 emit_movimm(value,hr);
4429 void load_all_consts(signed char regmap[],int is32,u_int dirty,int i)
4433 for(hr=0;hr<HOST_REGS;hr++) {
4434 if(hr!=EXCLUDE_REG&®map[hr]>=0&&((dirty>>hr)&1)) {
4435 if(((regs[i].isconst>>hr)&1)&®map[hr]<64&®map[hr]>0) {
4436 int value=constmap[i][hr];
4441 emit_movimm(value,hr);
4447 for(hr=0;hr<HOST_REGS;hr++) {
4448 if(hr!=EXCLUDE_REG&®map[hr]>=0&&((dirty>>hr)&1)) {
4449 if(((regs[i].isconst>>hr)&1)&®map[hr]>64) {
4450 if((is32>>(regmap[hr]&63))&1) {
4451 int lr=get_reg(regmap,regmap[hr]-64);
4453 emit_sarimm(lr,31,hr);
4457 int value=constmap[i][hr];
4462 emit_movimm(value,hr);
4470 // Write out all dirty registers (except cycle count)
4471 void wb_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty)
4474 for(hr=0;hr<HOST_REGS;hr++) {
4475 if(hr!=EXCLUDE_REG) {
4476 if(i_regmap[hr]>0) {
4477 if(i_regmap[hr]!=CCREG) {
4478 if((i_dirty>>hr)&1) {
4479 if(i_regmap[hr]<64) {
4480 emit_storereg(i_regmap[hr],hr);
4482 if( ((i_is32>>i_regmap[hr])&1) ) {
4483 #ifdef DESTRUCTIVE_WRITEBACK
4484 emit_sarimm(hr,31,hr);
4485 emit_storereg(i_regmap[hr]|64,hr);
4487 emit_sarimm(hr,31,HOST_TEMPREG);
4488 emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
4493 if( !((i_is32>>(i_regmap[hr]&63))&1) ) {
4494 emit_storereg(i_regmap[hr],hr);
4503 // Write out dirty registers that we need to reload (pair with load_needed_regs)
4504 // This writes the registers not written by store_regs_bt
4505 void wb_needed_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4508 int t=(addr-start)>>2;
4509 for(hr=0;hr<HOST_REGS;hr++) {
4510 if(hr!=EXCLUDE_REG) {
4511 if(i_regmap[hr]>0) {
4512 if(i_regmap[hr]!=CCREG) {
4513 if(i_regmap[hr]==regs[t].regmap_entry[hr] && ((regs[t].dirty>>hr)&1) && !(((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) {
4514 if((i_dirty>>hr)&1) {
4515 if(i_regmap[hr]<64) {
4516 emit_storereg(i_regmap[hr],hr);
4518 if( ((i_is32>>i_regmap[hr])&1) ) {
4519 #ifdef DESTRUCTIVE_WRITEBACK
4520 emit_sarimm(hr,31,hr);
4521 emit_storereg(i_regmap[hr]|64,hr);
4523 emit_sarimm(hr,31,HOST_TEMPREG);
4524 emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
4529 if( !((i_is32>>(i_regmap[hr]&63))&1) ) {
4530 emit_storereg(i_regmap[hr],hr);
4541 // Load all registers (except cycle count)
4542 void load_all_regs(signed char i_regmap[])
4545 for(hr=0;hr<HOST_REGS;hr++) {
4546 if(hr!=EXCLUDE_REG) {
4547 if(i_regmap[hr]==0) {
4551 if(i_regmap[hr]>0 && (i_regmap[hr]&63)<TEMPREG && i_regmap[hr]!=CCREG)
4553 emit_loadreg(i_regmap[hr],hr);
4559 // Load all current registers also needed by next instruction
4560 void load_needed_regs(signed char i_regmap[],signed char next_regmap[])
4563 for(hr=0;hr<HOST_REGS;hr++) {
4564 if(hr!=EXCLUDE_REG) {
4565 if(get_reg(next_regmap,i_regmap[hr])>=0) {
4566 if(i_regmap[hr]==0) {
4570 if(i_regmap[hr]>0 && (i_regmap[hr]&63)<TEMPREG && i_regmap[hr]!=CCREG)
4572 emit_loadreg(i_regmap[hr],hr);
4579 // Load all regs, storing cycle count if necessary
4580 void load_regs_entry(int t)
4583 if(is_ds[t]) emit_addimm(HOST_CCREG,CLOCK_DIVIDER,HOST_CCREG);
4584 else if(ccadj[t]) emit_addimm(HOST_CCREG,-ccadj[t]*CLOCK_DIVIDER,HOST_CCREG);
4585 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) {
4586 emit_storereg(CCREG,HOST_CCREG);
4589 for(hr=0;hr<HOST_REGS;hr++) {
4590 if(regs[t].regmap_entry[hr]>=0&®s[t].regmap_entry[hr]<TEMPREG) {
4591 if(regs[t].regmap_entry[hr]==0) {
4594 else if(regs[t].regmap_entry[hr]!=CCREG)
4596 emit_loadreg(regs[t].regmap_entry[hr],hr);
4601 for(hr=0;hr<HOST_REGS;hr++) {
4602 if(regs[t].regmap_entry[hr]>=64&®s[t].regmap_entry[hr]<TEMPREG+64) {
4603 assert(regs[t].regmap_entry[hr]!=64);
4604 if((regs[t].was32>>(regs[t].regmap_entry[hr]&63))&1) {
4605 int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64);
4607 emit_loadreg(regs[t].regmap_entry[hr],hr);
4611 emit_sarimm(lr,31,hr);
4616 emit_loadreg(regs[t].regmap_entry[hr],hr);
4622 // Store dirty registers prior to branch
4623 void store_regs_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4625 if(internal_branch(i_is32,addr))
4627 int t=(addr-start)>>2;
4629 for(hr=0;hr<HOST_REGS;hr++) {
4630 if(hr!=EXCLUDE_REG) {
4631 if(i_regmap[hr]>0 && i_regmap[hr]!=CCREG) {
4632 if(i_regmap[hr]!=regs[t].regmap_entry[hr] || !((regs[t].dirty>>hr)&1) || (((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) {
4633 if((i_dirty>>hr)&1) {
4634 if(i_regmap[hr]<64) {
4635 if(!((unneeded_reg[t]>>i_regmap[hr])&1)) {
4636 emit_storereg(i_regmap[hr],hr);
4637 if( ((i_is32>>i_regmap[hr])&1) && !((unneeded_reg_upper[t]>>i_regmap[hr])&1) ) {
4638 #ifdef DESTRUCTIVE_WRITEBACK
4639 emit_sarimm(hr,31,hr);
4640 emit_storereg(i_regmap[hr]|64,hr);
4642 emit_sarimm(hr,31,HOST_TEMPREG);
4643 emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
4648 if( !((i_is32>>(i_regmap[hr]&63))&1) && !((unneeded_reg_upper[t]>>(i_regmap[hr]&63))&1) ) {
4649 emit_storereg(i_regmap[hr],hr);
4660 // Branch out of this block, write out all dirty regs
4661 wb_dirtys(i_regmap,i_is32,i_dirty);
4665 // Load all needed registers for branch target
4666 void load_regs_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4668 //if(addr>=start && addr<(start+slen*4))
4669 if(internal_branch(i_is32,addr))
4671 int t=(addr-start)>>2;
4673 // Store the cycle count before loading something else
4674 if(i_regmap[HOST_CCREG]!=CCREG) {
4675 assert(i_regmap[HOST_CCREG]==-1);
4677 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) {
4678 emit_storereg(CCREG,HOST_CCREG);
4681 for(hr=0;hr<HOST_REGS;hr++) {
4682 if(hr!=EXCLUDE_REG&®s[t].regmap_entry[hr]>=0&®s[t].regmap_entry[hr]<TEMPREG) {
4683 #ifdef DESTRUCTIVE_WRITEBACK
4684 if(i_regmap[hr]!=regs[t].regmap_entry[hr] || ( !((regs[t].dirty>>hr)&1) && ((i_dirty>>hr)&1) && (((i_is32&~unneeded_reg_upper[t])>>i_regmap[hr])&1) ) || (((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) {
4686 if(i_regmap[hr]!=regs[t].regmap_entry[hr] ) {
4688 if(regs[t].regmap_entry[hr]==0) {
4691 else if(regs[t].regmap_entry[hr]!=CCREG)
4693 emit_loadreg(regs[t].regmap_entry[hr],hr);
4699 for(hr=0;hr<HOST_REGS;hr++) {
4700 if(hr!=EXCLUDE_REG&®s[t].regmap_entry[hr]>=64&®s[t].regmap_entry[hr]<TEMPREG+64) {
4701 if(i_regmap[hr]!=regs[t].regmap_entry[hr]) {
4702 assert(regs[t].regmap_entry[hr]!=64);
4703 if((i_is32>>(regs[t].regmap_entry[hr]&63))&1) {
4704 int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64);
4706 emit_loadreg(regs[t].regmap_entry[hr],hr);
4710 emit_sarimm(lr,31,hr);
4715 emit_loadreg(regs[t].regmap_entry[hr],hr);
4718 else if((i_is32>>(regs[t].regmap_entry[hr]&63))&1) {
4719 int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64);
4721 emit_sarimm(lr,31,hr);
4728 int match_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4730 if(addr>=start && addr<start+slen*4-4)
4732 int t=(addr-start)>>2;
4734 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) return 0;
4735 for(hr=0;hr<HOST_REGS;hr++)
4739 if(i_regmap[hr]!=regs[t].regmap_entry[hr])
4741 if(regs[t].regmap_entry[hr]>=0&&(regs[t].regmap_entry[hr]|64)<TEMPREG+64)
4748 if(i_regmap[hr]<TEMPREG)
4750 if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4753 else if(i_regmap[hr]>=64&&i_regmap[hr]<TEMPREG+64)
4755 if(!((unneeded_reg_upper[t]>>(i_regmap[hr]&63))&1))
4760 else // Same register but is it 32-bit or dirty?
4763 if(!((regs[t].dirty>>hr)&1))
4767 if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4769 //printf("%x: dirty no match\n",addr);
4774 if((((regs[t].was32^i_is32)&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)
4776 //printf("%x: is32 no match\n",addr);
4782 //if(is32[t]&~unneeded_reg_upper[t]&~i_is32) return 0;
4784 if(requires_32bit[t]&~i_is32) return 0;
4786 // Delay slots are not valid branch targets
4787 //if(t>0&&(itype[t-1]==RJUMP||itype[t-1]==UJUMP||itype[t-1]==CJUMP||itype[t-1]==SJUMP||itype[t-1]==FJUMP)) return 0;
4788 // Delay slots require additional processing, so do not match
4789 if(is_ds[t]) return 0;
4794 for(hr=0;hr<HOST_REGS;hr++)
4800 if(hr!=HOST_CCREG||i_regmap[hr]!=CCREG)
4814 // Used when a branch jumps into the delay slot of another branch
4815 void ds_assemble_entry(int i)
4817 int t=(ba[i]-start)>>2;
4818 if(!instr_addr[t]) instr_addr[t]=(u_int)out;
4819 assem_debug("Assemble delay slot at %x\n",ba[i]);
4820 assem_debug("<->\n");
4821 if(regs[t].regmap_entry[HOST_CCREG]==CCREG&®s[t].regmap[HOST_CCREG]!=CCREG)
4822 wb_register(CCREG,regs[t].regmap_entry,regs[t].wasdirty,regs[t].was32);
4823 load_regs(regs[t].regmap_entry,regs[t].regmap,regs[t].was32,rs1[t],rs2[t]);
4824 address_generation(t,®s[t],regs[t].regmap_entry);
4825 if(itype[t]==STORE||itype[t]==STORELR||(opcode[t]&0x3b)==0x39||(opcode[t]&0x3b)==0x3a)
4826 load_regs(regs[t].regmap_entry,regs[t].regmap,regs[t].was32,INVCP,INVCP);
4831 alu_assemble(t,®s[t]);break;
4833 imm16_assemble(t,®s[t]);break;
4835 shift_assemble(t,®s[t]);break;
4837 shiftimm_assemble(t,®s[t]);break;
4839 load_assemble(t,®s[t]);break;
4841 loadlr_assemble(t,®s[t]);break;
4843 store_assemble(t,®s[t]);break;
4845 storelr_assemble(t,®s[t]);break;
4847 cop0_assemble(t,®s[t]);break;
4849 cop1_assemble(t,®s[t]);break;
4851 c1ls_assemble(t,®s[t]);break;
4853 cop2_assemble(t,®s[t]);break;
4855 c2ls_assemble(t,®s[t]);break;
4857 c2op_assemble(t,®s[t]);break;
4859 fconv_assemble(t,®s[t]);break;
4861 float_assemble(t,®s[t]);break;
4863 fcomp_assemble(t,®s[t]);break;
4865 multdiv_assemble(t,®s[t]);break;
4867 mov_assemble(t,®s[t]);break;
4877 printf("Jump in the delay slot. This is probably a bug.\n");
4879 store_regs_bt(regs[t].regmap,regs[t].is32,regs[t].dirty,ba[i]+4);
4880 load_regs_bt(regs[t].regmap,regs[t].is32,regs[t].dirty,ba[i]+4);
4881 if(internal_branch(regs[t].is32,ba[i]+4))
4882 assem_debug("branch: internal\n");
4884 assem_debug("branch: external\n");
4885 assert(internal_branch(regs[t].is32,ba[i]+4));
4886 add_to_linker((int)out,ba[i]+4,internal_branch(regs[t].is32,ba[i]+4));
4890 void do_cc(int i,signed char i_regmap[],int *adj,int addr,int taken,int invert)
4899 //if(ba[i]>=start && ba[i]<(start+slen*4))
4900 if(internal_branch(branch_regs[i].is32,ba[i]))
4902 int t=(ba[i]-start)>>2;
4903 if(is_ds[t]) *adj=-1; // Branch into delay slot adds an extra cycle
4911 if(taken==TAKEN && i==(ba[i]-start)>>2 && source[i+1]==0) {
4913 if(count&1) emit_addimm_and_set_flags(2*(count+2),HOST_CCREG);
4915 //emit_subfrommem(&idlecount,HOST_CCREG); // Count idle cycles
4916 emit_andimm(HOST_CCREG,3,HOST_CCREG);
4920 else if(*adj==0||invert) {
4921 emit_addimm_and_set_flags(CLOCK_DIVIDER*(count+2),HOST_CCREG);
4927 emit_cmpimm(HOST_CCREG,-CLOCK_DIVIDER*(count+2));
4931 add_stub(CC_STUB,jaddr,idle?idle:(int)out,(*adj==0||invert||idle)?0:(count+2),i,addr,taken,0);
4934 void do_ccstub(int n)
4937 assem_debug("do_ccstub %x\n",start+stubs[n][4]*4);
4938 set_jump_target(stubs[n][1],(int)out);
4940 if(stubs[n][6]==NULLDS) {
4941 // Delay slot instruction is nullified ("likely" branch)
4942 wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty);
4944 else if(stubs[n][6]!=TAKEN) {
4945 wb_dirtys(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty);
4948 if(internal_branch(branch_regs[i].is32,ba[i]))
4949 wb_needed_dirtys(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
4953 // Save PC as return address
4954 emit_movimm(stubs[n][5],EAX);
4955 emit_writeword(EAX,(int)&pcaddr);
4959 // Return address depends on which way the branch goes
4960 if(itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
4962 int s1l=get_reg(branch_regs[i].regmap,rs1[i]);
4963 int s1h=get_reg(branch_regs[i].regmap,rs1[i]|64);
4964 int s2l=get_reg(branch_regs[i].regmap,rs2[i]);
4965 int s2h=get_reg(branch_regs[i].regmap,rs2[i]|64);
4975 if((branch_regs[i].is32>>rs1[i])&(branch_regs[i].is32>>rs2[i])&1) {
4979 #ifdef DESTRUCTIVE_WRITEBACK
4981 if((branch_regs[i].dirty>>s1l)&(branch_regs[i].is32>>rs1[i])&1)
4982 emit_loadreg(rs1[i],s1l);
4985 if((branch_regs[i].dirty>>s1l)&(branch_regs[i].is32>>rs2[i])&1)
4986 emit_loadreg(rs2[i],s1l);
4989 if((branch_regs[i].dirty>>s2l)&(branch_regs[i].is32>>rs2[i])&1)
4990 emit_loadreg(rs2[i],s2l);
4993 int addr=-1,alt=-1,ntaddr=-1;
4996 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
4997 (branch_regs[i].regmap[hr]&63)!=rs1[i] &&
4998 (branch_regs[i].regmap[hr]&63)!=rs2[i] )
5006 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
5007 (branch_regs[i].regmap[hr]&63)!=rs1[i] &&
5008 (branch_regs[i].regmap[hr]&63)!=rs2[i] )
5014 if((opcode[i]&0x2E)==6) // BLEZ/BGTZ needs another register
5018 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
5019 (branch_regs[i].regmap[hr]&63)!=rs1[i] &&
5020 (branch_regs[i].regmap[hr]&63)!=rs2[i] )
5026 assert(hr<HOST_REGS);
5028 if((opcode[i]&0x2f)==4) // BEQ
5030 #ifdef HAVE_CMOV_IMM
5032 if(s2l>=0) emit_cmp(s1l,s2l);
5033 else emit_test(s1l,s1l);
5034 emit_cmov2imm_e_ne_compact(ba[i],start+i*4+8,addr);
5039 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
5041 if(s2h>=0) emit_cmp(s1h,s2h);
5042 else emit_test(s1h,s1h);
5043 emit_cmovne_reg(alt,addr);
5045 if(s2l>=0) emit_cmp(s1l,s2l);
5046 else emit_test(s1l,s1l);
5047 emit_cmovne_reg(alt,addr);
5050 if((opcode[i]&0x2f)==5) // BNE
5052 #ifdef HAVE_CMOV_IMM
5054 if(s2l>=0) emit_cmp(s1l,s2l);
5055 else emit_test(s1l,s1l);
5056 emit_cmov2imm_e_ne_compact(start+i*4+8,ba[i],addr);
5061 emit_mov2imm_compact(start+i*4+8,addr,ba[i],alt);
5063 if(s2h>=0) emit_cmp(s1h,s2h);
5064 else emit_test(s1h,s1h);
5065 emit_cmovne_reg(alt,addr);
5067 if(s2l>=0) emit_cmp(s1l,s2l);
5068 else emit_test(s1l,s1l);
5069 emit_cmovne_reg(alt,addr);
5072 if((opcode[i]&0x2f)==6) // BLEZ
5074 //emit_movimm(ba[i],alt);
5075 //emit_movimm(start+i*4+8,addr);
5076 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
5078 if(s1h>=0) emit_mov(addr,ntaddr);
5079 emit_cmovl_reg(alt,addr);
5082 emit_cmovne_reg(ntaddr,addr);
5083 emit_cmovs_reg(alt,addr);
5086 if((opcode[i]&0x2f)==7) // BGTZ
5088 //emit_movimm(ba[i],addr);
5089 //emit_movimm(start+i*4+8,ntaddr);
5090 emit_mov2imm_compact(ba[i],addr,start+i*4+8,ntaddr);
5092 if(s1h>=0) emit_mov(addr,alt);
5093 emit_cmovl_reg(ntaddr,addr);
5096 emit_cmovne_reg(alt,addr);
5097 emit_cmovs_reg(ntaddr,addr);
5100 if((opcode[i]==1)&&(opcode2[i]&0x2D)==0) // BLTZ
5102 //emit_movimm(ba[i],alt);
5103 //emit_movimm(start+i*4+8,addr);
5104 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
5105 if(s1h>=0) emit_test(s1h,s1h);
5106 else emit_test(s1l,s1l);
5107 emit_cmovs_reg(alt,addr);
5109 if((opcode[i]==1)&&(opcode2[i]&0x2D)==1) // BGEZ
5111 //emit_movimm(ba[i],addr);
5112 //emit_movimm(start+i*4+8,alt);
5113 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
5114 if(s1h>=0) emit_test(s1h,s1h);
5115 else emit_test(s1l,s1l);
5116 emit_cmovs_reg(alt,addr);
5118 if(opcode[i]==0x11 && opcode2[i]==0x08 ) {
5119 if(source[i]&0x10000) // BC1T
5121 //emit_movimm(ba[i],alt);
5122 //emit_movimm(start+i*4+8,addr);
5123 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
5124 emit_testimm(s1l,0x800000);
5125 emit_cmovne_reg(alt,addr);
5129 //emit_movimm(ba[i],addr);
5130 //emit_movimm(start+i*4+8,alt);
5131 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
5132 emit_testimm(s1l,0x800000);
5133 emit_cmovne_reg(alt,addr);
5136 emit_writeword(addr,(int)&pcaddr);
5141 int r=get_reg(branch_regs[i].regmap,rs1[i]);
5142 if(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]) {
5143 r=get_reg(branch_regs[i].regmap,RTEMP);
5145 emit_writeword(r,(int)&pcaddr);
5147 else {printf("Unknown branch type in do_ccstub\n");exit(1);}
5149 // Update cycle count
5150 assert(branch_regs[i].regmap[HOST_CCREG]==CCREG||branch_regs[i].regmap[HOST_CCREG]==-1);
5151 if(stubs[n][3]) emit_addimm(HOST_CCREG,CLOCK_DIVIDER*stubs[n][3],HOST_CCREG);
5152 emit_call((int)cc_interrupt);
5153 if(stubs[n][3]) emit_addimm(HOST_CCREG,-CLOCK_DIVIDER*stubs[n][3],HOST_CCREG);
5154 if(stubs[n][6]==TAKEN) {
5155 if(internal_branch(branch_regs[i].is32,ba[i]))
5156 load_needed_regs(branch_regs[i].regmap,regs[(ba[i]-start)>>2].regmap_entry);
5157 else if(itype[i]==RJUMP) {
5158 if(get_reg(branch_regs[i].regmap,RTEMP)>=0)
5159 emit_readword((int)&pcaddr,get_reg(branch_regs[i].regmap,RTEMP));
5161 emit_loadreg(rs1[i],get_reg(branch_regs[i].regmap,rs1[i]));
5163 }else if(stubs[n][6]==NOTTAKEN) {
5164 if(i<slen-2) load_needed_regs(branch_regs[i].regmap,regmap_pre[i+2]);
5165 else load_all_regs(branch_regs[i].regmap);
5166 }else if(stubs[n][6]==NULLDS) {
5167 // Delay slot instruction is nullified ("likely" branch)
5168 if(i<slen-2) load_needed_regs(regs[i].regmap,regmap_pre[i+2]);
5169 else load_all_regs(regs[i].regmap);
5171 load_all_regs(branch_regs[i].regmap);
5173 emit_jmp(stubs[n][2]); // return address
5175 /* This works but uses a lot of memory...
5176 emit_readword((int)&last_count,ECX);
5177 emit_add(HOST_CCREG,ECX,EAX);
5178 emit_writeword(EAX,(int)&Count);
5179 emit_call((int)gen_interupt);
5180 emit_readword((int)&Count,HOST_CCREG);
5181 emit_readword((int)&next_interupt,EAX);
5182 emit_readword((int)&pending_exception,EBX);
5183 emit_writeword(EAX,(int)&last_count);
5184 emit_sub(HOST_CCREG,EAX,HOST_CCREG);
5186 int jne_instr=(int)out;
5188 if(stubs[n][3]) emit_addimm(HOST_CCREG,-2*stubs[n][3],HOST_CCREG);
5189 load_all_regs(branch_regs[i].regmap);
5190 emit_jmp(stubs[n][2]); // return address
5191 set_jump_target(jne_instr,(int)out);
5192 emit_readword((int)&pcaddr,EAX);
5193 // Call get_addr_ht instead of doing the hash table here.
5194 // This code is executed infrequently and takes up a lot of space
5195 // so smaller is better.
5196 emit_storereg(CCREG,HOST_CCREG);
5198 emit_call((int)get_addr_ht);
5199 emit_loadreg(CCREG,HOST_CCREG);
5200 emit_addimm(ESP,4,ESP);
5204 add_to_linker(int addr,int target,int ext)
5206 link_addr[linkcount][0]=addr;
5207 link_addr[linkcount][1]=target;
5208 link_addr[linkcount][2]=ext;
5212 static void ujump_assemble_write_ra(int i)
5215 unsigned int return_address;
5216 rt=get_reg(branch_regs[i].regmap,31);
5217 assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5219 return_address=start+i*4+8;
5222 if(internal_branch(branch_regs[i].is32,return_address)&&rt1[i+1]!=31) {
5223 int temp=-1; // note: must be ds-safe
5227 if(temp>=0) do_miniht_insert(return_address,rt,temp);
5228 else emit_movimm(return_address,rt);
5236 if(i_regmap[temp]!=PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5239 emit_movimm(return_address,rt); // PC into link register
5241 emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
5247 void ujump_assemble(int i,struct regstat *i_regs)
5249 signed char *i_regmap=i_regs->regmap;
5251 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
5252 address_generation(i+1,i_regs,regs[i].regmap_entry);
5254 int temp=get_reg(branch_regs[i].regmap,PTEMP);
5255 if(rt1[i]==31&&temp>=0)
5257 int return_address=start+i*4+8;
5258 if(get_reg(branch_regs[i].regmap,31)>0)
5259 if(i_regmap[temp]==PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5262 if(rt1[i]==31&&(rt1[i]==rs1[i+1]||rt1[i]==rs2[i+1])) {
5263 ujump_assemble_write_ra(i); // writeback ra for DS
5266 ds_assemble(i+1,i_regs);
5267 uint64_t bc_unneeded=branch_regs[i].u;
5268 uint64_t bc_unneeded_upper=branch_regs[i].uu;
5269 bc_unneeded|=1|(1LL<<rt1[i]);
5270 bc_unneeded_upper|=1|(1LL<<rt1[i]);
5271 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5272 bc_unneeded,bc_unneeded_upper);
5273 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5274 if(!ra_done&&rt1[i]==31)
5275 ujump_assemble_write_ra(i);
5277 cc=get_reg(branch_regs[i].regmap,CCREG);
5278 assert(cc==HOST_CCREG);
5279 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5281 if(rt1[i]==31&&temp>=0) emit_prefetchreg(temp);
5283 do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5284 if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5285 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5286 if(internal_branch(branch_regs[i].is32,ba[i]))
5287 assem_debug("branch: internal\n");
5289 assem_debug("branch: external\n");
5290 if(internal_branch(branch_regs[i].is32,ba[i])&&is_ds[(ba[i]-start)>>2]) {
5291 ds_assemble_entry(i);
5294 add_to_linker((int)out,ba[i],internal_branch(branch_regs[i].is32,ba[i]));
5299 static void rjump_assemble_write_ra(int i)
5301 int rt,return_address;
5302 assert(rt1[i+1]!=rt1[i]);
5303 assert(rt2[i+1]!=rt1[i]);
5304 rt=get_reg(branch_regs[i].regmap,rt1[i]);
5305 assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5307 return_address=start+i*4+8;
5311 if(i_regmap[temp]!=PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5314 emit_movimm(return_address,rt); // PC into link register
5316 emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
5320 void rjump_assemble(int i,struct regstat *i_regs)
5322 signed char *i_regmap=i_regs->regmap;
5326 rs=get_reg(branch_regs[i].regmap,rs1[i]);
5328 if(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]) {
5329 // Delay slot abuse, make a copy of the branch address register
5330 temp=get_reg(branch_regs[i].regmap,RTEMP);
5332 assert(regs[i].regmap[temp]==RTEMP);
5336 address_generation(i+1,i_regs,regs[i].regmap_entry);
5340 if((temp=get_reg(branch_regs[i].regmap,PTEMP))>=0) {
5341 int return_address=start+i*4+8;
5342 if(i_regmap[temp]==PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5348 int rh=get_reg(regs[i].regmap,RHASH);
5349 if(rh>=0) do_preload_rhash(rh);
5352 if(rt1[i]!=0&&(rt1[i]==rs1[i+1]||rt1[i]==rs2[i+1])) {
5353 rjump_assemble_write_ra(i);
5356 ds_assemble(i+1,i_regs);
5357 uint64_t bc_unneeded=branch_regs[i].u;
5358 uint64_t bc_unneeded_upper=branch_regs[i].uu;
5359 bc_unneeded|=1|(1LL<<rt1[i]);
5360 bc_unneeded_upper|=1|(1LL<<rt1[i]);
5361 bc_unneeded&=~(1LL<<rs1[i]);
5362 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5363 bc_unneeded,bc_unneeded_upper);
5364 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],CCREG);
5365 if(!ra_done&&rt1[i]!=0)
5366 rjump_assemble_write_ra(i);
5367 cc=get_reg(branch_regs[i].regmap,CCREG);
5368 assert(cc==HOST_CCREG);
5370 int rh=get_reg(branch_regs[i].regmap,RHASH);
5371 int ht=get_reg(branch_regs[i].regmap,RHTBL);
5373 if(regs[i].regmap[rh]!=RHASH) do_preload_rhash(rh);
5374 do_preload_rhtbl(ht);
5378 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,-1);
5379 #ifdef DESTRUCTIVE_WRITEBACK
5380 if((branch_regs[i].dirty>>rs)&(branch_regs[i].is32>>rs1[i])&1) {
5381 if(rs1[i]!=rt1[i+1]&&rs1[i]!=rt2[i+1]) {
5382 emit_loadreg(rs1[i],rs);
5387 if(rt1[i]==31&&temp>=0) emit_prefetchreg(temp);
5391 do_miniht_load(ht,rh);
5394 //do_cc(i,branch_regs[i].regmap,&adj,-1,TAKEN);
5395 //if(adj) emit_addimm(cc,2*(ccadj[i]+2-adj),cc); // ??? - Shouldn't happen
5397 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG);
5398 add_stub(CC_STUB,(int)out,jump_vaddr_reg[rs],0,i,-1,TAKEN,0);
5400 //load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,-1);
5403 do_miniht_jump(rs,rh,ht);
5408 //if(rs!=EAX) emit_mov(rs,EAX);
5409 //emit_jmp((int)jump_vaddr_eax);
5410 emit_jmp(jump_vaddr_reg[rs]);
5415 emit_shrimm(rs,16,rs);
5416 emit_xor(temp,rs,rs);
5417 emit_movzwl_reg(rs,rs);
5418 emit_shlimm(rs,4,rs);
5419 emit_cmpmem_indexed((int)hash_table,rs,temp);
5420 emit_jne((int)out+14);
5421 emit_readword_indexed((int)hash_table+4,rs,rs);
5423 emit_cmpmem_indexed((int)hash_table+8,rs,temp);
5424 emit_addimm_no_flags(8,rs);
5425 emit_jeq((int)out-17);
5426 // No hit on hash table, call compiler
5429 #ifdef DEBUG_CYCLE_COUNT
5430 emit_readword((int)&last_count,ECX);
5431 emit_add(HOST_CCREG,ECX,HOST_CCREG);
5432 emit_readword((int)&next_interupt,ECX);
5433 emit_writeword(HOST_CCREG,(int)&Count);
5434 emit_sub(HOST_CCREG,ECX,HOST_CCREG);
5435 emit_writeword(ECX,(int)&last_count);
5438 emit_storereg(CCREG,HOST_CCREG);
5439 emit_call((int)get_addr);
5440 emit_loadreg(CCREG,HOST_CCREG);
5441 emit_addimm(ESP,4,ESP);
5443 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5444 if(rt1[i]!=31&&i<slen-2&&(((u_int)out)&7)) emit_mov(13,13);
5448 void cjump_assemble(int i,struct regstat *i_regs)
5450 signed char *i_regmap=i_regs->regmap;
5453 match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5454 assem_debug("match=%d\n",match);
5455 int s1h,s1l,s2h,s2l;
5456 int prev_cop1_usable=cop1_usable;
5457 int unconditional=0,nop=0;
5460 int internal=internal_branch(branch_regs[i].is32,ba[i]);
5461 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
5462 if(!match) invert=1;
5463 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5464 if(i>(ba[i]-start)>>2) invert=1;
5468 s1l=get_reg(branch_regs[i].regmap,rs1[i]);
5469 s1h=get_reg(branch_regs[i].regmap,rs1[i]|64);
5470 s2l=get_reg(branch_regs[i].regmap,rs2[i]);
5471 s2h=get_reg(branch_regs[i].regmap,rs2[i]|64);
5474 s1l=get_reg(i_regmap,rs1[i]);
5475 s1h=get_reg(i_regmap,rs1[i]|64);
5476 s2l=get_reg(i_regmap,rs2[i]);
5477 s2h=get_reg(i_regmap,rs2[i]|64);
5479 if(rs1[i]==0&&rs2[i]==0)
5481 if(opcode[i]&1) nop=1;
5482 else unconditional=1;
5483 //assert(opcode[i]!=5);
5484 //assert(opcode[i]!=7);
5485 //assert(opcode[i]!=0x15);
5486 //assert(opcode[i]!=0x17);
5492 only32=(regs[i].was32>>rs2[i])&1;
5497 only32=(regs[i].was32>>rs1[i])&1;
5500 only32=(regs[i].was32>>rs1[i])&(regs[i].was32>>rs2[i])&1;
5504 // Out of order execution (delay slot first)
5506 address_generation(i+1,i_regs,regs[i].regmap_entry);
5507 ds_assemble(i+1,i_regs);
5509 uint64_t bc_unneeded=branch_regs[i].u;
5510 uint64_t bc_unneeded_upper=branch_regs[i].uu;
5511 bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
5512 bc_unneeded_upper&=~((1LL<<us1[i])|(1LL<<us2[i]));
5514 bc_unneeded_upper|=1;
5515 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5516 bc_unneeded,bc_unneeded_upper);
5517 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],rs2[i]);
5518 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5519 cc=get_reg(branch_regs[i].regmap,CCREG);
5520 assert(cc==HOST_CCREG);
5522 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5523 //do_cc(i,branch_regs[i].regmap,&adj,unconditional?ba[i]:-1,unconditional);
5524 //assem_debug("cycle count (adj)\n");
5526 do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5527 if(i!=(ba[i]-start)>>2 || source[i+1]!=0) {
5528 if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5529 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5531 assem_debug("branch: internal\n");
5533 assem_debug("branch: external\n");
5534 if(internal&&is_ds[(ba[i]-start)>>2]) {
5535 ds_assemble_entry(i);
5538 add_to_linker((int)out,ba[i],internal);
5541 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5542 if(((u_int)out)&7) emit_addnop(0);
5547 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc);
5550 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
5553 int taken=0,nottaken=0,nottaken1=0;
5554 do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
5555 if(adj&&!invert) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5559 if(opcode[i]==4) // BEQ
5561 if(s2h>=0) emit_cmp(s1h,s2h);
5562 else emit_test(s1h,s1h);
5566 if(opcode[i]==5) // BNE
5568 if(s2h>=0) emit_cmp(s1h,s2h);
5569 else emit_test(s1h,s1h);
5570 if(invert) taken=(int)out;
5571 else add_to_linker((int)out,ba[i],internal);
5574 if(opcode[i]==6) // BLEZ
5577 if(invert) taken=(int)out;
5578 else add_to_linker((int)out,ba[i],internal);
5583 if(opcode[i]==7) // BGTZ
5588 if(invert) taken=(int)out;
5589 else add_to_linker((int)out,ba[i],internal);
5594 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5596 if(opcode[i]==4) // BEQ
5598 if(s2l>=0) emit_cmp(s1l,s2l);
5599 else emit_test(s1l,s1l);
5604 add_to_linker((int)out,ba[i],internal);
5608 if(opcode[i]==5) // BNE
5610 if(s2l>=0) emit_cmp(s1l,s2l);
5611 else emit_test(s1l,s1l);
5616 add_to_linker((int)out,ba[i],internal);
5620 if(opcode[i]==6) // BLEZ
5627 add_to_linker((int)out,ba[i],internal);
5631 if(opcode[i]==7) // BGTZ
5638 add_to_linker((int)out,ba[i],internal);
5643 if(taken) set_jump_target(taken,(int)out);
5644 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5645 if(match&&(!internal||!is_ds[(ba[i]-start)>>2])) {
5647 emit_addimm(cc,-CLOCK_DIVIDER*adj,cc);
5648 add_to_linker((int)out,ba[i],internal);
5651 add_to_linker((int)out,ba[i],internal*2);
5657 if(adj) emit_addimm(cc,-CLOCK_DIVIDER*adj,cc);
5658 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5659 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5661 assem_debug("branch: internal\n");
5663 assem_debug("branch: external\n");
5664 if(internal&&is_ds[(ba[i]-start)>>2]) {
5665 ds_assemble_entry(i);
5668 add_to_linker((int)out,ba[i],internal);
5672 set_jump_target(nottaken,(int)out);
5675 if(nottaken1) set_jump_target(nottaken1,(int)out);
5677 if(!invert) emit_addimm(cc,CLOCK_DIVIDER*adj,cc);
5679 } // (!unconditional)
5683 // In-order execution (branch first)
5684 //if(likely[i]) printf("IOL\n");
5687 int taken=0,nottaken=0,nottaken1=0;
5688 if(!unconditional&&!nop) {
5692 if((opcode[i]&0x2f)==4) // BEQ
5694 if(s2h>=0) emit_cmp(s1h,s2h);
5695 else emit_test(s1h,s1h);
5699 if((opcode[i]&0x2f)==5) // BNE
5701 if(s2h>=0) emit_cmp(s1h,s2h);
5702 else emit_test(s1h,s1h);
5706 if((opcode[i]&0x2f)==6) // BLEZ
5714 if((opcode[i]&0x2f)==7) // BGTZ
5724 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5726 if((opcode[i]&0x2f)==4) // BEQ
5728 if(s2l>=0) emit_cmp(s1l,s2l);
5729 else emit_test(s1l,s1l);
5733 if((opcode[i]&0x2f)==5) // BNE
5735 if(s2l>=0) emit_cmp(s1l,s2l);
5736 else emit_test(s1l,s1l);
5740 if((opcode[i]&0x2f)==6) // BLEZ
5746 if((opcode[i]&0x2f)==7) // BGTZ
5752 } // if(!unconditional)
5754 uint64_t ds_unneeded=branch_regs[i].u;
5755 uint64_t ds_unneeded_upper=branch_regs[i].uu;
5756 ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
5757 ds_unneeded_upper&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
5758 if((~ds_unneeded_upper>>rt1[i+1])&1) ds_unneeded_upper&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
5760 ds_unneeded_upper|=1;
5763 if(taken) set_jump_target(taken,(int)out);
5764 assem_debug("1:\n");
5765 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5766 ds_unneeded,ds_unneeded_upper);
5768 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
5769 address_generation(i+1,&branch_regs[i],0);
5770 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,INVCP);
5771 ds_assemble(i+1,&branch_regs[i]);
5772 cc=get_reg(branch_regs[i].regmap,CCREG);
5774 emit_loadreg(CCREG,cc=HOST_CCREG);
5775 // CHECK: Is the following instruction (fall thru) allocated ok?
5777 assert(cc==HOST_CCREG);
5778 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5779 do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
5780 assem_debug("cycle count (adj)\n");
5781 if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5782 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5784 assem_debug("branch: internal\n");
5786 assem_debug("branch: external\n");
5787 if(internal&&is_ds[(ba[i]-start)>>2]) {
5788 ds_assemble_entry(i);
5791 add_to_linker((int)out,ba[i],internal);
5796 cop1_usable=prev_cop1_usable;
5797 if(!unconditional) {
5798 if(nottaken1) set_jump_target(nottaken1,(int)out);
5799 set_jump_target(nottaken,(int)out);
5800 assem_debug("2:\n");
5802 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5803 ds_unneeded,ds_unneeded_upper);
5804 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
5805 address_generation(i+1,&branch_regs[i],0);
5806 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5807 ds_assemble(i+1,&branch_regs[i]);
5809 cc=get_reg(branch_regs[i].regmap,CCREG);
5810 if(cc==-1&&!likely[i]) {
5811 // Cycle count isn't in a register, temporarily load it then write it out
5812 emit_loadreg(CCREG,HOST_CCREG);
5813 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG);
5816 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
5817 emit_storereg(CCREG,HOST_CCREG);
5820 cc=get_reg(i_regmap,CCREG);
5821 assert(cc==HOST_CCREG);
5822 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc);
5825 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
5831 void sjump_assemble(int i,struct regstat *i_regs)
5833 signed char *i_regmap=i_regs->regmap;
5836 match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5837 assem_debug("smatch=%d\n",match);
5839 int prev_cop1_usable=cop1_usable;
5840 int unconditional=0,nevertaken=0;
5843 int internal=internal_branch(branch_regs[i].is32,ba[i]);
5844 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
5845 if(!match) invert=1;
5846 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5847 if(i>(ba[i]-start)>>2) invert=1;
5850 //if(opcode2[i]>=0x10) return; // FIXME (BxxZAL)
5851 //assert(opcode2[i]<0x10||rs1[i]==0); // FIXME (BxxZAL)
5854 s1l=get_reg(branch_regs[i].regmap,rs1[i]);
5855 s1h=get_reg(branch_regs[i].regmap,rs1[i]|64);
5858 s1l=get_reg(i_regmap,rs1[i]);
5859 s1h=get_reg(i_regmap,rs1[i]|64);
5863 if(opcode2[i]&1) unconditional=1;
5865 // These are never taken (r0 is never less than zero)
5866 //assert(opcode2[i]!=0);
5867 //assert(opcode2[i]!=2);
5868 //assert(opcode2[i]!=0x10);
5869 //assert(opcode2[i]!=0x12);
5872 only32=(regs[i].was32>>rs1[i])&1;
5876 // Out of order execution (delay slot first)
5878 address_generation(i+1,i_regs,regs[i].regmap_entry);
5879 ds_assemble(i+1,i_regs);
5881 uint64_t bc_unneeded=branch_regs[i].u;
5882 uint64_t bc_unneeded_upper=branch_regs[i].uu;
5883 bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
5884 bc_unneeded_upper&=~((1LL<<us1[i])|(1LL<<us2[i]));
5886 bc_unneeded_upper|=1;
5887 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5888 bc_unneeded,bc_unneeded_upper);
5889 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],rs1[i]);
5890 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5892 int rt,return_address;
5893 rt=get_reg(branch_regs[i].regmap,31);
5894 assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5896 // Save the PC even if the branch is not taken
5897 return_address=start+i*4+8;
5898 emit_movimm(return_address,rt); // PC into link register
5900 if(!nevertaken) emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
5904 cc=get_reg(branch_regs[i].regmap,CCREG);
5905 assert(cc==HOST_CCREG);
5907 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5908 //do_cc(i,branch_regs[i].regmap,&adj,unconditional?ba[i]:-1,unconditional);
5909 assem_debug("cycle count (adj)\n");
5911 do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5912 if(i!=(ba[i]-start)>>2 || source[i+1]!=0) {
5913 if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5914 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5916 assem_debug("branch: internal\n");
5918 assem_debug("branch: external\n");
5919 if(internal&&is_ds[(ba[i]-start)>>2]) {
5920 ds_assemble_entry(i);
5923 add_to_linker((int)out,ba[i],internal);
5926 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5927 if(((u_int)out)&7) emit_addnop(0);
5931 else if(nevertaken) {
5932 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc);
5935 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
5939 do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
5940 if(adj&&!invert) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5944 if((opcode2[i]&0xf)==0) // BLTZ/BLTZAL
5951 add_to_linker((int)out,ba[i],internal);
5955 if((opcode2[i]&0xf)==1) // BGEZ/BLTZAL
5962 add_to_linker((int)out,ba[i],internal);
5970 if((opcode2[i]&0xf)==0) // BLTZ/BLTZAL
5977 add_to_linker((int)out,ba[i],internal);
5981 if((opcode2[i]&0xf)==1) // BGEZ/BLTZAL
5988 add_to_linker((int)out,ba[i],internal);
5995 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5996 if(match&&(!internal||!is_ds[(ba[i]-start)>>2])) {
5998 emit_addimm(cc,-CLOCK_DIVIDER*adj,cc);
5999 add_to_linker((int)out,ba[i],internal);
6002 add_to_linker((int)out,ba[i],internal*2);
6008 if(adj) emit_addimm(cc,-CLOCK_DIVIDER*adj,cc);
6009 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6010 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6012 assem_debug("branch: internal\n");
6014 assem_debug("branch: external\n");
6015 if(internal&&is_ds[(ba[i]-start)>>2]) {
6016 ds_assemble_entry(i);
6019 add_to_linker((int)out,ba[i],internal);
6023 set_jump_target(nottaken,(int)out);
6027 if(!invert) emit_addimm(cc,CLOCK_DIVIDER*adj,cc);
6029 } // (!unconditional)
6033 // In-order execution (branch first)
6037 int rt,return_address;
6038 rt=get_reg(branch_regs[i].regmap,31);
6040 // Save the PC even if the branch is not taken
6041 return_address=start+i*4+8;
6042 emit_movimm(return_address,rt); // PC into link register
6044 emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
6048 if(!unconditional) {
6049 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
6053 if((opcode2[i]&0x0d)==0) // BLTZ/BLTZL/BLTZAL/BLTZALL
6059 if((opcode2[i]&0x0d)==1) // BGEZ/BGEZL/BGEZAL/BGEZALL
6069 if((opcode2[i]&0x0d)==0) // BLTZ/BLTZL/BLTZAL/BLTZALL
6075 if((opcode2[i]&0x0d)==1) // BGEZ/BGEZL/BGEZAL/BGEZALL
6082 } // if(!unconditional)
6084 uint64_t ds_unneeded=branch_regs[i].u;
6085 uint64_t ds_unneeded_upper=branch_regs[i].uu;
6086 ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6087 ds_unneeded_upper&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6088 if((~ds_unneeded_upper>>rt1[i+1])&1) ds_unneeded_upper&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
6090 ds_unneeded_upper|=1;
6093 //assem_debug("1:\n");
6094 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6095 ds_unneeded,ds_unneeded_upper);
6097 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
6098 address_generation(i+1,&branch_regs[i],0);
6099 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,INVCP);
6100 ds_assemble(i+1,&branch_regs[i]);
6101 cc=get_reg(branch_regs[i].regmap,CCREG);
6103 emit_loadreg(CCREG,cc=HOST_CCREG);
6104 // CHECK: Is the following instruction (fall thru) allocated ok?
6106 assert(cc==HOST_CCREG);
6107 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6108 do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
6109 assem_debug("cycle count (adj)\n");
6110 if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
6111 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6113 assem_debug("branch: internal\n");
6115 assem_debug("branch: external\n");
6116 if(internal&&is_ds[(ba[i]-start)>>2]) {
6117 ds_assemble_entry(i);
6120 add_to_linker((int)out,ba[i],internal);
6125 cop1_usable=prev_cop1_usable;
6126 if(!unconditional) {
6127 set_jump_target(nottaken,(int)out);
6128 assem_debug("1:\n");
6130 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6131 ds_unneeded,ds_unneeded_upper);
6132 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
6133 address_generation(i+1,&branch_regs[i],0);
6134 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
6135 ds_assemble(i+1,&branch_regs[i]);
6137 cc=get_reg(branch_regs[i].regmap,CCREG);
6138 if(cc==-1&&!likely[i]) {
6139 // Cycle count isn't in a register, temporarily load it then write it out
6140 emit_loadreg(CCREG,HOST_CCREG);
6141 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG);
6144 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
6145 emit_storereg(CCREG,HOST_CCREG);
6148 cc=get_reg(i_regmap,CCREG);
6149 assert(cc==HOST_CCREG);
6150 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc);
6153 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
6159 void fjump_assemble(int i,struct regstat *i_regs)
6161 signed char *i_regmap=i_regs->regmap;
6164 match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6165 assem_debug("fmatch=%d\n",match);
6169 int internal=internal_branch(branch_regs[i].is32,ba[i]);
6170 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
6171 if(!match) invert=1;
6172 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
6173 if(i>(ba[i]-start)>>2) invert=1;
6177 fs=get_reg(branch_regs[i].regmap,FSREG);
6178 address_generation(i+1,i_regs,regs[i].regmap_entry); // Is this okay?
6181 fs=get_reg(i_regmap,FSREG);
6184 // Check cop1 unusable
6186 cs=get_reg(i_regmap,CSREG);
6188 emit_testimm(cs,0x20000000);
6191 add_stub(FP_STUB,eaddr,(int)out,i,cs,(int)i_regs,0,0);
6196 // Out of order execution (delay slot first)
6198 ds_assemble(i+1,i_regs);
6200 uint64_t bc_unneeded=branch_regs[i].u;
6201 uint64_t bc_unneeded_upper=branch_regs[i].uu;
6202 bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
6203 bc_unneeded_upper&=~((1LL<<us1[i])|(1LL<<us2[i]));
6205 bc_unneeded_upper|=1;
6206 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6207 bc_unneeded,bc_unneeded_upper);
6208 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],rs1[i]);
6209 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
6210 cc=get_reg(branch_regs[i].regmap,CCREG);
6211 assert(cc==HOST_CCREG);
6212 do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
6213 assem_debug("cycle count (adj)\n");
6216 if(adj&&!invert) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
6219 emit_testimm(fs,0x800000);
6220 if(source[i]&0x10000) // BC1T
6226 add_to_linker((int)out,ba[i],internal);
6235 add_to_linker((int)out,ba[i],internal);
6243 if(adj) emit_addimm(cc,-CLOCK_DIVIDER*adj,cc);
6244 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
6245 else if(match) emit_addnop(13);
6247 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6248 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6250 assem_debug("branch: internal\n");
6252 assem_debug("branch: external\n");
6253 if(internal&&is_ds[(ba[i]-start)>>2]) {
6254 ds_assemble_entry(i);
6257 add_to_linker((int)out,ba[i],internal);
6260 set_jump_target(nottaken,(int)out);
6264 if(!invert) emit_addimm(cc,CLOCK_DIVIDER*adj,cc);
6266 } // (!unconditional)
6270 // In-order execution (branch first)
6274 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
6277 emit_testimm(fs,0x800000);
6278 if(source[i]&0x10000) // BC1T
6289 } // if(!unconditional)
6291 uint64_t ds_unneeded=branch_regs[i].u;
6292 uint64_t ds_unneeded_upper=branch_regs[i].uu;
6293 ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6294 ds_unneeded_upper&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6295 if((~ds_unneeded_upper>>rt1[i+1])&1) ds_unneeded_upper&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
6297 ds_unneeded_upper|=1;
6299 //assem_debug("1:\n");
6300 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6301 ds_unneeded,ds_unneeded_upper);
6303 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
6304 address_generation(i+1,&branch_regs[i],0);
6305 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,INVCP);
6306 ds_assemble(i+1,&branch_regs[i]);
6307 cc=get_reg(branch_regs[i].regmap,CCREG);
6309 emit_loadreg(CCREG,cc=HOST_CCREG);
6310 // CHECK: Is the following instruction (fall thru) allocated ok?
6312 assert(cc==HOST_CCREG);
6313 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6314 do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
6315 assem_debug("cycle count (adj)\n");
6316 if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
6317 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6319 assem_debug("branch: internal\n");
6321 assem_debug("branch: external\n");
6322 if(internal&&is_ds[(ba[i]-start)>>2]) {
6323 ds_assemble_entry(i);
6326 add_to_linker((int)out,ba[i],internal);
6331 if(1) { // <- FIXME (don't need this)
6332 set_jump_target(nottaken,(int)out);
6333 assem_debug("1:\n");
6335 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6336 ds_unneeded,ds_unneeded_upper);
6337 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
6338 address_generation(i+1,&branch_regs[i],0);
6339 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
6340 ds_assemble(i+1,&branch_regs[i]);
6342 cc=get_reg(branch_regs[i].regmap,CCREG);
6343 if(cc==-1&&!likely[i]) {
6344 // Cycle count isn't in a register, temporarily load it then write it out
6345 emit_loadreg(CCREG,HOST_CCREG);
6346 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG);
6349 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
6350 emit_storereg(CCREG,HOST_CCREG);
6353 cc=get_reg(i_regmap,CCREG);
6354 assert(cc==HOST_CCREG);
6355 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc);
6358 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
6364 static void pagespan_assemble(int i,struct regstat *i_regs)
6366 int s1l=get_reg(i_regs->regmap,rs1[i]);
6367 int s1h=get_reg(i_regs->regmap,rs1[i]|64);
6368 int s2l=get_reg(i_regs->regmap,rs2[i]);
6369 int s2h=get_reg(i_regs->regmap,rs2[i]|64);
6370 void *nt_branch=NULL;
6373 int unconditional=0;
6383 if((i_regs->is32>>rs1[i])&(i_regs->is32>>rs2[i])&1) {
6387 int addr,alt,ntaddr;
6388 if(i_regs->regmap[HOST_BTREG]<0) {addr=HOST_BTREG;}
6392 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
6393 (i_regs->regmap[hr]&63)!=rs1[i] &&
6394 (i_regs->regmap[hr]&63)!=rs2[i] )
6403 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG && hr!=HOST_BTREG &&
6404 (i_regs->regmap[hr]&63)!=rs1[i] &&
6405 (i_regs->regmap[hr]&63)!=rs2[i] )
6411 if((opcode[i]&0x2E)==6) // BLEZ/BGTZ needs another register
6415 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG && hr!=HOST_BTREG &&
6416 (i_regs->regmap[hr]&63)!=rs1[i] &&
6417 (i_regs->regmap[hr]&63)!=rs2[i] )
6424 assert(hr<HOST_REGS);
6425 if((opcode[i]&0x2e)==4||opcode[i]==0x11) { // BEQ/BNE/BEQL/BNEL/BC1
6426 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,CCREG,CCREG);
6428 emit_addimm(HOST_CCREG,CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG);
6429 if(opcode[i]==2) // J
6433 if(opcode[i]==3) // JAL
6436 int rt=get_reg(i_regs->regmap,31);
6437 emit_movimm(start+i*4+8,rt);
6440 if(opcode[i]==0&&(opcode2[i]&0x3E)==8) // JR/JALR
6443 if(opcode2[i]==9) // JALR
6445 int rt=get_reg(i_regs->regmap,rt1[i]);
6446 emit_movimm(start+i*4+8,rt);
6449 if((opcode[i]&0x3f)==4) // BEQ
6456 #ifdef HAVE_CMOV_IMM
6458 if(s2l>=0) emit_cmp(s1l,s2l);
6459 else emit_test(s1l,s1l);
6460 emit_cmov2imm_e_ne_compact(ba[i],start+i*4+8,addr);
6466 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
6468 if(s2h>=0) emit_cmp(s1h,s2h);
6469 else emit_test(s1h,s1h);
6470 emit_cmovne_reg(alt,addr);
6472 if(s2l>=0) emit_cmp(s1l,s2l);
6473 else emit_test(s1l,s1l);
6474 emit_cmovne_reg(alt,addr);
6477 if((opcode[i]&0x3f)==5) // BNE
6479 #ifdef HAVE_CMOV_IMM
6481 if(s2l>=0) emit_cmp(s1l,s2l);
6482 else emit_test(s1l,s1l);
6483 emit_cmov2imm_e_ne_compact(start+i*4+8,ba[i],addr);
6489 emit_mov2imm_compact(start+i*4+8,addr,ba[i],alt);
6491 if(s2h>=0) emit_cmp(s1h,s2h);
6492 else emit_test(s1h,s1h);
6493 emit_cmovne_reg(alt,addr);
6495 if(s2l>=0) emit_cmp(s1l,s2l);
6496 else emit_test(s1l,s1l);
6497 emit_cmovne_reg(alt,addr);
6500 if((opcode[i]&0x3f)==0x14) // BEQL
6503 if(s2h>=0) emit_cmp(s1h,s2h);
6504 else emit_test(s1h,s1h);
6508 if(s2l>=0) emit_cmp(s1l,s2l);
6509 else emit_test(s1l,s1l);
6510 if(nottaken) set_jump_target(nottaken,(int)out);
6514 if((opcode[i]&0x3f)==0x15) // BNEL
6517 if(s2h>=0) emit_cmp(s1h,s2h);
6518 else emit_test(s1h,s1h);
6522 if(s2l>=0) emit_cmp(s1l,s2l);
6523 else emit_test(s1l,s1l);
6526 if(taken) set_jump_target(taken,(int)out);
6528 if((opcode[i]&0x3f)==6) // BLEZ
6530 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
6532 if(s1h>=0) emit_mov(addr,ntaddr);
6533 emit_cmovl_reg(alt,addr);
6536 emit_cmovne_reg(ntaddr,addr);
6537 emit_cmovs_reg(alt,addr);
6540 if((opcode[i]&0x3f)==7) // BGTZ
6542 emit_mov2imm_compact(ba[i],addr,start+i*4+8,ntaddr);
6544 if(s1h>=0) emit_mov(addr,alt);
6545 emit_cmovl_reg(ntaddr,addr);
6548 emit_cmovne_reg(alt,addr);
6549 emit_cmovs_reg(ntaddr,addr);
6552 if((opcode[i]&0x3f)==0x16) // BLEZL
6554 assert((opcode[i]&0x3f)!=0x16);
6556 if((opcode[i]&0x3f)==0x17) // BGTZL
6558 assert((opcode[i]&0x3f)!=0x17);
6560 assert(opcode[i]!=1); // BLTZ/BGEZ
6562 //FIXME: Check CSREG
6563 if(opcode[i]==0x11 && opcode2[i]==0x08 ) {
6564 if((source[i]&0x30000)==0) // BC1F
6566 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
6567 emit_testimm(s1l,0x800000);
6568 emit_cmovne_reg(alt,addr);
6570 if((source[i]&0x30000)==0x10000) // BC1T
6572 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
6573 emit_testimm(s1l,0x800000);
6574 emit_cmovne_reg(alt,addr);
6576 if((source[i]&0x30000)==0x20000) // BC1FL
6578 emit_testimm(s1l,0x800000);
6582 if((source[i]&0x30000)==0x30000) // BC1TL
6584 emit_testimm(s1l,0x800000);
6590 assert(i_regs->regmap[HOST_CCREG]==CCREG);
6591 wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty);
6592 if(likely[i]||unconditional)
6594 emit_movimm(ba[i],HOST_BTREG);
6596 else if(addr!=HOST_BTREG)
6598 emit_mov(addr,HOST_BTREG);
6600 void *branch_addr=out;
6602 int target_addr=start+i*4+5;
6604 void *compiled_target_addr=check_addr(target_addr);
6605 emit_extjump_ds((int)branch_addr,target_addr);
6606 if(compiled_target_addr) {
6607 set_jump_target((int)branch_addr,(int)compiled_target_addr);
6608 add_link(target_addr,stub);
6610 else set_jump_target((int)branch_addr,(int)stub);
6613 set_jump_target((int)nottaken,(int)out);
6614 wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty);
6615 void *branch_addr=out;
6617 int target_addr=start+i*4+8;
6619 void *compiled_target_addr=check_addr(target_addr);
6620 emit_extjump_ds((int)branch_addr,target_addr);
6621 if(compiled_target_addr) {
6622 set_jump_target((int)branch_addr,(int)compiled_target_addr);
6623 add_link(target_addr,stub);
6625 else set_jump_target((int)branch_addr,(int)stub);
6629 // Assemble the delay slot for the above
6630 static void pagespan_ds()
6632 assem_debug("initial delay slot:\n");
6633 u_int vaddr=start+1;
6634 u_int page=get_page(vaddr);
6635 u_int vpage=get_vpage(vaddr);
6636 ll_add(jump_dirty+vpage,vaddr,(void *)out);
6638 ll_add(jump_in+page,vaddr,(void *)out);
6639 assert(regs[0].regmap_entry[HOST_CCREG]==CCREG);
6640 if(regs[0].regmap[HOST_CCREG]!=CCREG)
6641 wb_register(CCREG,regs[0].regmap_entry,regs[0].wasdirty,regs[0].was32);
6642 if(regs[0].regmap[HOST_BTREG]!=BTREG)
6643 emit_writeword(HOST_BTREG,(int)&branch_target);
6644 load_regs(regs[0].regmap_entry,regs[0].regmap,regs[0].was32,rs1[0],rs2[0]);
6645 address_generation(0,®s[0],regs[0].regmap_entry);
6646 if(itype[0]==STORE||itype[0]==STORELR||(opcode[0]&0x3b)==0x39||(opcode[0]&0x3b)==0x3a)
6647 load_regs(regs[0].regmap_entry,regs[0].regmap,regs[0].was32,INVCP,INVCP);
6652 alu_assemble(0,®s[0]);break;
6654 imm16_assemble(0,®s[0]);break;
6656 shift_assemble(0,®s[0]);break;
6658 shiftimm_assemble(0,®s[0]);break;
6660 load_assemble(0,®s[0]);break;
6662 loadlr_assemble(0,®s[0]);break;
6664 store_assemble(0,®s[0]);break;
6666 storelr_assemble(0,®s[0]);break;
6668 cop0_assemble(0,®s[0]);break;
6670 cop1_assemble(0,®s[0]);break;
6672 c1ls_assemble(0,®s[0]);break;
6674 cop2_assemble(0,®s[0]);break;
6676 c2ls_assemble(0,®s[0]);break;
6678 c2op_assemble(0,®s[0]);break;
6680 fconv_assemble(0,®s[0]);break;
6682 float_assemble(0,®s[0]);break;
6684 fcomp_assemble(0,®s[0]);break;
6686 multdiv_assemble(0,®s[0]);break;
6688 mov_assemble(0,®s[0]);break;
6698 printf("Jump in the delay slot. This is probably a bug.\n");
6700 int btaddr=get_reg(regs[0].regmap,BTREG);
6702 btaddr=get_reg(regs[0].regmap,-1);
6703 emit_readword((int)&branch_target,btaddr);
6705 assert(btaddr!=HOST_CCREG);
6706 if(regs[0].regmap[HOST_CCREG]!=CCREG) emit_loadreg(CCREG,HOST_CCREG);
6708 emit_movimm(start+4,HOST_TEMPREG);
6709 emit_cmp(btaddr,HOST_TEMPREG);
6711 emit_cmpimm(btaddr,start+4);
6713 int branch=(int)out;
6715 store_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,-1);
6716 emit_jmp(jump_vaddr_reg[btaddr]);
6717 set_jump_target(branch,(int)out);
6718 store_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,start+4);
6719 load_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,start+4);
6722 // Basic liveness analysis for MIPS registers
6723 void unneeded_registers(int istart,int iend,int r)
6726 uint64_t u,uu,gte_u,b,bu,gte_bu;
6727 uint64_t temp_u,temp_uu,temp_gte_u;
6732 u=unneeded_reg[iend+1];
6733 uu=unneeded_reg_upper[iend+1];
6738 for (i=iend;i>=istart;i--)
6740 //printf("unneeded registers i=%d (%d,%d) r=%d\n",i,istart,iend,r);
6741 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
6743 // If subroutine call, flag return address as a possible branch target
6744 if(rt1[i]==31 && i<slen-2) bt[i+2]=1;
6746 if(ba[i]<start || ba[i]>=(start+slen*4))
6748 // Branch out of this block, flush all regs
6753 if(itype[i]==UJUMP&&rt1[i]==31)
6755 uu=u=0x300C00F; // Discard at, v0-v1, t6-t9
6757 if(itype[i]==RJUMP&&rs1[i]==31)
6759 uu=u=0x300C0F3; // Discard at, a0-a3, t6-t9
6761 if(start>0x80000400&&start<0x80000000+RAM_SIZE) {
6762 if(itype[i]==UJUMP&&rt1[i]==31)
6764 //uu=u=0x30300FF0FLL; // Discard at, v0-v1, t0-t9, lo, hi
6765 uu=u=0x300FF0F; // Discard at, v0-v1, t0-t9
6767 if(itype[i]==RJUMP&&rs1[i]==31)
6769 //uu=u=0x30300FFF3LL; // Discard at, a0-a3, t0-t9, lo, hi
6770 uu=u=0x300FFF3; // Discard at, a0-a3, t0-t9
6773 branch_unneeded_reg[i]=u;
6774 branch_unneeded_reg_upper[i]=uu;
6775 // Merge in delay slot
6776 tdep=(~uu>>rt1[i+1])&1;
6777 u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6778 uu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6779 u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6780 uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6781 uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6784 gte_u&=~gte_rs[i+1];
6785 // If branch is "likely" (and conditional)
6786 // then we skip the delay slot on the fall-thru path
6789 u&=unneeded_reg[i+2];
6790 uu&=unneeded_reg_upper[i+2];
6791 gte_u&=gte_unneeded[i+2];
6803 // Internal branch, flag target
6804 bt[(ba[i]-start)>>2]=1;
6805 if(ba[i]<=start+i*4) {
6807 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
6809 // Unconditional branch
6813 // Conditional branch (not taken case)
6814 temp_u=unneeded_reg[i+2];
6815 temp_uu=unneeded_reg_upper[i+2];
6816 temp_gte_u&=gte_unneeded[i+2];
6818 // Merge in delay slot
6819 tdep=(~temp_uu>>rt1[i+1])&1;
6820 temp_u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6821 temp_uu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6822 temp_u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6823 temp_uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6824 temp_uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6825 temp_u|=1;temp_uu|=1;
6826 temp_gte_u|=gte_rt[i+1];
6827 temp_gte_u&=~gte_rs[i+1];
6828 // If branch is "likely" (and conditional)
6829 // then we skip the delay slot on the fall-thru path
6832 temp_u&=unneeded_reg[i+2];
6833 temp_uu&=unneeded_reg_upper[i+2];
6834 temp_gte_u&=gte_unneeded[i+2];
6843 tdep=(~temp_uu>>rt1[i])&1;
6844 temp_u|=(1LL<<rt1[i])|(1LL<<rt2[i]);
6845 temp_uu|=(1LL<<rt1[i])|(1LL<<rt2[i]);
6846 temp_u&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
6847 temp_uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
6848 temp_uu&=~((tdep<<dep1[i])|(tdep<<dep2[i]));
6849 temp_u|=1;temp_uu|=1;
6850 temp_gte_u|=gte_rt[i];
6851 temp_gte_u&=~gte_rs[i];
6852 unneeded_reg[i]=temp_u;
6853 unneeded_reg_upper[i]=temp_uu;
6854 gte_unneeded[i]=temp_gte_u;
6855 // Only go three levels deep. This recursion can take an
6856 // excessive amount of time if there are a lot of nested loops.
6858 unneeded_registers((ba[i]-start)>>2,i-1,r+1);
6860 unneeded_reg[(ba[i]-start)>>2]=1;
6861 unneeded_reg_upper[(ba[i]-start)>>2]=1;
6862 gte_unneeded[(ba[i]-start)>>2]=0;
6865 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
6867 // Unconditional branch
6868 u=unneeded_reg[(ba[i]-start)>>2];
6869 uu=unneeded_reg_upper[(ba[i]-start)>>2];
6870 gte_u=gte_unneeded[(ba[i]-start)>>2];
6871 branch_unneeded_reg[i]=u;
6872 branch_unneeded_reg_upper[i]=uu;
6875 //branch_unneeded_reg[i]=u;
6876 //branch_unneeded_reg_upper[i]=uu;
6877 // Merge in delay slot
6878 tdep=(~uu>>rt1[i+1])&1;
6879 u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6880 uu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6881 u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6882 uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6883 uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6886 gte_u&=~gte_rs[i+1];
6888 // Conditional branch
6889 b=unneeded_reg[(ba[i]-start)>>2];
6890 bu=unneeded_reg_upper[(ba[i]-start)>>2];
6891 gte_bu=gte_unneeded[(ba[i]-start)>>2];
6892 branch_unneeded_reg[i]=b;
6893 branch_unneeded_reg_upper[i]=bu;
6896 //branch_unneeded_reg[i]=b;
6897 //branch_unneeded_reg_upper[i]=bu;
6898 // Branch delay slot
6899 tdep=(~uu>>rt1[i+1])&1;
6900 b|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6901 bu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6902 b&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6903 bu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6904 bu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6906 gte_bu|=gte_rt[i+1];
6907 gte_bu&=~gte_rs[i+1];
6908 // If branch is "likely" then we skip the
6909 // delay slot on the fall-thru path
6915 u&=unneeded_reg[i+2];
6916 uu&=unneeded_reg_upper[i+2];
6917 gte_u&=gte_unneeded[i+2];
6929 branch_unneeded_reg[i]&=unneeded_reg[i+2];
6930 branch_unneeded_reg_upper[i]&=unneeded_reg_upper[i+2];
6931 //branch_unneeded_reg[i]=1;
6932 //branch_unneeded_reg_upper[i]=1;
6934 branch_unneeded_reg[i]=1;
6935 branch_unneeded_reg_upper[i]=1;
6941 else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
6943 // SYSCALL instruction (software interrupt)
6947 else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
6949 // ERET instruction (return from interrupt)
6954 tdep=(~uu>>rt1[i])&1;
6955 // Written registers are unneeded
6961 // Accessed registers are needed
6967 // Source-target dependencies
6968 uu&=~(tdep<<dep1[i]);
6969 uu&=~(tdep<<dep2[i]);
6970 // R0 is always unneeded
6974 unneeded_reg_upper[i]=uu;
6975 gte_unneeded[i]=gte_u;
6977 printf("ur (%d,%d) %x: ",istart,iend,start+i*4);
6980 for(r=1;r<=CCREG;r++) {
6981 if((unneeded_reg[i]>>r)&1) {
6982 if(r==HIREG) printf(" HI");
6983 else if(r==LOREG) printf(" LO");
6984 else printf(" r%d",r);
6988 for(r=1;r<=CCREG;r++) {
6989 if(((unneeded_reg_upper[i]&~unneeded_reg[i])>>r)&1) {
6990 if(r==HIREG) printf(" HI");
6991 else if(r==LOREG) printf(" LO");
6992 else printf(" r%d",r);
6998 for (i=iend;i>=istart;i--)
7000 unneeded_reg_upper[i]=branch_unneeded_reg_upper[i]=-1LL;
7005 // Identify registers which are likely to contain 32-bit values
7006 // This is used to predict whether any branches will jump to a
7007 // location with 64-bit values in registers.
7008 static void provisional_32bit()
7012 uint64_t lastbranch=1;
7017 if(itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP) {
7018 if(i>1) is32=lastbranch;
7024 if(itype[i-2]==CJUMP||itype[i-2]==SJUMP||itype[i-2]==FJUMP) {
7026 if(i>2) is32=lastbranch;
7030 if((opcode[i-2]&0x2f)==0x05) // BNE/BNEL
7032 if(rs1[i-2]==0||rs2[i-2]==0)
7035 is32|=1LL<<rs1[i-2];
7038 is32|=1LL<<rs2[i-2];
7043 // If something jumps here with 64-bit values
7044 // then promote those registers to 64 bits
7047 uint64_t temp_is32=is32;
7050 if(ba[j]==start+i*4)
7051 //temp_is32&=branch_regs[j].is32;
7056 if(ba[j]==start+i*4)
7067 if(type==UJUMP||type==RJUMP||type==CJUMP||type==SJUMP||type==FJUMP) {
7068 // Branches don't write registers, consider the delay slot instead.
7079 if(opcode[i]==0x27||opcode[i]==0x37|| // LWU/LD
7080 opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
7089 if(op==0x1a||op==0x1b) is32&=~(1LL<<rt); // LDR/LDL
7090 if(op==0x22) is32|=1LL<<rt; // LWL
7093 if (op==0x08||op==0x09|| // ADDI/ADDIU
7094 op==0x0a||op==0x0b|| // SLTI/SLTIU
7100 if(op==0x18||op==0x19) { // DADDI/DADDIU
7103 // is32|=((is32>>s1)&1LL)<<rt;
7105 if(op==0x0d||op==0x0e) { // ORI/XORI
7106 uint64_t sr=((is32>>s1)&1LL);
7122 if(op2>=0x20&&op2<=0x23) { // ADD/ADDU/SUB/SUBU
7125 if(op2==0x2a||op2==0x2b) { // SLT/SLTU
7128 else if(op2>=0x24&&op2<=0x27) { // AND/OR/XOR/NOR
7129 uint64_t sr=((is32>>s1)&(is32>>s2)&1LL);
7133 else if(op2>=0x2c&&op2<=0x2d) { // DADD/DADDU
7138 uint64_t sr=((is32>>s1)&1LL);
7143 uint64_t sr=((is32>>s2)&1LL);
7151 else if(op2>=0x2e&&op2<=0x2f) { // DSUB/DSUBU
7156 uint64_t sr=((is32>>s1)&1LL);
7166 if (op2>=0x1c&&op2<=0x1f) { // DMULT/DMULTU/DDIV/DDIVU
7167 is32&=~((1LL<<HIREG)|(1LL<<LOREG));
7170 is32|=(1LL<<HIREG)|(1LL<<LOREG);
7175 uint64_t sr=((is32>>s1)&1LL);
7181 if(op2>=0x14&&op2<=0x17) is32&=~(1LL<<rt); // DSLLV/DSRLV/DSRAV
7182 else is32|=1LL<<rt; // SLLV/SRLV/SRAV
7186 // DSLL/DSRL/DSRA/DSLL32/DSRL32 but not DSRA32 have 64-bit result
7187 if(op2>=0x38&&op2<0x3f) is32&=~(1LL<<rt);
7190 if(op2==0) is32|=1LL<<rt; // MFC0
7194 if(op2==0) is32|=1LL<<rt; // MFC1
7195 if(op2==1) is32&=~(1LL<<rt); // DMFC1
7196 if(op2==2) is32|=1LL<<rt; // CFC1
7218 if(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)
7220 if(rt1[i-1]==31) // JAL/JALR
7222 // Subroutine call will return here, don't alloc any registers
7227 // Internal branch will jump here, match registers to caller
7235 // Identify registers which may be assumed to contain 32-bit values
7236 // and where optimizations will rely on this.
7237 // This is used to determine whether backward branches can safely
7238 // jump to a location with 64-bit values in registers.
7239 static void provisional_r32()
7244 for (i=slen-1;i>=0;i--)
7247 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
7249 if(ba[i]<start || ba[i]>=(start+slen*4))
7251 // Branch out of this block, don't need anything
7257 // Need whatever matches the target
7258 // (and doesn't get overwritten by the delay slot instruction)
7260 int t=(ba[i]-start)>>2;
7261 if(ba[i]>start+i*4) {
7263 //if(!(requires_32bit[t]&~regs[i].was32))
7264 // r32|=requires_32bit[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
7265 if(!(pr32[t]&~regs[i].was32))
7266 r32|=pr32[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
7269 if(!(regs[t].was32&~unneeded_reg_upper[t]&~regs[i].was32))
7270 r32|=regs[t].was32&~unneeded_reg_upper[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
7273 // Conditional branch may need registers for following instructions
7274 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
7277 //r32|=requires_32bit[i+2];
7280 // Mark this address as a branch target since it may be called
7281 // upon return from interrupt
7285 // Merge in delay slot
7287 // These are overwritten unless the branch is "likely"
7288 // and the delay slot is nullified if not taken
7289 r32&=~(1LL<<rt1[i+1]);
7290 r32&=~(1LL<<rt2[i+1]);
7292 // Assume these are needed (delay slot)
7295 if((regs[i].was32>>us1[i+1])&1) r32|=1LL<<us1[i+1];
7299 if((regs[i].was32>>us2[i+1])&1) r32|=1LL<<us2[i+1];
7301 if(dep1[i+1]&&!((unneeded_reg_upper[i]>>dep1[i+1])&1))
7303 if((regs[i].was32>>dep1[i+1])&1) r32|=1LL<<dep1[i+1];
7305 if(dep2[i+1]&&!((unneeded_reg_upper[i]>>dep2[i+1])&1))
7307 if((regs[i].was32>>dep2[i+1])&1) r32|=1LL<<dep2[i+1];
7310 else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
7312 // SYSCALL instruction (software interrupt)
7315 else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
7317 // ERET instruction (return from interrupt)
7321 r32&=~(1LL<<rt1[i]);
7322 r32&=~(1LL<<rt2[i]);
7325 if((regs[i].was32>>us1[i])&1) r32|=1LL<<us1[i];
7329 if((regs[i].was32>>us2[i])&1) r32|=1LL<<us2[i];
7331 if(dep1[i]&&!((unneeded_reg_upper[i]>>dep1[i])&1))
7333 if((regs[i].was32>>dep1[i])&1) r32|=1LL<<dep1[i];
7335 if(dep2[i]&&!((unneeded_reg_upper[i]>>dep2[i])&1))
7337 if((regs[i].was32>>dep2[i])&1) r32|=1LL<<dep2[i];
7339 //requires_32bit[i]=r32;
7342 // Dirty registers which are 32-bit, require 32-bit input
7343 // as they will be written as 32-bit values
7344 for(hr=0;hr<HOST_REGS;hr++)
7346 if(regs[i].regmap_entry[hr]>0&®s[i].regmap_entry[hr]<64) {
7347 if((regs[i].was32>>regs[i].regmap_entry[hr])&(regs[i].wasdirty>>hr)&1) {
7348 if(!((unneeded_reg_upper[i]>>regs[i].regmap_entry[hr])&1))
7349 pr32[i]|=1LL<<regs[i].regmap_entry[hr];
7350 //requires_32bit[i]|=1LL<<regs[i].regmap_entry[hr];
7357 // Write back dirty registers as soon as we will no longer modify them,
7358 // so that we don't end up with lots of writes at the branches.
7359 void clean_registers(int istart,int iend,int wr)
7363 u_int will_dirty_i,will_dirty_next,temp_will_dirty;
7364 u_int wont_dirty_i,wont_dirty_next,temp_wont_dirty;
7366 will_dirty_i=will_dirty_next=0;
7367 wont_dirty_i=wont_dirty_next=0;
7369 will_dirty_i=will_dirty_next=will_dirty[iend+1];
7370 wont_dirty_i=wont_dirty_next=wont_dirty[iend+1];
7372 for (i=iend;i>=istart;i--)
7374 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
7376 if(ba[i]<start || ba[i]>=(start+slen*4))
7378 // Branch out of this block, flush all regs
7379 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
7381 // Unconditional branch
7384 // Merge in delay slot (will dirty)
7385 for(r=0;r<HOST_REGS;r++) {
7386 if(r!=EXCLUDE_REG) {
7387 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7388 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7389 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7390 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7391 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7392 if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7393 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7394 if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7395 if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7396 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7397 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7398 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7399 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7400 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7406 // Conditional branch
7408 wont_dirty_i=wont_dirty_next;
7409 // Merge in delay slot (will dirty)
7410 for(r=0;r<HOST_REGS;r++) {
7411 if(r!=EXCLUDE_REG) {
7413 // Might not dirty if likely branch is not taken
7414 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7415 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7416 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7417 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7418 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7419 if(branch_regs[i].regmap[r]==0) will_dirty_i&=~(1<<r);
7420 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7421 //if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7422 //if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7423 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7424 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7425 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7426 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7427 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7432 // Merge in delay slot (wont dirty)
7433 for(r=0;r<HOST_REGS;r++) {
7434 if(r!=EXCLUDE_REG) {
7435 if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7436 if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7437 if((regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7438 if((regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7439 if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7440 if((branch_regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7441 if((branch_regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7442 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7443 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7444 if(branch_regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7448 #ifndef DESTRUCTIVE_WRITEBACK
7449 branch_regs[i].dirty&=wont_dirty_i;
7451 branch_regs[i].dirty|=will_dirty_i;
7457 if(ba[i]<=start+i*4) {
7459 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
7461 // Unconditional branch
7464 // Merge in delay slot (will dirty)
7465 for(r=0;r<HOST_REGS;r++) {
7466 if(r!=EXCLUDE_REG) {
7467 if((branch_regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7468 if((branch_regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7469 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7470 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7471 if((branch_regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7472 if(branch_regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
7473 if(branch_regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7474 if((regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7475 if((regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7476 if((regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7477 if((regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7478 if((regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7479 if(regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
7480 if(regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7484 // Conditional branch (not taken case)
7485 temp_will_dirty=will_dirty_next;
7486 temp_wont_dirty=wont_dirty_next;
7487 // Merge in delay slot (will dirty)
7488 for(r=0;r<HOST_REGS;r++) {
7489 if(r!=EXCLUDE_REG) {
7491 // Will not dirty if likely branch is not taken
7492 if((branch_regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7493 if((branch_regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7494 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7495 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7496 if((branch_regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7497 if(branch_regs[i].regmap[r]==0) temp_will_dirty&=~(1<<r);
7498 if(branch_regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7499 //if((regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7500 //if((regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7501 if((regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7502 if((regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7503 if((regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7504 if(regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
7505 if(regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7510 // Merge in delay slot (wont dirty)
7511 for(r=0;r<HOST_REGS;r++) {
7512 if(r!=EXCLUDE_REG) {
7513 if((regs[i].regmap[r]&63)==rt1[i]) temp_wont_dirty|=1<<r;
7514 if((regs[i].regmap[r]&63)==rt2[i]) temp_wont_dirty|=1<<r;
7515 if((regs[i].regmap[r]&63)==rt1[i+1]) temp_wont_dirty|=1<<r;
7516 if((regs[i].regmap[r]&63)==rt2[i+1]) temp_wont_dirty|=1<<r;
7517 if(regs[i].regmap[r]==CCREG) temp_wont_dirty|=1<<r;
7518 if((branch_regs[i].regmap[r]&63)==rt1[i]) temp_wont_dirty|=1<<r;
7519 if((branch_regs[i].regmap[r]&63)==rt2[i]) temp_wont_dirty|=1<<r;
7520 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) temp_wont_dirty|=1<<r;
7521 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) temp_wont_dirty|=1<<r;
7522 if(branch_regs[i].regmap[r]==CCREG) temp_wont_dirty|=1<<r;
7525 // Deal with changed mappings
7527 for(r=0;r<HOST_REGS;r++) {
7528 if(r!=EXCLUDE_REG) {
7529 if(regs[i].regmap[r]!=regmap_pre[i][r]) {
7530 temp_will_dirty&=~(1<<r);
7531 temp_wont_dirty&=~(1<<r);
7532 if((regmap_pre[i][r]&63)>0 && (regmap_pre[i][r]&63)<34) {
7533 temp_will_dirty|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7534 temp_wont_dirty|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7536 temp_will_dirty|=1<<r;
7537 temp_wont_dirty|=1<<r;
7544 will_dirty[i]=temp_will_dirty;
7545 wont_dirty[i]=temp_wont_dirty;
7546 clean_registers((ba[i]-start)>>2,i-1,0);
7548 // Limit recursion. It can take an excessive amount
7549 // of time if there are a lot of nested loops.
7550 will_dirty[(ba[i]-start)>>2]=0;
7551 wont_dirty[(ba[i]-start)>>2]=-1;
7556 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
7558 // Unconditional branch
7561 //if(ba[i]>start+i*4) { // Disable recursion (for debugging)
7562 for(r=0;r<HOST_REGS;r++) {
7563 if(r!=EXCLUDE_REG) {
7564 if(branch_regs[i].regmap[r]==regs[(ba[i]-start)>>2].regmap_entry[r]) {
7565 will_dirty_i|=will_dirty[(ba[i]-start)>>2]&(1<<r);
7566 wont_dirty_i|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
7568 if(branch_regs[i].regmap[r]>=0) {
7569 will_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>(branch_regs[i].regmap[r]&63))&1)<<r;
7570 wont_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>(branch_regs[i].regmap[r]&63))&1)<<r;
7575 // Merge in delay slot
7576 for(r=0;r<HOST_REGS;r++) {
7577 if(r!=EXCLUDE_REG) {
7578 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7579 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7580 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7581 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7582 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7583 if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7584 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7585 if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7586 if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7587 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7588 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7589 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7590 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7591 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7595 // Conditional branch
7596 will_dirty_i=will_dirty_next;
7597 wont_dirty_i=wont_dirty_next;
7598 //if(ba[i]>start+i*4) { // Disable recursion (for debugging)
7599 for(r=0;r<HOST_REGS;r++) {
7600 if(r!=EXCLUDE_REG) {
7601 signed char target_reg=branch_regs[i].regmap[r];
7602 if(target_reg==regs[(ba[i]-start)>>2].regmap_entry[r]) {
7603 will_dirty_i&=will_dirty[(ba[i]-start)>>2]&(1<<r);
7604 wont_dirty_i|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
7606 else if(target_reg>=0) {
7607 will_dirty_i&=((unneeded_reg[(ba[i]-start)>>2]>>(target_reg&63))&1)<<r;
7608 wont_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>(target_reg&63))&1)<<r;
7610 // Treat delay slot as part of branch too
7611 /*if(regs[i+1].regmap[r]==regs[(ba[i]-start)>>2].regmap_entry[r]) {
7612 will_dirty[i+1]&=will_dirty[(ba[i]-start)>>2]&(1<<r);
7613 wont_dirty[i+1]|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
7617 will_dirty[i+1]&=~(1<<r);
7622 // Merge in delay slot
7623 for(r=0;r<HOST_REGS;r++) {
7624 if(r!=EXCLUDE_REG) {
7626 // Might not dirty if likely branch is not taken
7627 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7628 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7629 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7630 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7631 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7632 if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7633 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7634 //if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7635 //if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7636 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7637 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7638 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7639 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7640 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7645 // Merge in delay slot (won't dirty)
7646 for(r=0;r<HOST_REGS;r++) {
7647 if(r!=EXCLUDE_REG) {
7648 if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7649 if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7650 if((regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7651 if((regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7652 if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7653 if((branch_regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7654 if((branch_regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7655 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7656 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7657 if(branch_regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7661 #ifndef DESTRUCTIVE_WRITEBACK
7662 branch_regs[i].dirty&=wont_dirty_i;
7664 branch_regs[i].dirty|=will_dirty_i;
7669 else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
7671 // SYSCALL instruction (software interrupt)
7675 else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
7677 // ERET instruction (return from interrupt)
7681 will_dirty_next=will_dirty_i;
7682 wont_dirty_next=wont_dirty_i;
7683 for(r=0;r<HOST_REGS;r++) {
7684 if(r!=EXCLUDE_REG) {
7685 if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7686 if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7687 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7688 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7689 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7690 if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7691 if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7692 if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7694 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=FJUMP)
7696 // Don't store a register immediately after writing it,
7697 // may prevent dual-issue.
7698 if((regs[i].regmap[r]&63)==rt1[i-1]) wont_dirty_i|=1<<r;
7699 if((regs[i].regmap[r]&63)==rt2[i-1]) wont_dirty_i|=1<<r;
7705 will_dirty[i]=will_dirty_i;
7706 wont_dirty[i]=wont_dirty_i;
7707 // Mark registers that won't be dirtied as not dirty
7709 /*printf("wr (%d,%d) %x will:",istart,iend,start+i*4);
7710 for(r=0;r<HOST_REGS;r++) {
7711 if((will_dirty_i>>r)&1) {
7717 //if(i==istart||(itype[i-1]!=RJUMP&&itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=FJUMP)) {
7718 regs[i].dirty|=will_dirty_i;
7719 #ifndef DESTRUCTIVE_WRITEBACK
7720 regs[i].dirty&=wont_dirty_i;
7721 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
7723 if(i<iend-1&&itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000) {
7724 for(r=0;r<HOST_REGS;r++) {
7725 if(r!=EXCLUDE_REG) {
7726 if(regs[i].regmap[r]==regmap_pre[i+2][r]) {
7727 regs[i+2].wasdirty&=wont_dirty_i|~(1<<r);
7728 }else {/*printf("i: %x (%d) mismatch(+2): %d\n",start+i*4,i,r);/*assert(!((wont_dirty_i>>r)&1));*/}
7736 for(r=0;r<HOST_REGS;r++) {
7737 if(r!=EXCLUDE_REG) {
7738 if(regs[i].regmap[r]==regmap_pre[i+1][r]) {
7739 regs[i+1].wasdirty&=wont_dirty_i|~(1<<r);
7740 }else {/*printf("i: %x (%d) mismatch(+1): %d\n",start+i*4,i,r);/*assert(!((wont_dirty_i>>r)&1));*/}
7748 // Deal with changed mappings
7749 temp_will_dirty=will_dirty_i;
7750 temp_wont_dirty=wont_dirty_i;
7751 for(r=0;r<HOST_REGS;r++) {
7752 if(r!=EXCLUDE_REG) {
7754 if(regs[i].regmap[r]==regmap_pre[i][r]) {
7756 #ifndef DESTRUCTIVE_WRITEBACK
7757 regs[i].wasdirty&=wont_dirty_i|~(1<<r);
7759 regs[i].wasdirty|=will_dirty_i&(1<<r);
7762 else if(regmap_pre[i][r]>=0&&(nr=get_reg(regs[i].regmap,regmap_pre[i][r]))>=0) {
7763 // Register moved to a different register
7764 will_dirty_i&=~(1<<r);
7765 wont_dirty_i&=~(1<<r);
7766 will_dirty_i|=((temp_will_dirty>>nr)&1)<<r;
7767 wont_dirty_i|=((temp_wont_dirty>>nr)&1)<<r;
7769 #ifndef DESTRUCTIVE_WRITEBACK
7770 regs[i].wasdirty&=wont_dirty_i|~(1<<r);
7772 regs[i].wasdirty|=will_dirty_i&(1<<r);
7776 will_dirty_i&=~(1<<r);
7777 wont_dirty_i&=~(1<<r);
7778 if((regmap_pre[i][r]&63)>0 && (regmap_pre[i][r]&63)<34) {
7779 will_dirty_i|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7780 wont_dirty_i|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7783 /*printf("i: %x (%d) mismatch: %d\n",start+i*4,i,r);/*assert(!((will_dirty>>r)&1));*/
7793 void disassemble_inst(int i)
7795 if (bt[i]) printf("*"); else printf(" ");
7798 printf (" %x: %s %8x\n",start+i*4,insn[i],ba[i]);break;
7800 printf (" %x: %s r%d,r%d,%8x\n",start+i*4,insn[i],rs1[i],rs2[i],i?start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14):*ba);break;
7802 printf (" %x: %s r%d,%8x\n",start+i*4,insn[i],rs1[i],start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14));break;
7804 printf (" %x: %s %8x\n",start+i*4,insn[i],ba[i]);break;
7806 if (opcode[i]==0x9&&rt1[i]!=31)
7807 printf (" %x: %s r%d,r%d\n",start+i*4,insn[i],rt1[i],rs1[i]);
7809 printf (" %x: %s r%d\n",start+i*4,insn[i],rs1[i]);
7812 printf (" %x: %s (pagespan) r%d,r%d,%8x\n",start+i*4,insn[i],rs1[i],rs2[i],ba[i]);break;
7814 if(opcode[i]==0xf) //LUI
7815 printf (" %x: %s r%d,%4x0000\n",start+i*4,insn[i],rt1[i],imm[i]&0xffff);
7817 printf (" %x: %s r%d,r%d,%d\n",start+i*4,insn[i],rt1[i],rs1[i],imm[i]);
7821 printf (" %x: %s r%d,r%d+%x\n",start+i*4,insn[i],rt1[i],rs1[i],imm[i]);
7825 printf (" %x: %s r%d,r%d+%x\n",start+i*4,insn[i],rs2[i],rs1[i],imm[i]);
7829 printf (" %x: %s r%d,r%d,r%d\n",start+i*4,insn[i],rt1[i],rs1[i],rs2[i]);
7832 printf (" %x: %s r%d,r%d\n",start+i*4,insn[i],rs1[i],rs2[i]);
7835 printf (" %x: %s r%d,r%d,%d\n",start+i*4,insn[i],rt1[i],rs1[i],imm[i]);
7838 if((opcode2[i]&0x1d)==0x10)
7839 printf (" %x: %s r%d\n",start+i*4,insn[i],rt1[i]);
7840 else if((opcode2[i]&0x1d)==0x11)
7841 printf (" %x: %s r%d\n",start+i*4,insn[i],rs1[i]);
7843 printf (" %x: %s\n",start+i*4,insn[i]);
7847 printf (" %x: %s r%d,cpr0[%d]\n",start+i*4,insn[i],rt1[i],(source[i]>>11)&0x1f); // MFC0
7848 else if(opcode2[i]==4)
7849 printf (" %x: %s r%d,cpr0[%d]\n",start+i*4,insn[i],rs1[i],(source[i]>>11)&0x1f); // MTC0
7850 else printf (" %x: %s\n",start+i*4,insn[i]);
7854 printf (" %x: %s r%d,cpr1[%d]\n",start+i*4,insn[i],rt1[i],(source[i]>>11)&0x1f); // MFC1
7855 else if(opcode2[i]>3)
7856 printf (" %x: %s r%d,cpr1[%d]\n",start+i*4,insn[i],rs1[i],(source[i]>>11)&0x1f); // MTC1
7857 else printf (" %x: %s\n",start+i*4,insn[i]);
7861 printf (" %x: %s r%d,cpr2[%d]\n",start+i*4,insn[i],rt1[i],(source[i]>>11)&0x1f); // MFC2
7862 else if(opcode2[i]>3)
7863 printf (" %x: %s r%d,cpr2[%d]\n",start+i*4,insn[i],rs1[i],(source[i]>>11)&0x1f); // MTC2
7864 else printf (" %x: %s\n",start+i*4,insn[i]);
7867 printf (" %x: %s cpr1[%d],r%d+%x\n",start+i*4,insn[i],(source[i]>>16)&0x1f,rs1[i],imm[i]);
7870 printf (" %x: %s cpr2[%d],r%d+%x\n",start+i*4,insn[i],(source[i]>>16)&0x1f,rs1[i],imm[i]);
7873 printf (" %x: %s (INTCALL)\n",start+i*4,insn[i]);
7876 //printf (" %s %8x\n",insn[i],source[i]);
7877 printf (" %x: %s\n",start+i*4,insn[i]);
7881 static void disassemble_inst(int i) {}
7884 // clear the state completely, instead of just marking
7885 // things invalid like invalidate_all_pages() does
7886 void new_dynarec_clear_full()
7889 out=(u_char *)BASE_ADDR;
7890 memset(invalid_code,1,sizeof(invalid_code));
7891 memset(hash_table,0xff,sizeof(hash_table));
7892 memset(mini_ht,-1,sizeof(mini_ht));
7893 memset(restore_candidate,0,sizeof(restore_candidate));
7894 memset(shadow,0,sizeof(shadow));
7896 expirep=16384; // Expiry pointer, +2 blocks
7897 pending_exception=0;
7900 inv_code_start=inv_code_end=~0;
7907 for(n=0;n<524288;n++) // 0 .. 0x7FFFFFFF
7909 for(n=524288;n<526336;n++) // 0x80000000 .. 0x807FFFFF
7910 memory_map[n]=((u_int)rdram-0x80000000)>>2;
7911 for(n=526336;n<1048576;n++) // 0x80800000 .. 0xFFFFFFFF
7913 for(n=0;n<4096;n++) ll_clear(jump_in+n);
7914 for(n=0;n<4096;n++) ll_clear(jump_out+n);
7915 for(n=0;n<4096;n++) ll_clear(jump_dirty+n);
7918 void new_dynarec_init()
7920 printf("Init new dynarec\n");
7921 out=(u_char *)BASE_ADDR;
7922 if (mmap (out, 1<<TARGET_SIZE_2,
7923 PROT_READ | PROT_WRITE | PROT_EXEC,
7924 MAP_FIXED | MAP_PRIVATE | MAP_ANONYMOUS,
7925 -1, 0) <= 0) {printf("mmap() failed\n");}
7927 rdword=&readmem_dword;
7928 fake_pc.f.r.rs=&readmem_dword;
7929 fake_pc.f.r.rt=&readmem_dword;
7930 fake_pc.f.r.rd=&readmem_dword;
7933 new_dynarec_clear_full();
7935 // Copy this into local area so we don't have to put it in every literal pool
7936 invc_ptr=invalid_code;
7939 for(n=0;n<0x8000;n++) { // 0 .. 0x7FFFFFFF
7940 writemem[n] = write_nomem_new;
7941 writememb[n] = write_nomemb_new;
7942 writememh[n] = write_nomemh_new;
7944 writememd[n] = write_nomemd_new;
7946 readmem[n] = read_nomem_new;
7947 readmemb[n] = read_nomemb_new;
7948 readmemh[n] = read_nomemh_new;
7950 readmemd[n] = read_nomemd_new;
7953 for(n=0x8000;n<0x8080;n++) { // 0x80000000 .. 0x807FFFFF
7954 writemem[n] = write_rdram_new;
7955 writememb[n] = write_rdramb_new;
7956 writememh[n] = write_rdramh_new;
7958 writememd[n] = write_rdramd_new;
7961 for(n=0xC000;n<0x10000;n++) { // 0xC0000000 .. 0xFFFFFFFF
7962 writemem[n] = write_nomem_new;
7963 writememb[n] = write_nomemb_new;
7964 writememh[n] = write_nomemh_new;
7966 writememd[n] = write_nomemd_new;
7968 readmem[n] = read_nomem_new;
7969 readmemb[n] = read_nomemb_new;
7970 readmemh[n] = read_nomemh_new;
7972 readmemd[n] = read_nomemd_new;
7980 void new_dynarec_cleanup()
7983 if (munmap ((void *)BASE_ADDR, 1<<TARGET_SIZE_2) < 0) {printf("munmap() failed\n");}
7984 for(n=0;n<4096;n++) ll_clear(jump_in+n);
7985 for(n=0;n<4096;n++) ll_clear(jump_out+n);
7986 for(n=0;n<4096;n++) ll_clear(jump_dirty+n);
7988 if (munmap (ROM_COPY, 67108864) < 0) {printf("munmap() failed\n");}
7992 int new_recompile_block(int addr)
7995 if(addr==0x800cd050) {
7997 for(block=0x80000;block<0x80800;block++) invalidate_block(block);
7999 for(n=0;n<=2048;n++) ll_clear(jump_dirty+n);
8002 //if(Count==365117028) tracedebug=1;
8003 assem_debug("NOTCOMPILED: addr = %x -> %x\n", (int)addr, (int)out);
8004 //printf("NOTCOMPILED: addr = %x -> %x\n", (int)addr, (int)out);
8005 //printf("TRACE: count=%d next=%d (compile %x)\n",Count,next_interupt,addr);
8007 //printf("TRACE: count=%d next=%d (checksum %x)\n",Count,next_interupt,mchecksum());
8008 //printf("fpu mapping=%x enabled=%x\n",(Status & 0x04000000)>>26,(Status & 0x20000000)>>29);
8009 /*if(Count>=312978186) {
8013 start = (u_int)addr&~3;
8014 //assert(((u_int)addr&1)==0);
8015 new_dynarec_did_compile=1;
8017 if(!sp_in_mirror&&(signed int)(psxRegs.GPR.n.sp&0xffe00000)>0x80200000&&
8018 0x10000<=psxRegs.GPR.n.sp&&(psxRegs.GPR.n.sp&~0xe0e00000)<RAM_SIZE) {
8019 printf("SP hack enabled (%08x), @%08x\n", psxRegs.GPR.n.sp, psxRegs.pc);
8022 if (Config.HLE && start == 0x80001000) // hlecall
8024 // XXX: is this enough? Maybe check hleSoftCall?
8025 u_int beginning=(u_int)out;
8026 u_int page=get_page(start);
8027 invalid_code[start>>12]=0;
8028 emit_movimm(start,0);
8029 emit_writeword(0,(int)&pcaddr);
8030 emit_jmp((int)new_dyna_leave);
8033 __clear_cache((void *)beginning,out);
8035 ll_add(jump_in+page,start,(void *)beginning);
8038 else if ((u_int)addr < 0x00200000 ||
8039 (0xa0000000 <= addr && addr < 0xa0200000)) {
8040 // used for BIOS calls mostly?
8041 source = (u_int *)((u_int)rdram+(start&0x1fffff));
8042 pagelimit = (addr&0xa0000000)|0x00200000;
8044 else if (!Config.HLE && (
8045 /* (0x9fc00000 <= addr && addr < 0x9fc80000) ||*/
8046 (0xbfc00000 <= addr && addr < 0xbfc80000))) {
8048 source = (u_int *)((u_int)psxR+(start&0x7ffff));
8049 pagelimit = (addr&0xfff00000)|0x80000;
8054 if ((int)addr >= 0xa4000000 && (int)addr < 0xa4001000) {
8055 source = (u_int *)((u_int)SP_DMEM+start-0xa4000000);
8056 pagelimit = 0xa4001000;
8060 if ((int)addr >= 0x80000000 && (int)addr < 0x80000000+RAM_SIZE) {
8061 source = (u_int *)((u_int)rdram+start-0x80000000);
8062 pagelimit = 0x80000000+RAM_SIZE;
8065 else if ((signed int)addr >= (signed int)0xC0000000) {
8066 //printf("addr=%x mm=%x\n",(u_int)addr,(memory_map[start>>12]<<2));
8067 //if(tlb_LUT_r[start>>12])
8068 //source = (u_int *)(((int)rdram)+(tlb_LUT_r[start>>12]&0xFFFFF000)+(((int)addr)&0xFFF)-0x80000000);
8069 if((signed int)memory_map[start>>12]>=0) {
8070 source = (u_int *)((u_int)(start+(memory_map[start>>12]<<2)));
8071 pagelimit=(start+4096)&0xFFFFF000;
8072 int map=memory_map[start>>12];
8075 //printf("start: %x next: %x\n",map,memory_map[pagelimit>>12]);
8076 if((map&0xBFFFFFFF)==(memory_map[pagelimit>>12]&0xBFFFFFFF)) pagelimit+=4096;
8078 assem_debug("pagelimit=%x\n",pagelimit);
8079 assem_debug("mapping=%x (%x)\n",memory_map[start>>12],(memory_map[start>>12]<<2)+start);
8082 assem_debug("Compile at unmapped memory address: %x \n", (int)addr);
8083 //assem_debug("start: %x next: %x\n",memory_map[start>>12],memory_map[(start+4096)>>12]);
8084 return -1; // Caller will invoke exception handler
8086 //printf("source= %x\n",(int)source);
8090 printf("Compile at bogus memory address: %x \n", (int)addr);
8094 /* Pass 1: disassemble */
8095 /* Pass 2: register dependencies, branch targets */
8096 /* Pass 3: register allocation */
8097 /* Pass 4: branch dependencies */
8098 /* Pass 5: pre-alloc */
8099 /* Pass 6: optimize clean/dirty state */
8100 /* Pass 7: flag 32-bit registers */
8101 /* Pass 8: assembly */
8102 /* Pass 9: linker */
8103 /* Pass 10: garbage collection / free memory */
8107 unsigned int type,op,op2;
8109 //printf("addr = %x source = %x %x\n", addr,source,source[0]);
8111 /* Pass 1 disassembly */
8113 for(i=0;!done;i++) {
8114 bt[i]=0;likely[i]=0;ooo[i]=0;op2=0;
8115 minimum_free_regs[i]=0;
8116 opcode[i]=op=source[i]>>26;
8119 case 0x00: strcpy(insn[i],"special"); type=NI;
8123 case 0x00: strcpy(insn[i],"SLL"); type=SHIFTIMM; break;
8124 case 0x02: strcpy(insn[i],"SRL"); type=SHIFTIMM; break;
8125 case 0x03: strcpy(insn[i],"SRA"); type=SHIFTIMM; break;
8126 case 0x04: strcpy(insn[i],"SLLV"); type=SHIFT; break;
8127 case 0x06: strcpy(insn[i],"SRLV"); type=SHIFT; break;
8128 case 0x07: strcpy(insn[i],"SRAV"); type=SHIFT; break;
8129 case 0x08: strcpy(insn[i],"JR"); type=RJUMP; break;
8130 case 0x09: strcpy(insn[i],"JALR"); type=RJUMP; break;
8131 case 0x0C: strcpy(insn[i],"SYSCALL"); type=SYSCALL; break;
8132 case 0x0D: strcpy(insn[i],"BREAK"); type=OTHER; break;
8133 case 0x0F: strcpy(insn[i],"SYNC"); type=OTHER; break;
8134 case 0x10: strcpy(insn[i],"MFHI"); type=MOV; break;
8135 case 0x11: strcpy(insn[i],"MTHI"); type=MOV; break;
8136 case 0x12: strcpy(insn[i],"MFLO"); type=MOV; break;
8137 case 0x13: strcpy(insn[i],"MTLO"); type=MOV; break;
8138 case 0x18: strcpy(insn[i],"MULT"); type=MULTDIV; break;
8139 case 0x19: strcpy(insn[i],"MULTU"); type=MULTDIV; break;
8140 case 0x1A: strcpy(insn[i],"DIV"); type=MULTDIV; break;
8141 case 0x1B: strcpy(insn[i],"DIVU"); type=MULTDIV; break;
8142 case 0x20: strcpy(insn[i],"ADD"); type=ALU; break;
8143 case 0x21: strcpy(insn[i],"ADDU"); type=ALU; break;
8144 case 0x22: strcpy(insn[i],"SUB"); type=ALU; break;
8145 case 0x23: strcpy(insn[i],"SUBU"); type=ALU; break;
8146 case 0x24: strcpy(insn[i],"AND"); type=ALU; break;
8147 case 0x25: strcpy(insn[i],"OR"); type=ALU; break;
8148 case 0x26: strcpy(insn[i],"XOR"); type=ALU; break;
8149 case 0x27: strcpy(insn[i],"NOR"); type=ALU; break;
8150 case 0x2A: strcpy(insn[i],"SLT"); type=ALU; break;
8151 case 0x2B: strcpy(insn[i],"SLTU"); type=ALU; break;
8152 case 0x30: strcpy(insn[i],"TGE"); type=NI; break;
8153 case 0x31: strcpy(insn[i],"TGEU"); type=NI; break;
8154 case 0x32: strcpy(insn[i],"TLT"); type=NI; break;
8155 case 0x33: strcpy(insn[i],"TLTU"); type=NI; break;
8156 case 0x34: strcpy(insn[i],"TEQ"); type=NI; break;
8157 case 0x36: strcpy(insn[i],"TNE"); type=NI; break;
8159 case 0x14: strcpy(insn[i],"DSLLV"); type=SHIFT; break;
8160 case 0x16: strcpy(insn[i],"DSRLV"); type=SHIFT; break;
8161 case 0x17: strcpy(insn[i],"DSRAV"); type=SHIFT; break;
8162 case 0x1C: strcpy(insn[i],"DMULT"); type=MULTDIV; break;
8163 case 0x1D: strcpy(insn[i],"DMULTU"); type=MULTDIV; break;
8164 case 0x1E: strcpy(insn[i],"DDIV"); type=MULTDIV; break;
8165 case 0x1F: strcpy(insn[i],"DDIVU"); type=MULTDIV; break;
8166 case 0x2C: strcpy(insn[i],"DADD"); type=ALU; break;
8167 case 0x2D: strcpy(insn[i],"DADDU"); type=ALU; break;
8168 case 0x2E: strcpy(insn[i],"DSUB"); type=ALU; break;
8169 case 0x2F: strcpy(insn[i],"DSUBU"); type=ALU; break;
8170 case 0x38: strcpy(insn[i],"DSLL"); type=SHIFTIMM; break;
8171 case 0x3A: strcpy(insn[i],"DSRL"); type=SHIFTIMM; break;
8172 case 0x3B: strcpy(insn[i],"DSRA"); type=SHIFTIMM; break;
8173 case 0x3C: strcpy(insn[i],"DSLL32"); type=SHIFTIMM; break;
8174 case 0x3E: strcpy(insn[i],"DSRL32"); type=SHIFTIMM; break;
8175 case 0x3F: strcpy(insn[i],"DSRA32"); type=SHIFTIMM; break;
8179 case 0x01: strcpy(insn[i],"regimm"); type=NI;
8180 op2=(source[i]>>16)&0x1f;
8183 case 0x00: strcpy(insn[i],"BLTZ"); type=SJUMP; break;
8184 case 0x01: strcpy(insn[i],"BGEZ"); type=SJUMP; break;
8185 case 0x02: strcpy(insn[i],"BLTZL"); type=SJUMP; break;
8186 case 0x03: strcpy(insn[i],"BGEZL"); type=SJUMP; break;
8187 case 0x08: strcpy(insn[i],"TGEI"); type=NI; break;
8188 case 0x09: strcpy(insn[i],"TGEIU"); type=NI; break;
8189 case 0x0A: strcpy(insn[i],"TLTI"); type=NI; break;
8190 case 0x0B: strcpy(insn[i],"TLTIU"); type=NI; break;
8191 case 0x0C: strcpy(insn[i],"TEQI"); type=NI; break;
8192 case 0x0E: strcpy(insn[i],"TNEI"); type=NI; break;
8193 case 0x10: strcpy(insn[i],"BLTZAL"); type=SJUMP; break;
8194 case 0x11: strcpy(insn[i],"BGEZAL"); type=SJUMP; break;
8195 case 0x12: strcpy(insn[i],"BLTZALL"); type=SJUMP; break;
8196 case 0x13: strcpy(insn[i],"BGEZALL"); type=SJUMP; break;
8199 case 0x02: strcpy(insn[i],"J"); type=UJUMP; break;
8200 case 0x03: strcpy(insn[i],"JAL"); type=UJUMP; break;
8201 case 0x04: strcpy(insn[i],"BEQ"); type=CJUMP; break;
8202 case 0x05: strcpy(insn[i],"BNE"); type=CJUMP; break;
8203 case 0x06: strcpy(insn[i],"BLEZ"); type=CJUMP; break;
8204 case 0x07: strcpy(insn[i],"BGTZ"); type=CJUMP; break;
8205 case 0x08: strcpy(insn[i],"ADDI"); type=IMM16; break;
8206 case 0x09: strcpy(insn[i],"ADDIU"); type=IMM16; break;
8207 case 0x0A: strcpy(insn[i],"SLTI"); type=IMM16; break;
8208 case 0x0B: strcpy(insn[i],"SLTIU"); type=IMM16; break;
8209 case 0x0C: strcpy(insn[i],"ANDI"); type=IMM16; break;
8210 case 0x0D: strcpy(insn[i],"ORI"); type=IMM16; break;
8211 case 0x0E: strcpy(insn[i],"XORI"); type=IMM16; break;
8212 case 0x0F: strcpy(insn[i],"LUI"); type=IMM16; break;
8213 case 0x10: strcpy(insn[i],"cop0"); type=NI;
8214 op2=(source[i]>>21)&0x1f;
8217 case 0x00: strcpy(insn[i],"MFC0"); type=COP0; break;
8218 case 0x04: strcpy(insn[i],"MTC0"); type=COP0; break;
8219 case 0x10: strcpy(insn[i],"tlb"); type=NI;
8220 switch(source[i]&0x3f)
8222 case 0x01: strcpy(insn[i],"TLBR"); type=COP0; break;
8223 case 0x02: strcpy(insn[i],"TLBWI"); type=COP0; break;
8224 case 0x06: strcpy(insn[i],"TLBWR"); type=COP0; break;
8225 case 0x08: strcpy(insn[i],"TLBP"); type=COP0; break;
8227 case 0x10: strcpy(insn[i],"RFE"); type=COP0; break;
8229 case 0x18: strcpy(insn[i],"ERET"); type=COP0; break;
8234 case 0x11: strcpy(insn[i],"cop1"); type=NI;
8235 op2=(source[i]>>21)&0x1f;
8238 case 0x00: strcpy(insn[i],"MFC1"); type=COP1; break;
8239 case 0x01: strcpy(insn[i],"DMFC1"); type=COP1; break;
8240 case 0x02: strcpy(insn[i],"CFC1"); type=COP1; break;
8241 case 0x04: strcpy(insn[i],"MTC1"); type=COP1; break;
8242 case 0x05: strcpy(insn[i],"DMTC1"); type=COP1; break;
8243 case 0x06: strcpy(insn[i],"CTC1"); type=COP1; break;
8244 case 0x08: strcpy(insn[i],"BC1"); type=FJUMP;
8245 switch((source[i]>>16)&0x3)
8247 case 0x00: strcpy(insn[i],"BC1F"); break;
8248 case 0x01: strcpy(insn[i],"BC1T"); break;
8249 case 0x02: strcpy(insn[i],"BC1FL"); break;
8250 case 0x03: strcpy(insn[i],"BC1TL"); break;
8253 case 0x10: strcpy(insn[i],"C1.S"); type=NI;
8254 switch(source[i]&0x3f)
8256 case 0x00: strcpy(insn[i],"ADD.S"); type=FLOAT; break;
8257 case 0x01: strcpy(insn[i],"SUB.S"); type=FLOAT; break;
8258 case 0x02: strcpy(insn[i],"MUL.S"); type=FLOAT; break;
8259 case 0x03: strcpy(insn[i],"DIV.S"); type=FLOAT; break;
8260 case 0x04: strcpy(insn[i],"SQRT.S"); type=FLOAT; break;
8261 case 0x05: strcpy(insn[i],"ABS.S"); type=FLOAT; break;
8262 case 0x06: strcpy(insn[i],"MOV.S"); type=FLOAT; break;
8263 case 0x07: strcpy(insn[i],"NEG.S"); type=FLOAT; break;
8264 case 0x08: strcpy(insn[i],"ROUND.L.S"); type=FCONV; break;
8265 case 0x09: strcpy(insn[i],"TRUNC.L.S"); type=FCONV; break;
8266 case 0x0A: strcpy(insn[i],"CEIL.L.S"); type=FCONV; break;
8267 case 0x0B: strcpy(insn[i],"FLOOR.L.S"); type=FCONV; break;
8268 case 0x0C: strcpy(insn[i],"ROUND.W.S"); type=FCONV; break;
8269 case 0x0D: strcpy(insn[i],"TRUNC.W.S"); type=FCONV; break;
8270 case 0x0E: strcpy(insn[i],"CEIL.W.S"); type=FCONV; break;
8271 case 0x0F: strcpy(insn[i],"FLOOR.W.S"); type=FCONV; break;
8272 case 0x21: strcpy(insn[i],"CVT.D.S"); type=FCONV; break;
8273 case 0x24: strcpy(insn[i],"CVT.W.S"); type=FCONV; break;
8274 case 0x25: strcpy(insn[i],"CVT.L.S"); type=FCONV; break;
8275 case 0x30: strcpy(insn[i],"C.F.S"); type=FCOMP; break;
8276 case 0x31: strcpy(insn[i],"C.UN.S"); type=FCOMP; break;
8277 case 0x32: strcpy(insn[i],"C.EQ.S"); type=FCOMP; break;
8278 case 0x33: strcpy(insn[i],"C.UEQ.S"); type=FCOMP; break;
8279 case 0x34: strcpy(insn[i],"C.OLT.S"); type=FCOMP; break;
8280 case 0x35: strcpy(insn[i],"C.ULT.S"); type=FCOMP; break;
8281 case 0x36: strcpy(insn[i],"C.OLE.S"); type=FCOMP; break;
8282 case 0x37: strcpy(insn[i],"C.ULE.S"); type=FCOMP; break;
8283 case 0x38: strcpy(insn[i],"C.SF.S"); type=FCOMP; break;
8284 case 0x39: strcpy(insn[i],"C.NGLE.S"); type=FCOMP; break;
8285 case 0x3A: strcpy(insn[i],"C.SEQ.S"); type=FCOMP; break;
8286 case 0x3B: strcpy(insn[i],"C.NGL.S"); type=FCOMP; break;
8287 case 0x3C: strcpy(insn[i],"C.LT.S"); type=FCOMP; break;
8288 case 0x3D: strcpy(insn[i],"C.NGE.S"); type=FCOMP; break;
8289 case 0x3E: strcpy(insn[i],"C.LE.S"); type=FCOMP; break;
8290 case 0x3F: strcpy(insn[i],"C.NGT.S"); type=FCOMP; break;
8293 case 0x11: strcpy(insn[i],"C1.D"); type=NI;
8294 switch(source[i]&0x3f)
8296 case 0x00: strcpy(insn[i],"ADD.D"); type=FLOAT; break;
8297 case 0x01: strcpy(insn[i],"SUB.D"); type=FLOAT; break;
8298 case 0x02: strcpy(insn[i],"MUL.D"); type=FLOAT; break;
8299 case 0x03: strcpy(insn[i],"DIV.D"); type=FLOAT; break;
8300 case 0x04: strcpy(insn[i],"SQRT.D"); type=FLOAT; break;
8301 case 0x05: strcpy(insn[i],"ABS.D"); type=FLOAT; break;
8302 case 0x06: strcpy(insn[i],"MOV.D"); type=FLOAT; break;
8303 case 0x07: strcpy(insn[i],"NEG.D"); type=FLOAT; break;
8304 case 0x08: strcpy(insn[i],"ROUND.L.D"); type=FCONV; break;
8305 case 0x09: strcpy(insn[i],"TRUNC.L.D"); type=FCONV; break;
8306 case 0x0A: strcpy(insn[i],"CEIL.L.D"); type=FCONV; break;
8307 case 0x0B: strcpy(insn[i],"FLOOR.L.D"); type=FCONV; break;
8308 case 0x0C: strcpy(insn[i],"ROUND.W.D"); type=FCONV; break;
8309 case 0x0D: strcpy(insn[i],"TRUNC.W.D"); type=FCONV; break;
8310 case 0x0E: strcpy(insn[i],"CEIL.W.D"); type=FCONV; break;
8311 case 0x0F: strcpy(insn[i],"FLOOR.W.D"); type=FCONV; break;
8312 case 0x20: strcpy(insn[i],"CVT.S.D"); type=FCONV; break;
8313 case 0x24: strcpy(insn[i],"CVT.W.D"); type=FCONV; break;
8314 case 0x25: strcpy(insn[i],"CVT.L.D"); type=FCONV; break;
8315 case 0x30: strcpy(insn[i],"C.F.D"); type=FCOMP; break;
8316 case 0x31: strcpy(insn[i],"C.UN.D"); type=FCOMP; break;
8317 case 0x32: strcpy(insn[i],"C.EQ.D"); type=FCOMP; break;
8318 case 0x33: strcpy(insn[i],"C.UEQ.D"); type=FCOMP; break;
8319 case 0x34: strcpy(insn[i],"C.OLT.D"); type=FCOMP; break;
8320 case 0x35: strcpy(insn[i],"C.ULT.D"); type=FCOMP; break;
8321 case 0x36: strcpy(insn[i],"C.OLE.D"); type=FCOMP; break;
8322 case 0x37: strcpy(insn[i],"C.ULE.D"); type=FCOMP; break;
8323 case 0x38: strcpy(insn[i],"C.SF.D"); type=FCOMP; break;
8324 case 0x39: strcpy(insn[i],"C.NGLE.D"); type=FCOMP; break;
8325 case 0x3A: strcpy(insn[i],"C.SEQ.D"); type=FCOMP; break;
8326 case 0x3B: strcpy(insn[i],"C.NGL.D"); type=FCOMP; break;
8327 case 0x3C: strcpy(insn[i],"C.LT.D"); type=FCOMP; break;
8328 case 0x3D: strcpy(insn[i],"C.NGE.D"); type=FCOMP; break;
8329 case 0x3E: strcpy(insn[i],"C.LE.D"); type=FCOMP; break;
8330 case 0x3F: strcpy(insn[i],"C.NGT.D"); type=FCOMP; break;
8333 case 0x14: strcpy(insn[i],"C1.W"); type=NI;
8334 switch(source[i]&0x3f)
8336 case 0x20: strcpy(insn[i],"CVT.S.W"); type=FCONV; break;
8337 case 0x21: strcpy(insn[i],"CVT.D.W"); type=FCONV; break;
8340 case 0x15: strcpy(insn[i],"C1.L"); type=NI;
8341 switch(source[i]&0x3f)
8343 case 0x20: strcpy(insn[i],"CVT.S.L"); type=FCONV; break;
8344 case 0x21: strcpy(insn[i],"CVT.D.L"); type=FCONV; break;
8350 case 0x14: strcpy(insn[i],"BEQL"); type=CJUMP; break;
8351 case 0x15: strcpy(insn[i],"BNEL"); type=CJUMP; break;
8352 case 0x16: strcpy(insn[i],"BLEZL"); type=CJUMP; break;
8353 case 0x17: strcpy(insn[i],"BGTZL"); type=CJUMP; break;
8354 case 0x18: strcpy(insn[i],"DADDI"); type=IMM16; break;
8355 case 0x19: strcpy(insn[i],"DADDIU"); type=IMM16; break;
8356 case 0x1A: strcpy(insn[i],"LDL"); type=LOADLR; break;
8357 case 0x1B: strcpy(insn[i],"LDR"); type=LOADLR; break;
8359 case 0x20: strcpy(insn[i],"LB"); type=LOAD; break;
8360 case 0x21: strcpy(insn[i],"LH"); type=LOAD; break;
8361 case 0x22: strcpy(insn[i],"LWL"); type=LOADLR; break;
8362 case 0x23: strcpy(insn[i],"LW"); type=LOAD; break;
8363 case 0x24: strcpy(insn[i],"LBU"); type=LOAD; break;
8364 case 0x25: strcpy(insn[i],"LHU"); type=LOAD; break;
8365 case 0x26: strcpy(insn[i],"LWR"); type=LOADLR; break;
8367 case 0x27: strcpy(insn[i],"LWU"); type=LOAD; break;
8369 case 0x28: strcpy(insn[i],"SB"); type=STORE; break;
8370 case 0x29: strcpy(insn[i],"SH"); type=STORE; break;
8371 case 0x2A: strcpy(insn[i],"SWL"); type=STORELR; break;
8372 case 0x2B: strcpy(insn[i],"SW"); type=STORE; break;
8374 case 0x2C: strcpy(insn[i],"SDL"); type=STORELR; break;
8375 case 0x2D: strcpy(insn[i],"SDR"); type=STORELR; break;
8377 case 0x2E: strcpy(insn[i],"SWR"); type=STORELR; break;
8378 case 0x2F: strcpy(insn[i],"CACHE"); type=NOP; break;
8379 case 0x30: strcpy(insn[i],"LL"); type=NI; break;
8380 case 0x31: strcpy(insn[i],"LWC1"); type=C1LS; break;
8382 case 0x34: strcpy(insn[i],"LLD"); type=NI; break;
8383 case 0x35: strcpy(insn[i],"LDC1"); type=C1LS; break;
8384 case 0x37: strcpy(insn[i],"LD"); type=LOAD; break;
8386 case 0x38: strcpy(insn[i],"SC"); type=NI; break;
8387 case 0x39: strcpy(insn[i],"SWC1"); type=C1LS; break;
8389 case 0x3C: strcpy(insn[i],"SCD"); type=NI; break;
8390 case 0x3D: strcpy(insn[i],"SDC1"); type=C1LS; break;
8391 case 0x3F: strcpy(insn[i],"SD"); type=STORE; break;
8394 case 0x12: strcpy(insn[i],"COP2"); type=NI;
8395 op2=(source[i]>>21)&0x1f;
8397 if (source[i]&0x3f) { // use this hack to support old savestates with patched gte insns
8398 if (gte_handlers[source[i]&0x3f]!=NULL) {
8399 if (gte_regnames[source[i]&0x3f]!=NULL)
8400 strcpy(insn[i],gte_regnames[source[i]&0x3f]);
8402 snprintf(insn[i], sizeof(insn[i]), "COP2 %x", source[i]&0x3f);
8408 case 0x00: strcpy(insn[i],"MFC2"); type=COP2; break;
8409 case 0x02: strcpy(insn[i],"CFC2"); type=COP2; break;
8410 case 0x04: strcpy(insn[i],"MTC2"); type=COP2; break;
8411 case 0x06: strcpy(insn[i],"CTC2"); type=COP2; break;
8414 case 0x32: strcpy(insn[i],"LWC2"); type=C2LS; break;
8415 case 0x3A: strcpy(insn[i],"SWC2"); type=C2LS; break;
8416 case 0x3B: strcpy(insn[i],"HLECALL"); type=HLECALL; break;
8418 default: strcpy(insn[i],"???"); type=NI;
8419 printf("NI %08x @%08x (%08x)\n", source[i], addr + i*4, addr);
8424 /* Get registers/immediates */
8430 gte_rs[i]=gte_rt[i]=0;
8433 rs1[i]=(source[i]>>21)&0x1f;
8435 rt1[i]=(source[i]>>16)&0x1f;
8437 imm[i]=(short)source[i];
8441 rs1[i]=(source[i]>>21)&0x1f;
8442 rs2[i]=(source[i]>>16)&0x1f;
8445 imm[i]=(short)source[i];
8446 if(op==0x2c||op==0x2d||op==0x3f) us1[i]=rs2[i]; // 64-bit SDL/SDR/SD
8449 // LWL/LWR only load part of the register,
8450 // therefore the target register must be treated as a source too
8451 rs1[i]=(source[i]>>21)&0x1f;
8452 rs2[i]=(source[i]>>16)&0x1f;
8453 rt1[i]=(source[i]>>16)&0x1f;
8455 imm[i]=(short)source[i];
8456 if(op==0x1a||op==0x1b) us1[i]=rs2[i]; // LDR/LDL
8457 if(op==0x26) dep1[i]=rt1[i]; // LWR
8460 if (op==0x0f) rs1[i]=0; // LUI instruction has no source register
8461 else rs1[i]=(source[i]>>21)&0x1f;
8463 rt1[i]=(source[i]>>16)&0x1f;
8465 if(op>=0x0c&&op<=0x0e) { // ANDI/ORI/XORI
8466 imm[i]=(unsigned short)source[i];
8468 imm[i]=(short)source[i];
8470 if(op==0x18||op==0x19) us1[i]=rs1[i]; // DADDI/DADDIU
8471 if(op==0x0a||op==0x0b) us1[i]=rs1[i]; // SLTI/SLTIU
8472 if(op==0x0d||op==0x0e) dep1[i]=rs1[i]; // ORI/XORI
8479 // The JAL instruction writes to r31.
8486 rs1[i]=(source[i]>>21)&0x1f;
8490 // The JALR instruction writes to rd.
8492 rt1[i]=(source[i]>>11)&0x1f;
8497 rs1[i]=(source[i]>>21)&0x1f;
8498 rs2[i]=(source[i]>>16)&0x1f;
8501 if(op&2) { // BGTZ/BLEZ
8509 rs1[i]=(source[i]>>21)&0x1f;
8514 if(op2&0x10) { // BxxAL
8516 // NOTE: If the branch is not taken, r31 is still overwritten
8518 likely[i]=(op2&2)>>1;
8525 likely[i]=((source[i])>>17)&1;
8528 rs1[i]=(source[i]>>21)&0x1f; // source
8529 rs2[i]=(source[i]>>16)&0x1f; // subtract amount
8530 rt1[i]=(source[i]>>11)&0x1f; // destination
8532 if(op2==0x2a||op2==0x2b) { // SLT/SLTU
8533 us1[i]=rs1[i];us2[i]=rs2[i];
8535 else if(op2>=0x24&&op2<=0x27) { // AND/OR/XOR/NOR
8536 dep1[i]=rs1[i];dep2[i]=rs2[i];
8538 else if(op2>=0x2c&&op2<=0x2f) { // DADD/DSUB
8539 dep1[i]=rs1[i];dep2[i]=rs2[i];
8543 rs1[i]=(source[i]>>21)&0x1f; // source
8544 rs2[i]=(source[i]>>16)&0x1f; // divisor
8547 if (op2>=0x1c&&op2<=0x1f) { // DMULT/DMULTU/DDIV/DDIVU
8548 us1[i]=rs1[i];us2[i]=rs2[i];
8556 if(op2==0x10) rs1[i]=HIREG; // MFHI
8557 if(op2==0x11) rt1[i]=HIREG; // MTHI
8558 if(op2==0x12) rs1[i]=LOREG; // MFLO
8559 if(op2==0x13) rt1[i]=LOREG; // MTLO
8560 if((op2&0x1d)==0x10) rt1[i]=(source[i]>>11)&0x1f; // MFxx
8561 if((op2&0x1d)==0x11) rs1[i]=(source[i]>>21)&0x1f; // MTxx
8565 rs1[i]=(source[i]>>16)&0x1f; // target of shift
8566 rs2[i]=(source[i]>>21)&0x1f; // shift amount
8567 rt1[i]=(source[i]>>11)&0x1f; // destination
8569 // DSLLV/DSRLV/DSRAV are 64-bit
8570 if(op2>=0x14&&op2<=0x17) us1[i]=rs1[i];
8573 rs1[i]=(source[i]>>16)&0x1f;
8575 rt1[i]=(source[i]>>11)&0x1f;
8577 imm[i]=(source[i]>>6)&0x1f;
8578 // DSxx32 instructions
8579 if(op2>=0x3c) imm[i]|=0x20;
8580 // DSLL/DSRL/DSRA/DSRA32/DSRL32 but not DSLL32 require 64-bit source
8581 if(op2>=0x38&&op2!=0x3c) us1[i]=rs1[i];
8588 if(op2==0) rt1[i]=(source[i]>>16)&0x1F; // MFC0
8589 if(op2==4) rs1[i]=(source[i]>>16)&0x1F; // MTC0
8590 if(op2==4&&((source[i]>>11)&0x1f)==12) rt2[i]=CSREG; // Status
8591 if(op2==16) if((source[i]&0x3f)==0x18) rs2[i]=CCREG; // ERET
8598 if(op2<3) rt1[i]=(source[i]>>16)&0x1F; // MFC1/DMFC1/CFC1
8599 if(op2>3) rs1[i]=(source[i]>>16)&0x1F; // MTC1/DMTC1/CTC1
8600 if(op2==5) us1[i]=rs1[i]; // DMTC1
8608 if(op2<3) rt1[i]=(source[i]>>16)&0x1F; // MFC2/CFC2
8609 if(op2>3) rs1[i]=(source[i]>>16)&0x1F; // MTC2/CTC2
8611 int gr=(source[i]>>11)&0x1F;
8614 case 0x00: gte_rs[i]=1ll<<gr; break; // MFC2
8615 case 0x04: gte_rt[i]=1ll<<gr; break; // MTC2
8616 case 0x02: gte_rs[i]=1ll<<(gr+32); // CFC2
8617 if(gr==31&&!gte_reads_flags) {
8618 assem_debug("gte flag read encountered @%08x\n",addr + i*4);
8622 case 0x06: gte_rt[i]=1ll<<(gr+32); break; // CTC2
8626 rs1[i]=(source[i]>>21)&0x1F;
8630 imm[i]=(short)source[i];
8633 rs1[i]=(source[i]>>21)&0x1F;
8637 imm[i]=(short)source[i];
8638 if(op==0x32) gte_rt[i]=1ll<<((source[i]>>16)&0x1F); // LWC2
8639 else gte_rs[i]=1ll<<((source[i]>>16)&0x1F); // SWC2
8646 gte_rt[i]=1ll<<63; // every op changes flags
8647 // TODO: other regs?
8676 /* Calculate branch target addresses */
8678 ba[i]=((start+i*4+4)&0xF0000000)|(((unsigned int)source[i]<<6)>>4);
8679 else if(type==CJUMP&&rs1[i]==rs2[i]&&(op&1))
8680 ba[i]=start+i*4+8; // Ignore never taken branch
8681 else if(type==SJUMP&&rs1[i]==0&&!(op2&1))
8682 ba[i]=start+i*4+8; // Ignore never taken branch
8683 else if(type==CJUMP||type==SJUMP||type==FJUMP)
8684 ba[i]=start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14);
8687 if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)) {
8689 // branch in delay slot?
8690 if(type==RJUMP||type==UJUMP||type==CJUMP||type==SJUMP||type==FJUMP) {
8691 // don't handle first branch and call interpreter if it's hit
8692 printf("branch in delay slot @%08x (%08x)\n", addr + i*4, addr);
8695 // basic load delay detection
8696 else if((type==LOAD||type==LOADLR||type==COP0||type==COP2||type==C2LS)&&rt1[i]!=0) {
8697 int t=(ba[i-1]-start)/4;
8698 if(0 <= t && t < i &&(rt1[i]==rs1[t]||rt1[i]==rs2[t])&&itype[t]!=CJUMP&&itype[t]!=SJUMP) {
8699 // jump target wants DS result - potential load delay effect
8700 printf("load delay @%08x (%08x)\n", addr + i*4, addr);
8702 bt[t+1]=1; // expected return from interpreter
8704 else if(i>=2&&rt1[i-2]==2&&rt1[i]==2&&rs1[i]!=2&&rs2[i]!=2&&rs1[i-1]!=2&&rs2[i-1]!=2&&
8705 !(i>=3&&(itype[i-3]==RJUMP||itype[i-3]==UJUMP||itype[i-3]==CJUMP||itype[i-3]==SJUMP))) {
8706 // v0 overwrite like this is a sign of trouble, bail out
8707 printf("v0 overwrite @%08x (%08x)\n", addr + i*4, addr);
8713 rs2[i-1]=rt1[i-1]=rt2[i-1]=0;
8717 i--; // don't compile the DS
8721 /* Is this the end of the block? */
8722 if(i>0&&(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)) {
8723 if(rt1[i-1]==0) { // Continue past subroutine call (JAL)
8727 if(stop_after_jal) done=1;
8729 if((source[i+1]&0xfc00003f)==0x0d) done=1;
8731 // Don't recompile stuff that's already compiled
8732 if(check_addr(start+i*4+4)) done=1;
8733 // Don't get too close to the limit
8734 if(i>MAXBLOCK/2) done=1;
8736 if(itype[i]==SYSCALL&&stop_after_jal) done=1;
8737 if(itype[i]==HLECALL||itype[i]==INTCALL) done=2;
8739 // Does the block continue due to a branch?
8742 if(ba[j]==start+i*4) done=j=0; // Branch into delay slot
8743 if(ba[j]==start+i*4+4) done=j=0;
8744 if(ba[j]==start+i*4+8) done=j=0;
8747 //assert(i<MAXBLOCK-1);
8748 if(start+i*4==pagelimit-4) done=1;
8749 assert(start+i*4<pagelimit);
8750 if (i==MAXBLOCK-1) done=1;
8751 // Stop if we're compiling junk
8752 if(itype[i]==NI&&opcode[i]==0x11) {
8753 done=stop_after_jal=1;
8754 printf("Disabled speculative precompilation\n");
8758 if(itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==RJUMP||itype[i-1]==FJUMP) {
8759 if(start+i*4==pagelimit) {
8765 /* Pass 2 - Register dependencies and branch targets */
8767 unneeded_registers(0,slen-1,0);
8769 /* Pass 3 - Register allocation */
8771 struct regstat current; // Current register allocations/status
8774 current.u=unneeded_reg[0];
8775 current.uu=unneeded_reg_upper[0];
8776 clear_all_regs(current.regmap);
8777 alloc_reg(¤t,0,CCREG);
8778 dirty_reg(¤t,CCREG);
8786 provisional_32bit();
8789 // First instruction is delay slot
8794 unneeded_reg_upper[0]=1;
8795 current.regmap[HOST_BTREG]=BTREG;
8803 for(hr=0;hr<HOST_REGS;hr++)
8805 // Is this really necessary?
8806 if(current.regmap[hr]==0) current.regmap[hr]=-1;
8812 if((opcode[i-2]&0x2f)==0x05) // BNE/BNEL
8814 if(rs1[i-2]==0||rs2[i-2]==0)
8817 current.is32|=1LL<<rs1[i-2];
8818 int hr=get_reg(current.regmap,rs1[i-2]|64);
8819 if(hr>=0) current.regmap[hr]=-1;
8822 current.is32|=1LL<<rs2[i-2];
8823 int hr=get_reg(current.regmap,rs2[i-2]|64);
8824 if(hr>=0) current.regmap[hr]=-1;
8830 // If something jumps here with 64-bit values
8831 // then promote those registers to 64 bits
8834 uint64_t temp_is32=current.is32;
8837 if(ba[j]==start+i*4)
8838 temp_is32&=branch_regs[j].is32;
8842 if(ba[j]==start+i*4)
8846 if(temp_is32!=current.is32) {
8847 //printf("dumping 32-bit regs (%x)\n",start+i*4);
8848 #ifndef DESTRUCTIVE_WRITEBACK
8851 for(hr=0;hr<HOST_REGS;hr++)
8853 int r=current.regmap[hr];
8856 if((current.dirty>>hr)&((current.is32&~temp_is32)>>r)&1) {
8858 //printf("restore %d\n",r);
8862 current.is32=temp_is32;
8869 memcpy(regmap_pre[i],current.regmap,sizeof(current.regmap));
8870 regs[i].wasconst=current.isconst;
8871 regs[i].was32=current.is32;
8872 regs[i].wasdirty=current.dirty;
8873 #if defined(DESTRUCTIVE_WRITEBACK) && !defined(FORCE32)
8874 // To change a dirty register from 32 to 64 bits, we must write
8875 // it out during the previous cycle (for branches, 2 cycles)
8876 if(i<slen-1&&bt[i+1]&&itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP)
8878 uint64_t temp_is32=current.is32;
8881 if(ba[j]==start+i*4+4)
8882 temp_is32&=branch_regs[j].is32;
8886 if(ba[j]==start+i*4+4)
8890 if(temp_is32!=current.is32) {
8891 //printf("pre-dumping 32-bit regs (%x)\n",start+i*4);
8892 for(hr=0;hr<HOST_REGS;hr++)
8894 int r=current.regmap[hr];
8897 if((current.dirty>>hr)&((current.is32&~temp_is32)>>(r&63))&1) {
8898 if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP)
8900 if(rs1[i]!=(r&63)&&rs2[i]!=(r&63))
8902 //printf("dump %d/r%d\n",hr,r);
8903 current.regmap[hr]=-1;
8904 if(get_reg(current.regmap,r|64)>=0)
8905 current.regmap[get_reg(current.regmap,r|64)]=-1;
8913 else if(i<slen-2&&bt[i+2]&&(source[i-1]>>16)!=0x1000&&(itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP))
8915 uint64_t temp_is32=current.is32;
8918 if(ba[j]==start+i*4+8)
8919 temp_is32&=branch_regs[j].is32;
8923 if(ba[j]==start+i*4+8)
8927 if(temp_is32!=current.is32) {
8928 //printf("pre-dumping 32-bit regs (%x)\n",start+i*4);
8929 for(hr=0;hr<HOST_REGS;hr++)
8931 int r=current.regmap[hr];
8934 if((current.dirty>>hr)&((current.is32&~temp_is32)>>(r&63))&1) {
8935 if(rs1[i]!=(r&63)&&rs2[i]!=(r&63)&&rs1[i+1]!=(r&63)&&rs2[i+1]!=(r&63))
8937 //printf("dump %d/r%d\n",hr,r);
8938 current.regmap[hr]=-1;
8939 if(get_reg(current.regmap,r|64)>=0)
8940 current.regmap[get_reg(current.regmap,r|64)]=-1;
8948 if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP) {
8950 current.u=unneeded_reg[i+1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
8951 current.uu=unneeded_reg_upper[i+1]&~((1LL<<us1[i])|(1LL<<us2[i]));
8952 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
8961 current.u=branch_unneeded_reg[i]&~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
8962 current.uu=branch_unneeded_reg_upper[i]&~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
8963 if((~current.uu>>rt1[i+1])&1) current.uu&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
8964 current.u&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
8965 current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
8968 } else { printf("oops, branch at end of block with no delay slot\n");exit(1); }
8972 ds=0; // Skip delay slot, already allocated as part of branch
8973 // ...but we need to alloc it in case something jumps here
8975 current.u=branch_unneeded_reg[i-1]&unneeded_reg[i+1];
8976 current.uu=branch_unneeded_reg_upper[i-1]&unneeded_reg_upper[i+1];
8978 current.u=branch_unneeded_reg[i-1];
8979 current.uu=branch_unneeded_reg_upper[i-1];
8981 current.u&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
8982 current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
8983 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
8986 struct regstat temp;
8987 memcpy(&temp,¤t,sizeof(current));
8988 temp.wasdirty=temp.dirty;
8989 temp.was32=temp.is32;
8990 // TODO: Take into account unconditional branches, as below
8991 delayslot_alloc(&temp,i);
8992 memcpy(regs[i].regmap,temp.regmap,sizeof(temp.regmap));
8993 regs[i].wasdirty=temp.wasdirty;
8994 regs[i].was32=temp.was32;
8995 regs[i].dirty=temp.dirty;
8996 regs[i].is32=temp.is32;
9000 // Create entry (branch target) regmap
9001 for(hr=0;hr<HOST_REGS;hr++)
9003 int r=temp.regmap[hr];
9005 if(r!=regmap_pre[i][hr]) {
9006 regs[i].regmap_entry[hr]=-1;
9011 if((current.u>>r)&1) {
9012 regs[i].regmap_entry[hr]=-1;
9013 regs[i].regmap[hr]=-1;
9014 //Don't clear regs in the delay slot as the branch might need them
9015 //current.regmap[hr]=-1;
9017 regs[i].regmap_entry[hr]=r;
9020 if((current.uu>>(r&63))&1) {
9021 regs[i].regmap_entry[hr]=-1;
9022 regs[i].regmap[hr]=-1;
9023 //Don't clear regs in the delay slot as the branch might need them
9024 //current.regmap[hr]=-1;
9026 regs[i].regmap_entry[hr]=r;
9030 // First instruction expects CCREG to be allocated
9031 if(i==0&&hr==HOST_CCREG)
9032 regs[i].regmap_entry[hr]=CCREG;
9034 regs[i].regmap_entry[hr]=-1;
9038 else { // Not delay slot
9041 //current.isconst=0; // DEBUG
9042 //current.wasconst=0; // DEBUG
9043 //regs[i].wasconst=0; // DEBUG
9044 clear_const(¤t,rt1[i]);
9045 alloc_cc(¤t,i);
9046 dirty_reg(¤t,CCREG);
9048 alloc_reg(¤t,i,31);
9049 dirty_reg(¤t,31);
9050 //assert(rs1[i+1]!=31&&rs2[i+1]!=31);
9051 //assert(rt1[i+1]!=rt1[i]);
9053 alloc_reg(¤t,i,PTEMP);
9055 //current.is32|=1LL<<rt1[i];
9058 delayslot_alloc(¤t,i+1);
9059 //current.isconst=0; // DEBUG
9061 //printf("i=%d, isconst=%x\n",i,current.isconst);
9064 //current.isconst=0;
9065 //current.wasconst=0;
9066 //regs[i].wasconst=0;
9067 clear_const(¤t,rs1[i]);
9068 clear_const(¤t,rt1[i]);
9069 alloc_cc(¤t,i);
9070 dirty_reg(¤t,CCREG);
9071 if(rs1[i]!=rt1[i+1]&&rs1[i]!=rt2[i+1]) {
9072 alloc_reg(¤t,i,rs1[i]);
9074 alloc_reg(¤t,i,rt1[i]);
9075 dirty_reg(¤t,rt1[i]);
9076 assert(rs1[i+1]!=rt1[i]&&rs2[i+1]!=rt1[i]);
9077 assert(rt1[i+1]!=rt1[i]);
9079 alloc_reg(¤t,i,PTEMP);
9083 if(rs1[i]==31) { // JALR
9084 alloc_reg(¤t,i,RHASH);
9085 #ifndef HOST_IMM_ADDR32
9086 alloc_reg(¤t,i,RHTBL);
9090 delayslot_alloc(¤t,i+1);
9092 // The delay slot overwrites our source register,
9093 // allocate a temporary register to hold the old value.
9097 delayslot_alloc(¤t,i+1);
9099 alloc_reg(¤t,i,RTEMP);
9101 //current.isconst=0; // DEBUG
9106 //current.isconst=0;
9107 //current.wasconst=0;
9108 //regs[i].wasconst=0;
9109 clear_const(¤t,rs1[i]);
9110 clear_const(¤t,rs2[i]);
9111 if((opcode[i]&0x3E)==4) // BEQ/BNE
9113 alloc_cc(¤t,i);
9114 dirty_reg(¤t,CCREG);
9115 if(rs1[i]) alloc_reg(¤t,i,rs1[i]);
9116 if(rs2[i]) alloc_reg(¤t,i,rs2[i]);
9117 if(!((current.is32>>rs1[i])&(current.is32>>rs2[i])&1))
9119 if(rs1[i]) alloc_reg64(¤t,i,rs1[i]);
9120 if(rs2[i]) alloc_reg64(¤t,i,rs2[i]);
9122 if((rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]))||
9123 (rs2[i]&&(rs2[i]==rt1[i+1]||rs2[i]==rt2[i+1]))) {
9124 // The delay slot overwrites one of our conditions.
9125 // Allocate the branch condition registers instead.
9129 if(rs1[i]) alloc_reg(¤t,i,rs1[i]);
9130 if(rs2[i]) alloc_reg(¤t,i,rs2[i]);
9131 if(!((current.is32>>rs1[i])&(current.is32>>rs2[i])&1))
9133 if(rs1[i]) alloc_reg64(¤t,i,rs1[i]);
9134 if(rs2[i]) alloc_reg64(¤t,i,rs2[i]);
9140 delayslot_alloc(¤t,i+1);
9144 if((opcode[i]&0x3E)==6) // BLEZ/BGTZ
9146 alloc_cc(¤t,i);
9147 dirty_reg(¤t,CCREG);
9148 alloc_reg(¤t,i,rs1[i]);
9149 if(!(current.is32>>rs1[i]&1))
9151 alloc_reg64(¤t,i,rs1[i]);
9153 if(rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1])) {
9154 // The delay slot overwrites one of our conditions.
9155 // Allocate the branch condition registers instead.
9159 if(rs1[i]) alloc_reg(¤t,i,rs1[i]);
9160 if(!((current.is32>>rs1[i])&1))
9162 if(rs1[i]) alloc_reg64(¤t,i,rs1[i]);
9168 delayslot_alloc(¤t,i+1);
9172 // Don't alloc the delay slot yet because we might not execute it
9173 if((opcode[i]&0x3E)==0x14) // BEQL/BNEL
9178 alloc_cc(¤t,i);
9179 dirty_reg(¤t,CCREG);
9180 alloc_reg(¤t,i,rs1[i]);
9181 alloc_reg(¤t,i,rs2[i]);
9182 if(!((current.is32>>rs1[i])&(current.is32>>rs2[i])&1))
9184 alloc_reg64(¤t,i,rs1[i]);
9185 alloc_reg64(¤t,i,rs2[i]);
9189 if((opcode[i]&0x3E)==0x16) // BLEZL/BGTZL
9194 alloc_cc(¤t,i);
9195 dirty_reg(¤t,CCREG);
9196 alloc_reg(¤t,i,rs1[i]);
9197 if(!(current.is32>>rs1[i]&1))
9199 alloc_reg64(¤t,i,rs1[i]);
9203 //current.isconst=0;
9206 //current.isconst=0;
9207 //current.wasconst=0;
9208 //regs[i].wasconst=0;
9209 clear_const(¤t,rs1[i]);
9210 clear_const(¤t,rt1[i]);
9211 //if((opcode2[i]&0x1E)==0x0) // BLTZ/BGEZ
9212 if((opcode2[i]&0x0E)==0x0) // BLTZ/BGEZ
9214 alloc_cc(¤t,i);
9215 dirty_reg(¤t,CCREG);
9216 alloc_reg(¤t,i,rs1[i]);
9217 if(!(current.is32>>rs1[i]&1))
9219 alloc_reg64(¤t,i,rs1[i]);
9221 if (rt1[i]==31) { // BLTZAL/BGEZAL
9222 alloc_reg(¤t,i,31);
9223 dirty_reg(¤t,31);
9224 //#ifdef REG_PREFETCH
9225 //alloc_reg(¤t,i,PTEMP);
9227 //current.is32|=1LL<<rt1[i];
9229 if((rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1])) // The delay slot overwrites the branch condition.
9230 ||(rt1[i]==31&&(rs1[i+1]==31||rs2[i+1]==31||rt1[i+1]==31||rt2[i+1]==31))) { // DS touches $ra
9231 // Allocate the branch condition registers instead.
9235 if(rs1[i]) alloc_reg(¤t,i,rs1[i]);
9236 if(!((current.is32>>rs1[i])&1))
9238 if(rs1[i]) alloc_reg64(¤t,i,rs1[i]);
9244 delayslot_alloc(¤t,i+1);
9248 // Don't alloc the delay slot yet because we might not execute it
9249 if((opcode2[i]&0x1E)==0x2) // BLTZL/BGEZL
9254 alloc_cc(¤t,i);
9255 dirty_reg(¤t,CCREG);
9256 alloc_reg(¤t,i,rs1[i]);
9257 if(!(current.is32>>rs1[i]&1))
9259 alloc_reg64(¤t,i,rs1[i]);
9263 //current.isconst=0;
9269 if(likely[i]==0) // BC1F/BC1T
9271 // TODO: Theoretically we can run out of registers here on x86.
9272 // The delay slot can allocate up to six, and we need to check
9273 // CSREG before executing the delay slot. Possibly we can drop
9274 // the cycle count and then reload it after checking that the
9275 // FPU is in a usable state, or don't do out-of-order execution.
9276 alloc_cc(¤t,i);
9277 dirty_reg(¤t,CCREG);
9278 alloc_reg(¤t,i,FSREG);
9279 alloc_reg(¤t,i,CSREG);
9280 if(itype[i+1]==FCOMP) {
9281 // The delay slot overwrites the branch condition.
9282 // Allocate the branch condition registers instead.
9283 alloc_cc(¤t,i);
9284 dirty_reg(¤t,CCREG);
9285 alloc_reg(¤t,i,CSREG);
9286 alloc_reg(¤t,i,FSREG);
9290 delayslot_alloc(¤t,i+1);
9291 alloc_reg(¤t,i+1,CSREG);
9295 // Don't alloc the delay slot yet because we might not execute it
9296 if(likely[i]) // BC1FL/BC1TL
9298 alloc_cc(¤t,i);
9299 dirty_reg(¤t,CCREG);
9300 alloc_reg(¤t,i,CSREG);
9301 alloc_reg(¤t,i,FSREG);
9307 imm16_alloc(¤t,i);
9311 load_alloc(¤t,i);
9315 store_alloc(¤t,i);
9318 alu_alloc(¤t,i);
9321 shift_alloc(¤t,i);
9324 multdiv_alloc(¤t,i);
9327 shiftimm_alloc(¤t,i);
9330 mov_alloc(¤t,i);
9333 cop0_alloc(¤t,i);
9337 cop1_alloc(¤t,i);
9340 c1ls_alloc(¤t,i);
9343 c2ls_alloc(¤t,i);
9346 c2op_alloc(¤t,i);
9349 fconv_alloc(¤t,i);
9352 float_alloc(¤t,i);
9355 fcomp_alloc(¤t,i);
9360 syscall_alloc(¤t,i);
9363 pagespan_alloc(¤t,i);
9367 // Drop the upper half of registers that have become 32-bit
9368 current.uu|=current.is32&((1LL<<rt1[i])|(1LL<<rt2[i]));
9369 if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP) {
9370 current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
9371 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9374 current.uu|=current.is32&((1LL<<rt1[i+1])|(1LL<<rt2[i+1]));
9375 current.uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
9376 if((~current.uu>>rt1[i+1])&1) current.uu&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
9377 current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
9381 // Create entry (branch target) regmap
9382 for(hr=0;hr<HOST_REGS;hr++)
9385 r=current.regmap[hr];
9387 if(r!=regmap_pre[i][hr]) {
9388 // TODO: delay slot (?)
9389 or=get_reg(regmap_pre[i],r); // Get old mapping for this register
9390 if(or<0||(r&63)>=TEMPREG){
9391 regs[i].regmap_entry[hr]=-1;
9395 // Just move it to a different register
9396 regs[i].regmap_entry[hr]=r;
9397 // If it was dirty before, it's still dirty
9398 if((regs[i].wasdirty>>or)&1) dirty_reg(¤t,r&63);
9405 regs[i].regmap_entry[hr]=0;
9409 if((current.u>>r)&1) {
9410 regs[i].regmap_entry[hr]=-1;
9411 //regs[i].regmap[hr]=-1;
9412 current.regmap[hr]=-1;
9414 regs[i].regmap_entry[hr]=r;
9417 if((current.uu>>(r&63))&1) {
9418 regs[i].regmap_entry[hr]=-1;
9419 //regs[i].regmap[hr]=-1;
9420 current.regmap[hr]=-1;
9422 regs[i].regmap_entry[hr]=r;
9426 // Branches expect CCREG to be allocated at the target
9427 if(regmap_pre[i][hr]==CCREG)
9428 regs[i].regmap_entry[hr]=CCREG;
9430 regs[i].regmap_entry[hr]=-1;
9433 memcpy(regs[i].regmap,current.regmap,sizeof(current.regmap));
9435 /* Branch post-alloc */
9438 current.was32=current.is32;
9439 current.wasdirty=current.dirty;
9440 switch(itype[i-1]) {
9442 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9443 branch_regs[i-1].isconst=0;
9444 branch_regs[i-1].wasconst=0;
9445 branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1]));
9446 branch_regs[i-1].uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i-1])|(1LL<<us2[i-1]));
9447 alloc_cc(&branch_regs[i-1],i-1);
9448 dirty_reg(&branch_regs[i-1],CCREG);
9449 if(rt1[i-1]==31) { // JAL
9450 alloc_reg(&branch_regs[i-1],i-1,31);
9451 dirty_reg(&branch_regs[i-1],31);
9452 branch_regs[i-1].is32|=1LL<<31;
9454 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9455 memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9458 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9459 branch_regs[i-1].isconst=0;
9460 branch_regs[i-1].wasconst=0;
9461 branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1]));
9462 branch_regs[i-1].uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i-1])|(1LL<<us2[i-1]));
9463 alloc_cc(&branch_regs[i-1],i-1);
9464 dirty_reg(&branch_regs[i-1],CCREG);
9465 alloc_reg(&branch_regs[i-1],i-1,rs1[i-1]);
9466 if(rt1[i-1]!=0) { // JALR
9467 alloc_reg(&branch_regs[i-1],i-1,rt1[i-1]);
9468 dirty_reg(&branch_regs[i-1],rt1[i-1]);
9469 branch_regs[i-1].is32|=1LL<<rt1[i-1];
9472 if(rs1[i-1]==31) { // JALR
9473 alloc_reg(&branch_regs[i-1],i-1,RHASH);
9474 #ifndef HOST_IMM_ADDR32
9475 alloc_reg(&branch_regs[i-1],i-1,RHTBL);
9479 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9480 memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9483 if((opcode[i-1]&0x3E)==4) // BEQ/BNE
9485 alloc_cc(¤t,i-1);
9486 dirty_reg(¤t,CCREG);
9487 if((rs1[i-1]&&(rs1[i-1]==rt1[i]||rs1[i-1]==rt2[i]))||
9488 (rs2[i-1]&&(rs2[i-1]==rt1[i]||rs2[i-1]==rt2[i]))) {
9489 // The delay slot overwrote one of our conditions
9490 // Delay slot goes after the test (in order)
9491 current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
9492 current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i]));
9493 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9496 delayslot_alloc(¤t,i);
9501 current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1]));
9502 current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i-1])|(1LL<<us2[i-1]));
9503 // Alloc the branch condition registers
9504 if(rs1[i-1]) alloc_reg(¤t,i-1,rs1[i-1]);
9505 if(rs2[i-1]) alloc_reg(¤t,i-1,rs2[i-1]);
9506 if(!((current.is32>>rs1[i-1])&(current.is32>>rs2[i-1])&1))
9508 if(rs1[i-1]) alloc_reg64(¤t,i-1,rs1[i-1]);
9509 if(rs2[i-1]) alloc_reg64(¤t,i-1,rs2[i-1]);
9512 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9513 branch_regs[i-1].isconst=0;
9514 branch_regs[i-1].wasconst=0;
9515 memcpy(&branch_regs[i-1].regmap_entry,¤t.regmap,sizeof(current.regmap));
9516 memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9519 if((opcode[i-1]&0x3E)==6) // BLEZ/BGTZ
9521 alloc_cc(¤t,i-1);
9522 dirty_reg(¤t,CCREG);
9523 if(rs1[i-1]==rt1[i]||rs1[i-1]==rt2[i]) {
9524 // The delay slot overwrote the branch condition
9525 // Delay slot goes after the test (in order)
9526 current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
9527 current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i]));
9528 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9531 delayslot_alloc(¤t,i);
9536 current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]);
9537 current.uu=branch_unneeded_reg_upper[i-1]&~(1LL<<us1[i-1]);
9538 // Alloc the branch condition register
9539 alloc_reg(¤t,i-1,rs1[i-1]);
9540 if(!(current.is32>>rs1[i-1]&1))
9542 alloc_reg64(¤t,i-1,rs1[i-1]);
9545 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9546 branch_regs[i-1].isconst=0;
9547 branch_regs[i-1].wasconst=0;
9548 memcpy(&branch_regs[i-1].regmap_entry,¤t.regmap,sizeof(current.regmap));
9549 memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9552 // Alloc the delay slot in case the branch is taken
9553 if((opcode[i-1]&0x3E)==0x14) // BEQL/BNEL
9555 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9556 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9557 branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9558 if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9559 alloc_cc(&branch_regs[i-1],i);
9560 dirty_reg(&branch_regs[i-1],CCREG);
9561 delayslot_alloc(&branch_regs[i-1],i);
9562 branch_regs[i-1].isconst=0;
9563 alloc_reg(¤t,i,CCREG); // Not taken path
9564 dirty_reg(¤t,CCREG);
9565 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9568 if((opcode[i-1]&0x3E)==0x16) // BLEZL/BGTZL
9570 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9571 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9572 branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9573 if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9574 alloc_cc(&branch_regs[i-1],i);
9575 dirty_reg(&branch_regs[i-1],CCREG);
9576 delayslot_alloc(&branch_regs[i-1],i);
9577 branch_regs[i-1].isconst=0;
9578 alloc_reg(¤t,i,CCREG); // Not taken path
9579 dirty_reg(¤t,CCREG);
9580 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9584 //if((opcode2[i-1]&0x1E)==0) // BLTZ/BGEZ
9585 if((opcode2[i-1]&0x0E)==0) // BLTZ/BGEZ
9587 alloc_cc(¤t,i-1);
9588 dirty_reg(¤t,CCREG);
9589 if(rs1[i-1]==rt1[i]||rs1[i-1]==rt2[i]) {
9590 // The delay slot overwrote the branch condition
9591 // Delay slot goes after the test (in order)
9592 current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
9593 current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i]));
9594 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9597 delayslot_alloc(¤t,i);
9602 current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]);
9603 current.uu=branch_unneeded_reg_upper[i-1]&~(1LL<<us1[i-1]);
9604 // Alloc the branch condition register
9605 alloc_reg(¤t,i-1,rs1[i-1]);
9606 if(!(current.is32>>rs1[i-1]&1))
9608 alloc_reg64(¤t,i-1,rs1[i-1]);
9611 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9612 branch_regs[i-1].isconst=0;
9613 branch_regs[i-1].wasconst=0;
9614 memcpy(&branch_regs[i-1].regmap_entry,¤t.regmap,sizeof(current.regmap));
9615 memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9618 // Alloc the delay slot in case the branch is taken
9619 if((opcode2[i-1]&0x1E)==2) // BLTZL/BGEZL
9621 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9622 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9623 branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9624 if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9625 alloc_cc(&branch_regs[i-1],i);
9626 dirty_reg(&branch_regs[i-1],CCREG);
9627 delayslot_alloc(&branch_regs[i-1],i);
9628 branch_regs[i-1].isconst=0;
9629 alloc_reg(¤t,i,CCREG); // Not taken path
9630 dirty_reg(¤t,CCREG);
9631 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9633 // FIXME: BLTZAL/BGEZAL
9634 if(opcode2[i-1]&0x10) { // BxxZAL
9635 alloc_reg(&branch_regs[i-1],i-1,31);
9636 dirty_reg(&branch_regs[i-1],31);
9637 branch_regs[i-1].is32|=1LL<<31;
9641 if(likely[i-1]==0) // BC1F/BC1T
9643 alloc_cc(¤t,i-1);
9644 dirty_reg(¤t,CCREG);
9645 if(itype[i]==FCOMP) {
9646 // The delay slot overwrote the branch condition
9647 // Delay slot goes after the test (in order)
9648 delayslot_alloc(¤t,i);
9653 current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]);
9654 current.uu=branch_unneeded_reg_upper[i-1]&~(1LL<<us1[i-1]);
9655 // Alloc the branch condition register
9656 alloc_reg(¤t,i-1,FSREG);
9658 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9659 memcpy(&branch_regs[i-1].regmap_entry,¤t.regmap,sizeof(current.regmap));
9663 // Alloc the delay slot in case the branch is taken
9664 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9665 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9666 branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9667 if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9668 alloc_cc(&branch_regs[i-1],i);
9669 dirty_reg(&branch_regs[i-1],CCREG);
9670 delayslot_alloc(&branch_regs[i-1],i);
9671 branch_regs[i-1].isconst=0;
9672 alloc_reg(¤t,i,CCREG); // Not taken path
9673 dirty_reg(¤t,CCREG);
9674 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9679 if(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)
9681 if(rt1[i-1]==31) // JAL/JALR
9683 // Subroutine call will return here, don't alloc any registers
9686 clear_all_regs(current.regmap);
9687 alloc_reg(¤t,i,CCREG);
9688 dirty_reg(¤t,CCREG);
9692 // Internal branch will jump here, match registers to caller
9693 current.is32=0x3FFFFFFFFLL;
9695 clear_all_regs(current.regmap);
9696 alloc_reg(¤t,i,CCREG);
9697 dirty_reg(¤t,CCREG);
9700 if(ba[j]==start+i*4+4) {
9701 memcpy(current.regmap,branch_regs[j].regmap,sizeof(current.regmap));
9702 current.is32=branch_regs[j].is32;
9703 current.dirty=branch_regs[j].dirty;
9708 if(ba[j]==start+i*4+4) {
9709 for(hr=0;hr<HOST_REGS;hr++) {
9710 if(current.regmap[hr]!=branch_regs[j].regmap[hr]) {
9711 current.regmap[hr]=-1;
9713 current.is32&=branch_regs[j].is32;
9714 current.dirty&=branch_regs[j].dirty;
9723 // Count cycles in between branches
9725 if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP||itype[i]==SYSCALL||itype[i]==HLECALL))
9730 else if(/*itype[i]==LOAD||*/itype[i]==STORE||itype[i]==C1LS) // load causes weird timing issues
9732 cc+=2; // 2 cycle penalty (after CLOCK_DIVIDER)
9734 else if(itype[i]==C2LS)
9744 flush_dirty_uppers(¤t);
9746 regs[i].is32=current.is32;
9747 regs[i].dirty=current.dirty;
9748 regs[i].isconst=current.isconst;
9749 memcpy(constmap[i],current.constmap,sizeof(current.constmap));
9751 for(hr=0;hr<HOST_REGS;hr++) {
9752 if(hr!=EXCLUDE_REG&®s[i].regmap[hr]>=0) {
9753 if(regmap_pre[i][hr]!=regs[i].regmap[hr]) {
9754 regs[i].wasconst&=~(1<<hr);
9758 if(current.regmap[HOST_BTREG]==BTREG) current.regmap[HOST_BTREG]=-1;
9761 /* Pass 4 - Cull unused host registers */
9765 for (i=slen-1;i>=0;i--)
9768 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
9770 if(ba[i]<start || ba[i]>=(start+slen*4))
9772 // Branch out of this block, don't need anything
9778 // Need whatever matches the target
9780 int t=(ba[i]-start)>>2;
9781 for(hr=0;hr<HOST_REGS;hr++)
9783 if(regs[i].regmap_entry[hr]>=0) {
9784 if(regs[i].regmap_entry[hr]==regs[t].regmap_entry[hr]) nr|=1<<hr;
9788 // Conditional branch may need registers for following instructions
9789 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
9792 nr|=needed_reg[i+2];
9793 for(hr=0;hr<HOST_REGS;hr++)
9795 if(regmap_pre[i+2][hr]>=0&&get_reg(regs[i+2].regmap_entry,regmap_pre[i+2][hr])<0) nr&=~(1<<hr);
9796 //if((regmap_entry[i+2][hr])>=0) if(!((nr>>hr)&1)) printf("%x-bogus(%d=%d)\n",start+i*4,hr,regmap_entry[i+2][hr]);
9800 // Don't need stuff which is overwritten
9801 //if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr);
9802 //if(regs[i].regmap[hr]<0) nr&=~(1<<hr);
9803 // Merge in delay slot
9804 for(hr=0;hr<HOST_REGS;hr++)
9807 // These are overwritten unless the branch is "likely"
9808 // and the delay slot is nullified if not taken
9809 if(rt1[i+1]&&rt1[i+1]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9810 if(rt2[i+1]&&rt2[i+1]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9812 if(us1[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9813 if(us2[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9814 if(rs1[i+1]==regmap_pre[i][hr]) nr|=1<<hr;
9815 if(rs2[i+1]==regmap_pre[i][hr]) nr|=1<<hr;
9816 if(us1[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9817 if(us2[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9818 if(rs1[i+1]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9819 if(rs2[i+1]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9820 if(dep1[i+1]&&!((unneeded_reg_upper[i]>>dep1[i+1])&1)) {
9821 if(dep1[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9822 if(dep2[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9824 if(dep2[i+1]&&!((unneeded_reg_upper[i]>>dep2[i+1])&1)) {
9825 if(dep1[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9826 if(dep2[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9828 if(itype[i+1]==STORE || itype[i+1]==STORELR || (opcode[i+1]&0x3b)==0x39 || (opcode[i+1]&0x3b)==0x3a) {
9829 if(regmap_pre[i][hr]==INVCP) nr|=1<<hr;
9830 if(regs[i].regmap_entry[hr]==INVCP) nr|=1<<hr;
9834 else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
9836 // SYSCALL instruction (software interrupt)
9839 else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
9841 // ERET instruction (return from interrupt)
9847 for(hr=0;hr<HOST_REGS;hr++) {
9848 if(regmap_pre[i+1][hr]>=0&&get_reg(regs[i+1].regmap_entry,regmap_pre[i+1][hr])<0) nr&=~(1<<hr);
9849 if(regs[i].regmap[hr]!=regmap_pre[i+1][hr]) nr&=~(1<<hr);
9850 if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr);
9851 if(regs[i].regmap[hr]<0) nr&=~(1<<hr);
9855 for(hr=0;hr<HOST_REGS;hr++)
9857 // Overwritten registers are not needed
9858 if(rt1[i]&&rt1[i]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9859 if(rt2[i]&&rt2[i]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9860 if(FTEMP==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9861 // Source registers are needed
9862 if(us1[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9863 if(us2[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9864 if(rs1[i]==regmap_pre[i][hr]) nr|=1<<hr;
9865 if(rs2[i]==regmap_pre[i][hr]) nr|=1<<hr;
9866 if(us1[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9867 if(us2[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9868 if(rs1[i]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9869 if(rs2[i]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9870 if(dep1[i]&&!((unneeded_reg_upper[i]>>dep1[i])&1)) {
9871 if(dep1[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9872 if(dep1[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9874 if(dep2[i]&&!((unneeded_reg_upper[i]>>dep2[i])&1)) {
9875 if(dep2[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9876 if(dep2[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9878 if(itype[i]==STORE || itype[i]==STORELR || (opcode[i]&0x3b)==0x39 || (opcode[i]&0x3b)==0x3a) {
9879 if(regmap_pre[i][hr]==INVCP) nr|=1<<hr;
9880 if(regs[i].regmap_entry[hr]==INVCP) nr|=1<<hr;
9882 // Don't store a register immediately after writing it,
9883 // may prevent dual-issue.
9884 // But do so if this is a branch target, otherwise we
9885 // might have to load the register before the branch.
9886 if(i>0&&!bt[i]&&((regs[i].wasdirty>>hr)&1)) {
9887 if((regmap_pre[i][hr]>0&®map_pre[i][hr]<64&&!((unneeded_reg[i]>>regmap_pre[i][hr])&1)) ||
9888 (regmap_pre[i][hr]>64&&!((unneeded_reg_upper[i]>>(regmap_pre[i][hr]&63))&1)) ) {
9889 if(rt1[i-1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9890 if(rt2[i-1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9892 if((regs[i].regmap_entry[hr]>0&®s[i].regmap_entry[hr]<64&&!((unneeded_reg[i]>>regs[i].regmap_entry[hr])&1)) ||
9893 (regs[i].regmap_entry[hr]>64&&!((unneeded_reg_upper[i]>>(regs[i].regmap_entry[hr]&63))&1)) ) {
9894 if(rt1[i-1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9895 if(rt2[i-1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9899 // Cycle count is needed at branches. Assume it is needed at the target too.
9900 if(i==0||bt[i]||itype[i]==CJUMP||itype[i]==FJUMP||itype[i]==SPAN) {
9901 if(regmap_pre[i][HOST_CCREG]==CCREG) nr|=1<<HOST_CCREG;
9902 if(regs[i].regmap_entry[HOST_CCREG]==CCREG) nr|=1<<HOST_CCREG;
9907 // Deallocate unneeded registers
9908 for(hr=0;hr<HOST_REGS;hr++)
9911 if(regs[i].regmap_entry[hr]!=CCREG) regs[i].regmap_entry[hr]=-1;
9912 if((regs[i].regmap[hr]&63)!=rs1[i] && (regs[i].regmap[hr]&63)!=rs2[i] &&
9913 (regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] &&
9914 (regs[i].regmap[hr]&63)!=PTEMP && (regs[i].regmap[hr]&63)!=CCREG)
9916 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
9919 regs[i].regmap[hr]=-1;
9920 regs[i].isconst&=~(1<<hr);
9922 regmap_pre[i+2][hr]=-1;
9923 regs[i+2].wasconst&=~(1<<hr);
9928 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
9930 int d1=0,d2=0,map=0,temp=0;
9931 if(get_reg(regs[i].regmap,rt1[i+1]|64)>=0||get_reg(branch_regs[i].regmap,rt1[i+1]|64)>=0)
9937 if(itype[i+1]==LOAD || itype[i+1]==LOADLR ||
9938 itype[i+1]==STORE || itype[i+1]==STORELR ||
9939 itype[i+1]==C1LS || itype[i+1]==C2LS)
9942 if(itype[i+1]==STORE || itype[i+1]==STORELR ||
9943 (opcode[i+1]&0x3b)==0x39 || (opcode[i+1]&0x3b)==0x3a) { // SWC1/SDC1 || SWC2/SDC2
9946 if(itype[i+1]==LOADLR || itype[i+1]==STORELR ||
9947 itype[i+1]==C1LS || itype[i+1]==C2LS)
9949 if((regs[i].regmap[hr]&63)!=rs1[i] && (regs[i].regmap[hr]&63)!=rs2[i] &&
9950 (regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] &&
9951 (regs[i].regmap[hr]&63)!=rt1[i+1] && (regs[i].regmap[hr]&63)!=rt2[i+1] &&
9952 (regs[i].regmap[hr]^64)!=us1[i+1] && (regs[i].regmap[hr]^64)!=us2[i+1] &&
9953 (regs[i].regmap[hr]^64)!=d1 && (regs[i].regmap[hr]^64)!=d2 &&
9954 regs[i].regmap[hr]!=rs1[i+1] && regs[i].regmap[hr]!=rs2[i+1] &&
9955 (regs[i].regmap[hr]&63)!=temp && regs[i].regmap[hr]!=PTEMP &&
9956 regs[i].regmap[hr]!=RHASH && regs[i].regmap[hr]!=RHTBL &&
9957 regs[i].regmap[hr]!=RTEMP && regs[i].regmap[hr]!=CCREG &&
9958 regs[i].regmap[hr]!=map )
9960 regs[i].regmap[hr]=-1;
9961 regs[i].isconst&=~(1<<hr);
9962 if((branch_regs[i].regmap[hr]&63)!=rs1[i] && (branch_regs[i].regmap[hr]&63)!=rs2[i] &&
9963 (branch_regs[i].regmap[hr]&63)!=rt1[i] && (branch_regs[i].regmap[hr]&63)!=rt2[i] &&
9964 (branch_regs[i].regmap[hr]&63)!=rt1[i+1] && (branch_regs[i].regmap[hr]&63)!=rt2[i+1] &&
9965 (branch_regs[i].regmap[hr]^64)!=us1[i+1] && (branch_regs[i].regmap[hr]^64)!=us2[i+1] &&
9966 (branch_regs[i].regmap[hr]^64)!=d1 && (branch_regs[i].regmap[hr]^64)!=d2 &&
9967 branch_regs[i].regmap[hr]!=rs1[i+1] && branch_regs[i].regmap[hr]!=rs2[i+1] &&
9968 (branch_regs[i].regmap[hr]&63)!=temp && branch_regs[i].regmap[hr]!=PTEMP &&
9969 branch_regs[i].regmap[hr]!=RHASH && branch_regs[i].regmap[hr]!=RHTBL &&
9970 branch_regs[i].regmap[hr]!=RTEMP && branch_regs[i].regmap[hr]!=CCREG &&
9971 branch_regs[i].regmap[hr]!=map)
9973 branch_regs[i].regmap[hr]=-1;
9974 branch_regs[i].regmap_entry[hr]=-1;
9975 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
9977 if(!likely[i]&&i<slen-2) {
9978 regmap_pre[i+2][hr]=-1;
9979 regs[i+2].wasconst&=~(1<<hr);
9990 int d1=0,d2=0,map=-1,temp=-1;
9991 if(get_reg(regs[i].regmap,rt1[i]|64)>=0)
9997 if(itype[i]==LOAD || itype[i]==LOADLR ||
9998 itype[i]==STORE || itype[i]==STORELR ||
9999 itype[i]==C1LS || itype[i]==C2LS)
10001 } else if(itype[i]==STORE || itype[i]==STORELR ||
10002 (opcode[i]&0x3b)==0x39 || (opcode[i]&0x3b)==0x3a) { // SWC1/SDC1 || SWC2/SDC2
10005 if(itype[i]==LOADLR || itype[i]==STORELR ||
10006 itype[i]==C1LS || itype[i]==C2LS)
10008 if((regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] &&
10009 (regs[i].regmap[hr]^64)!=us1[i] && (regs[i].regmap[hr]^64)!=us2[i] &&
10010 (regs[i].regmap[hr]^64)!=d1 && (regs[i].regmap[hr]^64)!=d2 &&
10011 regs[i].regmap[hr]!=rs1[i] && regs[i].regmap[hr]!=rs2[i] &&
10012 (regs[i].regmap[hr]&63)!=temp && regs[i].regmap[hr]!=map &&
10013 (itype[i]!=SPAN||regs[i].regmap[hr]!=CCREG))
10015 if(i<slen-1&&!is_ds[i]) {
10016 if(regmap_pre[i+1][hr]!=-1 || regs[i].regmap[hr]!=-1)
10017 if(regmap_pre[i+1][hr]!=regs[i].regmap[hr])
10018 if(regs[i].regmap[hr]<64||!((regs[i].was32>>(regs[i].regmap[hr]&63))&1))
10020 printf("fail: %x (%d %d!=%d)\n",start+i*4,hr,regmap_pre[i+1][hr],regs[i].regmap[hr]);
10021 assert(regmap_pre[i+1][hr]==regs[i].regmap[hr]);
10023 regmap_pre[i+1][hr]=-1;
10024 if(regs[i+1].regmap_entry[hr]==CCREG) regs[i+1].regmap_entry[hr]=-1;
10025 regs[i+1].wasconst&=~(1<<hr);
10027 regs[i].regmap[hr]=-1;
10028 regs[i].isconst&=~(1<<hr);
10036 /* Pass 5 - Pre-allocate registers */
10038 // If a register is allocated during a loop, try to allocate it for the
10039 // entire loop, if possible. This avoids loading/storing registers
10040 // inside of the loop.
10042 signed char f_regmap[HOST_REGS];
10043 clear_all_regs(f_regmap);
10044 for(i=0;i<slen-1;i++)
10046 if(itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
10048 if(ba[i]>=start && ba[i]<(start+i*4))
10049 if(itype[i+1]==NOP||itype[i+1]==MOV||itype[i+1]==ALU
10050 ||itype[i+1]==SHIFTIMM||itype[i+1]==IMM16||itype[i+1]==LOAD
10051 ||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS
10052 ||itype[i+1]==SHIFT||itype[i+1]==COP1||itype[i+1]==FLOAT
10053 ||itype[i+1]==FCOMP||itype[i+1]==FCONV
10054 ||itype[i+1]==COP2||itype[i+1]==C2LS||itype[i+1]==C2OP)
10056 int t=(ba[i]-start)>>2;
10057 if(t>0&&(itype[t-1]!=UJUMP&&itype[t-1]!=RJUMP&&itype[t-1]!=CJUMP&&itype[t-1]!=SJUMP&&itype[t-1]!=FJUMP)) // loop_preload can't handle jumps into delay slots
10058 if(t<2||(itype[t-2]!=UJUMP&&itype[t-2]!=RJUMP)||rt1[t-2]!=31) // call/ret assumes no registers allocated
10059 for(hr=0;hr<HOST_REGS;hr++)
10061 if(regs[i].regmap[hr]>64) {
10062 if(!((regs[i].dirty>>hr)&1))
10063 f_regmap[hr]=regs[i].regmap[hr];
10064 else f_regmap[hr]=-1;
10066 else if(regs[i].regmap[hr]>=0) {
10067 if(f_regmap[hr]!=regs[i].regmap[hr]) {
10068 // dealloc old register
10070 for(n=0;n<HOST_REGS;n++)
10072 if(f_regmap[n]==regs[i].regmap[hr]) {f_regmap[n]=-1;}
10074 // and alloc new one
10075 f_regmap[hr]=regs[i].regmap[hr];
10078 if(branch_regs[i].regmap[hr]>64) {
10079 if(!((branch_regs[i].dirty>>hr)&1))
10080 f_regmap[hr]=branch_regs[i].regmap[hr];
10081 else f_regmap[hr]=-1;
10083 else if(branch_regs[i].regmap[hr]>=0) {
10084 if(f_regmap[hr]!=branch_regs[i].regmap[hr]) {
10085 // dealloc old register
10087 for(n=0;n<HOST_REGS;n++)
10089 if(f_regmap[n]==branch_regs[i].regmap[hr]) {f_regmap[n]=-1;}
10091 // and alloc new one
10092 f_regmap[hr]=branch_regs[i].regmap[hr];
10096 if(count_free_regs(regs[i].regmap)<=minimum_free_regs[i+1])
10097 f_regmap[hr]=branch_regs[i].regmap[hr];
10099 if(count_free_regs(branch_regs[i].regmap)<=minimum_free_regs[i+1])
10100 f_regmap[hr]=branch_regs[i].regmap[hr];
10102 // Avoid dirty->clean transition
10103 #ifdef DESTRUCTIVE_WRITEBACK
10104 if(t>0) if(get_reg(regmap_pre[t],f_regmap[hr])>=0) if((regs[t].wasdirty>>get_reg(regmap_pre[t],f_regmap[hr]))&1) f_regmap[hr]=-1;
10106 // This check is only strictly required in the DESTRUCTIVE_WRITEBACK
10107 // case above, however it's always a good idea. We can't hoist the
10108 // load if the register was already allocated, so there's no point
10109 // wasting time analyzing most of these cases. It only "succeeds"
10110 // when the mapping was different and the load can be replaced with
10111 // a mov, which is of negligible benefit. So such cases are
10113 if(f_regmap[hr]>0) {
10114 if(regs[t].regmap[hr]==f_regmap[hr]||(regs[t].regmap_entry[hr]<0&&get_reg(regmap_pre[t],f_regmap[hr])<0)) {
10115 int r=f_regmap[hr];
10118 //printf("Test %x -> %x, %x %d/%d\n",start+i*4,ba[i],start+j*4,hr,r);
10119 if(r<34&&((unneeded_reg[j]>>r)&1)) break;
10120 if(r>63&&((unneeded_reg_upper[j]>>(r&63))&1)) break;
10122 // NB This can exclude the case where the upper-half
10123 // register is lower numbered than the lower-half
10124 // register. Not sure if it's worth fixing...
10125 if(get_reg(regs[j].regmap,r&63)<0) break;
10126 if(get_reg(regs[j].regmap_entry,r&63)<0) break;
10127 if(regs[j].is32&(1LL<<(r&63))) break;
10129 if(regs[j].regmap[hr]==f_regmap[hr]&&(f_regmap[hr]&63)<TEMPREG) {
10130 //printf("Hit %x -> %x, %x %d/%d\n",start+i*4,ba[i],start+j*4,hr,r);
10132 if(regs[i].regmap[hr]==-1&&branch_regs[i].regmap[hr]==-1) {
10133 if(get_reg(regs[i+2].regmap,f_regmap[hr])>=0) break;
10135 if(get_reg(regs[i].regmap,r&63)<0) break;
10136 if(get_reg(branch_regs[i].regmap,r&63)<0) break;
10139 while(k>1&®s[k-1].regmap[hr]==-1) {
10140 if(count_free_regs(regs[k-1].regmap)<=minimum_free_regs[k-1]) {
10141 //printf("no free regs for store %x\n",start+(k-1)*4);
10144 if(get_reg(regs[k-1].regmap,f_regmap[hr])>=0) {
10145 //printf("no-match due to different register\n");
10148 if(itype[k-2]==UJUMP||itype[k-2]==RJUMP||itype[k-2]==CJUMP||itype[k-2]==SJUMP||itype[k-2]==FJUMP) {
10149 //printf("no-match due to branch\n");
10152 // call/ret fast path assumes no registers allocated
10153 if(k>2&&(itype[k-3]==UJUMP||itype[k-3]==RJUMP)&&rt1[k-3]==31) {
10157 // NB This can exclude the case where the upper-half
10158 // register is lower numbered than the lower-half
10159 // register. Not sure if it's worth fixing...
10160 if(get_reg(regs[k-1].regmap,r&63)<0) break;
10161 if(regs[k-1].is32&(1LL<<(r&63))) break;
10166 if((regs[k].is32&(1LL<<f_regmap[hr]))!=
10167 (regs[i+2].was32&(1LL<<f_regmap[hr]))) {
10168 //printf("bad match after branch\n");
10172 if(regs[k-1].regmap[hr]==f_regmap[hr]&®map_pre[k][hr]==f_regmap[hr]) {
10173 //printf("Extend r%d, %x ->\n",hr,start+k*4);
10175 regs[k].regmap_entry[hr]=f_regmap[hr];
10176 regs[k].regmap[hr]=f_regmap[hr];
10177 regmap_pre[k+1][hr]=f_regmap[hr];
10178 regs[k].wasdirty&=~(1<<hr);
10179 regs[k].dirty&=~(1<<hr);
10180 regs[k].wasdirty|=(1<<hr)®s[k-1].dirty;
10181 regs[k].dirty|=(1<<hr)®s[k].wasdirty;
10182 regs[k].wasconst&=~(1<<hr);
10183 regs[k].isconst&=~(1<<hr);
10188 //printf("Fail Extend r%d, %x ->\n",hr,start+k*4);
10191 assert(regs[i-1].regmap[hr]==f_regmap[hr]);
10192 if(regs[i-1].regmap[hr]==f_regmap[hr]&®map_pre[i][hr]==f_regmap[hr]) {
10193 //printf("OK fill %x (r%d)\n",start+i*4,hr);
10194 regs[i].regmap_entry[hr]=f_regmap[hr];
10195 regs[i].regmap[hr]=f_regmap[hr];
10196 regs[i].wasdirty&=~(1<<hr);
10197 regs[i].dirty&=~(1<<hr);
10198 regs[i].wasdirty|=(1<<hr)®s[i-1].dirty;
10199 regs[i].dirty|=(1<<hr)®s[i-1].dirty;
10200 regs[i].wasconst&=~(1<<hr);
10201 regs[i].isconst&=~(1<<hr);
10202 branch_regs[i].regmap_entry[hr]=f_regmap[hr];
10203 branch_regs[i].wasdirty&=~(1<<hr);
10204 branch_regs[i].wasdirty|=(1<<hr)®s[i].dirty;
10205 branch_regs[i].regmap[hr]=f_regmap[hr];
10206 branch_regs[i].dirty&=~(1<<hr);
10207 branch_regs[i].dirty|=(1<<hr)®s[i].dirty;
10208 branch_regs[i].wasconst&=~(1<<hr);
10209 branch_regs[i].isconst&=~(1<<hr);
10210 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000) {
10211 regmap_pre[i+2][hr]=f_regmap[hr];
10212 regs[i+2].wasdirty&=~(1<<hr);
10213 regs[i+2].wasdirty|=(1<<hr)®s[i].dirty;
10214 assert((branch_regs[i].is32&(1LL<<f_regmap[hr]))==
10215 (regs[i+2].was32&(1LL<<f_regmap[hr])));
10220 // Alloc register clean at beginning of loop,
10221 // but may dirty it in pass 6
10222 regs[k].regmap_entry[hr]=f_regmap[hr];
10223 regs[k].regmap[hr]=f_regmap[hr];
10224 regs[k].dirty&=~(1<<hr);
10225 regs[k].wasconst&=~(1<<hr);
10226 regs[k].isconst&=~(1<<hr);
10227 if(itype[k]==UJUMP||itype[k]==RJUMP||itype[k]==CJUMP||itype[k]==SJUMP||itype[k]==FJUMP) {
10228 branch_regs[k].regmap_entry[hr]=f_regmap[hr];
10229 branch_regs[k].regmap[hr]=f_regmap[hr];
10230 branch_regs[k].dirty&=~(1<<hr);
10231 branch_regs[k].wasconst&=~(1<<hr);
10232 branch_regs[k].isconst&=~(1<<hr);
10233 if(itype[k]!=RJUMP&&itype[k]!=UJUMP&&(source[k]>>16)!=0x1000) {
10234 regmap_pre[k+2][hr]=f_regmap[hr];
10235 regs[k+2].wasdirty&=~(1<<hr);
10236 assert((branch_regs[k].is32&(1LL<<f_regmap[hr]))==
10237 (regs[k+2].was32&(1LL<<f_regmap[hr])));
10242 regmap_pre[k+1][hr]=f_regmap[hr];
10243 regs[k+1].wasdirty&=~(1<<hr);
10246 if(regs[j].regmap[hr]==f_regmap[hr])
10247 regs[j].regmap_entry[hr]=f_regmap[hr];
10251 if(regs[j].regmap[hr]>=0)
10253 if(get_reg(regs[j].regmap,f_regmap[hr])>=0) {
10254 //printf("no-match due to different register\n");
10257 if((regs[j+1].is32&(1LL<<f_regmap[hr]))!=(regs[j].is32&(1LL<<f_regmap[hr]))) {
10258 //printf("32/64 mismatch %x %d\n",start+j*4,hr);
10261 if(itype[j]==UJUMP||itype[j]==RJUMP||(source[j]>>16)==0x1000)
10263 // Stop on unconditional branch
10266 if(itype[j]==CJUMP||itype[j]==SJUMP||itype[j]==FJUMP)
10269 if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j+1])
10272 if(count_free_regs(branch_regs[j].regmap)<=minimum_free_regs[j+1])
10275 if(get_reg(branch_regs[j].regmap,f_regmap[hr])>=0) {
10276 //printf("no-match due to different register (branch)\n");
10280 if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j]) {
10281 //printf("No free regs for store %x\n",start+j*4);
10284 if(f_regmap[hr]>=64) {
10285 if(regs[j].is32&(1LL<<(f_regmap[hr]&63))) {
10290 if(get_reg(regs[j].regmap,f_regmap[hr]&63)<0) {
10301 // Non branch or undetermined branch target
10302 for(hr=0;hr<HOST_REGS;hr++)
10304 if(hr!=EXCLUDE_REG) {
10305 if(regs[i].regmap[hr]>64) {
10306 if(!((regs[i].dirty>>hr)&1))
10307 f_regmap[hr]=regs[i].regmap[hr];
10309 else if(regs[i].regmap[hr]>=0) {
10310 if(f_regmap[hr]!=regs[i].regmap[hr]) {
10311 // dealloc old register
10313 for(n=0;n<HOST_REGS;n++)
10315 if(f_regmap[n]==regs[i].regmap[hr]) {f_regmap[n]=-1;}
10317 // and alloc new one
10318 f_regmap[hr]=regs[i].regmap[hr];
10323 // Try to restore cycle count at branch targets
10325 for(j=i;j<slen-1;j++) {
10326 if(regs[j].regmap[HOST_CCREG]!=-1) break;
10327 if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j]) {
10328 //printf("no free regs for store %x\n",start+j*4);
10332 if(regs[j].regmap[HOST_CCREG]==CCREG) {
10334 //printf("Extend CC, %x -> %x\n",start+k*4,start+j*4);
10336 regs[k].regmap_entry[HOST_CCREG]=CCREG;
10337 regs[k].regmap[HOST_CCREG]=CCREG;
10338 regmap_pre[k+1][HOST_CCREG]=CCREG;
10339 regs[k+1].wasdirty|=1<<HOST_CCREG;
10340 regs[k].dirty|=1<<HOST_CCREG;
10341 regs[k].wasconst&=~(1<<HOST_CCREG);
10342 regs[k].isconst&=~(1<<HOST_CCREG);
10345 regs[j].regmap_entry[HOST_CCREG]=CCREG;
10347 // Work backwards from the branch target
10348 if(j>i&&f_regmap[HOST_CCREG]==CCREG)
10350 //printf("Extend backwards\n");
10353 while(regs[k-1].regmap[HOST_CCREG]==-1) {
10354 if(count_free_regs(regs[k-1].regmap)<=minimum_free_regs[k-1]) {
10355 //printf("no free regs for store %x\n",start+(k-1)*4);
10360 if(regs[k-1].regmap[HOST_CCREG]==CCREG) {
10361 //printf("Extend CC, %x ->\n",start+k*4);
10363 regs[k].regmap_entry[HOST_CCREG]=CCREG;
10364 regs[k].regmap[HOST_CCREG]=CCREG;
10365 regmap_pre[k+1][HOST_CCREG]=CCREG;
10366 regs[k+1].wasdirty|=1<<HOST_CCREG;
10367 regs[k].dirty|=1<<HOST_CCREG;
10368 regs[k].wasconst&=~(1<<HOST_CCREG);
10369 regs[k].isconst&=~(1<<HOST_CCREG);
10374 //printf("Fail Extend CC, %x ->\n",start+k*4);
10378 if(itype[i]!=STORE&&itype[i]!=STORELR&&itype[i]!=C1LS&&itype[i]!=SHIFT&&
10379 itype[i]!=NOP&&itype[i]!=MOV&&itype[i]!=ALU&&itype[i]!=SHIFTIMM&&
10380 itype[i]!=IMM16&&itype[i]!=LOAD&&itype[i]!=COP1&&itype[i]!=FLOAT&&
10381 itype[i]!=FCONV&&itype[i]!=FCOMP)
10383 memcpy(f_regmap,regs[i].regmap,sizeof(f_regmap));
10388 // Cache memory offset or tlb map pointer if a register is available
10389 #ifndef HOST_IMM_ADDR32
10394 int earliest_available[HOST_REGS];
10395 int loop_start[HOST_REGS];
10396 int score[HOST_REGS];
10397 int end[HOST_REGS];
10398 int reg=using_tlb?MMREG:ROREG;
10401 for(hr=0;hr<HOST_REGS;hr++) {
10402 score[hr]=0;earliest_available[hr]=0;
10403 loop_start[hr]=MAXBLOCK;
10405 for(i=0;i<slen-1;i++)
10407 // Can't do anything if no registers are available
10408 if(count_free_regs(regs[i].regmap)<=minimum_free_regs[i]) {
10409 for(hr=0;hr<HOST_REGS;hr++) {
10410 score[hr]=0;earliest_available[hr]=i+1;
10411 loop_start[hr]=MAXBLOCK;
10414 if(itype[i]==UJUMP||itype[i]==RJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP) {
10416 if(count_free_regs(branch_regs[i].regmap)<=minimum_free_regs[i+1]) {
10417 for(hr=0;hr<HOST_REGS;hr++) {
10418 score[hr]=0;earliest_available[hr]=i+1;
10419 loop_start[hr]=MAXBLOCK;
10423 if(count_free_regs(regs[i].regmap)<=minimum_free_regs[i+1]) {
10424 for(hr=0;hr<HOST_REGS;hr++) {
10425 score[hr]=0;earliest_available[hr]=i+1;
10426 loop_start[hr]=MAXBLOCK;
10431 // Mark unavailable registers
10432 for(hr=0;hr<HOST_REGS;hr++) {
10433 if(regs[i].regmap[hr]>=0) {
10434 score[hr]=0;earliest_available[hr]=i+1;
10435 loop_start[hr]=MAXBLOCK;
10437 if(itype[i]==UJUMP||itype[i]==RJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP) {
10438 if(branch_regs[i].regmap[hr]>=0) {
10439 score[hr]=0;earliest_available[hr]=i+2;
10440 loop_start[hr]=MAXBLOCK;
10444 // No register allocations after unconditional jumps
10445 if(itype[i]==UJUMP||itype[i]==RJUMP||(source[i]>>16)==0x1000)
10447 for(hr=0;hr<HOST_REGS;hr++) {
10448 score[hr]=0;earliest_available[hr]=i+2;
10449 loop_start[hr]=MAXBLOCK;
10451 i++; // Skip delay slot too
10452 //printf("skip delay slot: %x\n",start+i*4);
10456 if(itype[i]==LOAD||itype[i]==LOADLR||
10457 itype[i]==STORE||itype[i]==STORELR||itype[i]==C1LS) {
10458 for(hr=0;hr<HOST_REGS;hr++) {
10459 if(hr!=EXCLUDE_REG) {
10461 for(j=i;j<slen-1;j++) {
10462 if(regs[j].regmap[hr]>=0) break;
10463 if(itype[j]==UJUMP||itype[j]==RJUMP||itype[j]==CJUMP||itype[j]==SJUMP||itype[j]==FJUMP) {
10464 if(branch_regs[j].regmap[hr]>=0) break;
10466 if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j+1]) break;
10468 if(count_free_regs(branch_regs[j].regmap)<=minimum_free_regs[j+1]) break;
10471 else if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j]) break;
10472 if(itype[j]==UJUMP||itype[j]==RJUMP||itype[j]==CJUMP||itype[j]==SJUMP||itype[j]==FJUMP) {
10473 int t=(ba[j]-start)>>2;
10474 if(t<j&&t>=earliest_available[hr]) {
10475 if(t==1||(t>1&&itype[t-2]!=UJUMP&&itype[t-2]!=RJUMP)||(t>1&&rt1[t-2]!=31)) { // call/ret assumes no registers allocated
10476 // Score a point for hoisting loop invariant
10477 if(t<loop_start[hr]) loop_start[hr]=t;
10478 //printf("set loop_start: i=%x j=%x (%x)\n",start+i*4,start+j*4,start+t*4);
10484 if(regs[t].regmap[hr]==reg) {
10485 // Score a point if the branch target matches this register
10490 if(itype[j+1]==LOAD||itype[j+1]==LOADLR||
10491 itype[j+1]==STORE||itype[j+1]==STORELR||itype[j+1]==C1LS) {
10496 if(itype[j]==UJUMP||itype[j]==RJUMP||(source[j]>>16)==0x1000)
10498 // Stop on unconditional branch
10502 if(itype[j]==LOAD||itype[j]==LOADLR||
10503 itype[j]==STORE||itype[j]==STORELR||itype[j]==C1LS) {
10510 // Find highest score and allocate that register
10512 for(hr=0;hr<HOST_REGS;hr++) {
10513 if(hr!=EXCLUDE_REG) {
10514 if(score[hr]>score[maxscore]) {
10516 //printf("highest score: %d %d (%x->%x)\n",score[hr],hr,start+i*4,start+end[hr]*4);
10520 if(score[maxscore]>1)
10522 if(i<loop_start[maxscore]) loop_start[maxscore]=i;
10523 for(j=loop_start[maxscore];j<slen&&j<=end[maxscore];j++) {
10524 //if(regs[j].regmap[maxscore]>=0) {printf("oops: %x %x was %d=%d\n",loop_start[maxscore]*4+start,j*4+start,maxscore,regs[j].regmap[maxscore]);}
10525 assert(regs[j].regmap[maxscore]<0);
10526 if(j>loop_start[maxscore]) regs[j].regmap_entry[maxscore]=reg;
10527 regs[j].regmap[maxscore]=reg;
10528 regs[j].dirty&=~(1<<maxscore);
10529 regs[j].wasconst&=~(1<<maxscore);
10530 regs[j].isconst&=~(1<<maxscore);
10531 if(itype[j]==UJUMP||itype[j]==RJUMP||itype[j]==CJUMP||itype[j]==SJUMP||itype[j]==FJUMP) {
10532 branch_regs[j].regmap[maxscore]=reg;
10533 branch_regs[j].wasdirty&=~(1<<maxscore);
10534 branch_regs[j].dirty&=~(1<<maxscore);
10535 branch_regs[j].wasconst&=~(1<<maxscore);
10536 branch_regs[j].isconst&=~(1<<maxscore);
10537 if(itype[j]!=RJUMP&&itype[j]!=UJUMP&&(source[j]>>16)!=0x1000) {
10538 regmap_pre[j+2][maxscore]=reg;
10539 regs[j+2].wasdirty&=~(1<<maxscore);
10541 // loop optimization (loop_preload)
10542 int t=(ba[j]-start)>>2;
10543 if(t==loop_start[maxscore]) {
10544 if(t==1||(t>1&&itype[t-2]!=UJUMP&&itype[t-2]!=RJUMP)||(t>1&&rt1[t-2]!=31)) // call/ret assumes no registers allocated
10545 regs[t].regmap_entry[maxscore]=reg;
10550 if(j<1||(itype[j-1]!=RJUMP&&itype[j-1]!=UJUMP&&itype[j-1]!=CJUMP&&itype[j-1]!=SJUMP&&itype[j-1]!=FJUMP)) {
10551 regmap_pre[j+1][maxscore]=reg;
10552 regs[j+1].wasdirty&=~(1<<maxscore);
10557 if(itype[j-1]==RJUMP||itype[j-1]==UJUMP||itype[j-1]==CJUMP||itype[j-1]==SJUMP||itype[j-1]==FJUMP) i++; // skip delay slot
10558 for(hr=0;hr<HOST_REGS;hr++) {
10559 score[hr]=0;earliest_available[hr]=i+i;
10560 loop_start[hr]=MAXBLOCK;
10568 // This allocates registers (if possible) one instruction prior
10569 // to use, which can avoid a load-use penalty on certain CPUs.
10570 for(i=0;i<slen-1;i++)
10572 if(!i||(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP))
10576 if(itype[i]==ALU||itype[i]==MOV||itype[i]==LOAD||itype[i]==SHIFTIMM||itype[i]==IMM16
10577 ||((itype[i]==COP1||itype[i]==COP2)&&opcode2[i]<3))
10580 if((hr=get_reg(regs[i+1].regmap,rs1[i+1]))>=0)
10582 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
10584 regs[i].regmap[hr]=regs[i+1].regmap[hr];
10585 regmap_pre[i+1][hr]=regs[i+1].regmap[hr];
10586 regs[i+1].regmap_entry[hr]=regs[i+1].regmap[hr];
10587 regs[i].isconst&=~(1<<hr);
10588 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10589 constmap[i][hr]=constmap[i+1][hr];
10590 regs[i+1].wasdirty&=~(1<<hr);
10591 regs[i].dirty&=~(1<<hr);
10596 if((hr=get_reg(regs[i+1].regmap,rs2[i+1]))>=0)
10598 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
10600 regs[i].regmap[hr]=regs[i+1].regmap[hr];
10601 regmap_pre[i+1][hr]=regs[i+1].regmap[hr];
10602 regs[i+1].regmap_entry[hr]=regs[i+1].regmap[hr];
10603 regs[i].isconst&=~(1<<hr);
10604 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10605 constmap[i][hr]=constmap[i+1][hr];
10606 regs[i+1].wasdirty&=~(1<<hr);
10607 regs[i].dirty&=~(1<<hr);
10611 // Preload target address for load instruction (non-constant)
10612 if(itype[i+1]==LOAD&&rs1[i+1]&&get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10613 if((hr=get_reg(regs[i+1].regmap,rt1[i+1]))>=0)
10615 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
10617 regs[i].regmap[hr]=rs1[i+1];
10618 regmap_pre[i+1][hr]=rs1[i+1];
10619 regs[i+1].regmap_entry[hr]=rs1[i+1];
10620 regs[i].isconst&=~(1<<hr);
10621 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10622 constmap[i][hr]=constmap[i+1][hr];
10623 regs[i+1].wasdirty&=~(1<<hr);
10624 regs[i].dirty&=~(1<<hr);
10628 // Load source into target register
10629 if(lt1[i+1]&&get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10630 if((hr=get_reg(regs[i+1].regmap,rt1[i+1]))>=0)
10632 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
10634 regs[i].regmap[hr]=rs1[i+1];
10635 regmap_pre[i+1][hr]=rs1[i+1];
10636 regs[i+1].regmap_entry[hr]=rs1[i+1];
10637 regs[i].isconst&=~(1<<hr);
10638 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10639 constmap[i][hr]=constmap[i+1][hr];
10640 regs[i+1].wasdirty&=~(1<<hr);
10641 regs[i].dirty&=~(1<<hr);
10645 // Preload map address
10646 #ifndef HOST_IMM_ADDR32
10647 if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS||itype[i+1]==C2LS) {
10648 hr=get_reg(regs[i+1].regmap,TLREG);
10650 int sr=get_reg(regs[i+1].regmap,rs1[i+1]);
10651 if(sr>=0&&((regs[i+1].wasconst>>sr)&1)) {
10653 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
10655 regs[i].regmap[hr]=MGEN1+((i+1)&1);
10656 regmap_pre[i+1][hr]=MGEN1+((i+1)&1);
10657 regs[i+1].regmap_entry[hr]=MGEN1+((i+1)&1);
10658 regs[i].isconst&=~(1<<hr);
10659 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10660 constmap[i][hr]=constmap[i+1][hr];
10661 regs[i+1].wasdirty&=~(1<<hr);
10662 regs[i].dirty&=~(1<<hr);
10664 else if((nr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1))>=0)
10666 // move it to another register
10667 regs[i+1].regmap[hr]=-1;
10668 regmap_pre[i+2][hr]=-1;
10669 regs[i+1].regmap[nr]=TLREG;
10670 regmap_pre[i+2][nr]=TLREG;
10671 regs[i].regmap[nr]=MGEN1+((i+1)&1);
10672 regmap_pre[i+1][nr]=MGEN1+((i+1)&1);
10673 regs[i+1].regmap_entry[nr]=MGEN1+((i+1)&1);
10674 regs[i].isconst&=~(1<<nr);
10675 regs[i+1].isconst&=~(1<<nr);
10676 regs[i].dirty&=~(1<<nr);
10677 regs[i+1].wasdirty&=~(1<<nr);
10678 regs[i+1].dirty&=~(1<<nr);
10679 regs[i+2].wasdirty&=~(1<<nr);
10685 // Address for store instruction (non-constant)
10686 if(itype[i+1]==STORE||itype[i+1]==STORELR
10687 ||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a) { // SB/SH/SW/SD/SWC1/SDC1/SWC2/SDC2
10688 if(get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10689 hr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1);
10690 if(hr<0) hr=get_reg(regs[i+1].regmap,-1);
10691 else {regs[i+1].regmap[hr]=AGEN1+((i+1)&1);regs[i+1].isconst&=~(1<<hr);}
10693 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
10695 regs[i].regmap[hr]=rs1[i+1];
10696 regmap_pre[i+1][hr]=rs1[i+1];
10697 regs[i+1].regmap_entry[hr]=rs1[i+1];
10698 regs[i].isconst&=~(1<<hr);
10699 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10700 constmap[i][hr]=constmap[i+1][hr];
10701 regs[i+1].wasdirty&=~(1<<hr);
10702 regs[i].dirty&=~(1<<hr);
10706 if(itype[i+1]==LOADLR||(opcode[i+1]&0x3b)==0x31||(opcode[i+1]&0x3b)==0x32) { // LWC1/LDC1, LWC2/LDC2
10707 if(get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10709 hr=get_reg(regs[i+1].regmap,FTEMP);
10711 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
10713 regs[i].regmap[hr]=rs1[i+1];
10714 regmap_pre[i+1][hr]=rs1[i+1];
10715 regs[i+1].regmap_entry[hr]=rs1[i+1];
10716 regs[i].isconst&=~(1<<hr);
10717 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10718 constmap[i][hr]=constmap[i+1][hr];
10719 regs[i+1].wasdirty&=~(1<<hr);
10720 regs[i].dirty&=~(1<<hr);
10722 else if((nr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1))>=0)
10724 // move it to another register
10725 regs[i+1].regmap[hr]=-1;
10726 regmap_pre[i+2][hr]=-1;
10727 regs[i+1].regmap[nr]=FTEMP;
10728 regmap_pre[i+2][nr]=FTEMP;
10729 regs[i].regmap[nr]=rs1[i+1];
10730 regmap_pre[i+1][nr]=rs1[i+1];
10731 regs[i+1].regmap_entry[nr]=rs1[i+1];
10732 regs[i].isconst&=~(1<<nr);
10733 regs[i+1].isconst&=~(1<<nr);
10734 regs[i].dirty&=~(1<<nr);
10735 regs[i+1].wasdirty&=~(1<<nr);
10736 regs[i+1].dirty&=~(1<<nr);
10737 regs[i+2].wasdirty&=~(1<<nr);
10741 if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR/*||itype[i+1]==C1LS||||itype[i+1]==C2LS*/) {
10742 if(itype[i+1]==LOAD)
10743 hr=get_reg(regs[i+1].regmap,rt1[i+1]);
10744 if(itype[i+1]==LOADLR||(opcode[i+1]&0x3b)==0x31||(opcode[i+1]&0x3b)==0x32) // LWC1/LDC1, LWC2/LDC2
10745 hr=get_reg(regs[i+1].regmap,FTEMP);
10746 if(itype[i+1]==STORE||itype[i+1]==STORELR||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a) { // SWC1/SDC1/SWC2/SDC2
10747 hr=get_reg(regs[i+1].regmap,AGEN1+((i+1)&1));
10748 if(hr<0) hr=get_reg(regs[i+1].regmap,-1);
10750 if(hr>=0&®s[i].regmap[hr]<0) {
10751 int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
10752 if(rs>=0&&((regs[i+1].wasconst>>rs)&1)) {
10753 regs[i].regmap[hr]=AGEN1+((i+1)&1);
10754 regmap_pre[i+1][hr]=AGEN1+((i+1)&1);
10755 regs[i+1].regmap_entry[hr]=AGEN1+((i+1)&1);
10756 regs[i].isconst&=~(1<<hr);
10757 regs[i+1].wasdirty&=~(1<<hr);
10758 regs[i].dirty&=~(1<<hr);
10767 /* Pass 6 - Optimize clean/dirty state */
10768 clean_registers(0,slen-1,1);
10770 /* Pass 7 - Identify 32-bit registers */
10776 for (i=slen-1;i>=0;i--)
10779 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
10781 if(ba[i]<start || ba[i]>=(start+slen*4))
10783 // Branch out of this block, don't need anything
10789 // Need whatever matches the target
10790 // (and doesn't get overwritten by the delay slot instruction)
10792 int t=(ba[i]-start)>>2;
10793 if(ba[i]>start+i*4) {
10795 if(!(requires_32bit[t]&~regs[i].was32))
10796 r32|=requires_32bit[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
10799 //if(!(regs[t].was32&~unneeded_reg_upper[t]&~regs[i].was32))
10800 // r32|=regs[t].was32&~unneeded_reg_upper[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
10801 if(!(pr32[t]&~regs[i].was32))
10802 r32|=pr32[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
10805 // Conditional branch may need registers for following instructions
10806 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
10809 r32|=requires_32bit[i+2];
10810 r32&=regs[i].was32;
10811 // Mark this address as a branch target since it may be called
10812 // upon return from interrupt
10816 // Merge in delay slot
10818 // These are overwritten unless the branch is "likely"
10819 // and the delay slot is nullified if not taken
10820 r32&=~(1LL<<rt1[i+1]);
10821 r32&=~(1LL<<rt2[i+1]);
10823 // Assume these are needed (delay slot)
10826 if((regs[i].was32>>us1[i+1])&1) r32|=1LL<<us1[i+1];
10830 if((regs[i].was32>>us2[i+1])&1) r32|=1LL<<us2[i+1];
10832 if(dep1[i+1]&&!((unneeded_reg_upper[i]>>dep1[i+1])&1))
10834 if((regs[i].was32>>dep1[i+1])&1) r32|=1LL<<dep1[i+1];
10836 if(dep2[i+1]&&!((unneeded_reg_upper[i]>>dep2[i+1])&1))
10838 if((regs[i].was32>>dep2[i+1])&1) r32|=1LL<<dep2[i+1];
10841 else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
10843 // SYSCALL instruction (software interrupt)
10846 else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
10848 // ERET instruction (return from interrupt)
10852 r32&=~(1LL<<rt1[i]);
10853 r32&=~(1LL<<rt2[i]);
10856 if((regs[i].was32>>us1[i])&1) r32|=1LL<<us1[i];
10860 if((regs[i].was32>>us2[i])&1) r32|=1LL<<us2[i];
10862 if(dep1[i]&&!((unneeded_reg_upper[i]>>dep1[i])&1))
10864 if((regs[i].was32>>dep1[i])&1) r32|=1LL<<dep1[i];
10866 if(dep2[i]&&!((unneeded_reg_upper[i]>>dep2[i])&1))
10868 if((regs[i].was32>>dep2[i])&1) r32|=1LL<<dep2[i];
10870 requires_32bit[i]=r32;
10872 // Dirty registers which are 32-bit, require 32-bit input
10873 // as they will be written as 32-bit values
10874 for(hr=0;hr<HOST_REGS;hr++)
10876 if(regs[i].regmap_entry[hr]>0&®s[i].regmap_entry[hr]<64) {
10877 if((regs[i].was32>>regs[i].regmap_entry[hr])&(regs[i].wasdirty>>hr)&1) {
10878 if(!((unneeded_reg_upper[i]>>regs[i].regmap_entry[hr])&1))
10879 requires_32bit[i]|=1LL<<regs[i].regmap_entry[hr];
10883 //requires_32bit[i]=is32[i]&~unneeded_reg_upper[i]; // DEBUG
10886 for (i=slen-1;i>=0;i--)
10888 if(itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
10890 // Conditional branch
10891 if((source[i]>>16)!=0x1000&&i<slen-2) {
10892 // Mark this address as a branch target since it may be called
10893 // upon return from interrupt
10900 if(itype[slen-1]==SPAN) {
10901 bt[slen-1]=1; // Mark as a branch target so instruction can restart after exception
10905 /* Debug/disassembly */
10906 for(i=0;i<slen;i++)
10910 for(r=1;r<=CCREG;r++) {
10911 if((unneeded_reg[i]>>r)&1) {
10912 if(r==HIREG) printf(" HI");
10913 else if(r==LOREG) printf(" LO");
10914 else printf(" r%d",r);
10919 for(r=1;r<=CCREG;r++) {
10920 if(((unneeded_reg_upper[i]&~unneeded_reg[i])>>r)&1) {
10921 if(r==HIREG) printf(" HI");
10922 else if(r==LOREG) printf(" LO");
10923 else printf(" r%d",r);
10927 for(r=0;r<=CCREG;r++) {
10928 //if(((is32[i]>>r)&(~unneeded_reg[i]>>r))&1) {
10929 if((regs[i].was32>>r)&1) {
10930 if(r==CCREG) printf(" CC");
10931 else if(r==HIREG) printf(" HI");
10932 else if(r==LOREG) printf(" LO");
10933 else printf(" r%d",r);
10938 #if defined(__i386__) || defined(__x86_64__)
10939 printf("pre: eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",regmap_pre[i][0],regmap_pre[i][1],regmap_pre[i][2],regmap_pre[i][3],regmap_pre[i][5],regmap_pre[i][6],regmap_pre[i][7]);
10942 printf("pre: r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d\n",regmap_pre[i][0],regmap_pre[i][1],regmap_pre[i][2],regmap_pre[i][3],regmap_pre[i][4],regmap_pre[i][5],regmap_pre[i][6],regmap_pre[i][7],regmap_pre[i][8],regmap_pre[i][9],regmap_pre[i][10],regmap_pre[i][12]);
10945 if(needed_reg[i]&1) printf("eax ");
10946 if((needed_reg[i]>>1)&1) printf("ecx ");
10947 if((needed_reg[i]>>2)&1) printf("edx ");
10948 if((needed_reg[i]>>3)&1) printf("ebx ");
10949 if((needed_reg[i]>>5)&1) printf("ebp ");
10950 if((needed_reg[i]>>6)&1) printf("esi ");
10951 if((needed_reg[i]>>7)&1) printf("edi ");
10953 for(r=0;r<=CCREG;r++) {
10954 //if(((requires_32bit[i]>>r)&(~unneeded_reg[i]>>r))&1) {
10955 if((requires_32bit[i]>>r)&1) {
10956 if(r==CCREG) printf(" CC");
10957 else if(r==HIREG) printf(" HI");
10958 else if(r==LOREG) printf(" LO");
10959 else printf(" r%d",r);
10964 for(r=0;r<=CCREG;r++) {
10965 //if(((requires_32bit[i]>>r)&(~unneeded_reg[i]>>r))&1) {
10966 if((pr32[i]>>r)&1) {
10967 if(r==CCREG) printf(" CC");
10968 else if(r==HIREG) printf(" HI");
10969 else if(r==LOREG) printf(" LO");
10970 else printf(" r%d",r);
10973 if(pr32[i]!=requires_32bit[i]) printf(" OOPS");
10975 #if defined(__i386__) || defined(__x86_64__)
10976 printf("entry: eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",regs[i].regmap_entry[0],regs[i].regmap_entry[1],regs[i].regmap_entry[2],regs[i].regmap_entry[3],regs[i].regmap_entry[5],regs[i].regmap_entry[6],regs[i].regmap_entry[7]);
10978 if(regs[i].wasdirty&1) printf("eax ");
10979 if((regs[i].wasdirty>>1)&1) printf("ecx ");
10980 if((regs[i].wasdirty>>2)&1) printf("edx ");
10981 if((regs[i].wasdirty>>3)&1) printf("ebx ");
10982 if((regs[i].wasdirty>>5)&1) printf("ebp ");
10983 if((regs[i].wasdirty>>6)&1) printf("esi ");
10984 if((regs[i].wasdirty>>7)&1) printf("edi ");
10987 printf("entry: r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d\n",regs[i].regmap_entry[0],regs[i].regmap_entry[1],regs[i].regmap_entry[2],regs[i].regmap_entry[3],regs[i].regmap_entry[4],regs[i].regmap_entry[5],regs[i].regmap_entry[6],regs[i].regmap_entry[7],regs[i].regmap_entry[8],regs[i].regmap_entry[9],regs[i].regmap_entry[10],regs[i].regmap_entry[12]);
10989 if(regs[i].wasdirty&1) printf("r0 ");
10990 if((regs[i].wasdirty>>1)&1) printf("r1 ");
10991 if((regs[i].wasdirty>>2)&1) printf("r2 ");
10992 if((regs[i].wasdirty>>3)&1) printf("r3 ");
10993 if((regs[i].wasdirty>>4)&1) printf("r4 ");
10994 if((regs[i].wasdirty>>5)&1) printf("r5 ");
10995 if((regs[i].wasdirty>>6)&1) printf("r6 ");
10996 if((regs[i].wasdirty>>7)&1) printf("r7 ");
10997 if((regs[i].wasdirty>>8)&1) printf("r8 ");
10998 if((regs[i].wasdirty>>9)&1) printf("r9 ");
10999 if((regs[i].wasdirty>>10)&1) printf("r10 ");
11000 if((regs[i].wasdirty>>12)&1) printf("r12 ");
11003 disassemble_inst(i);
11004 //printf ("ccadj[%d] = %d\n",i,ccadj[i]);
11005 #if defined(__i386__) || defined(__x86_64__)
11006 printf("eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d dirty: ",regs[i].regmap[0],regs[i].regmap[1],regs[i].regmap[2],regs[i].regmap[3],regs[i].regmap[5],regs[i].regmap[6],regs[i].regmap[7]);
11007 if(regs[i].dirty&1) printf("eax ");
11008 if((regs[i].dirty>>1)&1) printf("ecx ");
11009 if((regs[i].dirty>>2)&1) printf("edx ");
11010 if((regs[i].dirty>>3)&1) printf("ebx ");
11011 if((regs[i].dirty>>5)&1) printf("ebp ");
11012 if((regs[i].dirty>>6)&1) printf("esi ");
11013 if((regs[i].dirty>>7)&1) printf("edi ");
11016 printf("r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d dirty: ",regs[i].regmap[0],regs[i].regmap[1],regs[i].regmap[2],regs[i].regmap[3],regs[i].regmap[4],regs[i].regmap[5],regs[i].regmap[6],regs[i].regmap[7],regs[i].regmap[8],regs[i].regmap[9],regs[i].regmap[10],regs[i].regmap[12]);
11017 if(regs[i].dirty&1) printf("r0 ");
11018 if((regs[i].dirty>>1)&1) printf("r1 ");
11019 if((regs[i].dirty>>2)&1) printf("r2 ");
11020 if((regs[i].dirty>>3)&1) printf("r3 ");
11021 if((regs[i].dirty>>4)&1) printf("r4 ");
11022 if((regs[i].dirty>>5)&1) printf("r5 ");
11023 if((regs[i].dirty>>6)&1) printf("r6 ");
11024 if((regs[i].dirty>>7)&1) printf("r7 ");
11025 if((regs[i].dirty>>8)&1) printf("r8 ");
11026 if((regs[i].dirty>>9)&1) printf("r9 ");
11027 if((regs[i].dirty>>10)&1) printf("r10 ");
11028 if((regs[i].dirty>>12)&1) printf("r12 ");
11031 if(regs[i].isconst) {
11032 printf("constants: ");
11033 #if defined(__i386__) || defined(__x86_64__)
11034 if(regs[i].isconst&1) printf("eax=%x ",(int)constmap[i][0]);
11035 if((regs[i].isconst>>1)&1) printf("ecx=%x ",(int)constmap[i][1]);
11036 if((regs[i].isconst>>2)&1) printf("edx=%x ",(int)constmap[i][2]);
11037 if((regs[i].isconst>>3)&1) printf("ebx=%x ",(int)constmap[i][3]);
11038 if((regs[i].isconst>>5)&1) printf("ebp=%x ",(int)constmap[i][5]);
11039 if((regs[i].isconst>>6)&1) printf("esi=%x ",(int)constmap[i][6]);
11040 if((regs[i].isconst>>7)&1) printf("edi=%x ",(int)constmap[i][7]);
11043 if(regs[i].isconst&1) printf("r0=%x ",(int)constmap[i][0]);
11044 if((regs[i].isconst>>1)&1) printf("r1=%x ",(int)constmap[i][1]);
11045 if((regs[i].isconst>>2)&1) printf("r2=%x ",(int)constmap[i][2]);
11046 if((regs[i].isconst>>3)&1) printf("r3=%x ",(int)constmap[i][3]);
11047 if((regs[i].isconst>>4)&1) printf("r4=%x ",(int)constmap[i][4]);
11048 if((regs[i].isconst>>5)&1) printf("r5=%x ",(int)constmap[i][5]);
11049 if((regs[i].isconst>>6)&1) printf("r6=%x ",(int)constmap[i][6]);
11050 if((regs[i].isconst>>7)&1) printf("r7=%x ",(int)constmap[i][7]);
11051 if((regs[i].isconst>>8)&1) printf("r8=%x ",(int)constmap[i][8]);
11052 if((regs[i].isconst>>9)&1) printf("r9=%x ",(int)constmap[i][9]);
11053 if((regs[i].isconst>>10)&1) printf("r10=%x ",(int)constmap[i][10]);
11054 if((regs[i].isconst>>12)&1) printf("r12=%x ",(int)constmap[i][12]);
11060 for(r=0;r<=CCREG;r++) {
11061 if((regs[i].is32>>r)&1) {
11062 if(r==CCREG) printf(" CC");
11063 else if(r==HIREG) printf(" HI");
11064 else if(r==LOREG) printf(" LO");
11065 else printf(" r%d",r);
11071 for(r=0;r<=CCREG;r++) {
11072 if((p32[i]>>r)&1) {
11073 if(r==CCREG) printf(" CC");
11074 else if(r==HIREG) printf(" HI");
11075 else if(r==LOREG) printf(" LO");
11076 else printf(" r%d",r);
11079 if(p32[i]!=regs[i].is32) printf(" NO MATCH\n");
11080 else printf("\n");*/
11081 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP) {
11082 #if defined(__i386__) || defined(__x86_64__)
11083 printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d dirty: ",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
11084 if(branch_regs[i].dirty&1) printf("eax ");
11085 if((branch_regs[i].dirty>>1)&1) printf("ecx ");
11086 if((branch_regs[i].dirty>>2)&1) printf("edx ");
11087 if((branch_regs[i].dirty>>3)&1) printf("ebx ");
11088 if((branch_regs[i].dirty>>5)&1) printf("ebp ");
11089 if((branch_regs[i].dirty>>6)&1) printf("esi ");
11090 if((branch_regs[i].dirty>>7)&1) printf("edi ");
11093 printf("branch(%d): r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d dirty: ",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[4],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7],branch_regs[i].regmap[8],branch_regs[i].regmap[9],branch_regs[i].regmap[10],branch_regs[i].regmap[12]);
11094 if(branch_regs[i].dirty&1) printf("r0 ");
11095 if((branch_regs[i].dirty>>1)&1) printf("r1 ");
11096 if((branch_regs[i].dirty>>2)&1) printf("r2 ");
11097 if((branch_regs[i].dirty>>3)&1) printf("r3 ");
11098 if((branch_regs[i].dirty>>4)&1) printf("r4 ");
11099 if((branch_regs[i].dirty>>5)&1) printf("r5 ");
11100 if((branch_regs[i].dirty>>6)&1) printf("r6 ");
11101 if((branch_regs[i].dirty>>7)&1) printf("r7 ");
11102 if((branch_regs[i].dirty>>8)&1) printf("r8 ");
11103 if((branch_regs[i].dirty>>9)&1) printf("r9 ");
11104 if((branch_regs[i].dirty>>10)&1) printf("r10 ");
11105 if((branch_regs[i].dirty>>12)&1) printf("r12 ");
11109 for(r=0;r<=CCREG;r++) {
11110 if((branch_regs[i].is32>>r)&1) {
11111 if(r==CCREG) printf(" CC");
11112 else if(r==HIREG) printf(" HI");
11113 else if(r==LOREG) printf(" LO");
11114 else printf(" r%d",r);
11123 /* Pass 8 - Assembly */
11124 linkcount=0;stubcount=0;
11125 ds=0;is_delayslot=0;
11127 uint64_t is32_pre=0;
11129 u_int beginning=(u_int)out;
11130 if((u_int)addr&1) {
11134 u_int instr_addr0_override=0;
11137 if (start == 0x80030000) {
11138 // nasty hack for fastbios thing
11139 // override block entry to this code
11140 instr_addr0_override=(u_int)out;
11141 emit_movimm(start,0);
11142 // abuse io address var as a flag that we
11143 // have already returned here once
11144 emit_readword((int)&address,1);
11145 emit_writeword(0,(int)&pcaddr);
11146 emit_writeword(0,(int)&address);
11148 emit_jne((int)new_dyna_leave);
11151 for(i=0;i<slen;i++)
11153 //if(ds) printf("ds: ");
11154 disassemble_inst(i);
11156 ds=0; // Skip delay slot
11157 if(bt[i]) assem_debug("OOPS - branch into delay slot\n");
11160 #ifndef DESTRUCTIVE_WRITEBACK
11161 if(i<2||(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000))
11163 wb_sx(regmap_pre[i],regs[i].regmap_entry,regs[i].wasdirty,is32_pre,regs[i].was32,
11164 unneeded_reg[i],unneeded_reg_upper[i]);
11165 wb_valid(regmap_pre[i],regs[i].regmap_entry,dirty_pre,regs[i].wasdirty,is32_pre,
11166 unneeded_reg[i],unneeded_reg_upper[i]);
11168 if((itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)&&!likely[i]) {
11169 is32_pre=branch_regs[i].is32;
11170 dirty_pre=branch_regs[i].dirty;
11172 is32_pre=regs[i].is32;
11173 dirty_pre=regs[i].dirty;
11177 if(i<2||(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000))
11179 wb_invalidate(regmap_pre[i],regs[i].regmap_entry,regs[i].wasdirty,regs[i].was32,
11180 unneeded_reg[i],unneeded_reg_upper[i]);
11181 loop_preload(regmap_pre[i],regs[i].regmap_entry);
11183 // branch target entry point
11184 instr_addr[i]=(u_int)out;
11185 assem_debug("<->\n");
11187 if(regs[i].regmap_entry[HOST_CCREG]==CCREG&®s[i].regmap[HOST_CCREG]!=CCREG)
11188 wb_register(CCREG,regs[i].regmap_entry,regs[i].wasdirty,regs[i].was32);
11189 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs1[i],rs2[i]);
11190 address_generation(i,®s[i],regs[i].regmap_entry);
11191 load_consts(regmap_pre[i],regs[i].regmap,regs[i].was32,i);
11192 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
11194 // Load the delay slot registers if necessary
11195 if(rs1[i+1]!=rs1[i]&&rs1[i+1]!=rs2[i]&&(rs1[i+1]!=rt1[i]||rt1[i]==0))
11196 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs1[i+1],rs1[i+1]);
11197 if(rs2[i+1]!=rs1[i+1]&&rs2[i+1]!=rs1[i]&&rs2[i+1]!=rs2[i]&&(rs2[i+1]!=rt1[i]||rt1[i]==0))
11198 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs2[i+1],rs2[i+1]);
11199 if(itype[i+1]==STORE||itype[i+1]==STORELR||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a)
11200 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,INVCP,INVCP);
11204 // Preload registers for following instruction
11205 if(rs1[i+1]!=rs1[i]&&rs1[i+1]!=rs2[i])
11206 if(rs1[i+1]!=rt1[i]&&rs1[i+1]!=rt2[i])
11207 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs1[i+1],rs1[i+1]);
11208 if(rs2[i+1]!=rs1[i+1]&&rs2[i+1]!=rs1[i]&&rs2[i+1]!=rs2[i])
11209 if(rs2[i+1]!=rt1[i]&&rs2[i+1]!=rt2[i])
11210 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs2[i+1],rs2[i+1]);
11212 // TODO: if(is_ooo(i)) address_generation(i+1);
11213 if(itype[i]==CJUMP||itype[i]==FJUMP)
11214 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,CCREG,CCREG);
11215 if(itype[i]==STORE||itype[i]==STORELR||(opcode[i]&0x3b)==0x39||(opcode[i]&0x3b)==0x3a)
11216 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,INVCP,INVCP);
11217 if(bt[i]) cop1_usable=0;
11221 alu_assemble(i,®s[i]);break;
11223 imm16_assemble(i,®s[i]);break;
11225 shift_assemble(i,®s[i]);break;
11227 shiftimm_assemble(i,®s[i]);break;
11229 load_assemble(i,®s[i]);break;
11231 loadlr_assemble(i,®s[i]);break;
11233 store_assemble(i,®s[i]);break;
11235 storelr_assemble(i,®s[i]);break;
11237 cop0_assemble(i,®s[i]);break;
11239 cop1_assemble(i,®s[i]);break;
11241 c1ls_assemble(i,®s[i]);break;
11243 cop2_assemble(i,®s[i]);break;
11245 c2ls_assemble(i,®s[i]);break;
11247 c2op_assemble(i,®s[i]);break;
11249 fconv_assemble(i,®s[i]);break;
11251 float_assemble(i,®s[i]);break;
11253 fcomp_assemble(i,®s[i]);break;
11255 multdiv_assemble(i,®s[i]);break;
11257 mov_assemble(i,®s[i]);break;
11259 syscall_assemble(i,®s[i]);break;
11261 hlecall_assemble(i,®s[i]);break;
11263 intcall_assemble(i,®s[i]);break;
11265 ujump_assemble(i,®s[i]);ds=1;break;
11267 rjump_assemble(i,®s[i]);ds=1;break;
11269 cjump_assemble(i,®s[i]);ds=1;break;
11271 sjump_assemble(i,®s[i]);ds=1;break;
11273 fjump_assemble(i,®s[i]);ds=1;break;
11275 pagespan_assemble(i,®s[i]);break;
11277 if(itype[i]==UJUMP||itype[i]==RJUMP||(source[i]>>16)==0x1000)
11278 literal_pool(1024);
11280 literal_pool_jumpover(256);
11283 //assert(itype[i-2]==UJUMP||itype[i-2]==RJUMP||(source[i-2]>>16)==0x1000);
11284 // If the block did not end with an unconditional branch,
11285 // add a jump to the next instruction.
11287 if(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000&&itype[i-1]!=SPAN) {
11288 assert(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP);
11290 if(itype[i-2]!=CJUMP&&itype[i-2]!=SJUMP&&itype[i-2]!=FJUMP) {
11291 store_regs_bt(regs[i-1].regmap,regs[i-1].is32,regs[i-1].dirty,start+i*4);
11292 if(regs[i-1].regmap[HOST_CCREG]!=CCREG)
11293 emit_loadreg(CCREG,HOST_CCREG);
11294 emit_addimm(HOST_CCREG,CLOCK_DIVIDER*(ccadj[i-1]+1),HOST_CCREG);
11296 else if(!likely[i-2])
11298 store_regs_bt(branch_regs[i-2].regmap,branch_regs[i-2].is32,branch_regs[i-2].dirty,start+i*4);
11299 assert(branch_regs[i-2].regmap[HOST_CCREG]==CCREG);
11303 store_regs_bt(regs[i-2].regmap,regs[i-2].is32,regs[i-2].dirty,start+i*4);
11304 assert(regs[i-2].regmap[HOST_CCREG]==CCREG);
11306 add_to_linker((int)out,start+i*4,0);
11313 assert(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP);
11314 store_regs_bt(regs[i-1].regmap,regs[i-1].is32,regs[i-1].dirty,start+i*4);
11315 if(regs[i-1].regmap[HOST_CCREG]!=CCREG)
11316 emit_loadreg(CCREG,HOST_CCREG);
11317 emit_addimm(HOST_CCREG,CLOCK_DIVIDER*(ccadj[i-1]+1),HOST_CCREG);
11318 add_to_linker((int)out,start+i*4,0);
11322 // TODO: delay slot stubs?
11324 for(i=0;i<stubcount;i++)
11326 switch(stubs[i][0])
11334 do_readstub(i);break;
11339 do_writestub(i);break;
11341 do_ccstub(i);break;
11343 do_invstub(i);break;
11345 do_cop1stub(i);break;
11347 do_unalignedwritestub(i);break;
11351 if (instr_addr0_override)
11352 instr_addr[0] = instr_addr0_override;
11354 /* Pass 9 - Linker */
11355 for(i=0;i<linkcount;i++)
11357 assem_debug("%8x -> %8x\n",link_addr[i][0],link_addr[i][1]);
11359 if(!link_addr[i][2])
11362 void *addr=check_addr(link_addr[i][1]);
11363 emit_extjump(link_addr[i][0],link_addr[i][1]);
11365 set_jump_target(link_addr[i][0],(int)addr);
11366 add_link(link_addr[i][1],stub);
11368 else set_jump_target(link_addr[i][0],(int)stub);
11373 int target=(link_addr[i][1]-start)>>2;
11374 assert(target>=0&&target<slen);
11375 assert(instr_addr[target]);
11376 //#ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
11377 //set_jump_target_fillslot(link_addr[i][0],instr_addr[target],link_addr[i][2]>>1);
11379 set_jump_target(link_addr[i][0],instr_addr[target]);
11383 // External Branch Targets (jump_in)
11384 if(copy+slen*4>(void *)shadow+sizeof(shadow)) copy=shadow;
11385 for(i=0;i<slen;i++)
11389 if(instr_addr[i]) // TODO - delay slots (=null)
11391 u_int vaddr=start+i*4;
11392 u_int page=get_page(vaddr);
11393 u_int vpage=get_vpage(vaddr);
11395 //if(!(is32[i]&(~unneeded_reg_upper[i])&~(1LL<<CCREG)))
11397 if(!requires_32bit[i])
11402 assem_debug("%8x (%d) <- %8x\n",instr_addr[i],i,start+i*4);
11403 assem_debug("jump_in: %x\n",start+i*4);
11404 ll_add(jump_dirty+vpage,vaddr,(void *)out);
11405 int entry_point=do_dirty_stub(i);
11406 ll_add(jump_in+page,vaddr,(void *)entry_point);
11407 // If there was an existing entry in the hash table,
11408 // replace it with the new address.
11409 // Don't add new entries. We'll insert the
11410 // ones that actually get used in check_addr().
11411 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
11412 if(ht_bin[0]==vaddr) {
11413 ht_bin[1]=entry_point;
11415 if(ht_bin[2]==vaddr) {
11416 ht_bin[3]=entry_point;
11421 u_int r=requires_32bit[i]|!!(requires_32bit[i]>>32);
11422 assem_debug("%8x (%d) <- %8x\n",instr_addr[i],i,start+i*4);
11423 assem_debug("jump_in: %x (restricted - %x)\n",start+i*4,r);
11424 //int entry_point=(int)out;
11425 ////assem_debug("entry_point: %x\n",entry_point);
11426 //load_regs_entry(i);
11427 //if(entry_point==(int)out)
11428 // entry_point=instr_addr[i];
11430 // emit_jmp(instr_addr[i]);
11431 //ll_add_32(jump_in+page,vaddr,r,(void *)entry_point);
11432 ll_add_32(jump_dirty+vpage,vaddr,r,(void *)out);
11433 int entry_point=do_dirty_stub(i);
11434 ll_add_32(jump_in+page,vaddr,r,(void *)entry_point);
11439 // Write out the literal pool if necessary
11441 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
11443 if(((u_int)out)&7) emit_addnop(13);
11445 assert((u_int)out-beginning<MAX_OUTPUT_BLOCK_SIZE);
11446 //printf("shadow buffer: %x-%x\n",(int)copy,(int)copy+slen*4);
11447 memcpy(copy,source,slen*4);
11451 __clear_cache((void *)beginning,out);
11454 // If we're within 256K of the end of the buffer,
11455 // start over from the beginning. (Is 256K enough?)
11456 if((int)out>BASE_ADDR+(1<<TARGET_SIZE_2)-MAX_OUTPUT_BLOCK_SIZE) out=(u_char *)BASE_ADDR;
11458 // Trap writes to any of the pages we compiled
11459 for(i=start>>12;i<=(start+slen*4)>>12;i++) {
11461 #ifndef DISABLE_TLB
11462 memory_map[i]|=0x40000000;
11463 if((signed int)start>=(signed int)0xC0000000) {
11465 j=(((u_int)i<<12)+(memory_map[i]<<2)-(u_int)rdram+(u_int)0x80000000)>>12;
11467 memory_map[j]|=0x40000000;
11468 //printf("write protect physical page: %x (virtual %x)\n",j<<12,start);
11472 inv_code_start=inv_code_end=~0;
11474 // for PCSX we need to mark all mirrors too
11475 if(get_page(start)<(RAM_SIZE>>12))
11476 for(i=start>>12;i<=(start+slen*4)>>12;i++)
11477 invalid_code[((u_int)0x00000000>>12)|(i&0x1ff)]=
11478 invalid_code[((u_int)0x80000000>>12)|(i&0x1ff)]=
11479 invalid_code[((u_int)0xa0000000>>12)|(i&0x1ff)]=0;
11482 /* Pass 10 - Free memory by expiring oldest blocks */
11484 int end=((((int)out-BASE_ADDR)>>(TARGET_SIZE_2-16))+16384)&65535;
11485 while(expirep!=end)
11487 int shift=TARGET_SIZE_2-3; // Divide into 8 blocks
11488 int base=BASE_ADDR+((expirep>>13)<<shift); // Base address of this block
11489 inv_debug("EXP: Phase %d\n",expirep);
11490 switch((expirep>>11)&3)
11493 // Clear jump_in and jump_dirty
11494 ll_remove_matching_addrs(jump_in+(expirep&2047),base,shift);
11495 ll_remove_matching_addrs(jump_dirty+(expirep&2047),base,shift);
11496 ll_remove_matching_addrs(jump_in+2048+(expirep&2047),base,shift);
11497 ll_remove_matching_addrs(jump_dirty+2048+(expirep&2047),base,shift);
11501 ll_kill_pointers(jump_out[expirep&2047],base,shift);
11502 ll_kill_pointers(jump_out[(expirep&2047)+2048],base,shift);
11505 // Clear hash table
11506 for(i=0;i<32;i++) {
11507 int *ht_bin=hash_table[((expirep&2047)<<5)+i];
11508 if((ht_bin[3]>>shift)==(base>>shift) ||
11509 ((ht_bin[3]-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(base>>shift)) {
11510 inv_debug("EXP: Remove hash %x -> %x\n",ht_bin[2],ht_bin[3]);
11511 ht_bin[2]=ht_bin[3]=-1;
11513 if((ht_bin[1]>>shift)==(base>>shift) ||
11514 ((ht_bin[1]-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(base>>shift)) {
11515 inv_debug("EXP: Remove hash %x -> %x\n",ht_bin[0],ht_bin[1]);
11516 ht_bin[0]=ht_bin[2];
11517 ht_bin[1]=ht_bin[3];
11518 ht_bin[2]=ht_bin[3]=-1;
11525 if((expirep&2047)==0)
11528 ll_remove_matching_addrs(jump_out+(expirep&2047),base,shift);
11529 ll_remove_matching_addrs(jump_out+2048+(expirep&2047),base,shift);
11532 expirep=(expirep+1)&65535;
11537 // vim:shiftwidth=2:expandtab