libpcsxcore/new_dynarec/new_dynarec.c

   1 /* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
   2  *   Mupen64plus - new_dynarec.c                                           *
   3  *   Copyright (C) 2009-2011 Ari64                                         *
   4  *                                                                         *
   5  *   This program is free software; you can redistribute it and/or modify  *
   6  *   it under the terms of the GNU General Public License as published by  *
   7  *   the Free Software Foundation; either version 2 of the License, or     *
   8  *   (at your option) any later version.                                   *
   9  *                                                                         *
  10  *   This program is distributed in the hope that it will be useful,       *
  11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  13  *   GNU General Public License for more details.                          *
  14  *                                                                         *
  15  *   You should have received a copy of the GNU General Public License     *
  16  *   along with this program; if not, write to the                         *
  17  *   Free Software Foundation, Inc.,                                       *
  18  *   51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.          *
  19  * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
  20
  21 #include <stdlib.h>
  22 #include <stdint.h> //include for uint64_t
  23 #include <assert.h>
  24 #include <errno.h>
  25 #include <sys/mman.h>
  26
  27 #include "emu_if.h" //emulator interface
  28
  29 //#define DISASM
  30 //#define assem_debug printf
  31 //#define inv_debug printf
  32 #define assem_debug(...)
  33 #define inv_debug(...)
  34
  35 #ifdef __i386__
  36 #include "assem_x86.h"
  37 #endif
  38 #ifdef __x86_64__
  39 #include "assem_x64.h"
  40 #endif
  41 #ifdef __arm__
  42 #include "assem_arm.h"
  43 #endif
  44
  45 #ifdef __BLACKBERRY_QNX__
  46 #undef __clear_cache
  47 #define __clear_cache(start,end) msync(start, (size_t)((void*)end - (void*)start), MS_SYNC | MS_CACHE_ONLY | MS_INVALIDATE_ICACHE);
  48 #elif defined(__MACH__)
  49 #include <libkern/OSCacheControl.h>
  50 #define __clear_cache mach_clear_cache
  51 static void __clear_cache(void *start, void *end) {
  52   size_t len = (char *)end - (char *)start;
  53   sys_dcache_flush(start, len);
  54   sys_icache_invalidate(start, len);
  55 }
  56 #endif
  57
  58 #define MAXBLOCK 4096
  59 #define MAX_OUTPUT_BLOCK_SIZE 262144
  60
  61 struct regstat
  62 {
  63   signed char regmap_entry[HOST_REGS];
  64   signed char regmap[HOST_REGS];
  65   uint64_t was32;
  66   uint64_t is32;
  67   uint64_t wasdirty;
  68   uint64_t dirty;
  69   uint64_t u;
  70   uint64_t uu;
  71   u_int wasconst;
  72   u_int isconst;
  73   u_int loadedconst;             // host regs that have constants loaded
  74   u_int waswritten;              // MIPS regs that were used as store base before
  75 };
  76
  77 struct ll_entry
  78 {
  79   u_int vaddr;
  80   u_int reg32;
  81   void *addr;
  82   struct ll_entry *next;
  83 };
  84
  85   u_int start;
  86   u_int *source;
  87   u_int pagelimit;
  88   char insn[MAXBLOCK][10];
  89   u_char itype[MAXBLOCK];
  90   u_char opcode[MAXBLOCK];
  91   u_char opcode2[MAXBLOCK];
  92   u_char bt[MAXBLOCK];
  93   u_char rs1[MAXBLOCK];
  94   u_char rs2[MAXBLOCK];
  95   u_char rt1[MAXBLOCK];
  96   u_char rt2[MAXBLOCK];
  97   u_char us1[MAXBLOCK];
  98   u_char us2[MAXBLOCK];
  99   u_char dep1[MAXBLOCK];
 100   u_char dep2[MAXBLOCK];
 101   u_char lt1[MAXBLOCK];
 102   static uint64_t gte_rs[MAXBLOCK]; // gte: 32 data and 32 ctl regs
 103   static uint64_t gte_rt[MAXBLOCK];
 104   static uint64_t gte_unneeded[MAXBLOCK];
 105   static u_int smrv[32]; // speculated MIPS register values
 106   static u_int smrv_strong; // mask or regs that are likely to have correct values
 107   static u_int smrv_weak; // same, but somewhat less likely
 108   static u_int smrv_strong_next; // same, but after current insn executes
 109   static u_int smrv_weak_next;
 110   int imm[MAXBLOCK];
 111   u_int ba[MAXBLOCK];
 112   char likely[MAXBLOCK];
 113   char is_ds[MAXBLOCK];
 114   char ooo[MAXBLOCK];
 115   uint64_t unneeded_reg[MAXBLOCK];
 116   uint64_t unneeded_reg_upper[MAXBLOCK];
 117   uint64_t branch_unneeded_reg[MAXBLOCK];
 118   uint64_t branch_unneeded_reg_upper[MAXBLOCK];
 119   uint64_t p32[MAXBLOCK];
 120   uint64_t pr32[MAXBLOCK];
 121   signed char regmap_pre[MAXBLOCK][HOST_REGS];
 122   static uint64_t current_constmap[HOST_REGS];
 123   static uint64_t constmap[MAXBLOCK][HOST_REGS];
 124   static struct regstat regs[MAXBLOCK];
 125   static struct regstat branch_regs[MAXBLOCK];
 126   signed char minimum_free_regs[MAXBLOCK];
 127   u_int needed_reg[MAXBLOCK];
 128   uint64_t requires_32bit[MAXBLOCK];
 129   u_int wont_dirty[MAXBLOCK];
 130   u_int will_dirty[MAXBLOCK];
 131   int ccadj[MAXBLOCK];
 132   int slen;
 133   u_int instr_addr[MAXBLOCK];
 134   u_int link_addr[MAXBLOCK][3];
 135   int linkcount;
 136   u_int stubs[MAXBLOCK*3][8];
 137   int stubcount;
 138   u_int literals[1024][2];
 139   int literalcount;
 140   int is_delayslot;
 141   int cop1_usable;
 142   u_char *out;
 143   struct ll_entry *jump_in[4096];
 144   struct ll_entry *jump_out[4096];
 145   struct ll_entry *jump_dirty[4096];
 146   u_int hash_table[65536][4]  __attribute__((aligned(16)));
 147   char shadow[1048576]  __attribute__((aligned(16)));
 148   void *copy;
 149   int expirep;
 150 #ifndef PCSX
 151   u_int using_tlb;
 152 #else
 153   static const u_int using_tlb=0;
 154 #endif
 155   int new_dynarec_did_compile;
 156   int new_dynarec_hacks;
 157   u_int stop_after_jal;
 158 #ifndef RAM_FIXED
 159   static u_int ram_offset;
 160 #else
 161   static const u_int ram_offset=0;
 162 #endif
 163   extern u_char restore_candidate[512];
 164   extern int cycle_count;
 165
 166   /* registers that may be allocated */
 167   /* 1-31 gpr */
 168 #define HIREG 32 // hi
 169 #define LOREG 33 // lo
 170 #define FSREG 34 // FPU status (FCSR)
 171 #define CSREG 35 // Coprocessor status
 172 #define CCREG 36 // Cycle count
 173 #define INVCP 37 // Pointer to invalid_code
 174 #define MMREG 38 // Pointer to memory_map
 175 #define ROREG 39 // ram offset (if rdram!=0x80000000)
 176 #define TEMPREG 40
 177 #define FTEMP 40 // FPU temporary register
 178 #define PTEMP 41 // Prefetch temporary register
 179 #define TLREG 42 // TLB mapping offset
 180 #define RHASH 43 // Return address hash
 181 #define RHTBL 44 // Return address hash table address
 182 #define RTEMP 45 // JR/JALR address register
 183 #define MAXREG 45
 184 #define AGEN1 46 // Address generation temporary register
 185 #define AGEN2 47 // Address generation temporary register
 186 #define MGEN1 48 // Maptable address generation temporary register
 187 #define MGEN2 49 // Maptable address generation temporary register
 188 #define BTREG 50 // Branch target temporary register
 189
 190   /* instruction types */
 191 #define NOP 0     // No operation
 192 #define LOAD 1    // Load
 193 #define STORE 2   // Store
 194 #define LOADLR 3  // Unaligned load
 195 #define STORELR 4 // Unaligned store
 196 #define MOV 5     // Move
 197 #define ALU 6     // Arithmetic/logic
 198 #define MULTDIV 7 // Multiply/divide
 199 #define SHIFT 8   // Shift by register
 200 #define SHIFTIMM 9// Shift by immediate
 201 #define IMM16 10  // 16-bit immediate
 202 #define RJUMP 11  // Unconditional jump to register
 203 #define UJUMP 12  // Unconditional jump
 204 #define CJUMP 13  // Conditional branch (BEQ/BNE/BGTZ/BLEZ)
 205 #define SJUMP 14  // Conditional branch (regimm format)
 206 #define COP0 15   // Coprocessor 0
 207 #define COP1 16   // Coprocessor 1
 208 #define C1LS 17   // Coprocessor 1 load/store
 209 #define FJUMP 18  // Conditional branch (floating point)
 210 #define FLOAT 19  // Floating point unit
 211 #define FCONV 20  // Convert integer to float
 212 #define FCOMP 21  // Floating point compare (sets FSREG)
 213 #define SYSCALL 22// SYSCALL
 214 #define OTHER 23  // Other
 215 #define SPAN 24   // Branch/delay slot spans 2 pages
 216 #define NI 25     // Not implemented
 217 #define HLECALL 26// PCSX fake opcodes for HLE
 218 #define COP2 27   // Coprocessor 2 move
 219 #define C2LS 28   // Coprocessor 2 load/store
 220 #define C2OP 29   // Coprocessor 2 operation
 221 #define INTCALL 30// Call interpreter to handle rare corner cases
 222
 223   /* stubs */
 224 #define CC_STUB 1
 225 #define FP_STUB 2
 226 #define LOADB_STUB 3
 227 #define LOADH_STUB 4
 228 #define LOADW_STUB 5
 229 #define LOADD_STUB 6
 230 #define LOADBU_STUB 7
 231 #define LOADHU_STUB 8
 232 #define STOREB_STUB 9
 233 #define STOREH_STUB 10
 234 #define STOREW_STUB 11
 235 #define STORED_STUB 12
 236 #define STORELR_STUB 13
 237 #define INVCODE_STUB 14
 238
 239   /* branch codes */
 240 #define TAKEN 1
 241 #define NOTTAKEN 2
 242 #define NULLDS 3
 243
 244 // asm linkage
 245 int new_recompile_block(int addr);
 246 void *get_addr_ht(u_int vaddr);
 247 void invalidate_block(u_int block);
 248 void invalidate_addr(u_int addr);
 249 void remove_hash(int vaddr);
 250 void jump_vaddr();
 251 void dyna_linker();
 252 void dyna_linker_ds();
 253 void verify_code();
 254 void verify_code_vm();
 255 void verify_code_ds();
 256 void cc_interrupt();
 257 void fp_exception();
 258 void fp_exception_ds();
 259 void jump_syscall();
 260 void jump_syscall_hle();
 261 void jump_eret();
 262 void jump_hlecall();
 263 void jump_intcall();
 264 void new_dyna_leave();
 265
 266 // TLB
 267 void TLBWI_new();
 268 void TLBWR_new();
 269 void read_nomem_new();
 270 void read_nomemb_new();
 271 void read_nomemh_new();
 272 void read_nomemd_new();
 273 void write_nomem_new();
 274 void write_nomemb_new();
 275 void write_nomemh_new();
 276 void write_nomemd_new();
 277 void write_rdram_new();
 278 void write_rdramb_new();
 279 void write_rdramh_new();
 280 void write_rdramd_new();
 281 extern u_int memory_map[1048576];
 282
 283 // Needed by assembler
 284 void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32);
 285 void wb_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty);
 286 void wb_needed_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr);
 287 void load_all_regs(signed char i_regmap[]);
 288 void load_needed_regs(signed char i_regmap[],signed char next_regmap[]);
 289 void load_regs_entry(int t);
 290 void load_all_consts(signed char regmap[],int is32,u_int dirty,int i);
 291
 292 int tracedebug=0;
 293
 294 //#define DEBUG_CYCLE_COUNT 1
 295
 296 #define NO_CYCLE_PENALTY_THR 12
 297
 298 int cycle_multiplier; // 100 for 1.0
 299
 300 static int CLOCK_ADJUST(int x)
 301 {
 302   int s=(x>>31)|1;
 303   return (x * cycle_multiplier + s * 50) / 100;
 304 }
 305
 306 static void tlb_hacks()
 307 {
 308 #ifndef DISABLE_TLB
 309   // Goldeneye hack
 310   if (strncmp((char *) ROM_HEADER->nom, "GOLDENEYE",9) == 0)
 311   {
 312     u_int addr;
 313     int n;
 314     switch (ROM_HEADER->Country_code&0xFF)
 315     {
 316       case 0x45: // U
 317         addr=0x34b30;
 318         break;
 319       case 0x4A: // J
 320         addr=0x34b70;
 321         break;
 322       case 0x50: // E
 323         addr=0x329f0;
 324         break;
 325       default:
 326         // Unknown country code
 327         addr=0;
 328         break;
 329     }
 330     u_int rom_addr=(u_int)rom;
 331     #ifdef ROM_COPY
 332     // Since memory_map is 32-bit, on 64-bit systems the rom needs to be
 333     // in the lower 4G of memory to use this hack.  Copy it if necessary.
 334     if((void *)rom>(void *)0xffffffff) {
 335       munmap(ROM_COPY, 67108864);
 336       if(mmap(ROM_COPY, 12582912,
 337               PROT_READ | PROT_WRITE,
 338               MAP_FIXED | MAP_PRIVATE | MAP_ANONYMOUS,
 339               -1, 0) <= 0) {printf("mmap() failed\n");}
 340       memcpy(ROM_COPY,rom,12582912);
 341       rom_addr=(u_int)ROM_COPY;
 342     }
 343     #endif
 344     if(addr) {
 345       for(n=0x7F000;n<0x80000;n++) {
 346         memory_map[n]=(((u_int)(rom_addr+addr-0x7F000000))>>2)|0x40000000;
 347       }
 348     }
 349   }
 350 #endif
 351 }
 352
 353 static u_int get_page(u_int vaddr)
 354 {
 355 #ifndef PCSX
 356   u_int page=(vaddr^0x80000000)>>12;
 357 #else
 358   u_int page=vaddr&~0xe0000000;
 359   if (page < 0x1000000)
 360     page &= ~0x0e00000; // RAM mirrors
 361   page>>=12;
 362 #endif
 363 #ifndef DISABLE_TLB
 364   if(page>262143&&tlb_LUT_r[vaddr>>12]) page=(tlb_LUT_r[vaddr>>12]^0x80000000)>>12;
 365 #endif
 366   if(page>2048) page=2048+(page&2047);
 367   return page;
 368 }
 369
 370 #ifndef PCSX
 371 static u_int get_vpage(u_int vaddr)
 372 {
 373   u_int vpage=(vaddr^0x80000000)>>12;
 374 #ifndef DISABLE_TLB
 375   if(vpage>262143&&tlb_LUT_r[vaddr>>12]) vpage&=2047; // jump_dirty uses a hash of the virtual address instead
 376 #endif
 377   if(vpage>2048) vpage=2048+(vpage&2047);
 378   return vpage;
 379 }
 380 #else
 381 // no virtual mem in PCSX
 382 static u_int get_vpage(u_int vaddr)
 383 {
 384   return get_page(vaddr);
 385 }
 386 #endif
 387
 388 // Get address from virtual address
 389 // This is called from the recompiled JR/JALR instructions
 390 void *get_addr(u_int vaddr)
 391 {
 392   u_int page=get_page(vaddr);
 393   u_int vpage=get_vpage(vaddr);
 394   struct ll_entry *head;
 395   //printf("TRACE: count=%d next=%d (get_addr %x,page %d)\n",Count,next_interupt,vaddr,page);
 396   head=jump_in[page];
 397   while(head!=NULL) {
 398     if(head->vaddr==vaddr&&head->reg32==0) {
 399   //printf("TRACE: count=%d next=%d (get_addr match %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
 400       int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
 401       ht_bin[3]=ht_bin[1];
 402       ht_bin[2]=ht_bin[0];
 403       ht_bin[1]=(int)head->addr;
 404       ht_bin[0]=vaddr;
 405       return head->addr;
 406     }
 407     head=head->next;
 408   }
 409   head=jump_dirty[vpage];
 410   while(head!=NULL) {
 411     if(head->vaddr==vaddr&&head->reg32==0) {
 412       //printf("TRACE: count=%d next=%d (get_addr match dirty %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
 413       // Don't restore blocks which are about to expire from the cache
 414       if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
 415       if(verify_dirty(head->addr)) {
 416         //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]);
 417         invalid_code[vaddr>>12]=0;
 418         inv_code_start=inv_code_end=~0;
 419 #ifndef DISABLE_TLB
 420         memory_map[vaddr>>12]|=0x40000000;
 421 #endif
 422         if(vpage<2048) {
 423 #ifndef DISABLE_TLB
 424           if(tlb_LUT_r[vaddr>>12]) {
 425             invalid_code[tlb_LUT_r[vaddr>>12]>>12]=0;
 426             memory_map[tlb_LUT_r[vaddr>>12]>>12]|=0x40000000;
 427           }
 428 #endif
 429           restore_candidate[vpage>>3]|=1<<(vpage&7);
 430         }
 431         else restore_candidate[page>>3]|=1<<(page&7);
 432         int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
 433         if(ht_bin[0]==vaddr) {
 434           ht_bin[1]=(int)head->addr; // Replace existing entry
 435         }
 436         else
 437         {
 438           ht_bin[3]=ht_bin[1];
 439           ht_bin[2]=ht_bin[0];
 440           ht_bin[1]=(int)head->addr;
 441           ht_bin[0]=vaddr;
 442         }
 443         return head->addr;
 444       }
 445     }
 446     head=head->next;
 447   }
 448   //printf("TRACE: count=%d next=%d (get_addr no-match %x)\n",Count,next_interupt,vaddr);
 449   int r=new_recompile_block(vaddr);
 450   if(r==0) return get_addr(vaddr);
 451   // Execute in unmapped page, generate pagefault execption
 452   Status|=2;
 453   Cause=(vaddr<<31)|0x8;
 454   EPC=(vaddr&1)?vaddr-5:vaddr;
 455   BadVAddr=(vaddr&~1);
 456   Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0);
 457   EntryHi=BadVAddr&0xFFFFE000;
 458   return get_addr_ht(0x80000000);
 459 }
 460 // Look up address in hash table first
 461 void *get_addr_ht(u_int vaddr)
 462 {
 463   //printf("TRACE: count=%d next=%d (get_addr_ht %x)\n",Count,next_interupt,vaddr);
 464   int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
 465   if(ht_bin[0]==vaddr) return (void *)ht_bin[1];
 466   if(ht_bin[2]==vaddr) return (void *)ht_bin[3];
 467   return get_addr(vaddr);
 468 }
 469
 470 void *get_addr_32(u_int vaddr,u_int flags)
 471 {
 472 #ifdef FORCE32
 473   return get_addr(vaddr);
 474 #else
 475   //printf("TRACE: count=%d next=%d (get_addr_32 %x,flags %x)\n",Count,next_interupt,vaddr,flags);
 476   int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
 477   if(ht_bin[0]==vaddr) return (void *)ht_bin[1];
 478   if(ht_bin[2]==vaddr) return (void *)ht_bin[3];
 479   u_int page=get_page(vaddr);
 480   u_int vpage=get_vpage(vaddr);
 481   struct ll_entry *head;
 482   head=jump_in[page];
 483   while(head!=NULL) {
 484     if(head->vaddr==vaddr&&(head->reg32&flags)==0) {
 485       //printf("TRACE: count=%d next=%d (get_addr_32 match %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
 486       if(head->reg32==0) {
 487         int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
 488         if(ht_bin[0]==-1) {
 489           ht_bin[1]=(int)head->addr;
 490           ht_bin[0]=vaddr;
 491         }else if(ht_bin[2]==-1) {
 492           ht_bin[3]=(int)head->addr;
 493           ht_bin[2]=vaddr;
 494         }
 495         //ht_bin[3]=ht_bin[1];
 496         //ht_bin[2]=ht_bin[0];
 497         //ht_bin[1]=(int)head->addr;
 498         //ht_bin[0]=vaddr;
 499       }
 500       return head->addr;
 501     }
 502     head=head->next;
 503   }
 504   head=jump_dirty[vpage];
 505   while(head!=NULL) {
 506     if(head->vaddr==vaddr&&(head->reg32&flags)==0) {
 507       //printf("TRACE: count=%d next=%d (get_addr_32 match dirty %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
 508       // Don't restore blocks which are about to expire from the cache
 509       if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
 510       if(verify_dirty(head->addr)) {
 511         //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]);
 512         invalid_code[vaddr>>12]=0;
 513         inv_code_start=inv_code_end=~0;
 514         memory_map[vaddr>>12]|=0x40000000;
 515         if(vpage<2048) {
 516 #ifndef DISABLE_TLB
 517           if(tlb_LUT_r[vaddr>>12]) {
 518             invalid_code[tlb_LUT_r[vaddr>>12]>>12]=0;
 519             memory_map[tlb_LUT_r[vaddr>>12]>>12]|=0x40000000;
 520           }
 521 #endif
 522           restore_candidate[vpage>>3]|=1<<(vpage&7);
 523         }
 524         else restore_candidate[page>>3]|=1<<(page&7);
 525         if(head->reg32==0) {
 526           int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
 527           if(ht_bin[0]==-1) {
 528             ht_bin[1]=(int)head->addr;
 529             ht_bin[0]=vaddr;
 530           }else if(ht_bin[2]==-1) {
 531             ht_bin[3]=(int)head->addr;
 532             ht_bin[2]=vaddr;
 533           }
 534           //ht_bin[3]=ht_bin[1];
 535           //ht_bin[2]=ht_bin[0];
 536           //ht_bin[1]=(int)head->addr;
 537           //ht_bin[0]=vaddr;
 538         }
 539         return head->addr;
 540       }
 541     }
 542     head=head->next;
 543   }
 544   //printf("TRACE: count=%d next=%d (get_addr_32 no-match %x,flags %x)\n",Count,next_interupt,vaddr,flags);
 545   int r=new_recompile_block(vaddr);
 546   if(r==0) return get_addr(vaddr);
 547   // Execute in unmapped page, generate pagefault execption
 548   Status|=2;
 549   Cause=(vaddr<<31)|0x8;
 550   EPC=(vaddr&1)?vaddr-5:vaddr;
 551   BadVAddr=(vaddr&~1);
 552   Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0);
 553   EntryHi=BadVAddr&0xFFFFE000;
 554   return get_addr_ht(0x80000000);
 555 #endif
 556 }
 557
 558 void clear_all_regs(signed char regmap[])
 559 {
 560   int hr;
 561   for (hr=0;hr<HOST_REGS;hr++) regmap[hr]=-1;
 562 }
 563
 564 signed char get_reg(signed char regmap[],int r)
 565 {
 566   int hr;
 567   for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&&regmap[hr]==r) return hr;
 568   return -1;
 569 }
 570
 571 // Find a register that is available for two consecutive cycles
 572 signed char get_reg2(signed char regmap1[],signed char regmap2[],int r)
 573 {
 574   int hr;
 575   for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&&regmap1[hr]==r&&regmap2[hr]==r) return hr;
 576   return -1;
 577 }
 578
 579 int count_free_regs(signed char regmap[])
 580 {
 581   int count=0;
 582   int hr;
 583   for(hr=0;hr<HOST_REGS;hr++)
 584   {
 585     if(hr!=EXCLUDE_REG) {
 586       if(regmap[hr]<0) count++;
 587     }
 588   }
 589   return count;
 590 }
 591
 592 void dirty_reg(struct regstat *cur,signed char reg)
 593 {
 594   int hr;
 595   if(!reg) return;
 596   for (hr=0;hr<HOST_REGS;hr++) {
 597     if((cur->regmap[hr]&63)==reg) {
 598       cur->dirty|=1<<hr;
 599     }
 600   }
 601 }
 602
 603 // If we dirty the lower half of a 64 bit register which is now being
 604 // sign-extended, we need to dump the upper half.
 605 // Note: Do this only after completion of the instruction, because
 606 // some instructions may need to read the full 64-bit value even if
 607 // overwriting it (eg SLTI, DSRA32).
 608 static void flush_dirty_uppers(struct regstat *cur)
 609 {
 610   int hr,reg;
 611   for (hr=0;hr<HOST_REGS;hr++) {
 612     if((cur->dirty>>hr)&1) {
 613       reg=cur->regmap[hr];
 614       if(reg>=64)
 615         if((cur->is32>>(reg&63))&1) cur->regmap[hr]=-1;
 616     }
 617   }
 618 }
 619
 620 void set_const(struct regstat *cur,signed char reg,uint64_t value)
 621 {
 622   int hr;
 623   if(!reg) return;
 624   for (hr=0;hr<HOST_REGS;hr++) {
 625     if(cur->regmap[hr]==reg) {
 626       cur->isconst|=1<<hr;
 627       current_constmap[hr]=value;
 628     }
 629     else if((cur->regmap[hr]^64)==reg) {
 630       cur->isconst|=1<<hr;
 631       current_constmap[hr]=value>>32;
 632     }
 633   }
 634 }
 635
 636 void clear_const(struct regstat *cur,signed char reg)
 637 {
 638   int hr;
 639   if(!reg) return;
 640   for (hr=0;hr<HOST_REGS;hr++) {
 641     if((cur->regmap[hr]&63)==reg) {
 642       cur->isconst&=~(1<<hr);
 643     }
 644   }
 645 }
 646
 647 int is_const(struct regstat *cur,signed char reg)
 648 {
 649   int hr;
 650   if(reg<0) return 0;
 651   if(!reg) return 1;
 652   for (hr=0;hr<HOST_REGS;hr++) {
 653     if((cur->regmap[hr]&63)==reg) {
 654       return (cur->isconst>>hr)&1;
 655     }
 656   }
 657   return 0;
 658 }
 659 uint64_t get_const(struct regstat *cur,signed char reg)
 660 {
 661   int hr;
 662   if(!reg) return 0;
 663   for (hr=0;hr<HOST_REGS;hr++) {
 664     if(cur->regmap[hr]==reg) {
 665       return current_constmap[hr];
 666     }
 667   }
 668   SysPrintf("Unknown constant in r%d\n",reg);
 669   exit(1);
 670 }
 671
 672 // Least soon needed registers
 673 // Look at the next ten instructions and see which registers
 674 // will be used.  Try not to reallocate these.
 675 void lsn(u_char hsn[], int i, int *preferred_reg)
 676 {
 677   int j;
 678   int b=-1;
 679   for(j=0;j<9;j++)
 680   {
 681     if(i+j>=slen) {
 682       j=slen-i-1;
 683       break;
 684     }
 685     if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
 686     {
 687       // Don't go past an unconditonal jump
 688       j++;
 689       break;
 690     }
 691   }
 692   for(;j>=0;j--)
 693   {
 694     if(rs1[i+j]) hsn[rs1[i+j]]=j;
 695     if(rs2[i+j]) hsn[rs2[i+j]]=j;
 696     if(rt1[i+j]) hsn[rt1[i+j]]=j;
 697     if(rt2[i+j]) hsn[rt2[i+j]]=j;
 698     if(itype[i+j]==STORE || itype[i+j]==STORELR) {
 699       // Stores can allocate zero
 700       hsn[rs1[i+j]]=j;
 701       hsn[rs2[i+j]]=j;
 702     }
 703     // On some architectures stores need invc_ptr
 704     #if defined(HOST_IMM8)
 705     if(itype[i+j]==STORE || itype[i+j]==STORELR || (opcode[i+j]&0x3b)==0x39 || (opcode[i+j]&0x3b)==0x3a) {
 706       hsn[INVCP]=j;
 707     }
 708     #endif
 709     if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP))
 710     {
 711       hsn[CCREG]=j;
 712       b=j;
 713     }
 714   }
 715   if(b>=0)
 716   {
 717     if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
 718     {
 719       // Follow first branch
 720       int t=(ba[i+b]-start)>>2;
 721       j=7-b;if(t+j>=slen) j=slen-t-1;
 722       for(;j>=0;j--)
 723       {
 724         if(rs1[t+j]) if(hsn[rs1[t+j]]>j+b+2) hsn[rs1[t+j]]=j+b+2;
 725         if(rs2[t+j]) if(hsn[rs2[t+j]]>j+b+2) hsn[rs2[t+j]]=j+b+2;
 726         //if(rt1[t+j]) if(hsn[rt1[t+j]]>j+b+2) hsn[rt1[t+j]]=j+b+2;
 727         //if(rt2[t+j]) if(hsn[rt2[t+j]]>j+b+2) hsn[rt2[t+j]]=j+b+2;
 728       }
 729     }
 730     // TODO: preferred register based on backward branch
 731   }
 732   // Delay slot should preferably not overwrite branch conditions or cycle count
 733   if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)) {
 734     if(rs1[i-1]) if(hsn[rs1[i-1]]>1) hsn[rs1[i-1]]=1;
 735     if(rs2[i-1]) if(hsn[rs2[i-1]]>1) hsn[rs2[i-1]]=1;
 736     hsn[CCREG]=1;
 737     // ...or hash tables
 738     hsn[RHASH]=1;
 739     hsn[RHTBL]=1;
 740   }
 741   // Coprocessor load/store needs FTEMP, even if not declared
 742   if(itype[i]==C1LS||itype[i]==C2LS) {
 743     hsn[FTEMP]=0;
 744   }
 745   // Load L/R also uses FTEMP as a temporary register
 746   if(itype[i]==LOADLR) {
 747     hsn[FTEMP]=0;
 748   }
 749   // Also SWL/SWR/SDL/SDR
 750   if(opcode[i]==0x2a||opcode[i]==0x2e||opcode[i]==0x2c||opcode[i]==0x2d) {
 751     hsn[FTEMP]=0;
 752   }
 753   // Don't remove the TLB registers either
 754   if(itype[i]==LOAD || itype[i]==LOADLR || itype[i]==STORE || itype[i]==STORELR || itype[i]==C1LS || itype[i]==C2LS) {
 755     hsn[TLREG]=0;
 756   }
 757   // Don't remove the miniht registers
 758   if(itype[i]==UJUMP||itype[i]==RJUMP)
 759   {
 760     hsn[RHASH]=0;
 761     hsn[RHTBL]=0;
 762   }
 763 }
 764
 765 // We only want to allocate registers if we're going to use them again soon
 766 int needed_again(int r, int i)
 767 {
 768   int j;
 769   int b=-1;
 770   int rn=10;
 771
 772   if(i>0&&(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000))
 773   {
 774     if(ba[i-1]<start || ba[i-1]>start+slen*4-4)
 775       return 0; // Don't need any registers if exiting the block
 776   }
 777   for(j=0;j<9;j++)
 778   {
 779     if(i+j>=slen) {
 780       j=slen-i-1;
 781       break;
 782     }
 783     if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
 784     {
 785       // Don't go past an unconditonal jump
 786       j++;
 787       break;
 788     }
 789     if(itype[i+j]==SYSCALL||itype[i+j]==HLECALL||itype[i+j]==INTCALL||((source[i+j]&0xfc00003f)==0x0d))
 790     {
 791       break;
 792     }
 793   }
 794   for(;j>=1;j--)
 795   {
 796     if(rs1[i+j]==r) rn=j;
 797     if(rs2[i+j]==r) rn=j;
 798     if((unneeded_reg[i+j]>>r)&1) rn=10;
 799     if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP))
 800     {
 801       b=j;
 802     }
 803   }
 804   /*
 805   if(b>=0)
 806   {
 807     if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
 808     {
 809       // Follow first branch
 810       int o=rn;
 811       int t=(ba[i+b]-start)>>2;
 812       j=7-b;if(t+j>=slen) j=slen-t-1;
 813       for(;j>=0;j--)
 814       {
 815         if(!((unneeded_reg[t+j]>>r)&1)) {
 816           if(rs1[t+j]==r) if(rn>j+b+2) rn=j+b+2;
 817           if(rs2[t+j]==r) if(rn>j+b+2) rn=j+b+2;
 818         }
 819         else rn=o;
 820       }
 821     }
 822   }*/
 823   if(rn<10) return 1;
 824   return 0;
 825 }
 826
 827 // Try to match register allocations at the end of a loop with those
 828 // at the beginning
 829 int loop_reg(int i, int r, int hr)
 830 {
 831   int j,k;
 832   for(j=0;j<9;j++)
 833   {
 834     if(i+j>=slen) {
 835       j=slen-i-1;
 836       break;
 837     }
 838     if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
 839     {
 840       // Don't go past an unconditonal jump
 841       j++;
 842       break;
 843     }
 844   }
 845   k=0;
 846   if(i>0){
 847     if(itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)
 848       k--;
 849   }
 850   for(;k<j;k++)
 851   {
 852     if(r<64&&((unneeded_reg[i+k]>>r)&1)) return hr;
 853     if(r>64&&((unneeded_reg_upper[i+k]>>r)&1)) return hr;
 854     if(i+k>=0&&(itype[i+k]==UJUMP||itype[i+k]==CJUMP||itype[i+k]==SJUMP||itype[i+k]==FJUMP))
 855     {
 856       if(ba[i+k]>=start && ba[i+k]<(start+i*4))
 857       {
 858         int t=(ba[i+k]-start)>>2;
 859         int reg=get_reg(regs[t].regmap_entry,r);
 860         if(reg>=0) return reg;
 861         //reg=get_reg(regs[t+1].regmap_entry,r);
 862         //if(reg>=0) return reg;
 863       }
 864     }
 865   }
 866   return hr;
 867 }
 868
 869
 870 // Allocate every register, preserving source/target regs
 871 void alloc_all(struct regstat *cur,int i)
 872 {
 873   int hr;
 874
 875   for(hr=0;hr<HOST_REGS;hr++) {
 876     if(hr!=EXCLUDE_REG) {
 877       if(((cur->regmap[hr]&63)!=rs1[i])&&((cur->regmap[hr]&63)!=rs2[i])&&
 878          ((cur->regmap[hr]&63)!=rt1[i])&&((cur->regmap[hr]&63)!=rt2[i]))
 879       {
 880         cur->regmap[hr]=-1;
 881         cur->dirty&=~(1<<hr);
 882       }
 883       // Don't need zeros
 884       if((cur->regmap[hr]&63)==0)
 885       {
 886         cur->regmap[hr]=-1;
 887         cur->dirty&=~(1<<hr);
 888       }
 889     }
 890   }
 891 }
 892
 893 #ifndef FORCE32
 894 void div64(int64_t dividend,int64_t divisor)
 895 {
 896   lo=dividend/divisor;
 897   hi=dividend%divisor;
 898   //printf("TRACE: ddiv %8x%8x %8x%8x\n" ,(int)reg[HIREG],(int)(reg[HIREG]>>32)
 899   //                                     ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
 900 }
 901 void divu64(uint64_t dividend,uint64_t divisor)
 902 {
 903   lo=dividend/divisor;
 904   hi=dividend%divisor;
 905   //printf("TRACE: ddivu %8x%8x %8x%8x\n",(int)reg[HIREG],(int)(reg[HIREG]>>32)
 906   //                                     ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
 907 }
 908
 909 void mult64(uint64_t m1,uint64_t m2)
 910 {
 911    unsigned long long int op1, op2, op3, op4;
 912    unsigned long long int result1, result2, result3, result4;
 913    unsigned long long int temp1, temp2, temp3, temp4;
 914    int sign = 0;
 915
 916    if (m1 < 0)
 917      {
 918     op2 = -m1;
 919     sign = 1 - sign;
 920      }
 921    else op2 = m1;
 922    if (m2 < 0)
 923      {
 924     op4 = -m2;
 925     sign = 1 - sign;
 926      }
 927    else op4 = m2;
 928
 929    op1 = op2 & 0xFFFFFFFF;
 930    op2 = (op2 >> 32) & 0xFFFFFFFF;
 931    op3 = op4 & 0xFFFFFFFF;
 932    op4 = (op4 >> 32) & 0xFFFFFFFF;
 933
 934    temp1 = op1 * op3;
 935    temp2 = (temp1 >> 32) + op1 * op4;
 936    temp3 = op2 * op3;
 937    temp4 = (temp3 >> 32) + op2 * op4;
 938
 939    result1 = temp1 & 0xFFFFFFFF;
 940    result2 = temp2 + (temp3 & 0xFFFFFFFF);
 941    result3 = (result2 >> 32) + temp4;
 942    result4 = (result3 >> 32);
 943
 944    lo = result1 | (result2 << 32);
 945    hi = (result3 & 0xFFFFFFFF) | (result4 << 32);
 946    if (sign)
 947      {
 948     hi = ~hi;
 949     if (!lo) hi++;
 950     else lo = ~lo + 1;
 951      }
 952 }
 953
 954 void multu64(uint64_t m1,uint64_t m2)
 955 {
 956    unsigned long long int op1, op2, op3, op4;
 957    unsigned long long int result1, result2, result3, result4;
 958    unsigned long long int temp1, temp2, temp3, temp4;
 959
 960    op1 = m1 & 0xFFFFFFFF;
 961    op2 = (m1 >> 32) & 0xFFFFFFFF;
 962    op3 = m2 & 0xFFFFFFFF;
 963    op4 = (m2 >> 32) & 0xFFFFFFFF;
 964
 965    temp1 = op1 * op3;
 966    temp2 = (temp1 >> 32) + op1 * op4;
 967    temp3 = op2 * op3;
 968    temp4 = (temp3 >> 32) + op2 * op4;
 969
 970    result1 = temp1 & 0xFFFFFFFF;
 971    result2 = temp2 + (temp3 & 0xFFFFFFFF);
 972    result3 = (result2 >> 32) + temp4;
 973    result4 = (result3 >> 32);
 974
 975    lo = result1 | (result2 << 32);
 976    hi = (result3 & 0xFFFFFFFF) | (result4 << 32);
 977
 978   //printf("TRACE: dmultu %8x%8x %8x%8x\n",(int)reg[HIREG],(int)(reg[HIREG]>>32)
 979   //                                      ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
 980 }
 981
 982 uint64_t ldl_merge(uint64_t original,uint64_t loaded,u_int bits)
 983 {
 984   if(bits) {
 985     original<<=64-bits;
 986     original>>=64-bits;
 987     loaded<<=bits;
 988     original|=loaded;
 989   }
 990   else original=loaded;
 991   return original;
 992 }
 993 uint64_t ldr_merge(uint64_t original,uint64_t loaded,u_int bits)
 994 {
 995   if(bits^56) {
 996     original>>=64-(bits^56);
 997     original<<=64-(bits^56);
 998     loaded>>=bits^56;
 999     original|=loaded;
1000   }
1001   else original=loaded;
1002   return original;
1003 }
1004 #endif
1005
1006 #ifdef __i386__
1007 #include "assem_x86.c"
1008 #endif
1009 #ifdef __x86_64__
1010 #include "assem_x64.c"
1011 #endif
1012 #ifdef __arm__
1013 #include "assem_arm.c"
1014 #endif
1015
1016 // Add virtual address mapping to linked list
1017 void ll_add(struct ll_entry **head,int vaddr,void *addr)
1018 {
1019   struct ll_entry *new_entry;
1020   new_entry=malloc(sizeof(struct ll_entry));
1021   assert(new_entry!=NULL);
1022   new_entry->vaddr=vaddr;
1023   new_entry->reg32=0;
1024   new_entry->addr=addr;
1025   new_entry->next=*head;
1026   *head=new_entry;
1027 }
1028
1029 // Add virtual address mapping for 32-bit compiled block
1030 void ll_add_32(struct ll_entry **head,int vaddr,u_int reg32,void *addr)
1031 {
1032   ll_add(head,vaddr,addr);
1033 #ifndef FORCE32
1034   (*head)->reg32=reg32;
1035 #endif
1036 }
1037
1038 // Check if an address is already compiled
1039 // but don't return addresses which are about to expire from the cache
1040 void *check_addr(u_int vaddr)
1041 {
1042   u_int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
1043   if(ht_bin[0]==vaddr) {
1044     if(((ht_bin[1]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
1045       if(isclean(ht_bin[1])) return (void *)ht_bin[1];
1046   }
1047   if(ht_bin[2]==vaddr) {
1048     if(((ht_bin[3]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
1049       if(isclean(ht_bin[3])) return (void *)ht_bin[3];
1050   }
1051   u_int page=get_page(vaddr);
1052   struct ll_entry *head;
1053   head=jump_in[page];
1054   while(head!=NULL) {
1055     if(head->vaddr==vaddr&&head->reg32==0) {
1056       if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1057         // Update existing entry with current address
1058         if(ht_bin[0]==vaddr) {
1059           ht_bin[1]=(int)head->addr;
1060           return head->addr;
1061         }
1062         if(ht_bin[2]==vaddr) {
1063           ht_bin[3]=(int)head->addr;
1064           return head->addr;
1065         }
1066         // Insert into hash table with low priority.
1067         // Don't evict existing entries, as they are probably
1068         // addresses that are being accessed frequently.
1069         if(ht_bin[0]==-1) {
1070           ht_bin[1]=(int)head->addr;
1071           ht_bin[0]=vaddr;
1072         }else if(ht_bin[2]==-1) {
1073           ht_bin[3]=(int)head->addr;
1074           ht_bin[2]=vaddr;
1075         }
1076         return head->addr;
1077       }
1078     }
1079     head=head->next;
1080   }
1081   return 0;
1082 }
1083
1084 void remove_hash(int vaddr)
1085 {
1086   //printf("remove hash: %x\n",vaddr);
1087   int *ht_bin=hash_table[(((vaddr)>>16)^vaddr)&0xFFFF];
1088   if(ht_bin[2]==vaddr) {
1089     ht_bin[2]=ht_bin[3]=-1;
1090   }
1091   if(ht_bin[0]==vaddr) {
1092     ht_bin[0]=ht_bin[2];
1093     ht_bin[1]=ht_bin[3];
1094     ht_bin[2]=ht_bin[3]=-1;
1095   }
1096 }
1097
1098 void ll_remove_matching_addrs(struct ll_entry **head,int addr,int shift)
1099 {
1100   struct ll_entry *next;
1101   while(*head) {
1102     if(((u_int)((*head)->addr)>>shift)==(addr>>shift) ||
1103        ((u_int)((*head)->addr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift))
1104     {
1105       inv_debug("EXP: Remove pointer to %x (%x)\n",(int)(*head)->addr,(*head)->vaddr);
1106       remove_hash((*head)->vaddr);
1107       next=(*head)->next;
1108       free(*head);
1109       *head=next;
1110     }
1111     else
1112     {
1113       head=&((*head)->next);
1114     }
1115   }
1116 }
1117
1118 // Remove all entries from linked list
1119 void ll_clear(struct ll_entry **head)
1120 {
1121   struct ll_entry *cur;
1122   struct ll_entry *next;
1123   if(cur=*head) {
1124     *head=0;
1125     while(cur) {
1126       next=cur->next;
1127       free(cur);
1128       cur=next;
1129     }
1130   }
1131 }
1132
1133 // Dereference the pointers and remove if it matches
1134 void ll_kill_pointers(struct ll_entry *head,int addr,int shift)
1135 {
1136   while(head) {
1137     int ptr=get_pointer(head->addr);
1138     inv_debug("EXP: Lookup pointer to %x at %x (%x)\n",(int)ptr,(int)head->addr,head->vaddr);
1139     if(((ptr>>shift)==(addr>>shift)) ||
1140        (((ptr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift)))
1141     {
1142       inv_debug("EXP: Kill pointer at %x (%x)\n",(int)head->addr,head->vaddr);
1143       u_int host_addr=(u_int)kill_pointer(head->addr);
1144       #ifdef __arm__
1145         needs_clear_cache[(host_addr-(u_int)BASE_ADDR)>>17]|=1<<(((host_addr-(u_int)BASE_ADDR)>>12)&31);
1146       #endif
1147     }
1148     head=head->next;
1149   }
1150 }
1151
1152 // This is called when we write to a compiled block (see do_invstub)
1153 void invalidate_page(u_int page)
1154 {
1155   struct ll_entry *head;
1156   struct ll_entry *next;
1157   head=jump_in[page];
1158   jump_in[page]=0;
1159   while(head!=NULL) {
1160     inv_debug("INVALIDATE: %x\n",head->vaddr);
1161     remove_hash(head->vaddr);
1162     next=head->next;
1163     free(head);
1164     head=next;
1165   }
1166   head=jump_out[page];
1167   jump_out[page]=0;
1168   while(head!=NULL) {
1169     inv_debug("INVALIDATE: kill pointer to %x (%x)\n",head->vaddr,(int)head->addr);
1170     u_int host_addr=(u_int)kill_pointer(head->addr);
1171     #ifdef __arm__
1172       needs_clear_cache[(host_addr-(u_int)BASE_ADDR)>>17]|=1<<(((host_addr-(u_int)BASE_ADDR)>>12)&31);
1173     #endif
1174     next=head->next;
1175     free(head);
1176     head=next;
1177   }
1178 }
1179
1180 static void invalidate_block_range(u_int block, u_int first, u_int last)
1181 {
1182   u_int page=get_page(block<<12);
1183   //printf("first=%d last=%d\n",first,last);
1184   invalidate_page(page);
1185   assert(first+5>page); // NB: this assumes MAXBLOCK<=4096 (4 pages)
1186   assert(last<page+5);
1187   // Invalidate the adjacent pages if a block crosses a 4K boundary
1188   while(first<page) {
1189     invalidate_page(first);
1190     first++;
1191   }
1192   for(first=page+1;first<last;first++) {
1193     invalidate_page(first);
1194   }
1195   #ifdef __arm__
1196     do_clear_cache();
1197   #endif
1198
1199   // Don't trap writes
1200   invalid_code[block]=1;
1201 #ifndef DISABLE_TLB
1202   // If there is a valid TLB entry for this page, remove write protect
1203   if(tlb_LUT_w[block]) {
1204     assert(tlb_LUT_r[block]==tlb_LUT_w[block]);
1205     // CHECK: Is this right?
1206     memory_map[block]=((tlb_LUT_w[block]&0xFFFFF000)-(block<<12)+(unsigned int)rdram-0x80000000)>>2;
1207     u_int real_block=tlb_LUT_w[block]>>12;
1208     invalid_code[real_block]=1;
1209     if(real_block>=0x80000&&real_block<0x80800) memory_map[real_block]=((u_int)rdram-0x80000000)>>2;
1210   }
1211   else if(block>=0x80000&&block<0x80800) memory_map[block]=((u_int)rdram-0x80000000)>>2;
1212 #endif
1213
1214   #ifdef USE_MINI_HT
1215   memset(mini_ht,-1,sizeof(mini_ht));
1216   #endif
1217 }
1218
1219 void invalidate_block(u_int block)
1220 {
1221   u_int page=get_page(block<<12);
1222   u_int vpage=get_vpage(block<<12);
1223   inv_debug("INVALIDATE: %x (%d)\n",block<<12,page);
1224   //inv_debug("invalid_code[block]=%d\n",invalid_code[block]);
1225   u_int first,last;
1226   first=last=page;
1227   struct ll_entry *head;
1228   head=jump_dirty[vpage];
1229   //printf("page=%d vpage=%d\n",page,vpage);
1230   while(head!=NULL) {
1231     u_int start,end;
1232     if(vpage>2047||(head->vaddr>>12)==block) { // Ignore vaddr hash collision
1233       get_bounds((int)head->addr,&start,&end);
1234       //printf("start: %x end: %x\n",start,end);
1235       if(page<2048&&start>=(u_int)rdram&&end<(u_int)rdram+RAM_SIZE) {
1236         if(((start-(u_int)rdram)>>12)<=page&&((end-1-(u_int)rdram)>>12)>=page) {
1237           if((((start-(u_int)rdram)>>12)&2047)<first) first=((start-(u_int)rdram)>>12)&2047;
1238           if((((end-1-(u_int)rdram)>>12)&2047)>last) last=((end-1-(u_int)rdram)>>12)&2047;
1239         }
1240       }
1241 #ifndef DISABLE_TLB
1242       if(page<2048&&(signed int)start>=(signed int)0xC0000000&&(signed int)end>=(signed int)0xC0000000) {
1243         if(((start+memory_map[start>>12]-(u_int)rdram)>>12)<=page&&((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)>=page) {
1244           if((((start+memory_map[start>>12]-(u_int)rdram)>>12)&2047)<first) first=((start+memory_map[start>>12]-(u_int)rdram)>>12)&2047;
1245           if((((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)&2047)>last) last=((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)&2047;
1246         }
1247       }
1248 #endif
1249     }
1250     head=head->next;
1251   }
1252   invalidate_block_range(block,first,last);
1253 }
1254
1255 void invalidate_addr(u_int addr)
1256 {
1257 #ifdef PCSX
1258   //static int rhits;
1259   // this check is done by the caller
1260   //if (inv_code_start<=addr&&addr<=inv_code_end) { rhits++; return; }
1261   u_int page=get_vpage(addr);
1262   if(page<2048) { // RAM
1263     struct ll_entry *head;
1264     u_int addr_min=~0, addr_max=0;
1265     u_int mask=RAM_SIZE-1;
1266     u_int addr_main=0x80000000|(addr&mask);
1267     int pg1;
1268     inv_code_start=addr_main&~0xfff;
1269     inv_code_end=addr_main|0xfff;
1270     pg1=page;
1271     if (pg1>0) {
1272       // must check previous page too because of spans..
1273       pg1--;
1274       inv_code_start-=0x1000;
1275     }
1276     for(;pg1<=page;pg1++) {
1277       for(head=jump_dirty[pg1];head!=NULL;head=head->next) {
1278         u_int start,end;
1279         get_bounds((int)head->addr,&start,&end);
1280         if(ram_offset) {
1281           start-=ram_offset;
1282           end-=ram_offset;
1283         }
1284         if(start<=addr_main&&addr_main<end) {
1285           if(start<addr_min) addr_min=start;
1286           if(end>addr_max) addr_max=end;
1287         }
1288         else if(addr_main<start) {
1289           if(start<inv_code_end)
1290             inv_code_end=start-1;
1291         }
1292         else {
1293           if(end>inv_code_start)
1294             inv_code_start=end;
1295         }
1296       }
1297     }
1298     if (addr_min!=~0) {
1299       inv_debug("INV ADDR: %08x hit %08x-%08x\n", addr, addr_min, addr_max);
1300       inv_code_start=inv_code_end=~0;
1301       invalidate_block_range(addr>>12,(addr_min&mask)>>12,(addr_max&mask)>>12);
1302       return;
1303     }
1304     else {
1305       inv_code_start=(addr&~mask)|(inv_code_start&mask);
1306       inv_code_end=(addr&~mask)|(inv_code_end&mask);
1307       inv_debug("INV ADDR: %08x miss, inv %08x-%08x, sk %d\n", addr, inv_code_start, inv_code_end, 0);
1308       return;
1309     }
1310   }
1311 #endif
1312   invalidate_block(addr>>12);
1313 }
1314
1315 // This is called when loading a save state.
1316 // Anything could have changed, so invalidate everything.
1317 void invalidate_all_pages()
1318 {
1319   u_int page,n;
1320   for(page=0;page<4096;page++)
1321     invalidate_page(page);
1322   for(page=0;page<1048576;page++)
1323     if(!invalid_code[page]) {
1324       restore_candidate[(page&2047)>>3]|=1<<(page&7);
1325       restore_candidate[((page&2047)>>3)+256]|=1<<(page&7);
1326     }
1327   #ifdef __arm__
1328   __clear_cache((void *)BASE_ADDR,(void *)BASE_ADDR+(1<<TARGET_SIZE_2));
1329   #endif
1330   #ifdef USE_MINI_HT
1331   memset(mini_ht,-1,sizeof(mini_ht));
1332   #endif
1333   #ifndef DISABLE_TLB
1334   // TLB
1335   for(page=0;page<0x100000;page++) {
1336     if(tlb_LUT_r[page]) {
1337       memory_map[page]=((tlb_LUT_r[page]&0xFFFFF000)-(page<<12)+(unsigned int)rdram-0x80000000)>>2;
1338       if(!tlb_LUT_w[page]||!invalid_code[page])
1339         memory_map[page]|=0x40000000; // Write protect
1340     }
1341     else memory_map[page]=-1;
1342     if(page==0x80000) page=0xC0000;
1343   }
1344   tlb_hacks();
1345   #endif
1346 }
1347
1348 // Add an entry to jump_out after making a link
1349 void add_link(u_int vaddr,void *src)
1350 {
1351   u_int page=get_page(vaddr);
1352   inv_debug("add_link: %x -> %x (%d)\n",(int)src,vaddr,page);
1353   int *ptr=(int *)(src+4);
1354   assert((*ptr&0x0fff0000)==0x059f0000);
1355   ll_add(jump_out+page,vaddr,src);
1356   //int ptr=get_pointer(src);
1357   //inv_debug("add_link: Pointer is to %x\n",(int)ptr);
1358 }
1359
1360 // If a code block was found to be unmodified (bit was set in
1361 // restore_candidate) and it remains unmodified (bit is clear
1362 // in invalid_code) then move the entries for that 4K page from
1363 // the dirty list to the clean list.
1364 void clean_blocks(u_int page)
1365 {
1366   struct ll_entry *head;
1367   inv_debug("INV: clean_blocks page=%d\n",page);
1368   head=jump_dirty[page];
1369   while(head!=NULL) {
1370     if(!invalid_code[head->vaddr>>12]) {
1371       // Don't restore blocks which are about to expire from the cache
1372       if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1373         u_int start,end;
1374         if(verify_dirty((int)head->addr)) {
1375           //printf("Possibly Restore %x (%x)\n",head->vaddr, (int)head->addr);
1376           u_int i;
1377           u_int inv=0;
1378           get_bounds((int)head->addr,&start,&end);
1379           if(start-(u_int)rdram<RAM_SIZE) {
1380             for(i=(start-(u_int)rdram+0x80000000)>>12;i<=(end-1-(u_int)rdram+0x80000000)>>12;i++) {
1381               inv|=invalid_code[i];
1382             }
1383           }
1384 #ifndef DISABLE_TLB
1385           if((signed int)head->vaddr>=(signed int)0xC0000000) {
1386             u_int addr = (head->vaddr+(memory_map[head->vaddr>>12]<<2));
1387             //printf("addr=%x start=%x end=%x\n",addr,start,end);
1388             if(addr<start||addr>=end) inv=1;
1389           }
1390 #endif
1391           else if((signed int)head->vaddr>=(signed int)0x80000000+RAM_SIZE) {
1392             inv=1;
1393           }
1394           if(!inv) {
1395             void * clean_addr=(void *)get_clean_addr((int)head->addr);
1396             if((((u_int)clean_addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1397               u_int ppage=page;
1398 #ifndef DISABLE_TLB
1399               if(page<2048&&tlb_LUT_r[head->vaddr>>12]) ppage=(tlb_LUT_r[head->vaddr>>12]^0x80000000)>>12;
1400 #endif
1401               inv_debug("INV: Restored %x (%x/%x)\n",head->vaddr, (int)head->addr, (int)clean_addr);
1402               //printf("page=%x, addr=%x\n",page,head->vaddr);
1403               //assert(head->vaddr>>12==(page|0x80000));
1404               ll_add_32(jump_in+ppage,head->vaddr,head->reg32,clean_addr);
1405               int *ht_bin=hash_table[((head->vaddr>>16)^head->vaddr)&0xFFFF];
1406               if(!head->reg32) {
1407                 if(ht_bin[0]==head->vaddr) {
1408                   ht_bin[1]=(int)clean_addr; // Replace existing entry
1409                 }
1410                 if(ht_bin[2]==head->vaddr) {
1411                   ht_bin[3]=(int)clean_addr; // Replace existing entry
1412                 }
1413               }
1414             }
1415           }
1416         }
1417       }
1418     }
1419     head=head->next;
1420   }
1421 }
1422
1423
1424 void mov_alloc(struct regstat *current,int i)
1425 {
1426   // Note: Don't need to actually alloc the source registers
1427   if((~current->is32>>rs1[i])&1) {
1428     //alloc_reg64(current,i,rs1[i]);
1429     alloc_reg64(current,i,rt1[i]);
1430     current->is32&=~(1LL<<rt1[i]);
1431   } else {
1432     //alloc_reg(current,i,rs1[i]);
1433     alloc_reg(current,i,rt1[i]);
1434     current->is32|=(1LL<<rt1[i]);
1435   }
1436   clear_const(current,rs1[i]);
1437   clear_const(current,rt1[i]);
1438   dirty_reg(current,rt1[i]);
1439 }
1440
1441 void shiftimm_alloc(struct regstat *current,int i)
1442 {
1443   if(opcode2[i]<=0x3) // SLL/SRL/SRA
1444   {
1445     if(rt1[i]) {
1446       if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1447       else lt1[i]=rs1[i];
1448       alloc_reg(current,i,rt1[i]);
1449       current->is32|=1LL<<rt1[i];
1450       dirty_reg(current,rt1[i]);
1451       if(is_const(current,rs1[i])) {
1452         int v=get_const(current,rs1[i]);
1453         if(opcode2[i]==0x00) set_const(current,rt1[i],v<<imm[i]);
1454         if(opcode2[i]==0x02) set_const(current,rt1[i],(u_int)v>>imm[i]);
1455         if(opcode2[i]==0x03) set_const(current,rt1[i],v>>imm[i]);
1456       }
1457       else clear_const(current,rt1[i]);
1458     }
1459   }
1460   else
1461   {
1462     clear_const(current,rs1[i]);
1463     clear_const(current,rt1[i]);
1464   }
1465
1466   if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA
1467   {
1468     if(rt1[i]) {
1469       if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1470       alloc_reg64(current,i,rt1[i]);
1471       current->is32&=~(1LL<<rt1[i]);
1472       dirty_reg(current,rt1[i]);
1473     }
1474   }
1475   if(opcode2[i]==0x3c) // DSLL32
1476   {
1477     if(rt1[i]) {
1478       if(rs1[i]) alloc_reg(current,i,rs1[i]);
1479       alloc_reg64(current,i,rt1[i]);
1480       current->is32&=~(1LL<<rt1[i]);
1481       dirty_reg(current,rt1[i]);
1482     }
1483   }
1484   if(opcode2[i]==0x3e) // DSRL32
1485   {
1486     if(rt1[i]) {
1487       alloc_reg64(current,i,rs1[i]);
1488       if(imm[i]==32) {
1489         alloc_reg64(current,i,rt1[i]);
1490         current->is32&=~(1LL<<rt1[i]);
1491       } else {
1492         alloc_reg(current,i,rt1[i]);
1493         current->is32|=1LL<<rt1[i];
1494       }
1495       dirty_reg(current,rt1[i]);
1496     }
1497   }
1498   if(opcode2[i]==0x3f) // DSRA32
1499   {
1500     if(rt1[i]) {
1501       alloc_reg64(current,i,rs1[i]);
1502       alloc_reg(current,i,rt1[i]);
1503       current->is32|=1LL<<rt1[i];
1504       dirty_reg(current,rt1[i]);
1505     }
1506   }
1507 }
1508
1509 void shift_alloc(struct regstat *current,int i)
1510 {
1511   if(rt1[i]) {
1512     if(opcode2[i]<=0x07) // SLLV/SRLV/SRAV
1513     {
1514       if(rs1[i]) alloc_reg(current,i,rs1[i]);
1515       if(rs2[i]) alloc_reg(current,i,rs2[i]);
1516       alloc_reg(current,i,rt1[i]);
1517       if(rt1[i]==rs2[i]) {
1518         alloc_reg_temp(current,i,-1);
1519         minimum_free_regs[i]=1;
1520       }
1521       current->is32|=1LL<<rt1[i];
1522     } else { // DSLLV/DSRLV/DSRAV
1523       if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1524       if(rs2[i]) alloc_reg(current,i,rs2[i]);
1525       alloc_reg64(current,i,rt1[i]);
1526       current->is32&=~(1LL<<rt1[i]);
1527       if(opcode2[i]==0x16||opcode2[i]==0x17) // DSRLV and DSRAV need a temporary register
1528       {
1529         alloc_reg_temp(current,i,-1);
1530         minimum_free_regs[i]=1;
1531       }
1532     }
1533     clear_const(current,rs1[i]);
1534     clear_const(current,rs2[i]);
1535     clear_const(current,rt1[i]);
1536     dirty_reg(current,rt1[i]);
1537   }
1538 }
1539
1540 void alu_alloc(struct regstat *current,int i)
1541 {
1542   if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
1543     if(rt1[i]) {
1544       if(rs1[i]&&rs2[i]) {
1545         alloc_reg(current,i,rs1[i]);
1546         alloc_reg(current,i,rs2[i]);
1547       }
1548       else {
1549         if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1550         if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]);
1551       }
1552       alloc_reg(current,i,rt1[i]);
1553     }
1554     current->is32|=1LL<<rt1[i];
1555   }
1556   if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU
1557     if(rt1[i]) {
1558       if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1559       {
1560         alloc_reg64(current,i,rs1[i]);
1561         alloc_reg64(current,i,rs2[i]);
1562         alloc_reg(current,i,rt1[i]);
1563       } else {
1564         alloc_reg(current,i,rs1[i]);
1565         alloc_reg(current,i,rs2[i]);
1566         alloc_reg(current,i,rt1[i]);
1567       }
1568     }
1569     current->is32|=1LL<<rt1[i];
1570   }
1571   if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR
1572     if(rt1[i]) {
1573       if(rs1[i]&&rs2[i]) {
1574         alloc_reg(current,i,rs1[i]);
1575         alloc_reg(current,i,rs2[i]);
1576       }
1577       else
1578       {
1579         if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1580         if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]);
1581       }
1582       alloc_reg(current,i,rt1[i]);
1583       if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1584       {
1585         if(!((current->uu>>rt1[i])&1)) {
1586           alloc_reg64(current,i,rt1[i]);
1587         }
1588         if(get_reg(current->regmap,rt1[i]|64)>=0) {
1589           if(rs1[i]&&rs2[i]) {
1590             alloc_reg64(current,i,rs1[i]);
1591             alloc_reg64(current,i,rs2[i]);
1592           }
1593           else
1594           {
1595             // Is is really worth it to keep 64-bit values in registers?
1596             #ifdef NATIVE_64BIT
1597             if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]);
1598             if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg64(current,i,rs2[i]);
1599             #endif
1600           }
1601         }
1602         current->is32&=~(1LL<<rt1[i]);
1603       } else {
1604         current->is32|=1LL<<rt1[i];
1605       }
1606     }
1607   }
1608   if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU
1609     if(rt1[i]) {
1610       if(rs1[i]&&rs2[i]) {
1611         if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1612           alloc_reg64(current,i,rs1[i]);
1613           alloc_reg64(current,i,rs2[i]);
1614           alloc_reg64(current,i,rt1[i]);
1615         } else {
1616           alloc_reg(current,i,rs1[i]);
1617           alloc_reg(current,i,rs2[i]);
1618           alloc_reg(current,i,rt1[i]);
1619         }
1620       }
1621       else {
1622         alloc_reg(current,i,rt1[i]);
1623         if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1624           // DADD used as move, or zeroing
1625           // If we have a 64-bit source, then make the target 64 bits too
1626           if(rs1[i]&&!((current->is32>>rs1[i])&1)) {
1627             if(get_reg(current->regmap,rs1[i])>=0) alloc_reg64(current,i,rs1[i]);
1628             alloc_reg64(current,i,rt1[i]);
1629           } else if(rs2[i]&&!((current->is32>>rs2[i])&1)) {
1630             if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]);
1631             alloc_reg64(current,i,rt1[i]);
1632           }
1633           if(opcode2[i]>=0x2e&&rs2[i]) {
1634             // DSUB used as negation - 64-bit result
1635             // If we have a 32-bit register, extend it to 64 bits
1636             if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]);
1637             alloc_reg64(current,i,rt1[i]);
1638           }
1639         }
1640       }
1641       if(rs1[i]&&rs2[i]) {
1642         current->is32&=~(1LL<<rt1[i]);
1643       } else if(rs1[i]) {
1644         current->is32&=~(1LL<<rt1[i]);
1645         if((current->is32>>rs1[i])&1)
1646           current->is32|=1LL<<rt1[i];
1647       } else if(rs2[i]) {
1648         current->is32&=~(1LL<<rt1[i]);
1649         if((current->is32>>rs2[i])&1)
1650           current->is32|=1LL<<rt1[i];
1651       } else {
1652         current->is32|=1LL<<rt1[i];
1653       }
1654     }
1655   }
1656   clear_const(current,rs1[i]);
1657   clear_const(current,rs2[i]);
1658   clear_const(current,rt1[i]);
1659   dirty_reg(current,rt1[i]);
1660 }
1661
1662 void imm16_alloc(struct regstat *current,int i)
1663 {
1664   if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1665   else lt1[i]=rs1[i];
1666   if(rt1[i]) alloc_reg(current,i,rt1[i]);
1667   if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU
1668     current->is32&=~(1LL<<rt1[i]);
1669     if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1670       // TODO: Could preserve the 32-bit flag if the immediate is zero
1671       alloc_reg64(current,i,rt1[i]);
1672       alloc_reg64(current,i,rs1[i]);
1673     }
1674     clear_const(current,rs1[i]);
1675     clear_const(current,rt1[i]);
1676   }
1677   else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU
1678     if((~current->is32>>rs1[i])&1) alloc_reg64(current,i,rs1[i]);
1679     current->is32|=1LL<<rt1[i];
1680     clear_const(current,rs1[i]);
1681     clear_const(current,rt1[i]);
1682   }
1683   else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI
1684     if(((~current->is32>>rs1[i])&1)&&opcode[i]>0x0c) {
1685       if(rs1[i]!=rt1[i]) {
1686         if(needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]);
1687         alloc_reg64(current,i,rt1[i]);
1688         current->is32&=~(1LL<<rt1[i]);
1689       }
1690     }
1691     else current->is32|=1LL<<rt1[i]; // ANDI clears upper bits
1692     if(is_const(current,rs1[i])) {
1693       int v=get_const(current,rs1[i]);
1694       if(opcode[i]==0x0c) set_const(current,rt1[i],v&imm[i]);
1695       if(opcode[i]==0x0d) set_const(current,rt1[i],v|imm[i]);
1696       if(opcode[i]==0x0e) set_const(current,rt1[i],v^imm[i]);
1697     }
1698     else clear_const(current,rt1[i]);
1699   }
1700   else if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU
1701     if(is_const(current,rs1[i])) {
1702       int v=get_const(current,rs1[i]);
1703       set_const(current,rt1[i],v+imm[i]);
1704     }
1705     else clear_const(current,rt1[i]);
1706     current->is32|=1LL<<rt1[i];
1707   }
1708   else {
1709     set_const(current,rt1[i],((long long)((short)imm[i]))<<16); // LUI
1710     current->is32|=1LL<<rt1[i];
1711   }
1712   dirty_reg(current,rt1[i]);
1713 }
1714
1715 void load_alloc(struct regstat *current,int i)
1716 {
1717   clear_const(current,rt1[i]);
1718   //if(rs1[i]!=rt1[i]&&needed_again(rs1[i],i)) clear_const(current,rs1[i]); // Does this help or hurt?
1719   if(!rs1[i]) current->u&=~1LL; // Allow allocating r0 if it's the source register
1720   if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1721   if(rt1[i]&&!((current->u>>rt1[i])&1)) {
1722     alloc_reg(current,i,rt1[i]);
1723     assert(get_reg(current->regmap,rt1[i])>=0);
1724     if(opcode[i]==0x27||opcode[i]==0x37) // LWU/LD
1725     {
1726       current->is32&=~(1LL<<rt1[i]);
1727       alloc_reg64(current,i,rt1[i]);
1728     }
1729     else if(opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
1730     {
1731       current->is32&=~(1LL<<rt1[i]);
1732       alloc_reg64(current,i,rt1[i]);
1733       alloc_all(current,i);
1734       alloc_reg64(current,i,FTEMP);
1735       minimum_free_regs[i]=HOST_REGS;
1736     }
1737     else current->is32|=1LL<<rt1[i];
1738     dirty_reg(current,rt1[i]);
1739     // If using TLB, need a register for pointer to the mapping table
1740     if(using_tlb) alloc_reg(current,i,TLREG);
1741     // LWL/LWR need a temporary register for the old value
1742     if(opcode[i]==0x22||opcode[i]==0x26)
1743     {
1744       alloc_reg(current,i,FTEMP);
1745       alloc_reg_temp(current,i,-1);
1746       minimum_free_regs[i]=1;
1747     }
1748   }
1749   else
1750   {
1751     // Load to r0 or unneeded register (dummy load)
1752     // but we still need a register to calculate the address
1753     if(opcode[i]==0x22||opcode[i]==0x26)
1754     {
1755       alloc_reg(current,i,FTEMP); // LWL/LWR need another temporary
1756     }
1757     // If using TLB, need a register for pointer to the mapping table
1758     if(using_tlb) alloc_reg(current,i,TLREG);
1759     alloc_reg_temp(current,i,-1);
1760     minimum_free_regs[i]=1;
1761     if(opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
1762     {
1763       alloc_all(current,i);
1764       alloc_reg64(current,i,FTEMP);
1765       minimum_free_regs[i]=HOST_REGS;
1766     }
1767   }
1768 }
1769
1770 void store_alloc(struct regstat *current,int i)
1771 {
1772   clear_const(current,rs2[i]);
1773   if(!(rs2[i])) current->u&=~1LL; // Allow allocating r0 if necessary
1774   if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1775   alloc_reg(current,i,rs2[i]);
1776   if(opcode[i]==0x2c||opcode[i]==0x2d||opcode[i]==0x3f) { // 64-bit SDL/SDR/SD
1777     alloc_reg64(current,i,rs2[i]);
1778     if(rs2[i]) alloc_reg(current,i,FTEMP);
1779   }
1780   // If using TLB, need a register for pointer to the mapping table
1781   if(using_tlb) alloc_reg(current,i,TLREG);
1782   #if defined(HOST_IMM8)
1783   // On CPUs without 32-bit immediates we need a pointer to invalid_code
1784   else alloc_reg(current,i,INVCP);
1785   #endif
1786   if(opcode[i]==0x2a||opcode[i]==0x2e||opcode[i]==0x2c||opcode[i]==0x2d) { // SWL/SWL/SDL/SDR
1787     alloc_reg(current,i,FTEMP);
1788   }
1789   // We need a temporary register for address generation
1790   alloc_reg_temp(current,i,-1);
1791   minimum_free_regs[i]=1;
1792 }
1793
1794 void c1ls_alloc(struct regstat *current,int i)
1795 {
1796   //clear_const(current,rs1[i]); // FIXME
1797   clear_const(current,rt1[i]);
1798   if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1799   alloc_reg(current,i,CSREG); // Status
1800   alloc_reg(current,i,FTEMP);
1801   if(opcode[i]==0x35||opcode[i]==0x3d) { // 64-bit LDC1/SDC1
1802     alloc_reg64(current,i,FTEMP);
1803   }
1804   // If using TLB, need a register for pointer to the mapping table
1805   if(using_tlb) alloc_reg(current,i,TLREG);
1806   #if defined(HOST_IMM8)
1807   // On CPUs without 32-bit immediates we need a pointer to invalid_code
1808   else if((opcode[i]&0x3b)==0x39) // SWC1/SDC1
1809     alloc_reg(current,i,INVCP);
1810   #endif
1811   // We need a temporary register for address generation
1812   alloc_reg_temp(current,i,-1);
1813 }
1814
1815 void c2ls_alloc(struct regstat *current,int i)
1816 {
1817   clear_const(current,rt1[i]);
1818   if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1819   alloc_reg(current,i,FTEMP);
1820   // If using TLB, need a register for pointer to the mapping table
1821   if(using_tlb) alloc_reg(current,i,TLREG);
1822   #if defined(HOST_IMM8)
1823   // On CPUs without 32-bit immediates we need a pointer to invalid_code
1824   else if((opcode[i]&0x3b)==0x3a) // SWC2/SDC2
1825     alloc_reg(current,i,INVCP);
1826   #endif
1827   // We need a temporary register for address generation
1828   alloc_reg_temp(current,i,-1);
1829   minimum_free_regs[i]=1;
1830 }
1831
1832 #ifndef multdiv_alloc
1833 void multdiv_alloc(struct regstat *current,int i)
1834 {
1835   //  case 0x18: MULT
1836   //  case 0x19: MULTU
1837   //  case 0x1A: DIV
1838   //  case 0x1B: DIVU
1839   //  case 0x1C: DMULT
1840   //  case 0x1D: DMULTU
1841   //  case 0x1E: DDIV
1842   //  case 0x1F: DDIVU
1843   clear_const(current,rs1[i]);
1844   clear_const(current,rs2[i]);
1845   if(rs1[i]&&rs2[i])
1846   {
1847     if((opcode2[i]&4)==0) // 32-bit
1848     {
1849       current->u&=~(1LL<<HIREG);
1850       current->u&=~(1LL<<LOREG);
1851       alloc_reg(current,i,HIREG);
1852       alloc_reg(current,i,LOREG);
1853       alloc_reg(current,i,rs1[i]);
1854       alloc_reg(current,i,rs2[i]);
1855       current->is32|=1LL<<HIREG;
1856       current->is32|=1LL<<LOREG;
1857       dirty_reg(current,HIREG);
1858       dirty_reg(current,LOREG);
1859     }
1860     else // 64-bit
1861     {
1862       current->u&=~(1LL<<HIREG);
1863       current->u&=~(1LL<<LOREG);
1864       current->uu&=~(1LL<<HIREG);
1865       current->uu&=~(1LL<<LOREG);
1866       alloc_reg64(current,i,HIREG);
1867       //if(HOST_REGS>10) alloc_reg64(current,i,LOREG);
1868       alloc_reg64(current,i,rs1[i]);
1869       alloc_reg64(current,i,rs2[i]);
1870       alloc_all(current,i);
1871       current->is32&=~(1LL<<HIREG);
1872       current->is32&=~(1LL<<LOREG);
1873       dirty_reg(current,HIREG);
1874       dirty_reg(current,LOREG);
1875       minimum_free_regs[i]=HOST_REGS;
1876     }
1877   }
1878   else
1879   {
1880     // Multiply by zero is zero.
1881     // MIPS does not have a divide by zero exception.
1882     // The result is undefined, we return zero.
1883     alloc_reg(current,i,HIREG);
1884     alloc_reg(current,i,LOREG);
1885     current->is32|=1LL<<HIREG;
1886     current->is32|=1LL<<LOREG;
1887     dirty_reg(current,HIREG);
1888     dirty_reg(current,LOREG);
1889   }
1890 }
1891 #endif
1892
1893 void cop0_alloc(struct regstat *current,int i)
1894 {
1895   if(opcode2[i]==0) // MFC0
1896   {
1897     if(rt1[i]) {
1898       clear_const(current,rt1[i]);
1899       alloc_all(current,i);
1900       alloc_reg(current,i,rt1[i]);
1901       current->is32|=1LL<<rt1[i];
1902       dirty_reg(current,rt1[i]);
1903     }
1904   }
1905   else if(opcode2[i]==4) // MTC0
1906   {
1907     if(rs1[i]){
1908       clear_const(current,rs1[i]);
1909       alloc_reg(current,i,rs1[i]);
1910       alloc_all(current,i);
1911     }
1912     else {
1913       alloc_all(current,i); // FIXME: Keep r0
1914       current->u&=~1LL;
1915       alloc_reg(current,i,0);
1916     }
1917   }
1918   else
1919   {
1920     // TLBR/TLBWI/TLBWR/TLBP/ERET
1921     assert(opcode2[i]==0x10);
1922     alloc_all(current,i);
1923   }
1924   minimum_free_regs[i]=HOST_REGS;
1925 }
1926
1927 void cop1_alloc(struct regstat *current,int i)
1928 {
1929   alloc_reg(current,i,CSREG); // Load status
1930   if(opcode2[i]<3) // MFC1/DMFC1/CFC1
1931   {
1932     if(rt1[i]){
1933       clear_const(current,rt1[i]);
1934       if(opcode2[i]==1) {
1935         alloc_reg64(current,i,rt1[i]); // DMFC1
1936         current->is32&=~(1LL<<rt1[i]);
1937       }else{
1938         alloc_reg(current,i,rt1[i]); // MFC1/CFC1
1939         current->is32|=1LL<<rt1[i];
1940       }
1941       dirty_reg(current,rt1[i]);
1942     }
1943     alloc_reg_temp(current,i,-1);
1944   }
1945   else if(opcode2[i]>3) // MTC1/DMTC1/CTC1
1946   {
1947     if(rs1[i]){
1948       clear_const(current,rs1[i]);
1949       if(opcode2[i]==5)
1950         alloc_reg64(current,i,rs1[i]); // DMTC1
1951       else
1952         alloc_reg(current,i,rs1[i]); // MTC1/CTC1
1953       alloc_reg_temp(current,i,-1);
1954     }
1955     else {
1956       current->u&=~1LL;
1957       alloc_reg(current,i,0);
1958       alloc_reg_temp(current,i,-1);
1959     }
1960   }
1961   minimum_free_regs[i]=1;
1962 }
1963 void fconv_alloc(struct regstat *current,int i)
1964 {
1965   alloc_reg(current,i,CSREG); // Load status
1966   alloc_reg_temp(current,i,-1);
1967   minimum_free_regs[i]=1;
1968 }
1969 void float_alloc(struct regstat *current,int i)
1970 {
1971   alloc_reg(current,i,CSREG); // Load status
1972   alloc_reg_temp(current,i,-1);
1973   minimum_free_regs[i]=1;
1974 }
1975 void c2op_alloc(struct regstat *current,int i)
1976 {
1977   alloc_reg_temp(current,i,-1);
1978 }
1979 void fcomp_alloc(struct regstat *current,int i)
1980 {
1981   alloc_reg(current,i,CSREG); // Load status
1982   alloc_reg(current,i,FSREG); // Load flags
1983   dirty_reg(current,FSREG); // Flag will be modified
1984   alloc_reg_temp(current,i,-1);
1985   minimum_free_regs[i]=1;
1986 }
1987
1988 void syscall_alloc(struct regstat *current,int i)
1989 {
1990   alloc_cc(current,i);
1991   dirty_reg(current,CCREG);
1992   alloc_all(current,i);
1993   minimum_free_regs[i]=HOST_REGS;
1994   current->isconst=0;
1995 }
1996
1997 void delayslot_alloc(struct regstat *current,int i)
1998 {
1999   switch(itype[i]) {
2000     case UJUMP:
2001     case CJUMP:
2002     case SJUMP:
2003     case RJUMP:
2004     case FJUMP:
2005     case SYSCALL:
2006     case HLECALL:
2007     case SPAN:
2008       assem_debug("jump in the delay slot.  this shouldn't happen.\n");//exit(1);
2009       SysPrintf("Disabled speculative precompilation\n");
2010       stop_after_jal=1;
2011       break;
2012     case IMM16:
2013       imm16_alloc(current,i);
2014       break;
2015     case LOAD:
2016     case LOADLR:
2017       load_alloc(current,i);
2018       break;
2019     case STORE:
2020     case STORELR:
2021       store_alloc(current,i);
2022       break;
2023     case ALU:
2024       alu_alloc(current,i);
2025       break;
2026     case SHIFT:
2027       shift_alloc(current,i);
2028       break;
2029     case MULTDIV:
2030       multdiv_alloc(current,i);
2031       break;
2032     case SHIFTIMM:
2033       shiftimm_alloc(current,i);
2034       break;
2035     case MOV:
2036       mov_alloc(current,i);
2037       break;
2038     case COP0:
2039       cop0_alloc(current,i);
2040       break;
2041     case COP1:
2042     case COP2:
2043       cop1_alloc(current,i);
2044       break;
2045     case C1LS:
2046       c1ls_alloc(current,i);
2047       break;
2048     case C2LS:
2049       c2ls_alloc(current,i);
2050       break;
2051     case FCONV:
2052       fconv_alloc(current,i);
2053       break;
2054     case FLOAT:
2055       float_alloc(current,i);
2056       break;
2057     case FCOMP:
2058       fcomp_alloc(current,i);
2059       break;
2060     case C2OP:
2061       c2op_alloc(current,i);
2062       break;
2063   }
2064 }
2065
2066 // Special case where a branch and delay slot span two pages in virtual memory
2067 static void pagespan_alloc(struct regstat *current,int i)
2068 {
2069   current->isconst=0;
2070   current->wasconst=0;
2071   regs[i].wasconst=0;
2072   minimum_free_regs[i]=HOST_REGS;
2073   alloc_all(current,i);
2074   alloc_cc(current,i);
2075   dirty_reg(current,CCREG);
2076   if(opcode[i]==3) // JAL
2077   {
2078     alloc_reg(current,i,31);
2079     dirty_reg(current,31);
2080   }
2081   if(opcode[i]==0&&(opcode2[i]&0x3E)==8) // JR/JALR
2082   {
2083     alloc_reg(current,i,rs1[i]);
2084     if (rt1[i]!=0) {
2085       alloc_reg(current,i,rt1[i]);
2086       dirty_reg(current,rt1[i]);
2087     }
2088   }
2089   if((opcode[i]&0x2E)==4) // BEQ/BNE/BEQL/BNEL
2090   {
2091     if(rs1[i]) alloc_reg(current,i,rs1[i]);
2092     if(rs2[i]) alloc_reg(current,i,rs2[i]);
2093     if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
2094     {
2095       if(rs1[i]) alloc_reg64(current,i,rs1[i]);
2096       if(rs2[i]) alloc_reg64(current,i,rs2[i]);
2097     }
2098   }
2099   else
2100   if((opcode[i]&0x2E)==6) // BLEZ/BGTZ/BLEZL/BGTZL
2101   {
2102     if(rs1[i]) alloc_reg(current,i,rs1[i]);
2103     if(!((current->is32>>rs1[i])&1))
2104     {
2105       if(rs1[i]) alloc_reg64(current,i,rs1[i]);
2106     }
2107   }
2108   else
2109   if(opcode[i]==0x11) // BC1
2110   {
2111     alloc_reg(current,i,FSREG);
2112     alloc_reg(current,i,CSREG);
2113   }
2114   //else ...
2115 }
2116
2117 add_stub(int type,int addr,int retaddr,int a,int b,int c,int d,int e)
2118 {
2119   stubs[stubcount][0]=type;
2120   stubs[stubcount][1]=addr;
2121   stubs[stubcount][2]=retaddr;
2122   stubs[stubcount][3]=a;
2123   stubs[stubcount][4]=b;
2124   stubs[stubcount][5]=c;
2125   stubs[stubcount][6]=d;
2126   stubs[stubcount][7]=e;
2127   stubcount++;
2128 }
2129
2130 // Write out a single register
2131 void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32)
2132 {
2133   int hr;
2134   for(hr=0;hr<HOST_REGS;hr++) {
2135     if(hr!=EXCLUDE_REG) {
2136       if((regmap[hr]&63)==r) {
2137         if((dirty>>hr)&1) {
2138           if(regmap[hr]<64) {
2139             emit_storereg(r,hr);
2140 #ifndef FORCE32
2141             if((is32>>regmap[hr])&1) {
2142               emit_sarimm(hr,31,hr);
2143               emit_storereg(r|64,hr);
2144             }
2145 #endif
2146           }else{
2147             emit_storereg(r|64,hr);
2148           }
2149         }
2150       }
2151     }
2152   }
2153 }
2154
2155 int mchecksum()
2156 {
2157   //if(!tracedebug) return 0;
2158   int i;
2159   int sum=0;
2160   for(i=0;i<2097152;i++) {
2161     unsigned int temp=sum;
2162     sum<<=1;
2163     sum|=(~temp)>>31;
2164     sum^=((u_int *)rdram)[i];
2165   }
2166   return sum;
2167 }
2168 int rchecksum()
2169 {
2170   int i;
2171   int sum=0;
2172   for(i=0;i<64;i++)
2173     sum^=((u_int *)reg)[i];
2174   return sum;
2175 }
2176 void rlist()
2177 {
2178   int i;
2179   printf("TRACE: ");
2180   for(i=0;i<32;i++)
2181     printf("r%d:%8x%8x ",i,((int *)(reg+i))[1],((int *)(reg+i))[0]);
2182   printf("\n");
2183 #ifndef DISABLE_COP1
2184   printf("TRACE: ");
2185   for(i=0;i<32;i++)
2186     printf("f%d:%8x%8x ",i,((int*)reg_cop1_simple[i])[1],*((int*)reg_cop1_simple[i]));
2187   printf("\n");
2188 #endif
2189 }
2190
2191 void enabletrace()
2192 {
2193   tracedebug=1;
2194 }
2195
2196 void memdebug(int i)
2197 {
2198   //printf("TRACE: count=%d next=%d (checksum %x) lo=%8x%8x\n",Count,next_interupt,mchecksum(),(int)(reg[LOREG]>>32),(int)reg[LOREG]);
2199   //printf("TRACE: count=%d next=%d (rchecksum %x)\n",Count,next_interupt,rchecksum());
2200   //rlist();
2201   //if(tracedebug) {
2202   //if(Count>=-2084597794) {
2203   if((signed int)Count>=-2084597794&&(signed int)Count<0) {
2204   //if(0) {
2205     printf("TRACE: count=%d next=%d (checksum %x)\n",Count,next_interupt,mchecksum());
2206     //printf("TRACE: count=%d next=%d (checksum %x) Status=%x\n",Count,next_interupt,mchecksum(),Status);
2207     //printf("TRACE: count=%d next=%d (checksum %x) hi=%8x%8x\n",Count,next_interupt,mchecksum(),(int)(reg[HIREG]>>32),(int)reg[HIREG]);
2208     rlist();
2209     #ifdef __i386__
2210     printf("TRACE: %x\n",(&i)[-1]);
2211     #endif
2212     #ifdef __arm__
2213     int j;
2214     printf("TRACE: %x \n",(&j)[10]);
2215     printf("TRACE: %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x\n",(&j)[1],(&j)[2],(&j)[3],(&j)[4],(&j)[5],(&j)[6],(&j)[7],(&j)[8],(&j)[9],(&j)[10],(&j)[11],(&j)[12],(&j)[13],(&j)[14],(&j)[15],(&j)[16],(&j)[17],(&j)[18],(&j)[19],(&j)[20]);
2216     #endif
2217     //fflush(stdout);
2218   }
2219   //printf("TRACE: %x\n",(&i)[-1]);
2220 }
2221
2222 void tlb_debug(u_int cause, u_int addr, u_int iaddr)
2223 {
2224   printf("TLB Exception: instruction=%x addr=%x cause=%x\n",iaddr, addr, cause);
2225 }
2226
2227 void alu_assemble(int i,struct regstat *i_regs)
2228 {
2229   if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
2230     if(rt1[i]) {
2231       signed char s1,s2,t;
2232       t=get_reg(i_regs->regmap,rt1[i]);
2233       if(t>=0) {
2234         s1=get_reg(i_regs->regmap,rs1[i]);
2235         s2=get_reg(i_regs->regmap,rs2[i]);
2236         if(rs1[i]&&rs2[i]) {
2237           assert(s1>=0);
2238           assert(s2>=0);
2239           if(opcode2[i]&2) emit_sub(s1,s2,t);
2240           else emit_add(s1,s2,t);
2241         }
2242         else if(rs1[i]) {
2243           if(s1>=0) emit_mov(s1,t);
2244           else emit_loadreg(rs1[i],t);
2245         }
2246         else if(rs2[i]) {
2247           if(s2>=0) {
2248             if(opcode2[i]&2) emit_neg(s2,t);
2249             else emit_mov(s2,t);
2250           }
2251           else {
2252             emit_loadreg(rs2[i],t);
2253             if(opcode2[i]&2) emit_neg(t,t);
2254           }
2255         }
2256         else emit_zeroreg(t);
2257       }
2258     }
2259   }
2260   if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU
2261     if(rt1[i]) {
2262       signed char s1l,s2l,s1h,s2h,tl,th;
2263       tl=get_reg(i_regs->regmap,rt1[i]);
2264       th=get_reg(i_regs->regmap,rt1[i]|64);
2265       if(tl>=0) {
2266         s1l=get_reg(i_regs->regmap,rs1[i]);
2267         s2l=get_reg(i_regs->regmap,rs2[i]);
2268         s1h=get_reg(i_regs->regmap,rs1[i]|64);
2269         s2h=get_reg(i_regs->regmap,rs2[i]|64);
2270         if(rs1[i]&&rs2[i]) {
2271           assert(s1l>=0);
2272           assert(s2l>=0);
2273           if(opcode2[i]&2) emit_subs(s1l,s2l,tl);
2274           else emit_adds(s1l,s2l,tl);
2275           if(th>=0) {
2276             #ifdef INVERTED_CARRY
2277             if(opcode2[i]&2) {if(s1h!=th) emit_mov(s1h,th);emit_sbb(th,s2h);}
2278             #else
2279             if(opcode2[i]&2) emit_sbc(s1h,s2h,th);
2280             #endif
2281             else emit_add(s1h,s2h,th);
2282           }
2283         }
2284         else if(rs1[i]) {
2285           if(s1l>=0) emit_mov(s1l,tl);
2286           else emit_loadreg(rs1[i],tl);
2287           if(th>=0) {
2288             if(s1h>=0) emit_mov(s1h,th);
2289             else emit_loadreg(rs1[i]|64,th);
2290           }
2291         }
2292         else if(rs2[i]) {
2293           if(s2l>=0) {
2294             if(opcode2[i]&2) emit_negs(s2l,tl);
2295             else emit_mov(s2l,tl);
2296           }
2297           else {
2298             emit_loadreg(rs2[i],tl);
2299             if(opcode2[i]&2) emit_negs(tl,tl);
2300           }
2301           if(th>=0) {
2302             #ifdef INVERTED_CARRY
2303             if(s2h>=0) emit_mov(s2h,th);
2304             else emit_loadreg(rs2[i]|64,th);
2305             if(opcode2[i]&2) {
2306               emit_adcimm(-1,th); // x86 has inverted carry flag
2307               emit_not(th,th);
2308             }
2309             #else
2310             if(opcode2[i]&2) {
2311               if(s2h>=0) emit_rscimm(s2h,0,th);
2312               else {
2313                 emit_loadreg(rs2[i]|64,th);
2314                 emit_rscimm(th,0,th);
2315               }
2316             }else{
2317               if(s2h>=0) emit_mov(s2h,th);
2318               else emit_loadreg(rs2[i]|64,th);
2319             }
2320             #endif
2321           }
2322         }
2323         else {
2324           emit_zeroreg(tl);
2325           if(th>=0) emit_zeroreg(th);
2326         }
2327       }
2328     }
2329   }
2330   if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU
2331     if(rt1[i]) {
2332       signed char s1l,s1h,s2l,s2h,t;
2333       if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1))
2334       {
2335         t=get_reg(i_regs->regmap,rt1[i]);
2336         //assert(t>=0);
2337         if(t>=0) {
2338           s1l=get_reg(i_regs->regmap,rs1[i]);
2339           s1h=get_reg(i_regs->regmap,rs1[i]|64);
2340           s2l=get_reg(i_regs->regmap,rs2[i]);
2341           s2h=get_reg(i_regs->regmap,rs2[i]|64);
2342           if(rs2[i]==0) // rx<r0
2343           {
2344             assert(s1h>=0);
2345             if(opcode2[i]==0x2a) // SLT
2346               emit_shrimm(s1h,31,t);
2347             else // SLTU (unsigned can not be less than zero)
2348               emit_zeroreg(t);
2349           }
2350           else if(rs1[i]==0) // r0<rx
2351           {
2352             assert(s2h>=0);
2353             if(opcode2[i]==0x2a) // SLT
2354               emit_set_gz64_32(s2h,s2l,t);
2355             else // SLTU (set if not zero)
2356               emit_set_nz64_32(s2h,s2l,t);
2357           }
2358           else {
2359             assert(s1l>=0);assert(s1h>=0);
2360             assert(s2l>=0);assert(s2h>=0);
2361             if(opcode2[i]==0x2a) // SLT
2362               emit_set_if_less64_32(s1h,s1l,s2h,s2l,t);
2363             else // SLTU
2364               emit_set_if_carry64_32(s1h,s1l,s2h,s2l,t);
2365           }
2366         }
2367       } else {
2368         t=get_reg(i_regs->regmap,rt1[i]);
2369         //assert(t>=0);
2370         if(t>=0) {
2371           s1l=get_reg(i_regs->regmap,rs1[i]);
2372           s2l=get_reg(i_regs->regmap,rs2[i]);
2373           if(rs2[i]==0) // rx<r0
2374           {
2375             assert(s1l>=0);
2376             if(opcode2[i]==0x2a) // SLT
2377               emit_shrimm(s1l,31,t);
2378             else // SLTU (unsigned can not be less than zero)
2379               emit_zeroreg(t);
2380           }
2381           else if(rs1[i]==0) // r0<rx
2382           {
2383             assert(s2l>=0);
2384             if(opcode2[i]==0x2a) // SLT
2385               emit_set_gz32(s2l,t);
2386             else // SLTU (set if not zero)
2387               emit_set_nz32(s2l,t);
2388           }
2389           else{
2390             assert(s1l>=0);assert(s2l>=0);
2391             if(opcode2[i]==0x2a) // SLT
2392               emit_set_if_less32(s1l,s2l,t);
2393             else // SLTU
2394               emit_set_if_carry32(s1l,s2l,t);
2395           }
2396         }
2397       }
2398     }
2399   }
2400   if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR
2401     if(rt1[i]) {
2402       signed char s1l,s1h,s2l,s2h,th,tl;
2403       tl=get_reg(i_regs->regmap,rt1[i]);
2404       th=get_reg(i_regs->regmap,rt1[i]|64);
2405       if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1)&&th>=0)
2406       {
2407         assert(tl>=0);
2408         if(tl>=0) {
2409           s1l=get_reg(i_regs->regmap,rs1[i]);
2410           s1h=get_reg(i_regs->regmap,rs1[i]|64);
2411           s2l=get_reg(i_regs->regmap,rs2[i]);
2412           s2h=get_reg(i_regs->regmap,rs2[i]|64);
2413           if(rs1[i]&&rs2[i]) {
2414             assert(s1l>=0);assert(s1h>=0);
2415             assert(s2l>=0);assert(s2h>=0);
2416             if(opcode2[i]==0x24) { // AND
2417               emit_and(s1l,s2l,tl);
2418               emit_and(s1h,s2h,th);
2419             } else
2420             if(opcode2[i]==0x25) { // OR
2421               emit_or(s1l,s2l,tl);
2422               emit_or(s1h,s2h,th);
2423             } else
2424             if(opcode2[i]==0x26) { // XOR
2425               emit_xor(s1l,s2l,tl);
2426               emit_xor(s1h,s2h,th);
2427             } else
2428             if(opcode2[i]==0x27) { // NOR
2429               emit_or(s1l,s2l,tl);
2430               emit_or(s1h,s2h,th);
2431               emit_not(tl,tl);
2432               emit_not(th,th);
2433             }
2434           }
2435           else
2436           {
2437             if(opcode2[i]==0x24) { // AND
2438               emit_zeroreg(tl);
2439               emit_zeroreg(th);
2440             } else
2441             if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR
2442               if(rs1[i]){
2443                 if(s1l>=0) emit_mov(s1l,tl);
2444                 else emit_loadreg(rs1[i],tl);
2445                 if(s1h>=0) emit_mov(s1h,th);
2446                 else emit_loadreg(rs1[i]|64,th);
2447               }
2448               else
2449               if(rs2[i]){
2450                 if(s2l>=0) emit_mov(s2l,tl);
2451                 else emit_loadreg(rs2[i],tl);
2452                 if(s2h>=0) emit_mov(s2h,th);
2453                 else emit_loadreg(rs2[i]|64,th);
2454               }
2455               else{
2456                 emit_zeroreg(tl);
2457                 emit_zeroreg(th);
2458               }
2459             } else
2460             if(opcode2[i]==0x27) { // NOR
2461               if(rs1[i]){
2462                 if(s1l>=0) emit_not(s1l,tl);
2463                 else{
2464                   emit_loadreg(rs1[i],tl);
2465                   emit_not(tl,tl);
2466                 }
2467                 if(s1h>=0) emit_not(s1h,th);
2468                 else{
2469                   emit_loadreg(rs1[i]|64,th);
2470                   emit_not(th,th);
2471                 }
2472               }
2473               else
2474               if(rs2[i]){
2475                 if(s2l>=0) emit_not(s2l,tl);
2476                 else{
2477                   emit_loadreg(rs2[i],tl);
2478                   emit_not(tl,tl);
2479                 }
2480                 if(s2h>=0) emit_not(s2h,th);
2481                 else{
2482                   emit_loadreg(rs2[i]|64,th);
2483                   emit_not(th,th);
2484                 }
2485               }
2486               else {
2487                 emit_movimm(-1,tl);
2488                 emit_movimm(-1,th);
2489               }
2490             }
2491           }
2492         }
2493       }
2494       else
2495       {
2496         // 32 bit
2497         if(tl>=0) {
2498           s1l=get_reg(i_regs->regmap,rs1[i]);
2499           s2l=get_reg(i_regs->regmap,rs2[i]);
2500           if(rs1[i]&&rs2[i]) {
2501             assert(s1l>=0);
2502             assert(s2l>=0);
2503             if(opcode2[i]==0x24) { // AND
2504               emit_and(s1l,s2l,tl);
2505             } else
2506             if(opcode2[i]==0x25) { // OR
2507               emit_or(s1l,s2l,tl);
2508             } else
2509             if(opcode2[i]==0x26) { // XOR
2510               emit_xor(s1l,s2l,tl);
2511             } else
2512             if(opcode2[i]==0x27) { // NOR
2513               emit_or(s1l,s2l,tl);
2514               emit_not(tl,tl);
2515             }
2516           }
2517           else
2518           {
2519             if(opcode2[i]==0x24) { // AND
2520               emit_zeroreg(tl);
2521             } else
2522             if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR
2523               if(rs1[i]){
2524                 if(s1l>=0) emit_mov(s1l,tl);
2525                 else emit_loadreg(rs1[i],tl); // CHECK: regmap_entry?
2526               }
2527               else
2528               if(rs2[i]){
2529                 if(s2l>=0) emit_mov(s2l,tl);
2530                 else emit_loadreg(rs2[i],tl); // CHECK: regmap_entry?
2531               }
2532               else emit_zeroreg(tl);
2533             } else
2534             if(opcode2[i]==0x27) { // NOR
2535               if(rs1[i]){
2536                 if(s1l>=0) emit_not(s1l,tl);
2537                 else {
2538                   emit_loadreg(rs1[i],tl);
2539                   emit_not(tl,tl);
2540                 }
2541               }
2542               else
2543               if(rs2[i]){
2544                 if(s2l>=0) emit_not(s2l,tl);
2545                 else {
2546                   emit_loadreg(rs2[i],tl);
2547                   emit_not(tl,tl);
2548                 }
2549               }
2550               else emit_movimm(-1,tl);
2551             }
2552           }
2553         }
2554       }
2555     }
2556   }
2557 }
2558
2559 void imm16_assemble(int i,struct regstat *i_regs)
2560 {
2561   if (opcode[i]==0x0f) { // LUI
2562     if(rt1[i]) {
2563       signed char t;
2564       t=get_reg(i_regs->regmap,rt1[i]);
2565       //assert(t>=0);
2566       if(t>=0) {
2567         if(!((i_regs->isconst>>t)&1))
2568           emit_movimm(imm[i]<<16,t);
2569       }
2570     }
2571   }
2572   if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU
2573     if(rt1[i]) {
2574       signed char s,t;
2575       t=get_reg(i_regs->regmap,rt1[i]);
2576       s=get_reg(i_regs->regmap,rs1[i]);
2577       if(rs1[i]) {
2578         //assert(t>=0);
2579         //assert(s>=0);
2580         if(t>=0) {
2581           if(!((i_regs->isconst>>t)&1)) {
2582             if(s<0) {
2583               if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2584               emit_addimm(t,imm[i],t);
2585             }else{
2586               if(!((i_regs->wasconst>>s)&1))
2587                 emit_addimm(s,imm[i],t);
2588               else
2589                 emit_movimm(constmap[i][s]+imm[i],t);
2590             }
2591           }
2592         }
2593       } else {
2594         if(t>=0) {
2595           if(!((i_regs->isconst>>t)&1))
2596             emit_movimm(imm[i],t);
2597         }
2598       }
2599     }
2600   }
2601   if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU
2602     if(rt1[i]) {
2603       signed char sh,sl,th,tl;
2604       th=get_reg(i_regs->regmap,rt1[i]|64);
2605       tl=get_reg(i_regs->regmap,rt1[i]);
2606       sh=get_reg(i_regs->regmap,rs1[i]|64);
2607       sl=get_reg(i_regs->regmap,rs1[i]);
2608       if(tl>=0) {
2609         if(rs1[i]) {
2610           assert(sh>=0);
2611           assert(sl>=0);
2612           if(th>=0) {
2613             emit_addimm64_32(sh,sl,imm[i],th,tl);
2614           }
2615           else {
2616             emit_addimm(sl,imm[i],tl);
2617           }
2618         } else {
2619           emit_movimm(imm[i],tl);
2620           if(th>=0) emit_movimm(((signed int)imm[i])>>31,th);
2621         }
2622       }
2623     }
2624   }
2625   else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU
2626     if(rt1[i]) {
2627       //assert(rs1[i]!=0); // r0 might be valid, but it's probably a bug
2628       signed char sh,sl,t;
2629       t=get_reg(i_regs->regmap,rt1[i]);
2630       sh=get_reg(i_regs->regmap,rs1[i]|64);
2631       sl=get_reg(i_regs->regmap,rs1[i]);
2632       //assert(t>=0);
2633       if(t>=0) {
2634         if(rs1[i]>0) {
2635           if(sh<0) assert((i_regs->was32>>rs1[i])&1);
2636           if(sh<0||((i_regs->was32>>rs1[i])&1)) {
2637             if(opcode[i]==0x0a) { // SLTI
2638               if(sl<0) {
2639                 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2640                 emit_slti32(t,imm[i],t);
2641               }else{
2642                 emit_slti32(sl,imm[i],t);
2643               }
2644             }
2645             else { // SLTIU
2646               if(sl<0) {
2647                 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2648                 emit_sltiu32(t,imm[i],t);
2649               }else{
2650                 emit_sltiu32(sl,imm[i],t);
2651               }
2652             }
2653           }else{ // 64-bit
2654             assert(sl>=0);
2655             if(opcode[i]==0x0a) // SLTI
2656               emit_slti64_32(sh,sl,imm[i],t);
2657             else // SLTIU
2658               emit_sltiu64_32(sh,sl,imm[i],t);
2659           }
2660         }else{
2661           // SLTI(U) with r0 is just stupid,
2662           // nonetheless examples can be found
2663           if(opcode[i]==0x0a) // SLTI
2664             if(0<imm[i]) emit_movimm(1,t);
2665             else emit_zeroreg(t);
2666           else // SLTIU
2667           {
2668             if(imm[i]) emit_movimm(1,t);
2669             else emit_zeroreg(t);
2670           }
2671         }
2672       }
2673     }
2674   }
2675   else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI
2676     if(rt1[i]) {
2677       signed char sh,sl,th,tl;
2678       th=get_reg(i_regs->regmap,rt1[i]|64);
2679       tl=get_reg(i_regs->regmap,rt1[i]);
2680       sh=get_reg(i_regs->regmap,rs1[i]|64);
2681       sl=get_reg(i_regs->regmap,rs1[i]);
2682       if(tl>=0 && !((i_regs->isconst>>tl)&1)) {
2683         if(opcode[i]==0x0c) //ANDI
2684         {
2685           if(rs1[i]) {
2686             if(sl<0) {
2687               if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl);
2688               emit_andimm(tl,imm[i],tl);
2689             }else{
2690               if(!((i_regs->wasconst>>sl)&1))
2691                 emit_andimm(sl,imm[i],tl);
2692               else
2693                 emit_movimm(constmap[i][sl]&imm[i],tl);
2694             }
2695           }
2696           else
2697             emit_zeroreg(tl);
2698           if(th>=0) emit_zeroreg(th);
2699         }
2700         else
2701         {
2702           if(rs1[i]) {
2703             if(sl<0) {
2704               if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl);
2705             }
2706             if(th>=0) {
2707               if(sh<0) {
2708                 emit_loadreg(rs1[i]|64,th);
2709               }else{
2710                 emit_mov(sh,th);
2711               }
2712             }
2713             if(opcode[i]==0x0d) //ORI
2714             if(sl<0) {
2715               emit_orimm(tl,imm[i],tl);
2716             }else{
2717               if(!((i_regs->wasconst>>sl)&1))
2718                 emit_orimm(sl,imm[i],tl);
2719               else
2720                 emit_movimm(constmap[i][sl]|imm[i],tl);
2721             }
2722             if(opcode[i]==0x0e) //XORI
2723             if(sl<0) {
2724               emit_xorimm(tl,imm[i],tl);
2725             }else{
2726               if(!((i_regs->wasconst>>sl)&1))
2727                 emit_xorimm(sl,imm[i],tl);
2728               else
2729                 emit_movimm(constmap[i][sl]^imm[i],tl);
2730             }
2731           }
2732           else {
2733             emit_movimm(imm[i],tl);
2734             if(th>=0) emit_zeroreg(th);
2735           }
2736         }
2737       }
2738     }
2739   }
2740 }
2741
2742 void shiftimm_assemble(int i,struct regstat *i_regs)
2743 {
2744   if(opcode2[i]<=0x3) // SLL/SRL/SRA
2745   {
2746     if(rt1[i]) {
2747       signed char s,t;
2748       t=get_reg(i_regs->regmap,rt1[i]);
2749       s=get_reg(i_regs->regmap,rs1[i]);
2750       //assert(t>=0);
2751       if(t>=0&&!((i_regs->isconst>>t)&1)){
2752         if(rs1[i]==0)
2753         {
2754           emit_zeroreg(t);
2755         }
2756         else
2757         {
2758           if(s<0&&i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2759           if(imm[i]) {
2760             if(opcode2[i]==0) // SLL
2761             {
2762               emit_shlimm(s<0?t:s,imm[i],t);
2763             }
2764             if(opcode2[i]==2) // SRL
2765             {
2766               emit_shrimm(s<0?t:s,imm[i],t);
2767             }
2768             if(opcode2[i]==3) // SRA
2769             {
2770               emit_sarimm(s<0?t:s,imm[i],t);
2771             }
2772           }else{
2773             // Shift by zero
2774             if(s>=0 && s!=t) emit_mov(s,t);
2775           }
2776         }
2777       }
2778       //emit_storereg(rt1[i],t); //DEBUG
2779     }
2780   }
2781   if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA
2782   {
2783     if(rt1[i]) {
2784       signed char sh,sl,th,tl;
2785       th=get_reg(i_regs->regmap,rt1[i]|64);
2786       tl=get_reg(i_regs->regmap,rt1[i]);
2787       sh=get_reg(i_regs->regmap,rs1[i]|64);
2788       sl=get_reg(i_regs->regmap,rs1[i]);
2789       if(tl>=0) {
2790         if(rs1[i]==0)
2791         {
2792           emit_zeroreg(tl);
2793           if(th>=0) emit_zeroreg(th);
2794         }
2795         else
2796         {
2797           assert(sl>=0);
2798           assert(sh>=0);
2799           if(imm[i]) {
2800             if(opcode2[i]==0x38) // DSLL
2801             {
2802               if(th>=0) emit_shldimm(sh,sl,imm[i],th);
2803               emit_shlimm(sl,imm[i],tl);
2804             }
2805             if(opcode2[i]==0x3a) // DSRL
2806             {
2807               emit_shrdimm(sl,sh,imm[i],tl);
2808               if(th>=0) emit_shrimm(sh,imm[i],th);
2809             }
2810             if(opcode2[i]==0x3b) // DSRA
2811             {
2812               emit_shrdimm(sl,sh,imm[i],tl);
2813               if(th>=0) emit_sarimm(sh,imm[i],th);
2814             }
2815           }else{
2816             // Shift by zero
2817             if(sl!=tl) emit_mov(sl,tl);
2818             if(th>=0&&sh!=th) emit_mov(sh,th);
2819           }
2820         }
2821       }
2822     }
2823   }
2824   if(opcode2[i]==0x3c) // DSLL32
2825   {
2826     if(rt1[i]) {
2827       signed char sl,tl,th;
2828       tl=get_reg(i_regs->regmap,rt1[i]);
2829       th=get_reg(i_regs->regmap,rt1[i]|64);
2830       sl=get_reg(i_regs->regmap,rs1[i]);
2831       if(th>=0||tl>=0){
2832         assert(tl>=0);
2833         assert(th>=0);
2834         assert(sl>=0);
2835         emit_mov(sl,th);
2836         emit_zeroreg(tl);
2837         if(imm[i]>32)
2838         {
2839           emit_shlimm(th,imm[i]&31,th);
2840         }
2841       }
2842     }
2843   }
2844   if(opcode2[i]==0x3e) // DSRL32
2845   {
2846     if(rt1[i]) {
2847       signed char sh,tl,th;
2848       tl=get_reg(i_regs->regmap,rt1[i]);
2849       th=get_reg(i_regs->regmap,rt1[i]|64);
2850       sh=get_reg(i_regs->regmap,rs1[i]|64);
2851       if(tl>=0){
2852         assert(sh>=0);
2853         emit_mov(sh,tl);
2854         if(th>=0) emit_zeroreg(th);
2855         if(imm[i]>32)
2856         {
2857           emit_shrimm(tl,imm[i]&31,tl);
2858         }
2859       }
2860     }
2861   }
2862   if(opcode2[i]==0x3f) // DSRA32
2863   {
2864     if(rt1[i]) {
2865       signed char sh,tl;
2866       tl=get_reg(i_regs->regmap,rt1[i]);
2867       sh=get_reg(i_regs->regmap,rs1[i]|64);
2868       if(tl>=0){
2869         assert(sh>=0);
2870         emit_mov(sh,tl);
2871         if(imm[i]>32)
2872         {
2873           emit_sarimm(tl,imm[i]&31,tl);
2874         }
2875       }
2876     }
2877   }
2878 }
2879
2880 #ifndef shift_assemble
2881 void shift_assemble(int i,struct regstat *i_regs)
2882 {
2883   printf("Need shift_assemble for this architecture.\n");
2884   exit(1);
2885 }
2886 #endif
2887
2888 void load_assemble(int i,struct regstat *i_regs)
2889 {
2890   int s,th,tl,addr,map=-1;
2891   int offset;
2892   int jaddr=0;
2893   int memtarget=0,c=0;
2894   int fastload_reg_override=0;
2895   u_int hr,reglist=0;
2896   th=get_reg(i_regs->regmap,rt1[i]|64);
2897   tl=get_reg(i_regs->regmap,rt1[i]);
2898   s=get_reg(i_regs->regmap,rs1[i]);
2899   offset=imm[i];
2900   for(hr=0;hr<HOST_REGS;hr++) {
2901     if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
2902   }
2903   if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
2904   if(s>=0) {
2905     c=(i_regs->wasconst>>s)&1;
2906     if (c) {
2907       memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
2908       if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
2909     }
2910   }
2911   //printf("load_assemble: c=%d\n",c);
2912   //if(c) printf("load_assemble: const=%x\n",(int)constmap[i][s]+offset);
2913   // FIXME: Even if the load is a NOP, we should check for pagefaults...
2914 #ifdef PCSX
2915   if(tl<0&&(!c||(((u_int)constmap[i][s]+offset)>>16)==0x1f80)
2916     ||rt1[i]==0) {
2917       // could be FIFO, must perform the read
2918       // ||dummy read
2919       assem_debug("(forced read)\n");
2920       tl=get_reg(i_regs->regmap,-1);
2921       assert(tl>=0);
2922   }
2923 #endif
2924   if(offset||s<0||c) addr=tl;
2925   else addr=s;
2926   //if(tl<0) tl=get_reg(i_regs->regmap,-1);
2927  if(tl>=0) {
2928   //printf("load_assemble: c=%d\n",c);
2929   //if(c) printf("load_assemble: const=%x\n",(int)constmap[i][s]+offset);
2930   assert(tl>=0); // Even if the load is a NOP, we must check for pagefaults and I/O
2931   reglist&=~(1<<tl);
2932   if(th>=0) reglist&=~(1<<th);
2933   if(!using_tlb) {
2934     if(!c) {
2935       #ifdef RAM_OFFSET
2936       map=get_reg(i_regs->regmap,ROREG);
2937       if(map<0) emit_loadreg(ROREG,map=HOST_TEMPREG);
2938       #endif
2939 //#define R29_HACK 1
2940       #ifdef R29_HACK
2941       // Strmnnrmn's speed hack
2942       if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
2943       #endif
2944       {
2945         jaddr=emit_fastpath_cmp_jump(i,addr,&fastload_reg_override);
2946       }
2947     }
2948     else if(ram_offset&&memtarget) {
2949       emit_addimm(addr,ram_offset,HOST_TEMPREG);
2950       fastload_reg_override=HOST_TEMPREG;
2951     }
2952   }else{ // using tlb
2953     int x=0;
2954     if (opcode[i]==0x20||opcode[i]==0x24) x=3; // LB/LBU
2955     if (opcode[i]==0x21||opcode[i]==0x25) x=2; // LH/LHU
2956     map=get_reg(i_regs->regmap,TLREG);
2957     assert(map>=0);
2958     reglist&=~(1<<map);
2959     map=do_tlb_r(addr,tl,map,x,-1,-1,c,constmap[i][s]+offset);
2960     do_tlb_r_branch(map,c,constmap[i][s]+offset,&jaddr);
2961   }
2962   int dummy=(rt1[i]==0)||(tl!=get_reg(i_regs->regmap,rt1[i])); // ignore loads to r0 and unneeded reg
2963   if (opcode[i]==0x20) { // LB
2964     if(!c||memtarget) {
2965       if(!dummy) {
2966         #ifdef HOST_IMM_ADDR32
2967         if(c)
2968           emit_movsbl_tlb((constmap[i][s]+offset)^3,map,tl);
2969         else
2970         #endif
2971         {
2972           //emit_xorimm(addr,3,tl);
2973           //gen_tlb_addr_r(tl,map);
2974           //emit_movsbl_indexed((int)rdram-0x80000000,tl,tl);
2975           int x=0,a=tl;
2976 #ifdef BIG_ENDIAN_MIPS
2977           if(!c) emit_xorimm(addr,3,tl);
2978           else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2979 #else
2980           if(!c) a=addr;
2981 #endif
2982           if(fastload_reg_override) a=fastload_reg_override;
2983
2984           emit_movsbl_indexed_tlb(x,a,map,tl);
2985         }
2986       }
2987       if(jaddr)
2988         add_stub(LOADB_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2989     }
2990     else
2991       inline_readstub(LOADB_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2992   }
2993   if (opcode[i]==0x21) { // LH
2994     if(!c||memtarget) {
2995       if(!dummy) {
2996         #ifdef HOST_IMM_ADDR32
2997         if(c)
2998           emit_movswl_tlb((constmap[i][s]+offset)^2,map,tl);
2999         else
3000         #endif
3001         {
3002           int x=0,a=tl;
3003 #ifdef BIG_ENDIAN_MIPS
3004           if(!c) emit_xorimm(addr,2,tl);
3005           else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
3006 #else
3007           if(!c) a=addr;
3008 #endif
3009           if(fastload_reg_override) a=fastload_reg_override;
3010           //#ifdef
3011           //emit_movswl_indexed_tlb(x,tl,map,tl);
3012           //else
3013           if(map>=0) {
3014             gen_tlb_addr_r(a,map);
3015             emit_movswl_indexed(x,a,tl);
3016           }else{
3017             #if 1 //def RAM_OFFSET
3018             emit_movswl_indexed(x,a,tl);
3019             #else
3020             emit_movswl_indexed((int)rdram-0x80000000+x,a,tl);
3021             #endif
3022           }
3023         }
3024       }
3025       if(jaddr)
3026         add_stub(LOADH_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3027     }
3028     else
3029       inline_readstub(LOADH_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3030   }
3031   if (opcode[i]==0x23) { // LW
3032     if(!c||memtarget) {
3033       if(!dummy) {
3034         int a=addr;
3035         if(fastload_reg_override) a=fastload_reg_override;
3036         //emit_readword_indexed((int)rdram-0x80000000,addr,tl);
3037         #ifdef HOST_IMM_ADDR32
3038         if(c)
3039           emit_readword_tlb(constmap[i][s]+offset,map,tl);
3040         else
3041         #endif
3042         emit_readword_indexed_tlb(0,a,map,tl);
3043       }
3044       if(jaddr)
3045         add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3046     }
3047     else
3048       inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3049   }
3050   if (opcode[i]==0x24) { // LBU
3051     if(!c||memtarget) {
3052       if(!dummy) {
3053         #ifdef HOST_IMM_ADDR32
3054         if(c)
3055           emit_movzbl_tlb((constmap[i][s]+offset)^3,map,tl);
3056         else
3057         #endif
3058         {
3059           //emit_xorimm(addr,3,tl);
3060           //gen_tlb_addr_r(tl,map);
3061           //emit_movzbl_indexed((int)rdram-0x80000000,tl,tl);
3062           int x=0,a=tl;
3063 #ifdef BIG_ENDIAN_MIPS
3064           if(!c) emit_xorimm(addr,3,tl);
3065           else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
3066 #else
3067           if(!c) a=addr;
3068 #endif
3069           if(fastload_reg_override) a=fastload_reg_override;
3070
3071           emit_movzbl_indexed_tlb(x,a,map,tl);
3072         }
3073       }
3074       if(jaddr)
3075         add_stub(LOADBU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3076     }
3077     else
3078       inline_readstub(LOADBU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3079   }
3080   if (opcode[i]==0x25) { // LHU
3081     if(!c||memtarget) {
3082       if(!dummy) {
3083         #ifdef HOST_IMM_ADDR32
3084         if(c)
3085           emit_movzwl_tlb((constmap[i][s]+offset)^2,map,tl);
3086         else
3087         #endif
3088         {
3089           int x=0,a=tl;
3090 #ifdef BIG_ENDIAN_MIPS
3091           if(!c) emit_xorimm(addr,2,tl);
3092           else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
3093 #else
3094           if(!c) a=addr;
3095 #endif
3096           if(fastload_reg_override) a=fastload_reg_override;
3097           //#ifdef
3098           //emit_movzwl_indexed_tlb(x,tl,map,tl);
3099           //#else
3100           if(map>=0) {
3101             gen_tlb_addr_r(a,map);
3102             emit_movzwl_indexed(x,a,tl);
3103           }else{
3104             #if 1 //def RAM_OFFSET
3105             emit_movzwl_indexed(x,a,tl);
3106             #else
3107             emit_movzwl_indexed((int)rdram-0x80000000+x,a,tl);
3108             #endif
3109           }
3110         }
3111       }
3112       if(jaddr)
3113         add_stub(LOADHU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3114     }
3115     else
3116       inline_readstub(LOADHU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3117   }
3118   if (opcode[i]==0x27) { // LWU
3119     assert(th>=0);
3120     if(!c||memtarget) {
3121       if(!dummy) {
3122         int a=addr;
3123         if(fastload_reg_override) a=fastload_reg_override;
3124         //emit_readword_indexed((int)rdram-0x80000000,addr,tl);
3125         #ifdef HOST_IMM_ADDR32
3126         if(c)
3127           emit_readword_tlb(constmap[i][s]+offset,map,tl);
3128         else
3129         #endif
3130         emit_readword_indexed_tlb(0,a,map,tl);
3131       }
3132       if(jaddr)
3133         add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3134     }
3135     else {
3136       inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3137     }
3138     emit_zeroreg(th);
3139   }
3140   if (opcode[i]==0x37) { // LD
3141     if(!c||memtarget) {
3142       if(!dummy) {
3143         int a=addr;
3144         if(fastload_reg_override) a=fastload_reg_override;
3145         //gen_tlb_addr_r(tl,map);
3146         //if(th>=0) emit_readword_indexed((int)rdram-0x80000000,addr,th);
3147         //emit_readword_indexed((int)rdram-0x7FFFFFFC,addr,tl);
3148         #ifdef HOST_IMM_ADDR32
3149         if(c)
3150           emit_readdword_tlb(constmap[i][s]+offset,map,th,tl);
3151         else
3152         #endif
3153         emit_readdword_indexed_tlb(0,a,map,th,tl);
3154       }
3155       if(jaddr)
3156         add_stub(LOADD_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3157     }
3158     else
3159       inline_readstub(LOADD_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3160   }
3161  }
3162   //emit_storereg(rt1[i],tl); // DEBUG
3163   //if(opcode[i]==0x23)
3164   //if(opcode[i]==0x24)
3165   //if(opcode[i]==0x23||opcode[i]==0x24)
3166   /*if(opcode[i]==0x21||opcode[i]==0x23||opcode[i]==0x24)
3167   {
3168     //emit_pusha();
3169     save_regs(0x100f);
3170         emit_readword((int)&last_count,ECX);
3171         #ifdef __i386__
3172         if(get_reg(i_regs->regmap,CCREG)<0)
3173           emit_loadreg(CCREG,HOST_CCREG);
3174         emit_add(HOST_CCREG,ECX,HOST_CCREG);
3175         emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3176         emit_writeword(HOST_CCREG,(int)&Count);
3177         #endif
3178         #ifdef __arm__
3179         if(get_reg(i_regs->regmap,CCREG)<0)
3180           emit_loadreg(CCREG,0);
3181         else
3182           emit_mov(HOST_CCREG,0);
3183         emit_add(0,ECX,0);
3184         emit_addimm(0,2*ccadj[i],0);
3185         emit_writeword(0,(int)&Count);
3186         #endif
3187     emit_call((int)memdebug);
3188     //emit_popa();
3189     restore_regs(0x100f);
3190   }/**/
3191 }
3192
3193 #ifndef loadlr_assemble
3194 void loadlr_assemble(int i,struct regstat *i_regs)
3195 {
3196   printf("Need loadlr_assemble for this architecture.\n");
3197   exit(1);
3198 }
3199 #endif
3200
3201 void store_assemble(int i,struct regstat *i_regs)
3202 {
3203   int s,th,tl,map=-1;
3204   int addr,temp;
3205   int offset;
3206   int jaddr=0,jaddr2,type;
3207   int memtarget=0,c=0;
3208   int agr=AGEN1+(i&1);
3209   int faststore_reg_override=0;
3210   u_int hr,reglist=0;
3211   th=get_reg(i_regs->regmap,rs2[i]|64);
3212   tl=get_reg(i_regs->regmap,rs2[i]);
3213   s=get_reg(i_regs->regmap,rs1[i]);
3214   temp=get_reg(i_regs->regmap,agr);
3215   if(temp<0) temp=get_reg(i_regs->regmap,-1);
3216   offset=imm[i];
3217   if(s>=0) {
3218     c=(i_regs->wasconst>>s)&1;
3219     if(c) {
3220       memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
3221       if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
3222     }
3223   }
3224   assert(tl>=0);
3225   assert(temp>=0);
3226   for(hr=0;hr<HOST_REGS;hr++) {
3227     if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3228   }
3229   if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
3230   if(offset||s<0||c) addr=temp;
3231   else addr=s;
3232   if(!using_tlb) {
3233     if(!c) {
3234       #ifndef PCSX
3235       #ifdef R29_HACK
3236       // Strmnnrmn's speed hack
3237       if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
3238       #endif
3239       emit_cmpimm(addr,RAM_SIZE);
3240       #ifdef DESTRUCTIVE_SHIFT
3241       if(s==addr) emit_mov(s,temp);
3242       #endif
3243       #ifdef R29_HACK
3244       memtarget=1;
3245       if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
3246       #endif
3247       {
3248         jaddr=(int)out;
3249         #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
3250         // Hint to branch predictor that the branch is unlikely to be taken
3251         if(rs1[i]>=28)
3252           emit_jno_unlikely(0);
3253         else
3254         #endif
3255         emit_jno(0);
3256       }
3257       #else
3258         jaddr=emit_fastpath_cmp_jump(i,addr,&faststore_reg_override);
3259       #endif
3260     }
3261     else if(ram_offset&&memtarget) {
3262       emit_addimm(addr,ram_offset,HOST_TEMPREG);
3263       faststore_reg_override=HOST_TEMPREG;
3264     }
3265   }else{ // using tlb
3266     int x=0;
3267     if (opcode[i]==0x28) x=3; // SB
3268     if (opcode[i]==0x29) x=2; // SH
3269     map=get_reg(i_regs->regmap,TLREG);
3270     assert(map>=0);
3271     reglist&=~(1<<map);
3272     map=do_tlb_w(addr,temp,map,x,c,constmap[i][s]+offset);
3273     do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr);
3274   }
3275
3276   if (opcode[i]==0x28) { // SB
3277     if(!c||memtarget) {
3278       int x=0,a=temp;
3279 #ifdef BIG_ENDIAN_MIPS
3280       if(!c) emit_xorimm(addr,3,temp);
3281       else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
3282 #else
3283       if(!c) a=addr;
3284 #endif
3285       if(faststore_reg_override) a=faststore_reg_override;
3286       //gen_tlb_addr_w(temp,map);
3287       //emit_writebyte_indexed(tl,(int)rdram-0x80000000,temp);
3288       emit_writebyte_indexed_tlb(tl,x,a,map,a);
3289     }
3290     type=STOREB_STUB;
3291   }
3292   if (opcode[i]==0x29) { // SH
3293     if(!c||memtarget) {
3294       int x=0,a=temp;
3295 #ifdef BIG_ENDIAN_MIPS
3296       if(!c) emit_xorimm(addr,2,temp);
3297       else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
3298 #else
3299       if(!c) a=addr;
3300 #endif
3301       if(faststore_reg_override) a=faststore_reg_override;
3302       //#ifdef
3303       //emit_writehword_indexed_tlb(tl,x,temp,map,temp);
3304       //#else
3305       if(map>=0) {
3306         gen_tlb_addr_w(a,map);
3307         emit_writehword_indexed(tl,x,a);
3308       }else
3309         //emit_writehword_indexed(tl,(int)rdram-0x80000000+x,a);
3310         emit_writehword_indexed(tl,x,a);
3311     }
3312     type=STOREH_STUB;
3313   }
3314   if (opcode[i]==0x2B) { // SW
3315     if(!c||memtarget) {
3316       int a=addr;
3317       if(faststore_reg_override) a=faststore_reg_override;
3318       //emit_writeword_indexed(tl,(int)rdram-0x80000000,addr);
3319       emit_writeword_indexed_tlb(tl,0,a,map,temp);
3320     }
3321     type=STOREW_STUB;
3322   }
3323   if (opcode[i]==0x3F) { // SD
3324     if(!c||memtarget) {
3325       int a=addr;
3326       if(faststore_reg_override) a=faststore_reg_override;
3327       if(rs2[i]) {
3328         assert(th>=0);
3329         //emit_writeword_indexed(th,(int)rdram-0x80000000,addr);
3330         //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,addr);
3331         emit_writedword_indexed_tlb(th,tl,0,a,map,temp);
3332       }else{
3333         // Store zero
3334         //emit_writeword_indexed(tl,(int)rdram-0x80000000,temp);
3335         //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,temp);
3336         emit_writedword_indexed_tlb(tl,tl,0,a,map,temp);
3337       }
3338     }
3339     type=STORED_STUB;
3340   }
3341 #ifdef PCSX
3342   if(jaddr) {
3343     // PCSX store handlers don't check invcode again
3344     reglist|=1<<addr;
3345     add_stub(type,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3346     jaddr=0;
3347   }
3348 #endif
3349   if(!using_tlb&&!(i_regs->waswritten&(1<<rs1[i]))&&!(new_dynarec_hacks&NDHACK_NO_SMC_CHECK)) {
3350     if(!c||memtarget) {
3351       #ifdef DESTRUCTIVE_SHIFT
3352       // The x86 shift operation is 'destructive'; it overwrites the
3353       // source register, so we need to make a copy first and use that.
3354       addr=temp;
3355       #endif
3356       #if defined(HOST_IMM8)
3357       int ir=get_reg(i_regs->regmap,INVCP);
3358       assert(ir>=0);
3359       emit_cmpmem_indexedsr12_reg(ir,addr,1);
3360       #else
3361       emit_cmpmem_indexedsr12_imm((int)invalid_code,addr,1);
3362       #endif
3363       #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3364       emit_callne(invalidate_addr_reg[addr]);
3365       #else
3366       jaddr2=(int)out;
3367       emit_jne(0);
3368       add_stub(INVCODE_STUB,jaddr2,(int)out,reglist|(1<<HOST_CCREG),addr,0,0,0);
3369       #endif
3370     }
3371   }
3372   u_int addr_val=constmap[i][s]+offset;
3373   if(jaddr) {
3374     add_stub(type,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3375   } else if(c&&!memtarget) {
3376     inline_writestub(type,i,addr_val,i_regs->regmap,rs2[i],ccadj[i],reglist);
3377   }
3378   // basic current block modification detection..
3379   // not looking back as that should be in mips cache already
3380   if(c&&start+i*4<addr_val&&addr_val<start+slen*4) {
3381     SysPrintf("write to %08x hits block %08x, pc=%08x\n",addr_val,start,start+i*4);
3382     assert(i_regs->regmap==regs[i].regmap); // not delay slot
3383     if(i_regs->regmap==regs[i].regmap) {
3384       load_all_consts(regs[i].regmap_entry,regs[i].was32,regs[i].wasdirty,i);
3385       wb_dirtys(regs[i].regmap_entry,regs[i].was32,regs[i].wasdirty);
3386       emit_movimm(start+i*4+4,0);
3387       emit_writeword(0,(int)&pcaddr);
3388       emit_jmp((int)do_interrupt);
3389     }
3390   }
3391   //if(opcode[i]==0x2B || opcode[i]==0x3F)
3392   //if(opcode[i]==0x2B || opcode[i]==0x28)
3393   //if(opcode[i]==0x2B || opcode[i]==0x29)
3394   //if(opcode[i]==0x2B)
3395   /*if(opcode[i]==0x2B || opcode[i]==0x28 || opcode[i]==0x29 || opcode[i]==0x3F)
3396   {
3397     #ifdef __i386__
3398     emit_pusha();
3399     #endif
3400     #ifdef __arm__
3401     save_regs(0x100f);
3402     #endif
3403         emit_readword((int)&last_count,ECX);
3404         #ifdef __i386__
3405         if(get_reg(i_regs->regmap,CCREG)<0)
3406           emit_loadreg(CCREG,HOST_CCREG);
3407         emit_add(HOST_CCREG,ECX,HOST_CCREG);
3408         emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3409         emit_writeword(HOST_CCREG,(int)&Count);
3410         #endif
3411         #ifdef __arm__
3412         if(get_reg(i_regs->regmap,CCREG)<0)
3413           emit_loadreg(CCREG,0);
3414         else
3415           emit_mov(HOST_CCREG,0);
3416         emit_add(0,ECX,0);
3417         emit_addimm(0,2*ccadj[i],0);
3418         emit_writeword(0,(int)&Count);
3419         #endif
3420     emit_call((int)memdebug);
3421     #ifdef __i386__
3422     emit_popa();
3423     #endif
3424     #ifdef __arm__
3425     restore_regs(0x100f);
3426     #endif
3427   }/**/
3428 }
3429
3430 void storelr_assemble(int i,struct regstat *i_regs)
3431 {
3432   int s,th,tl;
3433   int temp;
3434   int temp2;
3435   int offset;
3436   int jaddr=0,jaddr2;
3437   int case1,case2,case3;
3438   int done0,done1,done2;
3439   int memtarget=0,c=0;
3440   int agr=AGEN1+(i&1);
3441   u_int hr,reglist=0;
3442   th=get_reg(i_regs->regmap,rs2[i]|64);
3443   tl=get_reg(i_regs->regmap,rs2[i]);
3444   s=get_reg(i_regs->regmap,rs1[i]);
3445   temp=get_reg(i_regs->regmap,agr);
3446   if(temp<0) temp=get_reg(i_regs->regmap,-1);
3447   offset=imm[i];
3448   if(s>=0) {
3449     c=(i_regs->isconst>>s)&1;
3450     if(c) {
3451       memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
3452       if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
3453     }
3454   }
3455   assert(tl>=0);
3456   for(hr=0;hr<HOST_REGS;hr++) {
3457     if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3458   }
3459   assert(temp>=0);
3460   if(!using_tlb) {
3461     if(!c) {
3462       emit_cmpimm(s<0||offset?temp:s,RAM_SIZE);
3463       if(!offset&&s!=temp) emit_mov(s,temp);
3464       jaddr=(int)out;
3465       emit_jno(0);
3466     }
3467     else
3468     {
3469       if(!memtarget||!rs1[i]) {
3470         jaddr=(int)out;
3471         emit_jmp(0);
3472       }
3473     }
3474     #ifdef RAM_OFFSET
3475     int map=get_reg(i_regs->regmap,ROREG);
3476     if(map<0) emit_loadreg(ROREG,map=HOST_TEMPREG);
3477     gen_tlb_addr_w(temp,map);
3478     #else
3479     if((u_int)rdram!=0x80000000)
3480       emit_addimm_no_flags((u_int)rdram-(u_int)0x80000000,temp);
3481     #endif
3482   }else{ // using tlb
3483     int map=get_reg(i_regs->regmap,TLREG);
3484     assert(map>=0);
3485     reglist&=~(1<<map);
3486     map=do_tlb_w(c||s<0||offset?temp:s,temp,map,0,c,constmap[i][s]+offset);
3487     if(!c&&!offset&&s>=0) emit_mov(s,temp);
3488     do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr);
3489     if(!jaddr&&!memtarget) {
3490       jaddr=(int)out;
3491       emit_jmp(0);
3492     }
3493     gen_tlb_addr_w(temp,map);
3494   }
3495
3496   if (opcode[i]==0x2C||opcode[i]==0x2D) { // SDL/SDR
3497     temp2=get_reg(i_regs->regmap,FTEMP);
3498     if(!rs2[i]) temp2=th=tl;
3499   }
3500
3501 #ifndef BIG_ENDIAN_MIPS
3502     emit_xorimm(temp,3,temp);
3503 #endif
3504   emit_testimm(temp,2);
3505   case2=(int)out;
3506   emit_jne(0);
3507   emit_testimm(temp,1);
3508   case1=(int)out;
3509   emit_jne(0);
3510   // 0
3511   if (opcode[i]==0x2A) { // SWL
3512     emit_writeword_indexed(tl,0,temp);
3513   }
3514   if (opcode[i]==0x2E) { // SWR
3515     emit_writebyte_indexed(tl,3,temp);
3516   }
3517   if (opcode[i]==0x2C) { // SDL
3518     emit_writeword_indexed(th,0,temp);
3519     if(rs2[i]) emit_mov(tl,temp2);
3520   }
3521   if (opcode[i]==0x2D) { // SDR
3522     emit_writebyte_indexed(tl,3,temp);
3523     if(rs2[i]) emit_shldimm(th,tl,24,temp2);
3524   }
3525   done0=(int)out;
3526   emit_jmp(0);
3527   // 1
3528   set_jump_target(case1,(int)out);
3529   if (opcode[i]==0x2A) { // SWL
3530     // Write 3 msb into three least significant bytes
3531     if(rs2[i]) emit_rorimm(tl,8,tl);
3532     emit_writehword_indexed(tl,-1,temp);
3533     if(rs2[i]) emit_rorimm(tl,16,tl);
3534     emit_writebyte_indexed(tl,1,temp);
3535     if(rs2[i]) emit_rorimm(tl,8,tl);
3536   }
3537   if (opcode[i]==0x2E) { // SWR
3538     // Write two lsb into two most significant bytes
3539     emit_writehword_indexed(tl,1,temp);
3540   }
3541   if (opcode[i]==0x2C) { // SDL
3542     if(rs2[i]) emit_shrdimm(tl,th,8,temp2);
3543     // Write 3 msb into three least significant bytes
3544     if(rs2[i]) emit_rorimm(th,8,th);
3545     emit_writehword_indexed(th,-1,temp);
3546     if(rs2[i]) emit_rorimm(th,16,th);
3547     emit_writebyte_indexed(th,1,temp);
3548     if(rs2[i]) emit_rorimm(th,8,th);
3549   }
3550   if (opcode[i]==0x2D) { // SDR
3551     if(rs2[i]) emit_shldimm(th,tl,16,temp2);
3552     // Write two lsb into two most significant bytes
3553     emit_writehword_indexed(tl,1,temp);
3554   }
3555   done1=(int)out;
3556   emit_jmp(0);
3557   // 2
3558   set_jump_target(case2,(int)out);
3559   emit_testimm(temp,1);
3560   case3=(int)out;
3561   emit_jne(0);
3562   if (opcode[i]==0x2A) { // SWL
3563     // Write two msb into two least significant bytes
3564     if(rs2[i]) emit_rorimm(tl,16,tl);
3565     emit_writehword_indexed(tl,-2,temp);
3566     if(rs2[i]) emit_rorimm(tl,16,tl);
3567   }
3568   if (opcode[i]==0x2E) { // SWR
3569     // Write 3 lsb into three most significant bytes
3570     emit_writebyte_indexed(tl,-1,temp);
3571     if(rs2[i]) emit_rorimm(tl,8,tl);
3572     emit_writehword_indexed(tl,0,temp);
3573     if(rs2[i]) emit_rorimm(tl,24,tl);
3574   }
3575   if (opcode[i]==0x2C) { // SDL
3576     if(rs2[i]) emit_shrdimm(tl,th,16,temp2);
3577     // Write two msb into two least significant bytes
3578     if(rs2[i]) emit_rorimm(th,16,th);
3579     emit_writehword_indexed(th,-2,temp);
3580     if(rs2[i]) emit_rorimm(th,16,th);
3581   }
3582   if (opcode[i]==0x2D) { // SDR
3583     if(rs2[i]) emit_shldimm(th,tl,8,temp2);
3584     // Write 3 lsb into three most significant bytes
3585     emit_writebyte_indexed(tl,-1,temp);
3586     if(rs2[i]) emit_rorimm(tl,8,tl);
3587     emit_writehword_indexed(tl,0,temp);
3588     if(rs2[i]) emit_rorimm(tl,24,tl);
3589   }
3590   done2=(int)out;
3591   emit_jmp(0);
3592   // 3
3593   set_jump_target(case3,(int)out);
3594   if (opcode[i]==0x2A) { // SWL
3595     // Write msb into least significant byte
3596     if(rs2[i]) emit_rorimm(tl,24,tl);
3597     emit_writebyte_indexed(tl,-3,temp);
3598     if(rs2[i]) emit_rorimm(tl,8,tl);
3599   }
3600   if (opcode[i]==0x2E) { // SWR
3601     // Write entire word
3602     emit_writeword_indexed(tl,-3,temp);
3603   }
3604   if (opcode[i]==0x2C) { // SDL
3605     if(rs2[i]) emit_shrdimm(tl,th,24,temp2);
3606     // Write msb into least significant byte
3607     if(rs2[i]) emit_rorimm(th,24,th);
3608     emit_writebyte_indexed(th,-3,temp);
3609     if(rs2[i]) emit_rorimm(th,8,th);
3610   }
3611   if (opcode[i]==0x2D) { // SDR
3612     if(rs2[i]) emit_mov(th,temp2);
3613     // Write entire word
3614     emit_writeword_indexed(tl,-3,temp);
3615   }
3616   set_jump_target(done0,(int)out);
3617   set_jump_target(done1,(int)out);
3618   set_jump_target(done2,(int)out);
3619   if (opcode[i]==0x2C) { // SDL
3620     emit_testimm(temp,4);
3621     done0=(int)out;
3622     emit_jne(0);
3623     emit_andimm(temp,~3,temp);
3624     emit_writeword_indexed(temp2,4,temp);
3625     set_jump_target(done0,(int)out);
3626   }
3627   if (opcode[i]==0x2D) { // SDR
3628     emit_testimm(temp,4);
3629     done0=(int)out;
3630     emit_jeq(0);
3631     emit_andimm(temp,~3,temp);
3632     emit_writeword_indexed(temp2,-4,temp);
3633     set_jump_target(done0,(int)out);
3634   }
3635   if(!c||!memtarget)
3636     add_stub(STORELR_STUB,jaddr,(int)out,i,(int)i_regs,temp,ccadj[i],reglist);
3637   if(!using_tlb&&!(i_regs->waswritten&(1<<rs1[i]))&&!(new_dynarec_hacks&NDHACK_NO_SMC_CHECK)) {
3638     #ifdef RAM_OFFSET
3639     int map=get_reg(i_regs->regmap,ROREG);
3640     if(map<0) map=HOST_TEMPREG;
3641     gen_orig_addr_w(temp,map);
3642     #else
3643     emit_addimm_no_flags((u_int)0x80000000-(u_int)rdram,temp);
3644     #endif
3645     #if defined(HOST_IMM8)
3646     int ir=get_reg(i_regs->regmap,INVCP);
3647     assert(ir>=0);
3648     emit_cmpmem_indexedsr12_reg(ir,temp,1);
3649     #else
3650     emit_cmpmem_indexedsr12_imm((int)invalid_code,temp,1);
3651     #endif
3652     #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3653     emit_callne(invalidate_addr_reg[temp]);
3654     #else
3655     jaddr2=(int)out;
3656     emit_jne(0);
3657     add_stub(INVCODE_STUB,jaddr2,(int)out,reglist|(1<<HOST_CCREG),temp,0,0,0);
3658     #endif
3659   }
3660   /*
3661     emit_pusha();
3662     //save_regs(0x100f);
3663         emit_readword((int)&last_count,ECX);
3664         if(get_reg(i_regs->regmap,CCREG)<0)
3665           emit_loadreg(CCREG,HOST_CCREG);
3666         emit_add(HOST_CCREG,ECX,HOST_CCREG);
3667         emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3668         emit_writeword(HOST_CCREG,(int)&Count);
3669     emit_call((int)memdebug);
3670     emit_popa();
3671     //restore_regs(0x100f);
3672   /**/
3673 }
3674
3675 void c1ls_assemble(int i,struct regstat *i_regs)
3676 {
3677 #ifndef DISABLE_COP1
3678   int s,th,tl;
3679   int temp,ar;
3680   int map=-1;
3681   int offset;
3682   int c=0;
3683   int jaddr,jaddr2=0,jaddr3,type;
3684   int agr=AGEN1+(i&1);
3685   u_int hr,reglist=0;
3686   th=get_reg(i_regs->regmap,FTEMP|64);
3687   tl=get_reg(i_regs->regmap,FTEMP);
3688   s=get_reg(i_regs->regmap,rs1[i]);
3689   temp=get_reg(i_regs->regmap,agr);
3690   if(temp<0) temp=get_reg(i_regs->regmap,-1);
3691   offset=imm[i];
3692   assert(tl>=0);
3693   assert(rs1[i]>0);
3694   assert(temp>=0);
3695   for(hr=0;hr<HOST_REGS;hr++) {
3696     if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3697   }
3698   if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
3699   if (opcode[i]==0x31||opcode[i]==0x35) // LWC1/LDC1
3700   {
3701     // Loads use a temporary register which we need to save
3702     reglist|=1<<temp;
3703   }
3704   if (opcode[i]==0x39||opcode[i]==0x3D) // SWC1/SDC1
3705     ar=temp;
3706   else // LWC1/LDC1
3707     ar=tl;
3708   //if(s<0) emit_loadreg(rs1[i],ar); //address_generation does this now
3709   //else c=(i_regs->wasconst>>s)&1;
3710   if(s>=0) c=(i_regs->wasconst>>s)&1;
3711   // Check cop1 unusable
3712   if(!cop1_usable) {
3713     signed char rs=get_reg(i_regs->regmap,CSREG);
3714     assert(rs>=0);
3715     emit_testimm(rs,0x20000000);
3716     jaddr=(int)out;
3717     emit_jeq(0);
3718     add_stub(FP_STUB,jaddr,(int)out,i,rs,(int)i_regs,is_delayslot,0);
3719     cop1_usable=1;
3720   }
3721   if (opcode[i]==0x39) { // SWC1 (get float address)
3722     emit_readword((int)&reg_cop1_simple[(source[i]>>16)&0x1f],tl);
3723   }
3724   if (opcode[i]==0x3D) { // SDC1 (get double address)
3725     emit_readword((int)&reg_cop1_double[(source[i]>>16)&0x1f],tl);
3726   }
3727   // Generate address + offset
3728   if(!using_tlb) {
3729     if(!c)
3730       emit_cmpimm(offset||c||s<0?ar:s,RAM_SIZE);
3731   }
3732   else
3733   {
3734     map=get_reg(i_regs->regmap,TLREG);
3735     assert(map>=0);
3736     reglist&=~(1<<map);
3737     if (opcode[i]==0x31||opcode[i]==0x35) { // LWC1/LDC1
3738       map=do_tlb_r(offset||c||s<0?ar:s,ar,map,0,-1,-1,c,constmap[i][s]+offset);
3739     }
3740     if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3741       map=do_tlb_w(offset||c||s<0?ar:s,ar,map,0,c,constmap[i][s]+offset);
3742     }
3743   }
3744   if (opcode[i]==0x39) { // SWC1 (read float)
3745     emit_readword_indexed(0,tl,tl);
3746   }
3747   if (opcode[i]==0x3D) { // SDC1 (read double)
3748     emit_readword_indexed(4,tl,th);
3749     emit_readword_indexed(0,tl,tl);
3750   }
3751   if (opcode[i]==0x31) { // LWC1 (get target address)
3752     emit_readword((int)&reg_cop1_simple[(source[i]>>16)&0x1f],temp);
3753   }
3754   if (opcode[i]==0x35) { // LDC1 (get target address)
3755     emit_readword((int)&reg_cop1_double[(source[i]>>16)&0x1f],temp);
3756   }
3757   if(!using_tlb) {
3758     if(!c) {
3759       jaddr2=(int)out;
3760       emit_jno(0);
3761     }
3762     else if(((signed int)(constmap[i][s]+offset))>=(signed int)0x80000000+RAM_SIZE) {
3763       jaddr2=(int)out;
3764       emit_jmp(0); // inline_readstub/inline_writestub?  Very rare case
3765     }
3766     #ifdef DESTRUCTIVE_SHIFT
3767     if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3768       if(!offset&&!c&&s>=0) emit_mov(s,ar);
3769     }
3770     #endif
3771   }else{
3772     if (opcode[i]==0x31||opcode[i]==0x35) { // LWC1/LDC1
3773       do_tlb_r_branch(map,c,constmap[i][s]+offset,&jaddr2);
3774     }
3775     if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3776       do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr2);
3777     }
3778   }
3779   if (opcode[i]==0x31) { // LWC1
3780     //if(s>=0&&!c&&!offset) emit_mov(s,tl);
3781     //gen_tlb_addr_r(ar,map);
3782     //emit_readword_indexed((int)rdram-0x80000000,tl,tl);
3783     #ifdef HOST_IMM_ADDR32
3784     if(c) emit_readword_tlb(constmap[i][s]+offset,map,tl);
3785     else
3786     #endif
3787     emit_readword_indexed_tlb(0,offset||c||s<0?tl:s,map,tl);
3788     type=LOADW_STUB;
3789   }
3790   if (opcode[i]==0x35) { // LDC1
3791     assert(th>=0);
3792     //if(s>=0&&!c&&!offset) emit_mov(s,tl);
3793     //gen_tlb_addr_r(ar,map);
3794     //emit_readword_indexed((int)rdram-0x80000000,tl,th);
3795     //emit_readword_indexed((int)rdram-0x7FFFFFFC,tl,tl);
3796     #ifdef HOST_IMM_ADDR32
3797     if(c) emit_readdword_tlb(constmap[i][s]+offset,map,th,tl);
3798     else
3799     #endif
3800     emit_readdword_indexed_tlb(0,offset||c||s<0?tl:s,map,th,tl);
3801     type=LOADD_STUB;
3802   }
3803   if (opcode[i]==0x39) { // SWC1
3804     //emit_writeword_indexed(tl,(int)rdram-0x80000000,temp);
3805     emit_writeword_indexed_tlb(tl,0,offset||c||s<0?temp:s,map,temp);
3806     type=STOREW_STUB;
3807   }
3808   if (opcode[i]==0x3D) { // SDC1
3809     assert(th>=0);
3810     //emit_writeword_indexed(th,(int)rdram-0x80000000,temp);
3811     //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,temp);
3812     emit_writedword_indexed_tlb(th,tl,0,offset||c||s<0?temp:s,map,temp);
3813     type=STORED_STUB;
3814   }
3815   if(!using_tlb&&!(i_regs->waswritten&(1<<rs1[i]))&&!(new_dynarec_hacks&NDHACK_NO_SMC_CHECK)) {
3816     if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3817       #ifndef DESTRUCTIVE_SHIFT
3818       temp=offset||c||s<0?ar:s;
3819       #endif
3820       #if defined(HOST_IMM8)
3821       int ir=get_reg(i_regs->regmap,INVCP);
3822       assert(ir>=0);
3823       emit_cmpmem_indexedsr12_reg(ir,temp,1);
3824       #else
3825       emit_cmpmem_indexedsr12_imm((int)invalid_code,temp,1);
3826       #endif
3827       #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3828       emit_callne(invalidate_addr_reg[temp]);
3829       #else
3830       jaddr3=(int)out;
3831       emit_jne(0);
3832       add_stub(INVCODE_STUB,jaddr3,(int)out,reglist|(1<<HOST_CCREG),temp,0,0,0);
3833       #endif
3834     }
3835   }
3836   if(jaddr2) add_stub(type,jaddr2,(int)out,i,offset||c||s<0?ar:s,(int)i_regs,ccadj[i],reglist);
3837   if (opcode[i]==0x31) { // LWC1 (write float)
3838     emit_writeword_indexed(tl,0,temp);
3839   }
3840   if (opcode[i]==0x35) { // LDC1 (write double)
3841     emit_writeword_indexed(th,4,temp);
3842     emit_writeword_indexed(tl,0,temp);
3843   }
3844   //if(opcode[i]==0x39)
3845   /*if(opcode[i]==0x39||opcode[i]==0x31)
3846   {
3847     emit_pusha();
3848         emit_readword((int)&last_count,ECX);
3849         if(get_reg(i_regs->regmap,CCREG)<0)
3850           emit_loadreg(CCREG,HOST_CCREG);
3851         emit_add(HOST_CCREG,ECX,HOST_CCREG);
3852         emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3853         emit_writeword(HOST_CCREG,(int)&Count);
3854     emit_call((int)memdebug);
3855     emit_popa();
3856   }/**/
3857 #else
3858   cop1_unusable(i, i_regs);
3859 #endif
3860 }
3861
3862 void c2ls_assemble(int i,struct regstat *i_regs)
3863 {
3864   int s,tl;
3865   int ar;
3866   int offset;
3867   int memtarget=0,c=0;
3868   int jaddr2=0,jaddr3,type;
3869   int agr=AGEN1+(i&1);
3870   int fastio_reg_override=0;
3871   u_int hr,reglist=0;
3872   u_int copr=(source[i]>>16)&0x1f;
3873   s=get_reg(i_regs->regmap,rs1[i]);
3874   tl=get_reg(i_regs->regmap,FTEMP);
3875   offset=imm[i];
3876   assert(rs1[i]>0);
3877   assert(tl>=0);
3878   assert(!using_tlb);
3879
3880   for(hr=0;hr<HOST_REGS;hr++) {
3881     if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3882   }
3883   if(i_regs->regmap[HOST_CCREG]==CCREG)
3884     reglist&=~(1<<HOST_CCREG);
3885
3886   // get the address
3887   if (opcode[i]==0x3a) { // SWC2
3888     ar=get_reg(i_regs->regmap,agr);
3889     if(ar<0) ar=get_reg(i_regs->regmap,-1);
3890     reglist|=1<<ar;
3891   } else { // LWC2
3892     ar=tl;
3893   }
3894   if(s>=0) c=(i_regs->wasconst>>s)&1;
3895   memtarget=c&&(((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE);
3896   if (!offset&&!c&&s>=0) ar=s;
3897   assert(ar>=0);
3898
3899   if (opcode[i]==0x3a) { // SWC2
3900     cop2_get_dreg(copr,tl,HOST_TEMPREG);
3901     type=STOREW_STUB;
3902   }
3903   else
3904     type=LOADW_STUB;
3905
3906   if(c&&!memtarget) {
3907     jaddr2=(int)out;
3908     emit_jmp(0); // inline_readstub/inline_writestub?
3909   }
3910   else {
3911     if(!c) {
3912       jaddr2=emit_fastpath_cmp_jump(i,ar,&fastio_reg_override);
3913     }
3914     else if(ram_offset&&memtarget) {
3915       emit_addimm(ar,ram_offset,HOST_TEMPREG);
3916       fastio_reg_override=HOST_TEMPREG;
3917     }
3918     if (opcode[i]==0x32) { // LWC2
3919       #ifdef HOST_IMM_ADDR32
3920       if(c) emit_readword_tlb(constmap[i][s]+offset,-1,tl);
3921       else
3922       #endif
3923       int a=ar;
3924       if(fastio_reg_override) a=fastio_reg_override;
3925       emit_readword_indexed(0,a,tl);
3926     }
3927     if (opcode[i]==0x3a) { // SWC2
3928       #ifdef DESTRUCTIVE_SHIFT
3929       if(!offset&&!c&&s>=0) emit_mov(s,ar);
3930       #endif
3931       int a=ar;
3932       if(fastio_reg_override) a=fastio_reg_override;
3933       emit_writeword_indexed(tl,0,a);
3934     }
3935   }
3936   if(jaddr2)
3937     add_stub(type,jaddr2,(int)out,i,ar,(int)i_regs,ccadj[i],reglist);
3938   if(opcode[i]==0x3a) // SWC2
3939   if(!(i_regs->waswritten&(1<<rs1[i]))&&!(new_dynarec_hacks&NDHACK_NO_SMC_CHECK)) {
3940 #if defined(HOST_IMM8)
3941     int ir=get_reg(i_regs->regmap,INVCP);
3942     assert(ir>=0);
3943     emit_cmpmem_indexedsr12_reg(ir,ar,1);
3944 #else
3945     emit_cmpmem_indexedsr12_imm((int)invalid_code,ar,1);
3946 #endif
3947     #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3948     emit_callne(invalidate_addr_reg[ar]);
3949     #else
3950     jaddr3=(int)out;
3951     emit_jne(0);
3952     add_stub(INVCODE_STUB,jaddr3,(int)out,reglist|(1<<HOST_CCREG),ar,0,0,0);
3953     #endif
3954   }
3955   if (opcode[i]==0x32) { // LWC2
3956     cop2_put_dreg(copr,tl,HOST_TEMPREG);
3957   }
3958 }
3959
3960 #ifndef multdiv_assemble
3961 void multdiv_assemble(int i,struct regstat *i_regs)
3962 {
3963   printf("Need multdiv_assemble for this architecture.\n");
3964   exit(1);
3965 }
3966 #endif
3967
3968 void mov_assemble(int i,struct regstat *i_regs)
3969 {
3970   //if(opcode2[i]==0x10||opcode2[i]==0x12) { // MFHI/MFLO
3971   //if(opcode2[i]==0x11||opcode2[i]==0x13) { // MTHI/MTLO
3972   if(rt1[i]) {
3973     signed char sh,sl,th,tl;
3974     th=get_reg(i_regs->regmap,rt1[i]|64);
3975     tl=get_reg(i_regs->regmap,rt1[i]);
3976     //assert(tl>=0);
3977     if(tl>=0) {
3978       sh=get_reg(i_regs->regmap,rs1[i]|64);
3979       sl=get_reg(i_regs->regmap,rs1[i]);
3980       if(sl>=0) emit_mov(sl,tl);
3981       else emit_loadreg(rs1[i],tl);
3982       if(th>=0) {
3983         if(sh>=0) emit_mov(sh,th);
3984         else emit_loadreg(rs1[i]|64,th);
3985       }
3986     }
3987   }
3988 }
3989
3990 #ifndef fconv_assemble
3991 void fconv_assemble(int i,struct regstat *i_regs)
3992 {
3993   printf("Need fconv_assemble for this architecture.\n");
3994   exit(1);
3995 }
3996 #endif
3997
3998 #if 0
3999 void float_assemble(int i,struct regstat *i_regs)
4000 {
4001   printf("Need float_assemble for this architecture.\n");
4002   exit(1);
4003 }
4004 #endif
4005
4006 void syscall_assemble(int i,struct regstat *i_regs)
4007 {
4008   signed char ccreg=get_reg(i_regs->regmap,CCREG);
4009   assert(ccreg==HOST_CCREG);
4010   assert(!is_delayslot);
4011   emit_movimm(start+i*4,EAX); // Get PC
4012   emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i]),HOST_CCREG); // CHECK: is this right?  There should probably be an extra cycle...
4013   emit_jmp((int)jump_syscall_hle); // XXX
4014 }
4015
4016 void hlecall_assemble(int i,struct regstat *i_regs)
4017 {
4018   signed char ccreg=get_reg(i_regs->regmap,CCREG);
4019   assert(ccreg==HOST_CCREG);
4020   assert(!is_delayslot);
4021   emit_movimm(start+i*4+4,0); // Get PC
4022   emit_movimm((int)psxHLEt[source[i]&7],1);
4023   emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i]),HOST_CCREG); // XXX
4024   emit_jmp((int)jump_hlecall);
4025 }
4026
4027 void intcall_assemble(int i,struct regstat *i_regs)
4028 {
4029   signed char ccreg=get_reg(i_regs->regmap,CCREG);
4030   assert(ccreg==HOST_CCREG);
4031   assert(!is_delayslot);
4032   emit_movimm(start+i*4,0); // Get PC
4033   emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i]),HOST_CCREG);
4034   emit_jmp((int)jump_intcall);
4035 }
4036
4037 void ds_assemble(int i,struct regstat *i_regs)
4038 {
4039   speculate_register_values(i);
4040   is_delayslot=1;
4041   switch(itype[i]) {
4042     case ALU:
4043       alu_assemble(i,i_regs);break;
4044     case IMM16:
4045       imm16_assemble(i,i_regs);break;
4046     case SHIFT:
4047       shift_assemble(i,i_regs);break;
4048     case SHIFTIMM:
4049       shiftimm_assemble(i,i_regs);break;
4050     case LOAD:
4051       load_assemble(i,i_regs);break;
4052     case LOADLR:
4053       loadlr_assemble(i,i_regs);break;
4054     case STORE:
4055       store_assemble(i,i_regs);break;
4056     case STORELR:
4057       storelr_assemble(i,i_regs);break;
4058     case COP0:
4059       cop0_assemble(i,i_regs);break;
4060     case COP1:
4061       cop1_assemble(i,i_regs);break;
4062     case C1LS:
4063       c1ls_assemble(i,i_regs);break;
4064     case COP2:
4065       cop2_assemble(i,i_regs);break;
4066     case C2LS:
4067       c2ls_assemble(i,i_regs);break;
4068     case C2OP:
4069       c2op_assemble(i,i_regs);break;
4070     case FCONV:
4071       fconv_assemble(i,i_regs);break;
4072     case FLOAT:
4073       float_assemble(i,i_regs);break;
4074     case FCOMP:
4075       fcomp_assemble(i,i_regs);break;
4076     case MULTDIV:
4077       multdiv_assemble(i,i_regs);break;
4078     case MOV:
4079       mov_assemble(i,i_regs);break;
4080     case SYSCALL:
4081     case HLECALL:
4082     case INTCALL:
4083     case SPAN:
4084     case UJUMP:
4085     case RJUMP:
4086     case CJUMP:
4087     case SJUMP:
4088     case FJUMP:
4089       SysPrintf("Jump in the delay slot.  This is probably a bug.\n");
4090   }
4091   is_delayslot=0;
4092 }
4093
4094 // Is the branch target a valid internal jump?
4095 int internal_branch(uint64_t i_is32,int addr)
4096 {
4097   if(addr&1) return 0; // Indirect (register) jump
4098   if(addr>=start && addr<start+slen*4-4)
4099   {
4100     int t=(addr-start)>>2;
4101     // Delay slots are not valid branch targets
4102     //if(t>0&&(itype[t-1]==RJUMP||itype[t-1]==UJUMP||itype[t-1]==CJUMP||itype[t-1]==SJUMP||itype[t-1]==FJUMP)) return 0;
4103     // 64 -> 32 bit transition requires a recompile
4104     /*if(is32[t]&~unneeded_reg_upper[t]&~i_is32)
4105     {
4106       if(requires_32bit[t]&~i_is32) printf("optimizable: no\n");
4107       else printf("optimizable: yes\n");
4108     }*/
4109     //if(is32[t]&~unneeded_reg_upper[t]&~i_is32) return 0;
4110 #ifndef FORCE32
4111     if(requires_32bit[t]&~i_is32) return 0;
4112     else
4113 #endif
4114       return 1;
4115   }
4116   return 0;
4117 }
4118
4119 #ifndef wb_invalidate
4120 void wb_invalidate(signed char pre[],signed char entry[],uint64_t dirty,uint64_t is32,
4121   uint64_t u,uint64_t uu)
4122 {
4123   int hr;
4124   for(hr=0;hr<HOST_REGS;hr++) {
4125     if(hr!=EXCLUDE_REG) {
4126       if(pre[hr]!=entry[hr]) {
4127         if(pre[hr]>=0) {
4128           if((dirty>>hr)&1) {
4129             if(get_reg(entry,pre[hr])<0) {
4130               if(pre[hr]<64) {
4131                 if(!((u>>pre[hr])&1)) {
4132                   emit_storereg(pre[hr],hr);
4133                   if( ((is32>>pre[hr])&1) && !((uu>>pre[hr])&1) ) {
4134                     emit_sarimm(hr,31,hr);
4135                     emit_storereg(pre[hr]|64,hr);
4136                   }
4137                 }
4138               }else{
4139                 if(!((uu>>(pre[hr]&63))&1) && !((is32>>(pre[hr]&63))&1)) {
4140                   emit_storereg(pre[hr],hr);
4141                 }
4142               }
4143             }
4144           }
4145         }
4146       }
4147     }
4148   }
4149   // Move from one register to another (no writeback)
4150   for(hr=0;hr<HOST_REGS;hr++) {
4151     if(hr!=EXCLUDE_REG) {
4152       if(pre[hr]!=entry[hr]) {
4153         if(pre[hr]>=0&&(pre[hr]&63)<TEMPREG) {
4154           int nr;
4155           if((nr=get_reg(entry,pre[hr]))>=0) {
4156             emit_mov(hr,nr);
4157           }
4158         }
4159       }
4160     }
4161   }
4162 }
4163 #endif
4164
4165 // Load the specified registers
4166 // This only loads the registers given as arguments because
4167 // we don't want to load things that will be overwritten
4168 void load_regs(signed char entry[],signed char regmap[],int is32,int rs1,int rs2)
4169 {
4170   int hr;
4171   // Load 32-bit regs
4172   for(hr=0;hr<HOST_REGS;hr++) {
4173     if(hr!=EXCLUDE_REG&&regmap[hr]>=0) {
4174       if(entry[hr]!=regmap[hr]) {
4175         if(regmap[hr]==rs1||regmap[hr]==rs2)
4176         {
4177           if(regmap[hr]==0) {
4178             emit_zeroreg(hr);
4179           }
4180           else
4181           {
4182             emit_loadreg(regmap[hr],hr);
4183           }
4184         }
4185       }
4186     }
4187   }
4188   //Load 64-bit regs
4189   for(hr=0;hr<HOST_REGS;hr++) {
4190     if(hr!=EXCLUDE_REG&&regmap[hr]>=0) {
4191       if(entry[hr]!=regmap[hr]) {
4192         if(regmap[hr]-64==rs1||regmap[hr]-64==rs2)
4193         {
4194           assert(regmap[hr]!=64);
4195           if((is32>>(regmap[hr]&63))&1) {
4196             int lr=get_reg(regmap,regmap[hr]-64);
4197             if(lr>=0)
4198               emit_sarimm(lr,31,hr);
4199             else
4200               emit_loadreg(regmap[hr],hr);
4201           }
4202           else
4203           {
4204             emit_loadreg(regmap[hr],hr);
4205           }
4206         }
4207       }
4208     }
4209   }
4210 }
4211
4212 // Load registers prior to the start of a loop
4213 // so that they are not loaded within the loop
4214 static void loop_preload(signed char pre[],signed char entry[])
4215 {
4216   int hr;
4217   for(hr=0;hr<HOST_REGS;hr++) {
4218     if(hr!=EXCLUDE_REG) {
4219       if(pre[hr]!=entry[hr]) {
4220         if(entry[hr]>=0) {
4221           if(get_reg(pre,entry[hr])<0) {
4222             assem_debug("loop preload:\n");
4223             //printf("loop preload: %d\n",hr);
4224             if(entry[hr]==0) {
4225               emit_zeroreg(hr);
4226             }
4227             else if(entry[hr]<TEMPREG)
4228             {
4229               emit_loadreg(entry[hr],hr);
4230             }
4231             else if(entry[hr]-64<TEMPREG)
4232             {
4233               emit_loadreg(entry[hr],hr);
4234             }
4235           }
4236         }
4237       }
4238     }
4239   }
4240 }
4241
4242 // Generate address for load/store instruction
4243 // goes to AGEN for writes, FTEMP for LOADLR and cop1/2 loads
4244 void address_generation(int i,struct regstat *i_regs,signed char entry[])
4245 {
4246   if(itype[i]==LOAD||itype[i]==LOADLR||itype[i]==STORE||itype[i]==STORELR||itype[i]==C1LS||itype[i]==C2LS) {
4247     int ra=-1;
4248     int agr=AGEN1+(i&1);
4249     int mgr=MGEN1+(i&1);
4250     if(itype[i]==LOAD) {
4251       ra=get_reg(i_regs->regmap,rt1[i]);
4252       if(ra<0) ra=get_reg(i_regs->regmap,-1);
4253       assert(ra>=0);
4254     }
4255     if(itype[i]==LOADLR) {
4256       ra=get_reg(i_regs->regmap,FTEMP);
4257     }
4258     if(itype[i]==STORE||itype[i]==STORELR) {
4259       ra=get_reg(i_regs->regmap,agr);
4260       if(ra<0) ra=get_reg(i_regs->regmap,-1);
4261     }
4262     if(itype[i]==C1LS||itype[i]==C2LS) {
4263       if ((opcode[i]&0x3b)==0x31||(opcode[i]&0x3b)==0x32) // LWC1/LDC1/LWC2/LDC2
4264         ra=get_reg(i_regs->regmap,FTEMP);
4265       else { // SWC1/SDC1/SWC2/SDC2
4266         ra=get_reg(i_regs->regmap,agr);
4267         if(ra<0) ra=get_reg(i_regs->regmap,-1);
4268       }
4269     }
4270     int rs=get_reg(i_regs->regmap,rs1[i]);
4271     int rm=get_reg(i_regs->regmap,TLREG);
4272     if(ra>=0) {
4273       int offset=imm[i];
4274       int c=(i_regs->wasconst>>rs)&1;
4275       if(rs1[i]==0) {
4276         // Using r0 as a base address
4277         /*if(rm>=0) {
4278           if(!entry||entry[rm]!=mgr) {
4279             generate_map_const(offset,rm);
4280           } // else did it in the previous cycle
4281         }*/
4282         if(!entry||entry[ra]!=agr) {
4283           if (opcode[i]==0x22||opcode[i]==0x26) {
4284             emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR
4285           }else if (opcode[i]==0x1a||opcode[i]==0x1b) {
4286             emit_movimm(offset&0xFFFFFFF8,ra); // LDL/LDR
4287           }else{
4288             emit_movimm(offset,ra);
4289           }
4290         } // else did it in the previous cycle
4291       }
4292       else if(rs<0) {
4293         if(!entry||entry[ra]!=rs1[i])
4294           emit_loadreg(rs1[i],ra);
4295         //if(!entry||entry[ra]!=rs1[i])
4296         //  printf("poor load scheduling!\n");
4297       }
4298       else if(c) {
4299 #ifndef DISABLE_TLB
4300         if(rm>=0) {
4301           if(!entry||entry[rm]!=mgr) {
4302             if(itype[i]==STORE||itype[i]==STORELR||(opcode[i]&0x3b)==0x39||(opcode[i]&0x3b)==0x3a) {
4303               // Stores to memory go thru the mapper to detect self-modifying
4304               // code, loads don't.
4305               if((unsigned int)(constmap[i][rs]+offset)>=0xC0000000 ||
4306                  (unsigned int)(constmap[i][rs]+offset)<0x80000000+RAM_SIZE )
4307                 generate_map_const(constmap[i][rs]+offset,rm);
4308             }else{
4309               if((signed int)(constmap[i][rs]+offset)>=(signed int)0xC0000000)
4310                 generate_map_const(constmap[i][rs]+offset,rm);
4311             }
4312           }
4313         }
4314 #endif
4315         if(rs1[i]!=rt1[i]||itype[i]!=LOAD) {
4316           if(!entry||entry[ra]!=agr) {
4317             if (opcode[i]==0x22||opcode[i]==0x26) {
4318               emit_movimm((constmap[i][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR
4319             }else if (opcode[i]==0x1a||opcode[i]==0x1b) {
4320               emit_movimm((constmap[i][rs]+offset)&0xFFFFFFF8,ra); // LDL/LDR
4321             }else{
4322               #ifdef HOST_IMM_ADDR32
4323               if((itype[i]!=LOAD&&(opcode[i]&0x3b)!=0x31&&(opcode[i]&0x3b)!=0x32) || // LWC1/LDC1/LWC2/LDC2
4324                  (using_tlb&&((signed int)constmap[i][rs]+offset)>=(signed int)0xC0000000))
4325               #endif
4326               emit_movimm(constmap[i][rs]+offset,ra);
4327               regs[i].loadedconst|=1<<ra;
4328             }
4329           } // else did it in the previous cycle
4330         } // else load_consts already did it
4331       }
4332       if(offset&&!c&&rs1[i]) {
4333         if(rs>=0) {
4334           emit_addimm(rs,offset,ra);
4335         }else{
4336           emit_addimm(ra,offset,ra);
4337         }
4338       }
4339     }
4340   }
4341   // Preload constants for next instruction
4342   if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS||itype[i+1]==C2LS) {
4343     int agr,ra;
4344     #if !defined(HOST_IMM_ADDR32) && !defined(DISABLE_TLB)
4345     // Mapper entry
4346     agr=MGEN1+((i+1)&1);
4347     ra=get_reg(i_regs->regmap,agr);
4348     if(ra>=0) {
4349       int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
4350       int offset=imm[i+1];
4351       int c=(regs[i+1].wasconst>>rs)&1;
4352       if(c) {
4353         if(itype[i+1]==STORE||itype[i+1]==STORELR
4354            ||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a) { // SWC1/SDC1, SWC2/SDC2
4355           // Stores to memory go thru the mapper to detect self-modifying
4356           // code, loads don't.
4357           if((unsigned int)(constmap[i+1][rs]+offset)>=0xC0000000 ||
4358              (unsigned int)(constmap[i+1][rs]+offset)<0x80000000+RAM_SIZE )
4359             generate_map_const(constmap[i+1][rs]+offset,ra);
4360         }else{
4361           if((signed int)(constmap[i+1][rs]+offset)>=(signed int)0xC0000000)
4362             generate_map_const(constmap[i+1][rs]+offset,ra);
4363         }
4364       }
4365       /*else if(rs1[i]==0) {
4366         generate_map_const(offset,ra);
4367       }*/
4368     }
4369     #endif
4370     // Actual address
4371     agr=AGEN1+((i+1)&1);
4372     ra=get_reg(i_regs->regmap,agr);
4373     if(ra>=0) {
4374       int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
4375       int offset=imm[i+1];
4376       int c=(regs[i+1].wasconst>>rs)&1;
4377       if(c&&(rs1[i+1]!=rt1[i+1]||itype[i+1]!=LOAD)) {
4378         if (opcode[i+1]==0x22||opcode[i+1]==0x26) {
4379           emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR
4380         }else if (opcode[i+1]==0x1a||opcode[i+1]==0x1b) {
4381           emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFF8,ra); // LDL/LDR
4382         }else{
4383           #ifdef HOST_IMM_ADDR32
4384           if((itype[i+1]!=LOAD&&(opcode[i+1]&0x3b)!=0x31&&(opcode[i+1]&0x3b)!=0x32) || // LWC1/LDC1/LWC2/LDC2
4385              (using_tlb&&((signed int)constmap[i+1][rs]+offset)>=(signed int)0xC0000000))
4386           #endif
4387           emit_movimm(constmap[i+1][rs]+offset,ra);
4388           regs[i+1].loadedconst|=1<<ra;
4389         }
4390       }
4391       else if(rs1[i+1]==0) {
4392         // Using r0 as a base address
4393         if (opcode[i+1]==0x22||opcode[i+1]==0x26) {
4394           emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR
4395         }else if (opcode[i+1]==0x1a||opcode[i+1]==0x1b) {
4396           emit_movimm(offset&0xFFFFFFF8,ra); // LDL/LDR
4397         }else{
4398           emit_movimm(offset,ra);
4399         }
4400       }
4401     }
4402   }
4403 }
4404
4405 int get_final_value(int hr, int i, int *value)
4406 {
4407   int reg=regs[i].regmap[hr];
4408   while(i<slen-1) {
4409     if(regs[i+1].regmap[hr]!=reg) break;
4410     if(!((regs[i+1].isconst>>hr)&1)) break;
4411     if(bt[i+1]) break;
4412     i++;
4413   }
4414   if(i<slen-1) {
4415     if(itype[i]==UJUMP||itype[i]==RJUMP||itype[i]==CJUMP||itype[i]==SJUMP) {
4416       *value=constmap[i][hr];
4417       return 1;
4418     }
4419     if(!bt[i+1]) {
4420       if(itype[i+1]==UJUMP||itype[i+1]==RJUMP||itype[i+1]==CJUMP||itype[i+1]==SJUMP) {
4421         // Load in delay slot, out-of-order execution
4422         if(itype[i+2]==LOAD&&rs1[i+2]==reg&&rt1[i+2]==reg&&((regs[i+1].wasconst>>hr)&1))
4423         {
4424           #ifdef HOST_IMM_ADDR32
4425           if(!using_tlb||((signed int)constmap[i][hr]+imm[i+2])<(signed int)0xC0000000) return 0;
4426           #endif
4427           // Precompute load address
4428           *value=constmap[i][hr]+imm[i+2];
4429           return 1;
4430         }
4431       }
4432       if(itype[i+1]==LOAD&&rs1[i+1]==reg&&rt1[i+1]==reg)
4433       {
4434         #ifdef HOST_IMM_ADDR32
4435         if(!using_tlb||((signed int)constmap[i][hr]+imm[i+1])<(signed int)0xC0000000) return 0;
4436         #endif
4437         // Precompute load address
4438         *value=constmap[i][hr]+imm[i+1];
4439         //printf("c=%x imm=%x\n",(int)constmap[i][hr],imm[i+1]);
4440         return 1;
4441       }
4442     }
4443   }
4444   *value=constmap[i][hr];
4445   //printf("c=%x\n",(int)constmap[i][hr]);
4446   if(i==slen-1) return 1;
4447   if(reg<64) {
4448     return !((unneeded_reg[i+1]>>reg)&1);
4449   }else{
4450     return !((unneeded_reg_upper[i+1]>>reg)&1);
4451   }
4452 }
4453
4454 // Load registers with known constants
4455 void load_consts(signed char pre[],signed char regmap[],int is32,int i)
4456 {
4457   int hr,hr2;
4458   // propagate loaded constant flags
4459   if(i==0||bt[i])
4460     regs[i].loadedconst=0;
4461   else {
4462     for(hr=0;hr<HOST_REGS;hr++) {
4463       if(hr!=EXCLUDE_REG&&regmap[hr]>=0&&((regs[i-1].isconst>>hr)&1)&&pre[hr]==regmap[hr]
4464          &&regmap[hr]==regs[i-1].regmap[hr]&&((regs[i-1].loadedconst>>hr)&1))
4465       {
4466         regs[i].loadedconst|=1<<hr;
4467       }
4468     }
4469   }
4470   // Load 32-bit regs
4471   for(hr=0;hr<HOST_REGS;hr++) {
4472     if(hr!=EXCLUDE_REG&&regmap[hr]>=0) {
4473       //if(entry[hr]!=regmap[hr]) {
4474       if(!((regs[i].loadedconst>>hr)&1)) {
4475         if(((regs[i].isconst>>hr)&1)&&regmap[hr]<64&&regmap[hr]>0) {
4476           int value,similar=0;
4477           if(get_final_value(hr,i,&value)) {
4478             // see if some other register has similar value
4479             for(hr2=0;hr2<HOST_REGS;hr2++) {
4480               if(hr2!=EXCLUDE_REG&&((regs[i].loadedconst>>hr2)&1)) {
4481                 if(is_similar_value(value,constmap[i][hr2])) {
4482                   similar=1;
4483                   break;
4484                 }
4485               }
4486             }
4487             if(similar) {
4488               int value2;
4489               if(get_final_value(hr2,i,&value2)) // is this needed?
4490                 emit_movimm_from(value2,hr2,value,hr);
4491               else
4492                 emit_movimm(value,hr);
4493             }
4494             else if(value==0) {
4495               emit_zeroreg(hr);
4496             }
4497             else {
4498               emit_movimm(value,hr);
4499             }
4500           }
4501           regs[i].loadedconst|=1<<hr;
4502         }
4503       }
4504     }
4505   }
4506   // Load 64-bit regs
4507   for(hr=0;hr<HOST_REGS;hr++) {
4508     if(hr!=EXCLUDE_REG&&regmap[hr]>=0) {
4509       //if(entry[hr]!=regmap[hr]) {
4510       if(i==0||!((regs[i-1].isconst>>hr)&1)||pre[hr]!=regmap[hr]||bt[i]) {
4511         if(((regs[i].isconst>>hr)&1)&&regmap[hr]>64) {
4512           if((is32>>(regmap[hr]&63))&1) {
4513             int lr=get_reg(regmap,regmap[hr]-64);
4514             assert(lr>=0);
4515             emit_sarimm(lr,31,hr);
4516           }
4517           else
4518           {
4519             int value;
4520             if(get_final_value(hr,i,&value)) {
4521               if(value==0) {
4522                 emit_zeroreg(hr);
4523               }
4524               else {
4525                 emit_movimm(value,hr);
4526               }
4527             }
4528           }
4529         }
4530       }
4531     }
4532   }
4533 }
4534 void load_all_consts(signed char regmap[],int is32,u_int dirty,int i)
4535 {
4536   int hr;
4537   // Load 32-bit regs
4538   for(hr=0;hr<HOST_REGS;hr++) {
4539     if(hr!=EXCLUDE_REG&&regmap[hr]>=0&&((dirty>>hr)&1)) {
4540       if(((regs[i].isconst>>hr)&1)&&regmap[hr]<64&&regmap[hr]>0) {
4541         int value=constmap[i][hr];
4542         if(value==0) {
4543           emit_zeroreg(hr);
4544         }
4545         else {
4546           emit_movimm(value,hr);
4547         }
4548       }
4549     }
4550   }
4551   // Load 64-bit regs
4552   for(hr=0;hr<HOST_REGS;hr++) {
4553     if(hr!=EXCLUDE_REG&&regmap[hr]>=0&&((dirty>>hr)&1)) {
4554       if(((regs[i].isconst>>hr)&1)&&regmap[hr]>64) {
4555         if((is32>>(regmap[hr]&63))&1) {
4556           int lr=get_reg(regmap,regmap[hr]-64);
4557           assert(lr>=0);
4558           emit_sarimm(lr,31,hr);
4559         }
4560         else
4561         {
4562           int value=constmap[i][hr];
4563           if(value==0) {
4564             emit_zeroreg(hr);
4565           }
4566           else {
4567             emit_movimm(value,hr);
4568           }
4569         }
4570       }
4571     }
4572   }
4573 }
4574
4575 // Write out all dirty registers (except cycle count)
4576 void wb_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty)
4577 {
4578   int hr;
4579   for(hr=0;hr<HOST_REGS;hr++) {
4580     if(hr!=EXCLUDE_REG) {
4581       if(i_regmap[hr]>0) {
4582         if(i_regmap[hr]!=CCREG) {
4583           if((i_dirty>>hr)&1) {
4584             if(i_regmap[hr]<64) {
4585               emit_storereg(i_regmap[hr],hr);
4586 #ifndef FORCE32
4587               if( ((i_is32>>i_regmap[hr])&1) ) {
4588                 #ifdef DESTRUCTIVE_WRITEBACK
4589                 emit_sarimm(hr,31,hr);
4590                 emit_storereg(i_regmap[hr]|64,hr);
4591                 #else
4592                 emit_sarimm(hr,31,HOST_TEMPREG);
4593                 emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
4594                 #endif
4595               }
4596 #endif
4597             }else{
4598               if( !((i_is32>>(i_regmap[hr]&63))&1) ) {
4599                 emit_storereg(i_regmap[hr],hr);
4600               }
4601             }
4602           }
4603         }
4604       }
4605     }
4606   }
4607 }
4608 // Write out dirty registers that we need to reload (pair with load_needed_regs)
4609 // This writes the registers not written by store_regs_bt
4610 void wb_needed_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4611 {
4612   int hr;
4613   int t=(addr-start)>>2;
4614   for(hr=0;hr<HOST_REGS;hr++) {
4615     if(hr!=EXCLUDE_REG) {
4616       if(i_regmap[hr]>0) {
4617         if(i_regmap[hr]!=CCREG) {
4618           if(i_regmap[hr]==regs[t].regmap_entry[hr] && ((regs[t].dirty>>hr)&1) && !(((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) {
4619             if((i_dirty>>hr)&1) {
4620               if(i_regmap[hr]<64) {
4621                 emit_storereg(i_regmap[hr],hr);
4622 #ifndef FORCE32
4623                 if( ((i_is32>>i_regmap[hr])&1) ) {
4624                   #ifdef DESTRUCTIVE_WRITEBACK
4625                   emit_sarimm(hr,31,hr);
4626                   emit_storereg(i_regmap[hr]|64,hr);
4627                   #else
4628                   emit_sarimm(hr,31,HOST_TEMPREG);
4629                   emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
4630                   #endif
4631                 }
4632 #endif
4633               }else{
4634                 if( !((i_is32>>(i_regmap[hr]&63))&1) ) {
4635                   emit_storereg(i_regmap[hr],hr);
4636                 }
4637               }
4638             }
4639           }
4640         }
4641       }
4642     }
4643   }
4644 }
4645
4646 // Load all registers (except cycle count)
4647 void load_all_regs(signed char i_regmap[])
4648 {
4649   int hr;
4650   for(hr=0;hr<HOST_REGS;hr++) {
4651     if(hr!=EXCLUDE_REG) {
4652       if(i_regmap[hr]==0) {
4653         emit_zeroreg(hr);
4654       }
4655       else
4656       if(i_regmap[hr]>0 && (i_regmap[hr]&63)<TEMPREG && i_regmap[hr]!=CCREG)
4657       {
4658         emit_loadreg(i_regmap[hr],hr);
4659       }
4660     }
4661   }
4662 }
4663
4664 // Load all current registers also needed by next instruction
4665 void load_needed_regs(signed char i_regmap[],signed char next_regmap[])
4666 {
4667   int hr;
4668   for(hr=0;hr<HOST_REGS;hr++) {
4669     if(hr!=EXCLUDE_REG) {
4670       if(get_reg(next_regmap,i_regmap[hr])>=0) {
4671         if(i_regmap[hr]==0) {
4672           emit_zeroreg(hr);
4673         }
4674         else
4675         if(i_regmap[hr]>0 && (i_regmap[hr]&63)<TEMPREG && i_regmap[hr]!=CCREG)
4676         {
4677           emit_loadreg(i_regmap[hr],hr);
4678         }
4679       }
4680     }
4681   }
4682 }
4683
4684 // Load all regs, storing cycle count if necessary
4685 void load_regs_entry(int t)
4686 {
4687   int hr;
4688   if(is_ds[t]) emit_addimm(HOST_CCREG,CLOCK_ADJUST(1),HOST_CCREG);
4689   else if(ccadj[t]) emit_addimm(HOST_CCREG,-CLOCK_ADJUST(ccadj[t]),HOST_CCREG);
4690   if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) {
4691     emit_storereg(CCREG,HOST_CCREG);
4692   }
4693   // Load 32-bit regs
4694   for(hr=0;hr<HOST_REGS;hr++) {
4695     if(regs[t].regmap_entry[hr]>=0&&regs[t].regmap_entry[hr]<TEMPREG) {
4696       if(regs[t].regmap_entry[hr]==0) {
4697         emit_zeroreg(hr);
4698       }
4699       else if(regs[t].regmap_entry[hr]!=CCREG)
4700       {
4701         emit_loadreg(regs[t].regmap_entry[hr],hr);
4702       }
4703     }
4704   }
4705   // Load 64-bit regs
4706   for(hr=0;hr<HOST_REGS;hr++) {
4707     if(regs[t].regmap_entry[hr]>=64&&regs[t].regmap_entry[hr]<TEMPREG+64) {
4708       assert(regs[t].regmap_entry[hr]!=64);
4709       if((regs[t].was32>>(regs[t].regmap_entry[hr]&63))&1) {
4710         int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64);
4711         if(lr<0) {
4712           emit_loadreg(regs[t].regmap_entry[hr],hr);
4713         }
4714         else
4715         {
4716           emit_sarimm(lr,31,hr);
4717         }
4718       }
4719       else
4720       {
4721         emit_loadreg(regs[t].regmap_entry[hr],hr);
4722       }
4723     }
4724   }
4725 }
4726
4727 // Store dirty registers prior to branch
4728 void store_regs_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4729 {
4730   if(internal_branch(i_is32,addr))
4731   {
4732     int t=(addr-start)>>2;
4733     int hr;
4734     for(hr=0;hr<HOST_REGS;hr++) {
4735       if(hr!=EXCLUDE_REG) {
4736         if(i_regmap[hr]>0 && i_regmap[hr]!=CCREG) {
4737           if(i_regmap[hr]!=regs[t].regmap_entry[hr] || !((regs[t].dirty>>hr)&1) || (((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) {
4738             if((i_dirty>>hr)&1) {
4739               if(i_regmap[hr]<64) {
4740                 if(!((unneeded_reg[t]>>i_regmap[hr])&1)) {
4741                   emit_storereg(i_regmap[hr],hr);
4742                   if( ((i_is32>>i_regmap[hr])&1) && !((unneeded_reg_upper[t]>>i_regmap[hr])&1) ) {
4743                     #ifdef DESTRUCTIVE_WRITEBACK
4744                     emit_sarimm(hr,31,hr);
4745                     emit_storereg(i_regmap[hr]|64,hr);
4746                     #else
4747                     emit_sarimm(hr,31,HOST_TEMPREG);
4748                     emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
4749                     #endif
4750                   }
4751                 }
4752               }else{
4753                 if( !((i_is32>>(i_regmap[hr]&63))&1) && !((unneeded_reg_upper[t]>>(i_regmap[hr]&63))&1) ) {
4754                   emit_storereg(i_regmap[hr],hr);
4755                 }
4756               }
4757             }
4758           }
4759         }
4760       }
4761     }
4762   }
4763   else
4764   {
4765     // Branch out of this block, write out all dirty regs
4766     wb_dirtys(i_regmap,i_is32,i_dirty);
4767   }
4768 }
4769
4770 // Load all needed registers for branch target
4771 void load_regs_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4772 {
4773   //if(addr>=start && addr<(start+slen*4))
4774   if(internal_branch(i_is32,addr))
4775   {
4776     int t=(addr-start)>>2;
4777     int hr;
4778     // Store the cycle count before loading something else
4779     if(i_regmap[HOST_CCREG]!=CCREG) {
4780       assert(i_regmap[HOST_CCREG]==-1);
4781     }
4782     if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) {
4783       emit_storereg(CCREG,HOST_CCREG);
4784     }
4785     // Load 32-bit regs
4786     for(hr=0;hr<HOST_REGS;hr++) {
4787       if(hr!=EXCLUDE_REG&&regs[t].regmap_entry[hr]>=0&&regs[t].regmap_entry[hr]<TEMPREG) {
4788         #ifdef DESTRUCTIVE_WRITEBACK
4789         if(i_regmap[hr]!=regs[t].regmap_entry[hr] || ( !((regs[t].dirty>>hr)&1) && ((i_dirty>>hr)&1) && (((i_is32&~unneeded_reg_upper[t])>>i_regmap[hr])&1) ) || (((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) {
4790         #else
4791         if(i_regmap[hr]!=regs[t].regmap_entry[hr] ) {
4792         #endif
4793           if(regs[t].regmap_entry[hr]==0) {
4794             emit_zeroreg(hr);
4795           }
4796           else if(regs[t].regmap_entry[hr]!=CCREG)
4797           {
4798             emit_loadreg(regs[t].regmap_entry[hr],hr);
4799           }
4800         }
4801       }
4802     }
4803     //Load 64-bit regs
4804     for(hr=0;hr<HOST_REGS;hr++) {
4805       if(hr!=EXCLUDE_REG&&regs[t].regmap_entry[hr]>=64&&regs[t].regmap_entry[hr]<TEMPREG+64) {
4806         if(i_regmap[hr]!=regs[t].regmap_entry[hr]) {
4807           assert(regs[t].regmap_entry[hr]!=64);
4808           if((i_is32>>(regs[t].regmap_entry[hr]&63))&1) {
4809             int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64);
4810             if(lr<0) {
4811               emit_loadreg(regs[t].regmap_entry[hr],hr);
4812             }
4813             else
4814             {
4815               emit_sarimm(lr,31,hr);
4816             }
4817           }
4818           else
4819           {
4820             emit_loadreg(regs[t].regmap_entry[hr],hr);
4821           }
4822         }
4823         else if((i_is32>>(regs[t].regmap_entry[hr]&63))&1) {
4824           int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64);
4825           assert(lr>=0);
4826           emit_sarimm(lr,31,hr);
4827         }
4828       }
4829     }
4830   }
4831 }
4832
4833 int match_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4834 {
4835   if(addr>=start && addr<start+slen*4-4)
4836   {
4837     int t=(addr-start)>>2;
4838     int hr;
4839     if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) return 0;
4840     for(hr=0;hr<HOST_REGS;hr++)
4841     {
4842       if(hr!=EXCLUDE_REG)
4843       {
4844         if(i_regmap[hr]!=regs[t].regmap_entry[hr])
4845         {
4846           if(regs[t].regmap_entry[hr]>=0&&(regs[t].regmap_entry[hr]|64)<TEMPREG+64)
4847           {
4848             return 0;
4849           }
4850           else
4851           if((i_dirty>>hr)&1)
4852           {
4853             if(i_regmap[hr]<TEMPREG)
4854             {
4855               if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4856                 return 0;
4857             }
4858             else if(i_regmap[hr]>=64&&i_regmap[hr]<TEMPREG+64)
4859             {
4860               if(!((unneeded_reg_upper[t]>>(i_regmap[hr]&63))&1))
4861                 return 0;
4862             }
4863           }
4864         }
4865         else // Same register but is it 32-bit or dirty?
4866         if(i_regmap[hr]>=0)
4867         {
4868           if(!((regs[t].dirty>>hr)&1))
4869           {
4870             if((i_dirty>>hr)&1)
4871             {
4872               if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4873               {
4874                 //printf("%x: dirty no match\n",addr);
4875                 return 0;
4876               }
4877             }
4878           }
4879           if((((regs[t].was32^i_is32)&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)
4880           {
4881             //printf("%x: is32 no match\n",addr);
4882             return 0;
4883           }
4884         }
4885       }
4886     }
4887     //if(is32[t]&~unneeded_reg_upper[t]&~i_is32) return 0;
4888 #ifndef FORCE32
4889     if(requires_32bit[t]&~i_is32) return 0;
4890 #endif
4891     // Delay slots are not valid branch targets
4892     //if(t>0&&(itype[t-1]==RJUMP||itype[t-1]==UJUMP||itype[t-1]==CJUMP||itype[t-1]==SJUMP||itype[t-1]==FJUMP)) return 0;
4893     // Delay slots require additional processing, so do not match
4894     if(is_ds[t]) return 0;
4895   }
4896   else
4897   {
4898     int hr;
4899     for(hr=0;hr<HOST_REGS;hr++)
4900     {
4901       if(hr!=EXCLUDE_REG)
4902       {
4903         if(i_regmap[hr]>=0)
4904         {
4905           if(hr!=HOST_CCREG||i_regmap[hr]!=CCREG)
4906           {
4907             if((i_dirty>>hr)&1)
4908             {
4909               return 0;
4910             }
4911           }
4912         }
4913       }
4914     }
4915   }
4916   return 1;
4917 }
4918
4919 // Used when a branch jumps into the delay slot of another branch
4920 void ds_assemble_entry(int i)
4921 {
4922   int t=(ba[i]-start)>>2;
4923   if(!instr_addr[t]) instr_addr[t]=(u_int)out;
4924   assem_debug("Assemble delay slot at %x\n",ba[i]);
4925   assem_debug("<->\n");
4926   if(regs[t].regmap_entry[HOST_CCREG]==CCREG&&regs[t].regmap[HOST_CCREG]!=CCREG)
4927     wb_register(CCREG,regs[t].regmap_entry,regs[t].wasdirty,regs[t].was32);
4928   load_regs(regs[t].regmap_entry,regs[t].regmap,regs[t].was32,rs1[t],rs2[t]);
4929   address_generation(t,&regs[t],regs[t].regmap_entry);
4930   if(itype[t]==STORE||itype[t]==STORELR||(opcode[t]&0x3b)==0x39||(opcode[t]&0x3b)==0x3a)
4931     load_regs(regs[t].regmap_entry,regs[t].regmap,regs[t].was32,INVCP,INVCP);
4932   cop1_usable=0;
4933   is_delayslot=0;
4934   switch(itype[t]) {
4935     case ALU:
4936       alu_assemble(t,&regs[t]);break;
4937     case IMM16:
4938       imm16_assemble(t,&regs[t]);break;
4939     case SHIFT:
4940       shift_assemble(t,&regs[t]);break;
4941     case SHIFTIMM:
4942       shiftimm_assemble(t,&regs[t]);break;
4943     case LOAD:
4944       load_assemble(t,&regs[t]);break;
4945     case LOADLR:
4946       loadlr_assemble(t,&regs[t]);break;
4947     case STORE:
4948       store_assemble(t,&regs[t]);break;
4949     case STORELR:
4950       storelr_assemble(t,&regs[t]);break;
4951     case COP0:
4952       cop0_assemble(t,&regs[t]);break;
4953     case COP1:
4954       cop1_assemble(t,&regs[t]);break;
4955     case C1LS:
4956       c1ls_assemble(t,&regs[t]);break;
4957     case COP2:
4958       cop2_assemble(t,&regs[t]);break;
4959     case C2LS:
4960       c2ls_assemble(t,&regs[t]);break;
4961     case C2OP:
4962       c2op_assemble(t,&regs[t]);break;
4963     case FCONV:
4964       fconv_assemble(t,&regs[t]);break;
4965     case FLOAT:
4966       float_assemble(t,&regs[t]);break;
4967     case FCOMP:
4968       fcomp_assemble(t,&regs[t]);break;
4969     case MULTDIV:
4970       multdiv_assemble(t,&regs[t]);break;
4971     case MOV:
4972       mov_assemble(t,&regs[t]);break;
4973     case SYSCALL:
4974     case HLECALL:
4975     case INTCALL:
4976     case SPAN:
4977     case UJUMP:
4978     case RJUMP:
4979     case CJUMP:
4980     case SJUMP:
4981     case FJUMP:
4982       SysPrintf("Jump in the delay slot.  This is probably a bug.\n");
4983   }
4984   store_regs_bt(regs[t].regmap,regs[t].is32,regs[t].dirty,ba[i]+4);
4985   load_regs_bt(regs[t].regmap,regs[t].is32,regs[t].dirty,ba[i]+4);
4986   if(internal_branch(regs[t].is32,ba[i]+4))
4987     assem_debug("branch: internal\n");
4988   else
4989     assem_debug("branch: external\n");
4990   assert(internal_branch(regs[t].is32,ba[i]+4));
4991   add_to_linker((int)out,ba[i]+4,internal_branch(regs[t].is32,ba[i]+4));
4992   emit_jmp(0);
4993 }
4994
4995 void do_cc(int i,signed char i_regmap[],int *adj,int addr,int taken,int invert)
4996 {
4997   int count;
4998   int jaddr;
4999   int idle=0;
5000   int t=0;
5001   if(itype[i]==RJUMP)
5002   {
5003     *adj=0;
5004   }
5005   //if(ba[i]>=start && ba[i]<(start+slen*4))
5006   if(internal_branch(branch_regs[i].is32,ba[i]))
5007   {
5008     t=(ba[i]-start)>>2;
5009     if(is_ds[t]) *adj=-1; // Branch into delay slot adds an extra cycle
5010     else *adj=ccadj[t];
5011   }
5012   else
5013   {
5014     *adj=0;
5015   }
5016   count=ccadj[i];
5017   if(taken==TAKEN && i==(ba[i]-start)>>2 && source[i+1]==0) {
5018     // Idle loop
5019     if(count&1) emit_addimm_and_set_flags(2*(count+2),HOST_CCREG);
5020     idle=(int)out;
5021     //emit_subfrommem(&idlecount,HOST_CCREG); // Count idle cycles
5022     emit_andimm(HOST_CCREG,3,HOST_CCREG);
5023     jaddr=(int)out;
5024     emit_jmp(0);
5025   }
5026   else if(*adj==0||invert) {
5027     int cycles=CLOCK_ADJUST(count+2);
5028     // faster loop HACK
5029     if (t&&*adj) {
5030       int rel=t-i;
5031       if(-NO_CYCLE_PENALTY_THR<rel&&rel<0)
5032         cycles=CLOCK_ADJUST(*adj)+count+2-*adj;
5033     }
5034     emit_addimm_and_set_flags(cycles,HOST_CCREG);
5035     jaddr=(int)out;
5036     emit_jns(0);
5037   }
5038   else
5039   {
5040     emit_cmpimm(HOST_CCREG,-CLOCK_ADJUST(count+2));
5041     jaddr=(int)out;
5042     emit_jns(0);
5043   }
5044   add_stub(CC_STUB,jaddr,idle?idle:(int)out,(*adj==0||invert||idle)?0:(count+2),i,addr,taken,0);
5045 }
5046
5047 void do_ccstub(int n)
5048 {
5049   literal_pool(256);
5050   assem_debug("do_ccstub %x\n",start+stubs[n][4]*4);
5051   set_jump_target(stubs[n][1],(int)out);
5052   int i=stubs[n][4];
5053   if(stubs[n][6]==NULLDS) {
5054     // Delay slot instruction is nullified ("likely" branch)
5055     wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty);
5056   }
5057   else if(stubs[n][6]!=TAKEN) {
5058     wb_dirtys(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty);
5059   }
5060   else {
5061     if(internal_branch(branch_regs[i].is32,ba[i]))
5062       wb_needed_dirtys(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5063   }
5064   if(stubs[n][5]!=-1)
5065   {
5066     // Save PC as return address
5067     emit_movimm(stubs[n][5],EAX);
5068     emit_writeword(EAX,(int)&pcaddr);
5069   }
5070   else
5071   {
5072     // Return address depends on which way the branch goes
5073     if(itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
5074     {
5075       int s1l=get_reg(branch_regs[i].regmap,rs1[i]);
5076       int s1h=get_reg(branch_regs[i].regmap,rs1[i]|64);
5077       int s2l=get_reg(branch_regs[i].regmap,rs2[i]);
5078       int s2h=get_reg(branch_regs[i].regmap,rs2[i]|64);
5079       if(rs1[i]==0)
5080       {
5081         s1l=s2l;s1h=s2h;
5082         s2l=s2h=-1;
5083       }
5084       else if(rs2[i]==0)
5085       {
5086         s2l=s2h=-1;
5087       }
5088       if((branch_regs[i].is32>>rs1[i])&(branch_regs[i].is32>>rs2[i])&1) {
5089         s1h=s2h=-1;
5090       }
5091       assert(s1l>=0);
5092       #ifdef DESTRUCTIVE_WRITEBACK
5093       if(rs1[i]) {
5094         if((branch_regs[i].dirty>>s1l)&(branch_regs[i].is32>>rs1[i])&1)
5095           emit_loadreg(rs1[i],s1l);
5096       }
5097       else {
5098         if((branch_regs[i].dirty>>s1l)&(branch_regs[i].is32>>rs2[i])&1)
5099           emit_loadreg(rs2[i],s1l);
5100       }
5101       if(s2l>=0)
5102         if((branch_regs[i].dirty>>s2l)&(branch_regs[i].is32>>rs2[i])&1)
5103           emit_loadreg(rs2[i],s2l);
5104       #endif
5105       int hr=0;
5106       int addr=-1,alt=-1,ntaddr=-1;
5107       while(hr<HOST_REGS)
5108       {
5109         if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
5110            (branch_regs[i].regmap[hr]&63)!=rs1[i] &&
5111            (branch_regs[i].regmap[hr]&63)!=rs2[i] )
5112         {
5113           addr=hr++;break;
5114         }
5115         hr++;
5116       }
5117       while(hr<HOST_REGS)
5118       {
5119         if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
5120            (branch_regs[i].regmap[hr]&63)!=rs1[i] &&
5121            (branch_regs[i].regmap[hr]&63)!=rs2[i] )
5122         {
5123           alt=hr++;break;
5124         }
5125         hr++;
5126       }
5127       if((opcode[i]&0x2E)==6) // BLEZ/BGTZ needs another register
5128       {
5129         while(hr<HOST_REGS)
5130         {
5131           if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
5132              (branch_regs[i].regmap[hr]&63)!=rs1[i] &&
5133              (branch_regs[i].regmap[hr]&63)!=rs2[i] )
5134           {
5135             ntaddr=hr;break;
5136           }
5137           hr++;
5138         }
5139         assert(hr<HOST_REGS);
5140       }
5141       if((opcode[i]&0x2f)==4) // BEQ
5142       {
5143         #ifdef HAVE_CMOV_IMM
5144         if(s1h<0) {
5145           if(s2l>=0) emit_cmp(s1l,s2l);
5146           else emit_test(s1l,s1l);
5147           emit_cmov2imm_e_ne_compact(ba[i],start+i*4+8,addr);
5148         }
5149         else
5150         #endif
5151         {
5152           emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
5153           if(s1h>=0) {
5154             if(s2h>=0) emit_cmp(s1h,s2h);
5155             else emit_test(s1h,s1h);
5156             emit_cmovne_reg(alt,addr);
5157           }
5158           if(s2l>=0) emit_cmp(s1l,s2l);
5159           else emit_test(s1l,s1l);
5160           emit_cmovne_reg(alt,addr);
5161         }
5162       }
5163       if((opcode[i]&0x2f)==5) // BNE
5164       {
5165         #ifdef HAVE_CMOV_IMM
5166         if(s1h<0) {
5167           if(s2l>=0) emit_cmp(s1l,s2l);
5168           else emit_test(s1l,s1l);
5169           emit_cmov2imm_e_ne_compact(start+i*4+8,ba[i],addr);
5170         }
5171         else
5172         #endif
5173         {
5174           emit_mov2imm_compact(start+i*4+8,addr,ba[i],alt);
5175           if(s1h>=0) {
5176             if(s2h>=0) emit_cmp(s1h,s2h);
5177             else emit_test(s1h,s1h);
5178             emit_cmovne_reg(alt,addr);
5179           }
5180           if(s2l>=0) emit_cmp(s1l,s2l);
5181           else emit_test(s1l,s1l);
5182           emit_cmovne_reg(alt,addr);
5183         }
5184       }
5185       if((opcode[i]&0x2f)==6) // BLEZ
5186       {
5187         //emit_movimm(ba[i],alt);
5188         //emit_movimm(start+i*4+8,addr);
5189         emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
5190         emit_cmpimm(s1l,1);
5191         if(s1h>=0) emit_mov(addr,ntaddr);
5192         emit_cmovl_reg(alt,addr);
5193         if(s1h>=0) {
5194           emit_test(s1h,s1h);
5195           emit_cmovne_reg(ntaddr,addr);
5196           emit_cmovs_reg(alt,addr);
5197         }
5198       }
5199       if((opcode[i]&0x2f)==7) // BGTZ
5200       {
5201         //emit_movimm(ba[i],addr);
5202         //emit_movimm(start+i*4+8,ntaddr);
5203         emit_mov2imm_compact(ba[i],addr,start+i*4+8,ntaddr);
5204         emit_cmpimm(s1l,1);
5205         if(s1h>=0) emit_mov(addr,alt);
5206         emit_cmovl_reg(ntaddr,addr);
5207         if(s1h>=0) {
5208           emit_test(s1h,s1h);
5209           emit_cmovne_reg(alt,addr);
5210           emit_cmovs_reg(ntaddr,addr);
5211         }
5212       }
5213       if((opcode[i]==1)&&(opcode2[i]&0x2D)==0) // BLTZ
5214       {
5215         //emit_movimm(ba[i],alt);
5216         //emit_movimm(start+i*4+8,addr);
5217         emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
5218         if(s1h>=0) emit_test(s1h,s1h);
5219         else emit_test(s1l,s1l);
5220         emit_cmovs_reg(alt,addr);
5221       }
5222       if((opcode[i]==1)&&(opcode2[i]&0x2D)==1) // BGEZ
5223       {
5224         //emit_movimm(ba[i],addr);
5225         //emit_movimm(start+i*4+8,alt);
5226         emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
5227         if(s1h>=0) emit_test(s1h,s1h);
5228         else emit_test(s1l,s1l);
5229         emit_cmovs_reg(alt,addr);
5230       }
5231       if(opcode[i]==0x11 && opcode2[i]==0x08 ) {
5232         if(source[i]&0x10000) // BC1T
5233         {
5234           //emit_movimm(ba[i],alt);
5235           //emit_movimm(start+i*4+8,addr);
5236           emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
5237           emit_testimm(s1l,0x800000);
5238           emit_cmovne_reg(alt,addr);
5239         }
5240         else // BC1F
5241         {
5242           //emit_movimm(ba[i],addr);
5243           //emit_movimm(start+i*4+8,alt);
5244           emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
5245           emit_testimm(s1l,0x800000);
5246           emit_cmovne_reg(alt,addr);
5247         }
5248       }
5249       emit_writeword(addr,(int)&pcaddr);
5250     }
5251     else
5252     if(itype[i]==RJUMP)
5253     {
5254       int r=get_reg(branch_regs[i].regmap,rs1[i]);
5255       if(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]) {
5256         r=get_reg(branch_regs[i].regmap,RTEMP);
5257       }
5258       emit_writeword(r,(int)&pcaddr);
5259     }
5260     else {SysPrintf("Unknown branch type in do_ccstub\n");exit(1);}
5261   }
5262   // Update cycle count
5263   assert(branch_regs[i].regmap[HOST_CCREG]==CCREG||branch_regs[i].regmap[HOST_CCREG]==-1);
5264   if(stubs[n][3]) emit_addimm(HOST_CCREG,CLOCK_ADJUST((int)stubs[n][3]),HOST_CCREG);
5265   emit_call((int)cc_interrupt);
5266   if(stubs[n][3]) emit_addimm(HOST_CCREG,-CLOCK_ADJUST((int)stubs[n][3]),HOST_CCREG);
5267   if(stubs[n][6]==TAKEN) {
5268     if(internal_branch(branch_regs[i].is32,ba[i]))
5269       load_needed_regs(branch_regs[i].regmap,regs[(ba[i]-start)>>2].regmap_entry);
5270     else if(itype[i]==RJUMP) {
5271       if(get_reg(branch_regs[i].regmap,RTEMP)>=0)
5272         emit_readword((int)&pcaddr,get_reg(branch_regs[i].regmap,RTEMP));
5273       else
5274         emit_loadreg(rs1[i],get_reg(branch_regs[i].regmap,rs1[i]));
5275     }
5276   }else if(stubs[n][6]==NOTTAKEN) {
5277     if(i<slen-2) load_needed_regs(branch_regs[i].regmap,regmap_pre[i+2]);
5278     else load_all_regs(branch_regs[i].regmap);
5279   }else if(stubs[n][6]==NULLDS) {
5280     // Delay slot instruction is nullified ("likely" branch)
5281     if(i<slen-2) load_needed_regs(regs[i].regmap,regmap_pre[i+2]);
5282     else load_all_regs(regs[i].regmap);
5283   }else{
5284     load_all_regs(branch_regs[i].regmap);
5285   }
5286   emit_jmp(stubs[n][2]); // return address
5287
5288   /* This works but uses a lot of memory...
5289   emit_readword((int)&last_count,ECX);
5290   emit_add(HOST_CCREG,ECX,EAX);
5291   emit_writeword(EAX,(int)&Count);
5292   emit_call((int)gen_interupt);
5293   emit_readword((int)&Count,HOST_CCREG);
5294   emit_readword((int)&next_interupt,EAX);
5295   emit_readword((int)&pending_exception,EBX);
5296   emit_writeword(EAX,(int)&last_count);
5297   emit_sub(HOST_CCREG,EAX,HOST_CCREG);
5298   emit_test(EBX,EBX);
5299   int jne_instr=(int)out;
5300   emit_jne(0);
5301   if(stubs[n][3]) emit_addimm(HOST_CCREG,-2*stubs[n][3],HOST_CCREG);
5302   load_all_regs(branch_regs[i].regmap);
5303   emit_jmp(stubs[n][2]); // return address
5304   set_jump_target(jne_instr,(int)out);
5305   emit_readword((int)&pcaddr,EAX);
5306   // Call get_addr_ht instead of doing the hash table here.
5307   // This code is executed infrequently and takes up a lot of space
5308   // so smaller is better.
5309   emit_storereg(CCREG,HOST_CCREG);
5310   emit_pushreg(EAX);
5311   emit_call((int)get_addr_ht);
5312   emit_loadreg(CCREG,HOST_CCREG);
5313   emit_addimm(ESP,4,ESP);
5314   emit_jmpreg(EAX);*/
5315 }
5316
5317 add_to_linker(int addr,int target,int ext)
5318 {
5319   link_addr[linkcount][0]=addr;
5320   link_addr[linkcount][1]=target;
5321   link_addr[linkcount][2]=ext;
5322   linkcount++;
5323 }
5324
5325 static void ujump_assemble_write_ra(int i)
5326 {
5327   int rt;
5328   unsigned int return_address;
5329   rt=get_reg(branch_regs[i].regmap,31);
5330   assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5331   //assert(rt>=0);
5332   return_address=start+i*4+8;
5333   if(rt>=0) {
5334     #ifdef USE_MINI_HT
5335     if(internal_branch(branch_regs[i].is32,return_address)&&rt1[i+1]!=31) {
5336       int temp=-1; // note: must be ds-safe
5337       #ifdef HOST_TEMPREG
5338       temp=HOST_TEMPREG;
5339       #endif
5340       if(temp>=0) do_miniht_insert(return_address,rt,temp);
5341       else emit_movimm(return_address,rt);
5342     }
5343     else
5344     #endif
5345     {
5346       #ifdef REG_PREFETCH
5347       if(temp>=0)
5348       {
5349         if(i_regmap[temp]!=PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5350       }
5351       #endif
5352       emit_movimm(return_address,rt); // PC into link register
5353       #ifdef IMM_PREFETCH
5354       emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
5355       #endif
5356     }
5357   }
5358 }
5359
5360 void ujump_assemble(int i,struct regstat *i_regs)
5361 {
5362   signed char *i_regmap=i_regs->regmap;
5363   int ra_done=0;
5364   if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
5365   address_generation(i+1,i_regs,regs[i].regmap_entry);
5366   #ifdef REG_PREFETCH
5367   int temp=get_reg(branch_regs[i].regmap,PTEMP);
5368   if(rt1[i]==31&&temp>=0)
5369   {
5370     int return_address=start+i*4+8;
5371     if(get_reg(branch_regs[i].regmap,31)>0)
5372     if(i_regmap[temp]==PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5373   }
5374   #endif
5375   if(rt1[i]==31&&(rt1[i]==rs1[i+1]||rt1[i]==rs2[i+1])) {
5376     ujump_assemble_write_ra(i); // writeback ra for DS
5377     ra_done=1;
5378   }
5379   ds_assemble(i+1,i_regs);
5380   uint64_t bc_unneeded=branch_regs[i].u;
5381   uint64_t bc_unneeded_upper=branch_regs[i].uu;
5382   bc_unneeded|=1|(1LL<<rt1[i]);
5383   bc_unneeded_upper|=1|(1LL<<rt1[i]);
5384   wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5385                 bc_unneeded,bc_unneeded_upper);
5386   load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5387   if(!ra_done&&rt1[i]==31)
5388     ujump_assemble_write_ra(i);
5389   int cc,adj;
5390   cc=get_reg(branch_regs[i].regmap,CCREG);
5391   assert(cc==HOST_CCREG);
5392   store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5393   #ifdef REG_PREFETCH
5394   if(rt1[i]==31&&temp>=0) emit_prefetchreg(temp);
5395   #endif
5396   do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5397   if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
5398   load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5399   if(internal_branch(branch_regs[i].is32,ba[i]))
5400     assem_debug("branch: internal\n");
5401   else
5402     assem_debug("branch: external\n");
5403   if(internal_branch(branch_regs[i].is32,ba[i])&&is_ds[(ba[i]-start)>>2]) {
5404     ds_assemble_entry(i);
5405   }
5406   else {
5407     add_to_linker((int)out,ba[i],internal_branch(branch_regs[i].is32,ba[i]));
5408     emit_jmp(0);
5409   }
5410 }
5411
5412 static void rjump_assemble_write_ra(int i)
5413 {
5414   int rt,return_address;
5415   assert(rt1[i+1]!=rt1[i]);
5416   assert(rt2[i+1]!=rt1[i]);
5417   rt=get_reg(branch_regs[i].regmap,rt1[i]);
5418   assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5419   assert(rt>=0);
5420   return_address=start+i*4+8;
5421   #ifdef REG_PREFETCH
5422   if(temp>=0)
5423   {
5424     if(i_regmap[temp]!=PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5425   }
5426   #endif
5427   emit_movimm(return_address,rt); // PC into link register
5428   #ifdef IMM_PREFETCH
5429   emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
5430   #endif
5431 }
5432
5433 void rjump_assemble(int i,struct regstat *i_regs)
5434 {
5435   signed char *i_regmap=i_regs->regmap;
5436   int temp;
5437   int rs,cc,adj;
5438   int ra_done=0;
5439   rs=get_reg(branch_regs[i].regmap,rs1[i]);
5440   assert(rs>=0);
5441   if(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]) {
5442     // Delay slot abuse, make a copy of the branch address register
5443     temp=get_reg(branch_regs[i].regmap,RTEMP);
5444     assert(temp>=0);
5445     assert(regs[i].regmap[temp]==RTEMP);
5446     emit_mov(rs,temp);
5447     rs=temp;
5448   }
5449   address_generation(i+1,i_regs,regs[i].regmap_entry);
5450   #ifdef REG_PREFETCH
5451   if(rt1[i]==31)
5452   {
5453     if((temp=get_reg(branch_regs[i].regmap,PTEMP))>=0) {
5454       int return_address=start+i*4+8;
5455       if(i_regmap[temp]==PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5456     }
5457   }
5458   #endif
5459   #ifdef USE_MINI_HT
5460   if(rs1[i]==31) {
5461     int rh=get_reg(regs[i].regmap,RHASH);
5462     if(rh>=0) do_preload_rhash(rh);
5463   }
5464   #endif
5465   if(rt1[i]!=0&&(rt1[i]==rs1[i+1]||rt1[i]==rs2[i+1])) {
5466     rjump_assemble_write_ra(i);
5467     ra_done=1;
5468   }
5469   ds_assemble(i+1,i_regs);
5470   uint64_t bc_unneeded=branch_regs[i].u;
5471   uint64_t bc_unneeded_upper=branch_regs[i].uu;
5472   bc_unneeded|=1|(1LL<<rt1[i]);
5473   bc_unneeded_upper|=1|(1LL<<rt1[i]);
5474   bc_unneeded&=~(1LL<<rs1[i]);
5475   wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5476                 bc_unneeded,bc_unneeded_upper);
5477   load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],CCREG);
5478   if(!ra_done&&rt1[i]!=0)
5479     rjump_assemble_write_ra(i);
5480   cc=get_reg(branch_regs[i].regmap,CCREG);
5481   assert(cc==HOST_CCREG);
5482   #ifdef USE_MINI_HT
5483   int rh=get_reg(branch_regs[i].regmap,RHASH);
5484   int ht=get_reg(branch_regs[i].regmap,RHTBL);
5485   if(rs1[i]==31) {
5486     if(regs[i].regmap[rh]!=RHASH) do_preload_rhash(rh);
5487     do_preload_rhtbl(ht);
5488     do_rhash(rs,rh);
5489   }
5490   #endif
5491   store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,-1);
5492   #ifdef DESTRUCTIVE_WRITEBACK
5493   if((branch_regs[i].dirty>>rs)&(branch_regs[i].is32>>rs1[i])&1) {
5494     if(rs1[i]!=rt1[i+1]&&rs1[i]!=rt2[i+1]) {
5495       emit_loadreg(rs1[i],rs);
5496     }
5497   }
5498   #endif
5499   #ifdef REG_PREFETCH
5500   if(rt1[i]==31&&temp>=0) emit_prefetchreg(temp);
5501   #endif
5502   #ifdef USE_MINI_HT
5503   if(rs1[i]==31) {
5504     do_miniht_load(ht,rh);
5505   }
5506   #endif
5507   //do_cc(i,branch_regs[i].regmap,&adj,-1,TAKEN);
5508   //if(adj) emit_addimm(cc,2*(ccadj[i]+2-adj),cc); // ??? - Shouldn't happen
5509   //assert(adj==0);
5510   emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),HOST_CCREG);
5511   add_stub(CC_STUB,(int)out,jump_vaddr_reg[rs],0,i,-1,TAKEN,0);
5512 #ifdef PCSX
5513   if(itype[i+1]==COP0&&(source[i+1]&0x3f)==0x10)
5514     // special case for RFE
5515     emit_jmp(0);
5516   else
5517 #endif
5518   emit_jns(0);
5519   //load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,-1);
5520   #ifdef USE_MINI_HT
5521   if(rs1[i]==31) {
5522     do_miniht_jump(rs,rh,ht);
5523   }
5524   else
5525   #endif
5526   {
5527     //if(rs!=EAX) emit_mov(rs,EAX);
5528     //emit_jmp((int)jump_vaddr_eax);
5529     emit_jmp(jump_vaddr_reg[rs]);
5530   }
5531   /* Check hash table
5532   temp=!rs;
5533   emit_mov(rs,temp);
5534   emit_shrimm(rs,16,rs);
5535   emit_xor(temp,rs,rs);
5536   emit_movzwl_reg(rs,rs);
5537   emit_shlimm(rs,4,rs);
5538   emit_cmpmem_indexed((int)hash_table,rs,temp);
5539   emit_jne((int)out+14);
5540   emit_readword_indexed((int)hash_table+4,rs,rs);
5541   emit_jmpreg(rs);
5542   emit_cmpmem_indexed((int)hash_table+8,rs,temp);
5543   emit_addimm_no_flags(8,rs);
5544   emit_jeq((int)out-17);
5545   // No hit on hash table, call compiler
5546   emit_pushreg(temp);
5547 //DEBUG >
5548 #ifdef DEBUG_CYCLE_COUNT
5549   emit_readword((int)&last_count,ECX);
5550   emit_add(HOST_CCREG,ECX,HOST_CCREG);
5551   emit_readword((int)&next_interupt,ECX);
5552   emit_writeword(HOST_CCREG,(int)&Count);
5553   emit_sub(HOST_CCREG,ECX,HOST_CCREG);
5554   emit_writeword(ECX,(int)&last_count);
5555 #endif
5556 //DEBUG <
5557   emit_storereg(CCREG,HOST_CCREG);
5558   emit_call((int)get_addr);
5559   emit_loadreg(CCREG,HOST_CCREG);
5560   emit_addimm(ESP,4,ESP);
5561   emit_jmpreg(EAX);*/
5562   #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5563   if(rt1[i]!=31&&i<slen-2&&(((u_int)out)&7)) emit_mov(13,13);
5564   #endif
5565 }
5566
5567 void cjump_assemble(int i,struct regstat *i_regs)
5568 {
5569   signed char *i_regmap=i_regs->regmap;
5570   int cc;
5571   int match;
5572   match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5573   assem_debug("match=%d\n",match);
5574   int s1h,s1l,s2h,s2l;
5575   int prev_cop1_usable=cop1_usable;
5576   int unconditional=0,nop=0;
5577   int only32=0;
5578   int invert=0;
5579   int internal=internal_branch(branch_regs[i].is32,ba[i]);
5580   if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
5581   if(!match) invert=1;
5582   #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5583   if(i>(ba[i]-start)>>2) invert=1;
5584   #endif
5585
5586   if(ooo[i]) {
5587     s1l=get_reg(branch_regs[i].regmap,rs1[i]);
5588     s1h=get_reg(branch_regs[i].regmap,rs1[i]|64);
5589     s2l=get_reg(branch_regs[i].regmap,rs2[i]);
5590     s2h=get_reg(branch_regs[i].regmap,rs2[i]|64);
5591   }
5592   else {
5593     s1l=get_reg(i_regmap,rs1[i]);
5594     s1h=get_reg(i_regmap,rs1[i]|64);
5595     s2l=get_reg(i_regmap,rs2[i]);
5596     s2h=get_reg(i_regmap,rs2[i]|64);
5597   }
5598   if(rs1[i]==0&&rs2[i]==0)
5599   {
5600     if(opcode[i]&1) nop=1;
5601     else unconditional=1;
5602     //assert(opcode[i]!=5);
5603     //assert(opcode[i]!=7);
5604     //assert(opcode[i]!=0x15);
5605     //assert(opcode[i]!=0x17);
5606   }
5607   else if(rs1[i]==0)
5608   {
5609     s1l=s2l;s1h=s2h;
5610     s2l=s2h=-1;
5611     only32=(regs[i].was32>>rs2[i])&1;
5612   }
5613   else if(rs2[i]==0)
5614   {
5615     s2l=s2h=-1;
5616     only32=(regs[i].was32>>rs1[i])&1;
5617   }
5618   else {
5619     only32=(regs[i].was32>>rs1[i])&(regs[i].was32>>rs2[i])&1;
5620   }
5621
5622   if(ooo[i]) {
5623     // Out of order execution (delay slot first)
5624     //printf("OOOE\n");
5625     address_generation(i+1,i_regs,regs[i].regmap_entry);
5626     ds_assemble(i+1,i_regs);
5627     int adj;
5628     uint64_t bc_unneeded=branch_regs[i].u;
5629     uint64_t bc_unneeded_upper=branch_regs[i].uu;
5630     bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
5631     bc_unneeded_upper&=~((1LL<<us1[i])|(1LL<<us2[i]));
5632     bc_unneeded|=1;
5633     bc_unneeded_upper|=1;
5634     wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5635                   bc_unneeded,bc_unneeded_upper);
5636     load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],rs2[i]);
5637     load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5638     cc=get_reg(branch_regs[i].regmap,CCREG);
5639     assert(cc==HOST_CCREG);
5640     if(unconditional)
5641       store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5642     //do_cc(i,branch_regs[i].regmap,&adj,unconditional?ba[i]:-1,unconditional);
5643     //assem_debug("cycle count (adj)\n");
5644     if(unconditional) {
5645       do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5646       if(i!=(ba[i]-start)>>2 || source[i+1]!=0) {
5647         if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
5648         load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5649         if(internal)
5650           assem_debug("branch: internal\n");
5651         else
5652           assem_debug("branch: external\n");
5653         if(internal&&is_ds[(ba[i]-start)>>2]) {
5654           ds_assemble_entry(i);
5655         }
5656         else {
5657           add_to_linker((int)out,ba[i],internal);
5658           emit_jmp(0);
5659         }
5660         #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5661         if(((u_int)out)&7) emit_addnop(0);
5662         #endif
5663       }
5664     }
5665     else if(nop) {
5666       emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),cc);
5667       int jaddr=(int)out;
5668       emit_jns(0);
5669       add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
5670     }
5671     else {
5672       int taken=0,nottaken=0,nottaken1=0;
5673       do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
5674       if(adj&&!invert) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
5675       if(!only32)
5676       {
5677         assert(s1h>=0);
5678         if(opcode[i]==4) // BEQ
5679         {
5680           if(s2h>=0) emit_cmp(s1h,s2h);
5681           else emit_test(s1h,s1h);
5682           nottaken1=(int)out;
5683           emit_jne(1);
5684         }
5685         if(opcode[i]==5) // BNE
5686         {
5687           if(s2h>=0) emit_cmp(s1h,s2h);
5688           else emit_test(s1h,s1h);
5689           if(invert) taken=(int)out;
5690           else add_to_linker((int)out,ba[i],internal);
5691           emit_jne(0);
5692         }
5693         if(opcode[i]==6) // BLEZ
5694         {
5695           emit_test(s1h,s1h);
5696           if(invert) taken=(int)out;
5697           else add_to_linker((int)out,ba[i],internal);
5698           emit_js(0);
5699           nottaken1=(int)out;
5700           emit_jne(1);
5701         }
5702         if(opcode[i]==7) // BGTZ
5703         {
5704           emit_test(s1h,s1h);
5705           nottaken1=(int)out;
5706           emit_js(1);
5707           if(invert) taken=(int)out;
5708           else add_to_linker((int)out,ba[i],internal);
5709           emit_jne(0);
5710         }
5711       } // if(!only32)
5712
5713       //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5714       assert(s1l>=0);
5715       if(opcode[i]==4) // BEQ
5716       {
5717         if(s2l>=0) emit_cmp(s1l,s2l);
5718         else emit_test(s1l,s1l);
5719         if(invert){
5720           nottaken=(int)out;
5721           emit_jne(1);
5722         }else{
5723           add_to_linker((int)out,ba[i],internal);
5724           emit_jeq(0);
5725         }
5726       }
5727       if(opcode[i]==5) // BNE
5728       {
5729         if(s2l>=0) emit_cmp(s1l,s2l);
5730         else emit_test(s1l,s1l);
5731         if(invert){
5732           nottaken=(int)out;
5733           emit_jeq(1);
5734         }else{
5735           add_to_linker((int)out,ba[i],internal);
5736           emit_jne(0);
5737         }
5738       }
5739       if(opcode[i]==6) // BLEZ
5740       {
5741         emit_cmpimm(s1l,1);
5742         if(invert){
5743           nottaken=(int)out;
5744           emit_jge(1);
5745         }else{
5746           add_to_linker((int)out,ba[i],internal);
5747           emit_jl(0);
5748         }
5749       }
5750       if(opcode[i]==7) // BGTZ
5751       {
5752         emit_cmpimm(s1l,1);
5753         if(invert){
5754           nottaken=(int)out;
5755           emit_jl(1);
5756         }else{
5757           add_to_linker((int)out,ba[i],internal);
5758           emit_jge(0);
5759         }
5760       }
5761       if(invert) {
5762         if(taken) set_jump_target(taken,(int)out);
5763         #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5764         if(match&&(!internal||!is_ds[(ba[i]-start)>>2])) {
5765           if(adj) {
5766             emit_addimm(cc,-CLOCK_ADJUST(adj),cc);
5767             add_to_linker((int)out,ba[i],internal);
5768           }else{
5769             emit_addnop(13);
5770             add_to_linker((int)out,ba[i],internal*2);
5771           }
5772           emit_jmp(0);
5773         }else
5774         #endif
5775         {
5776           if(adj) emit_addimm(cc,-CLOCK_ADJUST(adj),cc);
5777           store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5778           load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5779           if(internal)
5780             assem_debug("branch: internal\n");
5781           else
5782             assem_debug("branch: external\n");
5783           if(internal&&is_ds[(ba[i]-start)>>2]) {
5784             ds_assemble_entry(i);
5785           }
5786           else {
5787             add_to_linker((int)out,ba[i],internal);
5788             emit_jmp(0);
5789           }
5790         }
5791         set_jump_target(nottaken,(int)out);
5792       }
5793
5794       if(nottaken1) set_jump_target(nottaken1,(int)out);
5795       if(adj) {
5796         if(!invert) emit_addimm(cc,CLOCK_ADJUST(adj),cc);
5797       }
5798     } // (!unconditional)
5799   } // if(ooo)
5800   else
5801   {
5802     // In-order execution (branch first)
5803     //if(likely[i]) printf("IOL\n");
5804     //else
5805     //printf("IOE\n");
5806     int taken=0,nottaken=0,nottaken1=0;
5807     if(!unconditional&&!nop) {
5808       if(!only32)
5809       {
5810         assert(s1h>=0);
5811         if((opcode[i]&0x2f)==4) // BEQ
5812         {
5813           if(s2h>=0) emit_cmp(s1h,s2h);
5814           else emit_test(s1h,s1h);
5815           nottaken1=(int)out;
5816           emit_jne(2);
5817         }
5818         if((opcode[i]&0x2f)==5) // BNE
5819         {
5820           if(s2h>=0) emit_cmp(s1h,s2h);
5821           else emit_test(s1h,s1h);
5822           taken=(int)out;
5823           emit_jne(1);
5824         }
5825         if((opcode[i]&0x2f)==6) // BLEZ
5826         {
5827           emit_test(s1h,s1h);
5828           taken=(int)out;
5829           emit_js(1);
5830           nottaken1=(int)out;
5831           emit_jne(2);
5832         }
5833         if((opcode[i]&0x2f)==7) // BGTZ
5834         {
5835           emit_test(s1h,s1h);
5836           nottaken1=(int)out;
5837           emit_js(2);
5838           taken=(int)out;
5839           emit_jne(1);
5840         }
5841       } // if(!only32)
5842
5843       //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5844       assert(s1l>=0);
5845       if((opcode[i]&0x2f)==4) // BEQ
5846       {
5847         if(s2l>=0) emit_cmp(s1l,s2l);
5848         else emit_test(s1l,s1l);
5849         nottaken=(int)out;
5850         emit_jne(2);
5851       }
5852       if((opcode[i]&0x2f)==5) // BNE
5853       {
5854         if(s2l>=0) emit_cmp(s1l,s2l);
5855         else emit_test(s1l,s1l);
5856         nottaken=(int)out;
5857         emit_jeq(2);
5858       }
5859       if((opcode[i]&0x2f)==6) // BLEZ
5860       {
5861         emit_cmpimm(s1l,1);
5862         nottaken=(int)out;
5863         emit_jge(2);
5864       }
5865       if((opcode[i]&0x2f)==7) // BGTZ
5866       {
5867         emit_cmpimm(s1l,1);
5868         nottaken=(int)out;
5869         emit_jl(2);
5870       }
5871     } // if(!unconditional)
5872     int adj;
5873     uint64_t ds_unneeded=branch_regs[i].u;
5874     uint64_t ds_unneeded_upper=branch_regs[i].uu;
5875     ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
5876     ds_unneeded_upper&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
5877     if((~ds_unneeded_upper>>rt1[i+1])&1) ds_unneeded_upper&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
5878     ds_unneeded|=1;
5879     ds_unneeded_upper|=1;
5880     // branch taken
5881     if(!nop) {
5882       if(taken) set_jump_target(taken,(int)out);
5883       assem_debug("1:\n");
5884       wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5885                     ds_unneeded,ds_unneeded_upper);
5886       // load regs
5887       load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
5888       address_generation(i+1,&branch_regs[i],0);
5889       load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,INVCP);
5890       ds_assemble(i+1,&branch_regs[i]);
5891       cc=get_reg(branch_regs[i].regmap,CCREG);
5892       if(cc==-1) {
5893         emit_loadreg(CCREG,cc=HOST_CCREG);
5894         // CHECK: Is the following instruction (fall thru) allocated ok?
5895       }
5896       assert(cc==HOST_CCREG);
5897       store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5898       do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
5899       assem_debug("cycle count (adj)\n");
5900       if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
5901       load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5902       if(internal)
5903         assem_debug("branch: internal\n");
5904       else
5905         assem_debug("branch: external\n");
5906       if(internal&&is_ds[(ba[i]-start)>>2]) {
5907         ds_assemble_entry(i);
5908       }
5909       else {
5910         add_to_linker((int)out,ba[i],internal);
5911         emit_jmp(0);
5912       }
5913     }
5914     // branch not taken
5915     cop1_usable=prev_cop1_usable;
5916     if(!unconditional) {
5917       if(nottaken1) set_jump_target(nottaken1,(int)out);
5918       set_jump_target(nottaken,(int)out);
5919       assem_debug("2:\n");
5920       if(!likely[i]) {
5921         wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5922                       ds_unneeded,ds_unneeded_upper);
5923         load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
5924         address_generation(i+1,&branch_regs[i],0);
5925         load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5926         ds_assemble(i+1,&branch_regs[i]);
5927       }
5928       cc=get_reg(branch_regs[i].regmap,CCREG);
5929       if(cc==-1&&!likely[i]) {
5930         // Cycle count isn't in a register, temporarily load it then write it out
5931         emit_loadreg(CCREG,HOST_CCREG);
5932         emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),HOST_CCREG);
5933         int jaddr=(int)out;
5934         emit_jns(0);
5935         add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
5936         emit_storereg(CCREG,HOST_CCREG);
5937       }
5938       else{
5939         cc=get_reg(i_regmap,CCREG);
5940         assert(cc==HOST_CCREG);
5941         emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),cc);
5942         int jaddr=(int)out;
5943         emit_jns(0);
5944         add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
5945       }
5946     }
5947   }
5948 }
5949
5950 void sjump_assemble(int i,struct regstat *i_regs)
5951 {
5952   signed char *i_regmap=i_regs->regmap;
5953   int cc;
5954   int match;
5955   match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5956   assem_debug("smatch=%d\n",match);
5957   int s1h,s1l;
5958   int prev_cop1_usable=cop1_usable;
5959   int unconditional=0,nevertaken=0;
5960   int only32=0;
5961   int invert=0;
5962   int internal=internal_branch(branch_regs[i].is32,ba[i]);
5963   if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
5964   if(!match) invert=1;
5965   #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5966   if(i>(ba[i]-start)>>2) invert=1;
5967   #endif
5968
5969   //if(opcode2[i]>=0x10) return; // FIXME (BxxZAL)
5970   //assert(opcode2[i]<0x10||rs1[i]==0); // FIXME (BxxZAL)
5971
5972   if(ooo[i]) {
5973     s1l=get_reg(branch_regs[i].regmap,rs1[i]);
5974     s1h=get_reg(branch_regs[i].regmap,rs1[i]|64);
5975   }
5976   else {
5977     s1l=get_reg(i_regmap,rs1[i]);
5978     s1h=get_reg(i_regmap,rs1[i]|64);
5979   }
5980   if(rs1[i]==0)
5981   {
5982     if(opcode2[i]&1) unconditional=1;
5983     else nevertaken=1;
5984     // These are never taken (r0 is never less than zero)
5985     //assert(opcode2[i]!=0);
5986     //assert(opcode2[i]!=2);
5987     //assert(opcode2[i]!=0x10);
5988     //assert(opcode2[i]!=0x12);
5989   }
5990   else {
5991     only32=(regs[i].was32>>rs1[i])&1;
5992   }
5993
5994   if(ooo[i]) {
5995     // Out of order execution (delay slot first)
5996     //printf("OOOE\n");
5997     address_generation(i+1,i_regs,regs[i].regmap_entry);
5998     ds_assemble(i+1,i_regs);
5999     int adj;
6000     uint64_t bc_unneeded=branch_regs[i].u;
6001     uint64_t bc_unneeded_upper=branch_regs[i].uu;
6002     bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
6003     bc_unneeded_upper&=~((1LL<<us1[i])|(1LL<<us2[i]));
6004     bc_unneeded|=1;
6005     bc_unneeded_upper|=1;
6006     wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6007                   bc_unneeded,bc_unneeded_upper);
6008     load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],rs1[i]);
6009     load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
6010     if(rt1[i]==31) {
6011       int rt,return_address;
6012       rt=get_reg(branch_regs[i].regmap,31);
6013       assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
6014       if(rt>=0) {
6015         // Save the PC even if the branch is not taken
6016         return_address=start+i*4+8;
6017         emit_movimm(return_address,rt); // PC into link register
6018         #ifdef IMM_PREFETCH
6019         if(!nevertaken) emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
6020         #endif
6021       }
6022     }
6023     cc=get_reg(branch_regs[i].regmap,CCREG);
6024     assert(cc==HOST_CCREG);
6025     if(unconditional)
6026       store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6027     //do_cc(i,branch_regs[i].regmap,&adj,unconditional?ba[i]:-1,unconditional);
6028     assem_debug("cycle count (adj)\n");
6029     if(unconditional) {
6030       do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
6031       if(i!=(ba[i]-start)>>2 || source[i+1]!=0) {
6032         if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
6033         load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6034         if(internal)
6035           assem_debug("branch: internal\n");
6036         else
6037           assem_debug("branch: external\n");
6038         if(internal&&is_ds[(ba[i]-start)>>2]) {
6039           ds_assemble_entry(i);
6040         }
6041         else {
6042           add_to_linker((int)out,ba[i],internal);
6043           emit_jmp(0);
6044         }
6045         #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
6046         if(((u_int)out)&7) emit_addnop(0);
6047         #endif
6048       }
6049     }
6050     else if(nevertaken) {
6051       emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),cc);
6052       int jaddr=(int)out;
6053       emit_jns(0);
6054       add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
6055     }
6056     else {
6057       int nottaken=0;
6058       do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
6059       if(adj&&!invert) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
6060       if(!only32)
6061       {
6062         assert(s1h>=0);
6063         if((opcode2[i]&0xf)==0) // BLTZ/BLTZAL
6064         {
6065           emit_test(s1h,s1h);
6066           if(invert){
6067             nottaken=(int)out;
6068             emit_jns(1);
6069           }else{
6070             add_to_linker((int)out,ba[i],internal);
6071             emit_js(0);
6072           }
6073         }
6074         if((opcode2[i]&0xf)==1) // BGEZ/BLTZAL
6075         {
6076           emit_test(s1h,s1h);
6077           if(invert){
6078             nottaken=(int)out;
6079             emit_js(1);
6080           }else{
6081             add_to_linker((int)out,ba[i],internal);
6082             emit_jns(0);
6083           }
6084         }
6085       } // if(!only32)
6086       else
6087       {
6088         assert(s1l>=0);
6089         if((opcode2[i]&0xf)==0) // BLTZ/BLTZAL
6090         {
6091           emit_test(s1l,s1l);
6092           if(invert){
6093             nottaken=(int)out;
6094             emit_jns(1);
6095           }else{
6096             add_to_linker((int)out,ba[i],internal);
6097             emit_js(0);
6098           }
6099         }
6100         if((opcode2[i]&0xf)==1) // BGEZ/BLTZAL
6101         {
6102           emit_test(s1l,s1l);
6103           if(invert){
6104             nottaken=(int)out;
6105             emit_js(1);
6106           }else{
6107             add_to_linker((int)out,ba[i],internal);
6108             emit_jns(0);
6109           }
6110         }
6111       } // if(!only32)
6112
6113       if(invert) {
6114         #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
6115         if(match&&(!internal||!is_ds[(ba[i]-start)>>2])) {
6116           if(adj) {
6117             emit_addimm(cc,-CLOCK_ADJUST(adj),cc);
6118             add_to_linker((int)out,ba[i],internal);
6119           }else{
6120             emit_addnop(13);
6121             add_to_linker((int)out,ba[i],internal*2);
6122           }
6123           emit_jmp(0);
6124         }else
6125         #endif
6126         {
6127           if(adj) emit_addimm(cc,-CLOCK_ADJUST(adj),cc);
6128           store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6129           load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6130           if(internal)
6131             assem_debug("branch: internal\n");
6132           else
6133             assem_debug("branch: external\n");
6134           if(internal&&is_ds[(ba[i]-start)>>2]) {
6135             ds_assemble_entry(i);
6136           }
6137           else {
6138             add_to_linker((int)out,ba[i],internal);
6139             emit_jmp(0);
6140           }
6141         }
6142         set_jump_target(nottaken,(int)out);
6143       }
6144
6145       if(adj) {
6146         if(!invert) emit_addimm(cc,CLOCK_ADJUST(adj),cc);
6147       }
6148     } // (!unconditional)
6149   } // if(ooo)
6150   else
6151   {
6152     // In-order execution (branch first)
6153     //printf("IOE\n");
6154     int nottaken=0;
6155     if(rt1[i]==31) {
6156       int rt,return_address;
6157       rt=get_reg(branch_regs[i].regmap,31);
6158       if(rt>=0) {
6159         // Save the PC even if the branch is not taken
6160         return_address=start+i*4+8;
6161         emit_movimm(return_address,rt); // PC into link register
6162         #ifdef IMM_PREFETCH
6163         emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
6164         #endif
6165       }
6166     }
6167     if(!unconditional) {
6168       //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
6169       if(!only32)
6170       {
6171         assert(s1h>=0);
6172         if((opcode2[i]&0x0d)==0) // BLTZ/BLTZL/BLTZAL/BLTZALL
6173         {
6174           emit_test(s1h,s1h);
6175           nottaken=(int)out;
6176           emit_jns(1);
6177         }
6178         if((opcode2[i]&0x0d)==1) // BGEZ/BGEZL/BGEZAL/BGEZALL
6179         {
6180           emit_test(s1h,s1h);
6181           nottaken=(int)out;
6182           emit_js(1);
6183         }
6184       } // if(!only32)
6185       else
6186       {
6187         assert(s1l>=0);
6188         if((opcode2[i]&0x0d)==0) // BLTZ/BLTZL/BLTZAL/BLTZALL
6189         {
6190           emit_test(s1l,s1l);
6191           nottaken=(int)out;
6192           emit_jns(1);
6193         }
6194         if((opcode2[i]&0x0d)==1) // BGEZ/BGEZL/BGEZAL/BGEZALL
6195         {
6196           emit_test(s1l,s1l);
6197           nottaken=(int)out;
6198           emit_js(1);
6199         }
6200       }
6201     } // if(!unconditional)
6202     int adj;
6203     uint64_t ds_unneeded=branch_regs[i].u;
6204     uint64_t ds_unneeded_upper=branch_regs[i].uu;
6205     ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6206     ds_unneeded_upper&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6207     if((~ds_unneeded_upper>>rt1[i+1])&1) ds_unneeded_upper&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
6208     ds_unneeded|=1;
6209     ds_unneeded_upper|=1;
6210     // branch taken
6211     if(!nevertaken) {
6212       //assem_debug("1:\n");
6213       wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6214                     ds_unneeded,ds_unneeded_upper);
6215       // load regs
6216       load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
6217       address_generation(i+1,&branch_regs[i],0);
6218       load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,INVCP);
6219       ds_assemble(i+1,&branch_regs[i]);
6220       cc=get_reg(branch_regs[i].regmap,CCREG);
6221       if(cc==-1) {
6222         emit_loadreg(CCREG,cc=HOST_CCREG);
6223         // CHECK: Is the following instruction (fall thru) allocated ok?
6224       }
6225       assert(cc==HOST_CCREG);
6226       store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6227       do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
6228       assem_debug("cycle count (adj)\n");
6229       if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
6230       load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6231       if(internal)
6232         assem_debug("branch: internal\n");
6233       else
6234         assem_debug("branch: external\n");
6235       if(internal&&is_ds[(ba[i]-start)>>2]) {
6236         ds_assemble_entry(i);
6237       }
6238       else {
6239         add_to_linker((int)out,ba[i],internal);
6240         emit_jmp(0);
6241       }
6242     }
6243     // branch not taken
6244     cop1_usable=prev_cop1_usable;
6245     if(!unconditional) {
6246       set_jump_target(nottaken,(int)out);
6247       assem_debug("1:\n");
6248       if(!likely[i]) {
6249         wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6250                       ds_unneeded,ds_unneeded_upper);
6251         load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
6252         address_generation(i+1,&branch_regs[i],0);
6253         load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
6254         ds_assemble(i+1,&branch_regs[i]);
6255       }
6256       cc=get_reg(branch_regs[i].regmap,CCREG);
6257       if(cc==-1&&!likely[i]) {
6258         // Cycle count isn't in a register, temporarily load it then write it out
6259         emit_loadreg(CCREG,HOST_CCREG);
6260         emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),HOST_CCREG);
6261         int jaddr=(int)out;
6262         emit_jns(0);
6263         add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
6264         emit_storereg(CCREG,HOST_CCREG);
6265       }
6266       else{
6267         cc=get_reg(i_regmap,CCREG);
6268         assert(cc==HOST_CCREG);
6269         emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),cc);
6270         int jaddr=(int)out;
6271         emit_jns(0);
6272         add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
6273       }
6274     }
6275   }
6276 }
6277
6278 void fjump_assemble(int i,struct regstat *i_regs)
6279 {
6280   signed char *i_regmap=i_regs->regmap;
6281   int cc;
6282   int match;
6283   match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6284   assem_debug("fmatch=%d\n",match);
6285   int fs,cs;
6286   int eaddr;
6287   int invert=0;
6288   int internal=internal_branch(branch_regs[i].is32,ba[i]);
6289   if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
6290   if(!match) invert=1;
6291   #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
6292   if(i>(ba[i]-start)>>2) invert=1;
6293   #endif
6294
6295   if(ooo[i]) {
6296     fs=get_reg(branch_regs[i].regmap,FSREG);
6297     address_generation(i+1,i_regs,regs[i].regmap_entry); // Is this okay?
6298   }
6299   else {
6300     fs=get_reg(i_regmap,FSREG);
6301   }
6302
6303   // Check cop1 unusable
6304   if(!cop1_usable) {
6305     cs=get_reg(i_regmap,CSREG);
6306     assert(cs>=0);
6307     emit_testimm(cs,0x20000000);
6308     eaddr=(int)out;
6309     emit_jeq(0);
6310     add_stub(FP_STUB,eaddr,(int)out,i,cs,(int)i_regs,0,0);
6311     cop1_usable=1;
6312   }
6313
6314   if(ooo[i]) {
6315     // Out of order execution (delay slot first)
6316     //printf("OOOE\n");
6317     ds_assemble(i+1,i_regs);
6318     int adj;
6319     uint64_t bc_unneeded=branch_regs[i].u;
6320     uint64_t bc_unneeded_upper=branch_regs[i].uu;
6321     bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
6322     bc_unneeded_upper&=~((1LL<<us1[i])|(1LL<<us2[i]));
6323     bc_unneeded|=1;
6324     bc_unneeded_upper|=1;
6325     wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6326                   bc_unneeded,bc_unneeded_upper);
6327     load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],rs1[i]);
6328     load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
6329     cc=get_reg(branch_regs[i].regmap,CCREG);
6330     assert(cc==HOST_CCREG);
6331     do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
6332     assem_debug("cycle count (adj)\n");
6333     if(1) {
6334       int nottaken=0;
6335       if(adj&&!invert) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
6336       if(1) {
6337         assert(fs>=0);
6338         emit_testimm(fs,0x800000);
6339         if(source[i]&0x10000) // BC1T
6340         {
6341           if(invert){
6342             nottaken=(int)out;
6343             emit_jeq(1);
6344           }else{
6345             add_to_linker((int)out,ba[i],internal);
6346             emit_jne(0);
6347           }
6348         }
6349         else // BC1F
6350           if(invert){
6351             nottaken=(int)out;
6352             emit_jne(1);
6353           }else{
6354             add_to_linker((int)out,ba[i],internal);
6355             emit_jeq(0);
6356           }
6357         {
6358         }
6359       } // if(!only32)
6360
6361       if(invert) {
6362         if(adj) emit_addimm(cc,-CLOCK_ADJUST(adj),cc);
6363         #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
6364         else if(match) emit_addnop(13);
6365         #endif
6366         store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6367         load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6368         if(internal)
6369           assem_debug("branch: internal\n");
6370         else
6371           assem_debug("branch: external\n");
6372         if(internal&&is_ds[(ba[i]-start)>>2]) {
6373           ds_assemble_entry(i);
6374         }
6375         else {
6376           add_to_linker((int)out,ba[i],internal);
6377           emit_jmp(0);
6378         }
6379         set_jump_target(nottaken,(int)out);
6380       }
6381
6382       if(adj) {
6383         if(!invert) emit_addimm(cc,CLOCK_ADJUST(adj),cc);
6384       }
6385     } // (!unconditional)
6386   } // if(ooo)
6387   else
6388   {
6389     // In-order execution (branch first)
6390     //printf("IOE\n");
6391     int nottaken=0;
6392     if(1) {
6393       //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
6394       if(1) {
6395         assert(fs>=0);
6396         emit_testimm(fs,0x800000);
6397         if(source[i]&0x10000) // BC1T
6398         {
6399           nottaken=(int)out;
6400           emit_jeq(1);
6401         }
6402         else // BC1F
6403         {
6404           nottaken=(int)out;
6405           emit_jne(1);
6406         }
6407       }
6408     } // if(!unconditional)
6409     int adj;
6410     uint64_t ds_unneeded=branch_regs[i].u;
6411     uint64_t ds_unneeded_upper=branch_regs[i].uu;
6412     ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6413     ds_unneeded_upper&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6414     if((~ds_unneeded_upper>>rt1[i+1])&1) ds_unneeded_upper&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
6415     ds_unneeded|=1;
6416     ds_unneeded_upper|=1;
6417     // branch taken
6418     //assem_debug("1:\n");
6419     wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6420                   ds_unneeded,ds_unneeded_upper);
6421     // load regs
6422     load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
6423     address_generation(i+1,&branch_regs[i],0);
6424     load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,INVCP);
6425     ds_assemble(i+1,&branch_regs[i]);
6426     cc=get_reg(branch_regs[i].regmap,CCREG);
6427     if(cc==-1) {
6428       emit_loadreg(CCREG,cc=HOST_CCREG);
6429       // CHECK: Is the following instruction (fall thru) allocated ok?
6430     }
6431     assert(cc==HOST_CCREG);
6432     store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6433     do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
6434     assem_debug("cycle count (adj)\n");
6435     if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
6436     load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6437     if(internal)
6438       assem_debug("branch: internal\n");
6439     else
6440       assem_debug("branch: external\n");
6441     if(internal&&is_ds[(ba[i]-start)>>2]) {
6442       ds_assemble_entry(i);
6443     }
6444     else {
6445       add_to_linker((int)out,ba[i],internal);
6446       emit_jmp(0);
6447     }
6448
6449     // branch not taken
6450     if(1) { // <- FIXME (don't need this)
6451       set_jump_target(nottaken,(int)out);
6452       assem_debug("1:\n");
6453       if(!likely[i]) {
6454         wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6455                       ds_unneeded,ds_unneeded_upper);
6456         load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
6457         address_generation(i+1,&branch_regs[i],0);
6458         load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
6459         ds_assemble(i+1,&branch_regs[i]);
6460       }
6461       cc=get_reg(branch_regs[i].regmap,CCREG);
6462       if(cc==-1&&!likely[i]) {
6463         // Cycle count isn't in a register, temporarily load it then write it out
6464         emit_loadreg(CCREG,HOST_CCREG);
6465         emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),HOST_CCREG);
6466         int jaddr=(int)out;
6467         emit_jns(0);
6468         add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
6469         emit_storereg(CCREG,HOST_CCREG);
6470       }
6471       else{
6472         cc=get_reg(i_regmap,CCREG);
6473         assert(cc==HOST_CCREG);
6474         emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),cc);
6475         int jaddr=(int)out;
6476         emit_jns(0);
6477         add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
6478       }
6479     }
6480   }
6481 }
6482
6483 static void pagespan_assemble(int i,struct regstat *i_regs)
6484 {
6485   int s1l=get_reg(i_regs->regmap,rs1[i]);
6486   int s1h=get_reg(i_regs->regmap,rs1[i]|64);
6487   int s2l=get_reg(i_regs->regmap,rs2[i]);
6488   int s2h=get_reg(i_regs->regmap,rs2[i]|64);
6489   void *nt_branch=NULL;
6490   int taken=0;
6491   int nottaken=0;
6492   int unconditional=0;
6493   if(rs1[i]==0)
6494   {
6495     s1l=s2l;s1h=s2h;
6496     s2l=s2h=-1;
6497   }
6498   else if(rs2[i]==0)
6499   {
6500     s2l=s2h=-1;
6501   }
6502   if((i_regs->is32>>rs1[i])&(i_regs->is32>>rs2[i])&1) {
6503     s1h=s2h=-1;
6504   }
6505   int hr=0;
6506   int addr,alt,ntaddr;
6507   if(i_regs->regmap[HOST_BTREG]<0) {addr=HOST_BTREG;}
6508   else {
6509     while(hr<HOST_REGS)
6510     {
6511       if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
6512          (i_regs->regmap[hr]&63)!=rs1[i] &&
6513          (i_regs->regmap[hr]&63)!=rs2[i] )
6514       {
6515         addr=hr++;break;
6516       }
6517       hr++;
6518     }
6519   }
6520   while(hr<HOST_REGS)
6521   {
6522     if(hr!=EXCLUDE_REG && hr!=HOST_CCREG && hr!=HOST_BTREG &&
6523        (i_regs->regmap[hr]&63)!=rs1[i] &&
6524        (i_regs->regmap[hr]&63)!=rs2[i] )
6525     {
6526       alt=hr++;break;
6527     }
6528     hr++;
6529   }
6530   if((opcode[i]&0x2E)==6) // BLEZ/BGTZ needs another register
6531   {
6532     while(hr<HOST_REGS)
6533     {
6534       if(hr!=EXCLUDE_REG && hr!=HOST_CCREG && hr!=HOST_BTREG &&
6535          (i_regs->regmap[hr]&63)!=rs1[i] &&
6536          (i_regs->regmap[hr]&63)!=rs2[i] )
6537       {
6538         ntaddr=hr;break;
6539       }
6540       hr++;
6541     }
6542   }
6543   assert(hr<HOST_REGS);
6544   if((opcode[i]&0x2e)==4||opcode[i]==0x11) { // BEQ/BNE/BEQL/BNEL/BC1
6545     load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,CCREG,CCREG);
6546   }
6547   emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i]+2),HOST_CCREG);
6548   if(opcode[i]==2) // J
6549   {
6550     unconditional=1;
6551   }
6552   if(opcode[i]==3) // JAL
6553   {
6554     // TODO: mini_ht
6555     int rt=get_reg(i_regs->regmap,31);
6556     emit_movimm(start+i*4+8,rt);
6557     unconditional=1;
6558   }
6559   if(opcode[i]==0&&(opcode2[i]&0x3E)==8) // JR/JALR
6560   {
6561     emit_mov(s1l,addr);
6562     if(opcode2[i]==9) // JALR
6563     {
6564       int rt=get_reg(i_regs->regmap,rt1[i]);
6565       emit_movimm(start+i*4+8,rt);
6566     }
6567   }
6568   if((opcode[i]&0x3f)==4) // BEQ
6569   {
6570     if(rs1[i]==rs2[i])
6571     {
6572       unconditional=1;
6573     }
6574     else
6575     #ifdef HAVE_CMOV_IMM
6576     if(s1h<0) {
6577       if(s2l>=0) emit_cmp(s1l,s2l);
6578       else emit_test(s1l,s1l);
6579       emit_cmov2imm_e_ne_compact(ba[i],start+i*4+8,addr);
6580     }
6581     else
6582     #endif
6583     {
6584       assert(s1l>=0);
6585       emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
6586       if(s1h>=0) {
6587         if(s2h>=0) emit_cmp(s1h,s2h);
6588         else emit_test(s1h,s1h);
6589         emit_cmovne_reg(alt,addr);
6590       }
6591       if(s2l>=0) emit_cmp(s1l,s2l);
6592       else emit_test(s1l,s1l);
6593       emit_cmovne_reg(alt,addr);
6594     }
6595   }
6596   if((opcode[i]&0x3f)==5) // BNE
6597   {
6598     #ifdef HAVE_CMOV_IMM
6599     if(s1h<0) {
6600       if(s2l>=0) emit_cmp(s1l,s2l);
6601       else emit_test(s1l,s1l);
6602       emit_cmov2imm_e_ne_compact(start+i*4+8,ba[i],addr);
6603     }
6604     else
6605     #endif
6606     {
6607       assert(s1l>=0);
6608       emit_mov2imm_compact(start+i*4+8,addr,ba[i],alt);
6609       if(s1h>=0) {
6610         if(s2h>=0) emit_cmp(s1h,s2h);
6611         else emit_test(s1h,s1h);
6612         emit_cmovne_reg(alt,addr);
6613       }
6614       if(s2l>=0) emit_cmp(s1l,s2l);
6615       else emit_test(s1l,s1l);
6616       emit_cmovne_reg(alt,addr);
6617     }
6618   }
6619   if((opcode[i]&0x3f)==0x14) // BEQL
6620   {
6621     if(s1h>=0) {
6622       if(s2h>=0) emit_cmp(s1h,s2h);
6623       else emit_test(s1h,s1h);
6624       nottaken=(int)out;
6625       emit_jne(0);
6626     }
6627     if(s2l>=0) emit_cmp(s1l,s2l);
6628     else emit_test(s1l,s1l);
6629     if(nottaken) set_jump_target(nottaken,(int)out);
6630     nottaken=(int)out;
6631     emit_jne(0);
6632   }
6633   if((opcode[i]&0x3f)==0x15) // BNEL
6634   {
6635     if(s1h>=0) {
6636       if(s2h>=0) emit_cmp(s1h,s2h);
6637       else emit_test(s1h,s1h);
6638       taken=(int)out;
6639       emit_jne(0);
6640     }
6641     if(s2l>=0) emit_cmp(s1l,s2l);
6642     else emit_test(s1l,s1l);
6643     nottaken=(int)out;
6644     emit_jeq(0);
6645     if(taken) set_jump_target(taken,(int)out);
6646   }
6647   if((opcode[i]&0x3f)==6) // BLEZ
6648   {
6649     emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
6650     emit_cmpimm(s1l,1);
6651     if(s1h>=0) emit_mov(addr,ntaddr);
6652     emit_cmovl_reg(alt,addr);
6653     if(s1h>=0) {
6654       emit_test(s1h,s1h);
6655       emit_cmovne_reg(ntaddr,addr);
6656       emit_cmovs_reg(alt,addr);
6657     }
6658   }
6659   if((opcode[i]&0x3f)==7) // BGTZ
6660   {
6661     emit_mov2imm_compact(ba[i],addr,start+i*4+8,ntaddr);
6662     emit_cmpimm(s1l,1);
6663     if(s1h>=0) emit_mov(addr,alt);
6664     emit_cmovl_reg(ntaddr,addr);
6665     if(s1h>=0) {
6666       emit_test(s1h,s1h);
6667       emit_cmovne_reg(alt,addr);
6668       emit_cmovs_reg(ntaddr,addr);
6669     }
6670   }
6671   if((opcode[i]&0x3f)==0x16) // BLEZL
6672   {
6673     assert((opcode[i]&0x3f)!=0x16);
6674   }
6675   if((opcode[i]&0x3f)==0x17) // BGTZL
6676   {
6677     assert((opcode[i]&0x3f)!=0x17);
6678   }
6679   assert(opcode[i]!=1); // BLTZ/BGEZ
6680
6681   //FIXME: Check CSREG
6682   if(opcode[i]==0x11 && opcode2[i]==0x08 ) {
6683     if((source[i]&0x30000)==0) // BC1F
6684     {
6685       emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
6686       emit_testimm(s1l,0x800000);
6687       emit_cmovne_reg(alt,addr);
6688     }
6689     if((source[i]&0x30000)==0x10000) // BC1T
6690     {
6691       emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
6692       emit_testimm(s1l,0x800000);
6693       emit_cmovne_reg(alt,addr);
6694     }
6695     if((source[i]&0x30000)==0x20000) // BC1FL
6696     {
6697       emit_testimm(s1l,0x800000);
6698       nottaken=(int)out;
6699       emit_jne(0);
6700     }
6701     if((source[i]&0x30000)==0x30000) // BC1TL
6702     {
6703       emit_testimm(s1l,0x800000);
6704       nottaken=(int)out;
6705       emit_jeq(0);
6706     }
6707   }
6708
6709   assert(i_regs->regmap[HOST_CCREG]==CCREG);
6710   wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty);
6711   if(likely[i]||unconditional)
6712   {
6713     emit_movimm(ba[i],HOST_BTREG);
6714   }
6715   else if(addr!=HOST_BTREG)
6716   {
6717     emit_mov(addr,HOST_BTREG);
6718   }
6719   void *branch_addr=out;
6720   emit_jmp(0);
6721   int target_addr=start+i*4+5;
6722   void *stub=out;
6723   void *compiled_target_addr=check_addr(target_addr);
6724   emit_extjump_ds((int)branch_addr,target_addr);
6725   if(compiled_target_addr) {
6726     set_jump_target((int)branch_addr,(int)compiled_target_addr);
6727     add_link(target_addr,stub);
6728   }
6729   else set_jump_target((int)branch_addr,(int)stub);
6730   if(likely[i]) {
6731     // Not-taken path
6732     set_jump_target((int)nottaken,(int)out);
6733     wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty);
6734     void *branch_addr=out;
6735     emit_jmp(0);
6736     int target_addr=start+i*4+8;
6737     void *stub=out;
6738     void *compiled_target_addr=check_addr(target_addr);
6739     emit_extjump_ds((int)branch_addr,target_addr);
6740     if(compiled_target_addr) {
6741       set_jump_target((int)branch_addr,(int)compiled_target_addr);
6742       add_link(target_addr,stub);
6743     }
6744     else set_jump_target((int)branch_addr,(int)stub);
6745   }
6746 }
6747
6748 // Assemble the delay slot for the above
6749 static void pagespan_ds()
6750 {
6751   assem_debug("initial delay slot:\n");
6752   u_int vaddr=start+1;
6753   u_int page=get_page(vaddr);
6754   u_int vpage=get_vpage(vaddr);
6755   ll_add(jump_dirty+vpage,vaddr,(void *)out);
6756   do_dirty_stub_ds();
6757   ll_add(jump_in+page,vaddr,(void *)out);
6758   assert(regs[0].regmap_entry[HOST_CCREG]==CCREG);
6759   if(regs[0].regmap[HOST_CCREG]!=CCREG)
6760     wb_register(CCREG,regs[0].regmap_entry,regs[0].wasdirty,regs[0].was32);
6761   if(regs[0].regmap[HOST_BTREG]!=BTREG)
6762     emit_writeword(HOST_BTREG,(int)&branch_target);
6763   load_regs(regs[0].regmap_entry,regs[0].regmap,regs[0].was32,rs1[0],rs2[0]);
6764   address_generation(0,&regs[0],regs[0].regmap_entry);
6765   if(itype[0]==STORE||itype[0]==STORELR||(opcode[0]&0x3b)==0x39||(opcode[0]&0x3b)==0x3a)
6766     load_regs(regs[0].regmap_entry,regs[0].regmap,regs[0].was32,INVCP,INVCP);
6767   cop1_usable=0;
6768   is_delayslot=0;
6769   switch(itype[0]) {
6770     case ALU:
6771       alu_assemble(0,&regs[0]);break;
6772     case IMM16:
6773       imm16_assemble(0,&regs[0]);break;
6774     case SHIFT:
6775       shift_assemble(0,&regs[0]);break;
6776     case SHIFTIMM:
6777       shiftimm_assemble(0,&regs[0]);break;
6778     case LOAD:
6779       load_assemble(0,&regs[0]);break;
6780     case LOADLR:
6781       loadlr_assemble(0,&regs[0]);break;
6782     case STORE:
6783       store_assemble(0,&regs[0]);break;
6784     case STORELR:
6785       storelr_assemble(0,&regs[0]);break;
6786     case COP0:
6787       cop0_assemble(0,&regs[0]);break;
6788     case COP1:
6789       cop1_assemble(0,&regs[0]);break;
6790     case C1LS:
6791       c1ls_assemble(0,&regs[0]);break;
6792     case COP2:
6793       cop2_assemble(0,&regs[0]);break;
6794     case C2LS:
6795       c2ls_assemble(0,&regs[0]);break;
6796     case C2OP:
6797       c2op_assemble(0,&regs[0]);break;
6798     case FCONV:
6799       fconv_assemble(0,&regs[0]);break;
6800     case FLOAT:
6801       float_assemble(0,&regs[0]);break;
6802     case FCOMP:
6803       fcomp_assemble(0,&regs[0]);break;
6804     case MULTDIV:
6805       multdiv_assemble(0,&regs[0]);break;
6806     case MOV:
6807       mov_assemble(0,&regs[0]);break;
6808     case SYSCALL:
6809     case HLECALL:
6810     case INTCALL:
6811     case SPAN:
6812     case UJUMP:
6813     case RJUMP:
6814     case CJUMP:
6815     case SJUMP:
6816     case FJUMP:
6817       SysPrintf("Jump in the delay slot.  This is probably a bug.\n");
6818   }
6819   int btaddr=get_reg(regs[0].regmap,BTREG);
6820   if(btaddr<0) {
6821     btaddr=get_reg(regs[0].regmap,-1);
6822     emit_readword((int)&branch_target,btaddr);
6823   }
6824   assert(btaddr!=HOST_CCREG);
6825   if(regs[0].regmap[HOST_CCREG]!=CCREG) emit_loadreg(CCREG,HOST_CCREG);
6826 #ifdef HOST_IMM8
6827   emit_movimm(start+4,HOST_TEMPREG);
6828   emit_cmp(btaddr,HOST_TEMPREG);
6829 #else
6830   emit_cmpimm(btaddr,start+4);
6831 #endif
6832   int branch=(int)out;
6833   emit_jeq(0);
6834   store_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,-1);
6835   emit_jmp(jump_vaddr_reg[btaddr]);
6836   set_jump_target(branch,(int)out);
6837   store_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,start+4);
6838   load_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,start+4);
6839 }
6840
6841 // Basic liveness analysis for MIPS registers
6842 void unneeded_registers(int istart,int iend,int r)
6843 {
6844   int i;
6845   uint64_t u,uu,gte_u,b,bu,gte_bu;
6846   uint64_t temp_u,temp_uu,temp_gte_u=0;
6847   uint64_t tdep;
6848   uint64_t gte_u_unknown=0;
6849   if(new_dynarec_hacks&NDHACK_GTE_UNNEEDED)
6850     gte_u_unknown=~0ll;
6851   if(iend==slen-1) {
6852     u=1;uu=1;
6853     gte_u=gte_u_unknown;
6854   }else{
6855     u=unneeded_reg[iend+1];
6856     uu=unneeded_reg_upper[iend+1];
6857     u=1;uu=1;
6858     gte_u=gte_unneeded[iend+1];
6859   }
6860
6861   for (i=iend;i>=istart;i--)
6862   {
6863     //printf("unneeded registers i=%d (%d,%d) r=%d\n",i,istart,iend,r);
6864     if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
6865     {
6866       // If subroutine call, flag return address as a possible branch target
6867       if(rt1[i]==31 && i<slen-2) bt[i+2]=1;
6868
6869       if(ba[i]<start || ba[i]>=(start+slen*4))
6870       {
6871         // Branch out of this block, flush all regs
6872         u=1;
6873         uu=1;
6874         gte_u=gte_u_unknown;
6875         /* Hexagon hack
6876         if(itype[i]==UJUMP&&rt1[i]==31)
6877         {
6878           uu=u=0x300C00F; // Discard at, v0-v1, t6-t9
6879         }
6880         if(itype[i]==RJUMP&&rs1[i]==31)
6881         {
6882           uu=u=0x300C0F3; // Discard at, a0-a3, t6-t9
6883         }
6884         if(start>0x80000400&&start<0x80000000+RAM_SIZE) {
6885           if(itype[i]==UJUMP&&rt1[i]==31)
6886           {
6887             //uu=u=0x30300FF0FLL; // Discard at, v0-v1, t0-t9, lo, hi
6888             uu=u=0x300FF0F; // Discard at, v0-v1, t0-t9
6889           }
6890           if(itype[i]==RJUMP&&rs1[i]==31)
6891           {
6892             //uu=u=0x30300FFF3LL; // Discard at, a0-a3, t0-t9, lo, hi
6893             uu=u=0x300FFF3; // Discard at, a0-a3, t0-t9
6894           }
6895         }*/
6896         branch_unneeded_reg[i]=u;
6897         branch_unneeded_reg_upper[i]=uu;
6898         // Merge in delay slot
6899         tdep=(~uu>>rt1[i+1])&1;
6900         u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6901         uu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6902         u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6903         uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6904         uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6905         u|=1;uu|=1;
6906         gte_u|=gte_rt[i+1];
6907         gte_u&=~gte_rs[i+1];
6908         // If branch is "likely" (and conditional)
6909         // then we skip the delay slot on the fall-thru path
6910         if(likely[i]) {
6911           if(i<slen-1) {
6912             u&=unneeded_reg[i+2];
6913             uu&=unneeded_reg_upper[i+2];
6914             gte_u&=gte_unneeded[i+2];
6915           }
6916           else
6917           {
6918             u=1;
6919             uu=1;
6920             gte_u=gte_u_unknown;
6921           }
6922         }
6923       }
6924       else
6925       {
6926         // Internal branch, flag target
6927         bt[(ba[i]-start)>>2]=1;
6928         if(ba[i]<=start+i*4) {
6929           // Backward branch
6930           if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
6931           {
6932             // Unconditional branch
6933             temp_u=1;temp_uu=1;
6934             temp_gte_u=0;
6935           } else {
6936             // Conditional branch (not taken case)
6937             temp_u=unneeded_reg[i+2];
6938             temp_uu=unneeded_reg_upper[i+2];
6939             temp_gte_u&=gte_unneeded[i+2];
6940           }
6941           // Merge in delay slot
6942           tdep=(~temp_uu>>rt1[i+1])&1;
6943           temp_u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6944           temp_uu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6945           temp_u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6946           temp_uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6947           temp_uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6948           temp_u|=1;temp_uu|=1;
6949           temp_gte_u|=gte_rt[i+1];
6950           temp_gte_u&=~gte_rs[i+1];
6951           // If branch is "likely" (and conditional)
6952           // then we skip the delay slot on the fall-thru path
6953           if(likely[i]) {
6954             if(i<slen-1) {
6955               temp_u&=unneeded_reg[i+2];
6956               temp_uu&=unneeded_reg_upper[i+2];
6957               temp_gte_u&=gte_unneeded[i+2];
6958             }
6959             else
6960             {
6961               temp_u=1;
6962               temp_uu=1;
6963               temp_gte_u=gte_u_unknown;
6964             }
6965           }
6966           tdep=(~temp_uu>>rt1[i])&1;
6967           temp_u|=(1LL<<rt1[i])|(1LL<<rt2[i]);
6968           temp_uu|=(1LL<<rt1[i])|(1LL<<rt2[i]);
6969           temp_u&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
6970           temp_uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
6971           temp_uu&=~((tdep<<dep1[i])|(tdep<<dep2[i]));
6972           temp_u|=1;temp_uu|=1;
6973           temp_gte_u|=gte_rt[i];
6974           temp_gte_u&=~gte_rs[i];
6975           unneeded_reg[i]=temp_u;
6976           unneeded_reg_upper[i]=temp_uu;
6977           gte_unneeded[i]=temp_gte_u;
6978           // Only go three levels deep.  This recursion can take an
6979           // excessive amount of time if there are a lot of nested loops.
6980           if(r<2) {
6981             unneeded_registers((ba[i]-start)>>2,i-1,r+1);
6982           }else{
6983             unneeded_reg[(ba[i]-start)>>2]=1;
6984             unneeded_reg_upper[(ba[i]-start)>>2]=1;
6985             gte_unneeded[(ba[i]-start)>>2]=gte_u_unknown;
6986           }
6987         } /*else*/ if(1) {
6988           if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
6989           {
6990             // Unconditional branch
6991             u=unneeded_reg[(ba[i]-start)>>2];
6992             uu=unneeded_reg_upper[(ba[i]-start)>>2];
6993             gte_u=gte_unneeded[(ba[i]-start)>>2];
6994             branch_unneeded_reg[i]=u;
6995             branch_unneeded_reg_upper[i]=uu;
6996         //u=1;
6997         //uu=1;
6998         //branch_unneeded_reg[i]=u;
6999         //branch_unneeded_reg_upper[i]=uu;
7000             // Merge in delay slot
7001             tdep=(~uu>>rt1[i+1])&1;
7002             u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
7003             uu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
7004             u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
7005             uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
7006             uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
7007             u|=1;uu|=1;
7008             gte_u|=gte_rt[i+1];
7009             gte_u&=~gte_rs[i+1];
7010           } else {
7011             // Conditional branch
7012             b=unneeded_reg[(ba[i]-start)>>2];
7013             bu=unneeded_reg_upper[(ba[i]-start)>>2];
7014             gte_bu=gte_unneeded[(ba[i]-start)>>2];
7015             branch_unneeded_reg[i]=b;
7016             branch_unneeded_reg_upper[i]=bu;
7017         //b=1;
7018         //bu=1;
7019         //branch_unneeded_reg[i]=b;
7020         //branch_unneeded_reg_upper[i]=bu;
7021             // Branch delay slot
7022             tdep=(~uu>>rt1[i+1])&1;
7023             b|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
7024             bu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
7025             b&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
7026             bu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
7027             bu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
7028             b|=1;bu|=1;
7029             gte_bu|=gte_rt[i+1];
7030             gte_bu&=~gte_rs[i+1];
7031             // If branch is "likely" then we skip the
7032             // delay slot on the fall-thru path
7033             if(likely[i]) {
7034               u=b;
7035               uu=bu;
7036               gte_u=gte_bu;
7037               if(i<slen-1) {
7038                 u&=unneeded_reg[i+2];
7039                 uu&=unneeded_reg_upper[i+2];
7040                 gte_u&=gte_unneeded[i+2];
7041         //u=1;
7042         //uu=1;
7043               }
7044             } else {
7045               u&=b;
7046               uu&=bu;
7047               gte_u&=gte_bu;
7048         //u=1;
7049         //uu=1;
7050             }
7051             if(i<slen-1) {
7052               branch_unneeded_reg[i]&=unneeded_reg[i+2];
7053               branch_unneeded_reg_upper[i]&=unneeded_reg_upper[i+2];
7054         //branch_unneeded_reg[i]=1;
7055         //branch_unneeded_reg_upper[i]=1;
7056             } else {
7057               branch_unneeded_reg[i]=1;
7058               branch_unneeded_reg_upper[i]=1;
7059             }
7060           }
7061         }
7062       }
7063     }
7064     else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
7065     {
7066       // SYSCALL instruction (software interrupt)
7067       u=1;
7068       uu=1;
7069     }
7070     else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
7071     {
7072       // ERET instruction (return from interrupt)
7073       u=1;
7074       uu=1;
7075     }
7076     //u=uu=1; // DEBUG
7077     tdep=(~uu>>rt1[i])&1;
7078     // Written registers are unneeded
7079     u|=1LL<<rt1[i];
7080     u|=1LL<<rt2[i];
7081     uu|=1LL<<rt1[i];
7082     uu|=1LL<<rt2[i];
7083     gte_u|=gte_rt[i];
7084     // Accessed registers are needed
7085     u&=~(1LL<<rs1[i]);
7086     u&=~(1LL<<rs2[i]);
7087     uu&=~(1LL<<us1[i]);
7088     uu&=~(1LL<<us2[i]);
7089     gte_u&=~gte_rs[i];
7090     if(gte_rs[i]&&rt1[i]&&(unneeded_reg[i+1]&(1ll<<rt1[i])))
7091       gte_u|=gte_rs[i]&gte_unneeded[i+1]; // MFC2/CFC2 to dead register, unneeded
7092     // Source-target dependencies
7093     uu&=~(tdep<<dep1[i]);
7094     uu&=~(tdep<<dep2[i]);
7095     // R0 is always unneeded
7096     u|=1;uu|=1;
7097     // Save it
7098     unneeded_reg[i]=u;
7099     unneeded_reg_upper[i]=uu;
7100     gte_unneeded[i]=gte_u;
7101     /*
7102     printf("ur (%d,%d) %x: ",istart,iend,start+i*4);
7103     printf("U:");
7104     int r;
7105     for(r=1;r<=CCREG;r++) {
7106       if((unneeded_reg[i]>>r)&1) {
7107         if(r==HIREG) printf(" HI");
7108         else if(r==LOREG) printf(" LO");
7109         else printf(" r%d",r);
7110       }
7111     }
7112     printf(" UU:");
7113     for(r=1;r<=CCREG;r++) {
7114       if(((unneeded_reg_upper[i]&~unneeded_reg[i])>>r)&1) {
7115         if(r==HIREG) printf(" HI");
7116         else if(r==LOREG) printf(" LO");
7117         else printf(" r%d",r);
7118       }
7119     }
7120     printf("\n");*/
7121   }
7122 #ifdef FORCE32
7123   for (i=iend;i>=istart;i--)
7124   {
7125     unneeded_reg_upper[i]=branch_unneeded_reg_upper[i]=-1LL;
7126   }
7127 #endif
7128 }
7129
7130 // Identify registers which are likely to contain 32-bit values
7131 // This is used to predict whether any branches will jump to a
7132 // location with 64-bit values in registers.
7133 static void provisional_32bit()
7134 {
7135   int i,j;
7136   uint64_t is32=1;
7137   uint64_t lastbranch=1;
7138
7139   for(i=0;i<slen;i++)
7140   {
7141     if(i>0) {
7142       if(itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP) {
7143         if(i>1) is32=lastbranch;
7144         else is32=1;
7145       }
7146     }
7147     if(i>1)
7148     {
7149       if(itype[i-2]==CJUMP||itype[i-2]==SJUMP||itype[i-2]==FJUMP) {
7150         if(likely[i-2]) {
7151           if(i>2) is32=lastbranch;
7152           else is32=1;
7153         }
7154       }
7155       if((opcode[i-2]&0x2f)==0x05) // BNE/BNEL
7156       {
7157         if(rs1[i-2]==0||rs2[i-2]==0)
7158         {
7159           if(rs1[i-2]) {
7160             is32|=1LL<<rs1[i-2];
7161           }
7162           if(rs2[i-2]) {
7163             is32|=1LL<<rs2[i-2];
7164           }
7165         }
7166       }
7167     }
7168     // If something jumps here with 64-bit values
7169     // then promote those registers to 64 bits
7170     if(bt[i])
7171     {
7172       uint64_t temp_is32=is32;
7173       for(j=i-1;j>=0;j--)
7174       {
7175         if(ba[j]==start+i*4)
7176           //temp_is32&=branch_regs[j].is32;
7177           temp_is32&=p32[j];
7178       }
7179       for(j=i;j<slen;j++)
7180       {
7181         if(ba[j]==start+i*4)
7182           temp_is32=1;
7183       }
7184       is32=temp_is32;
7185     }
7186     int type=itype[i];
7187     int op=opcode[i];
7188     int op2=opcode2[i];
7189     int rt=rt1[i];
7190     int s1=rs1[i];
7191     int s2=rs2[i];
7192     if(type==UJUMP||type==RJUMP||type==CJUMP||type==SJUMP||type==FJUMP) {
7193       // Branches don't write registers, consider the delay slot instead.
7194       type=itype[i+1];
7195       op=opcode[i+1];
7196       op2=opcode2[i+1];
7197       rt=rt1[i+1];
7198       s1=rs1[i+1];
7199       s2=rs2[i+1];
7200       lastbranch=is32;
7201     }
7202     switch(type) {
7203       case LOAD:
7204         if(opcode[i]==0x27||opcode[i]==0x37|| // LWU/LD
7205            opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
7206           is32&=~(1LL<<rt);
7207         else
7208           is32|=1LL<<rt;
7209         break;
7210       case STORE:
7211       case STORELR:
7212         break;
7213       case LOADLR:
7214         if(op==0x1a||op==0x1b) is32&=~(1LL<<rt); // LDR/LDL
7215         if(op==0x22) is32|=1LL<<rt; // LWL
7216         break;
7217       case IMM16:
7218         if (op==0x08||op==0x09|| // ADDI/ADDIU
7219             op==0x0a||op==0x0b|| // SLTI/SLTIU
7220             op==0x0c|| // ANDI
7221             op==0x0f)  // LUI
7222         {
7223           is32|=1LL<<rt;
7224         }
7225         if(op==0x18||op==0x19) { // DADDI/DADDIU
7226           is32&=~(1LL<<rt);
7227           //if(imm[i]==0)
7228           //  is32|=((is32>>s1)&1LL)<<rt;
7229         }
7230         if(op==0x0d||op==0x0e) { // ORI/XORI
7231           uint64_t sr=((is32>>s1)&1LL);
7232           is32&=~(1LL<<rt);
7233           is32|=sr<<rt;
7234         }
7235         break;
7236       case UJUMP:
7237         break;
7238       case RJUMP:
7239         break;
7240       case CJUMP:
7241         break;
7242       case SJUMP:
7243         break;
7244       case FJUMP:
7245         break;
7246       case ALU:
7247         if(op2>=0x20&&op2<=0x23) { // ADD/ADDU/SUB/SUBU
7248           is32|=1LL<<rt;
7249         }
7250         if(op2==0x2a||op2==0x2b) { // SLT/SLTU
7251           is32|=1LL<<rt;
7252         }
7253         else if(op2>=0x24&&op2<=0x27) { // AND/OR/XOR/NOR
7254           uint64_t sr=((is32>>s1)&(is32>>s2)&1LL);
7255           is32&=~(1LL<<rt);
7256           is32|=sr<<rt;
7257         }
7258         else if(op2>=0x2c&&op2<=0x2d) { // DADD/DADDU
7259           if(s1==0&&s2==0) {
7260             is32|=1LL<<rt;
7261           }
7262           else if(s2==0) {
7263             uint64_t sr=((is32>>s1)&1LL);
7264             is32&=~(1LL<<rt);
7265             is32|=sr<<rt;
7266           }
7267           else if(s1==0) {
7268             uint64_t sr=((is32>>s2)&1LL);
7269             is32&=~(1LL<<rt);
7270             is32|=sr<<rt;
7271           }
7272           else {
7273             is32&=~(1LL<<rt);
7274           }
7275         }
7276         else if(op2>=0x2e&&op2<=0x2f) { // DSUB/DSUBU
7277           if(s1==0&&s2==0) {
7278             is32|=1LL<<rt;
7279           }
7280           else if(s2==0) {
7281             uint64_t sr=((is32>>s1)&1LL);
7282             is32&=~(1LL<<rt);
7283             is32|=sr<<rt;
7284           }
7285           else {
7286             is32&=~(1LL<<rt);
7287           }
7288         }
7289         break;
7290       case MULTDIV:
7291         if (op2>=0x1c&&op2<=0x1f) { // DMULT/DMULTU/DDIV/DDIVU
7292           is32&=~((1LL<<HIREG)|(1LL<<LOREG));
7293         }
7294         else {
7295           is32|=(1LL<<HIREG)|(1LL<<LOREG);
7296         }
7297         break;
7298       case MOV:
7299         {
7300           uint64_t sr=((is32>>s1)&1LL);
7301           is32&=~(1LL<<rt);
7302           is32|=sr<<rt;
7303         }
7304         break;
7305       case SHIFT:
7306         if(op2>=0x14&&op2<=0x17) is32&=~(1LL<<rt); // DSLLV/DSRLV/DSRAV
7307         else is32|=1LL<<rt; // SLLV/SRLV/SRAV
7308         break;
7309       case SHIFTIMM:
7310         is32|=1LL<<rt;
7311         // DSLL/DSRL/DSRA/DSLL32/DSRL32 but not DSRA32 have 64-bit result
7312         if(op2>=0x38&&op2<0x3f) is32&=~(1LL<<rt);
7313         break;
7314       case COP0:
7315         if(op2==0) is32|=1LL<<rt; // MFC0
7316         break;
7317       case COP1:
7318       case COP2:
7319         if(op2==0) is32|=1LL<<rt; // MFC1
7320         if(op2==1) is32&=~(1LL<<rt); // DMFC1
7321         if(op2==2) is32|=1LL<<rt; // CFC1
7322         break;
7323       case C1LS:
7324       case C2LS:
7325         break;
7326       case FLOAT:
7327       case FCONV:
7328         break;
7329       case FCOMP:
7330         break;
7331       case C2OP:
7332       case SYSCALL:
7333       case HLECALL:
7334         break;
7335       default:
7336         break;
7337     }
7338     is32|=1;
7339     p32[i]=is32;
7340
7341     if(i>0)
7342     {
7343       if(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)
7344       {
7345         if(rt1[i-1]==31) // JAL/JALR
7346         {
7347           // Subroutine call will return here, don't alloc any registers
7348           is32=1;
7349         }
7350         else if(i+1<slen)
7351         {
7352           // Internal branch will jump here, match registers to caller
7353           is32=0x3FFFFFFFFLL;
7354         }
7355       }
7356     }
7357   }
7358 }
7359
7360 // Identify registers which may be assumed to contain 32-bit values
7361 // and where optimizations will rely on this.
7362 // This is used to determine whether backward branches can safely
7363 // jump to a location with 64-bit values in registers.
7364 static void provisional_r32()
7365 {
7366   u_int r32=0;
7367   int i;
7368
7369   for (i=slen-1;i>=0;i--)
7370   {
7371     int hr;
7372     if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
7373     {
7374       if(ba[i]<start || ba[i]>=(start+slen*4))
7375       {
7376         // Branch out of this block, don't need anything
7377         r32=0;
7378       }
7379       else
7380       {
7381         // Internal branch
7382         // Need whatever matches the target
7383         // (and doesn't get overwritten by the delay slot instruction)
7384         r32=0;
7385         int t=(ba[i]-start)>>2;
7386         if(ba[i]>start+i*4) {
7387           // Forward branch
7388           //if(!(requires_32bit[t]&~regs[i].was32))
7389           //  r32|=requires_32bit[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
7390           if(!(pr32[t]&~regs[i].was32))
7391             r32|=pr32[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
7392         }else{
7393           // Backward branch
7394           if(!(regs[t].was32&~unneeded_reg_upper[t]&~regs[i].was32))
7395             r32|=regs[t].was32&~unneeded_reg_upper[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
7396         }
7397       }
7398       // Conditional branch may need registers for following instructions
7399       if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
7400       {
7401         if(i<slen-2) {
7402           //r32|=requires_32bit[i+2];
7403           r32|=pr32[i+2];
7404           r32&=regs[i].was32;
7405           // Mark this address as a branch target since it may be called
7406           // upon return from interrupt
7407           //bt[i+2]=1;
7408         }
7409       }
7410       // Merge in delay slot
7411       if(!likely[i]) {
7412         // These are overwritten unless the branch is "likely"
7413         // and the delay slot is nullified if not taken
7414         r32&=~(1LL<<rt1[i+1]);
7415         r32&=~(1LL<<rt2[i+1]);
7416       }
7417       // Assume these are needed (delay slot)
7418       if(us1[i+1]>0)
7419       {
7420         if((regs[i].was32>>us1[i+1])&1) r32|=1LL<<us1[i+1];
7421       }
7422       if(us2[i+1]>0)
7423       {
7424         if((regs[i].was32>>us2[i+1])&1) r32|=1LL<<us2[i+1];
7425       }
7426       if(dep1[i+1]&&!((unneeded_reg_upper[i]>>dep1[i+1])&1))
7427       {
7428         if((regs[i].was32>>dep1[i+1])&1) r32|=1LL<<dep1[i+1];
7429       }
7430       if(dep2[i+1]&&!((unneeded_reg_upper[i]>>dep2[i+1])&1))
7431       {
7432         if((regs[i].was32>>dep2[i+1])&1) r32|=1LL<<dep2[i+1];
7433       }
7434     }
7435     else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
7436     {
7437       // SYSCALL instruction (software interrupt)
7438       r32=0;
7439     }
7440     else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
7441     {
7442       // ERET instruction (return from interrupt)
7443       r32=0;
7444     }
7445     // Check 32 bits
7446     r32&=~(1LL<<rt1[i]);
7447     r32&=~(1LL<<rt2[i]);
7448     if(us1[i]>0)
7449     {
7450       if((regs[i].was32>>us1[i])&1) r32|=1LL<<us1[i];
7451     }
7452     if(us2[i]>0)
7453     {
7454       if((regs[i].was32>>us2[i])&1) r32|=1LL<<us2[i];
7455     }
7456     if(dep1[i]&&!((unneeded_reg_upper[i]>>dep1[i])&1))
7457     {
7458       if((regs[i].was32>>dep1[i])&1) r32|=1LL<<dep1[i];
7459     }
7460     if(dep2[i]&&!((unneeded_reg_upper[i]>>dep2[i])&1))
7461     {
7462       if((regs[i].was32>>dep2[i])&1) r32|=1LL<<dep2[i];
7463     }
7464     //requires_32bit[i]=r32;
7465     pr32[i]=r32;
7466
7467     // Dirty registers which are 32-bit, require 32-bit input
7468     // as they will be written as 32-bit values
7469     for(hr=0;hr<HOST_REGS;hr++)
7470     {
7471       if(regs[i].regmap_entry[hr]>0&&regs[i].regmap_entry[hr]<64) {
7472         if((regs[i].was32>>regs[i].regmap_entry[hr])&(regs[i].wasdirty>>hr)&1) {
7473           if(!((unneeded_reg_upper[i]>>regs[i].regmap_entry[hr])&1))
7474           pr32[i]|=1LL<<regs[i].regmap_entry[hr];
7475           //requires_32bit[i]|=1LL<<regs[i].regmap_entry[hr];
7476         }
7477       }
7478     }
7479   }
7480 }
7481
7482 // Write back dirty registers as soon as we will no longer modify them,
7483 // so that we don't end up with lots of writes at the branches.
7484 void clean_registers(int istart,int iend,int wr)
7485 {
7486   int i;
7487   int r;
7488   u_int will_dirty_i,will_dirty_next,temp_will_dirty;
7489   u_int wont_dirty_i,wont_dirty_next,temp_wont_dirty;
7490   if(iend==slen-1) {
7491     will_dirty_i=will_dirty_next=0;
7492     wont_dirty_i=wont_dirty_next=0;
7493   }else{
7494     will_dirty_i=will_dirty_next=will_dirty[iend+1];
7495     wont_dirty_i=wont_dirty_next=wont_dirty[iend+1];
7496   }
7497   for (i=iend;i>=istart;i--)
7498   {
7499     if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
7500     {
7501       if(ba[i]<start || ba[i]>=(start+slen*4))
7502       {
7503         // Branch out of this block, flush all regs
7504         if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
7505         {
7506           // Unconditional branch
7507           will_dirty_i=0;
7508           wont_dirty_i=0;
7509           // Merge in delay slot (will dirty)
7510           for(r=0;r<HOST_REGS;r++) {
7511             if(r!=EXCLUDE_REG) {
7512               if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7513               if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7514               if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7515               if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7516               if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7517               if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7518               if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7519               if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7520               if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7521               if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7522               if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7523               if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7524               if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7525               if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7526             }
7527           }
7528         }
7529         else
7530         {
7531           // Conditional branch
7532           will_dirty_i=0;
7533           wont_dirty_i=wont_dirty_next;
7534           // Merge in delay slot (will dirty)
7535           for(r=0;r<HOST_REGS;r++) {
7536             if(r!=EXCLUDE_REG) {
7537               if(!likely[i]) {
7538                 // Might not dirty if likely branch is not taken
7539                 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7540                 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7541                 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7542                 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7543                 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7544                 if(branch_regs[i].regmap[r]==0) will_dirty_i&=~(1<<r);
7545                 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7546                 //if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7547                 //if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7548                 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7549                 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7550                 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7551                 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7552                 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7553               }
7554             }
7555           }
7556         }
7557         // Merge in delay slot (wont dirty)
7558         for(r=0;r<HOST_REGS;r++) {
7559           if(r!=EXCLUDE_REG) {
7560             if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7561             if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7562             if((regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7563             if((regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7564             if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7565             if((branch_regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7566             if((branch_regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7567             if((branch_regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7568             if((branch_regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7569             if(branch_regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7570           }
7571         }
7572         if(wr) {
7573           #ifndef DESTRUCTIVE_WRITEBACK
7574           branch_regs[i].dirty&=wont_dirty_i;
7575           #endif
7576           branch_regs[i].dirty|=will_dirty_i;
7577         }
7578       }
7579       else
7580       {
7581         // Internal branch
7582         if(ba[i]<=start+i*4) {
7583           // Backward branch
7584           if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
7585           {
7586             // Unconditional branch
7587             temp_will_dirty=0;
7588             temp_wont_dirty=0;
7589             // Merge in delay slot (will dirty)
7590             for(r=0;r<HOST_REGS;r++) {
7591               if(r!=EXCLUDE_REG) {
7592                 if((branch_regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7593                 if((branch_regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7594                 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7595                 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7596                 if((branch_regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7597                 if(branch_regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
7598                 if(branch_regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7599                 if((regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7600                 if((regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7601                 if((regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7602                 if((regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7603                 if((regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7604                 if(regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
7605                 if(regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7606               }
7607             }
7608           } else {
7609             // Conditional branch (not taken case)
7610             temp_will_dirty=will_dirty_next;
7611             temp_wont_dirty=wont_dirty_next;
7612             // Merge in delay slot (will dirty)
7613             for(r=0;r<HOST_REGS;r++) {
7614               if(r!=EXCLUDE_REG) {
7615                 if(!likely[i]) {
7616                   // Will not dirty if likely branch is not taken
7617                   if((branch_regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7618                   if((branch_regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7619                   if((branch_regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7620                   if((branch_regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7621                   if((branch_regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7622                   if(branch_regs[i].regmap[r]==0) temp_will_dirty&=~(1<<r);
7623                   if(branch_regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7624                   //if((regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7625                   //if((regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7626                   if((regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7627                   if((regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7628                   if((regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7629                   if(regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
7630                   if(regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7631                 }
7632               }
7633             }
7634           }
7635           // Merge in delay slot (wont dirty)
7636           for(r=0;r<HOST_REGS;r++) {
7637             if(r!=EXCLUDE_REG) {
7638               if((regs[i].regmap[r]&63)==rt1[i]) temp_wont_dirty|=1<<r;
7639               if((regs[i].regmap[r]&63)==rt2[i]) temp_wont_dirty|=1<<r;
7640               if((regs[i].regmap[r]&63)==rt1[i+1]) temp_wont_dirty|=1<<r;
7641               if((regs[i].regmap[r]&63)==rt2[i+1]) temp_wont_dirty|=1<<r;
7642               if(regs[i].regmap[r]==CCREG) temp_wont_dirty|=1<<r;
7643               if((branch_regs[i].regmap[r]&63)==rt1[i]) temp_wont_dirty|=1<<r;
7644               if((branch_regs[i].regmap[r]&63)==rt2[i]) temp_wont_dirty|=1<<r;
7645               if((branch_regs[i].regmap[r]&63)==rt1[i+1]) temp_wont_dirty|=1<<r;
7646               if((branch_regs[i].regmap[r]&63)==rt2[i+1]) temp_wont_dirty|=1<<r;
7647               if(branch_regs[i].regmap[r]==CCREG) temp_wont_dirty|=1<<r;
7648             }
7649           }
7650           // Deal with changed mappings
7651           if(i<iend) {
7652             for(r=0;r<HOST_REGS;r++) {
7653               if(r!=EXCLUDE_REG) {
7654                 if(regs[i].regmap[r]!=regmap_pre[i][r]) {
7655                   temp_will_dirty&=~(1<<r);
7656                   temp_wont_dirty&=~(1<<r);
7657                   if((regmap_pre[i][r]&63)>0 && (regmap_pre[i][r]&63)<34) {
7658                     temp_will_dirty|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7659                     temp_wont_dirty|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7660                   } else {
7661                     temp_will_dirty|=1<<r;
7662                     temp_wont_dirty|=1<<r;
7663                   }
7664                 }
7665               }
7666             }
7667           }
7668           if(wr) {
7669             will_dirty[i]=temp_will_dirty;
7670             wont_dirty[i]=temp_wont_dirty;
7671             clean_registers((ba[i]-start)>>2,i-1,0);
7672           }else{
7673             // Limit recursion.  It can take an excessive amount
7674             // of time if there are a lot of nested loops.
7675             will_dirty[(ba[i]-start)>>2]=0;
7676             wont_dirty[(ba[i]-start)>>2]=-1;
7677           }
7678         }
7679         /*else*/ if(1)
7680         {
7681           if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
7682           {
7683             // Unconditional branch
7684             will_dirty_i=0;
7685             wont_dirty_i=0;
7686           //if(ba[i]>start+i*4) { // Disable recursion (for debugging)
7687             for(r=0;r<HOST_REGS;r++) {
7688               if(r!=EXCLUDE_REG) {
7689                 if(branch_regs[i].regmap[r]==regs[(ba[i]-start)>>2].regmap_entry[r]) {
7690                   will_dirty_i|=will_dirty[(ba[i]-start)>>2]&(1<<r);
7691                   wont_dirty_i|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
7692                 }
7693                 if(branch_regs[i].regmap[r]>=0) {
7694                   will_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>(branch_regs[i].regmap[r]&63))&1)<<r;
7695                   wont_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>(branch_regs[i].regmap[r]&63))&1)<<r;
7696                 }
7697               }
7698             }
7699           //}
7700             // Merge in delay slot
7701             for(r=0;r<HOST_REGS;r++) {
7702               if(r!=EXCLUDE_REG) {
7703                 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7704                 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7705                 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7706                 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7707                 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7708                 if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7709                 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7710                 if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7711                 if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7712                 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7713                 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7714                 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7715                 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7716                 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7717               }
7718             }
7719           } else {
7720             // Conditional branch
7721             will_dirty_i=will_dirty_next;
7722             wont_dirty_i=wont_dirty_next;
7723           //if(ba[i]>start+i*4) { // Disable recursion (for debugging)
7724             for(r=0;r<HOST_REGS;r++) {
7725               if(r!=EXCLUDE_REG) {
7726                 signed char target_reg=branch_regs[i].regmap[r];
7727                 if(target_reg==regs[(ba[i]-start)>>2].regmap_entry[r]) {
7728                   will_dirty_i&=will_dirty[(ba[i]-start)>>2]&(1<<r);
7729                   wont_dirty_i|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
7730                 }
7731                 else if(target_reg>=0) {
7732                   will_dirty_i&=((unneeded_reg[(ba[i]-start)>>2]>>(target_reg&63))&1)<<r;
7733                   wont_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>(target_reg&63))&1)<<r;
7734                 }
7735                 // Treat delay slot as part of branch too
7736                 /*if(regs[i+1].regmap[r]==regs[(ba[i]-start)>>2].regmap_entry[r]) {
7737                   will_dirty[i+1]&=will_dirty[(ba[i]-start)>>2]&(1<<r);
7738                   wont_dirty[i+1]|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
7739                 }
7740                 else
7741                 {
7742                   will_dirty[i+1]&=~(1<<r);
7743                 }*/
7744               }
7745             }
7746           //}
7747             // Merge in delay slot
7748             for(r=0;r<HOST_REGS;r++) {
7749               if(r!=EXCLUDE_REG) {
7750                 if(!likely[i]) {
7751                   // Might not dirty if likely branch is not taken
7752                   if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7753                   if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7754                   if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7755                   if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7756                   if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7757                   if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7758                   if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7759                   //if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7760                   //if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7761                   if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7762                   if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7763                   if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7764                   if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7765                   if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7766                 }
7767               }
7768             }
7769           }
7770           // Merge in delay slot (won't dirty)
7771           for(r=0;r<HOST_REGS;r++) {
7772             if(r!=EXCLUDE_REG) {
7773               if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7774               if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7775               if((regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7776               if((regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7777               if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7778               if((branch_regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7779               if((branch_regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7780               if((branch_regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7781               if((branch_regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7782               if(branch_regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7783             }
7784           }
7785           if(wr) {
7786             #ifndef DESTRUCTIVE_WRITEBACK
7787             branch_regs[i].dirty&=wont_dirty_i;
7788             #endif
7789             branch_regs[i].dirty|=will_dirty_i;
7790           }
7791         }
7792       }
7793     }
7794     else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
7795     {
7796       // SYSCALL instruction (software interrupt)
7797       will_dirty_i=0;
7798       wont_dirty_i=0;
7799     }
7800     else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
7801     {
7802       // ERET instruction (return from interrupt)
7803       will_dirty_i=0;
7804       wont_dirty_i=0;
7805     }
7806     will_dirty_next=will_dirty_i;
7807     wont_dirty_next=wont_dirty_i;
7808     for(r=0;r<HOST_REGS;r++) {
7809       if(r!=EXCLUDE_REG) {
7810         if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7811         if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7812         if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7813         if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7814         if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7815         if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7816         if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7817         if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7818         if(i>istart) {
7819           if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=FJUMP)
7820           {
7821             // Don't store a register immediately after writing it,
7822             // may prevent dual-issue.
7823             if((regs[i].regmap[r]&63)==rt1[i-1]) wont_dirty_i|=1<<r;
7824             if((regs[i].regmap[r]&63)==rt2[i-1]) wont_dirty_i|=1<<r;
7825           }
7826         }
7827       }
7828     }
7829     // Save it
7830     will_dirty[i]=will_dirty_i;
7831     wont_dirty[i]=wont_dirty_i;
7832     // Mark registers that won't be dirtied as not dirty
7833     if(wr) {
7834       /*printf("wr (%d,%d) %x will:",istart,iend,start+i*4);
7835       for(r=0;r<HOST_REGS;r++) {
7836         if((will_dirty_i>>r)&1) {
7837           printf(" r%d",r);
7838         }
7839       }
7840       printf("\n");*/
7841
7842       //if(i==istart||(itype[i-1]!=RJUMP&&itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=FJUMP)) {
7843         regs[i].dirty|=will_dirty_i;
7844         #ifndef DESTRUCTIVE_WRITEBACK
7845         regs[i].dirty&=wont_dirty_i;
7846         if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
7847         {
7848           if(i<iend-1&&itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000) {
7849             for(r=0;r<HOST_REGS;r++) {
7850               if(r!=EXCLUDE_REG) {
7851                 if(regs[i].regmap[r]==regmap_pre[i+2][r]) {
7852                   regs[i+2].wasdirty&=wont_dirty_i|~(1<<r);
7853                 }else {/*printf("i: %x (%d) mismatch(+2): %d\n",start+i*4,i,r);/*assert(!((wont_dirty_i>>r)&1));*/}
7854               }
7855             }
7856           }
7857         }
7858         else
7859         {
7860           if(i<iend) {
7861             for(r=0;r<HOST_REGS;r++) {
7862               if(r!=EXCLUDE_REG) {
7863                 if(regs[i].regmap[r]==regmap_pre[i+1][r]) {
7864                   regs[i+1].wasdirty&=wont_dirty_i|~(1<<r);
7865                 }else {/*printf("i: %x (%d) mismatch(+1): %d\n",start+i*4,i,r);/*assert(!((wont_dirty_i>>r)&1));*/}
7866               }
7867             }
7868           }
7869         }
7870         #endif
7871       //}
7872     }
7873     // Deal with changed mappings
7874     temp_will_dirty=will_dirty_i;
7875     temp_wont_dirty=wont_dirty_i;
7876     for(r=0;r<HOST_REGS;r++) {
7877       if(r!=EXCLUDE_REG) {
7878         int nr;
7879         if(regs[i].regmap[r]==regmap_pre[i][r]) {
7880           if(wr) {
7881             #ifndef DESTRUCTIVE_WRITEBACK
7882             regs[i].wasdirty&=wont_dirty_i|~(1<<r);
7883             #endif
7884             regs[i].wasdirty|=will_dirty_i&(1<<r);
7885           }
7886         }
7887         else if(regmap_pre[i][r]>=0&&(nr=get_reg(regs[i].regmap,regmap_pre[i][r]))>=0) {
7888           // Register moved to a different register
7889           will_dirty_i&=~(1<<r);
7890           wont_dirty_i&=~(1<<r);
7891           will_dirty_i|=((temp_will_dirty>>nr)&1)<<r;
7892           wont_dirty_i|=((temp_wont_dirty>>nr)&1)<<r;
7893           if(wr) {
7894             #ifndef DESTRUCTIVE_WRITEBACK
7895             regs[i].wasdirty&=wont_dirty_i|~(1<<r);
7896             #endif
7897             regs[i].wasdirty|=will_dirty_i&(1<<r);
7898           }
7899         }
7900         else {
7901           will_dirty_i&=~(1<<r);
7902           wont_dirty_i&=~(1<<r);
7903           if((regmap_pre[i][r]&63)>0 && (regmap_pre[i][r]&63)<34) {
7904             will_dirty_i|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7905             wont_dirty_i|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7906           } else {
7907             wont_dirty_i|=1<<r;
7908             /*printf("i: %x (%d) mismatch: %d\n",start+i*4,i,r);/*assert(!((will_dirty>>r)&1));*/
7909           }
7910         }
7911       }
7912     }
7913   }
7914 }
7915
7916 #ifdef DISASM
7917   /* disassembly */
7918 void disassemble_inst(int i)
7919 {
7920     if (bt[i]) printf("*"); else printf(" ");
7921     switch(itype[i]) {
7922       case UJUMP:
7923         printf (" %x: %s %8x\n",start+i*4,insn[i],ba[i]);break;
7924       case CJUMP:
7925         printf (" %x: %s r%d,r%d,%8x\n",start+i*4,insn[i],rs1[i],rs2[i],i?start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14):*ba);break;
7926       case SJUMP:
7927         printf (" %x: %s r%d,%8x\n",start+i*4,insn[i],rs1[i],start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14));break;
7928       case FJUMP:
7929         printf (" %x: %s %8x\n",start+i*4,insn[i],ba[i]);break;
7930       case RJUMP:
7931         if (opcode[i]==0x9&&rt1[i]!=31)
7932           printf (" %x: %s r%d,r%d\n",start+i*4,insn[i],rt1[i],rs1[i]);
7933         else
7934           printf (" %x: %s r%d\n",start+i*4,insn[i],rs1[i]);
7935         break;
7936       case SPAN:
7937         printf (" %x: %s (pagespan) r%d,r%d,%8x\n",start+i*4,insn[i],rs1[i],rs2[i],ba[i]);break;
7938       case IMM16:
7939         if(opcode[i]==0xf) //LUI
7940           printf (" %x: %s r%d,%4x0000\n",start+i*4,insn[i],rt1[i],imm[i]&0xffff);
7941         else
7942           printf (" %x: %s r%d,r%d,%d\n",start+i*4,insn[i],rt1[i],rs1[i],imm[i]);
7943         break;
7944       case LOAD:
7945       case LOADLR:
7946         printf (" %x: %s r%d,r%d+%x\n",start+i*4,insn[i],rt1[i],rs1[i],imm[i]);
7947         break;
7948       case STORE:
7949       case STORELR:
7950         printf (" %x: %s r%d,r%d+%x\n",start+i*4,insn[i],rs2[i],rs1[i],imm[i]);
7951         break;
7952       case ALU:
7953       case SHIFT:
7954         printf (" %x: %s r%d,r%d,r%d\n",start+i*4,insn[i],rt1[i],rs1[i],rs2[i]);
7955         break;
7956       case MULTDIV:
7957         printf (" %x: %s r%d,r%d\n",start+i*4,insn[i],rs1[i],rs2[i]);
7958         break;
7959       case SHIFTIMM:
7960         printf (" %x: %s r%d,r%d,%d\n",start+i*4,insn[i],rt1[i],rs1[i],imm[i]);
7961         break;
7962       case MOV:
7963         if((opcode2[i]&0x1d)==0x10)
7964           printf (" %x: %s r%d\n",start+i*4,insn[i],rt1[i]);
7965         else if((opcode2[i]&0x1d)==0x11)
7966           printf (" %x: %s r%d\n",start+i*4,insn[i],rs1[i]);
7967         else
7968           printf (" %x: %s\n",start+i*4,insn[i]);
7969         break;
7970       case COP0:
7971         if(opcode2[i]==0)
7972           printf (" %x: %s r%d,cpr0[%d]\n",start+i*4,insn[i],rt1[i],(source[i]>>11)&0x1f); // MFC0
7973         else if(opcode2[i]==4)
7974           printf (" %x: %s r%d,cpr0[%d]\n",start+i*4,insn[i],rs1[i],(source[i]>>11)&0x1f); // MTC0
7975         else printf (" %x: %s\n",start+i*4,insn[i]);
7976         break;
7977       case COP1:
7978         if(opcode2[i]<3)
7979           printf (" %x: %s r%d,cpr1[%d]\n",start+i*4,insn[i],rt1[i],(source[i]>>11)&0x1f); // MFC1
7980         else if(opcode2[i]>3)
7981           printf (" %x: %s r%d,cpr1[%d]\n",start+i*4,insn[i],rs1[i],(source[i]>>11)&0x1f); // MTC1
7982         else printf (" %x: %s\n",start+i*4,insn[i]);
7983         break;
7984       case COP2:
7985         if(opcode2[i]<3)
7986           printf (" %x: %s r%d,cpr2[%d]\n",start+i*4,insn[i],rt1[i],(source[i]>>11)&0x1f); // MFC2
7987         else if(opcode2[i]>3)
7988           printf (" %x: %s r%d,cpr2[%d]\n",start+i*4,insn[i],rs1[i],(source[i]>>11)&0x1f); // MTC2
7989         else printf (" %x: %s\n",start+i*4,insn[i]);
7990         break;
7991       case C1LS:
7992         printf (" %x: %s cpr1[%d],r%d+%x\n",start+i*4,insn[i],(source[i]>>16)&0x1f,rs1[i],imm[i]);
7993         break;
7994       case C2LS:
7995         printf (" %x: %s cpr2[%d],r%d+%x\n",start+i*4,insn[i],(source[i]>>16)&0x1f,rs1[i],imm[i]);
7996         break;
7997       case INTCALL:
7998         printf (" %x: %s (INTCALL)\n",start+i*4,insn[i]);
7999         break;
8000       default:
8001         //printf (" %s %8x\n",insn[i],source[i]);
8002         printf (" %x: %s\n",start+i*4,insn[i]);
8003     }
8004 }
8005 #else
8006 static void disassemble_inst(int i) {}
8007 #endif // DISASM
8008
8009 #define DRC_TEST_VAL 0x74657374
8010
8011 static int new_dynarec_test(void)
8012 {
8013   int (*testfunc)(void) = (void *)out;
8014   int ret;
8015   emit_movimm(DRC_TEST_VAL,0); // test
8016   emit_jmpreg(14);
8017   literal_pool(0);
8018 #ifdef __arm__
8019   __clear_cache((void *)testfunc, out);
8020 #endif
8021   SysPrintf("testing if we can run recompiled code..\n");
8022   ret = testfunc();
8023   if (ret == DRC_TEST_VAL)
8024     SysPrintf("test passed.\n");
8025   else
8026     SysPrintf("test failed: %08x\n", ret);
8027   out=(u_char *)BASE_ADDR;
8028   return ret == DRC_TEST_VAL;
8029 }
8030
8031 // clear the state completely, instead of just marking
8032 // things invalid like invalidate_all_pages() does
8033 void new_dynarec_clear_full()
8034 {
8035   int n;
8036   out=(u_char *)BASE_ADDR;
8037   memset(invalid_code,1,sizeof(invalid_code));
8038   memset(hash_table,0xff,sizeof(hash_table));
8039   memset(mini_ht,-1,sizeof(mini_ht));
8040   memset(restore_candidate,0,sizeof(restore_candidate));
8041   memset(shadow,0,sizeof(shadow));
8042   copy=shadow;
8043   expirep=16384; // Expiry pointer, +2 blocks
8044   pending_exception=0;
8045   literalcount=0;
8046   stop_after_jal=0;
8047   inv_code_start=inv_code_end=~0;
8048   // TLB
8049 #ifndef DISABLE_TLB
8050   using_tlb=0;
8051   for(n=0;n<524288;n++) // 0 .. 0x7FFFFFFF
8052     memory_map[n]=-1;
8053   for(n=524288;n<526336;n++) // 0x80000000 .. 0x807FFFFF
8054     memory_map[n]=((u_int)rdram-0x80000000)>>2;
8055   for(n=526336;n<1048576;n++) // 0x80800000 .. 0xFFFFFFFF
8056     memory_map[n]=-1;
8057 #endif
8058   for(n=0;n<4096;n++) ll_clear(jump_in+n);
8059   for(n=0;n<4096;n++) ll_clear(jump_out+n);
8060   for(n=0;n<4096;n++) ll_clear(jump_dirty+n);
8061 }
8062
8063 void new_dynarec_init()
8064 {
8065   SysPrintf("Init new dynarec\n");
8066   out=(u_char *)BASE_ADDR;
8067 #if BASE_ADDR_FIXED
8068   if (mmap (out, 1<<TARGET_SIZE_2,
8069             PROT_READ | PROT_WRITE | PROT_EXEC,
8070             MAP_FIXED | MAP_PRIVATE | MAP_ANONYMOUS,
8071             -1, 0) <= 0) {
8072     SysPrintf("mmap() failed: %s\n", strerror(errno));
8073   }
8074 #else
8075   // not all systems allow execute in data segment by default
8076   if (mprotect(out, 1<<TARGET_SIZE_2, PROT_READ | PROT_WRITE | PROT_EXEC) != 0)
8077     SysPrintf("mprotect() failed: %s\n", strerror(errno));
8078 #endif
8079 #ifdef MUPEN64
8080   rdword=&readmem_dword;
8081   fake_pc.f.r.rs=&readmem_dword;
8082   fake_pc.f.r.rt=&readmem_dword;
8083   fake_pc.f.r.rd=&readmem_dword;
8084 #endif
8085   int n;
8086   cycle_multiplier=200;
8087   new_dynarec_clear_full();
8088 #ifdef HOST_IMM8
8089   // Copy this into local area so we don't have to put it in every literal pool
8090   invc_ptr=invalid_code;
8091 #endif
8092 #ifdef MUPEN64
8093   for(n=0;n<0x8000;n++) { // 0 .. 0x7FFFFFFF
8094     writemem[n] = write_nomem_new;
8095     writememb[n] = write_nomemb_new;
8096     writememh[n] = write_nomemh_new;
8097 #ifndef FORCE32
8098     writememd[n] = write_nomemd_new;
8099 #endif
8100     readmem[n] = read_nomem_new;
8101     readmemb[n] = read_nomemb_new;
8102     readmemh[n] = read_nomemh_new;
8103 #ifndef FORCE32
8104     readmemd[n] = read_nomemd_new;
8105 #endif
8106   }
8107   for(n=0x8000;n<0x8080;n++) { // 0x80000000 .. 0x807FFFFF
8108     writemem[n] = write_rdram_new;
8109     writememb[n] = write_rdramb_new;
8110     writememh[n] = write_rdramh_new;
8111 #ifndef FORCE32
8112     writememd[n] = write_rdramd_new;
8113 #endif
8114   }
8115   for(n=0xC000;n<0x10000;n++) { // 0xC0000000 .. 0xFFFFFFFF
8116     writemem[n] = write_nomem_new;
8117     writememb[n] = write_nomemb_new;
8118     writememh[n] = write_nomemh_new;
8119 #ifndef FORCE32
8120     writememd[n] = write_nomemd_new;
8121 #endif
8122     readmem[n] = read_nomem_new;
8123     readmemb[n] = read_nomemb_new;
8124     readmemh[n] = read_nomemh_new;
8125 #ifndef FORCE32
8126     readmemd[n] = read_nomemd_new;
8127 #endif
8128   }
8129 #endif
8130   tlb_hacks();
8131   arch_init();
8132   new_dynarec_test();
8133 #ifndef RAM_FIXED
8134   ram_offset=(u_int)rdram-0x80000000;
8135 #endif
8136   if (ram_offset!=0)
8137     SysPrintf("warning: RAM is not directly mapped, performance will suffer\n");
8138 }
8139
8140 void new_dynarec_cleanup()
8141 {
8142   int n;
8143   #if BASE_ADDR_FIXED
8144   if (munmap ((void *)BASE_ADDR, 1<<TARGET_SIZE_2) < 0) {SysPrintf("munmap() failed\n");}
8145   #endif
8146   for(n=0;n<4096;n++) ll_clear(jump_in+n);
8147   for(n=0;n<4096;n++) ll_clear(jump_out+n);
8148   for(n=0;n<4096;n++) ll_clear(jump_dirty+n);
8149   #ifdef ROM_COPY
8150   if (munmap (ROM_COPY, 67108864) < 0) {SysPrintf("munmap() failed\n");}
8151   #endif
8152 }
8153
8154 int new_recompile_block(int addr)
8155 {
8156 /*
8157   if(addr==0x800cd050) {
8158     int block;
8159     for(block=0x80000;block<0x80800;block++) invalidate_block(block);
8160     int n;
8161     for(n=0;n<=2048;n++) ll_clear(jump_dirty+n);
8162   }
8163 */
8164   //if(Count==365117028) tracedebug=1;
8165   assem_debug("NOTCOMPILED: addr = %x -> %x\n", (int)addr, (int)out);
8166   //printf("NOTCOMPILED: addr = %x -> %x\n", (int)addr, (int)out);
8167   //printf("TRACE: count=%d next=%d (compile %x)\n",Count,next_interupt,addr);
8168   //if(debug)
8169   //printf("TRACE: count=%d next=%d (checksum %x)\n",Count,next_interupt,mchecksum());
8170   //printf("fpu mapping=%x enabled=%x\n",(Status & 0x04000000)>>26,(Status & 0x20000000)>>29);
8171   /*if(Count>=312978186) {
8172     rlist();
8173   }*/
8174   //rlist();
8175   start = (u_int)addr&~3;
8176   //assert(((u_int)addr&1)==0);
8177   new_dynarec_did_compile=1;
8178 #ifdef PCSX
8179   if (Config.HLE && start == 0x80001000) // hlecall
8180   {
8181     // XXX: is this enough? Maybe check hleSoftCall?
8182     u_int beginning=(u_int)out;
8183     u_int page=get_page(start);
8184     invalid_code[start>>12]=0;
8185     emit_movimm(start,0);
8186     emit_writeword(0,(int)&pcaddr);
8187     emit_jmp((int)new_dyna_leave);
8188     literal_pool(0);
8189 #ifdef __arm__
8190     __clear_cache((void *)beginning,out);
8191 #endif
8192     ll_add(jump_in+page,start,(void *)beginning);
8193     return 0;
8194   }
8195   else if ((u_int)addr < 0x00200000 ||
8196     (0xa0000000 <= addr && addr < 0xa0200000)) {
8197     // used for BIOS calls mostly?
8198     source = (u_int *)((u_int)rdram+(start&0x1fffff));
8199     pagelimit = (addr&0xa0000000)|0x00200000;
8200   }
8201   else if (!Config.HLE && (
8202 /*    (0x9fc00000 <= addr && addr < 0x9fc80000) ||*/
8203     (0xbfc00000 <= addr && addr < 0xbfc80000))) {
8204     // BIOS
8205     source = (u_int *)((u_int)psxR+(start&0x7ffff));
8206     pagelimit = (addr&0xfff00000)|0x80000;
8207   }
8208   else
8209 #endif
8210 #ifdef MUPEN64
8211   if ((int)addr >= 0xa4000000 && (int)addr < 0xa4001000) {
8212     source = (u_int *)((u_int)SP_DMEM+start-0xa4000000);
8213     pagelimit = 0xa4001000;
8214   }
8215   else
8216 #endif
8217   if ((int)addr >= 0x80000000 && (int)addr < 0x80000000+RAM_SIZE) {
8218     source = (u_int *)((u_int)rdram+start-0x80000000);
8219     pagelimit = 0x80000000+RAM_SIZE;
8220   }
8221 #ifndef DISABLE_TLB
8222   else if ((signed int)addr >= (signed int)0xC0000000) {
8223     //printf("addr=%x mm=%x\n",(u_int)addr,(memory_map[start>>12]<<2));
8224     //if(tlb_LUT_r[start>>12])
8225       //source = (u_int *)(((int)rdram)+(tlb_LUT_r[start>>12]&0xFFFFF000)+(((int)addr)&0xFFF)-0x80000000);
8226     if((signed int)memory_map[start>>12]>=0) {
8227       source = (u_int *)((u_int)(start+(memory_map[start>>12]<<2)));
8228       pagelimit=(start+4096)&0xFFFFF000;
8229       int map=memory_map[start>>12];
8230       int i;
8231       for(i=0;i<5;i++) {
8232         //printf("start: %x next: %x\n",map,memory_map[pagelimit>>12]);
8233         if((map&0xBFFFFFFF)==(memory_map[pagelimit>>12]&0xBFFFFFFF)) pagelimit+=4096;
8234       }
8235       assem_debug("pagelimit=%x\n",pagelimit);
8236       assem_debug("mapping=%x (%x)\n",memory_map[start>>12],(memory_map[start>>12]<<2)+start);
8237     }
8238     else {
8239       assem_debug("Compile at unmapped memory address: %x \n", (int)addr);
8240       //assem_debug("start: %x next: %x\n",memory_map[start>>12],memory_map[(start+4096)>>12]);
8241       return -1; // Caller will invoke exception handler
8242     }
8243     //printf("source= %x\n",(int)source);
8244   }
8245 #endif
8246   else {
8247     SysPrintf("Compile at bogus memory address: %x \n", (int)addr);
8248     exit(1);
8249   }
8250
8251   /* Pass 1: disassemble */
8252   /* Pass 2: register dependencies, branch targets */
8253   /* Pass 3: register allocation */
8254   /* Pass 4: branch dependencies */
8255   /* Pass 5: pre-alloc */
8256   /* Pass 6: optimize clean/dirty state */
8257   /* Pass 7: flag 32-bit registers */
8258   /* Pass 8: assembly */
8259   /* Pass 9: linker */
8260   /* Pass 10: garbage collection / free memory */
8261
8262   int i,j;
8263   int done=0;
8264   unsigned int type,op,op2;
8265
8266   //printf("addr = %x source = %x %x\n", addr,source,source[0]);
8267
8268   /* Pass 1 disassembly */
8269
8270   for(i=0;!done;i++) {
8271     bt[i]=0;likely[i]=0;ooo[i]=0;op2=0;
8272     minimum_free_regs[i]=0;
8273     opcode[i]=op=source[i]>>26;
8274     switch(op)
8275     {
8276       case 0x00: strcpy(insn[i],"special"); type=NI;
8277         op2=source[i]&0x3f;
8278         switch(op2)
8279         {
8280           case 0x00: strcpy(insn[i],"SLL"); type=SHIFTIMM; break;
8281           case 0x02: strcpy(insn[i],"SRL"); type=SHIFTIMM; break;
8282           case 0x03: strcpy(insn[i],"SRA"); type=SHIFTIMM; break;
8283           case 0x04: strcpy(insn[i],"SLLV"); type=SHIFT; break;
8284           case 0x06: strcpy(insn[i],"SRLV"); type=SHIFT; break;
8285           case 0x07: strcpy(insn[i],"SRAV"); type=SHIFT; break;
8286           case 0x08: strcpy(insn[i],"JR"); type=RJUMP; break;
8287           case 0x09: strcpy(insn[i],"JALR"); type=RJUMP; break;
8288           case 0x0C: strcpy(insn[i],"SYSCALL"); type=SYSCALL; break;
8289           case 0x0D: strcpy(insn[i],"BREAK"); type=OTHER; break;
8290           case 0x0F: strcpy(insn[i],"SYNC"); type=OTHER; break;
8291           case 0x10: strcpy(insn[i],"MFHI"); type=MOV; break;
8292           case 0x11: strcpy(insn[i],"MTHI"); type=MOV; break;
8293           case 0x12: strcpy(insn[i],"MFLO"); type=MOV; break;
8294           case 0x13: strcpy(insn[i],"MTLO"); type=MOV; break;
8295           case 0x18: strcpy(insn[i],"MULT"); type=MULTDIV; break;
8296           case 0x19: strcpy(insn[i],"MULTU"); type=MULTDIV; break;
8297           case 0x1A: strcpy(insn[i],"DIV"); type=MULTDIV; break;
8298           case 0x1B: strcpy(insn[i],"DIVU"); type=MULTDIV; break;
8299           case 0x20: strcpy(insn[i],"ADD"); type=ALU; break;
8300           case 0x21: strcpy(insn[i],"ADDU"); type=ALU; break;
8301           case 0x22: strcpy(insn[i],"SUB"); type=ALU; break;
8302           case 0x23: strcpy(insn[i],"SUBU"); type=ALU; break;
8303           case 0x24: strcpy(insn[i],"AND"); type=ALU; break;
8304           case 0x25: strcpy(insn[i],"OR"); type=ALU; break;
8305           case 0x26: strcpy(insn[i],"XOR"); type=ALU; break;
8306           case 0x27: strcpy(insn[i],"NOR"); type=ALU; break;
8307           case 0x2A: strcpy(insn[i],"SLT"); type=ALU; break;
8308           case 0x2B: strcpy(insn[i],"SLTU"); type=ALU; break;
8309           case 0x30: strcpy(insn[i],"TGE"); type=NI; break;
8310           case 0x31: strcpy(insn[i],"TGEU"); type=NI; break;
8311           case 0x32: strcpy(insn[i],"TLT"); type=NI; break;
8312           case 0x33: strcpy(insn[i],"TLTU"); type=NI; break;
8313           case 0x34: strcpy(insn[i],"TEQ"); type=NI; break;
8314           case 0x36: strcpy(insn[i],"TNE"); type=NI; break;
8315 #ifndef FORCE32
8316           case 0x14: strcpy(insn[i],"DSLLV"); type=SHIFT; break;
8317           case 0x16: strcpy(insn[i],"DSRLV"); type=SHIFT; break;
8318           case 0x17: strcpy(insn[i],"DSRAV"); type=SHIFT; break;
8319           case 0x1C: strcpy(insn[i],"DMULT"); type=MULTDIV; break;
8320           case 0x1D: strcpy(insn[i],"DMULTU"); type=MULTDIV; break;
8321           case 0x1E: strcpy(insn[i],"DDIV"); type=MULTDIV; break;
8322           case 0x1F: strcpy(insn[i],"DDIVU"); type=MULTDIV; break;
8323           case 0x2C: strcpy(insn[i],"DADD"); type=ALU; break;
8324           case 0x2D: strcpy(insn[i],"DADDU"); type=ALU; break;
8325           case 0x2E: strcpy(insn[i],"DSUB"); type=ALU; break;
8326           case 0x2F: strcpy(insn[i],"DSUBU"); type=ALU; break;
8327           case 0x38: strcpy(insn[i],"DSLL"); type=SHIFTIMM; break;
8328           case 0x3A: strcpy(insn[i],"DSRL"); type=SHIFTIMM; break;
8329           case 0x3B: strcpy(insn[i],"DSRA"); type=SHIFTIMM; break;
8330           case 0x3C: strcpy(insn[i],"DSLL32"); type=SHIFTIMM; break;
8331           case 0x3E: strcpy(insn[i],"DSRL32"); type=SHIFTIMM; break;
8332           case 0x3F: strcpy(insn[i],"DSRA32"); type=SHIFTIMM; break;
8333 #endif
8334         }
8335         break;
8336       case 0x01: strcpy(insn[i],"regimm"); type=NI;
8337         op2=(source[i]>>16)&0x1f;
8338         switch(op2)
8339         {
8340           case 0x00: strcpy(insn[i],"BLTZ"); type=SJUMP; break;
8341           case 0x01: strcpy(insn[i],"BGEZ"); type=SJUMP; break;
8342           case 0x02: strcpy(insn[i],"BLTZL"); type=SJUMP; break;
8343           case 0x03: strcpy(insn[i],"BGEZL"); type=SJUMP; break;
8344           case 0x08: strcpy(insn[i],"TGEI"); type=NI; break;
8345           case 0x09: strcpy(insn[i],"TGEIU"); type=NI; break;
8346           case 0x0A: strcpy(insn[i],"TLTI"); type=NI; break;
8347           case 0x0B: strcpy(insn[i],"TLTIU"); type=NI; break;
8348           case 0x0C: strcpy(insn[i],"TEQI"); type=NI; break;
8349           case 0x0E: strcpy(insn[i],"TNEI"); type=NI; break;
8350           case 0x10: strcpy(insn[i],"BLTZAL"); type=SJUMP; break;
8351           case 0x11: strcpy(insn[i],"BGEZAL"); type=SJUMP; break;
8352           case 0x12: strcpy(insn[i],"BLTZALL"); type=SJUMP; break;
8353           case 0x13: strcpy(insn[i],"BGEZALL"); type=SJUMP; break;
8354         }
8355         break;
8356       case 0x02: strcpy(insn[i],"J"); type=UJUMP; break;
8357       case 0x03: strcpy(insn[i],"JAL"); type=UJUMP; break;
8358       case 0x04: strcpy(insn[i],"BEQ"); type=CJUMP; break;
8359       case 0x05: strcpy(insn[i],"BNE"); type=CJUMP; break;
8360       case 0x06: strcpy(insn[i],"BLEZ"); type=CJUMP; break;
8361       case 0x07: strcpy(insn[i],"BGTZ"); type=CJUMP; break;
8362       case 0x08: strcpy(insn[i],"ADDI"); type=IMM16; break;
8363       case 0x09: strcpy(insn[i],"ADDIU"); type=IMM16; break;
8364       case 0x0A: strcpy(insn[i],"SLTI"); type=IMM16; break;
8365       case 0x0B: strcpy(insn[i],"SLTIU"); type=IMM16; break;
8366       case 0x0C: strcpy(insn[i],"ANDI"); type=IMM16; break;
8367       case 0x0D: strcpy(insn[i],"ORI"); type=IMM16; break;
8368       case 0x0E: strcpy(insn[i],"XORI"); type=IMM16; break;
8369       case 0x0F: strcpy(insn[i],"LUI"); type=IMM16; break;
8370       case 0x10: strcpy(insn[i],"cop0"); type=NI;
8371         op2=(source[i]>>21)&0x1f;
8372         switch(op2)
8373         {
8374           case 0x00: strcpy(insn[i],"MFC0"); type=COP0; break;
8375           case 0x04: strcpy(insn[i],"MTC0"); type=COP0; break;
8376           case 0x10: strcpy(insn[i],"tlb"); type=NI;
8377           switch(source[i]&0x3f)
8378           {
8379             case 0x01: strcpy(insn[i],"TLBR"); type=COP0; break;
8380             case 0x02: strcpy(insn[i],"TLBWI"); type=COP0; break;
8381             case 0x06: strcpy(insn[i],"TLBWR"); type=COP0; break;
8382             case 0x08: strcpy(insn[i],"TLBP"); type=COP0; break;
8383 #ifdef PCSX
8384             case 0x10: strcpy(insn[i],"RFE"); type=COP0; break;
8385 #else
8386             case 0x18: strcpy(insn[i],"ERET"); type=COP0; break;
8387 #endif
8388           }
8389         }
8390         break;
8391       case 0x11: strcpy(insn[i],"cop1"); type=NI;
8392         op2=(source[i]>>21)&0x1f;
8393         switch(op2)
8394         {
8395           case 0x00: strcpy(insn[i],"MFC1"); type=COP1; break;
8396           case 0x01: strcpy(insn[i],"DMFC1"); type=COP1; break;
8397           case 0x02: strcpy(insn[i],"CFC1"); type=COP1; break;
8398           case 0x04: strcpy(insn[i],"MTC1"); type=COP1; break;
8399           case 0x05: strcpy(insn[i],"DMTC1"); type=COP1; break;
8400           case 0x06: strcpy(insn[i],"CTC1"); type=COP1; break;
8401           case 0x08: strcpy(insn[i],"BC1"); type=FJUMP;
8402           switch((source[i]>>16)&0x3)
8403           {
8404             case 0x00: strcpy(insn[i],"BC1F"); break;
8405             case 0x01: strcpy(insn[i],"BC1T"); break;
8406             case 0x02: strcpy(insn[i],"BC1FL"); break;
8407             case 0x03: strcpy(insn[i],"BC1TL"); break;
8408           }
8409           break;
8410           case 0x10: strcpy(insn[i],"C1.S"); type=NI;
8411           switch(source[i]&0x3f)
8412           {
8413             case 0x00: strcpy(insn[i],"ADD.S"); type=FLOAT; break;
8414             case 0x01: strcpy(insn[i],"SUB.S"); type=FLOAT; break;
8415             case 0x02: strcpy(insn[i],"MUL.S"); type=FLOAT; break;
8416             case 0x03: strcpy(insn[i],"DIV.S"); type=FLOAT; break;
8417             case 0x04: strcpy(insn[i],"SQRT.S"); type=FLOAT; break;
8418             case 0x05: strcpy(insn[i],"ABS.S"); type=FLOAT; break;
8419             case 0x06: strcpy(insn[i],"MOV.S"); type=FLOAT; break;
8420             case 0x07: strcpy(insn[i],"NEG.S"); type=FLOAT; break;
8421             case 0x08: strcpy(insn[i],"ROUND.L.S"); type=FCONV; break;
8422             case 0x09: strcpy(insn[i],"TRUNC.L.S"); type=FCONV; break;
8423             case 0x0A: strcpy(insn[i],"CEIL.L.S"); type=FCONV; break;
8424             case 0x0B: strcpy(insn[i],"FLOOR.L.S"); type=FCONV; break;
8425             case 0x0C: strcpy(insn[i],"ROUND.W.S"); type=FCONV; break;
8426             case 0x0D: strcpy(insn[i],"TRUNC.W.S"); type=FCONV; break;
8427             case 0x0E: strcpy(insn[i],"CEIL.W.S"); type=FCONV; break;
8428             case 0x0F: strcpy(insn[i],"FLOOR.W.S"); type=FCONV; break;
8429             case 0x21: strcpy(insn[i],"CVT.D.S"); type=FCONV; break;
8430             case 0x24: strcpy(insn[i],"CVT.W.S"); type=FCONV; break;
8431             case 0x25: strcpy(insn[i],"CVT.L.S"); type=FCONV; break;
8432             case 0x30: strcpy(insn[i],"C.F.S"); type=FCOMP; break;
8433             case 0x31: strcpy(insn[i],"C.UN.S"); type=FCOMP; break;
8434             case 0x32: strcpy(insn[i],"C.EQ.S"); type=FCOMP; break;
8435             case 0x33: strcpy(insn[i],"C.UEQ.S"); type=FCOMP; break;
8436             case 0x34: strcpy(insn[i],"C.OLT.S"); type=FCOMP; break;
8437             case 0x35: strcpy(insn[i],"C.ULT.S"); type=FCOMP; break;
8438             case 0x36: strcpy(insn[i],"C.OLE.S"); type=FCOMP; break;
8439             case 0x37: strcpy(insn[i],"C.ULE.S"); type=FCOMP; break;
8440             case 0x38: strcpy(insn[i],"C.SF.S"); type=FCOMP; break;
8441             case 0x39: strcpy(insn[i],"C.NGLE.S"); type=FCOMP; break;
8442             case 0x3A: strcpy(insn[i],"C.SEQ.S"); type=FCOMP; break;
8443             case 0x3B: strcpy(insn[i],"C.NGL.S"); type=FCOMP; break;
8444             case 0x3C: strcpy(insn[i],"C.LT.S"); type=FCOMP; break;
8445             case 0x3D: strcpy(insn[i],"C.NGE.S"); type=FCOMP; break;
8446             case 0x3E: strcpy(insn[i],"C.LE.S"); type=FCOMP; break;
8447             case 0x3F: strcpy(insn[i],"C.NGT.S"); type=FCOMP; break;
8448           }
8449           break;
8450           case 0x11: strcpy(insn[i],"C1.D"); type=NI;
8451           switch(source[i]&0x3f)
8452           {
8453             case 0x00: strcpy(insn[i],"ADD.D"); type=FLOAT; break;
8454             case 0x01: strcpy(insn[i],"SUB.D"); type=FLOAT; break;
8455             case 0x02: strcpy(insn[i],"MUL.D"); type=FLOAT; break;
8456             case 0x03: strcpy(insn[i],"DIV.D"); type=FLOAT; break;
8457             case 0x04: strcpy(insn[i],"SQRT.D"); type=FLOAT; break;
8458             case 0x05: strcpy(insn[i],"ABS.D"); type=FLOAT; break;
8459             case 0x06: strcpy(insn[i],"MOV.D"); type=FLOAT; break;
8460             case 0x07: strcpy(insn[i],"NEG.D"); type=FLOAT; break;
8461             case 0x08: strcpy(insn[i],"ROUND.L.D"); type=FCONV; break;
8462             case 0x09: strcpy(insn[i],"TRUNC.L.D"); type=FCONV; break;
8463             case 0x0A: strcpy(insn[i],"CEIL.L.D"); type=FCONV; break;
8464             case 0x0B: strcpy(insn[i],"FLOOR.L.D"); type=FCONV; break;
8465             case 0x0C: strcpy(insn[i],"ROUND.W.D"); type=FCONV; break;
8466             case 0x0D: strcpy(insn[i],"TRUNC.W.D"); type=FCONV; break;
8467             case 0x0E: strcpy(insn[i],"CEIL.W.D"); type=FCONV; break;
8468             case 0x0F: strcpy(insn[i],"FLOOR.W.D"); type=FCONV; break;
8469             case 0x20: strcpy(insn[i],"CVT.S.D"); type=FCONV; break;
8470             case 0x24: strcpy(insn[i],"CVT.W.D"); type=FCONV; break;
8471             case 0x25: strcpy(insn[i],"CVT.L.D"); type=FCONV; break;
8472             case 0x30: strcpy(insn[i],"C.F.D"); type=FCOMP; break;
8473             case 0x31: strcpy(insn[i],"C.UN.D"); type=FCOMP; break;
8474             case 0x32: strcpy(insn[i],"C.EQ.D"); type=FCOMP; break;
8475             case 0x33: strcpy(insn[i],"C.UEQ.D"); type=FCOMP; break;
8476             case 0x34: strcpy(insn[i],"C.OLT.D"); type=FCOMP; break;
8477             case 0x35: strcpy(insn[i],"C.ULT.D"); type=FCOMP; break;
8478             case 0x36: strcpy(insn[i],"C.OLE.D"); type=FCOMP; break;
8479             case 0x37: strcpy(insn[i],"C.ULE.D"); type=FCOMP; break;
8480             case 0x38: strcpy(insn[i],"C.SF.D"); type=FCOMP; break;
8481             case 0x39: strcpy(insn[i],"C.NGLE.D"); type=FCOMP; break;
8482             case 0x3A: strcpy(insn[i],"C.SEQ.D"); type=FCOMP; break;
8483             case 0x3B: strcpy(insn[i],"C.NGL.D"); type=FCOMP; break;
8484             case 0x3C: strcpy(insn[i],"C.LT.D"); type=FCOMP; break;
8485             case 0x3D: strcpy(insn[i],"C.NGE.D"); type=FCOMP; break;
8486             case 0x3E: strcpy(insn[i],"C.LE.D"); type=FCOMP; break;
8487             case 0x3F: strcpy(insn[i],"C.NGT.D"); type=FCOMP; break;
8488           }
8489           break;
8490           case 0x14: strcpy(insn[i],"C1.W"); type=NI;
8491           switch(source[i]&0x3f)
8492           {
8493             case 0x20: strcpy(insn[i],"CVT.S.W"); type=FCONV; break;
8494             case 0x21: strcpy(insn[i],"CVT.D.W"); type=FCONV; break;
8495           }
8496           break;
8497           case 0x15: strcpy(insn[i],"C1.L"); type=NI;
8498           switch(source[i]&0x3f)
8499           {
8500             case 0x20: strcpy(insn[i],"CVT.S.L"); type=FCONV; break;
8501             case 0x21: strcpy(insn[i],"CVT.D.L"); type=FCONV; break;
8502           }
8503           break;
8504         }
8505         break;
8506 #ifndef FORCE32
8507       case 0x14: strcpy(insn[i],"BEQL"); type=CJUMP; break;
8508       case 0x15: strcpy(insn[i],"BNEL"); type=CJUMP; break;
8509       case 0x16: strcpy(insn[i],"BLEZL"); type=CJUMP; break;
8510       case 0x17: strcpy(insn[i],"BGTZL"); type=CJUMP; break;
8511       case 0x18: strcpy(insn[i],"DADDI"); type=IMM16; break;
8512       case 0x19: strcpy(insn[i],"DADDIU"); type=IMM16; break;
8513       case 0x1A: strcpy(insn[i],"LDL"); type=LOADLR; break;
8514       case 0x1B: strcpy(insn[i],"LDR"); type=LOADLR; break;
8515 #endif
8516       case 0x20: strcpy(insn[i],"LB"); type=LOAD; break;
8517       case 0x21: strcpy(insn[i],"LH"); type=LOAD; break;
8518       case 0x22: strcpy(insn[i],"LWL"); type=LOADLR; break;
8519       case 0x23: strcpy(insn[i],"LW"); type=LOAD; break;
8520       case 0x24: strcpy(insn[i],"LBU"); type=LOAD; break;
8521       case 0x25: strcpy(insn[i],"LHU"); type=LOAD; break;
8522       case 0x26: strcpy(insn[i],"LWR"); type=LOADLR; break;
8523 #ifndef FORCE32
8524       case 0x27: strcpy(insn[i],"LWU"); type=LOAD; break;
8525 #endif
8526       case 0x28: strcpy(insn[i],"SB"); type=STORE; break;
8527       case 0x29: strcpy(insn[i],"SH"); type=STORE; break;
8528       case 0x2A: strcpy(insn[i],"SWL"); type=STORELR; break;
8529       case 0x2B: strcpy(insn[i],"SW"); type=STORE; break;
8530 #ifndef FORCE32
8531       case 0x2C: strcpy(insn[i],"SDL"); type=STORELR; break;
8532       case 0x2D: strcpy(insn[i],"SDR"); type=STORELR; break;
8533 #endif
8534       case 0x2E: strcpy(insn[i],"SWR"); type=STORELR; break;
8535       case 0x2F: strcpy(insn[i],"CACHE"); type=NOP; break;
8536       case 0x30: strcpy(insn[i],"LL"); type=NI; break;
8537       case 0x31: strcpy(insn[i],"LWC1"); type=C1LS; break;
8538 #ifndef FORCE32
8539       case 0x34: strcpy(insn[i],"LLD"); type=NI; break;
8540       case 0x35: strcpy(insn[i],"LDC1"); type=C1LS; break;
8541       case 0x37: strcpy(insn[i],"LD"); type=LOAD; break;
8542 #endif
8543       case 0x38: strcpy(insn[i],"SC"); type=NI; break;
8544       case 0x39: strcpy(insn[i],"SWC1"); type=C1LS; break;
8545 #ifndef FORCE32
8546       case 0x3C: strcpy(insn[i],"SCD"); type=NI; break;
8547       case 0x3D: strcpy(insn[i],"SDC1"); type=C1LS; break;
8548       case 0x3F: strcpy(insn[i],"SD"); type=STORE; break;
8549 #endif
8550 #ifdef PCSX
8551       case 0x12: strcpy(insn[i],"COP2"); type=NI;
8552         op2=(source[i]>>21)&0x1f;
8553         //if (op2 & 0x10) {
8554         if (source[i]&0x3f) { // use this hack to support old savestates with patched gte insns
8555           if (gte_handlers[source[i]&0x3f]!=NULL) {
8556             if (gte_regnames[source[i]&0x3f]!=NULL)
8557               strcpy(insn[i],gte_regnames[source[i]&0x3f]);
8558             else
8559               snprintf(insn[i], sizeof(insn[i]), "COP2 %x", source[i]&0x3f);
8560             type=C2OP;
8561           }
8562         }
8563         else switch(op2)
8564         {
8565           case 0x00: strcpy(insn[i],"MFC2"); type=COP2; break;
8566           case 0x02: strcpy(insn[i],"CFC2"); type=COP2; break;
8567           case 0x04: strcpy(insn[i],"MTC2"); type=COP2; break;
8568           case 0x06: strcpy(insn[i],"CTC2"); type=COP2; break;
8569         }
8570         break;
8571       case 0x32: strcpy(insn[i],"LWC2"); type=C2LS; break;
8572       case 0x3A: strcpy(insn[i],"SWC2"); type=C2LS; break;
8573       case 0x3B: strcpy(insn[i],"HLECALL"); type=HLECALL; break;
8574 #endif
8575       default: strcpy(insn[i],"???"); type=NI;
8576         SysPrintf("NI %08x @%08x (%08x)\n", source[i], addr + i*4, addr);
8577         break;
8578     }
8579     itype[i]=type;
8580     opcode2[i]=op2;
8581     /* Get registers/immediates */
8582     lt1[i]=0;
8583     us1[i]=0;
8584     us2[i]=0;
8585     dep1[i]=0;
8586     dep2[i]=0;
8587     gte_rs[i]=gte_rt[i]=0;
8588     switch(type) {
8589       case LOAD:
8590         rs1[i]=(source[i]>>21)&0x1f;
8591         rs2[i]=0;
8592         rt1[i]=(source[i]>>16)&0x1f;
8593         rt2[i]=0;
8594         imm[i]=(short)source[i];
8595         break;
8596       case STORE:
8597       case STORELR:
8598         rs1[i]=(source[i]>>21)&0x1f;
8599         rs2[i]=(source[i]>>16)&0x1f;
8600         rt1[i]=0;
8601         rt2[i]=0;
8602         imm[i]=(short)source[i];
8603         if(op==0x2c||op==0x2d||op==0x3f) us1[i]=rs2[i]; // 64-bit SDL/SDR/SD
8604         break;
8605       case LOADLR:
8606         // LWL/LWR only load part of the register,
8607         // therefore the target register must be treated as a source too
8608         rs1[i]=(source[i]>>21)&0x1f;
8609         rs2[i]=(source[i]>>16)&0x1f;
8610         rt1[i]=(source[i]>>16)&0x1f;
8611         rt2[i]=0;
8612         imm[i]=(short)source[i];
8613         if(op==0x1a||op==0x1b) us1[i]=rs2[i]; // LDR/LDL
8614         if(op==0x26) dep1[i]=rt1[i]; // LWR
8615         break;
8616       case IMM16:
8617         if (op==0x0f) rs1[i]=0; // LUI instruction has no source register
8618         else rs1[i]=(source[i]>>21)&0x1f;
8619         rs2[i]=0;
8620         rt1[i]=(source[i]>>16)&0x1f;
8621         rt2[i]=0;
8622         if(op>=0x0c&&op<=0x0e) { // ANDI/ORI/XORI
8623           imm[i]=(unsigned short)source[i];
8624         }else{
8625           imm[i]=(short)source[i];
8626         }
8627         if(op==0x18||op==0x19) us1[i]=rs1[i]; // DADDI/DADDIU
8628         if(op==0x0a||op==0x0b) us1[i]=rs1[i]; // SLTI/SLTIU
8629         if(op==0x0d||op==0x0e) dep1[i]=rs1[i]; // ORI/XORI
8630         break;
8631       case UJUMP:
8632         rs1[i]=0;
8633         rs2[i]=0;
8634         rt1[i]=0;
8635         rt2[i]=0;
8636         // The JAL instruction writes to r31.
8637         if (op&1) {
8638           rt1[i]=31;
8639         }
8640         rs2[i]=CCREG;
8641         break;
8642       case RJUMP:
8643         rs1[i]=(source[i]>>21)&0x1f;
8644         rs2[i]=0;
8645         rt1[i]=0;
8646         rt2[i]=0;
8647         // The JALR instruction writes to rd.
8648         if (op2&1) {
8649           rt1[i]=(source[i]>>11)&0x1f;
8650         }
8651         rs2[i]=CCREG;
8652         break;
8653       case CJUMP:
8654         rs1[i]=(source[i]>>21)&0x1f;
8655         rs2[i]=(source[i]>>16)&0x1f;
8656         rt1[i]=0;
8657         rt2[i]=0;
8658         if(op&2) { // BGTZ/BLEZ
8659           rs2[i]=0;
8660         }
8661         us1[i]=rs1[i];
8662         us2[i]=rs2[i];
8663         likely[i]=op>>4;
8664         break;
8665       case SJUMP:
8666         rs1[i]=(source[i]>>21)&0x1f;
8667         rs2[i]=CCREG;
8668         rt1[i]=0;
8669         rt2[i]=0;
8670         us1[i]=rs1[i];
8671         if(op2&0x10) { // BxxAL
8672           rt1[i]=31;
8673           // NOTE: If the branch is not taken, r31 is still overwritten
8674         }
8675         likely[i]=(op2&2)>>1;
8676         break;
8677       case FJUMP:
8678         rs1[i]=FSREG;
8679         rs2[i]=CSREG;
8680         rt1[i]=0;
8681         rt2[i]=0;
8682         likely[i]=((source[i])>>17)&1;
8683         break;
8684       case ALU:
8685         rs1[i]=(source[i]>>21)&0x1f; // source
8686         rs2[i]=(source[i]>>16)&0x1f; // subtract amount
8687         rt1[i]=(source[i]>>11)&0x1f; // destination
8688         rt2[i]=0;
8689         if(op2==0x2a||op2==0x2b) { // SLT/SLTU
8690           us1[i]=rs1[i];us2[i]=rs2[i];
8691         }
8692         else if(op2>=0x24&&op2<=0x27) { // AND/OR/XOR/NOR
8693           dep1[i]=rs1[i];dep2[i]=rs2[i];
8694         }
8695         else if(op2>=0x2c&&op2<=0x2f) { // DADD/DSUB
8696           dep1[i]=rs1[i];dep2[i]=rs2[i];
8697         }
8698         break;
8699       case MULTDIV:
8700         rs1[i]=(source[i]>>21)&0x1f; // source
8701         rs2[i]=(source[i]>>16)&0x1f; // divisor
8702         rt1[i]=HIREG;
8703         rt2[i]=LOREG;
8704         if (op2>=0x1c&&op2<=0x1f) { // DMULT/DMULTU/DDIV/DDIVU
8705           us1[i]=rs1[i];us2[i]=rs2[i];
8706         }
8707         break;
8708       case MOV:
8709         rs1[i]=0;
8710         rs2[i]=0;
8711         rt1[i]=0;
8712         rt2[i]=0;
8713         if(op2==0x10) rs1[i]=HIREG; // MFHI
8714         if(op2==0x11) rt1[i]=HIREG; // MTHI
8715         if(op2==0x12) rs1[i]=LOREG; // MFLO
8716         if(op2==0x13) rt1[i]=LOREG; // MTLO
8717         if((op2&0x1d)==0x10) rt1[i]=(source[i]>>11)&0x1f; // MFxx
8718         if((op2&0x1d)==0x11) rs1[i]=(source[i]>>21)&0x1f; // MTxx
8719         dep1[i]=rs1[i];
8720         break;
8721       case SHIFT:
8722         rs1[i]=(source[i]>>16)&0x1f; // target of shift
8723         rs2[i]=(source[i]>>21)&0x1f; // shift amount
8724         rt1[i]=(source[i]>>11)&0x1f; // destination
8725         rt2[i]=0;
8726         // DSLLV/DSRLV/DSRAV are 64-bit
8727         if(op2>=0x14&&op2<=0x17) us1[i]=rs1[i];
8728         break;
8729       case SHIFTIMM:
8730         rs1[i]=(source[i]>>16)&0x1f;
8731         rs2[i]=0;
8732         rt1[i]=(source[i]>>11)&0x1f;
8733         rt2[i]=0;
8734         imm[i]=(source[i]>>6)&0x1f;
8735         // DSxx32 instructions
8736         if(op2>=0x3c) imm[i]|=0x20;
8737         // DSLL/DSRL/DSRA/DSRA32/DSRL32 but not DSLL32 require 64-bit source
8738         if(op2>=0x38&&op2!=0x3c) us1[i]=rs1[i];
8739         break;
8740       case COP0:
8741         rs1[i]=0;
8742         rs2[i]=0;
8743         rt1[i]=0;
8744         rt2[i]=0;
8745         if(op2==0) rt1[i]=(source[i]>>16)&0x1F; // MFC0
8746         if(op2==4) rs1[i]=(source[i]>>16)&0x1F; // MTC0
8747         if(op2==4&&((source[i]>>11)&0x1f)==12) rt2[i]=CSREG; // Status
8748         if(op2==16) if((source[i]&0x3f)==0x18) rs2[i]=CCREG; // ERET
8749         break;
8750       case COP1:
8751         rs1[i]=0;
8752         rs2[i]=0;
8753         rt1[i]=0;
8754         rt2[i]=0;
8755         if(op2<3) rt1[i]=(source[i]>>16)&0x1F; // MFC1/DMFC1/CFC1
8756         if(op2>3) rs1[i]=(source[i]>>16)&0x1F; // MTC1/DMTC1/CTC1
8757         if(op2==5) us1[i]=rs1[i]; // DMTC1
8758         rs2[i]=CSREG;
8759         break;
8760       case COP2:
8761         rs1[i]=0;
8762         rs2[i]=0;
8763         rt1[i]=0;
8764         rt2[i]=0;
8765         if(op2<3) rt1[i]=(source[i]>>16)&0x1F; // MFC2/CFC2
8766         if(op2>3) rs1[i]=(source[i]>>16)&0x1F; // MTC2/CTC2
8767         rs2[i]=CSREG;
8768         int gr=(source[i]>>11)&0x1F;
8769         switch(op2)
8770         {
8771           case 0x00: gte_rs[i]=1ll<<gr; break; // MFC2
8772           case 0x04: gte_rt[i]=1ll<<gr; break; // MTC2
8773           case 0x02: gte_rs[i]=1ll<<(gr+32); break; // CFC2
8774           case 0x06: gte_rt[i]=1ll<<(gr+32); break; // CTC2
8775         }
8776         break;
8777       case C1LS:
8778         rs1[i]=(source[i]>>21)&0x1F;
8779         rs2[i]=CSREG;
8780         rt1[i]=0;
8781         rt2[i]=0;
8782         imm[i]=(short)source[i];
8783         break;
8784       case C2LS:
8785         rs1[i]=(source[i]>>21)&0x1F;
8786         rs2[i]=0;
8787         rt1[i]=0;
8788         rt2[i]=0;
8789         imm[i]=(short)source[i];
8790         if(op==0x32) gte_rt[i]=1ll<<((source[i]>>16)&0x1F); // LWC2
8791         else gte_rs[i]=1ll<<((source[i]>>16)&0x1F); // SWC2
8792         break;
8793       case C2OP:
8794         rs1[i]=0;
8795         rs2[i]=0;
8796         rt1[i]=0;
8797         rt2[i]=0;
8798         gte_rs[i]=gte_reg_reads[source[i]&0x3f];
8799         gte_rt[i]=gte_reg_writes[source[i]&0x3f];
8800         gte_rt[i]|=1ll<<63; // every op changes flags
8801         if((source[i]&0x3f)==GTE_MVMVA) {
8802           int v = (source[i] >> 15) & 3;
8803           gte_rs[i]&=~0xe3fll;
8804           if(v==3) gte_rs[i]|=0xe00ll;
8805           else gte_rs[i]|=3ll<<(v*2);
8806         }
8807         break;
8808       case FLOAT:
8809       case FCONV:
8810         rs1[i]=0;
8811         rs2[i]=CSREG;
8812         rt1[i]=0;
8813         rt2[i]=0;
8814         break;
8815       case FCOMP:
8816         rs1[i]=FSREG;
8817         rs2[i]=CSREG;
8818         rt1[i]=FSREG;
8819         rt2[i]=0;
8820         break;
8821       case SYSCALL:
8822       case HLECALL:
8823       case INTCALL:
8824         rs1[i]=CCREG;
8825         rs2[i]=0;
8826         rt1[i]=0;
8827         rt2[i]=0;
8828         break;
8829       default:
8830         rs1[i]=0;
8831         rs2[i]=0;
8832         rt1[i]=0;
8833         rt2[i]=0;
8834     }
8835     /* Calculate branch target addresses */
8836     if(type==UJUMP)
8837       ba[i]=((start+i*4+4)&0xF0000000)|(((unsigned int)source[i]<<6)>>4);
8838     else if(type==CJUMP&&rs1[i]==rs2[i]&&(op&1))
8839       ba[i]=start+i*4+8; // Ignore never taken branch
8840     else if(type==SJUMP&&rs1[i]==0&&!(op2&1))
8841       ba[i]=start+i*4+8; // Ignore never taken branch
8842     else if(type==CJUMP||type==SJUMP||type==FJUMP)
8843       ba[i]=start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14);
8844     else ba[i]=-1;
8845 #ifdef PCSX
8846     if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)) {
8847       int do_in_intrp=0;
8848       // branch in delay slot?
8849       if(type==RJUMP||type==UJUMP||type==CJUMP||type==SJUMP||type==FJUMP) {
8850         // don't handle first branch and call interpreter if it's hit
8851         SysPrintf("branch in delay slot @%08x (%08x)\n", addr + i*4, addr);
8852         do_in_intrp=1;
8853       }
8854       // basic load delay detection
8855       else if((type==LOAD||type==LOADLR||type==COP0||type==COP2||type==C2LS)&&rt1[i]!=0) {
8856         int t=(ba[i-1]-start)/4;
8857         if(0 <= t && t < i &&(rt1[i]==rs1[t]||rt1[i]==rs2[t])&&itype[t]!=CJUMP&&itype[t]!=SJUMP) {
8858           // jump target wants DS result - potential load delay effect
8859           SysPrintf("load delay @%08x (%08x)\n", addr + i*4, addr);
8860           do_in_intrp=1;
8861           bt[t+1]=1; // expected return from interpreter
8862         }
8863         else if(i>=2&&rt1[i-2]==2&&rt1[i]==2&&rs1[i]!=2&&rs2[i]!=2&&rs1[i-1]!=2&&rs2[i-1]!=2&&
8864               !(i>=3&&(itype[i-3]==RJUMP||itype[i-3]==UJUMP||itype[i-3]==CJUMP||itype[i-3]==SJUMP))) {
8865           // v0 overwrite like this is a sign of trouble, bail out
8866           SysPrintf("v0 overwrite @%08x (%08x)\n", addr + i*4, addr);
8867           do_in_intrp=1;
8868         }
8869       }
8870       if(do_in_intrp) {
8871         rs1[i-1]=CCREG;
8872         rs2[i-1]=rt1[i-1]=rt2[i-1]=0;
8873         ba[i-1]=-1;
8874         itype[i-1]=INTCALL;
8875         done=2;
8876         i--; // don't compile the DS
8877       }
8878     }
8879 #endif
8880     /* Is this the end of the block? */
8881     if(i>0&&(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)) {
8882       if(rt1[i-1]==0) { // Continue past subroutine call (JAL)
8883         done=2;
8884       }
8885       else {
8886         if(stop_after_jal) done=1;
8887         // Stop on BREAK
8888         if((source[i+1]&0xfc00003f)==0x0d) done=1;
8889       }
8890       // Don't recompile stuff that's already compiled
8891       if(check_addr(start+i*4+4)) done=1;
8892       // Don't get too close to the limit
8893       if(i>MAXBLOCK/2) done=1;
8894     }
8895     if(itype[i]==SYSCALL&&stop_after_jal) done=1;
8896     if(itype[i]==HLECALL||itype[i]==INTCALL) done=2;
8897     if(done==2) {
8898       // Does the block continue due to a branch?
8899       for(j=i-1;j>=0;j--)
8900       {
8901         if(ba[j]==start+i*4) done=j=0; // Branch into delay slot
8902         if(ba[j]==start+i*4+4) done=j=0;
8903         if(ba[j]==start+i*4+8) done=j=0;
8904       }
8905     }
8906     //assert(i<MAXBLOCK-1);
8907     if(start+i*4==pagelimit-4) done=1;
8908     assert(start+i*4<pagelimit);
8909     if (i==MAXBLOCK-1) done=1;
8910     // Stop if we're compiling junk
8911     if(itype[i]==NI&&opcode[i]==0x11) {
8912       done=stop_after_jal=1;
8913       SysPrintf("Disabled speculative precompilation\n");
8914     }
8915   }
8916   slen=i;
8917   if(itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==RJUMP||itype[i-1]==FJUMP) {
8918     if(start+i*4==pagelimit) {
8919       itype[i-1]=SPAN;
8920     }
8921   }
8922   assert(slen>0);
8923
8924   /* Pass 2 - Register dependencies and branch targets */
8925
8926   unneeded_registers(0,slen-1,0);
8927
8928   /* Pass 3 - Register allocation */
8929
8930   struct regstat current; // Current register allocations/status
8931   current.is32=1;
8932   current.dirty=0;
8933   current.u=unneeded_reg[0];
8934   current.uu=unneeded_reg_upper[0];
8935   clear_all_regs(current.regmap);
8936   alloc_reg(&current,0,CCREG);
8937   dirty_reg(&current,CCREG);
8938   current.isconst=0;
8939   current.wasconst=0;
8940   current.waswritten=0;
8941   int ds=0;
8942   int cc=0;
8943   int hr=-1;
8944
8945 #ifndef FORCE32
8946   provisional_32bit();
8947 #endif
8948   if((u_int)addr&1) {
8949     // First instruction is delay slot
8950     cc=-1;
8951     bt[1]=1;
8952     ds=1;
8953     unneeded_reg[0]=1;
8954     unneeded_reg_upper[0]=1;
8955     current.regmap[HOST_BTREG]=BTREG;
8956   }
8957
8958   for(i=0;i<slen;i++)
8959   {
8960     if(bt[i])
8961     {
8962       int hr;
8963       for(hr=0;hr<HOST_REGS;hr++)
8964       {
8965         // Is this really necessary?
8966         if(current.regmap[hr]==0) current.regmap[hr]=-1;
8967       }
8968       current.isconst=0;
8969       current.waswritten=0;
8970     }
8971     if(i>1)
8972     {
8973       if((opcode[i-2]&0x2f)==0x05) // BNE/BNEL
8974       {
8975         if(rs1[i-2]==0||rs2[i-2]==0)
8976         {
8977           if(rs1[i-2]) {
8978             current.is32|=1LL<<rs1[i-2];
8979             int hr=get_reg(current.regmap,rs1[i-2]|64);
8980             if(hr>=0) current.regmap[hr]=-1;
8981           }
8982           if(rs2[i-2]) {
8983             current.is32|=1LL<<rs2[i-2];
8984             int hr=get_reg(current.regmap,rs2[i-2]|64);
8985             if(hr>=0) current.regmap[hr]=-1;
8986           }
8987         }
8988       }
8989     }
8990 #ifndef FORCE32
8991     // If something jumps here with 64-bit values
8992     // then promote those registers to 64 bits
8993     if(bt[i])
8994     {
8995       uint64_t temp_is32=current.is32;
8996       for(j=i-1;j>=0;j--)
8997       {
8998         if(ba[j]==start+i*4)
8999           temp_is32&=branch_regs[j].is32;
9000       }
9001       for(j=i;j<slen;j++)
9002       {
9003         if(ba[j]==start+i*4)
9004           //temp_is32=1;
9005           temp_is32&=p32[j];
9006       }
9007       if(temp_is32!=current.is32) {
9008         //printf("dumping 32-bit regs (%x)\n",start+i*4);
9009         #ifndef DESTRUCTIVE_WRITEBACK
9010         if(ds)
9011         #endif
9012         for(hr=0;hr<HOST_REGS;hr++)
9013         {
9014           int r=current.regmap[hr];
9015           if(r>0&&r<64)
9016           {
9017             if((current.dirty>>hr)&((current.is32&~temp_is32)>>r)&1) {
9018               temp_is32|=1LL<<r;
9019               //printf("restore %d\n",r);
9020             }
9021           }
9022         }
9023         current.is32=temp_is32;
9024       }
9025     }
9026 #else
9027     current.is32=-1LL;
9028 #endif
9029
9030     memcpy(regmap_pre[i],current.regmap,sizeof(current.regmap));
9031     regs[i].wasconst=current.isconst;
9032     regs[i].was32=current.is32;
9033     regs[i].wasdirty=current.dirty;
9034     regs[i].loadedconst=0;
9035     #if defined(DESTRUCTIVE_WRITEBACK) && !defined(FORCE32)
9036     // To change a dirty register from 32 to 64 bits, we must write
9037     // it out during the previous cycle (for branches, 2 cycles)
9038     if(i<slen-1&&bt[i+1]&&itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP)
9039     {
9040       uint64_t temp_is32=current.is32;
9041       for(j=i-1;j>=0;j--)
9042       {
9043         if(ba[j]==start+i*4+4)
9044           temp_is32&=branch_regs[j].is32;
9045       }
9046       for(j=i;j<slen;j++)
9047       {
9048         if(ba[j]==start+i*4+4)
9049           //temp_is32=1;
9050           temp_is32&=p32[j];
9051       }
9052       if(temp_is32!=current.is32) {
9053         //printf("pre-dumping 32-bit regs (%x)\n",start+i*4);
9054         for(hr=0;hr<HOST_REGS;hr++)
9055         {
9056           int r=current.regmap[hr];
9057           if(r>0)
9058           {
9059             if((current.dirty>>hr)&((current.is32&~temp_is32)>>(r&63))&1) {
9060               if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP)
9061               {
9062                 if(rs1[i]!=(r&63)&&rs2[i]!=(r&63))
9063                 {
9064                   //printf("dump %d/r%d\n",hr,r);
9065                   current.regmap[hr]=-1;
9066                   if(get_reg(current.regmap,r|64)>=0)
9067                     current.regmap[get_reg(current.regmap,r|64)]=-1;
9068                 }
9069               }
9070             }
9071           }
9072         }
9073       }
9074     }
9075     else if(i<slen-2&&bt[i+2]&&(source[i-1]>>16)!=0x1000&&(itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP))
9076     {
9077       uint64_t temp_is32=current.is32;
9078       for(j=i-1;j>=0;j--)
9079       {
9080         if(ba[j]==start+i*4+8)
9081           temp_is32&=branch_regs[j].is32;
9082       }
9083       for(j=i;j<slen;j++)
9084       {
9085         if(ba[j]==start+i*4+8)
9086           //temp_is32=1;
9087           temp_is32&=p32[j];
9088       }
9089       if(temp_is32!=current.is32) {
9090         //printf("pre-dumping 32-bit regs (%x)\n",start+i*4);
9091         for(hr=0;hr<HOST_REGS;hr++)
9092         {
9093           int r=current.regmap[hr];
9094           if(r>0)
9095           {
9096             if((current.dirty>>hr)&((current.is32&~temp_is32)>>(r&63))&1) {
9097               if(rs1[i]!=(r&63)&&rs2[i]!=(r&63)&&rs1[i+1]!=(r&63)&&rs2[i+1]!=(r&63))
9098               {
9099                 //printf("dump %d/r%d\n",hr,r);
9100                 current.regmap[hr]=-1;
9101                 if(get_reg(current.regmap,r|64)>=0)
9102                   current.regmap[get_reg(current.regmap,r|64)]=-1;
9103               }
9104             }
9105           }
9106         }
9107       }
9108     }
9109     #endif
9110     if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP) {
9111       if(i+1<slen) {
9112         current.u=unneeded_reg[i+1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
9113         current.uu=unneeded_reg_upper[i+1]&~((1LL<<us1[i])|(1LL<<us2[i]));
9114         if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9115         current.u|=1;
9116         current.uu|=1;
9117       } else {
9118         current.u=1;
9119         current.uu=1;
9120       }
9121     } else {
9122       if(i+1<slen) {
9123         current.u=branch_unneeded_reg[i]&~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
9124         current.uu=branch_unneeded_reg_upper[i]&~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
9125         if((~current.uu>>rt1[i+1])&1) current.uu&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
9126         current.u&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
9127         current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
9128         current.u|=1;
9129         current.uu|=1;
9130       } else { SysPrintf("oops, branch at end of block with no delay slot\n");exit(1); }
9131     }
9132     is_ds[i]=ds;
9133     if(ds) {
9134       ds=0; // Skip delay slot, already allocated as part of branch
9135       // ...but we need to alloc it in case something jumps here
9136       if(i+1<slen) {
9137         current.u=branch_unneeded_reg[i-1]&unneeded_reg[i+1];
9138         current.uu=branch_unneeded_reg_upper[i-1]&unneeded_reg_upper[i+1];
9139       }else{
9140         current.u=branch_unneeded_reg[i-1];
9141         current.uu=branch_unneeded_reg_upper[i-1];
9142       }
9143       current.u&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
9144       current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
9145       if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9146       current.u|=1;
9147       current.uu|=1;
9148       struct regstat temp;
9149       memcpy(&temp,&current,sizeof(current));
9150       temp.wasdirty=temp.dirty;
9151       temp.was32=temp.is32;
9152       // TODO: Take into account unconditional branches, as below
9153       delayslot_alloc(&temp,i);
9154       memcpy(regs[i].regmap,temp.regmap,sizeof(temp.regmap));
9155       regs[i].wasdirty=temp.wasdirty;
9156       regs[i].was32=temp.was32;
9157       regs[i].dirty=temp.dirty;
9158       regs[i].is32=temp.is32;
9159       regs[i].isconst=0;
9160       regs[i].wasconst=0;
9161       current.isconst=0;
9162       // Create entry (branch target) regmap
9163       for(hr=0;hr<HOST_REGS;hr++)
9164       {
9165         int r=temp.regmap[hr];
9166         if(r>=0) {
9167           if(r!=regmap_pre[i][hr]) {
9168             regs[i].regmap_entry[hr]=-1;
9169           }
9170           else
9171           {
9172             if(r<64){
9173               if((current.u>>r)&1) {
9174                 regs[i].regmap_entry[hr]=-1;
9175                 regs[i].regmap[hr]=-1;
9176                 //Don't clear regs in the delay slot as the branch might need them
9177                 //current.regmap[hr]=-1;
9178               }else
9179                 regs[i].regmap_entry[hr]=r;
9180             }
9181             else {
9182               if((current.uu>>(r&63))&1) {
9183                 regs[i].regmap_entry[hr]=-1;
9184                 regs[i].regmap[hr]=-1;
9185                 //Don't clear regs in the delay slot as the branch might need them
9186                 //current.regmap[hr]=-1;
9187               }else
9188                 regs[i].regmap_entry[hr]=r;
9189             }
9190           }
9191         } else {
9192           // First instruction expects CCREG to be allocated
9193           if(i==0&&hr==HOST_CCREG)
9194             regs[i].regmap_entry[hr]=CCREG;
9195           else
9196             regs[i].regmap_entry[hr]=-1;
9197         }
9198       }
9199     }
9200     else { // Not delay slot
9201       switch(itype[i]) {
9202         case UJUMP:
9203           //current.isconst=0; // DEBUG
9204           //current.wasconst=0; // DEBUG
9205           //regs[i].wasconst=0; // DEBUG
9206           clear_const(&current,rt1[i]);
9207           alloc_cc(&current,i);
9208           dirty_reg(&current,CCREG);
9209           if (rt1[i]==31) {
9210             alloc_reg(&current,i,31);
9211             dirty_reg(&current,31);
9212             //assert(rs1[i+1]!=31&&rs2[i+1]!=31);
9213             //assert(rt1[i+1]!=rt1[i]);
9214             #ifdef REG_PREFETCH
9215             alloc_reg(&current,i,PTEMP);
9216             #endif
9217             //current.is32|=1LL<<rt1[i];
9218           }
9219           ooo[i]=1;
9220           delayslot_alloc(&current,i+1);
9221           //current.isconst=0; // DEBUG
9222           ds=1;
9223           //printf("i=%d, isconst=%x\n",i,current.isconst);
9224           break;
9225         case RJUMP:
9226           //current.isconst=0;
9227           //current.wasconst=0;
9228           //regs[i].wasconst=0;
9229           clear_const(&current,rs1[i]);
9230           clear_const(&current,rt1[i]);
9231           alloc_cc(&current,i);
9232           dirty_reg(&current,CCREG);
9233           if(rs1[i]!=rt1[i+1]&&rs1[i]!=rt2[i+1]) {
9234             alloc_reg(&current,i,rs1[i]);
9235             if (rt1[i]!=0) {
9236               alloc_reg(&current,i,rt1[i]);
9237               dirty_reg(&current,rt1[i]);
9238               assert(rs1[i+1]!=rt1[i]&&rs2[i+1]!=rt1[i]);
9239               assert(rt1[i+1]!=rt1[i]);
9240               #ifdef REG_PREFETCH
9241               alloc_reg(&current,i,PTEMP);
9242               #endif
9243             }
9244             #ifdef USE_MINI_HT
9245             if(rs1[i]==31) { // JALR
9246               alloc_reg(&current,i,RHASH);
9247               #ifndef HOST_IMM_ADDR32
9248               alloc_reg(&current,i,RHTBL);
9249               #endif
9250             }
9251             #endif
9252             delayslot_alloc(&current,i+1);
9253           } else {
9254             // The delay slot overwrites our source register,
9255             // allocate a temporary register to hold the old value.
9256             current.isconst=0;
9257             current.wasconst=0;
9258             regs[i].wasconst=0;
9259             delayslot_alloc(&current,i+1);
9260             current.isconst=0;
9261             alloc_reg(&current,i,RTEMP);
9262           }
9263           //current.isconst=0; // DEBUG
9264           ooo[i]=1;
9265           ds=1;
9266           break;
9267         case CJUMP:
9268           //current.isconst=0;
9269           //current.wasconst=0;
9270           //regs[i].wasconst=0;
9271           clear_const(&current,rs1[i]);
9272           clear_const(&current,rs2[i]);
9273           if((opcode[i]&0x3E)==4) // BEQ/BNE
9274           {
9275             alloc_cc(&current,i);
9276             dirty_reg(&current,CCREG);
9277             if(rs1[i]) alloc_reg(&current,i,rs1[i]);
9278             if(rs2[i]) alloc_reg(&current,i,rs2[i]);
9279             if(!((current.is32>>rs1[i])&(current.is32>>rs2[i])&1))
9280             {
9281               if(rs1[i]) alloc_reg64(&current,i,rs1[i]);
9282               if(rs2[i]) alloc_reg64(&current,i,rs2[i]);
9283             }
9284             if((rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]))||
9285                (rs2[i]&&(rs2[i]==rt1[i+1]||rs2[i]==rt2[i+1]))) {
9286               // The delay slot overwrites one of our conditions.
9287               // Allocate the branch condition registers instead.
9288               current.isconst=0;
9289               current.wasconst=0;
9290               regs[i].wasconst=0;
9291               if(rs1[i]) alloc_reg(&current,i,rs1[i]);
9292               if(rs2[i]) alloc_reg(&current,i,rs2[i]);
9293               if(!((current.is32>>rs1[i])&(current.is32>>rs2[i])&1))
9294               {
9295                 if(rs1[i]) alloc_reg64(&current,i,rs1[i]);
9296                 if(rs2[i]) alloc_reg64(&current,i,rs2[i]);
9297               }
9298             }
9299             else
9300             {
9301               ooo[i]=1;
9302               delayslot_alloc(&current,i+1);
9303             }
9304           }
9305           else
9306           if((opcode[i]&0x3E)==6) // BLEZ/BGTZ
9307           {
9308             alloc_cc(&current,i);
9309             dirty_reg(&current,CCREG);
9310             alloc_reg(&current,i,rs1[i]);
9311             if(!(current.is32>>rs1[i]&1))
9312             {
9313               alloc_reg64(&current,i,rs1[i]);
9314             }
9315             if(rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1])) {
9316               // The delay slot overwrites one of our conditions.
9317               // Allocate the branch condition registers instead.
9318               current.isconst=0;
9319               current.wasconst=0;
9320               regs[i].wasconst=0;
9321               if(rs1[i]) alloc_reg(&current,i,rs1[i]);
9322               if(!((current.is32>>rs1[i])&1))
9323               {
9324                 if(rs1[i]) alloc_reg64(&current,i,rs1[i]);
9325               }
9326             }
9327             else
9328             {
9329               ooo[i]=1;
9330               delayslot_alloc(&current,i+1);
9331             }
9332           }
9333           else
9334           // Don't alloc the delay slot yet because we might not execute it
9335           if((opcode[i]&0x3E)==0x14) // BEQL/BNEL
9336           {
9337             current.isconst=0;
9338             current.wasconst=0;
9339             regs[i].wasconst=0;
9340             alloc_cc(&current,i);
9341             dirty_reg(&current,CCREG);
9342             alloc_reg(&current,i,rs1[i]);
9343             alloc_reg(&current,i,rs2[i]);
9344             if(!((current.is32>>rs1[i])&(current.is32>>rs2[i])&1))
9345             {
9346               alloc_reg64(&current,i,rs1[i]);
9347               alloc_reg64(&current,i,rs2[i]);
9348             }
9349           }
9350           else
9351           if((opcode[i]&0x3E)==0x16) // BLEZL/BGTZL
9352           {
9353             current.isconst=0;
9354             current.wasconst=0;
9355             regs[i].wasconst=0;
9356             alloc_cc(&current,i);
9357             dirty_reg(&current,CCREG);
9358             alloc_reg(&current,i,rs1[i]);
9359             if(!(current.is32>>rs1[i]&1))
9360             {
9361               alloc_reg64(&current,i,rs1[i]);
9362             }
9363           }
9364           ds=1;
9365           //current.isconst=0;
9366           break;
9367         case SJUMP:
9368           //current.isconst=0;
9369           //current.wasconst=0;
9370           //regs[i].wasconst=0;
9371           clear_const(&current,rs1[i]);
9372           clear_const(&current,rt1[i]);
9373           //if((opcode2[i]&0x1E)==0x0) // BLTZ/BGEZ
9374           if((opcode2[i]&0x0E)==0x0) // BLTZ/BGEZ
9375           {
9376             alloc_cc(&current,i);
9377             dirty_reg(&current,CCREG);
9378             alloc_reg(&current,i,rs1[i]);
9379             if(!(current.is32>>rs1[i]&1))
9380             {
9381               alloc_reg64(&current,i,rs1[i]);
9382             }
9383             if (rt1[i]==31) { // BLTZAL/BGEZAL
9384               alloc_reg(&current,i,31);
9385               dirty_reg(&current,31);
9386               //#ifdef REG_PREFETCH
9387               //alloc_reg(&current,i,PTEMP);
9388               //#endif
9389               //current.is32|=1LL<<rt1[i];
9390             }
9391             if((rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1])) // The delay slot overwrites the branch condition.
9392                ||(rt1[i]==31&&(rs1[i+1]==31||rs2[i+1]==31||rt1[i+1]==31||rt2[i+1]==31))) { // DS touches $ra
9393               // Allocate the branch condition registers instead.
9394               current.isconst=0;
9395               current.wasconst=0;
9396               regs[i].wasconst=0;
9397               if(rs1[i]) alloc_reg(&current,i,rs1[i]);
9398               if(!((current.is32>>rs1[i])&1))
9399               {
9400                 if(rs1[i]) alloc_reg64(&current,i,rs1[i]);
9401               }
9402             }
9403             else
9404             {
9405               ooo[i]=1;
9406               delayslot_alloc(&current,i+1);
9407             }
9408           }
9409           else
9410           // Don't alloc the delay slot yet because we might not execute it
9411           if((opcode2[i]&0x1E)==0x2) // BLTZL/BGEZL
9412           {
9413             current.isconst=0;
9414             current.wasconst=0;
9415             regs[i].wasconst=0;
9416             alloc_cc(&current,i);
9417             dirty_reg(&current,CCREG);
9418             alloc_reg(&current,i,rs1[i]);
9419             if(!(current.is32>>rs1[i]&1))
9420             {
9421               alloc_reg64(&current,i,rs1[i]);
9422             }
9423           }
9424           ds=1;
9425           //current.isconst=0;
9426           break;
9427         case FJUMP:
9428           current.isconst=0;
9429           current.wasconst=0;
9430           regs[i].wasconst=0;
9431           if(likely[i]==0) // BC1F/BC1T
9432           {
9433             // TODO: Theoretically we can run out of registers here on x86.
9434             // The delay slot can allocate up to six, and we need to check
9435             // CSREG before executing the delay slot.  Possibly we can drop
9436             // the cycle count and then reload it after checking that the
9437             // FPU is in a usable state, or don't do out-of-order execution.
9438             alloc_cc(&current,i);
9439             dirty_reg(&current,CCREG);
9440             alloc_reg(&current,i,FSREG);
9441             alloc_reg(&current,i,CSREG);
9442             if(itype[i+1]==FCOMP) {
9443               // The delay slot overwrites the branch condition.
9444               // Allocate the branch condition registers instead.
9445               alloc_cc(&current,i);
9446               dirty_reg(&current,CCREG);
9447               alloc_reg(&current,i,CSREG);
9448               alloc_reg(&current,i,FSREG);
9449             }
9450             else {
9451               ooo[i]=1;
9452               delayslot_alloc(&current,i+1);
9453               alloc_reg(&current,i+1,CSREG);
9454             }
9455           }
9456           else
9457           // Don't alloc the delay slot yet because we might not execute it
9458           if(likely[i]) // BC1FL/BC1TL
9459           {
9460             alloc_cc(&current,i);
9461             dirty_reg(&current,CCREG);
9462             alloc_reg(&current,i,CSREG);
9463             alloc_reg(&current,i,FSREG);
9464           }
9465           ds=1;
9466           current.isconst=0;
9467           break;
9468         case IMM16:
9469           imm16_alloc(&current,i);
9470           break;
9471         case LOAD:
9472         case LOADLR:
9473           load_alloc(&current,i);
9474           break;
9475         case STORE:
9476         case STORELR:
9477           store_alloc(&current,i);
9478           break;
9479         case ALU:
9480           alu_alloc(&current,i);
9481           break;
9482         case SHIFT:
9483           shift_alloc(&current,i);
9484           break;
9485         case MULTDIV:
9486           multdiv_alloc(&current,i);
9487           break;
9488         case SHIFTIMM:
9489           shiftimm_alloc(&current,i);
9490           break;
9491         case MOV:
9492           mov_alloc(&current,i);
9493           break;
9494         case COP0:
9495           cop0_alloc(&current,i);
9496           break;
9497         case COP1:
9498         case COP2:
9499           cop1_alloc(&current,i);
9500           break;
9501         case C1LS:
9502           c1ls_alloc(&current,i);
9503           break;
9504         case C2LS:
9505           c2ls_alloc(&current,i);
9506           break;
9507         case C2OP:
9508           c2op_alloc(&current,i);
9509           break;
9510         case FCONV:
9511           fconv_alloc(&current,i);
9512           break;
9513         case FLOAT:
9514           float_alloc(&current,i);
9515           break;
9516         case FCOMP:
9517           fcomp_alloc(&current,i);
9518           break;
9519         case SYSCALL:
9520         case HLECALL:
9521         case INTCALL:
9522           syscall_alloc(&current,i);
9523           break;
9524         case SPAN:
9525           pagespan_alloc(&current,i);
9526           break;
9527       }
9528
9529       // Drop the upper half of registers that have become 32-bit
9530       current.uu|=current.is32&((1LL<<rt1[i])|(1LL<<rt2[i]));
9531       if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP) {
9532         current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
9533         if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9534         current.uu|=1;
9535       } else {
9536         current.uu|=current.is32&((1LL<<rt1[i+1])|(1LL<<rt2[i+1]));
9537         current.uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
9538         if((~current.uu>>rt1[i+1])&1) current.uu&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
9539         current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
9540         current.uu|=1;
9541       }
9542
9543       // Create entry (branch target) regmap
9544       for(hr=0;hr<HOST_REGS;hr++)
9545       {
9546         int r,or,er;
9547         r=current.regmap[hr];
9548         if(r>=0) {
9549           if(r!=regmap_pre[i][hr]) {
9550             // TODO: delay slot (?)
9551             or=get_reg(regmap_pre[i],r); // Get old mapping for this register
9552             if(or<0||(r&63)>=TEMPREG){
9553               regs[i].regmap_entry[hr]=-1;
9554             }
9555             else
9556             {
9557               // Just move it to a different register
9558               regs[i].regmap_entry[hr]=r;
9559               // If it was dirty before, it's still dirty
9560               if((regs[i].wasdirty>>or)&1) dirty_reg(&current,r&63);
9561             }
9562           }
9563           else
9564           {
9565             // Unneeded
9566             if(r==0){
9567               regs[i].regmap_entry[hr]=0;
9568             }
9569             else
9570             if(r<64){
9571               if((current.u>>r)&1) {
9572                 regs[i].regmap_entry[hr]=-1;
9573                 //regs[i].regmap[hr]=-1;
9574                 current.regmap[hr]=-1;
9575               }else
9576                 regs[i].regmap_entry[hr]=r;
9577             }
9578             else {
9579               if((current.uu>>(r&63))&1) {
9580                 regs[i].regmap_entry[hr]=-1;
9581                 //regs[i].regmap[hr]=-1;
9582                 current.regmap[hr]=-1;
9583               }else
9584                 regs[i].regmap_entry[hr]=r;
9585             }
9586           }
9587         } else {
9588           // Branches expect CCREG to be allocated at the target
9589           if(regmap_pre[i][hr]==CCREG)
9590             regs[i].regmap_entry[hr]=CCREG;
9591           else
9592             regs[i].regmap_entry[hr]=-1;
9593         }
9594       }
9595       memcpy(regs[i].regmap,current.regmap,sizeof(current.regmap));
9596     }
9597
9598     if(i>0&&(itype[i-1]==STORE||itype[i-1]==STORELR||(itype[i-1]==C2LS&&opcode[i-1]==0x3a))&&(u_int)imm[i-1]<0x800)
9599       current.waswritten|=1<<rs1[i-1];
9600     current.waswritten&=~(1<<rt1[i]);
9601     current.waswritten&=~(1<<rt2[i]);
9602     if((itype[i]==STORE||itype[i]==STORELR||(itype[i]==C2LS&&opcode[i]==0x3a))&&(u_int)imm[i]>=0x800)
9603       current.waswritten&=~(1<<rs1[i]);
9604
9605     /* Branch post-alloc */
9606     if(i>0)
9607     {
9608       current.was32=current.is32;
9609       current.wasdirty=current.dirty;
9610       switch(itype[i-1]) {
9611         case UJUMP:
9612           memcpy(&branch_regs[i-1],&current,sizeof(current));
9613           branch_regs[i-1].isconst=0;
9614           branch_regs[i-1].wasconst=0;
9615           branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1]));
9616           branch_regs[i-1].uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i-1])|(1LL<<us2[i-1]));
9617           alloc_cc(&branch_regs[i-1],i-1);
9618           dirty_reg(&branch_regs[i-1],CCREG);
9619           if(rt1[i-1]==31) { // JAL
9620             alloc_reg(&branch_regs[i-1],i-1,31);
9621             dirty_reg(&branch_regs[i-1],31);
9622             branch_regs[i-1].is32|=1LL<<31;
9623           }
9624           memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9625           memcpy(constmap[i],constmap[i-1],sizeof(current_constmap));
9626           break;
9627         case RJUMP:
9628           memcpy(&branch_regs[i-1],&current,sizeof(current));
9629           branch_regs[i-1].isconst=0;
9630           branch_regs[i-1].wasconst=0;
9631           branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1]));
9632           branch_regs[i-1].uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i-1])|(1LL<<us2[i-1]));
9633           alloc_cc(&branch_regs[i-1],i-1);
9634           dirty_reg(&branch_regs[i-1],CCREG);
9635           alloc_reg(&branch_regs[i-1],i-1,rs1[i-1]);
9636           if(rt1[i-1]!=0) { // JALR
9637             alloc_reg(&branch_regs[i-1],i-1,rt1[i-1]);
9638             dirty_reg(&branch_regs[i-1],rt1[i-1]);
9639             branch_regs[i-1].is32|=1LL<<rt1[i-1];
9640           }
9641           #ifdef USE_MINI_HT
9642           if(rs1[i-1]==31) { // JALR
9643             alloc_reg(&branch_regs[i-1],i-1,RHASH);
9644             #ifndef HOST_IMM_ADDR32
9645             alloc_reg(&branch_regs[i-1],i-1,RHTBL);
9646             #endif
9647           }
9648           #endif
9649           memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9650           memcpy(constmap[i],constmap[i-1],sizeof(current_constmap));
9651           break;
9652         case CJUMP:
9653           if((opcode[i-1]&0x3E)==4) // BEQ/BNE
9654           {
9655             alloc_cc(&current,i-1);
9656             dirty_reg(&current,CCREG);
9657             if((rs1[i-1]&&(rs1[i-1]==rt1[i]||rs1[i-1]==rt2[i]))||
9658                (rs2[i-1]&&(rs2[i-1]==rt1[i]||rs2[i-1]==rt2[i]))) {
9659               // The delay slot overwrote one of our conditions
9660               // Delay slot goes after the test (in order)
9661               current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
9662               current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i]));
9663               if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9664               current.u|=1;
9665               current.uu|=1;
9666               delayslot_alloc(&current,i);
9667               current.isconst=0;
9668             }
9669             else
9670             {
9671               current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1]));
9672               current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i-1])|(1LL<<us2[i-1]));
9673               // Alloc the branch condition registers
9674               if(rs1[i-1]) alloc_reg(&current,i-1,rs1[i-1]);
9675               if(rs2[i-1]) alloc_reg(&current,i-1,rs2[i-1]);
9676               if(!((current.is32>>rs1[i-1])&(current.is32>>rs2[i-1])&1))
9677               {
9678                 if(rs1[i-1]) alloc_reg64(&current,i-1,rs1[i-1]);
9679                 if(rs2[i-1]) alloc_reg64(&current,i-1,rs2[i-1]);
9680               }
9681             }
9682             memcpy(&branch_regs[i-1],&current,sizeof(current));
9683             branch_regs[i-1].isconst=0;
9684             branch_regs[i-1].wasconst=0;
9685             memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
9686             memcpy(constmap[i],constmap[i-1],sizeof(current_constmap));
9687           }
9688           else
9689           if((opcode[i-1]&0x3E)==6) // BLEZ/BGTZ
9690           {
9691             alloc_cc(&current,i-1);
9692             dirty_reg(&current,CCREG);
9693             if(rs1[i-1]==rt1[i]||rs1[i-1]==rt2[i]) {
9694               // The delay slot overwrote the branch condition
9695               // Delay slot goes after the test (in order)
9696               current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
9697               current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i]));
9698               if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9699               current.u|=1;
9700               current.uu|=1;
9701               delayslot_alloc(&current,i);
9702               current.isconst=0;
9703             }
9704             else
9705             {
9706               current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]);
9707               current.uu=branch_unneeded_reg_upper[i-1]&~(1LL<<us1[i-1]);
9708               // Alloc the branch condition register
9709               alloc_reg(&current,i-1,rs1[i-1]);
9710               if(!(current.is32>>rs1[i-1]&1))
9711               {
9712                 alloc_reg64(&current,i-1,rs1[i-1]);
9713               }
9714             }
9715             memcpy(&branch_regs[i-1],&current,sizeof(current));
9716             branch_regs[i-1].isconst=0;
9717             branch_regs[i-1].wasconst=0;
9718             memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
9719             memcpy(constmap[i],constmap[i-1],sizeof(current_constmap));
9720           }
9721           else
9722           // Alloc the delay slot in case the branch is taken
9723           if((opcode[i-1]&0x3E)==0x14) // BEQL/BNEL
9724           {
9725             memcpy(&branch_regs[i-1],&current,sizeof(current));
9726             branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9727             branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9728             if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9729             alloc_cc(&branch_regs[i-1],i);
9730             dirty_reg(&branch_regs[i-1],CCREG);
9731             delayslot_alloc(&branch_regs[i-1],i);
9732             branch_regs[i-1].isconst=0;
9733             alloc_reg(&current,i,CCREG); // Not taken path
9734             dirty_reg(&current,CCREG);
9735             memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9736           }
9737           else
9738           if((opcode[i-1]&0x3E)==0x16) // BLEZL/BGTZL
9739           {
9740             memcpy(&branch_regs[i-1],&current,sizeof(current));
9741             branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9742             branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9743             if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9744             alloc_cc(&branch_regs[i-1],i);
9745             dirty_reg(&branch_regs[i-1],CCREG);
9746             delayslot_alloc(&branch_regs[i-1],i);
9747             branch_regs[i-1].isconst=0;
9748             alloc_reg(&current,i,CCREG); // Not taken path
9749             dirty_reg(&current,CCREG);
9750             memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9751           }
9752           break;
9753         case SJUMP:
9754           //if((opcode2[i-1]&0x1E)==0) // BLTZ/BGEZ
9755           if((opcode2[i-1]&0x0E)==0) // BLTZ/BGEZ
9756           {
9757             alloc_cc(&current,i-1);
9758             dirty_reg(&current,CCREG);
9759             if(rs1[i-1]==rt1[i]||rs1[i-1]==rt2[i]) {
9760               // The delay slot overwrote the branch condition
9761               // Delay slot goes after the test (in order)
9762               current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
9763               current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i]));
9764               if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9765               current.u|=1;
9766               current.uu|=1;
9767               delayslot_alloc(&current,i);
9768               current.isconst=0;
9769             }
9770             else
9771             {
9772               current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]);
9773               current.uu=branch_unneeded_reg_upper[i-1]&~(1LL<<us1[i-1]);
9774               // Alloc the branch condition register
9775               alloc_reg(&current,i-1,rs1[i-1]);
9776               if(!(current.is32>>rs1[i-1]&1))
9777               {
9778                 alloc_reg64(&current,i-1,rs1[i-1]);
9779               }
9780             }
9781             memcpy(&branch_regs[i-1],&current,sizeof(current));
9782             branch_regs[i-1].isconst=0;
9783             branch_regs[i-1].wasconst=0;
9784             memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
9785             memcpy(constmap[i],constmap[i-1],sizeof(current_constmap));
9786           }
9787           else
9788           // Alloc the delay slot in case the branch is taken
9789           if((opcode2[i-1]&0x1E)==2) // BLTZL/BGEZL
9790           {
9791             memcpy(&branch_regs[i-1],&current,sizeof(current));
9792             branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9793             branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9794             if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9795             alloc_cc(&branch_regs[i-1],i);
9796             dirty_reg(&branch_regs[i-1],CCREG);
9797             delayslot_alloc(&branch_regs[i-1],i);
9798             branch_regs[i-1].isconst=0;
9799             alloc_reg(&current,i,CCREG); // Not taken path
9800             dirty_reg(&current,CCREG);
9801             memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9802           }
9803           // FIXME: BLTZAL/BGEZAL
9804           if(opcode2[i-1]&0x10) { // BxxZAL
9805             alloc_reg(&branch_regs[i-1],i-1,31);
9806             dirty_reg(&branch_regs[i-1],31);
9807             branch_regs[i-1].is32|=1LL<<31;
9808           }
9809           break;
9810         case FJUMP:
9811           if(likely[i-1]==0) // BC1F/BC1T
9812           {
9813             alloc_cc(&current,i-1);
9814             dirty_reg(&current,CCREG);
9815             if(itype[i]==FCOMP) {
9816               // The delay slot overwrote the branch condition
9817               // Delay slot goes after the test (in order)
9818               delayslot_alloc(&current,i);
9819               current.isconst=0;
9820             }
9821             else
9822             {
9823               current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]);
9824               current.uu=branch_unneeded_reg_upper[i-1]&~(1LL<<us1[i-1]);
9825               // Alloc the branch condition register
9826               alloc_reg(&current,i-1,FSREG);
9827             }
9828             memcpy(&branch_regs[i-1],&current,sizeof(current));
9829             memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
9830           }
9831           else // BC1FL/BC1TL
9832           {
9833             // Alloc the delay slot in case the branch is taken
9834             memcpy(&branch_regs[i-1],&current,sizeof(current));
9835             branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9836             branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9837             if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9838             alloc_cc(&branch_regs[i-1],i);
9839             dirty_reg(&branch_regs[i-1],CCREG);
9840             delayslot_alloc(&branch_regs[i-1],i);
9841             branch_regs[i-1].isconst=0;
9842             alloc_reg(&current,i,CCREG); // Not taken path
9843             dirty_reg(&current,CCREG);
9844             memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9845           }
9846           break;
9847       }
9848
9849       if(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)
9850       {
9851         if(rt1[i-1]==31) // JAL/JALR
9852         {
9853           // Subroutine call will return here, don't alloc any registers
9854           current.is32=1;
9855           current.dirty=0;
9856           clear_all_regs(current.regmap);
9857           alloc_reg(&current,i,CCREG);
9858           dirty_reg(&current,CCREG);
9859         }
9860         else if(i+1<slen)
9861         {
9862           // Internal branch will jump here, match registers to caller
9863           current.is32=0x3FFFFFFFFLL;
9864           current.dirty=0;
9865           clear_all_regs(current.regmap);
9866           alloc_reg(&current,i,CCREG);
9867           dirty_reg(&current,CCREG);
9868           for(j=i-1;j>=0;j--)
9869           {
9870             if(ba[j]==start+i*4+4) {
9871               memcpy(current.regmap,branch_regs[j].regmap,sizeof(current.regmap));
9872               current.is32=branch_regs[j].is32;
9873               current.dirty=branch_regs[j].dirty;
9874               break;
9875             }
9876           }
9877           while(j>=0) {
9878             if(ba[j]==start+i*4+4) {
9879               for(hr=0;hr<HOST_REGS;hr++) {
9880                 if(current.regmap[hr]!=branch_regs[j].regmap[hr]) {
9881                   current.regmap[hr]=-1;
9882                 }
9883                 current.is32&=branch_regs[j].is32;
9884                 current.dirty&=branch_regs[j].dirty;
9885               }
9886             }
9887             j--;
9888           }
9889         }
9890       }
9891     }
9892
9893     // Count cycles in between branches
9894     ccadj[i]=cc;
9895     if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP||itype[i]==SYSCALL||itype[i]==HLECALL))
9896     {
9897       cc=0;
9898     }
9899 #if defined(PCSX) && !defined(DRC_DBG)
9900     else if(itype[i]==C2OP&&gte_cycletab[source[i]&0x3f]>2)
9901     {
9902       // GTE runs in parallel until accessed, divide by 2 for a rough guess
9903       cc+=gte_cycletab[source[i]&0x3f]/2;
9904     }
9905     else if(/*itype[i]==LOAD||itype[i]==STORE||*/itype[i]==C1LS) // load,store causes weird timing issues
9906     {
9907       cc+=2; // 2 cycle penalty (after CLOCK_DIVIDER)
9908     }
9909     else if(itype[i]==C2LS)
9910     {
9911       cc+=4;
9912     }
9913 #endif
9914     else
9915     {
9916       cc++;
9917     }
9918
9919     flush_dirty_uppers(&current);
9920     if(!is_ds[i]) {
9921       regs[i].is32=current.is32;
9922       regs[i].dirty=current.dirty;
9923       regs[i].isconst=current.isconst;
9924       memcpy(constmap[i],current_constmap,sizeof(current_constmap));
9925     }
9926     for(hr=0;hr<HOST_REGS;hr++) {
9927       if(hr!=EXCLUDE_REG&&regs[i].regmap[hr]>=0) {
9928         if(regmap_pre[i][hr]!=regs[i].regmap[hr]) {
9929           regs[i].wasconst&=~(1<<hr);
9930         }
9931       }
9932     }
9933     if(current.regmap[HOST_BTREG]==BTREG) current.regmap[HOST_BTREG]=-1;
9934     regs[i].waswritten=current.waswritten;
9935   }
9936
9937   /* Pass 4 - Cull unused host registers */
9938
9939   uint64_t nr=0;
9940
9941   for (i=slen-1;i>=0;i--)
9942   {
9943     int hr;
9944     if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
9945     {
9946       if(ba[i]<start || ba[i]>=(start+slen*4))
9947       {
9948         // Branch out of this block, don't need anything
9949         nr=0;
9950       }
9951       else
9952       {
9953         // Internal branch
9954         // Need whatever matches the target
9955         nr=0;
9956         int t=(ba[i]-start)>>2;
9957         for(hr=0;hr<HOST_REGS;hr++)
9958         {
9959           if(regs[i].regmap_entry[hr]>=0) {
9960             if(regs[i].regmap_entry[hr]==regs[t].regmap_entry[hr]) nr|=1<<hr;
9961           }
9962         }
9963       }
9964       // Conditional branch may need registers for following instructions
9965       if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
9966       {
9967         if(i<slen-2) {
9968           nr|=needed_reg[i+2];
9969           for(hr=0;hr<HOST_REGS;hr++)
9970           {
9971             if(regmap_pre[i+2][hr]>=0&&get_reg(regs[i+2].regmap_entry,regmap_pre[i+2][hr])<0) nr&=~(1<<hr);
9972             //if((regmap_entry[i+2][hr])>=0) if(!((nr>>hr)&1)) printf("%x-bogus(%d=%d)\n",start+i*4,hr,regmap_entry[i+2][hr]);
9973           }
9974         }
9975       }
9976       // Don't need stuff which is overwritten
9977       //if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr);
9978       //if(regs[i].regmap[hr]<0) nr&=~(1<<hr);
9979       // Merge in delay slot
9980       for(hr=0;hr<HOST_REGS;hr++)
9981       {
9982         if(!likely[i]) {
9983           // These are overwritten unless the branch is "likely"
9984           // and the delay slot is nullified if not taken
9985           if(rt1[i+1]&&rt1[i+1]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9986           if(rt2[i+1]&&rt2[i+1]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9987         }
9988         if(us1[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9989         if(us2[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9990         if(rs1[i+1]==regmap_pre[i][hr]) nr|=1<<hr;
9991         if(rs2[i+1]==regmap_pre[i][hr]) nr|=1<<hr;
9992         if(us1[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9993         if(us2[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9994         if(rs1[i+1]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9995         if(rs2[i+1]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9996         if(dep1[i+1]&&!((unneeded_reg_upper[i]>>dep1[i+1])&1)) {
9997           if(dep1[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9998           if(dep2[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9999         }
10000         if(dep2[i+1]&&!((unneeded_reg_upper[i]>>dep2[i+1])&1)) {
10001           if(dep1[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
10002           if(dep2[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
10003         }
10004         if(itype[i+1]==STORE || itype[i+1]==STORELR || (opcode[i+1]&0x3b)==0x39 || (opcode[i+1]&0x3b)==0x3a) {
10005           if(regmap_pre[i][hr]==INVCP) nr|=1<<hr;
10006           if(regs[i].regmap_entry[hr]==INVCP) nr|=1<<hr;
10007         }
10008       }
10009     }
10010     else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
10011     {
10012       // SYSCALL instruction (software interrupt)
10013       nr=0;
10014     }
10015     else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
10016     {
10017       // ERET instruction (return from interrupt)
10018       nr=0;
10019     }
10020     else // Non-branch
10021     {
10022       if(i<slen-1) {
10023         for(hr=0;hr<HOST_REGS;hr++) {
10024           if(regmap_pre[i+1][hr]>=0&&get_reg(regs[i+1].regmap_entry,regmap_pre[i+1][hr])<0) nr&=~(1<<hr);
10025           if(regs[i].regmap[hr]!=regmap_pre[i+1][hr]) nr&=~(1<<hr);
10026           if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr);
10027           if(regs[i].regmap[hr]<0) nr&=~(1<<hr);
10028         }
10029       }
10030     }
10031     for(hr=0;hr<HOST_REGS;hr++)
10032     {
10033       // Overwritten registers are not needed
10034       if(rt1[i]&&rt1[i]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
10035       if(rt2[i]&&rt2[i]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
10036       if(FTEMP==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
10037       // Source registers are needed
10038       if(us1[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
10039       if(us2[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
10040       if(rs1[i]==regmap_pre[i][hr]) nr|=1<<hr;
10041       if(rs2[i]==regmap_pre[i][hr]) nr|=1<<hr;
10042       if(us1[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
10043       if(us2[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
10044       if(rs1[i]==regs[i].regmap_entry[hr]) nr|=1<<hr;
10045       if(rs2[i]==regs[i].regmap_entry[hr]) nr|=1<<hr;
10046       if(dep1[i]&&!((unneeded_reg_upper[i]>>dep1[i])&1)) {
10047         if(dep1[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
10048         if(dep1[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
10049       }
10050       if(dep2[i]&&!((unneeded_reg_upper[i]>>dep2[i])&1)) {
10051         if(dep2[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
10052         if(dep2[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
10053       }
10054       if(itype[i]==STORE || itype[i]==STORELR || (opcode[i]&0x3b)==0x39 || (opcode[i]&0x3b)==0x3a) {
10055         if(regmap_pre[i][hr]==INVCP) nr|=1<<hr;
10056         if(regs[i].regmap_entry[hr]==INVCP) nr|=1<<hr;
10057       }
10058       // Don't store a register immediately after writing it,
10059       // may prevent dual-issue.
10060       // But do so if this is a branch target, otherwise we
10061       // might have to load the register before the branch.
10062       if(i>0&&!bt[i]&&((regs[i].wasdirty>>hr)&1)) {
10063         if((regmap_pre[i][hr]>0&&regmap_pre[i][hr]<64&&!((unneeded_reg[i]>>regmap_pre[i][hr])&1)) ||
10064            (regmap_pre[i][hr]>64&&!((unneeded_reg_upper[i]>>(regmap_pre[i][hr]&63))&1)) ) {
10065           if(rt1[i-1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
10066           if(rt2[i-1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
10067         }
10068         if((regs[i].regmap_entry[hr]>0&&regs[i].regmap_entry[hr]<64&&!((unneeded_reg[i]>>regs[i].regmap_entry[hr])&1)) ||
10069            (regs[i].regmap_entry[hr]>64&&!((unneeded_reg_upper[i]>>(regs[i].regmap_entry[hr]&63))&1)) ) {
10070           if(rt1[i-1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
10071           if(rt2[i-1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
10072         }
10073       }
10074     }
10075     // Cycle count is needed at branches.  Assume it is needed at the target too.
10076     if(i==0||bt[i]||itype[i]==CJUMP||itype[i]==FJUMP||itype[i]==SPAN) {
10077       if(regmap_pre[i][HOST_CCREG]==CCREG) nr|=1<<HOST_CCREG;
10078       if(regs[i].regmap_entry[HOST_CCREG]==CCREG) nr|=1<<HOST_CCREG;
10079     }
10080     // Save it
10081     needed_reg[i]=nr;
10082
10083     // Deallocate unneeded registers
10084     for(hr=0;hr<HOST_REGS;hr++)
10085     {
10086       if(!((nr>>hr)&1)) {
10087         if(regs[i].regmap_entry[hr]!=CCREG) regs[i].regmap_entry[hr]=-1;
10088         if((regs[i].regmap[hr]&63)!=rs1[i] && (regs[i].regmap[hr]&63)!=rs2[i] &&
10089            (regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] &&
10090            (regs[i].regmap[hr]&63)!=PTEMP && (regs[i].regmap[hr]&63)!=CCREG)
10091         {
10092           if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
10093           {
10094             if(likely[i]) {
10095               regs[i].regmap[hr]=-1;
10096               regs[i].isconst&=~(1<<hr);
10097               if(i<slen-2) {
10098                 regmap_pre[i+2][hr]=-1;
10099                 regs[i+2].wasconst&=~(1<<hr);
10100               }
10101             }
10102           }
10103         }
10104         if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
10105         {
10106           int d1=0,d2=0,map=0,temp=0;
10107           if(get_reg(regs[i].regmap,rt1[i+1]|64)>=0||get_reg(branch_regs[i].regmap,rt1[i+1]|64)>=0)
10108           {
10109             d1=dep1[i+1];
10110             d2=dep2[i+1];
10111           }
10112           if(using_tlb) {
10113             if(itype[i+1]==LOAD || itype[i+1]==LOADLR ||
10114                itype[i+1]==STORE || itype[i+1]==STORELR ||
10115                itype[i+1]==C1LS || itype[i+1]==C2LS)
10116             map=TLREG;
10117           } else
10118           if(itype[i+1]==STORE || itype[i+1]==STORELR ||
10119              (opcode[i+1]&0x3b)==0x39 || (opcode[i+1]&0x3b)==0x3a) { // SWC1/SDC1 || SWC2/SDC2
10120             map=INVCP;
10121           }
10122           if(itype[i+1]==LOADLR || itype[i+1]==STORELR ||
10123              itype[i+1]==C1LS || itype[i+1]==C2LS)
10124             temp=FTEMP;
10125           if((regs[i].regmap[hr]&63)!=rs1[i] && (regs[i].regmap[hr]&63)!=rs2[i] &&
10126              (regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] &&
10127              (regs[i].regmap[hr]&63)!=rt1[i+1] && (regs[i].regmap[hr]&63)!=rt2[i+1] &&
10128              (regs[i].regmap[hr]^64)!=us1[i+1] && (regs[i].regmap[hr]^64)!=us2[i+1] &&
10129              (regs[i].regmap[hr]^64)!=d1 && (regs[i].regmap[hr]^64)!=d2 &&
10130              regs[i].regmap[hr]!=rs1[i+1] && regs[i].regmap[hr]!=rs2[i+1] &&
10131              (regs[i].regmap[hr]&63)!=temp && regs[i].regmap[hr]!=PTEMP &&
10132              regs[i].regmap[hr]!=RHASH && regs[i].regmap[hr]!=RHTBL &&
10133              regs[i].regmap[hr]!=RTEMP && regs[i].regmap[hr]!=CCREG &&
10134              regs[i].regmap[hr]!=map )
10135           {
10136             regs[i].regmap[hr]=-1;
10137             regs[i].isconst&=~(1<<hr);
10138             if((branch_regs[i].regmap[hr]&63)!=rs1[i] && (branch_regs[i].regmap[hr]&63)!=rs2[i] &&
10139                (branch_regs[i].regmap[hr]&63)!=rt1[i] && (branch_regs[i].regmap[hr]&63)!=rt2[i] &&
10140                (branch_regs[i].regmap[hr]&63)!=rt1[i+1] && (branch_regs[i].regmap[hr]&63)!=rt2[i+1] &&
10141                (branch_regs[i].regmap[hr]^64)!=us1[i+1] && (branch_regs[i].regmap[hr]^64)!=us2[i+1] &&
10142                (branch_regs[i].regmap[hr]^64)!=d1 && (branch_regs[i].regmap[hr]^64)!=d2 &&
10143                branch_regs[i].regmap[hr]!=rs1[i+1] && branch_regs[i].regmap[hr]!=rs2[i+1] &&
10144                (branch_regs[i].regmap[hr]&63)!=temp && branch_regs[i].regmap[hr]!=PTEMP &&
10145                branch_regs[i].regmap[hr]!=RHASH && branch_regs[i].regmap[hr]!=RHTBL &&
10146                branch_regs[i].regmap[hr]!=RTEMP && branch_regs[i].regmap[hr]!=CCREG &&
10147                branch_regs[i].regmap[hr]!=map)
10148             {
10149               branch_regs[i].regmap[hr]=-1;
10150               branch_regs[i].regmap_entry[hr]=-1;
10151               if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
10152               {
10153                 if(!likely[i]&&i<slen-2) {
10154                   regmap_pre[i+2][hr]=-1;
10155                   regs[i+2].wasconst&=~(1<<hr);
10156                 }
10157               }
10158             }
10159           }
10160         }
10161         else
10162         {
10163           // Non-branch
10164           if(i>0)
10165           {
10166             int d1=0,d2=0,map=-1,temp=-1;
10167             if(get_reg(regs[i].regmap,rt1[i]|64)>=0)
10168             {
10169               d1=dep1[i];
10170               d2=dep2[i];
10171             }
10172             if(using_tlb) {
10173               if(itype[i]==LOAD || itype[i]==LOADLR ||
10174                  itype[i]==STORE || itype[i]==STORELR ||
10175                  itype[i]==C1LS || itype[i]==C2LS)
10176               map=TLREG;
10177             } else if(itype[i]==STORE || itype[i]==STORELR ||
10178                       (opcode[i]&0x3b)==0x39 || (opcode[i]&0x3b)==0x3a) { // SWC1/SDC1 || SWC2/SDC2
10179               map=INVCP;
10180             }
10181             if(itype[i]==LOADLR || itype[i]==STORELR ||
10182                itype[i]==C1LS || itype[i]==C2LS)
10183               temp=FTEMP;
10184             if((regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] &&
10185                (regs[i].regmap[hr]^64)!=us1[i] && (regs[i].regmap[hr]^64)!=us2[i] &&
10186                (regs[i].regmap[hr]^64)!=d1 && (regs[i].regmap[hr]^64)!=d2 &&
10187                regs[i].regmap[hr]!=rs1[i] && regs[i].regmap[hr]!=rs2[i] &&
10188                (regs[i].regmap[hr]&63)!=temp && regs[i].regmap[hr]!=map &&
10189                (itype[i]!=SPAN||regs[i].regmap[hr]!=CCREG))
10190             {
10191               if(i<slen-1&&!is_ds[i]) {
10192                 if(regmap_pre[i+1][hr]!=-1 || regs[i].regmap[hr]!=-1)
10193                 if(regmap_pre[i+1][hr]!=regs[i].regmap[hr])
10194                 if(regs[i].regmap[hr]<64||!((regs[i].was32>>(regs[i].regmap[hr]&63))&1))
10195                 {
10196                   SysPrintf("fail: %x (%d %d!=%d)\n",start+i*4,hr,regmap_pre[i+1][hr],regs[i].regmap[hr]);
10197                   assert(regmap_pre[i+1][hr]==regs[i].regmap[hr]);
10198                 }
10199                 regmap_pre[i+1][hr]=-1;
10200                 if(regs[i+1].regmap_entry[hr]==CCREG) regs[i+1].regmap_entry[hr]=-1;
10201                 regs[i+1].wasconst&=~(1<<hr);
10202               }
10203               regs[i].regmap[hr]=-1;
10204               regs[i].isconst&=~(1<<hr);
10205             }
10206           }
10207         }
10208       }
10209     }
10210   }
10211
10212   /* Pass 5 - Pre-allocate registers */
10213
10214   // If a register is allocated during a loop, try to allocate it for the
10215   // entire loop, if possible.  This avoids loading/storing registers
10216   // inside of the loop.
10217
10218   signed char f_regmap[HOST_REGS];
10219   clear_all_regs(f_regmap);
10220   for(i=0;i<slen-1;i++)
10221   {
10222     if(itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
10223     {
10224       if(ba[i]>=start && ba[i]<(start+i*4))
10225       if(itype[i+1]==NOP||itype[i+1]==MOV||itype[i+1]==ALU
10226       ||itype[i+1]==SHIFTIMM||itype[i+1]==IMM16||itype[i+1]==LOAD
10227       ||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS
10228       ||itype[i+1]==SHIFT||itype[i+1]==COP1||itype[i+1]==FLOAT
10229       ||itype[i+1]==FCOMP||itype[i+1]==FCONV
10230       ||itype[i+1]==COP2||itype[i+1]==C2LS||itype[i+1]==C2OP)
10231       {
10232         int t=(ba[i]-start)>>2;
10233         if(t>0&&(itype[t-1]!=UJUMP&&itype[t-1]!=RJUMP&&itype[t-1]!=CJUMP&&itype[t-1]!=SJUMP&&itype[t-1]!=FJUMP)) // loop_preload can't handle jumps into delay slots
10234         if(t<2||(itype[t-2]!=UJUMP&&itype[t-2]!=RJUMP)||rt1[t-2]!=31) // call/ret assumes no registers allocated
10235         for(hr=0;hr<HOST_REGS;hr++)
10236         {
10237           if(regs[i].regmap[hr]>64) {
10238             if(!((regs[i].dirty>>hr)&1))
10239               f_regmap[hr]=regs[i].regmap[hr];
10240             else f_regmap[hr]=-1;
10241           }
10242           else if(regs[i].regmap[hr]>=0) {
10243             if(f_regmap[hr]!=regs[i].regmap[hr]) {
10244               // dealloc old register
10245               int n;
10246               for(n=0;n<HOST_REGS;n++)
10247               {
10248                 if(f_regmap[n]==regs[i].regmap[hr]) {f_regmap[n]=-1;}
10249               }
10250               // and alloc new one
10251               f_regmap[hr]=regs[i].regmap[hr];
10252             }
10253           }
10254           if(branch_regs[i].regmap[hr]>64) {
10255             if(!((branch_regs[i].dirty>>hr)&1))
10256               f_regmap[hr]=branch_regs[i].regmap[hr];
10257             else f_regmap[hr]=-1;
10258           }
10259           else if(branch_regs[i].regmap[hr]>=0) {
10260             if(f_regmap[hr]!=branch_regs[i].regmap[hr]) {
10261               // dealloc old register
10262               int n;
10263               for(n=0;n<HOST_REGS;n++)
10264               {
10265                 if(f_regmap[n]==branch_regs[i].regmap[hr]) {f_regmap[n]=-1;}
10266               }
10267               // and alloc new one
10268               f_regmap[hr]=branch_regs[i].regmap[hr];
10269             }
10270           }
10271           if(ooo[i]) {
10272             if(count_free_regs(regs[i].regmap)<=minimum_free_regs[i+1])
10273               f_regmap[hr]=branch_regs[i].regmap[hr];
10274           }else{
10275             if(count_free_regs(branch_regs[i].regmap)<=minimum_free_regs[i+1])
10276               f_regmap[hr]=branch_regs[i].regmap[hr];
10277           }
10278           // Avoid dirty->clean transition
10279           #ifdef DESTRUCTIVE_WRITEBACK
10280           if(t>0) if(get_reg(regmap_pre[t],f_regmap[hr])>=0) if((regs[t].wasdirty>>get_reg(regmap_pre[t],f_regmap[hr]))&1) f_regmap[hr]=-1;
10281           #endif
10282           // This check is only strictly required in the DESTRUCTIVE_WRITEBACK
10283           // case above, however it's always a good idea.  We can't hoist the
10284           // load if the register was already allocated, so there's no point
10285           // wasting time analyzing most of these cases.  It only "succeeds"
10286           // when the mapping was different and the load can be replaced with
10287           // a mov, which is of negligible benefit.  So such cases are
10288           // skipped below.
10289           if(f_regmap[hr]>0) {
10290             if(regs[t].regmap[hr]==f_regmap[hr]||(regs[t].regmap_entry[hr]<0&&get_reg(regmap_pre[t],f_regmap[hr])<0)) {
10291               int r=f_regmap[hr];
10292               for(j=t;j<=i;j++)
10293               {
10294                 //printf("Test %x -> %x, %x %d/%d\n",start+i*4,ba[i],start+j*4,hr,r);
10295                 if(r<34&&((unneeded_reg[j]>>r)&1)) break;
10296                 if(r>63&&((unneeded_reg_upper[j]>>(r&63))&1)) break;
10297                 if(r>63) {
10298                   // NB This can exclude the case where the upper-half
10299                   // register is lower numbered than the lower-half
10300                   // register.  Not sure if it's worth fixing...
10301                   if(get_reg(regs[j].regmap,r&63)<0) break;
10302                   if(get_reg(regs[j].regmap_entry,r&63)<0) break;
10303                   if(regs[j].is32&(1LL<<(r&63))) break;
10304                 }
10305                 if(regs[j].regmap[hr]==f_regmap[hr]&&(f_regmap[hr]&63)<TEMPREG) {
10306                   //printf("Hit %x -> %x, %x %d/%d\n",start+i*4,ba[i],start+j*4,hr,r);
10307                   int k;
10308                   if(regs[i].regmap[hr]==-1&&branch_regs[i].regmap[hr]==-1) {
10309                     if(get_reg(regs[i+2].regmap,f_regmap[hr])>=0) break;
10310                     if(r>63) {
10311                       if(get_reg(regs[i].regmap,r&63)<0) break;
10312                       if(get_reg(branch_regs[i].regmap,r&63)<0) break;
10313                     }
10314                     k=i;
10315                     while(k>1&&regs[k-1].regmap[hr]==-1) {
10316                       if(count_free_regs(regs[k-1].regmap)<=minimum_free_regs[k-1]) {
10317                         //printf("no free regs for store %x\n",start+(k-1)*4);
10318                         break;
10319                       }
10320                       if(get_reg(regs[k-1].regmap,f_regmap[hr])>=0) {
10321                         //printf("no-match due to different register\n");
10322                         break;
10323                       }
10324                       if(itype[k-2]==UJUMP||itype[k-2]==RJUMP||itype[k-2]==CJUMP||itype[k-2]==SJUMP||itype[k-2]==FJUMP) {
10325                         //printf("no-match due to branch\n");
10326                         break;
10327                       }
10328                       // call/ret fast path assumes no registers allocated
10329                       if(k>2&&(itype[k-3]==UJUMP||itype[k-3]==RJUMP)&&rt1[k-3]==31) {
10330                         break;
10331                       }
10332                       if(r>63) {
10333                         // NB This can exclude the case where the upper-half
10334                         // register is lower numbered than the lower-half
10335                         // register.  Not sure if it's worth fixing...
10336                         if(get_reg(regs[k-1].regmap,r&63)<0) break;
10337                         if(regs[k-1].is32&(1LL<<(r&63))) break;
10338                       }
10339                       k--;
10340                     }
10341                     if(i<slen-1) {
10342                       if((regs[k].is32&(1LL<<f_regmap[hr]))!=
10343                         (regs[i+2].was32&(1LL<<f_regmap[hr]))) {
10344                         //printf("bad match after branch\n");
10345                         break;
10346                       }
10347                     }
10348                     if(regs[k-1].regmap[hr]==f_regmap[hr]&&regmap_pre[k][hr]==f_regmap[hr]) {
10349                       //printf("Extend r%d, %x ->\n",hr,start+k*4);
10350                       while(k<i) {
10351                         regs[k].regmap_entry[hr]=f_regmap[hr];
10352                         regs[k].regmap[hr]=f_regmap[hr];
10353                         regmap_pre[k+1][hr]=f_regmap[hr];
10354                         regs[k].wasdirty&=~(1<<hr);
10355                         regs[k].dirty&=~(1<<hr);
10356                         regs[k].wasdirty|=(1<<hr)&regs[k-1].dirty;
10357                         regs[k].dirty|=(1<<hr)&regs[k].wasdirty;
10358                         regs[k].wasconst&=~(1<<hr);
10359                         regs[k].isconst&=~(1<<hr);
10360                         k++;
10361                       }
10362                     }
10363                     else {
10364                       //printf("Fail Extend r%d, %x ->\n",hr,start+k*4);
10365                       break;
10366                     }
10367                     assert(regs[i-1].regmap[hr]==f_regmap[hr]);
10368                     if(regs[i-1].regmap[hr]==f_regmap[hr]&&regmap_pre[i][hr]==f_regmap[hr]) {
10369                       //printf("OK fill %x (r%d)\n",start+i*4,hr);
10370                       regs[i].regmap_entry[hr]=f_regmap[hr];
10371                       regs[i].regmap[hr]=f_regmap[hr];
10372                       regs[i].wasdirty&=~(1<<hr);
10373                       regs[i].dirty&=~(1<<hr);
10374                       regs[i].wasdirty|=(1<<hr)&regs[i-1].dirty;
10375                       regs[i].dirty|=(1<<hr)&regs[i-1].dirty;
10376                       regs[i].wasconst&=~(1<<hr);
10377                       regs[i].isconst&=~(1<<hr);
10378                       branch_regs[i].regmap_entry[hr]=f_regmap[hr];
10379                       branch_regs[i].wasdirty&=~(1<<hr);
10380                       branch_regs[i].wasdirty|=(1<<hr)&regs[i].dirty;
10381                       branch_regs[i].regmap[hr]=f_regmap[hr];
10382                       branch_regs[i].dirty&=~(1<<hr);
10383                       branch_regs[i].dirty|=(1<<hr)&regs[i].dirty;
10384                       branch_regs[i].wasconst&=~(1<<hr);
10385                       branch_regs[i].isconst&=~(1<<hr);
10386                       if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000) {
10387                         regmap_pre[i+2][hr]=f_regmap[hr];
10388                         regs[i+2].wasdirty&=~(1<<hr);
10389                         regs[i+2].wasdirty|=(1<<hr)&regs[i].dirty;
10390                         assert((branch_regs[i].is32&(1LL<<f_regmap[hr]))==
10391                           (regs[i+2].was32&(1LL<<f_regmap[hr])));
10392                       }
10393                     }
10394                   }
10395                   for(k=t;k<j;k++) {
10396                     // Alloc register clean at beginning of loop,
10397                     // but may dirty it in pass 6
10398                     regs[k].regmap_entry[hr]=f_regmap[hr];
10399                     regs[k].regmap[hr]=f_regmap[hr];
10400                     regs[k].dirty&=~(1<<hr);
10401                     regs[k].wasconst&=~(1<<hr);
10402                     regs[k].isconst&=~(1<<hr);
10403                     if(itype[k]==UJUMP||itype[k]==RJUMP||itype[k]==CJUMP||itype[k]==SJUMP||itype[k]==FJUMP) {
10404                       branch_regs[k].regmap_entry[hr]=f_regmap[hr];
10405                       branch_regs[k].regmap[hr]=f_regmap[hr];
10406                       branch_regs[k].dirty&=~(1<<hr);
10407                       branch_regs[k].wasconst&=~(1<<hr);
10408                       branch_regs[k].isconst&=~(1<<hr);
10409                       if(itype[k]!=RJUMP&&itype[k]!=UJUMP&&(source[k]>>16)!=0x1000) {
10410                         regmap_pre[k+2][hr]=f_regmap[hr];
10411                         regs[k+2].wasdirty&=~(1<<hr);
10412                         assert((branch_regs[k].is32&(1LL<<f_regmap[hr]))==
10413                           (regs[k+2].was32&(1LL<<f_regmap[hr])));
10414                       }
10415                     }
10416                     else
10417                     {
10418                       regmap_pre[k+1][hr]=f_regmap[hr];
10419                       regs[k+1].wasdirty&=~(1<<hr);
10420                     }
10421                   }
10422                   if(regs[j].regmap[hr]==f_regmap[hr])
10423                     regs[j].regmap_entry[hr]=f_regmap[hr];
10424                   break;
10425                 }
10426                 if(j==i) break;
10427                 if(regs[j].regmap[hr]>=0)
10428                   break;
10429                 if(get_reg(regs[j].regmap,f_regmap[hr])>=0) {
10430                   //printf("no-match due to different register\n");
10431                   break;
10432                 }
10433                 if((regs[j+1].is32&(1LL<<f_regmap[hr]))!=(regs[j].is32&(1LL<<f_regmap[hr]))) {
10434                   //printf("32/64 mismatch %x %d\n",start+j*4,hr);
10435                   break;
10436                 }
10437                 if(itype[j]==UJUMP||itype[j]==RJUMP||(source[j]>>16)==0x1000)
10438                 {
10439                   // Stop on unconditional branch
10440                   break;
10441                 }
10442                 if(itype[j]==CJUMP||itype[j]==SJUMP||itype[j]==FJUMP)
10443                 {
10444                   if(ooo[j]) {
10445                     if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j+1])
10446                       break;
10447                   }else{
10448                     if(count_free_regs(branch_regs[j].regmap)<=minimum_free_regs[j+1])
10449                       break;
10450                   }
10451                   if(get_reg(branch_regs[j].regmap,f_regmap[hr])>=0) {
10452                     //printf("no-match due to different register (branch)\n");
10453                     break;
10454                   }
10455                 }
10456                 if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j]) {
10457                   //printf("No free regs for store %x\n",start+j*4);
10458                   break;
10459                 }
10460                 if(f_regmap[hr]>=64) {
10461                   if(regs[j].is32&(1LL<<(f_regmap[hr]&63))) {
10462                     break;
10463                   }
10464                   else
10465                   {
10466                     if(get_reg(regs[j].regmap,f_regmap[hr]&63)<0) {
10467                       break;
10468                     }
10469                   }
10470                 }
10471               }
10472             }
10473           }
10474         }
10475       }
10476     }else{
10477       // Non branch or undetermined branch target
10478       for(hr=0;hr<HOST_REGS;hr++)
10479       {
10480         if(hr!=EXCLUDE_REG) {
10481           if(regs[i].regmap[hr]>64) {
10482             if(!((regs[i].dirty>>hr)&1))
10483               f_regmap[hr]=regs[i].regmap[hr];
10484           }
10485           else if(regs[i].regmap[hr]>=0) {
10486             if(f_regmap[hr]!=regs[i].regmap[hr]) {
10487               // dealloc old register
10488               int n;
10489               for(n=0;n<HOST_REGS;n++)
10490               {
10491                 if(f_regmap[n]==regs[i].regmap[hr]) {f_regmap[n]=-1;}
10492               }
10493               // and alloc new one
10494               f_regmap[hr]=regs[i].regmap[hr];
10495             }
10496           }
10497         }
10498       }
10499       // Try to restore cycle count at branch targets
10500       if(bt[i]) {
10501         for(j=i;j<slen-1;j++) {
10502           if(regs[j].regmap[HOST_CCREG]!=-1) break;
10503           if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j]) {
10504             //printf("no free regs for store %x\n",start+j*4);
10505             break;
10506           }
10507         }
10508         if(regs[j].regmap[HOST_CCREG]==CCREG) {
10509           int k=i;
10510           //printf("Extend CC, %x -> %x\n",start+k*4,start+j*4);
10511           while(k<j) {
10512             regs[k].regmap_entry[HOST_CCREG]=CCREG;
10513             regs[k].regmap[HOST_CCREG]=CCREG;
10514             regmap_pre[k+1][HOST_CCREG]=CCREG;
10515             regs[k+1].wasdirty|=1<<HOST_CCREG;
10516             regs[k].dirty|=1<<HOST_CCREG;
10517             regs[k].wasconst&=~(1<<HOST_CCREG);
10518             regs[k].isconst&=~(1<<HOST_CCREG);
10519             k++;
10520           }
10521           regs[j].regmap_entry[HOST_CCREG]=CCREG;
10522         }
10523         // Work backwards from the branch target
10524         if(j>i&&f_regmap[HOST_CCREG]==CCREG)
10525         {
10526           //printf("Extend backwards\n");
10527           int k;
10528           k=i;
10529           while(regs[k-1].regmap[HOST_CCREG]==-1) {
10530             if(count_free_regs(regs[k-1].regmap)<=minimum_free_regs[k-1]) {
10531               //printf("no free regs for store %x\n",start+(k-1)*4);
10532               break;
10533             }
10534             k--;
10535           }
10536           if(regs[k-1].regmap[HOST_CCREG]==CCREG) {
10537             //printf("Extend CC, %x ->\n",start+k*4);
10538             while(k<=i) {
10539               regs[k].regmap_entry[HOST_CCREG]=CCREG;
10540               regs[k].regmap[HOST_CCREG]=CCREG;
10541               regmap_pre[k+1][HOST_CCREG]=CCREG;
10542               regs[k+1].wasdirty|=1<<HOST_CCREG;
10543               regs[k].dirty|=1<<HOST_CCREG;
10544               regs[k].wasconst&=~(1<<HOST_CCREG);
10545               regs[k].isconst&=~(1<<HOST_CCREG);
10546               k++;
10547             }
10548           }
10549           else {
10550             //printf("Fail Extend CC, %x ->\n",start+k*4);
10551           }
10552         }
10553       }
10554       if(itype[i]!=STORE&&itype[i]!=STORELR&&itype[i]!=C1LS&&itype[i]!=SHIFT&&
10555          itype[i]!=NOP&&itype[i]!=MOV&&itype[i]!=ALU&&itype[i]!=SHIFTIMM&&
10556          itype[i]!=IMM16&&itype[i]!=LOAD&&itype[i]!=COP1&&itype[i]!=FLOAT&&
10557          itype[i]!=FCONV&&itype[i]!=FCOMP)
10558       {
10559         memcpy(f_regmap,regs[i].regmap,sizeof(f_regmap));
10560       }
10561     }
10562   }
10563
10564   // Cache memory offset or tlb map pointer if a register is available
10565   #ifndef HOST_IMM_ADDR32
10566   #ifndef RAM_OFFSET
10567   if(using_tlb)
10568   #endif
10569   {
10570     int earliest_available[HOST_REGS];
10571     int loop_start[HOST_REGS];
10572     int score[HOST_REGS];
10573     int end[HOST_REGS];
10574     int reg=using_tlb?MMREG:ROREG;
10575
10576     // Init
10577     for(hr=0;hr<HOST_REGS;hr++) {
10578       score[hr]=0;earliest_available[hr]=0;
10579       loop_start[hr]=MAXBLOCK;
10580     }
10581     for(i=0;i<slen-1;i++)
10582     {
10583       // Can't do anything if no registers are available
10584       if(count_free_regs(regs[i].regmap)<=minimum_free_regs[i]) {
10585         for(hr=0;hr<HOST_REGS;hr++) {
10586           score[hr]=0;earliest_available[hr]=i+1;
10587           loop_start[hr]=MAXBLOCK;
10588         }
10589       }
10590       if(itype[i]==UJUMP||itype[i]==RJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP) {
10591         if(!ooo[i]) {
10592           if(count_free_regs(branch_regs[i].regmap)<=minimum_free_regs[i+1]) {
10593             for(hr=0;hr<HOST_REGS;hr++) {
10594               score[hr]=0;earliest_available[hr]=i+1;
10595               loop_start[hr]=MAXBLOCK;
10596             }
10597           }
10598         }else{
10599           if(count_free_regs(regs[i].regmap)<=minimum_free_regs[i+1]) {
10600             for(hr=0;hr<HOST_REGS;hr++) {
10601               score[hr]=0;earliest_available[hr]=i+1;
10602               loop_start[hr]=MAXBLOCK;
10603             }
10604           }
10605         }
10606       }
10607       // Mark unavailable registers
10608       for(hr=0;hr<HOST_REGS;hr++) {
10609         if(regs[i].regmap[hr]>=0) {
10610           score[hr]=0;earliest_available[hr]=i+1;
10611           loop_start[hr]=MAXBLOCK;
10612         }
10613         if(itype[i]==UJUMP||itype[i]==RJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP) {
10614           if(branch_regs[i].regmap[hr]>=0) {
10615             score[hr]=0;earliest_available[hr]=i+2;
10616             loop_start[hr]=MAXBLOCK;
10617           }
10618         }
10619       }
10620       // No register allocations after unconditional jumps
10621       if(itype[i]==UJUMP||itype[i]==RJUMP||(source[i]>>16)==0x1000)
10622       {
10623         for(hr=0;hr<HOST_REGS;hr++) {
10624           score[hr]=0;earliest_available[hr]=i+2;
10625           loop_start[hr]=MAXBLOCK;
10626         }
10627         i++; // Skip delay slot too
10628         //printf("skip delay slot: %x\n",start+i*4);
10629       }
10630       else
10631       // Possible match
10632       if(itype[i]==LOAD||itype[i]==LOADLR||
10633          itype[i]==STORE||itype[i]==STORELR||itype[i]==C1LS) {
10634         for(hr=0;hr<HOST_REGS;hr++) {
10635           if(hr!=EXCLUDE_REG) {
10636             end[hr]=i-1;
10637             for(j=i;j<slen-1;j++) {
10638               if(regs[j].regmap[hr]>=0) break;
10639               if(itype[j]==UJUMP||itype[j]==RJUMP||itype[j]==CJUMP||itype[j]==SJUMP||itype[j]==FJUMP) {
10640                 if(branch_regs[j].regmap[hr]>=0) break;
10641                 if(ooo[j]) {
10642                   if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j+1]) break;
10643                 }else{
10644                   if(count_free_regs(branch_regs[j].regmap)<=minimum_free_regs[j+1]) break;
10645                 }
10646               }
10647               else if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j]) break;
10648               if(itype[j]==UJUMP||itype[j]==RJUMP||itype[j]==CJUMP||itype[j]==SJUMP||itype[j]==FJUMP) {
10649                 int t=(ba[j]-start)>>2;
10650                 if(t<j&&t>=earliest_available[hr]) {
10651                   if(t==1||(t>1&&itype[t-2]!=UJUMP&&itype[t-2]!=RJUMP)||(t>1&&rt1[t-2]!=31)) { // call/ret assumes no registers allocated
10652                     // Score a point for hoisting loop invariant
10653                     if(t<loop_start[hr]) loop_start[hr]=t;
10654                     //printf("set loop_start: i=%x j=%x (%x)\n",start+i*4,start+j*4,start+t*4);
10655                     score[hr]++;
10656                     end[hr]=j;
10657                   }
10658                 }
10659                 else if(t<j) {
10660                   if(regs[t].regmap[hr]==reg) {
10661                     // Score a point if the branch target matches this register
10662                     score[hr]++;
10663                     end[hr]=j;
10664                   }
10665                 }
10666                 if(itype[j+1]==LOAD||itype[j+1]==LOADLR||
10667                    itype[j+1]==STORE||itype[j+1]==STORELR||itype[j+1]==C1LS) {
10668                   score[hr]++;
10669                   end[hr]=j;
10670                 }
10671               }
10672               if(itype[j]==UJUMP||itype[j]==RJUMP||(source[j]>>16)==0x1000)
10673               {
10674                 // Stop on unconditional branch
10675                 break;
10676               }
10677               else
10678               if(itype[j]==LOAD||itype[j]==LOADLR||
10679                  itype[j]==STORE||itype[j]==STORELR||itype[j]==C1LS) {
10680                 score[hr]++;
10681                 end[hr]=j;
10682               }
10683             }
10684           }
10685         }
10686         // Find highest score and allocate that register
10687         int maxscore=0;
10688         for(hr=0;hr<HOST_REGS;hr++) {
10689           if(hr!=EXCLUDE_REG) {
10690             if(score[hr]>score[maxscore]) {
10691               maxscore=hr;
10692               //printf("highest score: %d %d (%x->%x)\n",score[hr],hr,start+i*4,start+end[hr]*4);
10693             }
10694           }
10695         }
10696         if(score[maxscore]>1)
10697         {
10698           if(i<loop_start[maxscore]) loop_start[maxscore]=i;
10699           for(j=loop_start[maxscore];j<slen&&j<=end[maxscore];j++) {
10700             //if(regs[j].regmap[maxscore]>=0) {printf("oops: %x %x was %d=%d\n",loop_start[maxscore]*4+start,j*4+start,maxscore,regs[j].regmap[maxscore]);}
10701             assert(regs[j].regmap[maxscore]<0);
10702             if(j>loop_start[maxscore]) regs[j].regmap_entry[maxscore]=reg;
10703             regs[j].regmap[maxscore]=reg;
10704             regs[j].dirty&=~(1<<maxscore);
10705             regs[j].wasconst&=~(1<<maxscore);
10706             regs[j].isconst&=~(1<<maxscore);
10707             if(itype[j]==UJUMP||itype[j]==RJUMP||itype[j]==CJUMP||itype[j]==SJUMP||itype[j]==FJUMP) {
10708               branch_regs[j].regmap[maxscore]=reg;
10709               branch_regs[j].wasdirty&=~(1<<maxscore);
10710               branch_regs[j].dirty&=~(1<<maxscore);
10711               branch_regs[j].wasconst&=~(1<<maxscore);
10712               branch_regs[j].isconst&=~(1<<maxscore);
10713               if(itype[j]!=RJUMP&&itype[j]!=UJUMP&&(source[j]>>16)!=0x1000) {
10714                 regmap_pre[j+2][maxscore]=reg;
10715                 regs[j+2].wasdirty&=~(1<<maxscore);
10716               }
10717               // loop optimization (loop_preload)
10718               int t=(ba[j]-start)>>2;
10719               if(t==loop_start[maxscore]) {
10720                 if(t==1||(t>1&&itype[t-2]!=UJUMP&&itype[t-2]!=RJUMP)||(t>1&&rt1[t-2]!=31)) // call/ret assumes no registers allocated
10721                   regs[t].regmap_entry[maxscore]=reg;
10722               }
10723             }
10724             else
10725             {
10726               if(j<1||(itype[j-1]!=RJUMP&&itype[j-1]!=UJUMP&&itype[j-1]!=CJUMP&&itype[j-1]!=SJUMP&&itype[j-1]!=FJUMP)) {
10727                 regmap_pre[j+1][maxscore]=reg;
10728                 regs[j+1].wasdirty&=~(1<<maxscore);
10729               }
10730             }
10731           }
10732           i=j-1;
10733           if(itype[j-1]==RJUMP||itype[j-1]==UJUMP||itype[j-1]==CJUMP||itype[j-1]==SJUMP||itype[j-1]==FJUMP) i++; // skip delay slot
10734           for(hr=0;hr<HOST_REGS;hr++) {
10735             score[hr]=0;earliest_available[hr]=i+i;
10736             loop_start[hr]=MAXBLOCK;
10737           }
10738         }
10739       }
10740     }
10741   }
10742   #endif
10743
10744   // This allocates registers (if possible) one instruction prior
10745   // to use, which can avoid a load-use penalty on certain CPUs.
10746   for(i=0;i<slen-1;i++)
10747   {
10748     if(!i||(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP))
10749     {
10750       if(!bt[i+1])
10751       {
10752         if(itype[i]==ALU||itype[i]==MOV||itype[i]==LOAD||itype[i]==SHIFTIMM||itype[i]==IMM16
10753            ||((itype[i]==COP1||itype[i]==COP2)&&opcode2[i]<3))
10754         {
10755           if(rs1[i+1]) {
10756             if((hr=get_reg(regs[i+1].regmap,rs1[i+1]))>=0)
10757             {
10758               if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10759               {
10760                 regs[i].regmap[hr]=regs[i+1].regmap[hr];
10761                 regmap_pre[i+1][hr]=regs[i+1].regmap[hr];
10762                 regs[i+1].regmap_entry[hr]=regs[i+1].regmap[hr];
10763                 regs[i].isconst&=~(1<<hr);
10764                 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10765                 constmap[i][hr]=constmap[i+1][hr];
10766                 regs[i+1].wasdirty&=~(1<<hr);
10767                 regs[i].dirty&=~(1<<hr);
10768               }
10769             }
10770           }
10771           if(rs2[i+1]) {
10772             if((hr=get_reg(regs[i+1].regmap,rs2[i+1]))>=0)
10773             {
10774               if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10775               {
10776                 regs[i].regmap[hr]=regs[i+1].regmap[hr];
10777                 regmap_pre[i+1][hr]=regs[i+1].regmap[hr];
10778                 regs[i+1].regmap_entry[hr]=regs[i+1].regmap[hr];
10779                 regs[i].isconst&=~(1<<hr);
10780                 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10781                 constmap[i][hr]=constmap[i+1][hr];
10782                 regs[i+1].wasdirty&=~(1<<hr);
10783                 regs[i].dirty&=~(1<<hr);
10784               }
10785             }
10786           }
10787           // Preload target address for load instruction (non-constant)
10788           if(itype[i+1]==LOAD&&rs1[i+1]&&get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10789             if((hr=get_reg(regs[i+1].regmap,rt1[i+1]))>=0)
10790             {
10791               if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10792               {
10793                 regs[i].regmap[hr]=rs1[i+1];
10794                 regmap_pre[i+1][hr]=rs1[i+1];
10795                 regs[i+1].regmap_entry[hr]=rs1[i+1];
10796                 regs[i].isconst&=~(1<<hr);
10797                 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10798                 constmap[i][hr]=constmap[i+1][hr];
10799                 regs[i+1].wasdirty&=~(1<<hr);
10800                 regs[i].dirty&=~(1<<hr);
10801               }
10802             }
10803           }
10804           // Load source into target register
10805           if(lt1[i+1]&&get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10806             if((hr=get_reg(regs[i+1].regmap,rt1[i+1]))>=0)
10807             {
10808               if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10809               {
10810                 regs[i].regmap[hr]=rs1[i+1];
10811                 regmap_pre[i+1][hr]=rs1[i+1];
10812                 regs[i+1].regmap_entry[hr]=rs1[i+1];
10813                 regs[i].isconst&=~(1<<hr);
10814                 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10815                 constmap[i][hr]=constmap[i+1][hr];
10816                 regs[i+1].wasdirty&=~(1<<hr);
10817                 regs[i].dirty&=~(1<<hr);
10818               }
10819             }
10820           }
10821           // Preload map address
10822           #ifndef HOST_IMM_ADDR32
10823           if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS||itype[i+1]==C2LS) {
10824             hr=get_reg(regs[i+1].regmap,TLREG);
10825             if(hr>=0) {
10826               int sr=get_reg(regs[i+1].regmap,rs1[i+1]);
10827               if(sr>=0&&((regs[i+1].wasconst>>sr)&1)) {
10828                 int nr;
10829                 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10830                 {
10831                   regs[i].regmap[hr]=MGEN1+((i+1)&1);
10832                   regmap_pre[i+1][hr]=MGEN1+((i+1)&1);
10833                   regs[i+1].regmap_entry[hr]=MGEN1+((i+1)&1);
10834                   regs[i].isconst&=~(1<<hr);
10835                   regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10836                   constmap[i][hr]=constmap[i+1][hr];
10837                   regs[i+1].wasdirty&=~(1<<hr);
10838                   regs[i].dirty&=~(1<<hr);
10839                 }
10840                 else if((nr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1))>=0)
10841                 {
10842                   // move it to another register
10843                   regs[i+1].regmap[hr]=-1;
10844                   regmap_pre[i+2][hr]=-1;
10845                   regs[i+1].regmap[nr]=TLREG;
10846                   regmap_pre[i+2][nr]=TLREG;
10847                   regs[i].regmap[nr]=MGEN1+((i+1)&1);
10848                   regmap_pre[i+1][nr]=MGEN1+((i+1)&1);
10849                   regs[i+1].regmap_entry[nr]=MGEN1+((i+1)&1);
10850                   regs[i].isconst&=~(1<<nr);
10851                   regs[i+1].isconst&=~(1<<nr);
10852                   regs[i].dirty&=~(1<<nr);
10853                   regs[i+1].wasdirty&=~(1<<nr);
10854                   regs[i+1].dirty&=~(1<<nr);
10855                   regs[i+2].wasdirty&=~(1<<nr);
10856                 }
10857               }
10858             }
10859           }
10860           #endif
10861           // Address for store instruction (non-constant)
10862           if(itype[i+1]==STORE||itype[i+1]==STORELR
10863              ||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a) { // SB/SH/SW/SD/SWC1/SDC1/SWC2/SDC2
10864             if(get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10865               hr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1);
10866               if(hr<0) hr=get_reg(regs[i+1].regmap,-1);
10867               else {regs[i+1].regmap[hr]=AGEN1+((i+1)&1);regs[i+1].isconst&=~(1<<hr);}
10868               assert(hr>=0);
10869               if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10870               {
10871                 regs[i].regmap[hr]=rs1[i+1];
10872                 regmap_pre[i+1][hr]=rs1[i+1];
10873                 regs[i+1].regmap_entry[hr]=rs1[i+1];
10874                 regs[i].isconst&=~(1<<hr);
10875                 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10876                 constmap[i][hr]=constmap[i+1][hr];
10877                 regs[i+1].wasdirty&=~(1<<hr);
10878                 regs[i].dirty&=~(1<<hr);
10879               }
10880             }
10881           }
10882           if(itype[i+1]==LOADLR||(opcode[i+1]&0x3b)==0x31||(opcode[i+1]&0x3b)==0x32) { // LWC1/LDC1, LWC2/LDC2
10883             if(get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10884               int nr;
10885               hr=get_reg(regs[i+1].regmap,FTEMP);
10886               assert(hr>=0);
10887               if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10888               {
10889                 regs[i].regmap[hr]=rs1[i+1];
10890                 regmap_pre[i+1][hr]=rs1[i+1];
10891                 regs[i+1].regmap_entry[hr]=rs1[i+1];
10892                 regs[i].isconst&=~(1<<hr);
10893                 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10894                 constmap[i][hr]=constmap[i+1][hr];
10895                 regs[i+1].wasdirty&=~(1<<hr);
10896                 regs[i].dirty&=~(1<<hr);
10897               }
10898               else if((nr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1))>=0)
10899               {
10900                 // move it to another register
10901                 regs[i+1].regmap[hr]=-1;
10902                 regmap_pre[i+2][hr]=-1;
10903                 regs[i+1].regmap[nr]=FTEMP;
10904                 regmap_pre[i+2][nr]=FTEMP;
10905                 regs[i].regmap[nr]=rs1[i+1];
10906                 regmap_pre[i+1][nr]=rs1[i+1];
10907                 regs[i+1].regmap_entry[nr]=rs1[i+1];
10908                 regs[i].isconst&=~(1<<nr);
10909                 regs[i+1].isconst&=~(1<<nr);
10910                 regs[i].dirty&=~(1<<nr);
10911                 regs[i+1].wasdirty&=~(1<<nr);
10912                 regs[i+1].dirty&=~(1<<nr);
10913                 regs[i+2].wasdirty&=~(1<<nr);
10914               }
10915             }
10916           }
10917           if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR/*||itype[i+1]==C1LS||||itype[i+1]==C2LS*/) {
10918             if(itype[i+1]==LOAD)
10919               hr=get_reg(regs[i+1].regmap,rt1[i+1]);
10920             if(itype[i+1]==LOADLR||(opcode[i+1]&0x3b)==0x31||(opcode[i+1]&0x3b)==0x32) // LWC1/LDC1, LWC2/LDC2
10921               hr=get_reg(regs[i+1].regmap,FTEMP);
10922             if(itype[i+1]==STORE||itype[i+1]==STORELR||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a) { // SWC1/SDC1/SWC2/SDC2
10923               hr=get_reg(regs[i+1].regmap,AGEN1+((i+1)&1));
10924               if(hr<0) hr=get_reg(regs[i+1].regmap,-1);
10925             }
10926             if(hr>=0&&regs[i].regmap[hr]<0) {
10927               int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
10928               if(rs>=0&&((regs[i+1].wasconst>>rs)&1)) {
10929                 regs[i].regmap[hr]=AGEN1+((i+1)&1);
10930                 regmap_pre[i+1][hr]=AGEN1+((i+1)&1);
10931                 regs[i+1].regmap_entry[hr]=AGEN1+((i+1)&1);
10932                 regs[i].isconst&=~(1<<hr);
10933                 regs[i+1].wasdirty&=~(1<<hr);
10934                 regs[i].dirty&=~(1<<hr);
10935               }
10936             }
10937           }
10938         }
10939       }
10940     }
10941   }
10942
10943   /* Pass 6 - Optimize clean/dirty state */
10944   clean_registers(0,slen-1,1);
10945
10946   /* Pass 7 - Identify 32-bit registers */
10947 #ifndef FORCE32
10948   provisional_r32();
10949
10950   u_int r32=0;
10951
10952   for (i=slen-1;i>=0;i--)
10953   {
10954     int hr;
10955     if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
10956     {
10957       if(ba[i]<start || ba[i]>=(start+slen*4))
10958       {
10959         // Branch out of this block, don't need anything
10960         r32=0;
10961       }
10962       else
10963       {
10964         // Internal branch
10965         // Need whatever matches the target
10966         // (and doesn't get overwritten by the delay slot instruction)
10967         r32=0;
10968         int t=(ba[i]-start)>>2;
10969         if(ba[i]>start+i*4) {
10970           // Forward branch
10971           if(!(requires_32bit[t]&~regs[i].was32))
10972             r32|=requires_32bit[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
10973         }else{
10974           // Backward branch
10975           //if(!(regs[t].was32&~unneeded_reg_upper[t]&~regs[i].was32))
10976           //  r32|=regs[t].was32&~unneeded_reg_upper[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
10977           if(!(pr32[t]&~regs[i].was32))
10978             r32|=pr32[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
10979         }
10980       }
10981       // Conditional branch may need registers for following instructions
10982       if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
10983       {
10984         if(i<slen-2) {
10985           r32|=requires_32bit[i+2];
10986           r32&=regs[i].was32;
10987           // Mark this address as a branch target since it may be called
10988           // upon return from interrupt
10989           bt[i+2]=1;
10990         }
10991       }
10992       // Merge in delay slot
10993       if(!likely[i]) {
10994         // These are overwritten unless the branch is "likely"
10995         // and the delay slot is nullified if not taken
10996         r32&=~(1LL<<rt1[i+1]);
10997         r32&=~(1LL<<rt2[i+1]);
10998       }
10999       // Assume these are needed (delay slot)
11000       if(us1[i+1]>0)
11001       {
11002         if((regs[i].was32>>us1[i+1])&1) r32|=1LL<<us1[i+1];
11003       }
11004       if(us2[i+1]>0)
11005       {
11006         if((regs[i].was32>>us2[i+1])&1) r32|=1LL<<us2[i+1];
11007       }
11008       if(dep1[i+1]&&!((unneeded_reg_upper[i]>>dep1[i+1])&1))
11009       {
11010         if((regs[i].was32>>dep1[i+1])&1) r32|=1LL<<dep1[i+1];
11011       }
11012       if(dep2[i+1]&&!((unneeded_reg_upper[i]>>dep2[i+1])&1))
11013       {
11014         if((regs[i].was32>>dep2[i+1])&1) r32|=1LL<<dep2[i+1];
11015       }
11016     }
11017     else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
11018     {
11019       // SYSCALL instruction (software interrupt)
11020       r32=0;
11021     }
11022     else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
11023     {
11024       // ERET instruction (return from interrupt)
11025       r32=0;
11026     }
11027     // Check 32 bits
11028     r32&=~(1LL<<rt1[i]);
11029     r32&=~(1LL<<rt2[i]);
11030     if(us1[i]>0)
11031     {
11032       if((regs[i].was32>>us1[i])&1) r32|=1LL<<us1[i];
11033     }
11034     if(us2[i]>0)
11035     {
11036       if((regs[i].was32>>us2[i])&1) r32|=1LL<<us2[i];
11037     }
11038     if(dep1[i]&&!((unneeded_reg_upper[i]>>dep1[i])&1))
11039     {
11040       if((regs[i].was32>>dep1[i])&1) r32|=1LL<<dep1[i];
11041     }
11042     if(dep2[i]&&!((unneeded_reg_upper[i]>>dep2[i])&1))
11043     {
11044       if((regs[i].was32>>dep2[i])&1) r32|=1LL<<dep2[i];
11045     }
11046     requires_32bit[i]=r32;
11047
11048     // Dirty registers which are 32-bit, require 32-bit input
11049     // as they will be written as 32-bit values
11050     for(hr=0;hr<HOST_REGS;hr++)
11051     {
11052       if(regs[i].regmap_entry[hr]>0&&regs[i].regmap_entry[hr]<64) {
11053         if((regs[i].was32>>regs[i].regmap_entry[hr])&(regs[i].wasdirty>>hr)&1) {
11054           if(!((unneeded_reg_upper[i]>>regs[i].regmap_entry[hr])&1))
11055           requires_32bit[i]|=1LL<<regs[i].regmap_entry[hr];
11056         }
11057       }
11058     }
11059     //requires_32bit[i]=is32[i]&~unneeded_reg_upper[i]; // DEBUG
11060   }
11061 #else
11062   for (i=slen-1;i>=0;i--)
11063   {
11064     if(itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
11065     {
11066       // Conditional branch
11067       if((source[i]>>16)!=0x1000&&i<slen-2) {
11068         // Mark this address as a branch target since it may be called
11069         // upon return from interrupt
11070         bt[i+2]=1;
11071       }
11072     }
11073   }
11074 #endif
11075
11076   if(itype[slen-1]==SPAN) {
11077     bt[slen-1]=1; // Mark as a branch target so instruction can restart after exception
11078   }
11079
11080 #ifdef DISASM
11081   /* Debug/disassembly */
11082   for(i=0;i<slen;i++)
11083   {
11084     printf("U:");
11085     int r;
11086     for(r=1;r<=CCREG;r++) {
11087       if((unneeded_reg[i]>>r)&1) {
11088         if(r==HIREG) printf(" HI");
11089         else if(r==LOREG) printf(" LO");
11090         else printf(" r%d",r);
11091       }
11092     }
11093 #ifndef FORCE32
11094     printf(" UU:");
11095     for(r=1;r<=CCREG;r++) {
11096       if(((unneeded_reg_upper[i]&~unneeded_reg[i])>>r)&1) {
11097         if(r==HIREG) printf(" HI");
11098         else if(r==LOREG) printf(" LO");
11099         else printf(" r%d",r);
11100       }
11101     }
11102     printf(" 32:");
11103     for(r=0;r<=CCREG;r++) {
11104       //if(((is32[i]>>r)&(~unneeded_reg[i]>>r))&1) {
11105       if((regs[i].was32>>r)&1) {
11106         if(r==CCREG) printf(" CC");
11107         else if(r==HIREG) printf(" HI");
11108         else if(r==LOREG) printf(" LO");
11109         else printf(" r%d",r);
11110       }
11111     }
11112 #endif
11113     printf("\n");
11114     #if defined(__i386__) || defined(__x86_64__)
11115     printf("pre: eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",regmap_pre[i][0],regmap_pre[i][1],regmap_pre[i][2],regmap_pre[i][3],regmap_pre[i][5],regmap_pre[i][6],regmap_pre[i][7]);
11116     #endif
11117     #ifdef __arm__
11118     printf("pre: r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d\n",regmap_pre[i][0],regmap_pre[i][1],regmap_pre[i][2],regmap_pre[i][3],regmap_pre[i][4],regmap_pre[i][5],regmap_pre[i][6],regmap_pre[i][7],regmap_pre[i][8],regmap_pre[i][9],regmap_pre[i][10],regmap_pre[i][12]);
11119     #endif
11120     printf("needs: ");
11121     if(needed_reg[i]&1) printf("eax ");
11122     if((needed_reg[i]>>1)&1) printf("ecx ");
11123     if((needed_reg[i]>>2)&1) printf("edx ");
11124     if((needed_reg[i]>>3)&1) printf("ebx ");
11125     if((needed_reg[i]>>5)&1) printf("ebp ");
11126     if((needed_reg[i]>>6)&1) printf("esi ");
11127     if((needed_reg[i]>>7)&1) printf("edi ");
11128     printf("r:");
11129     for(r=0;r<=CCREG;r++) {
11130       //if(((requires_32bit[i]>>r)&(~unneeded_reg[i]>>r))&1) {
11131       if((requires_32bit[i]>>r)&1) {
11132         if(r==CCREG) printf(" CC");
11133         else if(r==HIREG) printf(" HI");
11134         else if(r==LOREG) printf(" LO");
11135         else printf(" r%d",r);
11136       }
11137     }
11138     printf("\n");
11139     /*printf("pr:");
11140     for(r=0;r<=CCREG;r++) {
11141       //if(((requires_32bit[i]>>r)&(~unneeded_reg[i]>>r))&1) {
11142       if((pr32[i]>>r)&1) {
11143         if(r==CCREG) printf(" CC");
11144         else if(r==HIREG) printf(" HI");
11145         else if(r==LOREG) printf(" LO");
11146         else printf(" r%d",r);
11147       }
11148     }
11149     if(pr32[i]!=requires_32bit[i]) printf(" OOPS");
11150     printf("\n");*/
11151     #if defined(__i386__) || defined(__x86_64__)
11152     printf("entry: eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",regs[i].regmap_entry[0],regs[i].regmap_entry[1],regs[i].regmap_entry[2],regs[i].regmap_entry[3],regs[i].regmap_entry[5],regs[i].regmap_entry[6],regs[i].regmap_entry[7]);
11153     printf("dirty: ");
11154     if(regs[i].wasdirty&1) printf("eax ");
11155     if((regs[i].wasdirty>>1)&1) printf("ecx ");
11156     if((regs[i].wasdirty>>2)&1) printf("edx ");
11157     if((regs[i].wasdirty>>3)&1) printf("ebx ");
11158     if((regs[i].wasdirty>>5)&1) printf("ebp ");
11159     if((regs[i].wasdirty>>6)&1) printf("esi ");
11160     if((regs[i].wasdirty>>7)&1) printf("edi ");
11161     #endif
11162     #ifdef __arm__
11163     printf("entry: r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d\n",regs[i].regmap_entry[0],regs[i].regmap_entry[1],regs[i].regmap_entry[2],regs[i].regmap_entry[3],regs[i].regmap_entry[4],regs[i].regmap_entry[5],regs[i].regmap_entry[6],regs[i].regmap_entry[7],regs[i].regmap_entry[8],regs[i].regmap_entry[9],regs[i].regmap_entry[10],regs[i].regmap_entry[12]);
11164     printf("dirty: ");
11165     if(regs[i].wasdirty&1) printf("r0 ");
11166     if((regs[i].wasdirty>>1)&1) printf("r1 ");
11167     if((regs[i].wasdirty>>2)&1) printf("r2 ");
11168     if((regs[i].wasdirty>>3)&1) printf("r3 ");
11169     if((regs[i].wasdirty>>4)&1) printf("r4 ");
11170     if((regs[i].wasdirty>>5)&1) printf("r5 ");
11171     if((regs[i].wasdirty>>6)&1) printf("r6 ");
11172     if((regs[i].wasdirty>>7)&1) printf("r7 ");
11173     if((regs[i].wasdirty>>8)&1) printf("r8 ");
11174     if((regs[i].wasdirty>>9)&1) printf("r9 ");
11175     if((regs[i].wasdirty>>10)&1) printf("r10 ");
11176     if((regs[i].wasdirty>>12)&1) printf("r12 ");
11177     #endif
11178     printf("\n");
11179     disassemble_inst(i);
11180     //printf ("ccadj[%d] = %d\n",i,ccadj[i]);
11181     #if defined(__i386__) || defined(__x86_64__)
11182     printf("eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d dirty: ",regs[i].regmap[0],regs[i].regmap[1],regs[i].regmap[2],regs[i].regmap[3],regs[i].regmap[5],regs[i].regmap[6],regs[i].regmap[7]);
11183     if(regs[i].dirty&1) printf("eax ");
11184     if((regs[i].dirty>>1)&1) printf("ecx ");
11185     if((regs[i].dirty>>2)&1) printf("edx ");
11186     if((regs[i].dirty>>3)&1) printf("ebx ");
11187     if((regs[i].dirty>>5)&1) printf("ebp ");
11188     if((regs[i].dirty>>6)&1) printf("esi ");
11189     if((regs[i].dirty>>7)&1) printf("edi ");
11190     #endif
11191     #ifdef __arm__
11192     printf("r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d dirty: ",regs[i].regmap[0],regs[i].regmap[1],regs[i].regmap[2],regs[i].regmap[3],regs[i].regmap[4],regs[i].regmap[5],regs[i].regmap[6],regs[i].regmap[7],regs[i].regmap[8],regs[i].regmap[9],regs[i].regmap[10],regs[i].regmap[12]);
11193     if(regs[i].dirty&1) printf("r0 ");
11194     if((regs[i].dirty>>1)&1) printf("r1 ");
11195     if((regs[i].dirty>>2)&1) printf("r2 ");
11196     if((regs[i].dirty>>3)&1) printf("r3 ");
11197     if((regs[i].dirty>>4)&1) printf("r4 ");
11198     if((regs[i].dirty>>5)&1) printf("r5 ");
11199     if((regs[i].dirty>>6)&1) printf("r6 ");
11200     if((regs[i].dirty>>7)&1) printf("r7 ");
11201     if((regs[i].dirty>>8)&1) printf("r8 ");
11202     if((regs[i].dirty>>9)&1) printf("r9 ");
11203     if((regs[i].dirty>>10)&1) printf("r10 ");
11204     if((regs[i].dirty>>12)&1) printf("r12 ");
11205     #endif
11206     printf("\n");
11207     if(regs[i].isconst) {
11208       printf("constants: ");
11209       #if defined(__i386__) || defined(__x86_64__)
11210       if(regs[i].isconst&1) printf("eax=%x ",(int)constmap[i][0]);
11211       if((regs[i].isconst>>1)&1) printf("ecx=%x ",(int)constmap[i][1]);
11212       if((regs[i].isconst>>2)&1) printf("edx=%x ",(int)constmap[i][2]);
11213       if((regs[i].isconst>>3)&1) printf("ebx=%x ",(int)constmap[i][3]);
11214       if((regs[i].isconst>>5)&1) printf("ebp=%x ",(int)constmap[i][5]);
11215       if((regs[i].isconst>>6)&1) printf("esi=%x ",(int)constmap[i][6]);
11216       if((regs[i].isconst>>7)&1) printf("edi=%x ",(int)constmap[i][7]);
11217       #endif
11218       #ifdef __arm__
11219       if(regs[i].isconst&1) printf("r0=%x ",(int)constmap[i][0]);
11220       if((regs[i].isconst>>1)&1) printf("r1=%x ",(int)constmap[i][1]);
11221       if((regs[i].isconst>>2)&1) printf("r2=%x ",(int)constmap[i][2]);
11222       if((regs[i].isconst>>3)&1) printf("r3=%x ",(int)constmap[i][3]);
11223       if((regs[i].isconst>>4)&1) printf("r4=%x ",(int)constmap[i][4]);
11224       if((regs[i].isconst>>5)&1) printf("r5=%x ",(int)constmap[i][5]);
11225       if((regs[i].isconst>>6)&1) printf("r6=%x ",(int)constmap[i][6]);
11226       if((regs[i].isconst>>7)&1) printf("r7=%x ",(int)constmap[i][7]);
11227       if((regs[i].isconst>>8)&1) printf("r8=%x ",(int)constmap[i][8]);
11228       if((regs[i].isconst>>9)&1) printf("r9=%x ",(int)constmap[i][9]);
11229       if((regs[i].isconst>>10)&1) printf("r10=%x ",(int)constmap[i][10]);
11230       if((regs[i].isconst>>12)&1) printf("r12=%x ",(int)constmap[i][12]);
11231       #endif
11232       printf("\n");
11233     }
11234 #ifndef FORCE32
11235     printf(" 32:");
11236     for(r=0;r<=CCREG;r++) {
11237       if((regs[i].is32>>r)&1) {
11238         if(r==CCREG) printf(" CC");
11239         else if(r==HIREG) printf(" HI");
11240         else if(r==LOREG) printf(" LO");
11241         else printf(" r%d",r);
11242       }
11243     }
11244     printf("\n");
11245 #endif
11246     /*printf(" p32:");
11247     for(r=0;r<=CCREG;r++) {
11248       if((p32[i]>>r)&1) {
11249         if(r==CCREG) printf(" CC");
11250         else if(r==HIREG) printf(" HI");
11251         else if(r==LOREG) printf(" LO");
11252         else printf(" r%d",r);
11253       }
11254     }
11255     if(p32[i]!=regs[i].is32) printf(" NO MATCH\n");
11256     else printf("\n");*/
11257     if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP) {
11258       #if defined(__i386__) || defined(__x86_64__)
11259       printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d dirty: ",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
11260       if(branch_regs[i].dirty&1) printf("eax ");
11261       if((branch_regs[i].dirty>>1)&1) printf("ecx ");
11262       if((branch_regs[i].dirty>>2)&1) printf("edx ");
11263       if((branch_regs[i].dirty>>3)&1) printf("ebx ");
11264       if((branch_regs[i].dirty>>5)&1) printf("ebp ");
11265       if((branch_regs[i].dirty>>6)&1) printf("esi ");
11266       if((branch_regs[i].dirty>>7)&1) printf("edi ");
11267       #endif
11268       #ifdef __arm__
11269       printf("branch(%d): r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d dirty: ",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[4],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7],branch_regs[i].regmap[8],branch_regs[i].regmap[9],branch_regs[i].regmap[10],branch_regs[i].regmap[12]);
11270       if(branch_regs[i].dirty&1) printf("r0 ");
11271       if((branch_regs[i].dirty>>1)&1) printf("r1 ");
11272       if((branch_regs[i].dirty>>2)&1) printf("r2 ");
11273       if((branch_regs[i].dirty>>3)&1) printf("r3 ");
11274       if((branch_regs[i].dirty>>4)&1) printf("r4 ");
11275       if((branch_regs[i].dirty>>5)&1) printf("r5 ");
11276       if((branch_regs[i].dirty>>6)&1) printf("r6 ");
11277       if((branch_regs[i].dirty>>7)&1) printf("r7 ");
11278       if((branch_regs[i].dirty>>8)&1) printf("r8 ");
11279       if((branch_regs[i].dirty>>9)&1) printf("r9 ");
11280       if((branch_regs[i].dirty>>10)&1) printf("r10 ");
11281       if((branch_regs[i].dirty>>12)&1) printf("r12 ");
11282       #endif
11283 #ifndef FORCE32
11284       printf(" 32:");
11285       for(r=0;r<=CCREG;r++) {
11286         if((branch_regs[i].is32>>r)&1) {
11287           if(r==CCREG) printf(" CC");
11288           else if(r==HIREG) printf(" HI");
11289           else if(r==LOREG) printf(" LO");
11290           else printf(" r%d",r);
11291         }
11292       }
11293       printf("\n");
11294 #endif
11295     }
11296   }
11297 #endif // DISASM
11298
11299   /* Pass 8 - Assembly */
11300   linkcount=0;stubcount=0;
11301   ds=0;is_delayslot=0;
11302   cop1_usable=0;
11303   uint64_t is32_pre=0;
11304   u_int dirty_pre=0;
11305   u_int beginning=(u_int)out;
11306   if((u_int)addr&1) {
11307     ds=1;
11308     pagespan_ds();
11309   }
11310   u_int instr_addr0_override=0;
11311
11312 #ifdef PCSX
11313   if (start == 0x80030000) {
11314     // nasty hack for fastbios thing
11315     // override block entry to this code
11316     instr_addr0_override=(u_int)out;
11317     emit_movimm(start,0);
11318     // abuse io address var as a flag that we
11319     // have already returned here once
11320     emit_readword((int)&address,1);
11321     emit_writeword(0,(int)&pcaddr);
11322     emit_writeword(0,(int)&address);
11323     emit_cmp(0,1);
11324     emit_jne((int)new_dyna_leave);
11325   }
11326 #endif
11327   for(i=0;i<slen;i++)
11328   {
11329     //if(ds) printf("ds: ");
11330     disassemble_inst(i);
11331     if(ds) {
11332       ds=0; // Skip delay slot
11333       if(bt[i]) assem_debug("OOPS - branch into delay slot\n");
11334       instr_addr[i]=0;
11335     } else {
11336       speculate_register_values(i);
11337       #ifndef DESTRUCTIVE_WRITEBACK
11338       if(i<2||(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000))
11339       {
11340         wb_sx(regmap_pre[i],regs[i].regmap_entry,regs[i].wasdirty,is32_pre,regs[i].was32,
11341               unneeded_reg[i],unneeded_reg_upper[i]);
11342         wb_valid(regmap_pre[i],regs[i].regmap_entry,dirty_pre,regs[i].wasdirty,is32_pre,
11343               unneeded_reg[i],unneeded_reg_upper[i]);
11344       }
11345       if((itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)&&!likely[i]) {
11346         is32_pre=branch_regs[i].is32;
11347         dirty_pre=branch_regs[i].dirty;
11348       }else{
11349         is32_pre=regs[i].is32;
11350         dirty_pre=regs[i].dirty;
11351       }
11352       #endif
11353       // write back
11354       if(i<2||(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000))
11355       {
11356         wb_invalidate(regmap_pre[i],regs[i].regmap_entry,regs[i].wasdirty,regs[i].was32,
11357                       unneeded_reg[i],unneeded_reg_upper[i]);
11358         loop_preload(regmap_pre[i],regs[i].regmap_entry);
11359       }
11360       // branch target entry point
11361       instr_addr[i]=(u_int)out;
11362       assem_debug("<->\n");
11363       // load regs
11364       if(regs[i].regmap_entry[HOST_CCREG]==CCREG&&regs[i].regmap[HOST_CCREG]!=CCREG)
11365         wb_register(CCREG,regs[i].regmap_entry,regs[i].wasdirty,regs[i].was32);
11366       load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs1[i],rs2[i]);
11367       address_generation(i,&regs[i],regs[i].regmap_entry);
11368       load_consts(regmap_pre[i],regs[i].regmap,regs[i].was32,i);
11369       if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
11370       {
11371         // Load the delay slot registers if necessary
11372         if(rs1[i+1]!=rs1[i]&&rs1[i+1]!=rs2[i]&&(rs1[i+1]!=rt1[i]||rt1[i]==0))
11373           load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs1[i+1],rs1[i+1]);
11374         if(rs2[i+1]!=rs1[i+1]&&rs2[i+1]!=rs1[i]&&rs2[i+1]!=rs2[i]&&(rs2[i+1]!=rt1[i]||rt1[i]==0))
11375           load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs2[i+1],rs2[i+1]);
11376         if(itype[i+1]==STORE||itype[i+1]==STORELR||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a)
11377           load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,INVCP,INVCP);
11378       }
11379       else if(i+1<slen)
11380       {
11381         // Preload registers for following instruction
11382         if(rs1[i+1]!=rs1[i]&&rs1[i+1]!=rs2[i])
11383           if(rs1[i+1]!=rt1[i]&&rs1[i+1]!=rt2[i])
11384             load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs1[i+1],rs1[i+1]);
11385         if(rs2[i+1]!=rs1[i+1]&&rs2[i+1]!=rs1[i]&&rs2[i+1]!=rs2[i])
11386           if(rs2[i+1]!=rt1[i]&&rs2[i+1]!=rt2[i])
11387             load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs2[i+1],rs2[i+1]);
11388       }
11389       // TODO: if(is_ooo(i)) address_generation(i+1);
11390       if(itype[i]==CJUMP||itype[i]==FJUMP)
11391         load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,CCREG,CCREG);
11392       if(itype[i]==STORE||itype[i]==STORELR||(opcode[i]&0x3b)==0x39||(opcode[i]&0x3b)==0x3a)
11393         load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,INVCP,INVCP);
11394       if(bt[i]) cop1_usable=0;
11395       // assemble
11396       switch(itype[i]) {
11397         case ALU:
11398           alu_assemble(i,&regs[i]);break;
11399         case IMM16:
11400           imm16_assemble(i,&regs[i]);break;
11401         case SHIFT:
11402           shift_assemble(i,&regs[i]);break;
11403         case SHIFTIMM:
11404           shiftimm_assemble(i,&regs[i]);break;
11405         case LOAD:
11406           load_assemble(i,&regs[i]);break;
11407         case LOADLR:
11408           loadlr_assemble(i,&regs[i]);break;
11409         case STORE:
11410           store_assemble(i,&regs[i]);break;
11411         case STORELR:
11412           storelr_assemble(i,&regs[i]);break;
11413         case COP0:
11414           cop0_assemble(i,&regs[i]);break;
11415         case COP1:
11416           cop1_assemble(i,&regs[i]);break;
11417         case C1LS:
11418           c1ls_assemble(i,&regs[i]);break;
11419         case COP2:
11420           cop2_assemble(i,&regs[i]);break;
11421         case C2LS:
11422           c2ls_assemble(i,&regs[i]);break;
11423         case C2OP:
11424           c2op_assemble(i,&regs[i]);break;
11425         case FCONV:
11426           fconv_assemble(i,&regs[i]);break;
11427         case FLOAT:
11428           float_assemble(i,&regs[i]);break;
11429         case FCOMP:
11430           fcomp_assemble(i,&regs[i]);break;
11431         case MULTDIV:
11432           multdiv_assemble(i,&regs[i]);break;
11433         case MOV:
11434           mov_assemble(i,&regs[i]);break;
11435         case SYSCALL:
11436           syscall_assemble(i,&regs[i]);break;
11437         case HLECALL:
11438           hlecall_assemble(i,&regs[i]);break;
11439         case INTCALL:
11440           intcall_assemble(i,&regs[i]);break;
11441         case UJUMP:
11442           ujump_assemble(i,&regs[i]);ds=1;break;
11443         case RJUMP:
11444           rjump_assemble(i,&regs[i]);ds=1;break;
11445         case CJUMP:
11446           cjump_assemble(i,&regs[i]);ds=1;break;
11447         case SJUMP:
11448           sjump_assemble(i,&regs[i]);ds=1;break;
11449         case FJUMP:
11450           fjump_assemble(i,&regs[i]);ds=1;break;
11451         case SPAN:
11452           pagespan_assemble(i,&regs[i]);break;
11453       }
11454       if(itype[i]==UJUMP||itype[i]==RJUMP||(source[i]>>16)==0x1000)
11455         literal_pool(1024);
11456       else
11457         literal_pool_jumpover(256);
11458     }
11459   }
11460   //assert(itype[i-2]==UJUMP||itype[i-2]==RJUMP||(source[i-2]>>16)==0x1000);
11461   // If the block did not end with an unconditional branch,
11462   // add a jump to the next instruction.
11463   if(i>1) {
11464     if(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000&&itype[i-1]!=SPAN) {
11465       assert(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP);
11466       assert(i==slen);
11467       if(itype[i-2]!=CJUMP&&itype[i-2]!=SJUMP&&itype[i-2]!=FJUMP) {
11468         store_regs_bt(regs[i-1].regmap,regs[i-1].is32,regs[i-1].dirty,start+i*4);
11469         if(regs[i-1].regmap[HOST_CCREG]!=CCREG)
11470           emit_loadreg(CCREG,HOST_CCREG);
11471         emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i-1]+1),HOST_CCREG);
11472       }
11473       else if(!likely[i-2])
11474       {
11475         store_regs_bt(branch_regs[i-2].regmap,branch_regs[i-2].is32,branch_regs[i-2].dirty,start+i*4);
11476         assert(branch_regs[i-2].regmap[HOST_CCREG]==CCREG);
11477       }
11478       else
11479       {
11480         store_regs_bt(regs[i-2].regmap,regs[i-2].is32,regs[i-2].dirty,start+i*4);
11481         assert(regs[i-2].regmap[HOST_CCREG]==CCREG);
11482       }
11483       add_to_linker((int)out,start+i*4,0);
11484       emit_jmp(0);
11485     }
11486   }
11487   else
11488   {
11489     assert(i>0);
11490     assert(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP);
11491     store_regs_bt(regs[i-1].regmap,regs[i-1].is32,regs[i-1].dirty,start+i*4);
11492     if(regs[i-1].regmap[HOST_CCREG]!=CCREG)
11493       emit_loadreg(CCREG,HOST_CCREG);
11494     emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i-1]+1),HOST_CCREG);
11495     add_to_linker((int)out,start+i*4,0);
11496     emit_jmp(0);
11497   }
11498
11499   // TODO: delay slot stubs?
11500   // Stubs
11501   for(i=0;i<stubcount;i++)
11502   {
11503     switch(stubs[i][0])
11504     {
11505       case LOADB_STUB:
11506       case LOADH_STUB:
11507       case LOADW_STUB:
11508       case LOADD_STUB:
11509       case LOADBU_STUB:
11510       case LOADHU_STUB:
11511         do_readstub(i);break;
11512       case STOREB_STUB:
11513       case STOREH_STUB:
11514       case STOREW_STUB:
11515       case STORED_STUB:
11516         do_writestub(i);break;
11517       case CC_STUB:
11518         do_ccstub(i);break;
11519       case INVCODE_STUB:
11520         do_invstub(i);break;
11521       case FP_STUB:
11522         do_cop1stub(i);break;
11523       case STORELR_STUB:
11524         do_unalignedwritestub(i);break;
11525     }
11526   }
11527
11528   if (instr_addr0_override)
11529     instr_addr[0] = instr_addr0_override;
11530
11531   /* Pass 9 - Linker */
11532   for(i=0;i<linkcount;i++)
11533   {
11534     assem_debug("%8x -> %8x\n",link_addr[i][0],link_addr[i][1]);
11535     literal_pool(64);
11536     if(!link_addr[i][2])
11537     {
11538       void *stub=out;
11539       void *addr=check_addr(link_addr[i][1]);
11540       emit_extjump(link_addr[i][0],link_addr[i][1]);
11541       if(addr) {
11542         set_jump_target(link_addr[i][0],(int)addr);
11543         add_link(link_addr[i][1],stub);
11544       }
11545       else set_jump_target(link_addr[i][0],(int)stub);
11546     }
11547     else
11548     {
11549       // Internal branch
11550       int target=(link_addr[i][1]-start)>>2;
11551       assert(target>=0&&target<slen);
11552       assert(instr_addr[target]);
11553       //#ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
11554       //set_jump_target_fillslot(link_addr[i][0],instr_addr[target],link_addr[i][2]>>1);
11555       //#else
11556       set_jump_target(link_addr[i][0],instr_addr[target]);
11557       //#endif
11558     }
11559   }
11560   // External Branch Targets (jump_in)
11561   if(copy+slen*4>(void *)shadow+sizeof(shadow)) copy=shadow;
11562   for(i=0;i<slen;i++)
11563   {
11564     if(bt[i]||i==0)
11565     {
11566       if(instr_addr[i]) // TODO - delay slots (=null)
11567       {
11568         u_int vaddr=start+i*4;
11569         u_int page=get_page(vaddr);
11570         u_int vpage=get_vpage(vaddr);
11571         literal_pool(256);
11572         //if(!(is32[i]&(~unneeded_reg_upper[i])&~(1LL<<CCREG)))
11573 #ifndef FORCE32
11574         if(!requires_32bit[i])
11575 #else
11576         if(1)
11577 #endif
11578         {
11579           assem_debug("%8x (%d) <- %8x\n",instr_addr[i],i,start+i*4);
11580           assem_debug("jump_in: %x\n",start+i*4);
11581           ll_add(jump_dirty+vpage,vaddr,(void *)out);
11582           int entry_point=do_dirty_stub(i);
11583           ll_add(jump_in+page,vaddr,(void *)entry_point);
11584           // If there was an existing entry in the hash table,
11585           // replace it with the new address.
11586           // Don't add new entries.  We'll insert the
11587           // ones that actually get used in check_addr().
11588           int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
11589           if(ht_bin[0]==vaddr) {
11590             ht_bin[1]=entry_point;
11591           }
11592           if(ht_bin[2]==vaddr) {
11593             ht_bin[3]=entry_point;
11594           }
11595         }
11596         else
11597         {
11598           u_int r=requires_32bit[i]|!!(requires_32bit[i]>>32);
11599           assem_debug("%8x (%d) <- %8x\n",instr_addr[i],i,start+i*4);
11600           assem_debug("jump_in: %x (restricted - %x)\n",start+i*4,r);
11601           //int entry_point=(int)out;
11602           ////assem_debug("entry_point: %x\n",entry_point);
11603           //load_regs_entry(i);
11604           //if(entry_point==(int)out)
11605           //  entry_point=instr_addr[i];
11606           //else
11607           //  emit_jmp(instr_addr[i]);
11608           //ll_add_32(jump_in+page,vaddr,r,(void *)entry_point);
11609           ll_add_32(jump_dirty+vpage,vaddr,r,(void *)out);
11610           int entry_point=do_dirty_stub(i);
11611           ll_add_32(jump_in+page,vaddr,r,(void *)entry_point);
11612         }
11613       }
11614     }
11615   }
11616   // Write out the literal pool if necessary
11617   literal_pool(0);
11618   #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
11619   // Align code
11620   if(((u_int)out)&7) emit_addnop(13);
11621   #endif
11622   assert((u_int)out-beginning<MAX_OUTPUT_BLOCK_SIZE);
11623   //printf("shadow buffer: %x-%x\n",(int)copy,(int)copy+slen*4);
11624   memcpy(copy,source,slen*4);
11625   copy+=slen*4;
11626
11627   #ifdef __arm__
11628   __clear_cache((void *)beginning,out);
11629   #endif
11630
11631   // If we're within 256K of the end of the buffer,
11632   // start over from the beginning. (Is 256K enough?)
11633   if((u_int)out>(u_int)BASE_ADDR+(1<<TARGET_SIZE_2)-MAX_OUTPUT_BLOCK_SIZE) out=(u_char *)BASE_ADDR;
11634
11635   // Trap writes to any of the pages we compiled
11636   for(i=start>>12;i<=(start+slen*4)>>12;i++) {
11637     invalid_code[i]=0;
11638 #ifndef DISABLE_TLB
11639     memory_map[i]|=0x40000000;
11640     if((signed int)start>=(signed int)0xC0000000) {
11641       assert(using_tlb);
11642       j=(((u_int)i<<12)+(memory_map[i]<<2)-(u_int)rdram+(u_int)0x80000000)>>12;
11643       invalid_code[j]=0;
11644       memory_map[j]|=0x40000000;
11645       //printf("write protect physical page: %x (virtual %x)\n",j<<12,start);
11646     }
11647 #endif
11648   }
11649   inv_code_start=inv_code_end=~0;
11650 #ifdef PCSX
11651   // for PCSX we need to mark all mirrors too
11652   if(get_page(start)<(RAM_SIZE>>12))
11653     for(i=start>>12;i<=(start+slen*4)>>12;i++)
11654       invalid_code[((u_int)0x00000000>>12)|(i&0x1ff)]=
11655       invalid_code[((u_int)0x80000000>>12)|(i&0x1ff)]=
11656       invalid_code[((u_int)0xa0000000>>12)|(i&0x1ff)]=0;
11657 #endif
11658
11659   /* Pass 10 - Free memory by expiring oldest blocks */
11660
11661   int end=((((int)out-(int)BASE_ADDR)>>(TARGET_SIZE_2-16))+16384)&65535;
11662   while(expirep!=end)
11663   {
11664     int shift=TARGET_SIZE_2-3; // Divide into 8 blocks
11665     int base=(int)BASE_ADDR+((expirep>>13)<<shift); // Base address of this block
11666     inv_debug("EXP: Phase %d\n",expirep);
11667     switch((expirep>>11)&3)
11668     {
11669       case 0:
11670         // Clear jump_in and jump_dirty
11671         ll_remove_matching_addrs(jump_in+(expirep&2047),base,shift);
11672         ll_remove_matching_addrs(jump_dirty+(expirep&2047),base,shift);
11673         ll_remove_matching_addrs(jump_in+2048+(expirep&2047),base,shift);
11674         ll_remove_matching_addrs(jump_dirty+2048+(expirep&2047),base,shift);
11675         break;
11676       case 1:
11677         // Clear pointers
11678         ll_kill_pointers(jump_out[expirep&2047],base,shift);
11679         ll_kill_pointers(jump_out[(expirep&2047)+2048],base,shift);
11680         break;
11681       case 2:
11682         // Clear hash table
11683         for(i=0;i<32;i++) {
11684           int *ht_bin=hash_table[((expirep&2047)<<5)+i];
11685           if((ht_bin[3]>>shift)==(base>>shift) ||
11686              ((ht_bin[3]-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(base>>shift)) {
11687             inv_debug("EXP: Remove hash %x -> %x\n",ht_bin[2],ht_bin[3]);
11688             ht_bin[2]=ht_bin[3]=-1;
11689           }
11690           if((ht_bin[1]>>shift)==(base>>shift) ||
11691              ((ht_bin[1]-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(base>>shift)) {
11692             inv_debug("EXP: Remove hash %x -> %x\n",ht_bin[0],ht_bin[1]);
11693             ht_bin[0]=ht_bin[2];
11694             ht_bin[1]=ht_bin[3];
11695             ht_bin[2]=ht_bin[3]=-1;
11696           }
11697         }
11698         break;
11699       case 3:
11700         // Clear jump_out
11701         #ifdef __arm__
11702         if((expirep&2047)==0)
11703           do_clear_cache();
11704         #endif
11705         ll_remove_matching_addrs(jump_out+(expirep&2047),base,shift);
11706         ll_remove_matching_addrs(jump_out+2048+(expirep&2047),base,shift);
11707         break;
11708     }
11709     expirep=(expirep+1)&65535;
11710   }
11711   return 0;
11712 }
11713
11714 // vim:shiftwidth=2:expandtab