spu: rework synchronization
[pcsx_rearmed.git] / libpcsxcore / new_dynarec / new_dynarec.c
1 /* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
2  *   Mupen64plus - new_dynarec.c                                           *
3  *   Copyright (C) 2009-2011 Ari64                                         *
4  *                                                                         *
5  *   This program is free software; you can redistribute it and/or modify  *
6  *   it under the terms of the GNU General Public License as published by  *
7  *   the Free Software Foundation; either version 2 of the License, or     *
8  *   (at your option) any later version.                                   *
9  *                                                                         *
10  *   This program is distributed in the hope that it will be useful,       *
11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
13  *   GNU General Public License for more details.                          *
14  *                                                                         *
15  *   You should have received a copy of the GNU General Public License     *
16  *   along with this program; if not, write to the                         *
17  *   Free Software Foundation, Inc.,                                       *
18  *   51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.          *
19  * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
20
21 #include <stdlib.h>
22 #include <stdint.h> //include for uint64_t
23 #include <assert.h>
24 #include <errno.h>
25 #include <sys/mman.h>
26
27 #include "emu_if.h" //emulator interface
28
29 //#define DISASM
30 //#define assem_debug printf
31 //#define inv_debug printf
32 #define assem_debug(...)
33 #define inv_debug(...)
34
35 #ifdef __i386__
36 #include "assem_x86.h"
37 #endif
38 #ifdef __x86_64__
39 #include "assem_x64.h"
40 #endif
41 #ifdef __arm__
42 #include "assem_arm.h"
43 #endif
44
45 #ifdef __BLACKBERRY_QNX__
46 #undef __clear_cache
47 #define __clear_cache(start,end) msync(start, (size_t)((void*)end - (void*)start), MS_SYNC | MS_CACHE_ONLY | MS_INVALIDATE_ICACHE);
48 #elif defined(__MACH__)
49 #include <libkern/OSCacheControl.h>
50 #define __clear_cache mach_clear_cache
51 static void __clear_cache(void *start, void *end) {
52   size_t len = (char *)end - (char *)start;
53   sys_dcache_flush(start, len);
54   sys_icache_invalidate(start, len);
55 }
56 #endif
57
58 #define MAXBLOCK 4096
59 #define MAX_OUTPUT_BLOCK_SIZE 262144
60
61 struct regstat
62 {
63   signed char regmap_entry[HOST_REGS];
64   signed char regmap[HOST_REGS];
65   uint64_t was32;
66   uint64_t is32;
67   uint64_t wasdirty;
68   uint64_t dirty;
69   uint64_t u;
70   uint64_t uu;
71   u_int wasconst;
72   u_int isconst;
73   u_int loadedconst;             // host regs that have constants loaded
74   u_int waswritten;              // MIPS regs that were used as store base before
75 };
76
77 struct ll_entry
78 {
79   u_int vaddr;
80   u_int reg32;
81   void *addr;
82   struct ll_entry *next;
83 };
84
85   u_int start;
86   u_int *source;
87   u_int pagelimit;
88   char insn[MAXBLOCK][10];
89   u_char itype[MAXBLOCK];
90   u_char opcode[MAXBLOCK];
91   u_char opcode2[MAXBLOCK];
92   u_char bt[MAXBLOCK];
93   u_char rs1[MAXBLOCK];
94   u_char rs2[MAXBLOCK];
95   u_char rt1[MAXBLOCK];
96   u_char rt2[MAXBLOCK];
97   u_char us1[MAXBLOCK];
98   u_char us2[MAXBLOCK];
99   u_char dep1[MAXBLOCK];
100   u_char dep2[MAXBLOCK];
101   u_char lt1[MAXBLOCK];
102   static uint64_t gte_rs[MAXBLOCK]; // gte: 32 data and 32 ctl regs
103   static uint64_t gte_rt[MAXBLOCK];
104   static uint64_t gte_unneeded[MAXBLOCK];
105   static u_int smrv[32]; // speculated MIPS register values
106   static u_int smrv_strong; // mask or regs that are likely to have correct values
107   static u_int smrv_weak; // same, but somewhat less likely
108   static u_int smrv_strong_next; // same, but after current insn executes
109   static u_int smrv_weak_next;
110   int imm[MAXBLOCK];
111   u_int ba[MAXBLOCK];
112   char likely[MAXBLOCK];
113   char is_ds[MAXBLOCK];
114   char ooo[MAXBLOCK];
115   uint64_t unneeded_reg[MAXBLOCK];
116   uint64_t unneeded_reg_upper[MAXBLOCK];
117   uint64_t branch_unneeded_reg[MAXBLOCK];
118   uint64_t branch_unneeded_reg_upper[MAXBLOCK];
119   uint64_t p32[MAXBLOCK];
120   uint64_t pr32[MAXBLOCK];
121   signed char regmap_pre[MAXBLOCK][HOST_REGS];
122   static uint64_t current_constmap[HOST_REGS];
123   static uint64_t constmap[MAXBLOCK][HOST_REGS];
124   static struct regstat regs[MAXBLOCK];
125   static struct regstat branch_regs[MAXBLOCK];
126   signed char minimum_free_regs[MAXBLOCK];
127   u_int needed_reg[MAXBLOCK];
128   uint64_t requires_32bit[MAXBLOCK];
129   u_int wont_dirty[MAXBLOCK];
130   u_int will_dirty[MAXBLOCK];
131   int ccadj[MAXBLOCK];
132   int slen;
133   u_int instr_addr[MAXBLOCK];
134   u_int link_addr[MAXBLOCK][3];
135   int linkcount;
136   u_int stubs[MAXBLOCK*3][8];
137   int stubcount;
138   u_int literals[1024][2];
139   int literalcount;
140   int is_delayslot;
141   int cop1_usable;
142   u_char *out;
143   struct ll_entry *jump_in[4096];
144   struct ll_entry *jump_out[4096];
145   struct ll_entry *jump_dirty[4096];
146   u_int hash_table[65536][4]  __attribute__((aligned(16)));
147   char shadow[1048576]  __attribute__((aligned(16)));
148   void *copy;
149   int expirep;
150 #ifndef PCSX
151   u_int using_tlb;
152 #else
153   static const u_int using_tlb=0;
154 #endif
155   int new_dynarec_did_compile;
156   int new_dynarec_hacks;
157   u_int stop_after_jal;
158 #ifndef RAM_FIXED
159   static u_int ram_offset;
160 #else
161   static const u_int ram_offset=0;
162 #endif
163   extern u_char restore_candidate[512];
164   extern int cycle_count;
165
166   /* registers that may be allocated */
167   /* 1-31 gpr */
168 #define HIREG 32 // hi
169 #define LOREG 33 // lo
170 #define FSREG 34 // FPU status (FCSR)
171 #define CSREG 35 // Coprocessor status
172 #define CCREG 36 // Cycle count
173 #define INVCP 37 // Pointer to invalid_code
174 #define MMREG 38 // Pointer to memory_map
175 #define ROREG 39 // ram offset (if rdram!=0x80000000)
176 #define TEMPREG 40
177 #define FTEMP 40 // FPU temporary register
178 #define PTEMP 41 // Prefetch temporary register
179 #define TLREG 42 // TLB mapping offset
180 #define RHASH 43 // Return address hash
181 #define RHTBL 44 // Return address hash table address
182 #define RTEMP 45 // JR/JALR address register
183 #define MAXREG 45
184 #define AGEN1 46 // Address generation temporary register
185 #define AGEN2 47 // Address generation temporary register
186 #define MGEN1 48 // Maptable address generation temporary register
187 #define MGEN2 49 // Maptable address generation temporary register
188 #define BTREG 50 // Branch target temporary register
189
190   /* instruction types */
191 #define NOP 0     // No operation
192 #define LOAD 1    // Load
193 #define STORE 2   // Store
194 #define LOADLR 3  // Unaligned load
195 #define STORELR 4 // Unaligned store
196 #define MOV 5     // Move 
197 #define ALU 6     // Arithmetic/logic
198 #define MULTDIV 7 // Multiply/divide
199 #define SHIFT 8   // Shift by register
200 #define SHIFTIMM 9// Shift by immediate
201 #define IMM16 10  // 16-bit immediate
202 #define RJUMP 11  // Unconditional jump to register
203 #define UJUMP 12  // Unconditional jump
204 #define CJUMP 13  // Conditional branch (BEQ/BNE/BGTZ/BLEZ)
205 #define SJUMP 14  // Conditional branch (regimm format)
206 #define COP0 15   // Coprocessor 0
207 #define COP1 16   // Coprocessor 1
208 #define C1LS 17   // Coprocessor 1 load/store
209 #define FJUMP 18  // Conditional branch (floating point)
210 #define FLOAT 19  // Floating point unit
211 #define FCONV 20  // Convert integer to float
212 #define FCOMP 21  // Floating point compare (sets FSREG)
213 #define SYSCALL 22// SYSCALL
214 #define OTHER 23  // Other
215 #define SPAN 24   // Branch/delay slot spans 2 pages
216 #define NI 25     // Not implemented
217 #define HLECALL 26// PCSX fake opcodes for HLE
218 #define COP2 27   // Coprocessor 2 move
219 #define C2LS 28   // Coprocessor 2 load/store
220 #define C2OP 29   // Coprocessor 2 operation
221 #define INTCALL 30// Call interpreter to handle rare corner cases
222
223   /* stubs */
224 #define CC_STUB 1
225 #define FP_STUB 2
226 #define LOADB_STUB 3
227 #define LOADH_STUB 4
228 #define LOADW_STUB 5
229 #define LOADD_STUB 6
230 #define LOADBU_STUB 7
231 #define LOADHU_STUB 8
232 #define STOREB_STUB 9
233 #define STOREH_STUB 10
234 #define STOREW_STUB 11
235 #define STORED_STUB 12
236 #define STORELR_STUB 13
237 #define INVCODE_STUB 14
238
239   /* branch codes */
240 #define TAKEN 1
241 #define NOTTAKEN 2
242 #define NULLDS 3
243
244 // asm linkage
245 int new_recompile_block(int addr);
246 void *get_addr_ht(u_int vaddr);
247 void invalidate_block(u_int block);
248 void invalidate_addr(u_int addr);
249 void remove_hash(int vaddr);
250 void jump_vaddr();
251 void dyna_linker();
252 void dyna_linker_ds();
253 void verify_code();
254 void verify_code_vm();
255 void verify_code_ds();
256 void cc_interrupt();
257 void fp_exception();
258 void fp_exception_ds();
259 void jump_syscall();
260 void jump_syscall_hle();
261 void jump_eret();
262 void jump_hlecall();
263 void jump_intcall();
264 void new_dyna_leave();
265
266 // TLB
267 void TLBWI_new();
268 void TLBWR_new();
269 void read_nomem_new();
270 void read_nomemb_new();
271 void read_nomemh_new();
272 void read_nomemd_new();
273 void write_nomem_new();
274 void write_nomemb_new();
275 void write_nomemh_new();
276 void write_nomemd_new();
277 void write_rdram_new();
278 void write_rdramb_new();
279 void write_rdramh_new();
280 void write_rdramd_new();
281 extern u_int memory_map[1048576];
282
283 // Needed by assembler
284 void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32);
285 void wb_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty);
286 void wb_needed_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr);
287 void load_all_regs(signed char i_regmap[]);
288 void load_needed_regs(signed char i_regmap[],signed char next_regmap[]);
289 void load_regs_entry(int t);
290 void load_all_consts(signed char regmap[],int is32,u_int dirty,int i);
291
292 int tracedebug=0;
293
294 //#define DEBUG_CYCLE_COUNT 1
295
296 #define NO_CYCLE_PENALTY_THR 12
297
298 int cycle_multiplier; // 100 for 1.0
299
300 static int CLOCK_ADJUST(int x)
301 {
302   int s=(x>>31)|1;
303   return (x * cycle_multiplier + s * 50) / 100;
304 }
305
306 static void tlb_hacks()
307 {
308 #ifndef DISABLE_TLB
309   // Goldeneye hack
310   if (strncmp((char *) ROM_HEADER->nom, "GOLDENEYE",9) == 0)
311   {
312     u_int addr;
313     int n;
314     switch (ROM_HEADER->Country_code&0xFF) 
315     {
316       case 0x45: // U
317         addr=0x34b30;
318         break;                   
319       case 0x4A: // J 
320         addr=0x34b70;    
321         break;    
322       case 0x50: // E 
323         addr=0x329f0;
324         break;                        
325       default: 
326         // Unknown country code
327         addr=0;
328         break;
329     }
330     u_int rom_addr=(u_int)rom;
331     #ifdef ROM_COPY
332     // Since memory_map is 32-bit, on 64-bit systems the rom needs to be
333     // in the lower 4G of memory to use this hack.  Copy it if necessary.
334     if((void *)rom>(void *)0xffffffff) {
335       munmap(ROM_COPY, 67108864);
336       if(mmap(ROM_COPY, 12582912,
337               PROT_READ | PROT_WRITE,
338               MAP_FIXED | MAP_PRIVATE | MAP_ANONYMOUS,
339               -1, 0) <= 0) {printf("mmap() failed\n");}
340       memcpy(ROM_COPY,rom,12582912);
341       rom_addr=(u_int)ROM_COPY;
342     }
343     #endif
344     if(addr) {
345       for(n=0x7F000;n<0x80000;n++) {
346         memory_map[n]=(((u_int)(rom_addr+addr-0x7F000000))>>2)|0x40000000;
347       }
348     }
349   }
350 #endif
351 }
352
353 static u_int get_page(u_int vaddr)
354 {
355 #ifndef PCSX
356   u_int page=(vaddr^0x80000000)>>12;
357 #else
358   u_int page=vaddr&~0xe0000000;
359   if (page < 0x1000000)
360     page &= ~0x0e00000; // RAM mirrors
361   page>>=12;
362 #endif
363 #ifndef DISABLE_TLB
364   if(page>262143&&tlb_LUT_r[vaddr>>12]) page=(tlb_LUT_r[vaddr>>12]^0x80000000)>>12;
365 #endif
366   if(page>2048) page=2048+(page&2047);
367   return page;
368 }
369
370 #ifndef PCSX
371 static u_int get_vpage(u_int vaddr)
372 {
373   u_int vpage=(vaddr^0x80000000)>>12;
374 #ifndef DISABLE_TLB
375   if(vpage>262143&&tlb_LUT_r[vaddr>>12]) vpage&=2047; // jump_dirty uses a hash of the virtual address instead
376 #endif
377   if(vpage>2048) vpage=2048+(vpage&2047);
378   return vpage;
379 }
380 #else
381 // no virtual mem in PCSX
382 static u_int get_vpage(u_int vaddr)
383 {
384   return get_page(vaddr);
385 }
386 #endif
387
388 // Get address from virtual address
389 // This is called from the recompiled JR/JALR instructions
390 void *get_addr(u_int vaddr)
391 {
392   u_int page=get_page(vaddr);
393   u_int vpage=get_vpage(vaddr);
394   struct ll_entry *head;
395   //printf("TRACE: count=%d next=%d (get_addr %x,page %d)\n",Count,next_interupt,vaddr,page);
396   head=jump_in[page];
397   while(head!=NULL) {
398     if(head->vaddr==vaddr&&head->reg32==0) {
399   //printf("TRACE: count=%d next=%d (get_addr match %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
400       int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
401       ht_bin[3]=ht_bin[1];
402       ht_bin[2]=ht_bin[0];
403       ht_bin[1]=(int)head->addr;
404       ht_bin[0]=vaddr;
405       return head->addr;
406     }
407     head=head->next;
408   }
409   head=jump_dirty[vpage];
410   while(head!=NULL) {
411     if(head->vaddr==vaddr&&head->reg32==0) {
412       //printf("TRACE: count=%d next=%d (get_addr match dirty %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
413       // Don't restore blocks which are about to expire from the cache
414       if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
415       if(verify_dirty(head->addr)) {
416         //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]);
417         invalid_code[vaddr>>12]=0;
418         inv_code_start=inv_code_end=~0;
419 #ifndef DISABLE_TLB
420         memory_map[vaddr>>12]|=0x40000000;
421 #endif
422         if(vpage<2048) {
423 #ifndef DISABLE_TLB
424           if(tlb_LUT_r[vaddr>>12]) {
425             invalid_code[tlb_LUT_r[vaddr>>12]>>12]=0;
426             memory_map[tlb_LUT_r[vaddr>>12]>>12]|=0x40000000;
427           }
428 #endif
429           restore_candidate[vpage>>3]|=1<<(vpage&7);
430         }
431         else restore_candidate[page>>3]|=1<<(page&7);
432         int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
433         if(ht_bin[0]==vaddr) {
434           ht_bin[1]=(int)head->addr; // Replace existing entry
435         }
436         else
437         {
438           ht_bin[3]=ht_bin[1];
439           ht_bin[2]=ht_bin[0];
440           ht_bin[1]=(int)head->addr;
441           ht_bin[0]=vaddr;
442         }
443         return head->addr;
444       }
445     }
446     head=head->next;
447   }
448   //printf("TRACE: count=%d next=%d (get_addr no-match %x)\n",Count,next_interupt,vaddr);
449   int r=new_recompile_block(vaddr);
450   if(r==0) return get_addr(vaddr);
451   // Execute in unmapped page, generate pagefault execption
452   Status|=2;
453   Cause=(vaddr<<31)|0x8;
454   EPC=(vaddr&1)?vaddr-5:vaddr;
455   BadVAddr=(vaddr&~1);
456   Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0);
457   EntryHi=BadVAddr&0xFFFFE000;
458   return get_addr_ht(0x80000000);
459 }
460 // Look up address in hash table first
461 void *get_addr_ht(u_int vaddr)
462 {
463   //printf("TRACE: count=%d next=%d (get_addr_ht %x)\n",Count,next_interupt,vaddr);
464   int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
465   if(ht_bin[0]==vaddr) return (void *)ht_bin[1];
466   if(ht_bin[2]==vaddr) return (void *)ht_bin[3];
467   return get_addr(vaddr);
468 }
469
470 void *get_addr_32(u_int vaddr,u_int flags)
471 {
472 #ifdef FORCE32
473   return get_addr(vaddr);
474 #else
475   //printf("TRACE: count=%d next=%d (get_addr_32 %x,flags %x)\n",Count,next_interupt,vaddr,flags);
476   int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
477   if(ht_bin[0]==vaddr) return (void *)ht_bin[1];
478   if(ht_bin[2]==vaddr) return (void *)ht_bin[3];
479   u_int page=get_page(vaddr);
480   u_int vpage=get_vpage(vaddr);
481   struct ll_entry *head;
482   head=jump_in[page];
483   while(head!=NULL) {
484     if(head->vaddr==vaddr&&(head->reg32&flags)==0) {
485       //printf("TRACE: count=%d next=%d (get_addr_32 match %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
486       if(head->reg32==0) {
487         int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
488         if(ht_bin[0]==-1) {
489           ht_bin[1]=(int)head->addr;
490           ht_bin[0]=vaddr;
491         }else if(ht_bin[2]==-1) {
492           ht_bin[3]=(int)head->addr;
493           ht_bin[2]=vaddr;
494         }
495         //ht_bin[3]=ht_bin[1];
496         //ht_bin[2]=ht_bin[0];
497         //ht_bin[1]=(int)head->addr;
498         //ht_bin[0]=vaddr;
499       }
500       return head->addr;
501     }
502     head=head->next;
503   }
504   head=jump_dirty[vpage];
505   while(head!=NULL) {
506     if(head->vaddr==vaddr&&(head->reg32&flags)==0) {
507       //printf("TRACE: count=%d next=%d (get_addr_32 match dirty %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
508       // Don't restore blocks which are about to expire from the cache
509       if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
510       if(verify_dirty(head->addr)) {
511         //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]);
512         invalid_code[vaddr>>12]=0;
513         inv_code_start=inv_code_end=~0;
514         memory_map[vaddr>>12]|=0x40000000;
515         if(vpage<2048) {
516 #ifndef DISABLE_TLB
517           if(tlb_LUT_r[vaddr>>12]) {
518             invalid_code[tlb_LUT_r[vaddr>>12]>>12]=0;
519             memory_map[tlb_LUT_r[vaddr>>12]>>12]|=0x40000000;
520           }
521 #endif
522           restore_candidate[vpage>>3]|=1<<(vpage&7);
523         }
524         else restore_candidate[page>>3]|=1<<(page&7);
525         if(head->reg32==0) {
526           int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
527           if(ht_bin[0]==-1) {
528             ht_bin[1]=(int)head->addr;
529             ht_bin[0]=vaddr;
530           }else if(ht_bin[2]==-1) {
531             ht_bin[3]=(int)head->addr;
532             ht_bin[2]=vaddr;
533           }
534           //ht_bin[3]=ht_bin[1];
535           //ht_bin[2]=ht_bin[0];
536           //ht_bin[1]=(int)head->addr;
537           //ht_bin[0]=vaddr;
538         }
539         return head->addr;
540       }
541     }
542     head=head->next;
543   }
544   //printf("TRACE: count=%d next=%d (get_addr_32 no-match %x,flags %x)\n",Count,next_interupt,vaddr,flags);
545   int r=new_recompile_block(vaddr);
546   if(r==0) return get_addr(vaddr);
547   // Execute in unmapped page, generate pagefault execption
548   Status|=2;
549   Cause=(vaddr<<31)|0x8;
550   EPC=(vaddr&1)?vaddr-5:vaddr;
551   BadVAddr=(vaddr&~1);
552   Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0);
553   EntryHi=BadVAddr&0xFFFFE000;
554   return get_addr_ht(0x80000000);
555 #endif
556 }
557
558 void clear_all_regs(signed char regmap[])
559 {
560   int hr;
561   for (hr=0;hr<HOST_REGS;hr++) regmap[hr]=-1;
562 }
563
564 signed char get_reg(signed char regmap[],int r)
565 {
566   int hr;
567   for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&&regmap[hr]==r) return hr;
568   return -1;
569 }
570
571 // Find a register that is available for two consecutive cycles
572 signed char get_reg2(signed char regmap1[],signed char regmap2[],int r)
573 {
574   int hr;
575   for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&&regmap1[hr]==r&&regmap2[hr]==r) return hr;
576   return -1;
577 }
578
579 int count_free_regs(signed char regmap[])
580 {
581   int count=0;
582   int hr;
583   for(hr=0;hr<HOST_REGS;hr++)
584   {
585     if(hr!=EXCLUDE_REG) {
586       if(regmap[hr]<0) count++;
587     }
588   }
589   return count;
590 }
591
592 void dirty_reg(struct regstat *cur,signed char reg)
593 {
594   int hr;
595   if(!reg) return;
596   for (hr=0;hr<HOST_REGS;hr++) {
597     if((cur->regmap[hr]&63)==reg) {
598       cur->dirty|=1<<hr;
599     }
600   }
601 }
602
603 // If we dirty the lower half of a 64 bit register which is now being
604 // sign-extended, we need to dump the upper half.
605 // Note: Do this only after completion of the instruction, because
606 // some instructions may need to read the full 64-bit value even if
607 // overwriting it (eg SLTI, DSRA32).
608 static void flush_dirty_uppers(struct regstat *cur)
609 {
610   int hr,reg;
611   for (hr=0;hr<HOST_REGS;hr++) {
612     if((cur->dirty>>hr)&1) {
613       reg=cur->regmap[hr];
614       if(reg>=64) 
615         if((cur->is32>>(reg&63))&1) cur->regmap[hr]=-1;
616     }
617   }
618 }
619
620 void set_const(struct regstat *cur,signed char reg,uint64_t value)
621 {
622   int hr;
623   if(!reg) return;
624   for (hr=0;hr<HOST_REGS;hr++) {
625     if(cur->regmap[hr]==reg) {
626       cur->isconst|=1<<hr;
627       current_constmap[hr]=value;
628     }
629     else if((cur->regmap[hr]^64)==reg) {
630       cur->isconst|=1<<hr;
631       current_constmap[hr]=value>>32;
632     }
633   }
634 }
635
636 void clear_const(struct regstat *cur,signed char reg)
637 {
638   int hr;
639   if(!reg) return;
640   for (hr=0;hr<HOST_REGS;hr++) {
641     if((cur->regmap[hr]&63)==reg) {
642       cur->isconst&=~(1<<hr);
643     }
644   }
645 }
646
647 int is_const(struct regstat *cur,signed char reg)
648 {
649   int hr;
650   if(reg<0) return 0;
651   if(!reg) return 1;
652   for (hr=0;hr<HOST_REGS;hr++) {
653     if((cur->regmap[hr]&63)==reg) {
654       return (cur->isconst>>hr)&1;
655     }
656   }
657   return 0;
658 }
659 uint64_t get_const(struct regstat *cur,signed char reg)
660 {
661   int hr;
662   if(!reg) return 0;
663   for (hr=0;hr<HOST_REGS;hr++) {
664     if(cur->regmap[hr]==reg) {
665       return current_constmap[hr];
666     }
667   }
668   SysPrintf("Unknown constant in r%d\n",reg);
669   exit(1);
670 }
671
672 // Least soon needed registers
673 // Look at the next ten instructions and see which registers
674 // will be used.  Try not to reallocate these.
675 void lsn(u_char hsn[], int i, int *preferred_reg)
676 {
677   int j;
678   int b=-1;
679   for(j=0;j<9;j++)
680   {
681     if(i+j>=slen) {
682       j=slen-i-1;
683       break;
684     }
685     if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
686     {
687       // Don't go past an unconditonal jump
688       j++;
689       break;
690     }
691   }
692   for(;j>=0;j--)
693   {
694     if(rs1[i+j]) hsn[rs1[i+j]]=j;
695     if(rs2[i+j]) hsn[rs2[i+j]]=j;
696     if(rt1[i+j]) hsn[rt1[i+j]]=j;
697     if(rt2[i+j]) hsn[rt2[i+j]]=j;
698     if(itype[i+j]==STORE || itype[i+j]==STORELR) {
699       // Stores can allocate zero
700       hsn[rs1[i+j]]=j;
701       hsn[rs2[i+j]]=j;
702     }
703     // On some architectures stores need invc_ptr
704     #if defined(HOST_IMM8)
705     if(itype[i+j]==STORE || itype[i+j]==STORELR || (opcode[i+j]&0x3b)==0x39 || (opcode[i+j]&0x3b)==0x3a) {
706       hsn[INVCP]=j;
707     }
708     #endif
709     if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP))
710     {
711       hsn[CCREG]=j;
712       b=j;
713     }
714   }
715   if(b>=0)
716   {
717     if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
718     {
719       // Follow first branch
720       int t=(ba[i+b]-start)>>2;
721       j=7-b;if(t+j>=slen) j=slen-t-1;
722       for(;j>=0;j--)
723       {
724         if(rs1[t+j]) if(hsn[rs1[t+j]]>j+b+2) hsn[rs1[t+j]]=j+b+2;
725         if(rs2[t+j]) if(hsn[rs2[t+j]]>j+b+2) hsn[rs2[t+j]]=j+b+2;
726         //if(rt1[t+j]) if(hsn[rt1[t+j]]>j+b+2) hsn[rt1[t+j]]=j+b+2;
727         //if(rt2[t+j]) if(hsn[rt2[t+j]]>j+b+2) hsn[rt2[t+j]]=j+b+2;
728       }
729     }
730     // TODO: preferred register based on backward branch
731   }
732   // Delay slot should preferably not overwrite branch conditions or cycle count
733   if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)) {
734     if(rs1[i-1]) if(hsn[rs1[i-1]]>1) hsn[rs1[i-1]]=1;
735     if(rs2[i-1]) if(hsn[rs2[i-1]]>1) hsn[rs2[i-1]]=1;
736     hsn[CCREG]=1;
737     // ...or hash tables
738     hsn[RHASH]=1;
739     hsn[RHTBL]=1;
740   }
741   // Coprocessor load/store needs FTEMP, even if not declared
742   if(itype[i]==C1LS||itype[i]==C2LS) {
743     hsn[FTEMP]=0;
744   }
745   // Load L/R also uses FTEMP as a temporary register
746   if(itype[i]==LOADLR) {
747     hsn[FTEMP]=0;
748   }
749   // Also SWL/SWR/SDL/SDR
750   if(opcode[i]==0x2a||opcode[i]==0x2e||opcode[i]==0x2c||opcode[i]==0x2d) {
751     hsn[FTEMP]=0;
752   }
753   // Don't remove the TLB registers either
754   if(itype[i]==LOAD || itype[i]==LOADLR || itype[i]==STORE || itype[i]==STORELR || itype[i]==C1LS || itype[i]==C2LS) {
755     hsn[TLREG]=0;
756   }
757   // Don't remove the miniht registers
758   if(itype[i]==UJUMP||itype[i]==RJUMP)
759   {
760     hsn[RHASH]=0;
761     hsn[RHTBL]=0;
762   }
763 }
764
765 // We only want to allocate registers if we're going to use them again soon
766 int needed_again(int r, int i)
767 {
768   int j;
769   int b=-1;
770   int rn=10;
771   
772   if(i>0&&(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000))
773   {
774     if(ba[i-1]<start || ba[i-1]>start+slen*4-4)
775       return 0; // Don't need any registers if exiting the block
776   }
777   for(j=0;j<9;j++)
778   {
779     if(i+j>=slen) {
780       j=slen-i-1;
781       break;
782     }
783     if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
784     {
785       // Don't go past an unconditonal jump
786       j++;
787       break;
788     }
789     if(itype[i+j]==SYSCALL||itype[i+j]==HLECALL||itype[i+j]==INTCALL||((source[i+j]&0xfc00003f)==0x0d))
790     {
791       break;
792     }
793   }
794   for(;j>=1;j--)
795   {
796     if(rs1[i+j]==r) rn=j;
797     if(rs2[i+j]==r) rn=j;
798     if((unneeded_reg[i+j]>>r)&1) rn=10;
799     if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP))
800     {
801       b=j;
802     }
803   }
804   /*
805   if(b>=0)
806   {
807     if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
808     {
809       // Follow first branch
810       int o=rn;
811       int t=(ba[i+b]-start)>>2;
812       j=7-b;if(t+j>=slen) j=slen-t-1;
813       for(;j>=0;j--)
814       {
815         if(!((unneeded_reg[t+j]>>r)&1)) {
816           if(rs1[t+j]==r) if(rn>j+b+2) rn=j+b+2;
817           if(rs2[t+j]==r) if(rn>j+b+2) rn=j+b+2;
818         }
819         else rn=o;
820       }
821     }
822   }*/
823   if(rn<10) return 1;
824   return 0;
825 }
826
827 // Try to match register allocations at the end of a loop with those
828 // at the beginning
829 int loop_reg(int i, int r, int hr)
830 {
831   int j,k;
832   for(j=0;j<9;j++)
833   {
834     if(i+j>=slen) {
835       j=slen-i-1;
836       break;
837     }
838     if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
839     {
840       // Don't go past an unconditonal jump
841       j++;
842       break;
843     }
844   }
845   k=0;
846   if(i>0){
847     if(itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)
848       k--;
849   }
850   for(;k<j;k++)
851   {
852     if(r<64&&((unneeded_reg[i+k]>>r)&1)) return hr;
853     if(r>64&&((unneeded_reg_upper[i+k]>>r)&1)) return hr;
854     if(i+k>=0&&(itype[i+k]==UJUMP||itype[i+k]==CJUMP||itype[i+k]==SJUMP||itype[i+k]==FJUMP))
855     {
856       if(ba[i+k]>=start && ba[i+k]<(start+i*4))
857       {
858         int t=(ba[i+k]-start)>>2;
859         int reg=get_reg(regs[t].regmap_entry,r);
860         if(reg>=0) return reg;
861         //reg=get_reg(regs[t+1].regmap_entry,r);
862         //if(reg>=0) return reg;
863       }
864     }
865   }
866   return hr;
867 }
868
869
870 // Allocate every register, preserving source/target regs
871 void alloc_all(struct regstat *cur,int i)
872 {
873   int hr;
874   
875   for(hr=0;hr<HOST_REGS;hr++) {
876     if(hr!=EXCLUDE_REG) {
877       if(((cur->regmap[hr]&63)!=rs1[i])&&((cur->regmap[hr]&63)!=rs2[i])&&
878          ((cur->regmap[hr]&63)!=rt1[i])&&((cur->regmap[hr]&63)!=rt2[i]))
879       {
880         cur->regmap[hr]=-1;
881         cur->dirty&=~(1<<hr);
882       }
883       // Don't need zeros
884       if((cur->regmap[hr]&63)==0)
885       {
886         cur->regmap[hr]=-1;
887         cur->dirty&=~(1<<hr);
888       }
889     }
890   }
891 }
892
893 #ifndef FORCE32
894 void div64(int64_t dividend,int64_t divisor)
895 {
896   lo=dividend/divisor;
897   hi=dividend%divisor;
898   //printf("TRACE: ddiv %8x%8x %8x%8x\n" ,(int)reg[HIREG],(int)(reg[HIREG]>>32)
899   //                                     ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
900 }
901 void divu64(uint64_t dividend,uint64_t divisor)
902 {
903   lo=dividend/divisor;
904   hi=dividend%divisor;
905   //printf("TRACE: ddivu %8x%8x %8x%8x\n",(int)reg[HIREG],(int)(reg[HIREG]>>32)
906   //                                     ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
907 }
908
909 void mult64(uint64_t m1,uint64_t m2)
910 {
911    unsigned long long int op1, op2, op3, op4;
912    unsigned long long int result1, result2, result3, result4;
913    unsigned long long int temp1, temp2, temp3, temp4;
914    int sign = 0;
915    
916    if (m1 < 0)
917      {
918     op2 = -m1;
919     sign = 1 - sign;
920      }
921    else op2 = m1;
922    if (m2 < 0)
923      {
924     op4 = -m2;
925     sign = 1 - sign;
926      }
927    else op4 = m2;
928    
929    op1 = op2 & 0xFFFFFFFF;
930    op2 = (op2 >> 32) & 0xFFFFFFFF;
931    op3 = op4 & 0xFFFFFFFF;
932    op4 = (op4 >> 32) & 0xFFFFFFFF;
933    
934    temp1 = op1 * op3;
935    temp2 = (temp1 >> 32) + op1 * op4;
936    temp3 = op2 * op3;
937    temp4 = (temp3 >> 32) + op2 * op4;
938    
939    result1 = temp1 & 0xFFFFFFFF;
940    result2 = temp2 + (temp3 & 0xFFFFFFFF);
941    result3 = (result2 >> 32) + temp4;
942    result4 = (result3 >> 32);
943    
944    lo = result1 | (result2 << 32);
945    hi = (result3 & 0xFFFFFFFF) | (result4 << 32);
946    if (sign)
947      {
948     hi = ~hi;
949     if (!lo) hi++;
950     else lo = ~lo + 1;
951      }
952 }
953
954 void multu64(uint64_t m1,uint64_t m2)
955 {
956    unsigned long long int op1, op2, op3, op4;
957    unsigned long long int result1, result2, result3, result4;
958    unsigned long long int temp1, temp2, temp3, temp4;
959    
960    op1 = m1 & 0xFFFFFFFF;
961    op2 = (m1 >> 32) & 0xFFFFFFFF;
962    op3 = m2 & 0xFFFFFFFF;
963    op4 = (m2 >> 32) & 0xFFFFFFFF;
964    
965    temp1 = op1 * op3;
966    temp2 = (temp1 >> 32) + op1 * op4;
967    temp3 = op2 * op3;
968    temp4 = (temp3 >> 32) + op2 * op4;
969    
970    result1 = temp1 & 0xFFFFFFFF;
971    result2 = temp2 + (temp3 & 0xFFFFFFFF);
972    result3 = (result2 >> 32) + temp4;
973    result4 = (result3 >> 32);
974    
975    lo = result1 | (result2 << 32);
976    hi = (result3 & 0xFFFFFFFF) | (result4 << 32);
977    
978   //printf("TRACE: dmultu %8x%8x %8x%8x\n",(int)reg[HIREG],(int)(reg[HIREG]>>32)
979   //                                      ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
980 }
981
982 uint64_t ldl_merge(uint64_t original,uint64_t loaded,u_int bits)
983 {
984   if(bits) {
985     original<<=64-bits;
986     original>>=64-bits;
987     loaded<<=bits;
988     original|=loaded;
989   }
990   else original=loaded;
991   return original;
992 }
993 uint64_t ldr_merge(uint64_t original,uint64_t loaded,u_int bits)
994 {
995   if(bits^56) {
996     original>>=64-(bits^56);
997     original<<=64-(bits^56);
998     loaded>>=bits^56;
999     original|=loaded;
1000   }
1001   else original=loaded;
1002   return original;
1003 }
1004 #endif
1005
1006 #ifdef __i386__
1007 #include "assem_x86.c"
1008 #endif
1009 #ifdef __x86_64__
1010 #include "assem_x64.c"
1011 #endif
1012 #ifdef __arm__
1013 #include "assem_arm.c"
1014 #endif
1015
1016 // Add virtual address mapping to linked list
1017 void ll_add(struct ll_entry **head,int vaddr,void *addr)
1018 {
1019   struct ll_entry *new_entry;
1020   new_entry=malloc(sizeof(struct ll_entry));
1021   assert(new_entry!=NULL);
1022   new_entry->vaddr=vaddr;
1023   new_entry->reg32=0;
1024   new_entry->addr=addr;
1025   new_entry->next=*head;
1026   *head=new_entry;
1027 }
1028
1029 // Add virtual address mapping for 32-bit compiled block
1030 void ll_add_32(struct ll_entry **head,int vaddr,u_int reg32,void *addr)
1031 {
1032   ll_add(head,vaddr,addr);
1033 #ifndef FORCE32
1034   (*head)->reg32=reg32;
1035 #endif
1036 }
1037
1038 // Check if an address is already compiled
1039 // but don't return addresses which are about to expire from the cache
1040 void *check_addr(u_int vaddr)
1041 {
1042   u_int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
1043   if(ht_bin[0]==vaddr) {
1044     if(((ht_bin[1]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
1045       if(isclean(ht_bin[1])) return (void *)ht_bin[1];
1046   }
1047   if(ht_bin[2]==vaddr) {
1048     if(((ht_bin[3]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
1049       if(isclean(ht_bin[3])) return (void *)ht_bin[3];
1050   }
1051   u_int page=get_page(vaddr);
1052   struct ll_entry *head;
1053   head=jump_in[page];
1054   while(head!=NULL) {
1055     if(head->vaddr==vaddr&&head->reg32==0) {
1056       if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1057         // Update existing entry with current address
1058         if(ht_bin[0]==vaddr) {
1059           ht_bin[1]=(int)head->addr;
1060           return head->addr;
1061         }
1062         if(ht_bin[2]==vaddr) {
1063           ht_bin[3]=(int)head->addr;
1064           return head->addr;
1065         }
1066         // Insert into hash table with low priority.
1067         // Don't evict existing entries, as they are probably
1068         // addresses that are being accessed frequently.
1069         if(ht_bin[0]==-1) {
1070           ht_bin[1]=(int)head->addr;
1071           ht_bin[0]=vaddr;
1072         }else if(ht_bin[2]==-1) {
1073           ht_bin[3]=(int)head->addr;
1074           ht_bin[2]=vaddr;
1075         }
1076         return head->addr;
1077       }
1078     }
1079     head=head->next;
1080   }
1081   return 0;
1082 }
1083
1084 void remove_hash(int vaddr)
1085 {
1086   //printf("remove hash: %x\n",vaddr);
1087   int *ht_bin=hash_table[(((vaddr)>>16)^vaddr)&0xFFFF];
1088   if(ht_bin[2]==vaddr) {
1089     ht_bin[2]=ht_bin[3]=-1;
1090   }
1091   if(ht_bin[0]==vaddr) {
1092     ht_bin[0]=ht_bin[2];
1093     ht_bin[1]=ht_bin[3];
1094     ht_bin[2]=ht_bin[3]=-1;
1095   }
1096 }
1097
1098 void ll_remove_matching_addrs(struct ll_entry **head,int addr,int shift)
1099 {
1100   struct ll_entry *next;
1101   while(*head) {
1102     if(((u_int)((*head)->addr)>>shift)==(addr>>shift) || 
1103        ((u_int)((*head)->addr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift))
1104     {
1105       inv_debug("EXP: Remove pointer to %x (%x)\n",(int)(*head)->addr,(*head)->vaddr);
1106       remove_hash((*head)->vaddr);
1107       next=(*head)->next;
1108       free(*head);
1109       *head=next;
1110     }
1111     else
1112     {
1113       head=&((*head)->next);
1114     }
1115   }
1116 }
1117
1118 // Remove all entries from linked list
1119 void ll_clear(struct ll_entry **head)
1120 {
1121   struct ll_entry *cur;
1122   struct ll_entry *next;
1123   if(cur=*head) {
1124     *head=0;
1125     while(cur) {
1126       next=cur->next;
1127       free(cur);
1128       cur=next;
1129     }
1130   }
1131 }
1132
1133 // Dereference the pointers and remove if it matches
1134 void ll_kill_pointers(struct ll_entry *head,int addr,int shift)
1135 {
1136   while(head) {
1137     int ptr=get_pointer(head->addr);
1138     inv_debug("EXP: Lookup pointer to %x at %x (%x)\n",(int)ptr,(int)head->addr,head->vaddr);
1139     if(((ptr>>shift)==(addr>>shift)) ||
1140        (((ptr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift)))
1141     {
1142       inv_debug("EXP: Kill pointer at %x (%x)\n",(int)head->addr,head->vaddr);
1143       u_int host_addr=(u_int)kill_pointer(head->addr);
1144       #ifdef __arm__
1145         needs_clear_cache[(host_addr-(u_int)BASE_ADDR)>>17]|=1<<(((host_addr-(u_int)BASE_ADDR)>>12)&31);
1146       #endif
1147     }
1148     head=head->next;
1149   }
1150 }
1151
1152 // This is called when we write to a compiled block (see do_invstub)
1153 void invalidate_page(u_int page)
1154 {
1155   struct ll_entry *head;
1156   struct ll_entry *next;
1157   head=jump_in[page];
1158   jump_in[page]=0;
1159   while(head!=NULL) {
1160     inv_debug("INVALIDATE: %x\n",head->vaddr);
1161     remove_hash(head->vaddr);
1162     next=head->next;
1163     free(head);
1164     head=next;
1165   }
1166   head=jump_out[page];
1167   jump_out[page]=0;
1168   while(head!=NULL) {
1169     inv_debug("INVALIDATE: kill pointer to %x (%x)\n",head->vaddr,(int)head->addr);
1170     u_int host_addr=(u_int)kill_pointer(head->addr);
1171     #ifdef __arm__
1172       needs_clear_cache[(host_addr-(u_int)BASE_ADDR)>>17]|=1<<(((host_addr-(u_int)BASE_ADDR)>>12)&31);
1173     #endif
1174     next=head->next;
1175     free(head);
1176     head=next;
1177   }
1178 }
1179
1180 static void invalidate_block_range(u_int block, u_int first, u_int last)
1181 {
1182   u_int page=get_page(block<<12);
1183   //printf("first=%d last=%d\n",first,last);
1184   invalidate_page(page);
1185   assert(first+5>page); // NB: this assumes MAXBLOCK<=4096 (4 pages)
1186   assert(last<page+5);
1187   // Invalidate the adjacent pages if a block crosses a 4K boundary
1188   while(first<page) {
1189     invalidate_page(first);
1190     first++;
1191   }
1192   for(first=page+1;first<last;first++) {
1193     invalidate_page(first);
1194   }
1195   #ifdef __arm__
1196     do_clear_cache();
1197   #endif
1198   
1199   // Don't trap writes
1200   invalid_code[block]=1;
1201 #ifndef DISABLE_TLB
1202   // If there is a valid TLB entry for this page, remove write protect
1203   if(tlb_LUT_w[block]) {
1204     assert(tlb_LUT_r[block]==tlb_LUT_w[block]);
1205     // CHECK: Is this right?
1206     memory_map[block]=((tlb_LUT_w[block]&0xFFFFF000)-(block<<12)+(unsigned int)rdram-0x80000000)>>2;
1207     u_int real_block=tlb_LUT_w[block]>>12;
1208     invalid_code[real_block]=1;
1209     if(real_block>=0x80000&&real_block<0x80800) memory_map[real_block]=((u_int)rdram-0x80000000)>>2;
1210   }
1211   else if(block>=0x80000&&block<0x80800) memory_map[block]=((u_int)rdram-0x80000000)>>2;
1212 #endif
1213
1214   #ifdef USE_MINI_HT
1215   memset(mini_ht,-1,sizeof(mini_ht));
1216   #endif
1217 }
1218
1219 void invalidate_block(u_int block)
1220 {
1221   u_int page=get_page(block<<12);
1222   u_int vpage=get_vpage(block<<12);
1223   inv_debug("INVALIDATE: %x (%d)\n",block<<12,page);
1224   //inv_debug("invalid_code[block]=%d\n",invalid_code[block]);
1225   u_int first,last;
1226   first=last=page;
1227   struct ll_entry *head;
1228   head=jump_dirty[vpage];
1229   //printf("page=%d vpage=%d\n",page,vpage);
1230   while(head!=NULL) {
1231     u_int start,end;
1232     if(vpage>2047||(head->vaddr>>12)==block) { // Ignore vaddr hash collision
1233       get_bounds((int)head->addr,&start,&end);
1234       //printf("start: %x end: %x\n",start,end);
1235       if(page<2048&&start>=(u_int)rdram&&end<(u_int)rdram+RAM_SIZE) {
1236         if(((start-(u_int)rdram)>>12)<=page&&((end-1-(u_int)rdram)>>12)>=page) {
1237           if((((start-(u_int)rdram)>>12)&2047)<first) first=((start-(u_int)rdram)>>12)&2047;
1238           if((((end-1-(u_int)rdram)>>12)&2047)>last) last=((end-1-(u_int)rdram)>>12)&2047;
1239         }
1240       }
1241 #ifndef DISABLE_TLB
1242       if(page<2048&&(signed int)start>=(signed int)0xC0000000&&(signed int)end>=(signed int)0xC0000000) {
1243         if(((start+memory_map[start>>12]-(u_int)rdram)>>12)<=page&&((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)>=page) {
1244           if((((start+memory_map[start>>12]-(u_int)rdram)>>12)&2047)<first) first=((start+memory_map[start>>12]-(u_int)rdram)>>12)&2047;
1245           if((((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)&2047)>last) last=((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)&2047;
1246         }
1247       }
1248 #endif
1249     }
1250     head=head->next;
1251   }
1252   invalidate_block_range(block,first,last);
1253 }
1254
1255 void invalidate_addr(u_int addr)
1256 {
1257 #ifdef PCSX
1258   //static int rhits;
1259   // this check is done by the caller
1260   //if (inv_code_start<=addr&&addr<=inv_code_end) { rhits++; return; }
1261   u_int page=get_vpage(addr);
1262   if(page<2048) { // RAM
1263     struct ll_entry *head;
1264     u_int addr_min=~0, addr_max=0;
1265     u_int mask=RAM_SIZE-1;
1266     u_int addr_main=0x80000000|(addr&mask);
1267     int pg1;
1268     inv_code_start=addr_main&~0xfff;
1269     inv_code_end=addr_main|0xfff;
1270     pg1=page;
1271     if (pg1>0) {
1272       // must check previous page too because of spans..
1273       pg1--;
1274       inv_code_start-=0x1000;
1275     }
1276     for(;pg1<=page;pg1++) {
1277       for(head=jump_dirty[pg1];head!=NULL;head=head->next) {
1278         u_int start,end;
1279         get_bounds((int)head->addr,&start,&end);
1280         if(ram_offset) {
1281           start-=ram_offset;
1282           end-=ram_offset;
1283         }
1284         if(start<=addr_main&&addr_main<end) {
1285           if(start<addr_min) addr_min=start;
1286           if(end>addr_max) addr_max=end;
1287         }
1288         else if(addr_main<start) {
1289           if(start<inv_code_end)
1290             inv_code_end=start-1;
1291         }
1292         else {
1293           if(end>inv_code_start)
1294             inv_code_start=end;
1295         }
1296       }
1297     }
1298     if (addr_min!=~0) {
1299       inv_debug("INV ADDR: %08x hit %08x-%08x\n", addr, addr_min, addr_max);
1300       inv_code_start=inv_code_end=~0;
1301       invalidate_block_range(addr>>12,(addr_min&mask)>>12,(addr_max&mask)>>12);
1302       return;
1303     }
1304     else {
1305       inv_code_start=(addr&~mask)|(inv_code_start&mask);
1306       inv_code_end=(addr&~mask)|(inv_code_end&mask);
1307       inv_debug("INV ADDR: %08x miss, inv %08x-%08x, sk %d\n", addr, inv_code_start, inv_code_end, 0);
1308       return;
1309     }
1310   }
1311 #endif
1312   invalidate_block(addr>>12);
1313 }
1314
1315 // This is called when loading a save state.
1316 // Anything could have changed, so invalidate everything.
1317 void invalidate_all_pages()
1318 {
1319   u_int page,n;
1320   for(page=0;page<4096;page++)
1321     invalidate_page(page);
1322   for(page=0;page<1048576;page++)
1323     if(!invalid_code[page]) {
1324       restore_candidate[(page&2047)>>3]|=1<<(page&7);
1325       restore_candidate[((page&2047)>>3)+256]|=1<<(page&7);
1326     }
1327   #ifdef __arm__
1328   __clear_cache((void *)BASE_ADDR,(void *)BASE_ADDR+(1<<TARGET_SIZE_2));
1329   #endif
1330   #ifdef USE_MINI_HT
1331   memset(mini_ht,-1,sizeof(mini_ht));
1332   #endif
1333   #ifndef DISABLE_TLB
1334   // TLB
1335   for(page=0;page<0x100000;page++) {
1336     if(tlb_LUT_r[page]) {
1337       memory_map[page]=((tlb_LUT_r[page]&0xFFFFF000)-(page<<12)+(unsigned int)rdram-0x80000000)>>2;
1338       if(!tlb_LUT_w[page]||!invalid_code[page])
1339         memory_map[page]|=0x40000000; // Write protect
1340     }
1341     else memory_map[page]=-1;
1342     if(page==0x80000) page=0xC0000;
1343   }
1344   tlb_hacks();
1345   #endif
1346 }
1347
1348 // Add an entry to jump_out after making a link
1349 void add_link(u_int vaddr,void *src)
1350 {
1351   u_int page=get_page(vaddr);
1352   inv_debug("add_link: %x -> %x (%d)\n",(int)src,vaddr,page);
1353   int *ptr=(int *)(src+4);
1354   assert((*ptr&0x0fff0000)==0x059f0000);
1355   ll_add(jump_out+page,vaddr,src);
1356   //int ptr=get_pointer(src);
1357   //inv_debug("add_link: Pointer is to %x\n",(int)ptr);
1358 }
1359
1360 // If a code block was found to be unmodified (bit was set in
1361 // restore_candidate) and it remains unmodified (bit is clear
1362 // in invalid_code) then move the entries for that 4K page from
1363 // the dirty list to the clean list.
1364 void clean_blocks(u_int page)
1365 {
1366   struct ll_entry *head;
1367   inv_debug("INV: clean_blocks page=%d\n",page);
1368   head=jump_dirty[page];
1369   while(head!=NULL) {
1370     if(!invalid_code[head->vaddr>>12]) {
1371       // Don't restore blocks which are about to expire from the cache
1372       if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1373         u_int start,end;
1374         if(verify_dirty((int)head->addr)) {
1375           //printf("Possibly Restore %x (%x)\n",head->vaddr, (int)head->addr);
1376           u_int i;
1377           u_int inv=0;
1378           get_bounds((int)head->addr,&start,&end);
1379           if(start-(u_int)rdram<RAM_SIZE) {
1380             for(i=(start-(u_int)rdram+0x80000000)>>12;i<=(end-1-(u_int)rdram+0x80000000)>>12;i++) {
1381               inv|=invalid_code[i];
1382             }
1383           }
1384 #ifndef DISABLE_TLB
1385           if((signed int)head->vaddr>=(signed int)0xC0000000) {
1386             u_int addr = (head->vaddr+(memory_map[head->vaddr>>12]<<2));
1387             //printf("addr=%x start=%x end=%x\n",addr,start,end);
1388             if(addr<start||addr>=end) inv=1;
1389           }
1390 #endif
1391           else if((signed int)head->vaddr>=(signed int)0x80000000+RAM_SIZE) {
1392             inv=1;
1393           }
1394           if(!inv) {
1395             void * clean_addr=(void *)get_clean_addr((int)head->addr);
1396             if((((u_int)clean_addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1397               u_int ppage=page;
1398 #ifndef DISABLE_TLB
1399               if(page<2048&&tlb_LUT_r[head->vaddr>>12]) ppage=(tlb_LUT_r[head->vaddr>>12]^0x80000000)>>12;
1400 #endif
1401               inv_debug("INV: Restored %x (%x/%x)\n",head->vaddr, (int)head->addr, (int)clean_addr);
1402               //printf("page=%x, addr=%x\n",page,head->vaddr);
1403               //assert(head->vaddr>>12==(page|0x80000));
1404               ll_add_32(jump_in+ppage,head->vaddr,head->reg32,clean_addr);
1405               int *ht_bin=hash_table[((head->vaddr>>16)^head->vaddr)&0xFFFF];
1406               if(!head->reg32) {
1407                 if(ht_bin[0]==head->vaddr) {
1408                   ht_bin[1]=(int)clean_addr; // Replace existing entry
1409                 }
1410                 if(ht_bin[2]==head->vaddr) {
1411                   ht_bin[3]=(int)clean_addr; // Replace existing entry
1412                 }
1413               }
1414             }
1415           }
1416         }
1417       }
1418     }
1419     head=head->next;
1420   }
1421 }
1422
1423
1424 void mov_alloc(struct regstat *current,int i)
1425 {
1426   // Note: Don't need to actually alloc the source registers
1427   if((~current->is32>>rs1[i])&1) {
1428     //alloc_reg64(current,i,rs1[i]);
1429     alloc_reg64(current,i,rt1[i]);
1430     current->is32&=~(1LL<<rt1[i]);
1431   } else {
1432     //alloc_reg(current,i,rs1[i]);
1433     alloc_reg(current,i,rt1[i]);
1434     current->is32|=(1LL<<rt1[i]);
1435   }
1436   clear_const(current,rs1[i]);
1437   clear_const(current,rt1[i]);
1438   dirty_reg(current,rt1[i]);
1439 }
1440
1441 void shiftimm_alloc(struct regstat *current,int i)
1442 {
1443   if(opcode2[i]<=0x3) // SLL/SRL/SRA
1444   {
1445     if(rt1[i]) {
1446       if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1447       else lt1[i]=rs1[i];
1448       alloc_reg(current,i,rt1[i]);
1449       current->is32|=1LL<<rt1[i];
1450       dirty_reg(current,rt1[i]);
1451       if(is_const(current,rs1[i])) {
1452         int v=get_const(current,rs1[i]);
1453         if(opcode2[i]==0x00) set_const(current,rt1[i],v<<imm[i]);
1454         if(opcode2[i]==0x02) set_const(current,rt1[i],(u_int)v>>imm[i]);
1455         if(opcode2[i]==0x03) set_const(current,rt1[i],v>>imm[i]);
1456       }
1457       else clear_const(current,rt1[i]);
1458     }
1459   }
1460   else
1461   {
1462     clear_const(current,rs1[i]);
1463     clear_const(current,rt1[i]);
1464   }
1465
1466   if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA
1467   {
1468     if(rt1[i]) {
1469       if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1470       alloc_reg64(current,i,rt1[i]);
1471       current->is32&=~(1LL<<rt1[i]);
1472       dirty_reg(current,rt1[i]);
1473     }
1474   }
1475   if(opcode2[i]==0x3c) // DSLL32
1476   {
1477     if(rt1[i]) {
1478       if(rs1[i]) alloc_reg(current,i,rs1[i]);
1479       alloc_reg64(current,i,rt1[i]);
1480       current->is32&=~(1LL<<rt1[i]);
1481       dirty_reg(current,rt1[i]);
1482     }
1483   }
1484   if(opcode2[i]==0x3e) // DSRL32
1485   {
1486     if(rt1[i]) {
1487       alloc_reg64(current,i,rs1[i]);
1488       if(imm[i]==32) {
1489         alloc_reg64(current,i,rt1[i]);
1490         current->is32&=~(1LL<<rt1[i]);
1491       } else {
1492         alloc_reg(current,i,rt1[i]);
1493         current->is32|=1LL<<rt1[i];
1494       }
1495       dirty_reg(current,rt1[i]);
1496     }
1497   }
1498   if(opcode2[i]==0x3f) // DSRA32
1499   {
1500     if(rt1[i]) {
1501       alloc_reg64(current,i,rs1[i]);
1502       alloc_reg(current,i,rt1[i]);
1503       current->is32|=1LL<<rt1[i];
1504       dirty_reg(current,rt1[i]);
1505     }
1506   }
1507 }
1508
1509 void shift_alloc(struct regstat *current,int i)
1510 {
1511   if(rt1[i]) {
1512     if(opcode2[i]<=0x07) // SLLV/SRLV/SRAV
1513     {
1514       if(rs1[i]) alloc_reg(current,i,rs1[i]);
1515       if(rs2[i]) alloc_reg(current,i,rs2[i]);
1516       alloc_reg(current,i,rt1[i]);
1517       if(rt1[i]==rs2[i]) {
1518         alloc_reg_temp(current,i,-1);
1519         minimum_free_regs[i]=1;
1520       }
1521       current->is32|=1LL<<rt1[i];
1522     } else { // DSLLV/DSRLV/DSRAV
1523       if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1524       if(rs2[i]) alloc_reg(current,i,rs2[i]);
1525       alloc_reg64(current,i,rt1[i]);
1526       current->is32&=~(1LL<<rt1[i]);
1527       if(opcode2[i]==0x16||opcode2[i]==0x17) // DSRLV and DSRAV need a temporary register
1528       {
1529         alloc_reg_temp(current,i,-1);
1530         minimum_free_regs[i]=1;
1531       }
1532     }
1533     clear_const(current,rs1[i]);
1534     clear_const(current,rs2[i]);
1535     clear_const(current,rt1[i]);
1536     dirty_reg(current,rt1[i]);
1537   }
1538 }
1539
1540 void alu_alloc(struct regstat *current,int i)
1541 {
1542   if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
1543     if(rt1[i]) {
1544       if(rs1[i]&&rs2[i]) {
1545         alloc_reg(current,i,rs1[i]);
1546         alloc_reg(current,i,rs2[i]);
1547       }
1548       else {
1549         if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1550         if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]);
1551       }
1552       alloc_reg(current,i,rt1[i]);
1553     }
1554     current->is32|=1LL<<rt1[i];
1555   }
1556   if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU
1557     if(rt1[i]) {
1558       if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1559       {
1560         alloc_reg64(current,i,rs1[i]);
1561         alloc_reg64(current,i,rs2[i]);
1562         alloc_reg(current,i,rt1[i]);
1563       } else {
1564         alloc_reg(current,i,rs1[i]);
1565         alloc_reg(current,i,rs2[i]);
1566         alloc_reg(current,i,rt1[i]);
1567       }
1568     }
1569     current->is32|=1LL<<rt1[i];
1570   }
1571   if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR
1572     if(rt1[i]) {
1573       if(rs1[i]&&rs2[i]) {
1574         alloc_reg(current,i,rs1[i]);
1575         alloc_reg(current,i,rs2[i]);
1576       }
1577       else
1578       {
1579         if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1580         if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]);
1581       }
1582       alloc_reg(current,i,rt1[i]);
1583       if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1584       {
1585         if(!((current->uu>>rt1[i])&1)) {
1586           alloc_reg64(current,i,rt1[i]);
1587         }
1588         if(get_reg(current->regmap,rt1[i]|64)>=0) {
1589           if(rs1[i]&&rs2[i]) {
1590             alloc_reg64(current,i,rs1[i]);
1591             alloc_reg64(current,i,rs2[i]);
1592           }
1593           else
1594           {
1595             // Is is really worth it to keep 64-bit values in registers?
1596             #ifdef NATIVE_64BIT
1597             if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]);
1598             if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg64(current,i,rs2[i]);
1599             #endif
1600           }
1601         }
1602         current->is32&=~(1LL<<rt1[i]);
1603       } else {
1604         current->is32|=1LL<<rt1[i];
1605       }
1606     }
1607   }
1608   if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU
1609     if(rt1[i]) {
1610       if(rs1[i]&&rs2[i]) {
1611         if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1612           alloc_reg64(current,i,rs1[i]);
1613           alloc_reg64(current,i,rs2[i]);
1614           alloc_reg64(current,i,rt1[i]);
1615         } else {
1616           alloc_reg(current,i,rs1[i]);
1617           alloc_reg(current,i,rs2[i]);
1618           alloc_reg(current,i,rt1[i]);
1619         }
1620       }
1621       else {
1622         alloc_reg(current,i,rt1[i]);
1623         if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1624           // DADD used as move, or zeroing
1625           // If we have a 64-bit source, then make the target 64 bits too
1626           if(rs1[i]&&!((current->is32>>rs1[i])&1)) {
1627             if(get_reg(current->regmap,rs1[i])>=0) alloc_reg64(current,i,rs1[i]);
1628             alloc_reg64(current,i,rt1[i]);
1629           } else if(rs2[i]&&!((current->is32>>rs2[i])&1)) {
1630             if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]);
1631             alloc_reg64(current,i,rt1[i]);
1632           }
1633           if(opcode2[i]>=0x2e&&rs2[i]) {
1634             // DSUB used as negation - 64-bit result
1635             // If we have a 32-bit register, extend it to 64 bits
1636             if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]);
1637             alloc_reg64(current,i,rt1[i]);
1638           }
1639         }
1640       }
1641       if(rs1[i]&&rs2[i]) {
1642         current->is32&=~(1LL<<rt1[i]);
1643       } else if(rs1[i]) {
1644         current->is32&=~(1LL<<rt1[i]);
1645         if((current->is32>>rs1[i])&1)
1646           current->is32|=1LL<<rt1[i];
1647       } else if(rs2[i]) {
1648         current->is32&=~(1LL<<rt1[i]);
1649         if((current->is32>>rs2[i])&1)
1650           current->is32|=1LL<<rt1[i];
1651       } else {
1652         current->is32|=1LL<<rt1[i];
1653       }
1654     }
1655   }
1656   clear_const(current,rs1[i]);
1657   clear_const(current,rs2[i]);
1658   clear_const(current,rt1[i]);
1659   dirty_reg(current,rt1[i]);
1660 }
1661
1662 void imm16_alloc(struct regstat *current,int i)
1663 {
1664   if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1665   else lt1[i]=rs1[i];
1666   if(rt1[i]) alloc_reg(current,i,rt1[i]);
1667   if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU
1668     current->is32&=~(1LL<<rt1[i]);
1669     if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1670       // TODO: Could preserve the 32-bit flag if the immediate is zero
1671       alloc_reg64(current,i,rt1[i]);
1672       alloc_reg64(current,i,rs1[i]);
1673     }
1674     clear_const(current,rs1[i]);
1675     clear_const(current,rt1[i]);
1676   }
1677   else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU
1678     if((~current->is32>>rs1[i])&1) alloc_reg64(current,i,rs1[i]);
1679     current->is32|=1LL<<rt1[i];
1680     clear_const(current,rs1[i]);
1681     clear_const(current,rt1[i]);
1682   }
1683   else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI
1684     if(((~current->is32>>rs1[i])&1)&&opcode[i]>0x0c) {
1685       if(rs1[i]!=rt1[i]) {
1686         if(needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]);
1687         alloc_reg64(current,i,rt1[i]);
1688         current->is32&=~(1LL<<rt1[i]);
1689       }
1690     }
1691     else current->is32|=1LL<<rt1[i]; // ANDI clears upper bits
1692     if(is_const(current,rs1[i])) {
1693       int v=get_const(current,rs1[i]);
1694       if(opcode[i]==0x0c) set_const(current,rt1[i],v&imm[i]);
1695       if(opcode[i]==0x0d) set_const(current,rt1[i],v|imm[i]);
1696       if(opcode[i]==0x0e) set_const(current,rt1[i],v^imm[i]);
1697     }
1698     else clear_const(current,rt1[i]);
1699   }
1700   else if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU
1701     if(is_const(current,rs1[i])) {
1702       int v=get_const(current,rs1[i]);
1703       set_const(current,rt1[i],v+imm[i]);
1704     }
1705     else clear_const(current,rt1[i]);
1706     current->is32|=1LL<<rt1[i];
1707   }
1708   else {
1709     set_const(current,rt1[i],((long long)((short)imm[i]))<<16); // LUI
1710     current->is32|=1LL<<rt1[i];
1711   }
1712   dirty_reg(current,rt1[i]);
1713 }
1714
1715 void load_alloc(struct regstat *current,int i)
1716 {
1717   clear_const(current,rt1[i]);
1718   //if(rs1[i]!=rt1[i]&&needed_again(rs1[i],i)) clear_const(current,rs1[i]); // Does this help or hurt?
1719   if(!rs1[i]) current->u&=~1LL; // Allow allocating r0 if it's the source register
1720   if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1721   if(rt1[i]&&!((current->u>>rt1[i])&1)) {
1722     alloc_reg(current,i,rt1[i]);
1723     assert(get_reg(current->regmap,rt1[i])>=0);
1724     if(opcode[i]==0x27||opcode[i]==0x37) // LWU/LD
1725     {
1726       current->is32&=~(1LL<<rt1[i]);
1727       alloc_reg64(current,i,rt1[i]);
1728     }
1729     else if(opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
1730     {
1731       current->is32&=~(1LL<<rt1[i]);
1732       alloc_reg64(current,i,rt1[i]);
1733       alloc_all(current,i);
1734       alloc_reg64(current,i,FTEMP);
1735       minimum_free_regs[i]=HOST_REGS;
1736     }
1737     else current->is32|=1LL<<rt1[i];
1738     dirty_reg(current,rt1[i]);
1739     // If using TLB, need a register for pointer to the mapping table
1740     if(using_tlb) alloc_reg(current,i,TLREG);
1741     // LWL/LWR need a temporary register for the old value
1742     if(opcode[i]==0x22||opcode[i]==0x26)
1743     {
1744       alloc_reg(current,i,FTEMP);
1745       alloc_reg_temp(current,i,-1);
1746       minimum_free_regs[i]=1;
1747     }
1748   }
1749   else
1750   {
1751     // Load to r0 or unneeded register (dummy load)
1752     // but we still need a register to calculate the address
1753     if(opcode[i]==0x22||opcode[i]==0x26)
1754     {
1755       alloc_reg(current,i,FTEMP); // LWL/LWR need another temporary
1756     }
1757     // If using TLB, need a register for pointer to the mapping table
1758     if(using_tlb) alloc_reg(current,i,TLREG);
1759     alloc_reg_temp(current,i,-1);
1760     minimum_free_regs[i]=1;
1761     if(opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
1762     {
1763       alloc_all(current,i);
1764       alloc_reg64(current,i,FTEMP);
1765       minimum_free_regs[i]=HOST_REGS;
1766     }
1767   }
1768 }
1769
1770 void store_alloc(struct regstat *current,int i)
1771 {
1772   clear_const(current,rs2[i]);
1773   if(!(rs2[i])) current->u&=~1LL; // Allow allocating r0 if necessary
1774   if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1775   alloc_reg(current,i,rs2[i]);
1776   if(opcode[i]==0x2c||opcode[i]==0x2d||opcode[i]==0x3f) { // 64-bit SDL/SDR/SD
1777     alloc_reg64(current,i,rs2[i]);
1778     if(rs2[i]) alloc_reg(current,i,FTEMP);
1779   }
1780   // If using TLB, need a register for pointer to the mapping table
1781   if(using_tlb) alloc_reg(current,i,TLREG);
1782   #if defined(HOST_IMM8)
1783   // On CPUs without 32-bit immediates we need a pointer to invalid_code
1784   else alloc_reg(current,i,INVCP);
1785   #endif
1786   if(opcode[i]==0x2a||opcode[i]==0x2e||opcode[i]==0x2c||opcode[i]==0x2d) { // SWL/SWL/SDL/SDR
1787     alloc_reg(current,i,FTEMP);
1788   }
1789   // We need a temporary register for address generation
1790   alloc_reg_temp(current,i,-1);
1791   minimum_free_regs[i]=1;
1792 }
1793
1794 void c1ls_alloc(struct regstat *current,int i)
1795 {
1796   //clear_const(current,rs1[i]); // FIXME
1797   clear_const(current,rt1[i]);
1798   if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1799   alloc_reg(current,i,CSREG); // Status
1800   alloc_reg(current,i,FTEMP);
1801   if(opcode[i]==0x35||opcode[i]==0x3d) { // 64-bit LDC1/SDC1
1802     alloc_reg64(current,i,FTEMP);
1803   }
1804   // If using TLB, need a register for pointer to the mapping table
1805   if(using_tlb) alloc_reg(current,i,TLREG);
1806   #if defined(HOST_IMM8)
1807   // On CPUs without 32-bit immediates we need a pointer to invalid_code
1808   else if((opcode[i]&0x3b)==0x39) // SWC1/SDC1
1809     alloc_reg(current,i,INVCP);
1810   #endif
1811   // We need a temporary register for address generation
1812   alloc_reg_temp(current,i,-1);
1813 }
1814
1815 void c2ls_alloc(struct regstat *current,int i)
1816 {
1817   clear_const(current,rt1[i]);
1818   if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1819   alloc_reg(current,i,FTEMP);
1820   // If using TLB, need a register for pointer to the mapping table
1821   if(using_tlb) alloc_reg(current,i,TLREG);
1822   #if defined(HOST_IMM8)
1823   // On CPUs without 32-bit immediates we need a pointer to invalid_code
1824   else if((opcode[i]&0x3b)==0x3a) // SWC2/SDC2
1825     alloc_reg(current,i,INVCP);
1826   #endif
1827   // We need a temporary register for address generation
1828   alloc_reg_temp(current,i,-1);
1829   minimum_free_regs[i]=1;
1830 }
1831
1832 #ifndef multdiv_alloc
1833 void multdiv_alloc(struct regstat *current,int i)
1834 {
1835   //  case 0x18: MULT
1836   //  case 0x19: MULTU
1837   //  case 0x1A: DIV
1838   //  case 0x1B: DIVU
1839   //  case 0x1C: DMULT
1840   //  case 0x1D: DMULTU
1841   //  case 0x1E: DDIV
1842   //  case 0x1F: DDIVU
1843   clear_const(current,rs1[i]);
1844   clear_const(current,rs2[i]);
1845   if(rs1[i]&&rs2[i])
1846   {
1847     if((opcode2[i]&4)==0) // 32-bit
1848     {
1849       current->u&=~(1LL<<HIREG);
1850       current->u&=~(1LL<<LOREG);
1851       alloc_reg(current,i,HIREG);
1852       alloc_reg(current,i,LOREG);
1853       alloc_reg(current,i,rs1[i]);
1854       alloc_reg(current,i,rs2[i]);
1855       current->is32|=1LL<<HIREG;
1856       current->is32|=1LL<<LOREG;
1857       dirty_reg(current,HIREG);
1858       dirty_reg(current,LOREG);
1859     }
1860     else // 64-bit
1861     {
1862       current->u&=~(1LL<<HIREG);
1863       current->u&=~(1LL<<LOREG);
1864       current->uu&=~(1LL<<HIREG);
1865       current->uu&=~(1LL<<LOREG);
1866       alloc_reg64(current,i,HIREG);
1867       //if(HOST_REGS>10) alloc_reg64(current,i,LOREG);
1868       alloc_reg64(current,i,rs1[i]);
1869       alloc_reg64(current,i,rs2[i]);
1870       alloc_all(current,i);
1871       current->is32&=~(1LL<<HIREG);
1872       current->is32&=~(1LL<<LOREG);
1873       dirty_reg(current,HIREG);
1874       dirty_reg(current,LOREG);
1875       minimum_free_regs[i]=HOST_REGS;
1876     }
1877   }
1878   else
1879   {
1880     // Multiply by zero is zero.
1881     // MIPS does not have a divide by zero exception.
1882     // The result is undefined, we return zero.
1883     alloc_reg(current,i,HIREG);
1884     alloc_reg(current,i,LOREG);
1885     current->is32|=1LL<<HIREG;
1886     current->is32|=1LL<<LOREG;
1887     dirty_reg(current,HIREG);
1888     dirty_reg(current,LOREG);
1889   }
1890 }
1891 #endif
1892
1893 void cop0_alloc(struct regstat *current,int i)
1894 {
1895   if(opcode2[i]==0) // MFC0
1896   {
1897     if(rt1[i]) {
1898       clear_const(current,rt1[i]);
1899       alloc_all(current,i);
1900       alloc_reg(current,i,rt1[i]);
1901       current->is32|=1LL<<rt1[i];
1902       dirty_reg(current,rt1[i]);
1903     }
1904   }
1905   else if(opcode2[i]==4) // MTC0
1906   {
1907     if(rs1[i]){
1908       clear_const(current,rs1[i]);
1909       alloc_reg(current,i,rs1[i]);
1910       alloc_all(current,i);
1911     }
1912     else {
1913       alloc_all(current,i); // FIXME: Keep r0
1914       current->u&=~1LL;
1915       alloc_reg(current,i,0);
1916     }
1917   }
1918   else
1919   {
1920     // TLBR/TLBWI/TLBWR/TLBP/ERET
1921     assert(opcode2[i]==0x10);
1922     alloc_all(current,i);
1923   }
1924   minimum_free_regs[i]=HOST_REGS;
1925 }
1926
1927 void cop1_alloc(struct regstat *current,int i)
1928 {
1929   alloc_reg(current,i,CSREG); // Load status
1930   if(opcode2[i]<3) // MFC1/DMFC1/CFC1
1931   {
1932     if(rt1[i]){
1933       clear_const(current,rt1[i]);
1934       if(opcode2[i]==1) {
1935         alloc_reg64(current,i,rt1[i]); // DMFC1
1936         current->is32&=~(1LL<<rt1[i]);
1937       }else{
1938         alloc_reg(current,i,rt1[i]); // MFC1/CFC1
1939         current->is32|=1LL<<rt1[i];
1940       }
1941       dirty_reg(current,rt1[i]);
1942     }
1943     alloc_reg_temp(current,i,-1);
1944   }
1945   else if(opcode2[i]>3) // MTC1/DMTC1/CTC1
1946   {
1947     if(rs1[i]){
1948       clear_const(current,rs1[i]);
1949       if(opcode2[i]==5)
1950         alloc_reg64(current,i,rs1[i]); // DMTC1
1951       else
1952         alloc_reg(current,i,rs1[i]); // MTC1/CTC1
1953       alloc_reg_temp(current,i,-1);
1954     }
1955     else {
1956       current->u&=~1LL;
1957       alloc_reg(current,i,0);
1958       alloc_reg_temp(current,i,-1);
1959     }
1960   }
1961   minimum_free_regs[i]=1;
1962 }
1963 void fconv_alloc(struct regstat *current,int i)
1964 {
1965   alloc_reg(current,i,CSREG); // Load status
1966   alloc_reg_temp(current,i,-1);
1967   minimum_free_regs[i]=1;
1968 }
1969 void float_alloc(struct regstat *current,int i)
1970 {
1971   alloc_reg(current,i,CSREG); // Load status
1972   alloc_reg_temp(current,i,-1);
1973   minimum_free_regs[i]=1;
1974 }
1975 void c2op_alloc(struct regstat *current,int i)
1976 {
1977   alloc_reg_temp(current,i,-1);
1978 }
1979 void fcomp_alloc(struct regstat *current,int i)
1980 {
1981   alloc_reg(current,i,CSREG); // Load status
1982   alloc_reg(current,i,FSREG); // Load flags
1983   dirty_reg(current,FSREG); // Flag will be modified
1984   alloc_reg_temp(current,i,-1);
1985   minimum_free_regs[i]=1;
1986 }
1987
1988 void syscall_alloc(struct regstat *current,int i)
1989 {
1990   alloc_cc(current,i);
1991   dirty_reg(current,CCREG);
1992   alloc_all(current,i);
1993   minimum_free_regs[i]=HOST_REGS;
1994   current->isconst=0;
1995 }
1996
1997 void delayslot_alloc(struct regstat *current,int i)
1998 {
1999   switch(itype[i]) {
2000     case UJUMP:
2001     case CJUMP:
2002     case SJUMP:
2003     case RJUMP:
2004     case FJUMP:
2005     case SYSCALL:
2006     case HLECALL:
2007     case SPAN:
2008       assem_debug("jump in the delay slot.  this shouldn't happen.\n");//exit(1);
2009       SysPrintf("Disabled speculative precompilation\n");
2010       stop_after_jal=1;
2011       break;
2012     case IMM16:
2013       imm16_alloc(current,i);
2014       break;
2015     case LOAD:
2016     case LOADLR:
2017       load_alloc(current,i);
2018       break;
2019     case STORE:
2020     case STORELR:
2021       store_alloc(current,i);
2022       break;
2023     case ALU:
2024       alu_alloc(current,i);
2025       break;
2026     case SHIFT:
2027       shift_alloc(current,i);
2028       break;
2029     case MULTDIV:
2030       multdiv_alloc(current,i);
2031       break;
2032     case SHIFTIMM:
2033       shiftimm_alloc(current,i);
2034       break;
2035     case MOV:
2036       mov_alloc(current,i);
2037       break;
2038     case COP0:
2039       cop0_alloc(current,i);
2040       break;
2041     case COP1:
2042     case COP2:
2043       cop1_alloc(current,i);
2044       break;
2045     case C1LS:
2046       c1ls_alloc(current,i);
2047       break;
2048     case C2LS:
2049       c2ls_alloc(current,i);
2050       break;
2051     case FCONV:
2052       fconv_alloc(current,i);
2053       break;
2054     case FLOAT:
2055       float_alloc(current,i);
2056       break;
2057     case FCOMP:
2058       fcomp_alloc(current,i);
2059       break;
2060     case C2OP:
2061       c2op_alloc(current,i);
2062       break;
2063   }
2064 }
2065
2066 // Special case where a branch and delay slot span two pages in virtual memory
2067 static void pagespan_alloc(struct regstat *current,int i)
2068 {
2069   current->isconst=0;
2070   current->wasconst=0;
2071   regs[i].wasconst=0;
2072   minimum_free_regs[i]=HOST_REGS;
2073   alloc_all(current,i);
2074   alloc_cc(current,i);
2075   dirty_reg(current,CCREG);
2076   if(opcode[i]==3) // JAL
2077   {
2078     alloc_reg(current,i,31);
2079     dirty_reg(current,31);
2080   }
2081   if(opcode[i]==0&&(opcode2[i]&0x3E)==8) // JR/JALR
2082   {
2083     alloc_reg(current,i,rs1[i]);
2084     if (rt1[i]!=0) {
2085       alloc_reg(current,i,rt1[i]);
2086       dirty_reg(current,rt1[i]);
2087     }
2088   }
2089   if((opcode[i]&0x2E)==4) // BEQ/BNE/BEQL/BNEL
2090   {
2091     if(rs1[i]) alloc_reg(current,i,rs1[i]);
2092     if(rs2[i]) alloc_reg(current,i,rs2[i]);
2093     if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
2094     {
2095       if(rs1[i]) alloc_reg64(current,i,rs1[i]);
2096       if(rs2[i]) alloc_reg64(current,i,rs2[i]);
2097     }
2098   }
2099   else
2100   if((opcode[i]&0x2E)==6) // BLEZ/BGTZ/BLEZL/BGTZL
2101   {
2102     if(rs1[i]) alloc_reg(current,i,rs1[i]);
2103     if(!((current->is32>>rs1[i])&1))
2104     {
2105       if(rs1[i]) alloc_reg64(current,i,rs1[i]);
2106     }
2107   }
2108   else
2109   if(opcode[i]==0x11) // BC1
2110   {
2111     alloc_reg(current,i,FSREG);
2112     alloc_reg(current,i,CSREG);
2113   }
2114   //else ...
2115 }
2116
2117 add_stub(int type,int addr,int retaddr,int a,int b,int c,int d,int e)
2118 {
2119   stubs[stubcount][0]=type;
2120   stubs[stubcount][1]=addr;
2121   stubs[stubcount][2]=retaddr;
2122   stubs[stubcount][3]=a;
2123   stubs[stubcount][4]=b;
2124   stubs[stubcount][5]=c;
2125   stubs[stubcount][6]=d;
2126   stubs[stubcount][7]=e;
2127   stubcount++;
2128 }
2129
2130 // Write out a single register
2131 void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32)
2132 {
2133   int hr;
2134   for(hr=0;hr<HOST_REGS;hr++) {
2135     if(hr!=EXCLUDE_REG) {
2136       if((regmap[hr]&63)==r) {
2137         if((dirty>>hr)&1) {
2138           if(regmap[hr]<64) {
2139             emit_storereg(r,hr);
2140 #ifndef FORCE32
2141             if((is32>>regmap[hr])&1) {
2142               emit_sarimm(hr,31,hr);
2143               emit_storereg(r|64,hr);
2144             }
2145 #endif
2146           }else{
2147             emit_storereg(r|64,hr);
2148           }
2149         }
2150       }
2151     }
2152   }
2153 }
2154
2155 int mchecksum()
2156 {
2157   //if(!tracedebug) return 0;
2158   int i;
2159   int sum=0;
2160   for(i=0;i<2097152;i++) {
2161     unsigned int temp=sum;
2162     sum<<=1;
2163     sum|=(~temp)>>31;
2164     sum^=((u_int *)rdram)[i];
2165   }
2166   return sum;
2167 }
2168 int rchecksum()
2169 {
2170   int i;
2171   int sum=0;
2172   for(i=0;i<64;i++)
2173     sum^=((u_int *)reg)[i];
2174   return sum;
2175 }
2176 void rlist()
2177 {
2178   int i;
2179   printf("TRACE: ");
2180   for(i=0;i<32;i++)
2181     printf("r%d:%8x%8x ",i,((int *)(reg+i))[1],((int *)(reg+i))[0]);
2182   printf("\n");
2183 #ifndef DISABLE_COP1
2184   printf("TRACE: ");
2185   for(i=0;i<32;i++)
2186     printf("f%d:%8x%8x ",i,((int*)reg_cop1_simple[i])[1],*((int*)reg_cop1_simple[i]));
2187   printf("\n");
2188 #endif
2189 }
2190
2191 void enabletrace()
2192 {
2193   tracedebug=1;
2194 }
2195
2196 void memdebug(int i)
2197 {
2198   //printf("TRACE: count=%d next=%d (checksum %x) lo=%8x%8x\n",Count,next_interupt,mchecksum(),(int)(reg[LOREG]>>32),(int)reg[LOREG]);
2199   //printf("TRACE: count=%d next=%d (rchecksum %x)\n",Count,next_interupt,rchecksum());
2200   //rlist();
2201   //if(tracedebug) {
2202   //if(Count>=-2084597794) {
2203   if((signed int)Count>=-2084597794&&(signed int)Count<0) {
2204   //if(0) {
2205     printf("TRACE: count=%d next=%d (checksum %x)\n",Count,next_interupt,mchecksum());
2206     //printf("TRACE: count=%d next=%d (checksum %x) Status=%x\n",Count,next_interupt,mchecksum(),Status);
2207     //printf("TRACE: count=%d next=%d (checksum %x) hi=%8x%8x\n",Count,next_interupt,mchecksum(),(int)(reg[HIREG]>>32),(int)reg[HIREG]);
2208     rlist();
2209     #ifdef __i386__
2210     printf("TRACE: %x\n",(&i)[-1]);
2211     #endif
2212     #ifdef __arm__
2213     int j;
2214     printf("TRACE: %x \n",(&j)[10]);
2215     printf("TRACE: %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x\n",(&j)[1],(&j)[2],(&j)[3],(&j)[4],(&j)[5],(&j)[6],(&j)[7],(&j)[8],(&j)[9],(&j)[10],(&j)[11],(&j)[12],(&j)[13],(&j)[14],(&j)[15],(&j)[16],(&j)[17],(&j)[18],(&j)[19],(&j)[20]);
2216     #endif
2217     //fflush(stdout);
2218   }
2219   //printf("TRACE: %x\n",(&i)[-1]);
2220 }
2221
2222 void tlb_debug(u_int cause, u_int addr, u_int iaddr)
2223 {
2224   printf("TLB Exception: instruction=%x addr=%x cause=%x\n",iaddr, addr, cause);
2225 }
2226
2227 void alu_assemble(int i,struct regstat *i_regs)
2228 {
2229   if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
2230     if(rt1[i]) {
2231       signed char s1,s2,t;
2232       t=get_reg(i_regs->regmap,rt1[i]);
2233       if(t>=0) {
2234         s1=get_reg(i_regs->regmap,rs1[i]);
2235         s2=get_reg(i_regs->regmap,rs2[i]);
2236         if(rs1[i]&&rs2[i]) {
2237           assert(s1>=0);
2238           assert(s2>=0);
2239           if(opcode2[i]&2) emit_sub(s1,s2,t);
2240           else emit_add(s1,s2,t);
2241         }
2242         else if(rs1[i]) {
2243           if(s1>=0) emit_mov(s1,t);
2244           else emit_loadreg(rs1[i],t);
2245         }
2246         else if(rs2[i]) {
2247           if(s2>=0) {
2248             if(opcode2[i]&2) emit_neg(s2,t);
2249             else emit_mov(s2,t);
2250           }
2251           else {
2252             emit_loadreg(rs2[i],t);
2253             if(opcode2[i]&2) emit_neg(t,t);
2254           }
2255         }
2256         else emit_zeroreg(t);
2257       }
2258     }
2259   }
2260   if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU
2261     if(rt1[i]) {
2262       signed char s1l,s2l,s1h,s2h,tl,th;
2263       tl=get_reg(i_regs->regmap,rt1[i]);
2264       th=get_reg(i_regs->regmap,rt1[i]|64);
2265       if(tl>=0) {
2266         s1l=get_reg(i_regs->regmap,rs1[i]);
2267         s2l=get_reg(i_regs->regmap,rs2[i]);
2268         s1h=get_reg(i_regs->regmap,rs1[i]|64);
2269         s2h=get_reg(i_regs->regmap,rs2[i]|64);
2270         if(rs1[i]&&rs2[i]) {
2271           assert(s1l>=0);
2272           assert(s2l>=0);
2273           if(opcode2[i]&2) emit_subs(s1l,s2l,tl);
2274           else emit_adds(s1l,s2l,tl);
2275           if(th>=0) {
2276             #ifdef INVERTED_CARRY
2277             if(opcode2[i]&2) {if(s1h!=th) emit_mov(s1h,th);emit_sbb(th,s2h);}
2278             #else
2279             if(opcode2[i]&2) emit_sbc(s1h,s2h,th);
2280             #endif
2281             else emit_add(s1h,s2h,th);
2282           }
2283         }
2284         else if(rs1[i]) {
2285           if(s1l>=0) emit_mov(s1l,tl);
2286           else emit_loadreg(rs1[i],tl);
2287           if(th>=0) {
2288             if(s1h>=0) emit_mov(s1h,th);
2289             else emit_loadreg(rs1[i]|64,th);
2290           }
2291         }
2292         else if(rs2[i]) {
2293           if(s2l>=0) {
2294             if(opcode2[i]&2) emit_negs(s2l,tl);
2295             else emit_mov(s2l,tl);
2296           }
2297           else {
2298             emit_loadreg(rs2[i],tl);
2299             if(opcode2[i]&2) emit_negs(tl,tl);
2300           }
2301           if(th>=0) {
2302             #ifdef INVERTED_CARRY
2303             if(s2h>=0) emit_mov(s2h,th);
2304             else emit_loadreg(rs2[i]|64,th);
2305             if(opcode2[i]&2) {
2306               emit_adcimm(-1,th); // x86 has inverted carry flag
2307               emit_not(th,th);
2308             }
2309             #else
2310             if(opcode2[i]&2) {
2311               if(s2h>=0) emit_rscimm(s2h,0,th);
2312               else {
2313                 emit_loadreg(rs2[i]|64,th);
2314                 emit_rscimm(th,0,th);
2315               }
2316             }else{
2317               if(s2h>=0) emit_mov(s2h,th);
2318               else emit_loadreg(rs2[i]|64,th);
2319             }
2320             #endif
2321           }
2322         }
2323         else {
2324           emit_zeroreg(tl);
2325           if(th>=0) emit_zeroreg(th);
2326         }
2327       }
2328     }
2329   }
2330   if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU
2331     if(rt1[i]) {
2332       signed char s1l,s1h,s2l,s2h,t;
2333       if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1))
2334       {
2335         t=get_reg(i_regs->regmap,rt1[i]);
2336         //assert(t>=0);
2337         if(t>=0) {
2338           s1l=get_reg(i_regs->regmap,rs1[i]);
2339           s1h=get_reg(i_regs->regmap,rs1[i]|64);
2340           s2l=get_reg(i_regs->regmap,rs2[i]);
2341           s2h=get_reg(i_regs->regmap,rs2[i]|64);
2342           if(rs2[i]==0) // rx<r0
2343           {
2344             assert(s1h>=0);
2345             if(opcode2[i]==0x2a) // SLT
2346               emit_shrimm(s1h,31,t);
2347             else // SLTU (unsigned can not be less than zero)
2348               emit_zeroreg(t);
2349           }
2350           else if(rs1[i]==0) // r0<rx
2351           {
2352             assert(s2h>=0);
2353             if(opcode2[i]==0x2a) // SLT
2354               emit_set_gz64_32(s2h,s2l,t);
2355             else // SLTU (set if not zero)
2356               emit_set_nz64_32(s2h,s2l,t);
2357           }
2358           else {
2359             assert(s1l>=0);assert(s1h>=0);
2360             assert(s2l>=0);assert(s2h>=0);
2361             if(opcode2[i]==0x2a) // SLT
2362               emit_set_if_less64_32(s1h,s1l,s2h,s2l,t);
2363             else // SLTU
2364               emit_set_if_carry64_32(s1h,s1l,s2h,s2l,t);
2365           }
2366         }
2367       } else {
2368         t=get_reg(i_regs->regmap,rt1[i]);
2369         //assert(t>=0);
2370         if(t>=0) {
2371           s1l=get_reg(i_regs->regmap,rs1[i]);
2372           s2l=get_reg(i_regs->regmap,rs2[i]);
2373           if(rs2[i]==0) // rx<r0
2374           {
2375             assert(s1l>=0);
2376             if(opcode2[i]==0x2a) // SLT
2377               emit_shrimm(s1l,31,t);
2378             else // SLTU (unsigned can not be less than zero)
2379               emit_zeroreg(t);
2380           }
2381           else if(rs1[i]==0) // r0<rx
2382           {
2383             assert(s2l>=0);
2384             if(opcode2[i]==0x2a) // SLT
2385               emit_set_gz32(s2l,t);
2386             else // SLTU (set if not zero)
2387               emit_set_nz32(s2l,t);
2388           }
2389           else{
2390             assert(s1l>=0);assert(s2l>=0);
2391             if(opcode2[i]==0x2a) // SLT
2392               emit_set_if_less32(s1l,s2l,t);
2393             else // SLTU
2394               emit_set_if_carry32(s1l,s2l,t);
2395           }
2396         }
2397       }
2398     }
2399   }
2400   if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR
2401     if(rt1[i]) {
2402       signed char s1l,s1h,s2l,s2h,th,tl;
2403       tl=get_reg(i_regs->regmap,rt1[i]);
2404       th=get_reg(i_regs->regmap,rt1[i]|64);
2405       if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1)&&th>=0)
2406       {
2407         assert(tl>=0);
2408         if(tl>=0) {
2409           s1l=get_reg(i_regs->regmap,rs1[i]);
2410           s1h=get_reg(i_regs->regmap,rs1[i]|64);
2411           s2l=get_reg(i_regs->regmap,rs2[i]);
2412           s2h=get_reg(i_regs->regmap,rs2[i]|64);
2413           if(rs1[i]&&rs2[i]) {
2414             assert(s1l>=0);assert(s1h>=0);
2415             assert(s2l>=0);assert(s2h>=0);
2416             if(opcode2[i]==0x24) { // AND
2417               emit_and(s1l,s2l,tl);
2418               emit_and(s1h,s2h,th);
2419             } else
2420             if(opcode2[i]==0x25) { // OR
2421               emit_or(s1l,s2l,tl);
2422               emit_or(s1h,s2h,th);
2423             } else
2424             if(opcode2[i]==0x26) { // XOR
2425               emit_xor(s1l,s2l,tl);
2426               emit_xor(s1h,s2h,th);
2427             } else
2428             if(opcode2[i]==0x27) { // NOR
2429               emit_or(s1l,s2l,tl);
2430               emit_or(s1h,s2h,th);
2431               emit_not(tl,tl);
2432               emit_not(th,th);
2433             }
2434           }
2435           else
2436           {
2437             if(opcode2[i]==0x24) { // AND
2438               emit_zeroreg(tl);
2439               emit_zeroreg(th);
2440             } else
2441             if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR
2442               if(rs1[i]){
2443                 if(s1l>=0) emit_mov(s1l,tl);
2444                 else emit_loadreg(rs1[i],tl);
2445                 if(s1h>=0) emit_mov(s1h,th);
2446                 else emit_loadreg(rs1[i]|64,th);
2447               }
2448               else
2449               if(rs2[i]){
2450                 if(s2l>=0) emit_mov(s2l,tl);
2451                 else emit_loadreg(rs2[i],tl);
2452                 if(s2h>=0) emit_mov(s2h,th);
2453                 else emit_loadreg(rs2[i]|64,th);
2454               }
2455               else{
2456                 emit_zeroreg(tl);
2457                 emit_zeroreg(th);
2458               }
2459             } else
2460             if(opcode2[i]==0x27) { // NOR
2461               if(rs1[i]){
2462                 if(s1l>=0) emit_not(s1l,tl);
2463                 else{
2464                   emit_loadreg(rs1[i],tl);
2465                   emit_not(tl,tl);
2466                 }
2467                 if(s1h>=0) emit_not(s1h,th);
2468                 else{
2469                   emit_loadreg(rs1[i]|64,th);
2470                   emit_not(th,th);
2471                 }
2472               }
2473               else
2474               if(rs2[i]){
2475                 if(s2l>=0) emit_not(s2l,tl);
2476                 else{
2477                   emit_loadreg(rs2[i],tl);
2478                   emit_not(tl,tl);
2479                 }
2480                 if(s2h>=0) emit_not(s2h,th);
2481                 else{
2482                   emit_loadreg(rs2[i]|64,th);
2483                   emit_not(th,th);
2484                 }
2485               }
2486               else {
2487                 emit_movimm(-1,tl);
2488                 emit_movimm(-1,th);
2489               }
2490             }
2491           }
2492         }
2493       }
2494       else
2495       {
2496         // 32 bit
2497         if(tl>=0) {
2498           s1l=get_reg(i_regs->regmap,rs1[i]);
2499           s2l=get_reg(i_regs->regmap,rs2[i]);
2500           if(rs1[i]&&rs2[i]) {
2501             assert(s1l>=0);
2502             assert(s2l>=0);
2503             if(opcode2[i]==0x24) { // AND
2504               emit_and(s1l,s2l,tl);
2505             } else
2506             if(opcode2[i]==0x25) { // OR
2507               emit_or(s1l,s2l,tl);
2508             } else
2509             if(opcode2[i]==0x26) { // XOR
2510               emit_xor(s1l,s2l,tl);
2511             } else
2512             if(opcode2[i]==0x27) { // NOR
2513               emit_or(s1l,s2l,tl);
2514               emit_not(tl,tl);
2515             }
2516           }
2517           else
2518           {
2519             if(opcode2[i]==0x24) { // AND
2520               emit_zeroreg(tl);
2521             } else
2522             if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR
2523               if(rs1[i]){
2524                 if(s1l>=0) emit_mov(s1l,tl);
2525                 else emit_loadreg(rs1[i],tl); // CHECK: regmap_entry?
2526               }
2527               else
2528               if(rs2[i]){
2529                 if(s2l>=0) emit_mov(s2l,tl);
2530                 else emit_loadreg(rs2[i],tl); // CHECK: regmap_entry?
2531               }
2532               else emit_zeroreg(tl);
2533             } else
2534             if(opcode2[i]==0x27) { // NOR
2535               if(rs1[i]){
2536                 if(s1l>=0) emit_not(s1l,tl);
2537                 else {
2538                   emit_loadreg(rs1[i],tl);
2539                   emit_not(tl,tl);
2540                 }
2541               }
2542               else
2543               if(rs2[i]){
2544                 if(s2l>=0) emit_not(s2l,tl);
2545                 else {
2546                   emit_loadreg(rs2[i],tl);
2547                   emit_not(tl,tl);
2548                 }
2549               }
2550               else emit_movimm(-1,tl);
2551             }
2552           }
2553         }
2554       }
2555     }
2556   }
2557 }
2558
2559 void imm16_assemble(int i,struct regstat *i_regs)
2560 {
2561   if (opcode[i]==0x0f) { // LUI
2562     if(rt1[i]) {
2563       signed char t;
2564       t=get_reg(i_regs->regmap,rt1[i]);
2565       //assert(t>=0);
2566       if(t>=0) {
2567         if(!((i_regs->isconst>>t)&1))
2568           emit_movimm(imm[i]<<16,t);
2569       }
2570     }
2571   }
2572   if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU
2573     if(rt1[i]) {
2574       signed char s,t;
2575       t=get_reg(i_regs->regmap,rt1[i]);
2576       s=get_reg(i_regs->regmap,rs1[i]);
2577       if(rs1[i]) {
2578         //assert(t>=0);
2579         //assert(s>=0);
2580         if(t>=0) {
2581           if(!((i_regs->isconst>>t)&1)) {
2582             if(s<0) {
2583               if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2584               emit_addimm(t,imm[i],t);
2585             }else{
2586               if(!((i_regs->wasconst>>s)&1))
2587                 emit_addimm(s,imm[i],t);
2588               else
2589                 emit_movimm(constmap[i][s]+imm[i],t);
2590             }
2591           }
2592         }
2593       } else {
2594         if(t>=0) {
2595           if(!((i_regs->isconst>>t)&1))
2596             emit_movimm(imm[i],t);
2597         }
2598       }
2599     }
2600   }
2601   if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU
2602     if(rt1[i]) {
2603       signed char sh,sl,th,tl;
2604       th=get_reg(i_regs->regmap,rt1[i]|64);
2605       tl=get_reg(i_regs->regmap,rt1[i]);
2606       sh=get_reg(i_regs->regmap,rs1[i]|64);
2607       sl=get_reg(i_regs->regmap,rs1[i]);
2608       if(tl>=0) {
2609         if(rs1[i]) {
2610           assert(sh>=0);
2611           assert(sl>=0);
2612           if(th>=0) {
2613             emit_addimm64_32(sh,sl,imm[i],th,tl);
2614           }
2615           else {
2616             emit_addimm(sl,imm[i],tl);
2617           }
2618         } else {
2619           emit_movimm(imm[i],tl);
2620           if(th>=0) emit_movimm(((signed int)imm[i])>>31,th);
2621         }
2622       }
2623     }
2624   }
2625   else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU
2626     if(rt1[i]) {
2627       //assert(rs1[i]!=0); // r0 might be valid, but it's probably a bug
2628       signed char sh,sl,t;
2629       t=get_reg(i_regs->regmap,rt1[i]);
2630       sh=get_reg(i_regs->regmap,rs1[i]|64);
2631       sl=get_reg(i_regs->regmap,rs1[i]);
2632       //assert(t>=0);
2633       if(t>=0) {
2634         if(rs1[i]>0) {
2635           if(sh<0) assert((i_regs->was32>>rs1[i])&1);
2636           if(sh<0||((i_regs->was32>>rs1[i])&1)) {
2637             if(opcode[i]==0x0a) { // SLTI
2638               if(sl<0) {
2639                 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2640                 emit_slti32(t,imm[i],t);
2641               }else{
2642                 emit_slti32(sl,imm[i],t);
2643               }
2644             }
2645             else { // SLTIU
2646               if(sl<0) {
2647                 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2648                 emit_sltiu32(t,imm[i],t);
2649               }else{
2650                 emit_sltiu32(sl,imm[i],t);
2651               }
2652             }
2653           }else{ // 64-bit
2654             assert(sl>=0);
2655             if(opcode[i]==0x0a) // SLTI
2656               emit_slti64_32(sh,sl,imm[i],t);
2657             else // SLTIU
2658               emit_sltiu64_32(sh,sl,imm[i],t);
2659           }
2660         }else{
2661           // SLTI(U) with r0 is just stupid,
2662           // nonetheless examples can be found
2663           if(opcode[i]==0x0a) // SLTI
2664             if(0<imm[i]) emit_movimm(1,t);
2665             else emit_zeroreg(t);
2666           else // SLTIU
2667           {
2668             if(imm[i]) emit_movimm(1,t);
2669             else emit_zeroreg(t);
2670           }
2671         }
2672       }
2673     }
2674   }
2675   else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI
2676     if(rt1[i]) {
2677       signed char sh,sl,th,tl;
2678       th=get_reg(i_regs->regmap,rt1[i]|64);
2679       tl=get_reg(i_regs->regmap,rt1[i]);
2680       sh=get_reg(i_regs->regmap,rs1[i]|64);
2681       sl=get_reg(i_regs->regmap,rs1[i]);
2682       if(tl>=0 && !((i_regs->isconst>>tl)&1)) {
2683         if(opcode[i]==0x0c) //ANDI
2684         {
2685           if(rs1[i]) {
2686             if(sl<0) {
2687               if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl);
2688               emit_andimm(tl,imm[i],tl);
2689             }else{
2690               if(!((i_regs->wasconst>>sl)&1))
2691                 emit_andimm(sl,imm[i],tl);
2692               else
2693                 emit_movimm(constmap[i][sl]&imm[i],tl);
2694             }
2695           }
2696           else
2697             emit_zeroreg(tl);
2698           if(th>=0) emit_zeroreg(th);
2699         }
2700         else
2701         {
2702           if(rs1[i]) {
2703             if(sl<0) {
2704               if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl);
2705             }
2706             if(th>=0) {
2707               if(sh<0) {
2708                 emit_loadreg(rs1[i]|64,th);
2709               }else{
2710                 emit_mov(sh,th);
2711               }
2712             }
2713             if(opcode[i]==0x0d) //ORI
2714             if(sl<0) {
2715               emit_orimm(tl,imm[i],tl);
2716             }else{
2717               if(!((i_regs->wasconst>>sl)&1))
2718                 emit_orimm(sl,imm[i],tl);
2719               else
2720                 emit_movimm(constmap[i][sl]|imm[i],tl);
2721             }
2722             if(opcode[i]==0x0e) //XORI
2723             if(sl<0) {
2724               emit_xorimm(tl,imm[i],tl);
2725             }else{
2726               if(!((i_regs->wasconst>>sl)&1))
2727                 emit_xorimm(sl,imm[i],tl);
2728               else
2729                 emit_movimm(constmap[i][sl]^imm[i],tl);
2730             }
2731           }
2732           else {
2733             emit_movimm(imm[i],tl);
2734             if(th>=0) emit_zeroreg(th);
2735           }
2736         }
2737       }
2738     }
2739   }
2740 }
2741
2742 void shiftimm_assemble(int i,struct regstat *i_regs)
2743 {
2744   if(opcode2[i]<=0x3) // SLL/SRL/SRA
2745   {
2746     if(rt1[i]) {
2747       signed char s,t;
2748       t=get_reg(i_regs->regmap,rt1[i]);
2749       s=get_reg(i_regs->regmap,rs1[i]);
2750       //assert(t>=0);
2751       if(t>=0&&!((i_regs->isconst>>t)&1)){
2752         if(rs1[i]==0)
2753         {
2754           emit_zeroreg(t);
2755         }
2756         else
2757         {
2758           if(s<0&&i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2759           if(imm[i]) {
2760             if(opcode2[i]==0) // SLL
2761             {
2762               emit_shlimm(s<0?t:s,imm[i],t);
2763             }
2764             if(opcode2[i]==2) // SRL
2765             {
2766               emit_shrimm(s<0?t:s,imm[i],t);
2767             }
2768             if(opcode2[i]==3) // SRA
2769             {
2770               emit_sarimm(s<0?t:s,imm[i],t);
2771             }
2772           }else{
2773             // Shift by zero
2774             if(s>=0 && s!=t) emit_mov(s,t);
2775           }
2776         }
2777       }
2778       //emit_storereg(rt1[i],t); //DEBUG
2779     }
2780   }
2781   if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA
2782   {
2783     if(rt1[i]) {
2784       signed char sh,sl,th,tl;
2785       th=get_reg(i_regs->regmap,rt1[i]|64);
2786       tl=get_reg(i_regs->regmap,rt1[i]);
2787       sh=get_reg(i_regs->regmap,rs1[i]|64);
2788       sl=get_reg(i_regs->regmap,rs1[i]);
2789       if(tl>=0) {
2790         if(rs1[i]==0)
2791         {
2792           emit_zeroreg(tl);
2793           if(th>=0) emit_zeroreg(th);
2794         }
2795         else
2796         {
2797           assert(sl>=0);
2798           assert(sh>=0);
2799           if(imm[i]) {
2800             if(opcode2[i]==0x38) // DSLL
2801             {
2802               if(th>=0) emit_shldimm(sh,sl,imm[i],th);
2803               emit_shlimm(sl,imm[i],tl);
2804             }
2805             if(opcode2[i]==0x3a) // DSRL
2806             {
2807               emit_shrdimm(sl,sh,imm[i],tl);
2808               if(th>=0) emit_shrimm(sh,imm[i],th);
2809             }
2810             if(opcode2[i]==0x3b) // DSRA
2811             {
2812               emit_shrdimm(sl,sh,imm[i],tl);
2813               if(th>=0) emit_sarimm(sh,imm[i],th);
2814             }
2815           }else{
2816             // Shift by zero
2817             if(sl!=tl) emit_mov(sl,tl);
2818             if(th>=0&&sh!=th) emit_mov(sh,th);
2819           }
2820         }
2821       }
2822     }
2823   }
2824   if(opcode2[i]==0x3c) // DSLL32
2825   {
2826     if(rt1[i]) {
2827       signed char sl,tl,th;
2828       tl=get_reg(i_regs->regmap,rt1[i]);
2829       th=get_reg(i_regs->regmap,rt1[i]|64);
2830       sl=get_reg(i_regs->regmap,rs1[i]);
2831       if(th>=0||tl>=0){
2832         assert(tl>=0);
2833         assert(th>=0);
2834         assert(sl>=0);
2835         emit_mov(sl,th);
2836         emit_zeroreg(tl);
2837         if(imm[i]>32)
2838         {
2839           emit_shlimm(th,imm[i]&31,th);
2840         }
2841       }
2842     }
2843   }
2844   if(opcode2[i]==0x3e) // DSRL32
2845   {
2846     if(rt1[i]) {
2847       signed char sh,tl,th;
2848       tl=get_reg(i_regs->regmap,rt1[i]);
2849       th=get_reg(i_regs->regmap,rt1[i]|64);
2850       sh=get_reg(i_regs->regmap,rs1[i]|64);
2851       if(tl>=0){
2852         assert(sh>=0);
2853         emit_mov(sh,tl);
2854         if(th>=0) emit_zeroreg(th);
2855         if(imm[i]>32)
2856         {
2857           emit_shrimm(tl,imm[i]&31,tl);
2858         }
2859       }
2860     }
2861   }
2862   if(opcode2[i]==0x3f) // DSRA32
2863   {
2864     if(rt1[i]) {
2865       signed char sh,tl;
2866       tl=get_reg(i_regs->regmap,rt1[i]);
2867       sh=get_reg(i_regs->regmap,rs1[i]|64);
2868       if(tl>=0){
2869         assert(sh>=0);
2870         emit_mov(sh,tl);
2871         if(imm[i]>32)
2872         {
2873           emit_sarimm(tl,imm[i]&31,tl);
2874         }
2875       }
2876     }
2877   }
2878 }
2879
2880 #ifndef shift_assemble
2881 void shift_assemble(int i,struct regstat *i_regs)
2882 {
2883   printf("Need shift_assemble for this architecture.\n");
2884   exit(1);
2885 }
2886 #endif
2887
2888 void load_assemble(int i,struct regstat *i_regs)
2889 {
2890   int s,th,tl,addr,map=-1;
2891   int offset;
2892   int jaddr=0;
2893   int memtarget=0,c=0;
2894   int fastload_reg_override=0;
2895   u_int hr,reglist=0;
2896   th=get_reg(i_regs->regmap,rt1[i]|64);
2897   tl=get_reg(i_regs->regmap,rt1[i]);
2898   s=get_reg(i_regs->regmap,rs1[i]);
2899   offset=imm[i];
2900   for(hr=0;hr<HOST_REGS;hr++) {
2901     if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
2902   }
2903   if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
2904   if(s>=0) {
2905     c=(i_regs->wasconst>>s)&1;
2906     if (c) {
2907       memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
2908       if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
2909     }
2910   }
2911   //printf("load_assemble: c=%d\n",c);
2912   //if(c) printf("load_assemble: const=%x\n",(int)constmap[i][s]+offset);
2913   // FIXME: Even if the load is a NOP, we should check for pagefaults...
2914 #ifdef PCSX
2915   if(tl<0&&(!c||(((u_int)constmap[i][s]+offset)>>16)==0x1f80)
2916     ||rt1[i]==0) {
2917       // could be FIFO, must perform the read
2918       // ||dummy read
2919       assem_debug("(forced read)\n");
2920       tl=get_reg(i_regs->regmap,-1);
2921       assert(tl>=0);
2922   }
2923 #endif
2924   if(offset||s<0||c) addr=tl;
2925   else addr=s;
2926   //if(tl<0) tl=get_reg(i_regs->regmap,-1);
2927  if(tl>=0) {
2928   //printf("load_assemble: c=%d\n",c);
2929   //if(c) printf("load_assemble: const=%x\n",(int)constmap[i][s]+offset);
2930   assert(tl>=0); // Even if the load is a NOP, we must check for pagefaults and I/O
2931   reglist&=~(1<<tl);
2932   if(th>=0) reglist&=~(1<<th);
2933   if(!using_tlb) {
2934     if(!c) {
2935       #ifdef RAM_OFFSET
2936       map=get_reg(i_regs->regmap,ROREG);
2937       if(map<0) emit_loadreg(ROREG,map=HOST_TEMPREG);
2938       #endif
2939 //#define R29_HACK 1
2940       #ifdef R29_HACK
2941       // Strmnnrmn's speed hack
2942       if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
2943       #endif
2944       {
2945         jaddr=emit_fastpath_cmp_jump(i,addr,&fastload_reg_override);
2946       }
2947     }
2948     else if(ram_offset&&memtarget) {
2949       emit_addimm(addr,ram_offset,HOST_TEMPREG);
2950       fastload_reg_override=HOST_TEMPREG;
2951     }
2952   }else{ // using tlb
2953     int x=0;
2954     if (opcode[i]==0x20||opcode[i]==0x24) x=3; // LB/LBU
2955     if (opcode[i]==0x21||opcode[i]==0x25) x=2; // LH/LHU
2956     map=get_reg(i_regs->regmap,TLREG);
2957     assert(map>=0);
2958     reglist&=~(1<<map);
2959     map=do_tlb_r(addr,tl,map,x,-1,-1,c,constmap[i][s]+offset);
2960     do_tlb_r_branch(map,c,constmap[i][s]+offset,&jaddr);
2961   }
2962   int dummy=(rt1[i]==0)||(tl!=get_reg(i_regs->regmap,rt1[i])); // ignore loads to r0 and unneeded reg
2963   if (opcode[i]==0x20) { // LB
2964     if(!c||memtarget) {
2965       if(!dummy) {
2966         #ifdef HOST_IMM_ADDR32
2967         if(c)
2968           emit_movsbl_tlb((constmap[i][s]+offset)^3,map,tl);
2969         else
2970         #endif
2971         {
2972           //emit_xorimm(addr,3,tl);
2973           //gen_tlb_addr_r(tl,map);
2974           //emit_movsbl_indexed((int)rdram-0x80000000,tl,tl);
2975           int x=0,a=tl;
2976 #ifdef BIG_ENDIAN_MIPS
2977           if(!c) emit_xorimm(addr,3,tl);
2978           else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2979 #else
2980           if(!c) a=addr;
2981 #endif
2982           if(fastload_reg_override) a=fastload_reg_override;
2983
2984           emit_movsbl_indexed_tlb(x,a,map,tl);
2985         }
2986       }
2987       if(jaddr)
2988         add_stub(LOADB_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2989     }
2990     else
2991       inline_readstub(LOADB_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2992   }
2993   if (opcode[i]==0x21) { // LH
2994     if(!c||memtarget) {
2995       if(!dummy) {
2996         #ifdef HOST_IMM_ADDR32
2997         if(c)
2998           emit_movswl_tlb((constmap[i][s]+offset)^2,map,tl);
2999         else
3000         #endif
3001         {
3002           int x=0,a=tl;
3003 #ifdef BIG_ENDIAN_MIPS
3004           if(!c) emit_xorimm(addr,2,tl);
3005           else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
3006 #else
3007           if(!c) a=addr;
3008 #endif
3009           if(fastload_reg_override) a=fastload_reg_override;
3010           //#ifdef
3011           //emit_movswl_indexed_tlb(x,tl,map,tl);
3012           //else
3013           if(map>=0) {
3014             gen_tlb_addr_r(a,map);
3015             emit_movswl_indexed(x,a,tl);
3016           }else{
3017             #if 1 //def RAM_OFFSET
3018             emit_movswl_indexed(x,a,tl);
3019             #else
3020             emit_movswl_indexed((int)rdram-0x80000000+x,a,tl);
3021             #endif
3022           }
3023         }
3024       }
3025       if(jaddr)
3026         add_stub(LOADH_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3027     }
3028     else
3029       inline_readstub(LOADH_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3030   }
3031   if (opcode[i]==0x23) { // LW
3032     if(!c||memtarget) {
3033       if(!dummy) {
3034         int a=addr;
3035         if(fastload_reg_override) a=fastload_reg_override;
3036         //emit_readword_indexed((int)rdram-0x80000000,addr,tl);
3037         #ifdef HOST_IMM_ADDR32
3038         if(c)
3039           emit_readword_tlb(constmap[i][s]+offset,map,tl);
3040         else
3041         #endif
3042         emit_readword_indexed_tlb(0,a,map,tl);
3043       }
3044       if(jaddr)
3045         add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3046     }
3047     else
3048       inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3049   }
3050   if (opcode[i]==0x24) { // LBU
3051     if(!c||memtarget) {
3052       if(!dummy) {
3053         #ifdef HOST_IMM_ADDR32
3054         if(c)
3055           emit_movzbl_tlb((constmap[i][s]+offset)^3,map,tl);
3056         else
3057         #endif
3058         {
3059           //emit_xorimm(addr,3,tl);
3060           //gen_tlb_addr_r(tl,map);
3061           //emit_movzbl_indexed((int)rdram-0x80000000,tl,tl);
3062           int x=0,a=tl;
3063 #ifdef BIG_ENDIAN_MIPS
3064           if(!c) emit_xorimm(addr,3,tl);
3065           else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
3066 #else
3067           if(!c) a=addr;
3068 #endif
3069           if(fastload_reg_override) a=fastload_reg_override;
3070
3071           emit_movzbl_indexed_tlb(x,a,map,tl);
3072         }
3073       }
3074       if(jaddr)
3075         add_stub(LOADBU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3076     }
3077     else
3078       inline_readstub(LOADBU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3079   }
3080   if (opcode[i]==0x25) { // LHU
3081     if(!c||memtarget) {
3082       if(!dummy) {
3083         #ifdef HOST_IMM_ADDR32
3084         if(c)
3085           emit_movzwl_tlb((constmap[i][s]+offset)^2,map,tl);
3086         else
3087         #endif
3088         {
3089           int x=0,a=tl;
3090 #ifdef BIG_ENDIAN_MIPS
3091           if(!c) emit_xorimm(addr,2,tl);
3092           else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
3093 #else
3094           if(!c) a=addr;
3095 #endif
3096           if(fastload_reg_override) a=fastload_reg_override;
3097           //#ifdef
3098           //emit_movzwl_indexed_tlb(x,tl,map,tl);
3099           //#else
3100           if(map>=0) {
3101             gen_tlb_addr_r(a,map);
3102             emit_movzwl_indexed(x,a,tl);
3103           }else{
3104             #if 1 //def RAM_OFFSET
3105             emit_movzwl_indexed(x,a,tl);
3106             #else
3107             emit_movzwl_indexed((int)rdram-0x80000000+x,a,tl);
3108             #endif
3109           }
3110         }
3111       }
3112       if(jaddr)
3113         add_stub(LOADHU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3114     }
3115     else
3116       inline_readstub(LOADHU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3117   }
3118   if (opcode[i]==0x27) { // LWU
3119     assert(th>=0);
3120     if(!c||memtarget) {
3121       if(!dummy) {
3122         int a=addr;
3123         if(fastload_reg_override) a=fastload_reg_override;
3124         //emit_readword_indexed((int)rdram-0x80000000,addr,tl);
3125         #ifdef HOST_IMM_ADDR32
3126         if(c)
3127           emit_readword_tlb(constmap[i][s]+offset,map,tl);
3128         else
3129         #endif
3130         emit_readword_indexed_tlb(0,a,map,tl);
3131       }
3132       if(jaddr)
3133         add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3134     }
3135     else {
3136       inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3137     }
3138     emit_zeroreg(th);
3139   }
3140   if (opcode[i]==0x37) { // LD
3141     if(!c||memtarget) {
3142       if(!dummy) {
3143         int a=addr;
3144         if(fastload_reg_override) a=fastload_reg_override;
3145         //gen_tlb_addr_r(tl,map);
3146         //if(th>=0) emit_readword_indexed((int)rdram-0x80000000,addr,th);
3147         //emit_readword_indexed((int)rdram-0x7FFFFFFC,addr,tl);
3148         #ifdef HOST_IMM_ADDR32
3149         if(c)
3150           emit_readdword_tlb(constmap[i][s]+offset,map,th,tl);
3151         else
3152         #endif
3153         emit_readdword_indexed_tlb(0,a,map,th,tl);
3154       }
3155       if(jaddr)
3156         add_stub(LOADD_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3157     }
3158     else
3159       inline_readstub(LOADD_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3160   }
3161  }
3162   //emit_storereg(rt1[i],tl); // DEBUG
3163   //if(opcode[i]==0x23)
3164   //if(opcode[i]==0x24)
3165   //if(opcode[i]==0x23||opcode[i]==0x24)
3166   /*if(opcode[i]==0x21||opcode[i]==0x23||opcode[i]==0x24)
3167   {
3168     //emit_pusha();
3169     save_regs(0x100f);
3170         emit_readword((int)&last_count,ECX);
3171         #ifdef __i386__
3172         if(get_reg(i_regs->regmap,CCREG)<0)
3173           emit_loadreg(CCREG,HOST_CCREG);
3174         emit_add(HOST_CCREG,ECX,HOST_CCREG);
3175         emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3176         emit_writeword(HOST_CCREG,(int)&Count);
3177         #endif
3178         #ifdef __arm__
3179         if(get_reg(i_regs->regmap,CCREG)<0)
3180           emit_loadreg(CCREG,0);
3181         else
3182           emit_mov(HOST_CCREG,0);
3183         emit_add(0,ECX,0);
3184         emit_addimm(0,2*ccadj[i],0);
3185         emit_writeword(0,(int)&Count);
3186         #endif
3187     emit_call((int)memdebug);
3188     //emit_popa();
3189     restore_regs(0x100f);
3190   }/**/
3191 }
3192
3193 #ifndef loadlr_assemble
3194 void loadlr_assemble(int i,struct regstat *i_regs)
3195 {
3196   printf("Need loadlr_assemble for this architecture.\n");
3197   exit(1);
3198 }
3199 #endif
3200
3201 void store_assemble(int i,struct regstat *i_regs)
3202 {
3203   int s,th,tl,map=-1;
3204   int addr,temp;
3205   int offset;
3206   int jaddr=0,jaddr2,type;
3207   int memtarget=0,c=0;
3208   int agr=AGEN1+(i&1);
3209   int faststore_reg_override=0;
3210   u_int hr,reglist=0;
3211   th=get_reg(i_regs->regmap,rs2[i]|64);
3212   tl=get_reg(i_regs->regmap,rs2[i]);
3213   s=get_reg(i_regs->regmap,rs1[i]);
3214   temp=get_reg(i_regs->regmap,agr);
3215   if(temp<0) temp=get_reg(i_regs->regmap,-1);
3216   offset=imm[i];
3217   if(s>=0) {
3218     c=(i_regs->wasconst>>s)&1;
3219     if(c) {
3220       memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
3221       if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
3222     }
3223   }
3224   assert(tl>=0);
3225   assert(temp>=0);
3226   for(hr=0;hr<HOST_REGS;hr++) {
3227     if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3228   }
3229   if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
3230   if(offset||s<0||c) addr=temp;
3231   else addr=s;
3232   if(!using_tlb) {
3233     if(!c) {
3234       #ifndef PCSX
3235       #ifdef R29_HACK
3236       // Strmnnrmn's speed hack
3237       if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
3238       #endif
3239       emit_cmpimm(addr,RAM_SIZE);
3240       #ifdef DESTRUCTIVE_SHIFT
3241       if(s==addr) emit_mov(s,temp);
3242       #endif
3243       #ifdef R29_HACK
3244       memtarget=1;
3245       if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
3246       #endif
3247       {
3248         jaddr=(int)out;
3249         #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
3250         // Hint to branch predictor that the branch is unlikely to be taken
3251         if(rs1[i]>=28)
3252           emit_jno_unlikely(0);
3253         else
3254         #endif
3255         emit_jno(0);
3256       }
3257       #else
3258         jaddr=emit_fastpath_cmp_jump(i,addr,&faststore_reg_override);
3259       #endif
3260     }
3261     else if(ram_offset&&memtarget) {
3262       emit_addimm(addr,ram_offset,HOST_TEMPREG);
3263       faststore_reg_override=HOST_TEMPREG;
3264     }
3265   }else{ // using tlb
3266     int x=0;
3267     if (opcode[i]==0x28) x=3; // SB
3268     if (opcode[i]==0x29) x=2; // SH
3269     map=get_reg(i_regs->regmap,TLREG);
3270     assert(map>=0);
3271     reglist&=~(1<<map);
3272     map=do_tlb_w(addr,temp,map,x,c,constmap[i][s]+offset);
3273     do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr);
3274   }
3275
3276   if (opcode[i]==0x28) { // SB
3277     if(!c||memtarget) {
3278       int x=0,a=temp;
3279 #ifdef BIG_ENDIAN_MIPS
3280       if(!c) emit_xorimm(addr,3,temp);
3281       else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
3282 #else
3283       if(!c) a=addr;
3284 #endif
3285       if(faststore_reg_override) a=faststore_reg_override;
3286       //gen_tlb_addr_w(temp,map);
3287       //emit_writebyte_indexed(tl,(int)rdram-0x80000000,temp);
3288       emit_writebyte_indexed_tlb(tl,x,a,map,a);
3289     }
3290     type=STOREB_STUB;
3291   }
3292   if (opcode[i]==0x29) { // SH
3293     if(!c||memtarget) {
3294       int x=0,a=temp;
3295 #ifdef BIG_ENDIAN_MIPS
3296       if(!c) emit_xorimm(addr,2,temp);
3297       else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
3298 #else
3299       if(!c) a=addr;
3300 #endif
3301       if(faststore_reg_override) a=faststore_reg_override;
3302       //#ifdef
3303       //emit_writehword_indexed_tlb(tl,x,temp,map,temp);
3304       //#else
3305       if(map>=0) {
3306         gen_tlb_addr_w(a,map);
3307         emit_writehword_indexed(tl,x,a);
3308       }else
3309         //emit_writehword_indexed(tl,(int)rdram-0x80000000+x,a);
3310         emit_writehword_indexed(tl,x,a);
3311     }
3312     type=STOREH_STUB;
3313   }
3314   if (opcode[i]==0x2B) { // SW
3315     if(!c||memtarget) {
3316       int a=addr;
3317       if(faststore_reg_override) a=faststore_reg_override;
3318       //emit_writeword_indexed(tl,(int)rdram-0x80000000,addr);
3319       emit_writeword_indexed_tlb(tl,0,a,map,temp);
3320     }
3321     type=STOREW_STUB;
3322   }
3323   if (opcode[i]==0x3F) { // SD
3324     if(!c||memtarget) {
3325       int a=addr;
3326       if(faststore_reg_override) a=faststore_reg_override;
3327       if(rs2[i]) {
3328         assert(th>=0);
3329         //emit_writeword_indexed(th,(int)rdram-0x80000000,addr);
3330         //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,addr);
3331         emit_writedword_indexed_tlb(th,tl,0,a,map,temp);
3332       }else{
3333         // Store zero
3334         //emit_writeword_indexed(tl,(int)rdram-0x80000000,temp);
3335         //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,temp);
3336         emit_writedword_indexed_tlb(tl,tl,0,a,map,temp);
3337       }
3338     }
3339     type=STORED_STUB;
3340   }
3341 #ifdef PCSX
3342   if(jaddr) {
3343     // PCSX store handlers don't check invcode again
3344     reglist|=1<<addr;
3345     add_stub(type,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3346     jaddr=0;
3347   }
3348 #endif
3349   if(!using_tlb&&!(i_regs->waswritten&(1<<rs1[i]))&&!(new_dynarec_hacks&NDHACK_NO_SMC_CHECK)) {
3350     if(!c||memtarget) {
3351       #ifdef DESTRUCTIVE_SHIFT
3352       // The x86 shift operation is 'destructive'; it overwrites the
3353       // source register, so we need to make a copy first and use that.
3354       addr=temp;
3355       #endif
3356       #if defined(HOST_IMM8)
3357       int ir=get_reg(i_regs->regmap,INVCP);
3358       assert(ir>=0);
3359       emit_cmpmem_indexedsr12_reg(ir,addr,1);
3360       #else
3361       emit_cmpmem_indexedsr12_imm((int)invalid_code,addr,1);
3362       #endif
3363       #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3364       emit_callne(invalidate_addr_reg[addr]);
3365       #else
3366       jaddr2=(int)out;
3367       emit_jne(0);
3368       add_stub(INVCODE_STUB,jaddr2,(int)out,reglist|(1<<HOST_CCREG),addr,0,0,0);
3369       #endif
3370     }
3371   }
3372   u_int addr_val=constmap[i][s]+offset;
3373   if(jaddr) {
3374     add_stub(type,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3375   } else if(c&&!memtarget) {
3376     inline_writestub(type,i,addr_val,i_regs->regmap,rs2[i],ccad