libpcsxcore/new_dynarec/new_dynarec.c

   1 /* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
   2  *   Mupen64plus - new_dynarec.c                                           *
   3  *   Copyright (C) 2009-2011 Ari64                                         *
   4  *                                                                         *
   5  *   This program is free software; you can redistribute it and/or modify  *
   6  *   it under the terms of the GNU General Public License as published by  *
   7  *   the Free Software Foundation; either version 2 of the License, or     *
   8  *   (at your option) any later version.                                   *
   9  *                                                                         *
  10  *   This program is distributed in the hope that it will be useful,       *
  11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  13  *   GNU General Public License for more details.                          *
  14  *                                                                         *
  15  *   You should have received a copy of the GNU General Public License     *
  16  *   along with this program; if not, write to the                         *
  17  *   Free Software Foundation, Inc.,                                       *
  18  *   51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.          *
  19  * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
  20
  21 #include <stdlib.h>
  22 #include <stdint.h> //include for uint64_t
  23 #include <assert.h>
  24 #include <sys/mman.h>
  25
  26 #include "emu_if.h" //emulator interface
  27
  28 //#define DISASM
  29 //#define assem_debug printf
  30 //#define inv_debug printf
  31 #define assem_debug(...)
  32 #define inv_debug(...)
  33
  34 #ifdef __i386__
  35 #include "assem_x86.h"
  36 #endif
  37 #ifdef __x86_64__
  38 #include "assem_x64.h"
  39 #endif
  40 #ifdef __arm__
  41 #include "assem_arm.h"
  42 #endif
  43
  44 #define MAXBLOCK 4096
  45 #define MAX_OUTPUT_BLOCK_SIZE 262144
  46
  47 int cycle_multiplier; // 100 for 1.0
  48 #define CLOCK_ADJUST(x) (((x) * cycle_multiplier + 50) / 100)
  49
  50 struct regstat
  51 {
  52   signed char regmap_entry[HOST_REGS];
  53   signed char regmap[HOST_REGS];
  54   uint64_t was32;
  55   uint64_t is32;
  56   uint64_t wasdirty;
  57   uint64_t dirty;
  58   uint64_t u;
  59   uint64_t uu;
  60   u_int wasconst;
  61   u_int isconst;
  62   u_int waswritten;              // regs that were used as store base before
  63   uint64_t constmap[HOST_REGS];
  64 };
  65
  66 struct ll_entry
  67 {
  68   u_int vaddr;
  69   u_int reg32;
  70   void *addr;
  71   struct ll_entry *next;
  72 };
  73
  74   u_int start;
  75   u_int *source;
  76   u_int pagelimit;
  77   char insn[MAXBLOCK][10];
  78   u_char itype[MAXBLOCK];
  79   u_char opcode[MAXBLOCK];
  80   u_char opcode2[MAXBLOCK];
  81   u_char bt[MAXBLOCK];
  82   u_char rs1[MAXBLOCK];
  83   u_char rs2[MAXBLOCK];
  84   u_char rt1[MAXBLOCK];
  85   u_char rt2[MAXBLOCK];
  86   u_char us1[MAXBLOCK];
  87   u_char us2[MAXBLOCK];
  88   u_char dep1[MAXBLOCK];
  89   u_char dep2[MAXBLOCK];
  90   u_char lt1[MAXBLOCK];
  91   static uint64_t gte_rs[MAXBLOCK]; // gte: 32 data and 32 ctl regs
  92   static uint64_t gte_rt[MAXBLOCK];
  93   static uint64_t gte_unneeded[MAXBLOCK];
  94   static int gte_reads_flags; // gte flag read encountered
  95   static u_int smrv[32]; // speculated MIPS register values
  96   static u_int smrv_strong; // mask or regs that are likely to have correct values
  97   static u_int smrv_weak; // same, but somewhat less likely
  98   static u_int smrv_strong_next; // same, but after current insn executes
  99   static u_int smrv_weak_next;
 100   int imm[MAXBLOCK];
 101   u_int ba[MAXBLOCK];
 102   char likely[MAXBLOCK];
 103   char is_ds[MAXBLOCK];
 104   char ooo[MAXBLOCK];
 105   uint64_t unneeded_reg[MAXBLOCK];
 106   uint64_t unneeded_reg_upper[MAXBLOCK];
 107   uint64_t branch_unneeded_reg[MAXBLOCK];
 108   uint64_t branch_unneeded_reg_upper[MAXBLOCK];
 109   uint64_t p32[MAXBLOCK];
 110   uint64_t pr32[MAXBLOCK];
 111   signed char regmap_pre[MAXBLOCK][HOST_REGS];
 112   signed char regmap[MAXBLOCK][HOST_REGS];
 113   signed char regmap_entry[MAXBLOCK][HOST_REGS];
 114   uint64_t constmap[MAXBLOCK][HOST_REGS];
 115   struct regstat regs[MAXBLOCK];
 116   struct regstat branch_regs[MAXBLOCK];
 117   signed char minimum_free_regs[MAXBLOCK];
 118   u_int needed_reg[MAXBLOCK];
 119   uint64_t requires_32bit[MAXBLOCK];
 120   u_int wont_dirty[MAXBLOCK];
 121   u_int will_dirty[MAXBLOCK];
 122   int ccadj[MAXBLOCK];
 123   int slen;
 124   u_int instr_addr[MAXBLOCK];
 125   u_int link_addr[MAXBLOCK][3];
 126   int linkcount;
 127   u_int stubs[MAXBLOCK*3][8];
 128   int stubcount;
 129   u_int literals[1024][2];
 130   int literalcount;
 131   int is_delayslot;
 132   int cop1_usable;
 133   u_char *out;
 134   struct ll_entry *jump_in[4096];
 135   struct ll_entry *jump_out[4096];
 136   struct ll_entry *jump_dirty[4096];
 137   u_int hash_table[65536][4]  __attribute__((aligned(16)));
 138   char shadow[1048576]  __attribute__((aligned(16)));
 139   void *copy;
 140   int expirep;
 141 #ifndef PCSX
 142   u_int using_tlb;
 143 #else
 144   static const u_int using_tlb=0;
 145 #endif
 146   int new_dynarec_did_compile;
 147   u_int stop_after_jal;
 148   extern u_char restore_candidate[512];
 149   extern int cycle_count;
 150
 151   /* registers that may be allocated */
 152   /* 1-31 gpr */
 153 #define HIREG 32 // hi
 154 #define LOREG 33 // lo
 155 #define FSREG 34 // FPU status (FCSR)
 156 #define CSREG 35 // Coprocessor status
 157 #define CCREG 36 // Cycle count
 158 #define INVCP 37 // Pointer to invalid_code
 159 #define MMREG 38 // Pointer to memory_map
 160 #define ROREG 39 // ram offset (if rdram!=0x80000000)
 161 #define TEMPREG 40
 162 #define FTEMP 40 // FPU temporary register
 163 #define PTEMP 41 // Prefetch temporary register
 164 #define TLREG 42 // TLB mapping offset
 165 #define RHASH 43 // Return address hash
 166 #define RHTBL 44 // Return address hash table address
 167 #define RTEMP 45 // JR/JALR address register
 168 #define MAXREG 45
 169 #define AGEN1 46 // Address generation temporary register
 170 #define AGEN2 47 // Address generation temporary register
 171 #define MGEN1 48 // Maptable address generation temporary register
 172 #define MGEN2 49 // Maptable address generation temporary register
 173 #define BTREG 50 // Branch target temporary register
 174
 175   /* instruction types */
 176 #define NOP 0     // No operation
 177 #define LOAD 1    // Load
 178 #define STORE 2   // Store
 179 #define LOADLR 3  // Unaligned load
 180 #define STORELR 4 // Unaligned store
 181 #define MOV 5     // Move
 182 #define ALU 6     // Arithmetic/logic
 183 #define MULTDIV 7 // Multiply/divide
 184 #define SHIFT 8   // Shift by register
 185 #define SHIFTIMM 9// Shift by immediate
 186 #define IMM16 10  // 16-bit immediate
 187 #define RJUMP 11  // Unconditional jump to register
 188 #define UJUMP 12  // Unconditional jump
 189 #define CJUMP 13  // Conditional branch (BEQ/BNE/BGTZ/BLEZ)
 190 #define SJUMP 14  // Conditional branch (regimm format)
 191 #define COP0 15   // Coprocessor 0
 192 #define COP1 16   // Coprocessor 1
 193 #define C1LS 17   // Coprocessor 1 load/store
 194 #define FJUMP 18  // Conditional branch (floating point)
 195 #define FLOAT 19  // Floating point unit
 196 #define FCONV 20  // Convert integer to float
 197 #define FCOMP 21  // Floating point compare (sets FSREG)
 198 #define SYSCALL 22// SYSCALL
 199 #define OTHER 23  // Other
 200 #define SPAN 24   // Branch/delay slot spans 2 pages
 201 #define NI 25     // Not implemented
 202 #define HLECALL 26// PCSX fake opcodes for HLE
 203 #define COP2 27   // Coprocessor 2 move
 204 #define C2LS 28   // Coprocessor 2 load/store
 205 #define C2OP 29   // Coprocessor 2 operation
 206 #define INTCALL 30// Call interpreter to handle rare corner cases
 207
 208   /* stubs */
 209 #define CC_STUB 1
 210 #define FP_STUB 2
 211 #define LOADB_STUB 3
 212 #define LOADH_STUB 4
 213 #define LOADW_STUB 5
 214 #define LOADD_STUB 6
 215 #define LOADBU_STUB 7
 216 #define LOADHU_STUB 8
 217 #define STOREB_STUB 9
 218 #define STOREH_STUB 10
 219 #define STOREW_STUB 11
 220 #define STORED_STUB 12
 221 #define STORELR_STUB 13
 222 #define INVCODE_STUB 14
 223
 224   /* branch codes */
 225 #define TAKEN 1
 226 #define NOTTAKEN 2
 227 #define NULLDS 3
 228
 229 // asm linkage
 230 int new_recompile_block(int addr);
 231 void *get_addr_ht(u_int vaddr);
 232 void invalidate_block(u_int block);
 233 void invalidate_addr(u_int addr);
 234 void remove_hash(int vaddr);
 235 void jump_vaddr();
 236 void dyna_linker();
 237 void dyna_linker_ds();
 238 void verify_code();
 239 void verify_code_vm();
 240 void verify_code_ds();
 241 void cc_interrupt();
 242 void fp_exception();
 243 void fp_exception_ds();
 244 void jump_syscall();
 245 void jump_syscall_hle();
 246 void jump_eret();
 247 void jump_hlecall();
 248 void jump_intcall();
 249 void new_dyna_leave();
 250
 251 // TLB
 252 void TLBWI_new();
 253 void TLBWR_new();
 254 void read_nomem_new();
 255 void read_nomemb_new();
 256 void read_nomemh_new();
 257 void read_nomemd_new();
 258 void write_nomem_new();
 259 void write_nomemb_new();
 260 void write_nomemh_new();
 261 void write_nomemd_new();
 262 void write_rdram_new();
 263 void write_rdramb_new();
 264 void write_rdramh_new();
 265 void write_rdramd_new();
 266 extern u_int memory_map[1048576];
 267
 268 // Needed by assembler
 269 void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32);
 270 void wb_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty);
 271 void wb_needed_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr);
 272 void load_all_regs(signed char i_regmap[]);
 273 void load_needed_regs(signed char i_regmap[],signed char next_regmap[]);
 274 void load_regs_entry(int t);
 275 void load_all_consts(signed char regmap[],int is32,u_int dirty,int i);
 276
 277 int tracedebug=0;
 278
 279 //#define DEBUG_CYCLE_COUNT 1
 280
 281 static void tlb_hacks()
 282 {
 283 #ifndef DISABLE_TLB
 284   // Goldeneye hack
 285   if (strncmp((char *) ROM_HEADER->nom, "GOLDENEYE",9) == 0)
 286   {
 287     u_int addr;
 288     int n;
 289     switch (ROM_HEADER->Country_code&0xFF)
 290     {
 291       case 0x45: // U
 292         addr=0x34b30;
 293         break;
 294       case 0x4A: // J
 295         addr=0x34b70;
 296         break;
 297       case 0x50: // E
 298         addr=0x329f0;
 299         break;
 300       default:
 301         // Unknown country code
 302         addr=0;
 303         break;
 304     }
 305     u_int rom_addr=(u_int)rom;
 306     #ifdef ROM_COPY
 307     // Since memory_map is 32-bit, on 64-bit systems the rom needs to be
 308     // in the lower 4G of memory to use this hack.  Copy it if necessary.
 309     if((void *)rom>(void *)0xffffffff) {
 310       munmap(ROM_COPY, 67108864);
 311       if(mmap(ROM_COPY, 12582912,
 312               PROT_READ | PROT_WRITE,
 313               MAP_FIXED | MAP_PRIVATE | MAP_ANONYMOUS,
 314               -1, 0) <= 0) {printf("mmap() failed\n");}
 315       memcpy(ROM_COPY,rom,12582912);
 316       rom_addr=(u_int)ROM_COPY;
 317     }
 318     #endif
 319     if(addr) {
 320       for(n=0x7F000;n<0x80000;n++) {
 321         memory_map[n]=(((u_int)(rom_addr+addr-0x7F000000))>>2)|0x40000000;
 322       }
 323     }
 324   }
 325 #endif
 326 }
 327
 328 static u_int get_page(u_int vaddr)
 329 {
 330 #ifndef PCSX
 331   u_int page=(vaddr^0x80000000)>>12;
 332 #else
 333   u_int page=vaddr&~0xe0000000;
 334   if (page < 0x1000000)
 335     page &= ~0x0e00000; // RAM mirrors
 336   page>>=12;
 337 #endif
 338 #ifndef DISABLE_TLB
 339   if(page>262143&&tlb_LUT_r[vaddr>>12]) page=(tlb_LUT_r[vaddr>>12]^0x80000000)>>12;
 340 #endif
 341   if(page>2048) page=2048+(page&2047);
 342   return page;
 343 }
 344
 345 static u_int get_vpage(u_int vaddr)
 346 {
 347   u_int vpage=(vaddr^0x80000000)>>12;
 348 #ifndef DISABLE_TLB
 349   if(vpage>262143&&tlb_LUT_r[vaddr>>12]) vpage&=2047; // jump_dirty uses a hash of the virtual address instead
 350 #endif
 351   if(vpage>2048) vpage=2048+(vpage&2047);
 352   return vpage;
 353 }
 354
 355 // Get address from virtual address
 356 // This is called from the recompiled JR/JALR instructions
 357 void *get_addr(u_int vaddr)
 358 {
 359   u_int page=get_page(vaddr);
 360   u_int vpage=get_vpage(vaddr);
 361   struct ll_entry *head;
 362   //printf("TRACE: count=%d next=%d (get_addr %x,page %d)\n",Count,next_interupt,vaddr,page);
 363   head=jump_in[page];
 364   while(head!=NULL) {
 365     if(head->vaddr==vaddr&&head->reg32==0) {
 366   //printf("TRACE: count=%d next=%d (get_addr match %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
 367       int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
 368       ht_bin[3]=ht_bin[1];
 369       ht_bin[2]=ht_bin[0];
 370       ht_bin[1]=(int)head->addr;
 371       ht_bin[0]=vaddr;
 372       return head->addr;
 373     }
 374     head=head->next;
 375   }
 376   head=jump_dirty[vpage];
 377   while(head!=NULL) {
 378     if(head->vaddr==vaddr&&head->reg32==0) {
 379       //printf("TRACE: count=%d next=%d (get_addr match dirty %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
 380       // Don't restore blocks which are about to expire from the cache
 381       if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
 382       if(verify_dirty(head->addr)) {
 383         //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]);
 384         invalid_code[vaddr>>12]=0;
 385         inv_code_start=inv_code_end=~0;
 386 #ifndef DISABLE_TLB
 387         memory_map[vaddr>>12]|=0x40000000;
 388 #endif
 389         if(vpage<2048) {
 390 #ifndef DISABLE_TLB
 391           if(tlb_LUT_r[vaddr>>12]) {
 392             invalid_code[tlb_LUT_r[vaddr>>12]>>12]=0;
 393             memory_map[tlb_LUT_r[vaddr>>12]>>12]|=0x40000000;
 394           }
 395 #endif
 396           restore_candidate[vpage>>3]|=1<<(vpage&7);
 397         }
 398         else restore_candidate[page>>3]|=1<<(page&7);
 399         int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
 400         if(ht_bin[0]==vaddr) {
 401           ht_bin[1]=(int)head->addr; // Replace existing entry
 402         }
 403         else
 404         {
 405           ht_bin[3]=ht_bin[1];
 406           ht_bin[2]=ht_bin[0];
 407           ht_bin[1]=(int)head->addr;
 408           ht_bin[0]=vaddr;
 409         }
 410         return head->addr;
 411       }
 412     }
 413     head=head->next;
 414   }
 415   //printf("TRACE: count=%d next=%d (get_addr no-match %x)\n",Count,next_interupt,vaddr);
 416   int r=new_recompile_block(vaddr);
 417   if(r==0) return get_addr(vaddr);
 418   // Execute in unmapped page, generate pagefault execption
 419   Status|=2;
 420   Cause=(vaddr<<31)|0x8;
 421   EPC=(vaddr&1)?vaddr-5:vaddr;
 422   BadVAddr=(vaddr&~1);
 423   Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0);
 424   EntryHi=BadVAddr&0xFFFFE000;
 425   return get_addr_ht(0x80000000);
 426 }
 427 // Look up address in hash table first
 428 void *get_addr_ht(u_int vaddr)
 429 {
 430   //printf("TRACE: count=%d next=%d (get_addr_ht %x)\n",Count,next_interupt,vaddr);
 431   int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
 432   if(ht_bin[0]==vaddr) return (void *)ht_bin[1];
 433   if(ht_bin[2]==vaddr) return (void *)ht_bin[3];
 434   return get_addr(vaddr);
 435 }
 436
 437 void *get_addr_32(u_int vaddr,u_int flags)
 438 {
 439 #ifdef FORCE32
 440   return get_addr(vaddr);
 441 #else
 442   //printf("TRACE: count=%d next=%d (get_addr_32 %x,flags %x)\n",Count,next_interupt,vaddr,flags);
 443   int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
 444   if(ht_bin[0]==vaddr) return (void *)ht_bin[1];
 445   if(ht_bin[2]==vaddr) return (void *)ht_bin[3];
 446   u_int page=get_page(vaddr);
 447   u_int vpage=get_vpage(vaddr);
 448   struct ll_entry *head;
 449   head=jump_in[page];
 450   while(head!=NULL) {
 451     if(head->vaddr==vaddr&&(head->reg32&flags)==0) {
 452       //printf("TRACE: count=%d next=%d (get_addr_32 match %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
 453       if(head->reg32==0) {
 454         int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
 455         if(ht_bin[0]==-1) {
 456           ht_bin[1]=(int)head->addr;
 457           ht_bin[0]=vaddr;
 458         }else if(ht_bin[2]==-1) {
 459           ht_bin[3]=(int)head->addr;
 460           ht_bin[2]=vaddr;
 461         }
 462         //ht_bin[3]=ht_bin[1];
 463         //ht_bin[2]=ht_bin[0];
 464         //ht_bin[1]=(int)head->addr;
 465         //ht_bin[0]=vaddr;
 466       }
 467       return head->addr;
 468     }
 469     head=head->next;
 470   }
 471   head=jump_dirty[vpage];
 472   while(head!=NULL) {
 473     if(head->vaddr==vaddr&&(head->reg32&flags)==0) {
 474       //printf("TRACE: count=%d next=%d (get_addr_32 match dirty %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
 475       // Don't restore blocks which are about to expire from the cache
 476       if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
 477       if(verify_dirty(head->addr)) {
 478         //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]);
 479         invalid_code[vaddr>>12]=0;
 480         inv_code_start=inv_code_end=~0;
 481         memory_map[vaddr>>12]|=0x40000000;
 482         if(vpage<2048) {
 483 #ifndef DISABLE_TLB
 484           if(tlb_LUT_r[vaddr>>12]) {
 485             invalid_code[tlb_LUT_r[vaddr>>12]>>12]=0;
 486             memory_map[tlb_LUT_r[vaddr>>12]>>12]|=0x40000000;
 487           }
 488 #endif
 489           restore_candidate[vpage>>3]|=1<<(vpage&7);
 490         }
 491         else restore_candidate[page>>3]|=1<<(page&7);
 492         if(head->reg32==0) {
 493           int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
 494           if(ht_bin[0]==-1) {
 495             ht_bin[1]=(int)head->addr;
 496             ht_bin[0]=vaddr;
 497           }else if(ht_bin[2]==-1) {
 498             ht_bin[3]=(int)head->addr;
 499             ht_bin[2]=vaddr;
 500           }
 501           //ht_bin[3]=ht_bin[1];
 502           //ht_bin[2]=ht_bin[0];
 503           //ht_bin[1]=(int)head->addr;
 504           //ht_bin[0]=vaddr;
 505         }
 506         return head->addr;
 507       }
 508     }
 509     head=head->next;
 510   }
 511   //printf("TRACE: count=%d next=%d (get_addr_32 no-match %x,flags %x)\n",Count,next_interupt,vaddr,flags);
 512   int r=new_recompile_block(vaddr);
 513   if(r==0) return get_addr(vaddr);
 514   // Execute in unmapped page, generate pagefault execption
 515   Status|=2;
 516   Cause=(vaddr<<31)|0x8;
 517   EPC=(vaddr&1)?vaddr-5:vaddr;
 518   BadVAddr=(vaddr&~1);
 519   Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0);
 520   EntryHi=BadVAddr&0xFFFFE000;
 521   return get_addr_ht(0x80000000);
 522 #endif
 523 }
 524
 525 void clear_all_regs(signed char regmap[])
 526 {
 527   int hr;
 528   for (hr=0;hr<HOST_REGS;hr++) regmap[hr]=-1;
 529 }
 530
 531 signed char get_reg(signed char regmap[],int r)
 532 {
 533   int hr;
 534   for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&&regmap[hr]==r) return hr;
 535   return -1;
 536 }
 537
 538 // Find a register that is available for two consecutive cycles
 539 signed char get_reg2(signed char regmap1[],signed char regmap2[],int r)
 540 {
 541   int hr;
 542   for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&&regmap1[hr]==r&&regmap2[hr]==r) return hr;
 543   return -1;
 544 }
 545
 546 int count_free_regs(signed char regmap[])
 547 {
 548   int count=0;
 549   int hr;
 550   for(hr=0;hr<HOST_REGS;hr++)
 551   {
 552     if(hr!=EXCLUDE_REG) {
 553       if(regmap[hr]<0) count++;
 554     }
 555   }
 556   return count;
 557 }
 558
 559 void dirty_reg(struct regstat *cur,signed char reg)
 560 {
 561   int hr;
 562   if(!reg) return;
 563   for (hr=0;hr<HOST_REGS;hr++) {
 564     if((cur->regmap[hr]&63)==reg) {
 565       cur->dirty|=1<<hr;
 566     }
 567   }
 568 }
 569
 570 // If we dirty the lower half of a 64 bit register which is now being
 571 // sign-extended, we need to dump the upper half.
 572 // Note: Do this only after completion of the instruction, because
 573 // some instructions may need to read the full 64-bit value even if
 574 // overwriting it (eg SLTI, DSRA32).
 575 static void flush_dirty_uppers(struct regstat *cur)
 576 {
 577   int hr,reg;
 578   for (hr=0;hr<HOST_REGS;hr++) {
 579     if((cur->dirty>>hr)&1) {
 580       reg=cur->regmap[hr];
 581       if(reg>=64)
 582         if((cur->is32>>(reg&63))&1) cur->regmap[hr]=-1;
 583     }
 584   }
 585 }
 586
 587 void set_const(struct regstat *cur,signed char reg,uint64_t value)
 588 {
 589   int hr;
 590   if(!reg) return;
 591   for (hr=0;hr<HOST_REGS;hr++) {
 592     if(cur->regmap[hr]==reg) {
 593       cur->isconst|=1<<hr;
 594       cur->constmap[hr]=value;
 595     }
 596     else if((cur->regmap[hr]^64)==reg) {
 597       cur->isconst|=1<<hr;
 598       cur->constmap[hr]=value>>32;
 599     }
 600   }
 601 }
 602
 603 void clear_const(struct regstat *cur,signed char reg)
 604 {
 605   int hr;
 606   if(!reg) return;
 607   for (hr=0;hr<HOST_REGS;hr++) {
 608     if((cur->regmap[hr]&63)==reg) {
 609       cur->isconst&=~(1<<hr);
 610     }
 611   }
 612 }
 613
 614 int is_const(struct regstat *cur,signed char reg)
 615 {
 616   int hr;
 617   if(reg<0) return 0;
 618   if(!reg) return 1;
 619   for (hr=0;hr<HOST_REGS;hr++) {
 620     if((cur->regmap[hr]&63)==reg) {
 621       return (cur->isconst>>hr)&1;
 622     }
 623   }
 624   return 0;
 625 }
 626 uint64_t get_const(struct regstat *cur,signed char reg)
 627 {
 628   int hr;
 629   if(!reg) return 0;
 630   for (hr=0;hr<HOST_REGS;hr++) {
 631     if(cur->regmap[hr]==reg) {
 632       return cur->constmap[hr];
 633     }
 634   }
 635   printf("Unknown constant in r%d\n",reg);
 636   exit(1);
 637 }
 638
 639 // Least soon needed registers
 640 // Look at the next ten instructions and see which registers
 641 // will be used.  Try not to reallocate these.
 642 void lsn(u_char hsn[], int i, int *preferred_reg)
 643 {
 644   int j;
 645   int b=-1;
 646   for(j=0;j<9;j++)
 647   {
 648     if(i+j>=slen) {
 649       j=slen-i-1;
 650       break;
 651     }
 652     if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
 653     {
 654       // Don't go past an unconditonal jump
 655       j++;
 656       break;
 657     }
 658   }
 659   for(;j>=0;j--)
 660   {
 661     if(rs1[i+j]) hsn[rs1[i+j]]=j;
 662     if(rs2[i+j]) hsn[rs2[i+j]]=j;
 663     if(rt1[i+j]) hsn[rt1[i+j]]=j;
 664     if(rt2[i+j]) hsn[rt2[i+j]]=j;
 665     if(itype[i+j]==STORE || itype[i+j]==STORELR) {
 666       // Stores can allocate zero
 667       hsn[rs1[i+j]]=j;
 668       hsn[rs2[i+j]]=j;
 669     }
 670     // On some architectures stores need invc_ptr
 671     #if defined(HOST_IMM8)
 672     if(itype[i+j]==STORE || itype[i+j]==STORELR || (opcode[i+j]&0x3b)==0x39 || (opcode[i+j]&0x3b)==0x3a) {
 673       hsn[INVCP]=j;
 674     }
 675     #endif
 676     if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP))
 677     {
 678       hsn[CCREG]=j;
 679       b=j;
 680     }
 681   }
 682   if(b>=0)
 683   {
 684     if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
 685     {
 686       // Follow first branch
 687       int t=(ba[i+b]-start)>>2;
 688       j=7-b;if(t+j>=slen) j=slen-t-1;
 689       for(;j>=0;j--)
 690       {
 691         if(rs1[t+j]) if(hsn[rs1[t+j]]>j+b+2) hsn[rs1[t+j]]=j+b+2;
 692         if(rs2[t+j]) if(hsn[rs2[t+j]]>j+b+2) hsn[rs2[t+j]]=j+b+2;
 693         //if(rt1[t+j]) if(hsn[rt1[t+j]]>j+b+2) hsn[rt1[t+j]]=j+b+2;
 694         //if(rt2[t+j]) if(hsn[rt2[t+j]]>j+b+2) hsn[rt2[t+j]]=j+b+2;
 695       }
 696     }
 697     // TODO: preferred register based on backward branch
 698   }
 699   // Delay slot should preferably not overwrite branch conditions or cycle count
 700   if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)) {
 701     if(rs1[i-1]) if(hsn[rs1[i-1]]>1) hsn[rs1[i-1]]=1;
 702     if(rs2[i-1]) if(hsn[rs2[i-1]]>1) hsn[rs2[i-1]]=1;
 703     hsn[CCREG]=1;
 704     // ...or hash tables
 705     hsn[RHASH]=1;
 706     hsn[RHTBL]=1;
 707   }
 708   // Coprocessor load/store needs FTEMP, even if not declared
 709   if(itype[i]==C1LS||itype[i]==C2LS) {
 710     hsn[FTEMP]=0;
 711   }
 712   // Load L/R also uses FTEMP as a temporary register
 713   if(itype[i]==LOADLR) {
 714     hsn[FTEMP]=0;
 715   }
 716   // Also SWL/SWR/SDL/SDR
 717   if(opcode[i]==0x2a||opcode[i]==0x2e||opcode[i]==0x2c||opcode[i]==0x2d) {
 718     hsn[FTEMP]=0;
 719   }
 720   // Don't remove the TLB registers either
 721   if(itype[i]==LOAD || itype[i]==LOADLR || itype[i]==STORE || itype[i]==STORELR || itype[i]==C1LS || itype[i]==C2LS) {
 722     hsn[TLREG]=0;
 723   }
 724   // Don't remove the miniht registers
 725   if(itype[i]==UJUMP||itype[i]==RJUMP)
 726   {
 727     hsn[RHASH]=0;
 728     hsn[RHTBL]=0;
 729   }
 730 }
 731
 732 // We only want to allocate registers if we're going to use them again soon
 733 int needed_again(int r, int i)
 734 {
 735   int j;
 736   int b=-1;
 737   int rn=10;
 738
 739   if(i>0&&(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000))
 740   {
 741     if(ba[i-1]<start || ba[i-1]>start+slen*4-4)
 742       return 0; // Don't need any registers if exiting the block
 743   }
 744   for(j=0;j<9;j++)
 745   {
 746     if(i+j>=slen) {
 747       j=slen-i-1;
 748       break;
 749     }
 750     if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
 751     {
 752       // Don't go past an unconditonal jump
 753       j++;
 754       break;
 755     }
 756     if(itype[i+j]==SYSCALL||itype[i+j]==HLECALL||itype[i+j]==INTCALL||((source[i+j]&0xfc00003f)==0x0d))
 757     {
 758       break;
 759     }
 760   }
 761   for(;j>=1;j--)
 762   {
 763     if(rs1[i+j]==r) rn=j;
 764     if(rs2[i+j]==r) rn=j;
 765     if((unneeded_reg[i+j]>>r)&1) rn=10;
 766     if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP))
 767     {
 768       b=j;
 769     }
 770   }
 771   /*
 772   if(b>=0)
 773   {
 774     if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
 775     {
 776       // Follow first branch
 777       int o=rn;
 778       int t=(ba[i+b]-start)>>2;
 779       j=7-b;if(t+j>=slen) j=slen-t-1;
 780       for(;j>=0;j--)
 781       {
 782         if(!((unneeded_reg[t+j]>>r)&1)) {
 783           if(rs1[t+j]==r) if(rn>j+b+2) rn=j+b+2;
 784           if(rs2[t+j]==r) if(rn>j+b+2) rn=j+b+2;
 785         }
 786         else rn=o;
 787       }
 788     }
 789   }*/
 790   if(rn<10) return 1;
 791   return 0;
 792 }
 793
 794 // Try to match register allocations at the end of a loop with those
 795 // at the beginning
 796 int loop_reg(int i, int r, int hr)
 797 {
 798   int j,k;
 799   for(j=0;j<9;j++)
 800   {
 801     if(i+j>=slen) {
 802       j=slen-i-1;
 803       break;
 804     }
 805     if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
 806     {
 807       // Don't go past an unconditonal jump
 808       j++;
 809       break;
 810     }
 811   }
 812   k=0;
 813   if(i>0){
 814     if(itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)
 815       k--;
 816   }
 817   for(;k<j;k++)
 818   {
 819     if(r<64&&((unneeded_reg[i+k]>>r)&1)) return hr;
 820     if(r>64&&((unneeded_reg_upper[i+k]>>r)&1)) return hr;
 821     if(i+k>=0&&(itype[i+k]==UJUMP||itype[i+k]==CJUMP||itype[i+k]==SJUMP||itype[i+k]==FJUMP))
 822     {
 823       if(ba[i+k]>=start && ba[i+k]<(start+i*4))
 824       {
 825         int t=(ba[i+k]-start)>>2;
 826         int reg=get_reg(regs[t].regmap_entry,r);
 827         if(reg>=0) return reg;
 828         //reg=get_reg(regs[t+1].regmap_entry,r);
 829         //if(reg>=0) return reg;
 830       }
 831     }
 832   }
 833   return hr;
 834 }
 835
 836
 837 // Allocate every register, preserving source/target regs
 838 void alloc_all(struct regstat *cur,int i)
 839 {
 840   int hr;
 841
 842   for(hr=0;hr<HOST_REGS;hr++) {
 843     if(hr!=EXCLUDE_REG) {
 844       if(((cur->regmap[hr]&63)!=rs1[i])&&((cur->regmap[hr]&63)!=rs2[i])&&
 845          ((cur->regmap[hr]&63)!=rt1[i])&&((cur->regmap[hr]&63)!=rt2[i]))
 846       {
 847         cur->regmap[hr]=-1;
 848         cur->dirty&=~(1<<hr);
 849       }
 850       // Don't need zeros
 851       if((cur->regmap[hr]&63)==0)
 852       {
 853         cur->regmap[hr]=-1;
 854         cur->dirty&=~(1<<hr);
 855       }
 856     }
 857   }
 858 }
 859
 860 #ifndef FORCE32
 861 void div64(int64_t dividend,int64_t divisor)
 862 {
 863   lo=dividend/divisor;
 864   hi=dividend%divisor;
 865   //printf("TRACE: ddiv %8x%8x %8x%8x\n" ,(int)reg[HIREG],(int)(reg[HIREG]>>32)
 866   //                                     ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
 867 }
 868 void divu64(uint64_t dividend,uint64_t divisor)
 869 {
 870   lo=dividend/divisor;
 871   hi=dividend%divisor;
 872   //printf("TRACE: ddivu %8x%8x %8x%8x\n",(int)reg[HIREG],(int)(reg[HIREG]>>32)
 873   //                                     ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
 874 }
 875
 876 void mult64(uint64_t m1,uint64_t m2)
 877 {
 878    unsigned long long int op1, op2, op3, op4;
 879    unsigned long long int result1, result2, result3, result4;
 880    unsigned long long int temp1, temp2, temp3, temp4;
 881    int sign = 0;
 882
 883    if (m1 < 0)
 884      {
 885     op2 = -m1;
 886     sign = 1 - sign;
 887      }
 888    else op2 = m1;
 889    if (m2 < 0)
 890      {
 891     op4 = -m2;
 892     sign = 1 - sign;
 893      }
 894    else op4 = m2;
 895
 896    op1 = op2 & 0xFFFFFFFF;
 897    op2 = (op2 >> 32) & 0xFFFFFFFF;
 898    op3 = op4 & 0xFFFFFFFF;
 899    op4 = (op4 >> 32) & 0xFFFFFFFF;
 900
 901    temp1 = op1 * op3;
 902    temp2 = (temp1 >> 32) + op1 * op4;
 903    temp3 = op2 * op3;
 904    temp4 = (temp3 >> 32) + op2 * op4;
 905
 906    result1 = temp1 & 0xFFFFFFFF;
 907    result2 = temp2 + (temp3 & 0xFFFFFFFF);
 908    result3 = (result2 >> 32) + temp4;
 909    result4 = (result3 >> 32);
 910
 911    lo = result1 | (result2 << 32);
 912    hi = (result3 & 0xFFFFFFFF) | (result4 << 32);
 913    if (sign)
 914      {
 915     hi = ~hi;
 916     if (!lo) hi++;
 917     else lo = ~lo + 1;
 918      }
 919 }
 920
 921 void multu64(uint64_t m1,uint64_t m2)
 922 {
 923    unsigned long long int op1, op2, op3, op4;
 924    unsigned long long int result1, result2, result3, result4;
 925    unsigned long long int temp1, temp2, temp3, temp4;
 926
 927    op1 = m1 & 0xFFFFFFFF;
 928    op2 = (m1 >> 32) & 0xFFFFFFFF;
 929    op3 = m2 & 0xFFFFFFFF;
 930    op4 = (m2 >> 32) & 0xFFFFFFFF;
 931
 932    temp1 = op1 * op3;
 933    temp2 = (temp1 >> 32) + op1 * op4;
 934    temp3 = op2 * op3;
 935    temp4 = (temp3 >> 32) + op2 * op4;
 936
 937    result1 = temp1 & 0xFFFFFFFF;
 938    result2 = temp2 + (temp3 & 0xFFFFFFFF);
 939    result3 = (result2 >> 32) + temp4;
 940    result4 = (result3 >> 32);
 941
 942    lo = result1 | (result2 << 32);
 943    hi = (result3 & 0xFFFFFFFF) | (result4 << 32);
 944
 945   //printf("TRACE: dmultu %8x%8x %8x%8x\n",(int)reg[HIREG],(int)(reg[HIREG]>>32)
 946   //                                      ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
 947 }
 948
 949 uint64_t ldl_merge(uint64_t original,uint64_t loaded,u_int bits)
 950 {
 951   if(bits) {
 952     original<<=64-bits;
 953     original>>=64-bits;
 954     loaded<<=bits;
 955     original|=loaded;
 956   }
 957   else original=loaded;
 958   return original;
 959 }
 960 uint64_t ldr_merge(uint64_t original,uint64_t loaded,u_int bits)
 961 {
 962   if(bits^56) {
 963     original>>=64-(bits^56);
 964     original<<=64-(bits^56);
 965     loaded>>=bits^56;
 966     original|=loaded;
 967   }
 968   else original=loaded;
 969   return original;
 970 }
 971 #endif
 972
 973 #ifdef __i386__
 974 #include "assem_x86.c"
 975 #endif
 976 #ifdef __x86_64__
 977 #include "assem_x64.c"
 978 #endif
 979 #ifdef __arm__
 980 #include "assem_arm.c"
 981 #endif
 982
 983 // Add virtual address mapping to linked list
 984 void ll_add(struct ll_entry **head,int vaddr,void *addr)
 985 {
 986   struct ll_entry *new_entry;
 987   new_entry=malloc(sizeof(struct ll_entry));
 988   assert(new_entry!=NULL);
 989   new_entry->vaddr=vaddr;
 990   new_entry->reg32=0;
 991   new_entry->addr=addr;
 992   new_entry->next=*head;
 993   *head=new_entry;
 994 }
 995
 996 // Add virtual address mapping for 32-bit compiled block
 997 void ll_add_32(struct ll_entry **head,int vaddr,u_int reg32,void *addr)
 998 {
 999   ll_add(head,vaddr,addr);
1000 #ifndef FORCE32
1001   (*head)->reg32=reg32;
1002 #endif
1003 }
1004
1005 // Check if an address is already compiled
1006 // but don't return addresses which are about to expire from the cache
1007 void *check_addr(u_int vaddr)
1008 {
1009   u_int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
1010   if(ht_bin[0]==vaddr) {
1011     if(((ht_bin[1]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
1012       if(isclean(ht_bin[1])) return (void *)ht_bin[1];
1013   }
1014   if(ht_bin[2]==vaddr) {
1015     if(((ht_bin[3]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
1016       if(isclean(ht_bin[3])) return (void *)ht_bin[3];
1017   }
1018   u_int page=get_page(vaddr);
1019   struct ll_entry *head;
1020   head=jump_in[page];
1021   while(head!=NULL) {
1022     if(head->vaddr==vaddr&&head->reg32==0) {
1023       if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1024         // Update existing entry with current address
1025         if(ht_bin[0]==vaddr) {
1026           ht_bin[1]=(int)head->addr;
1027           return head->addr;
1028         }
1029         if(ht_bin[2]==vaddr) {
1030           ht_bin[3]=(int)head->addr;
1031           return head->addr;
1032         }
1033         // Insert into hash table with low priority.
1034         // Don't evict existing entries, as they are probably
1035         // addresses that are being accessed frequently.
1036         if(ht_bin[0]==-1) {
1037           ht_bin[1]=(int)head->addr;
1038           ht_bin[0]=vaddr;
1039         }else if(ht_bin[2]==-1) {
1040           ht_bin[3]=(int)head->addr;
1041           ht_bin[2]=vaddr;
1042         }
1043         return head->addr;
1044       }
1045     }
1046     head=head->next;
1047   }
1048   return 0;
1049 }
1050
1051 void remove_hash(int vaddr)
1052 {
1053   //printf("remove hash: %x\n",vaddr);
1054   int *ht_bin=hash_table[(((vaddr)>>16)^vaddr)&0xFFFF];
1055   if(ht_bin[2]==vaddr) {
1056     ht_bin[2]=ht_bin[3]=-1;
1057   }
1058   if(ht_bin[0]==vaddr) {
1059     ht_bin[0]=ht_bin[2];
1060     ht_bin[1]=ht_bin[3];
1061     ht_bin[2]=ht_bin[3]=-1;
1062   }
1063 }
1064
1065 void ll_remove_matching_addrs(struct ll_entry **head,int addr,int shift)
1066 {
1067   struct ll_entry *next;
1068   while(*head) {
1069     if(((u_int)((*head)->addr)>>shift)==(addr>>shift) ||
1070        ((u_int)((*head)->addr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift))
1071     {
1072       inv_debug("EXP: Remove pointer to %x (%x)\n",(int)(*head)->addr,(*head)->vaddr);
1073       remove_hash((*head)->vaddr);
1074       next=(*head)->next;
1075       free(*head);
1076       *head=next;
1077     }
1078     else
1079     {
1080       head=&((*head)->next);
1081     }
1082   }
1083 }
1084
1085 // Remove all entries from linked list
1086 void ll_clear(struct ll_entry **head)
1087 {
1088   struct ll_entry *cur;
1089   struct ll_entry *next;
1090   if(cur=*head) {
1091     *head=0;
1092     while(cur) {
1093       next=cur->next;
1094       free(cur);
1095       cur=next;
1096     }
1097   }
1098 }
1099
1100 // Dereference the pointers and remove if it matches
1101 void ll_kill_pointers(struct ll_entry *head,int addr,int shift)
1102 {
1103   while(head) {
1104     int ptr=get_pointer(head->addr);
1105     inv_debug("EXP: Lookup pointer to %x at %x (%x)\n",(int)ptr,(int)head->addr,head->vaddr);
1106     if(((ptr>>shift)==(addr>>shift)) ||
1107        (((ptr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift)))
1108     {
1109       inv_debug("EXP: Kill pointer at %x (%x)\n",(int)head->addr,head->vaddr);
1110       u_int host_addr=(u_int)kill_pointer(head->addr);
1111       #ifdef __arm__
1112         needs_clear_cache[(host_addr-(u_int)BASE_ADDR)>>17]|=1<<(((host_addr-(u_int)BASE_ADDR)>>12)&31);
1113       #endif
1114     }
1115     head=head->next;
1116   }
1117 }
1118
1119 // This is called when we write to a compiled block (see do_invstub)
1120 void invalidate_page(u_int page)
1121 {
1122   struct ll_entry *head;
1123   struct ll_entry *next;
1124   head=jump_in[page];
1125   jump_in[page]=0;
1126   while(head!=NULL) {
1127     inv_debug("INVALIDATE: %x\n",head->vaddr);
1128     remove_hash(head->vaddr);
1129     next=head->next;
1130     free(head);
1131     head=next;
1132   }
1133   head=jump_out[page];
1134   jump_out[page]=0;
1135   while(head!=NULL) {
1136     inv_debug("INVALIDATE: kill pointer to %x (%x)\n",head->vaddr,(int)head->addr);
1137     u_int host_addr=(u_int)kill_pointer(head->addr);
1138     #ifdef __arm__
1139       needs_clear_cache[(host_addr-(u_int)BASE_ADDR)>>17]|=1<<(((host_addr-(u_int)BASE_ADDR)>>12)&31);
1140     #endif
1141     next=head->next;
1142     free(head);
1143     head=next;
1144   }
1145 }
1146
1147 static void invalidate_block_range(u_int block, u_int first, u_int last)
1148 {
1149   u_int page=get_page(block<<12);
1150   //printf("first=%d last=%d\n",first,last);
1151   invalidate_page(page);
1152   assert(first+5>page); // NB: this assumes MAXBLOCK<=4096 (4 pages)
1153   assert(last<page+5);
1154   // Invalidate the adjacent pages if a block crosses a 4K boundary
1155   while(first<page) {
1156     invalidate_page(first);
1157     first++;
1158   }
1159   for(first=page+1;first<last;first++) {
1160     invalidate_page(first);
1161   }
1162   #ifdef __arm__
1163     do_clear_cache();
1164   #endif
1165
1166   // Don't trap writes
1167   invalid_code[block]=1;
1168 #ifndef DISABLE_TLB
1169   // If there is a valid TLB entry for this page, remove write protect
1170   if(tlb_LUT_w[block]) {
1171     assert(tlb_LUT_r[block]==tlb_LUT_w[block]);
1172     // CHECK: Is this right?
1173     memory_map[block]=((tlb_LUT_w[block]&0xFFFFF000)-(block<<12)+(unsigned int)rdram-0x80000000)>>2;
1174     u_int real_block=tlb_LUT_w[block]>>12;
1175     invalid_code[real_block]=1;
1176     if(real_block>=0x80000&&real_block<0x80800) memory_map[real_block]=((u_int)rdram-0x80000000)>>2;
1177   }
1178   else if(block>=0x80000&&block<0x80800) memory_map[block]=((u_int)rdram-0x80000000)>>2;
1179 #endif
1180
1181   #ifdef USE_MINI_HT
1182   memset(mini_ht,-1,sizeof(mini_ht));
1183   #endif
1184 }
1185
1186 void invalidate_block(u_int block)
1187 {
1188   u_int page=get_page(block<<12);
1189   u_int vpage=get_vpage(block<<12);
1190   inv_debug("INVALIDATE: %x (%d)\n",block<<12,page);
1191   //inv_debug("invalid_code[block]=%d\n",invalid_code[block]);
1192   u_int first,last;
1193   first=last=page;
1194   struct ll_entry *head;
1195   head=jump_dirty[vpage];
1196   //printf("page=%d vpage=%d\n",page,vpage);
1197   while(head!=NULL) {
1198     u_int start,end;
1199     if(vpage>2047||(head->vaddr>>12)==block) { // Ignore vaddr hash collision
1200       get_bounds((int)head->addr,&start,&end);
1201       //printf("start: %x end: %x\n",start,end);
1202       if(page<2048&&start>=0x80000000&&end<0x80000000+RAM_SIZE) {
1203         if(((start-(u_int)rdram)>>12)<=page&&((end-1-(u_int)rdram)>>12)>=page) {
1204           if((((start-(u_int)rdram)>>12)&2047)<first) first=((start-(u_int)rdram)>>12)&2047;
1205           if((((end-1-(u_int)rdram)>>12)&2047)>last) last=((end-1-(u_int)rdram)>>12)&2047;
1206         }
1207       }
1208 #ifndef DISABLE_TLB
1209       if(page<2048&&(signed int)start>=(signed int)0xC0000000&&(signed int)end>=(signed int)0xC0000000) {
1210         if(((start+memory_map[start>>12]-(u_int)rdram)>>12)<=page&&((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)>=page) {
1211           if((((start+memory_map[start>>12]-(u_int)rdram)>>12)&2047)<first) first=((start+memory_map[start>>12]-(u_int)rdram)>>12)&2047;
1212           if((((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)&2047)>last) last=((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)&2047;
1213         }
1214       }
1215 #endif
1216     }
1217     head=head->next;
1218   }
1219   invalidate_block_range(block,first,last);
1220 }
1221
1222 void invalidate_addr(u_int addr)
1223 {
1224 #ifdef PCSX
1225   //static int rhits;
1226   // this check is done by the caller
1227   //if (inv_code_start<=addr&&addr<=inv_code_end) { rhits++; return; }
1228   u_int page=get_page(addr);
1229   if(page<2048) { // RAM
1230     struct ll_entry *head;
1231     u_int addr_min=~0, addr_max=0;
1232     int mask=RAM_SIZE-1;
1233     int pg1;
1234     inv_code_start=addr&~0xfff;
1235     inv_code_end=addr|0xfff;
1236     pg1=page;
1237     if (pg1>0) {
1238       // must check previous page too because of spans..
1239       pg1--;
1240       inv_code_start-=0x1000;
1241     }
1242     for(;pg1<=page;pg1++) {
1243       for(head=jump_dirty[pg1];head!=NULL;head=head->next) {
1244         u_int start,end;
1245         get_bounds((int)head->addr,&start,&end);
1246         if((start&mask)<=(addr&mask)&&(addr&mask)<(end&mask)) {
1247           if(start<addr_min) addr_min=start;
1248           if(end>addr_max) addr_max=end;
1249         }
1250         else if(addr<start) {
1251           if(start<inv_code_end)
1252             inv_code_end=start-1;
1253         }
1254         else {
1255           if(end>inv_code_start)
1256             inv_code_start=end;
1257         }
1258       }
1259     }
1260     if (addr_min!=~0) {
1261       inv_debug("INV ADDR: %08x hit %08x-%08x\n", addr, addr_min, addr_max);
1262       inv_code_start=inv_code_end=~0;
1263       invalidate_block_range(addr>>12,(addr_min&mask)>>12,(addr_max&mask)>>12);
1264       return;
1265     }
1266     else {
1267       inv_debug("INV ADDR: %08x miss, inv %08x-%08x, sk %d\n", addr, inv_code_start, inv_code_end, 0);//rhits);
1268     }
1269     //rhits=0;
1270     if(page!=0) // FIXME: don't know what's up with page 0 (Klonoa)
1271       return;
1272   }
1273 #endif
1274   invalidate_block(addr>>12);
1275 }
1276
1277 // This is called when loading a save state.
1278 // Anything could have changed, so invalidate everything.
1279 void invalidate_all_pages()
1280 {
1281   u_int page,n;
1282   for(page=0;page<4096;page++)
1283     invalidate_page(page);
1284   for(page=0;page<1048576;page++)
1285     if(!invalid_code[page]) {
1286       restore_candidate[(page&2047)>>3]|=1<<(page&7);
1287       restore_candidate[((page&2047)>>3)+256]|=1<<(page&7);
1288     }
1289   #ifdef __arm__
1290   __clear_cache((void *)BASE_ADDR,(void *)BASE_ADDR+(1<<TARGET_SIZE_2));
1291   #endif
1292   #ifdef USE_MINI_HT
1293   memset(mini_ht,-1,sizeof(mini_ht));
1294   #endif
1295   #ifndef DISABLE_TLB
1296   // TLB
1297   for(page=0;page<0x100000;page++) {
1298     if(tlb_LUT_r[page]) {
1299       memory_map[page]=((tlb_LUT_r[page]&0xFFFFF000)-(page<<12)+(unsigned int)rdram-0x80000000)>>2;
1300       if(!tlb_LUT_w[page]||!invalid_code[page])
1301         memory_map[page]|=0x40000000; // Write protect
1302     }
1303     else memory_map[page]=-1;
1304     if(page==0x80000) page=0xC0000;
1305   }
1306   tlb_hacks();
1307   #endif
1308 }
1309
1310 // Add an entry to jump_out after making a link
1311 void add_link(u_int vaddr,void *src)
1312 {
1313   u_int page=get_page(vaddr);
1314   inv_debug("add_link: %x -> %x (%d)\n",(int)src,vaddr,page);
1315   int *ptr=(int *)(src+4);
1316   assert((*ptr&0x0fff0000)==0x059f0000);
1317   ll_add(jump_out+page,vaddr,src);
1318   //int ptr=get_pointer(src);
1319   //inv_debug("add_link: Pointer is to %x\n",(int)ptr);
1320 }
1321
1322 // If a code block was found to be unmodified (bit was set in
1323 // restore_candidate) and it remains unmodified (bit is clear
1324 // in invalid_code) then move the entries for that 4K page from
1325 // the dirty list to the clean list.
1326 void clean_blocks(u_int page)
1327 {
1328   struct ll_entry *head;
1329   inv_debug("INV: clean_blocks page=%d\n",page);
1330   head=jump_dirty[page];
1331   while(head!=NULL) {
1332     if(!invalid_code[head->vaddr>>12]) {
1333       // Don't restore blocks which are about to expire from the cache
1334       if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1335         u_int start,end;
1336         if(verify_dirty((int)head->addr)) {
1337           //printf("Possibly Restore %x (%x)\n",head->vaddr, (int)head->addr);
1338           u_int i;
1339           u_int inv=0;
1340           get_bounds((int)head->addr,&start,&end);
1341           if(start-(u_int)rdram<RAM_SIZE) {
1342             for(i=(start-(u_int)rdram+0x80000000)>>12;i<=(end-1-(u_int)rdram+0x80000000)>>12;i++) {
1343               inv|=invalid_code[i];
1344             }
1345           }
1346 #ifndef DISABLE_TLB
1347           if((signed int)head->vaddr>=(signed int)0xC0000000) {
1348             u_int addr = (head->vaddr+(memory_map[head->vaddr>>12]<<2));
1349             //printf("addr=%x start=%x end=%x\n",addr,start,end);
1350             if(addr<start||addr>=end) inv=1;
1351           }
1352 #endif
1353           else if((signed int)head->vaddr>=(signed int)0x80000000+RAM_SIZE) {
1354             inv=1;
1355           }
1356           if(!inv) {
1357             void * clean_addr=(void *)get_clean_addr((int)head->addr);
1358             if((((u_int)clean_addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1359               u_int ppage=page;
1360 #ifndef DISABLE_TLB
1361               if(page<2048&&tlb_LUT_r[head->vaddr>>12]) ppage=(tlb_LUT_r[head->vaddr>>12]^0x80000000)>>12;
1362 #endif
1363               inv_debug("INV: Restored %x (%x/%x)\n",head->vaddr, (int)head->addr, (int)clean_addr);
1364               //printf("page=%x, addr=%x\n",page,head->vaddr);
1365               //assert(head->vaddr>>12==(page|0x80000));
1366               ll_add_32(jump_in+ppage,head->vaddr,head->reg32,clean_addr);
1367               int *ht_bin=hash_table[((head->vaddr>>16)^head->vaddr)&0xFFFF];
1368               if(!head->reg32) {
1369                 if(ht_bin[0]==head->vaddr) {
1370                   ht_bin[1]=(int)clean_addr; // Replace existing entry
1371                 }
1372                 if(ht_bin[2]==head->vaddr) {
1373                   ht_bin[3]=(int)clean_addr; // Replace existing entry
1374                 }
1375               }
1376             }
1377           }
1378         }
1379       }
1380     }
1381     head=head->next;
1382   }
1383 }
1384
1385
1386 void mov_alloc(struct regstat *current,int i)
1387 {
1388   // Note: Don't need to actually alloc the source registers
1389   if((~current->is32>>rs1[i])&1) {
1390     //alloc_reg64(current,i,rs1[i]);
1391     alloc_reg64(current,i,rt1[i]);
1392     current->is32&=~(1LL<<rt1[i]);
1393   } else {
1394     //alloc_reg(current,i,rs1[i]);
1395     alloc_reg(current,i,rt1[i]);
1396     current->is32|=(1LL<<rt1[i]);
1397   }
1398   clear_const(current,rs1[i]);
1399   clear_const(current,rt1[i]);
1400   dirty_reg(current,rt1[i]);
1401 }
1402
1403 void shiftimm_alloc(struct regstat *current,int i)
1404 {
1405   if(opcode2[i]<=0x3) // SLL/SRL/SRA
1406   {
1407     if(rt1[i]) {
1408       if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1409       else lt1[i]=rs1[i];
1410       alloc_reg(current,i,rt1[i]);
1411       current->is32|=1LL<<rt1[i];
1412       dirty_reg(current,rt1[i]);
1413       if(is_const(current,rs1[i])) {
1414         int v=get_const(current,rs1[i]);
1415         if(opcode2[i]==0x00) set_const(current,rt1[i],v<<imm[i]);
1416         if(opcode2[i]==0x02) set_const(current,rt1[i],(u_int)v>>imm[i]);
1417         if(opcode2[i]==0x03) set_const(current,rt1[i],v>>imm[i]);
1418       }
1419       else clear_const(current,rt1[i]);
1420     }
1421   }
1422   else
1423   {
1424     clear_const(current,rs1[i]);
1425     clear_const(current,rt1[i]);
1426   }
1427
1428   if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA
1429   {
1430     if(rt1[i]) {
1431       if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1432       alloc_reg64(current,i,rt1[i]);
1433       current->is32&=~(1LL<<rt1[i]);
1434       dirty_reg(current,rt1[i]);
1435     }
1436   }
1437   if(opcode2[i]==0x3c) // DSLL32
1438   {
1439     if(rt1[i]) {
1440       if(rs1[i]) alloc_reg(current,i,rs1[i]);
1441       alloc_reg64(current,i,rt1[i]);
1442       current->is32&=~(1LL<<rt1[i]);
1443       dirty_reg(current,rt1[i]);
1444     }
1445   }
1446   if(opcode2[i]==0x3e) // DSRL32
1447   {
1448     if(rt1[i]) {
1449       alloc_reg64(current,i,rs1[i]);
1450       if(imm[i]==32) {
1451         alloc_reg64(current,i,rt1[i]);
1452         current->is32&=~(1LL<<rt1[i]);
1453       } else {
1454         alloc_reg(current,i,rt1[i]);
1455         current->is32|=1LL<<rt1[i];
1456       }
1457       dirty_reg(current,rt1[i]);
1458     }
1459   }
1460   if(opcode2[i]==0x3f) // DSRA32
1461   {
1462     if(rt1[i]) {
1463       alloc_reg64(current,i,rs1[i]);
1464       alloc_reg(current,i,rt1[i]);
1465       current->is32|=1LL<<rt1[i];
1466       dirty_reg(current,rt1[i]);
1467     }
1468   }
1469 }
1470
1471 void shift_alloc(struct regstat *current,int i)
1472 {
1473   if(rt1[i]) {
1474     if(opcode2[i]<=0x07) // SLLV/SRLV/SRAV
1475     {
1476       if(rs1[i]) alloc_reg(current,i,rs1[i]);
1477       if(rs2[i]) alloc_reg(current,i,rs2[i]);
1478       alloc_reg(current,i,rt1[i]);
1479       if(rt1[i]==rs2[i]) {
1480         alloc_reg_temp(current,i,-1);
1481         minimum_free_regs[i]=1;
1482       }
1483       current->is32|=1LL<<rt1[i];
1484     } else { // DSLLV/DSRLV/DSRAV
1485       if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1486       if(rs2[i]) alloc_reg(current,i,rs2[i]);
1487       alloc_reg64(current,i,rt1[i]);
1488       current->is32&=~(1LL<<rt1[i]);
1489       if(opcode2[i]==0x16||opcode2[i]==0x17) // DSRLV and DSRAV need a temporary register
1490       {
1491         alloc_reg_temp(current,i,-1);
1492         minimum_free_regs[i]=1;
1493       }
1494     }
1495     clear_const(current,rs1[i]);
1496     clear_const(current,rs2[i]);
1497     clear_const(current,rt1[i]);
1498     dirty_reg(current,rt1[i]);
1499   }
1500 }
1501
1502 void alu_alloc(struct regstat *current,int i)
1503 {
1504   if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
1505     if(rt1[i]) {
1506       if(rs1[i]&&rs2[i]) {
1507         alloc_reg(current,i,rs1[i]);
1508         alloc_reg(current,i,rs2[i]);
1509       }
1510       else {
1511         if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1512         if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]);
1513       }
1514       alloc_reg(current,i,rt1[i]);
1515     }
1516     current->is32|=1LL<<rt1[i];
1517   }
1518   if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU
1519     if(rt1[i]) {
1520       if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1521       {
1522         alloc_reg64(current,i,rs1[i]);
1523         alloc_reg64(current,i,rs2[i]);
1524         alloc_reg(current,i,rt1[i]);
1525       } else {
1526         alloc_reg(current,i,rs1[i]);
1527         alloc_reg(current,i,rs2[i]);
1528         alloc_reg(current,i,rt1[i]);
1529       }
1530     }
1531     current->is32|=1LL<<rt1[i];
1532   }
1533   if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR
1534     if(rt1[i]) {
1535       if(rs1[i]&&rs2[i]) {
1536         alloc_reg(current,i,rs1[i]);
1537         alloc_reg(current,i,rs2[i]);
1538       }
1539       else
1540       {
1541         if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1542         if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]);
1543       }
1544       alloc_reg(current,i,rt1[i]);
1545       if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1546       {
1547         if(!((current->uu>>rt1[i])&1)) {
1548           alloc_reg64(current,i,rt1[i]);
1549         }
1550         if(get_reg(current->regmap,rt1[i]|64)>=0) {
1551           if(rs1[i]&&rs2[i]) {
1552             alloc_reg64(current,i,rs1[i]);
1553             alloc_reg64(current,i,rs2[i]);
1554           }
1555           else
1556           {
1557             // Is is really worth it to keep 64-bit values in registers?
1558             #ifdef NATIVE_64BIT
1559             if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]);
1560             if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg64(current,i,rs2[i]);
1561             #endif
1562           }
1563         }
1564         current->is32&=~(1LL<<rt1[i]);
1565       } else {
1566         current->is32|=1LL<<rt1[i];
1567       }
1568     }
1569   }
1570   if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU
1571     if(rt1[i]) {
1572       if(rs1[i]&&rs2[i]) {
1573         if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1574           alloc_reg64(current,i,rs1[i]);
1575           alloc_reg64(current,i,rs2[i]);
1576           alloc_reg64(current,i,rt1[i]);
1577         } else {
1578           alloc_reg(current,i,rs1[i]);
1579           alloc_reg(current,i,rs2[i]);
1580           alloc_reg(current,i,rt1[i]);
1581         }
1582       }
1583       else {
1584         alloc_reg(current,i,rt1[i]);
1585         if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1586           // DADD used as move, or zeroing
1587           // If we have a 64-bit source, then make the target 64 bits too
1588           if(rs1[i]&&!((current->is32>>rs1[i])&1)) {
1589             if(get_reg(current->regmap,rs1[i])>=0) alloc_reg64(current,i,rs1[i]);
1590             alloc_reg64(current,i,rt1[i]);
1591           } else if(rs2[i]&&!((current->is32>>rs2[i])&1)) {
1592             if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]);
1593             alloc_reg64(current,i,rt1[i]);
1594           }
1595           if(opcode2[i]>=0x2e&&rs2[i]) {
1596             // DSUB used as negation - 64-bit result
1597             // If we have a 32-bit register, extend it to 64 bits
1598             if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]);
1599             alloc_reg64(current,i,rt1[i]);
1600           }
1601         }
1602       }
1603       if(rs1[i]&&rs2[i]) {
1604         current->is32&=~(1LL<<rt1[i]);
1605       } else if(rs1[i]) {
1606         current->is32&=~(1LL<<rt1[i]);
1607         if((current->is32>>rs1[i])&1)
1608           current->is32|=1LL<<rt1[i];
1609       } else if(rs2[i]) {
1610         current->is32&=~(1LL<<rt1[i]);
1611         if((current->is32>>rs2[i])&1)
1612           current->is32|=1LL<<rt1[i];
1613       } else {
1614         current->is32|=1LL<<rt1[i];
1615       }
1616     }
1617   }
1618   clear_const(current,rs1[i]);
1619   clear_const(current,rs2[i]);
1620   clear_const(current,rt1[i]);
1621   dirty_reg(current,rt1[i]);
1622 }
1623
1624 void imm16_alloc(struct regstat *current,int i)
1625 {
1626   if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1627   else lt1[i]=rs1[i];
1628   if(rt1[i]) alloc_reg(current,i,rt1[i]);
1629   if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU
1630     current->is32&=~(1LL<<rt1[i]);
1631     if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1632       // TODO: Could preserve the 32-bit flag if the immediate is zero
1633       alloc_reg64(current,i,rt1[i]);
1634       alloc_reg64(current,i,rs1[i]);
1635     }
1636     clear_const(current,rs1[i]);
1637     clear_const(current,rt1[i]);
1638   }
1639   else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU
1640     if((~current->is32>>rs1[i])&1) alloc_reg64(current,i,rs1[i]);
1641     current->is32|=1LL<<rt1[i];
1642     clear_const(current,rs1[i]);
1643     clear_const(current,rt1[i]);
1644   }
1645   else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI
1646     if(((~current->is32>>rs1[i])&1)&&opcode[i]>0x0c) {
1647       if(rs1[i]!=rt1[i]) {
1648         if(needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]);
1649         alloc_reg64(current,i,rt1[i]);
1650         current->is32&=~(1LL<<rt1[i]);
1651       }
1652     }
1653     else current->is32|=1LL<<rt1[i]; // ANDI clears upper bits
1654     if(is_const(current,rs1[i])) {
1655       int v=get_const(current,rs1[i]);
1656       if(opcode[i]==0x0c) set_const(current,rt1[i],v&imm[i]);
1657       if(opcode[i]==0x0d) set_const(current,rt1[i],v|imm[i]);
1658       if(opcode[i]==0x0e) set_const(current,rt1[i],v^imm[i]);
1659     }
1660     else clear_const(current,rt1[i]);
1661   }
1662   else if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU
1663     if(is_const(current,rs1[i])) {
1664       int v=get_const(current,rs1[i]);
1665       set_const(current,rt1[i],v+imm[i]);
1666     }
1667     else clear_const(current,rt1[i]);
1668     current->is32|=1LL<<rt1[i];
1669   }
1670   else {
1671     set_const(current,rt1[i],((long long)((short)imm[i]))<<16); // LUI
1672     current->is32|=1LL<<rt1[i];
1673   }
1674   dirty_reg(current,rt1[i]);
1675 }
1676
1677 void load_alloc(struct regstat *current,int i)
1678 {
1679   clear_const(current,rt1[i]);
1680   //if(rs1[i]!=rt1[i]&&needed_again(rs1[i],i)) clear_const(current,rs1[i]); // Does this help or hurt?
1681   if(!rs1[i]) current->u&=~1LL; // Allow allocating r0 if it's the source register
1682   if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1683   if(rt1[i]&&!((current->u>>rt1[i])&1)) {
1684     alloc_reg(current,i,rt1[i]);
1685     assert(get_reg(current->regmap,rt1[i])>=0);
1686     if(opcode[i]==0x27||opcode[i]==0x37) // LWU/LD
1687     {
1688       current->is32&=~(1LL<<rt1[i]);
1689       alloc_reg64(current,i,rt1[i]);
1690     }
1691     else if(opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
1692     {
1693       current->is32&=~(1LL<<rt1[i]);
1694       alloc_reg64(current,i,rt1[i]);
1695       alloc_all(current,i);
1696       alloc_reg64(current,i,FTEMP);
1697       minimum_free_regs[i]=HOST_REGS;
1698     }
1699     else current->is32|=1LL<<rt1[i];
1700     dirty_reg(current,rt1[i]);
1701     // If using TLB, need a register for pointer to the mapping table
1702     if(using_tlb) alloc_reg(current,i,TLREG);
1703     // LWL/LWR need a temporary register for the old value
1704     if(opcode[i]==0x22||opcode[i]==0x26)
1705     {
1706       alloc_reg(current,i,FTEMP);
1707       alloc_reg_temp(current,i,-1);
1708       minimum_free_regs[i]=1;
1709     }
1710   }
1711   else
1712   {
1713     // Load to r0 or unneeded register (dummy load)
1714     // but we still need a register to calculate the address
1715     if(opcode[i]==0x22||opcode[i]==0x26)
1716     {
1717       alloc_reg(current,i,FTEMP); // LWL/LWR need another temporary
1718     }
1719     // If using TLB, need a register for pointer to the mapping table
1720     if(using_tlb) alloc_reg(current,i,TLREG);
1721     alloc_reg_temp(current,i,-1);
1722     minimum_free_regs[i]=1;
1723     if(opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
1724     {
1725       alloc_all(current,i);
1726       alloc_reg64(current,i,FTEMP);
1727       minimum_free_regs[i]=HOST_REGS;
1728     }
1729   }
1730 }
1731
1732 void store_alloc(struct regstat *current,int i)
1733 {
1734   clear_const(current,rs2[i]);
1735   if(!(rs2[i])) current->u&=~1LL; // Allow allocating r0 if necessary
1736   if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1737   alloc_reg(current,i,rs2[i]);
1738   if(opcode[i]==0x2c||opcode[i]==0x2d||opcode[i]==0x3f) { // 64-bit SDL/SDR/SD
1739     alloc_reg64(current,i,rs2[i]);
1740     if(rs2[i]) alloc_reg(current,i,FTEMP);
1741   }
1742   // If using TLB, need a register for pointer to the mapping table
1743   if(using_tlb) alloc_reg(current,i,TLREG);
1744   #if defined(HOST_IMM8)
1745   // On CPUs without 32-bit immediates we need a pointer to invalid_code
1746   else alloc_reg(current,i,INVCP);
1747   #endif
1748   if(opcode[i]==0x2a||opcode[i]==0x2e||opcode[i]==0x2c||opcode[i]==0x2d) { // SWL/SWL/SDL/SDR
1749     alloc_reg(current,i,FTEMP);
1750   }
1751   // We need a temporary register for address generation
1752   alloc_reg_temp(current,i,-1);
1753   minimum_free_regs[i]=1;
1754 }
1755
1756 void c1ls_alloc(struct regstat *current,int i)
1757 {
1758   //clear_const(current,rs1[i]); // FIXME
1759   clear_const(current,rt1[i]);
1760   if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1761   alloc_reg(current,i,CSREG); // Status
1762   alloc_reg(current,i,FTEMP);
1763   if(opcode[i]==0x35||opcode[i]==0x3d) { // 64-bit LDC1/SDC1
1764     alloc_reg64(current,i,FTEMP);
1765   }
1766   // If using TLB, need a register for pointer to the mapping table
1767   if(using_tlb) alloc_reg(current,i,TLREG);
1768   #if defined(HOST_IMM8)
1769   // On CPUs without 32-bit immediates we need a pointer to invalid_code
1770   else if((opcode[i]&0x3b)==0x39) // SWC1/SDC1
1771     alloc_reg(current,i,INVCP);
1772   #endif
1773   // We need a temporary register for address generation
1774   alloc_reg_temp(current,i,-1);
1775 }
1776
1777 void c2ls_alloc(struct regstat *current,int i)
1778 {
1779   clear_const(current,rt1[i]);
1780   if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1781   alloc_reg(current,i,FTEMP);
1782   // If using TLB, need a register for pointer to the mapping table
1783   if(using_tlb) alloc_reg(current,i,TLREG);
1784   #if defined(HOST_IMM8)
1785   // On CPUs without 32-bit immediates we need a pointer to invalid_code
1786   else if((opcode[i]&0x3b)==0x3a) // SWC2/SDC2
1787     alloc_reg(current,i,INVCP);
1788   #endif
1789   // We need a temporary register for address generation
1790   alloc_reg_temp(current,i,-1);
1791   minimum_free_regs[i]=1;
1792 }
1793
1794 #ifndef multdiv_alloc
1795 void multdiv_alloc(struct regstat *current,int i)
1796 {
1797   //  case 0x18: MULT
1798   //  case 0x19: MULTU
1799   //  case 0x1A: DIV
1800   //  case 0x1B: DIVU
1801   //  case 0x1C: DMULT
1802   //  case 0x1D: DMULTU
1803   //  case 0x1E: DDIV
1804   //  case 0x1F: DDIVU
1805   clear_const(current,rs1[i]);
1806   clear_const(current,rs2[i]);
1807   if(rs1[i]&&rs2[i])
1808   {
1809     if((opcode2[i]&4)==0) // 32-bit
1810     {
1811       current->u&=~(1LL<<HIREG);
1812       current->u&=~(1LL<<LOREG);
1813       alloc_reg(current,i,HIREG);
1814       alloc_reg(current,i,LOREG);
1815       alloc_reg(current,i,rs1[i]);
1816       alloc_reg(current,i,rs2[i]);
1817       current->is32|=1LL<<HIREG;
1818       current->is32|=1LL<<LOREG;
1819       dirty_reg(current,HIREG);
1820       dirty_reg(current,LOREG);
1821     }
1822     else // 64-bit
1823     {
1824       current->u&=~(1LL<<HIREG);
1825       current->u&=~(1LL<<LOREG);
1826       current->uu&=~(1LL<<HIREG);
1827       current->uu&=~(1LL<<LOREG);
1828       alloc_reg64(current,i,HIREG);
1829       //if(HOST_REGS>10) alloc_reg64(current,i,LOREG);
1830       alloc_reg64(current,i,rs1[i]);
1831       alloc_reg64(current,i,rs2[i]);
1832       alloc_all(current,i);
1833       current->is32&=~(1LL<<HIREG);
1834       current->is32&=~(1LL<<LOREG);
1835       dirty_reg(current,HIREG);
1836       dirty_reg(current,LOREG);
1837       minimum_free_regs[i]=HOST_REGS;
1838     }
1839   }
1840   else
1841   {
1842     // Multiply by zero is zero.
1843     // MIPS does not have a divide by zero exception.
1844     // The result is undefined, we return zero.
1845     alloc_reg(current,i,HIREG);
1846     alloc_reg(current,i,LOREG);
1847     current->is32|=1LL<<HIREG;
1848     current->is32|=1LL<<LOREG;
1849     dirty_reg(current,HIREG);
1850     dirty_reg(current,LOREG);
1851   }
1852 }
1853 #endif
1854
1855 void cop0_alloc(struct regstat *current,int i)
1856 {
1857   if(opcode2[i]==0) // MFC0
1858   {
1859     if(rt1[i]) {
1860       clear_const(current,rt1[i]);
1861       alloc_all(current,i);
1862       alloc_reg(current,i,rt1[i]);
1863       current->is32|=1LL<<rt1[i];
1864       dirty_reg(current,rt1[i]);
1865     }
1866   }
1867   else if(opcode2[i]==4) // MTC0
1868   {
1869     if(rs1[i]){
1870       clear_const(current,rs1[i]);
1871       alloc_reg(current,i,rs1[i]);
1872       alloc_all(current,i);
1873     }
1874     else {
1875       alloc_all(current,i); // FIXME: Keep r0
1876       current->u&=~1LL;
1877       alloc_reg(current,i,0);
1878     }
1879   }
1880   else
1881   {
1882     // TLBR/TLBWI/TLBWR/TLBP/ERET
1883     assert(opcode2[i]==0x10);
1884     alloc_all(current,i);
1885   }
1886   minimum_free_regs[i]=HOST_REGS;
1887 }
1888
1889 void cop1_alloc(struct regstat *current,int i)
1890 {
1891   alloc_reg(current,i,CSREG); // Load status
1892   if(opcode2[i]<3) // MFC1/DMFC1/CFC1
1893   {
1894     if(rt1[i]){
1895       clear_const(current,rt1[i]);
1896       if(opcode2[i]==1) {
1897         alloc_reg64(current,i,rt1[i]); // DMFC1
1898         current->is32&=~(1LL<<rt1[i]);
1899       }else{
1900         alloc_reg(current,i,rt1[i]); // MFC1/CFC1
1901         current->is32|=1LL<<rt1[i];
1902       }
1903       dirty_reg(current,rt1[i]);
1904     }
1905     alloc_reg_temp(current,i,-1);
1906   }
1907   else if(opcode2[i]>3) // MTC1/DMTC1/CTC1
1908   {
1909     if(rs1[i]){
1910       clear_const(current,rs1[i]);
1911       if(opcode2[i]==5)
1912         alloc_reg64(current,i,rs1[i]); // DMTC1
1913       else
1914         alloc_reg(current,i,rs1[i]); // MTC1/CTC1
1915       alloc_reg_temp(current,i,-1);
1916     }
1917     else {
1918       current->u&=~1LL;
1919       alloc_reg(current,i,0);
1920       alloc_reg_temp(current,i,-1);
1921     }
1922   }
1923   minimum_free_regs[i]=1;
1924 }
1925 void fconv_alloc(struct regstat *current,int i)
1926 {
1927   alloc_reg(current,i,CSREG); // Load status
1928   alloc_reg_temp(current,i,-1);
1929   minimum_free_regs[i]=1;
1930 }
1931 void float_alloc(struct regstat *current,int i)
1932 {
1933   alloc_reg(current,i,CSREG); // Load status
1934   alloc_reg_temp(current,i,-1);
1935   minimum_free_regs[i]=1;
1936 }
1937 void c2op_alloc(struct regstat *current,int i)
1938 {
1939   alloc_reg_temp(current,i,-1);
1940 }
1941 void fcomp_alloc(struct regstat *current,int i)
1942 {
1943   alloc_reg(current,i,CSREG); // Load status
1944   alloc_reg(current,i,FSREG); // Load flags
1945   dirty_reg(current,FSREG); // Flag will be modified
1946   alloc_reg_temp(current,i,-1);
1947   minimum_free_regs[i]=1;
1948 }
1949
1950 void syscall_alloc(struct regstat *current,int i)
1951 {
1952   alloc_cc(current,i);
1953   dirty_reg(current,CCREG);
1954   alloc_all(current,i);
1955   minimum_free_regs[i]=HOST_REGS;
1956   current->isconst=0;
1957 }
1958
1959 void delayslot_alloc(struct regstat *current,int i)
1960 {
1961   switch(itype[i]) {
1962     case UJUMP:
1963     case CJUMP:
1964     case SJUMP:
1965     case RJUMP:
1966     case FJUMP:
1967     case SYSCALL:
1968     case HLECALL:
1969     case SPAN:
1970       assem_debug("jump in the delay slot.  this shouldn't happen.\n");//exit(1);
1971       printf("Disabled speculative precompilation\n");
1972       stop_after_jal=1;
1973       break;
1974     case IMM16:
1975       imm16_alloc(current,i);
1976       break;
1977     case LOAD:
1978     case LOADLR:
1979       load_alloc(current,i);
1980       break;
1981     case STORE:
1982     case STORELR:
1983       store_alloc(current,i);
1984       break;
1985     case ALU:
1986       alu_alloc(current,i);
1987       break;
1988     case SHIFT:
1989       shift_alloc(current,i);
1990       break;
1991     case MULTDIV:
1992       multdiv_alloc(current,i);
1993       break;
1994     case SHIFTIMM:
1995       shiftimm_alloc(current,i);
1996       break;
1997     case MOV:
1998       mov_alloc(current,i);
1999       break;
2000     case COP0:
2001       cop0_alloc(current,i);
2002       break;
2003     case COP1:
2004     case COP2:
2005       cop1_alloc(current,i);
2006       break;
2007     case C1LS:
2008       c1ls_alloc(current,i);
2009       break;
2010     case C2LS:
2011       c2ls_alloc(current,i);
2012       break;
2013     case FCONV:
2014       fconv_alloc(current,i);
2015       break;
2016     case FLOAT:
2017       float_alloc(current,i);
2018       break;
2019     case FCOMP:
2020       fcomp_alloc(current,i);
2021       break;
2022     case C2OP:
2023       c2op_alloc(current,i);
2024       break;
2025   }
2026 }
2027
2028 // Special case where a branch and delay slot span two pages in virtual memory
2029 static void pagespan_alloc(struct regstat *current,int i)
2030 {
2031   current->isconst=0;
2032   current->wasconst=0;
2033   regs[i].wasconst=0;
2034   minimum_free_regs[i]=HOST_REGS;
2035   alloc_all(current,i);
2036   alloc_cc(current,i);
2037   dirty_reg(current,CCREG);
2038   if(opcode[i]==3) // JAL
2039   {
2040     alloc_reg(current,i,31);
2041     dirty_reg(current,31);
2042   }
2043   if(opcode[i]==0&&(opcode2[i]&0x3E)==8) // JR/JALR
2044   {
2045     alloc_reg(current,i,rs1[i]);
2046     if (rt1[i]!=0) {
2047       alloc_reg(current,i,rt1[i]);
2048       dirty_reg(current,rt1[i]);
2049     }
2050   }
2051   if((opcode[i]&0x2E)==4) // BEQ/BNE/BEQL/BNEL
2052   {
2053     if(rs1[i]) alloc_reg(current,i,rs1[i]);
2054     if(rs2[i]) alloc_reg(current,i,rs2[i]);
2055     if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
2056     {
2057       if(rs1[i]) alloc_reg64(current,i,rs1[i]);
2058       if(rs2[i]) alloc_reg64(current,i,rs2[i]);
2059     }
2060   }
2061   else
2062   if((opcode[i]&0x2E)==6) // BLEZ/BGTZ/BLEZL/BGTZL
2063   {
2064     if(rs1[i]) alloc_reg(current,i,rs1[i]);
2065     if(!((current->is32>>rs1[i])&1))
2066     {
2067       if(rs1[i]) alloc_reg64(current,i,rs1[i]);
2068     }
2069   }
2070   else
2071   if(opcode[i]==0x11) // BC1
2072   {
2073     alloc_reg(current,i,FSREG);
2074     alloc_reg(current,i,CSREG);
2075   }
2076   //else ...
2077 }
2078
2079 add_stub(int type,int addr,int retaddr,int a,int b,int c,int d,int e)
2080 {
2081   stubs[stubcount][0]=type;
2082   stubs[stubcount][1]=addr;
2083   stubs[stubcount][2]=retaddr;
2084   stubs[stubcount][3]=a;
2085   stubs[stubcount][4]=b;
2086   stubs[stubcount][5]=c;
2087   stubs[stubcount][6]=d;
2088   stubs[stubcount][7]=e;
2089   stubcount++;
2090 }
2091
2092 // Write out a single register
2093 void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32)
2094 {
2095   int hr;
2096   for(hr=0;hr<HOST_REGS;hr++) {
2097     if(hr!=EXCLUDE_REG) {
2098       if((regmap[hr]&63)==r) {
2099         if((dirty>>hr)&1) {
2100           if(regmap[hr]<64) {
2101             emit_storereg(r,hr);
2102 #ifndef FORCE32
2103             if((is32>>regmap[hr])&1) {
2104               emit_sarimm(hr,31,hr);
2105               emit_storereg(r|64,hr);
2106             }
2107 #endif
2108           }else{
2109             emit_storereg(r|64,hr);
2110           }
2111         }
2112       }
2113     }
2114   }
2115 }
2116
2117 int mchecksum()
2118 {
2119   //if(!tracedebug) return 0;
2120   int i;
2121   int sum=0;
2122   for(i=0;i<2097152;i++) {
2123     unsigned int temp=sum;
2124     sum<<=1;
2125     sum|=(~temp)>>31;
2126     sum^=((u_int *)rdram)[i];
2127   }
2128   return sum;
2129 }
2130 int rchecksum()
2131 {
2132   int i;
2133   int sum=0;
2134   for(i=0;i<64;i++)
2135     sum^=((u_int *)reg)[i];
2136   return sum;
2137 }
2138 void rlist()
2139 {
2140   int i;
2141   printf("TRACE: ");
2142   for(i=0;i<32;i++)
2143     printf("r%d:%8x%8x ",i,((int *)(reg+i))[1],((int *)(reg+i))[0]);
2144   printf("\n");
2145 #ifndef DISABLE_COP1
2146   printf("TRACE: ");
2147   for(i=0;i<32;i++)
2148     printf("f%d:%8x%8x ",i,((int*)reg_cop1_simple[i])[1],*((int*)reg_cop1_simple[i]));
2149   printf("\n");
2150 #endif
2151 }
2152
2153 void enabletrace()
2154 {
2155   tracedebug=1;
2156 }
2157
2158 void memdebug(int i)
2159 {
2160   //printf("TRACE: count=%d next=%d (checksum %x) lo=%8x%8x\n",Count,next_interupt,mchecksum(),(int)(reg[LOREG]>>32),(int)reg[LOREG]);
2161   //printf("TRACE: count=%d next=%d (rchecksum %x)\n",Count,next_interupt,rchecksum());
2162   //rlist();
2163   //if(tracedebug) {
2164   //if(Count>=-2084597794) {
2165   if((signed int)Count>=-2084597794&&(signed int)Count<0) {
2166   //if(0) {
2167     printf("TRACE: count=%d next=%d (checksum %x)\n",Count,next_interupt,mchecksum());
2168     //printf("TRACE: count=%d next=%d (checksum %x) Status=%x\n",Count,next_interupt,mchecksum(),Status);
2169     //printf("TRACE: count=%d next=%d (checksum %x) hi=%8x%8x\n",Count,next_interupt,mchecksum(),(int)(reg[HIREG]>>32),(int)reg[HIREG]);
2170     rlist();
2171     #ifdef __i386__
2172     printf("TRACE: %x\n",(&i)[-1]);
2173     #endif
2174     #ifdef __arm__
2175     int j;
2176     printf("TRACE: %x \n",(&j)[10]);
2177     printf("TRACE: %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x\n",(&j)[1],(&j)[2],(&j)[3],(&j)[4],(&j)[5],(&j)[6],(&j)[7],(&j)[8],(&j)[9],(&j)[10],(&j)[11],(&j)[12],(&j)[13],(&j)[14],(&j)[15],(&j)[16],(&j)[17],(&j)[18],(&j)[19],(&j)[20]);
2178     #endif
2179     //fflush(stdout);
2180   }
2181   //printf("TRACE: %x\n",(&i)[-1]);
2182 }
2183
2184 void tlb_debug(u_int cause, u_int addr, u_int iaddr)
2185 {
2186   printf("TLB Exception: instruction=%x addr=%x cause=%x\n",iaddr, addr, cause);
2187 }
2188
2189 void alu_assemble(int i,struct regstat *i_regs)
2190 {
2191   if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
2192     if(rt1[i]) {
2193       signed char s1,s2,t;
2194       t=get_reg(i_regs->regmap,rt1[i]);
2195       if(t>=0) {
2196         s1=get_reg(i_regs->regmap,rs1[i]);
2197         s2=get_reg(i_regs->regmap,rs2[i]);
2198         if(rs1[i]&&rs2[i]) {
2199           assert(s1>=0);
2200           assert(s2>=0);
2201           if(opcode2[i]&2) emit_sub(s1,s2,t);
2202           else emit_add(s1,s2,t);
2203         }
2204         else if(rs1[i]) {
2205           if(s1>=0) emit_mov(s1,t);
2206           else emit_loadreg(rs1[i],t);
2207         }
2208         else if(rs2[i]) {
2209           if(s2>=0) {
2210             if(opcode2[i]&2) emit_neg(s2,t);
2211             else emit_mov(s2,t);
2212           }
2213           else {
2214             emit_loadreg(rs2[i],t);
2215             if(opcode2[i]&2) emit_neg(t,t);
2216           }
2217         }
2218         else emit_zeroreg(t);
2219       }
2220     }
2221   }
2222   if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU
2223     if(rt1[i]) {
2224       signed char s1l,s2l,s1h,s2h,tl,th;
2225       tl=get_reg(i_regs->regmap,rt1[i]);
2226       th=get_reg(i_regs->regmap,rt1[i]|64);
2227       if(tl>=0) {
2228         s1l=get_reg(i_regs->regmap,rs1[i]);
2229         s2l=get_reg(i_regs->regmap,rs2[i]);
2230         s1h=get_reg(i_regs->regmap,rs1[i]|64);
2231         s2h=get_reg(i_regs->regmap,rs2[i]|64);
2232         if(rs1[i]&&rs2[i]) {
2233           assert(s1l>=0);
2234           assert(s2l>=0);
2235           if(opcode2[i]&2) emit_subs(s1l,s2l,tl);
2236           else emit_adds(s1l,s2l,tl);
2237           if(th>=0) {
2238             #ifdef INVERTED_CARRY
2239             if(opcode2[i]&2) {if(s1h!=th) emit_mov(s1h,th);emit_sbb(th,s2h);}
2240             #else
2241             if(opcode2[i]&2) emit_sbc(s1h,s2h,th);
2242             #endif
2243             else emit_add(s1h,s2h,th);
2244           }
2245         }
2246         else if(rs1[i]) {
2247           if(s1l>=0) emit_mov(s1l,tl);
2248           else emit_loadreg(rs1[i],tl);
2249           if(th>=0) {
2250             if(s1h>=0) emit_mov(s1h,th);
2251             else emit_loadreg(rs1[i]|64,th);
2252           }
2253         }
2254         else if(rs2[i]) {
2255           if(s2l>=0) {
2256             if(opcode2[i]&2) emit_negs(s2l,tl);
2257             else emit_mov(s2l,tl);
2258           }
2259           else {
2260             emit_loadreg(rs2[i],tl);
2261             if(opcode2[i]&2) emit_negs(tl,tl);
2262           }
2263           if(th>=0) {
2264             #ifdef INVERTED_CARRY
2265             if(s2h>=0) emit_mov(s2h,th);
2266             else emit_loadreg(rs2[i]|64,th);
2267             if(opcode2[i]&2) {
2268               emit_adcimm(-1,th); // x86 has inverted carry flag
2269               emit_not(th,th);
2270             }
2271             #else
2272             if(opcode2[i]&2) {
2273               if(s2h>=0) emit_rscimm(s2h,0,th);
2274               else {
2275                 emit_loadreg(rs2[i]|64,th);
2276                 emit_rscimm(th,0,th);
2277               }
2278             }else{
2279               if(s2h>=0) emit_mov(s2h,th);
2280               else emit_loadreg(rs2[i]|64,th);
2281             }
2282             #endif
2283           }
2284         }
2285         else {
2286           emit_zeroreg(tl);
2287           if(th>=0) emit_zeroreg(th);
2288         }
2289       }
2290     }
2291   }
2292   if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU
2293     if(rt1[i]) {
2294       signed char s1l,s1h,s2l,s2h,t;
2295       if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1))
2296       {
2297         t=get_reg(i_regs->regmap,rt1[i]);
2298         //assert(t>=0);
2299         if(t>=0) {
2300           s1l=get_reg(i_regs->regmap,rs1[i]);
2301           s1h=get_reg(i_regs->regmap,rs1[i]|64);
2302           s2l=get_reg(i_regs->regmap,rs2[i]);
2303           s2h=get_reg(i_regs->regmap,rs2[i]|64);
2304           if(rs2[i]==0) // rx<r0
2305           {
2306             assert(s1h>=0);
2307             if(opcode2[i]==0x2a) // SLT
2308               emit_shrimm(s1h,31,t);
2309             else // SLTU (unsigned can not be less than zero)
2310               emit_zeroreg(t);
2311           }
2312           else if(rs1[i]==0) // r0<rx
2313           {
2314             assert(s2h>=0);
2315             if(opcode2[i]==0x2a) // SLT
2316               emit_set_gz64_32(s2h,s2l,t);
2317             else // SLTU (set if not zero)
2318               emit_set_nz64_32(s2h,s2l,t);
2319           }
2320           else {
2321             assert(s1l>=0);assert(s1h>=0);
2322             assert(s2l>=0);assert(s2h>=0);
2323             if(opcode2[i]==0x2a) // SLT
2324               emit_set_if_less64_32(s1h,s1l,s2h,s2l,t);
2325             else // SLTU
2326               emit_set_if_carry64_32(s1h,s1l,s2h,s2l,t);
2327           }
2328         }
2329       } else {
2330         t=get_reg(i_regs->regmap,rt1[i]);
2331         //assert(t>=0);
2332         if(t>=0) {
2333           s1l=get_reg(i_regs->regmap,rs1[i]);
2334           s2l=get_reg(i_regs->regmap,rs2[i]);
2335           if(rs2[i]==0) // rx<r0
2336           {
2337             assert(s1l>=0);
2338             if(opcode2[i]==0x2a) // SLT
2339               emit_shrimm(s1l,31,t);
2340             else // SLTU (unsigned can not be less than zero)
2341               emit_zeroreg(t);
2342           }
2343           else if(rs1[i]==0) // r0<rx
2344           {
2345             assert(s2l>=0);
2346             if(opcode2[i]==0x2a) // SLT
2347               emit_set_gz32(s2l,t);
2348             else // SLTU (set if not zero)
2349               emit_set_nz32(s2l,t);
2350           }
2351           else{
2352             assert(s1l>=0);assert(s2l>=0);
2353             if(opcode2[i]==0x2a) // SLT
2354               emit_set_if_less32(s1l,s2l,t);
2355             else // SLTU
2356               emit_set_if_carry32(s1l,s2l,t);
2357           }
2358         }
2359       }
2360     }
2361   }
2362   if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR
2363     if(rt1[i]) {
2364       signed char s1l,s1h,s2l,s2h,th,tl;
2365       tl=get_reg(i_regs->regmap,rt1[i]);
2366       th=get_reg(i_regs->regmap,rt1[i]|64);
2367       if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1)&&th>=0)
2368       {
2369         assert(tl>=0);
2370         if(tl>=0) {
2371           s1l=get_reg(i_regs->regmap,rs1[i]);
2372           s1h=get_reg(i_regs->regmap,rs1[i]|64);
2373           s2l=get_reg(i_regs->regmap,rs2[i]);
2374           s2h=get_reg(i_regs->regmap,rs2[i]|64);
2375           if(rs1[i]&&rs2[i]) {
2376             assert(s1l>=0);assert(s1h>=0);
2377             assert(s2l>=0);assert(s2h>=0);
2378             if(opcode2[i]==0x24) { // AND
2379               emit_and(s1l,s2l,tl);
2380               emit_and(s1h,s2h,th);
2381             } else
2382             if(opcode2[i]==0x25) { // OR
2383               emit_or(s1l,s2l,tl);
2384               emit_or(s1h,s2h,th);
2385             } else
2386             if(opcode2[i]==0x26) { // XOR
2387               emit_xor(s1l,s2l,tl);
2388               emit_xor(s1h,s2h,th);
2389             } else
2390             if(opcode2[i]==0x27) { // NOR
2391               emit_or(s1l,s2l,tl);
2392               emit_or(s1h,s2h,th);
2393               emit_not(tl,tl);
2394               emit_not(th,th);
2395             }
2396           }
2397           else
2398           {
2399             if(opcode2[i]==0x24) { // AND
2400               emit_zeroreg(tl);
2401               emit_zeroreg(th);
2402             } else
2403             if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR
2404               if(rs1[i]){
2405                 if(s1l>=0) emit_mov(s1l,tl);
2406                 else emit_loadreg(rs1[i],tl);
2407                 if(s1h>=0) emit_mov(s1h,th);
2408                 else emit_loadreg(rs1[i]|64,th);
2409               }
2410               else
2411               if(rs2[i]){
2412                 if(s2l>=0) emit_mov(s2l,tl);
2413                 else emit_loadreg(rs2[i],tl);
2414                 if(s2h>=0) emit_mov(s2h,th);
2415                 else emit_loadreg(rs2[i]|64,th);
2416               }
2417               else{
2418                 emit_zeroreg(tl);
2419                 emit_zeroreg(th);
2420               }
2421             } else
2422             if(opcode2[i]==0x27) { // NOR
2423               if(rs1[i]){
2424                 if(s1l>=0) emit_not(s1l,tl);
2425                 else{
2426                   emit_loadreg(rs1[i],tl);
2427                   emit_not(tl,tl);
2428                 }
2429                 if(s1h>=0) emit_not(s1h,th);
2430                 else{
2431                   emit_loadreg(rs1[i]|64,th);
2432                   emit_not(th,th);
2433                 }
2434               }
2435               else
2436               if(rs2[i]){
2437                 if(s2l>=0) emit_not(s2l,tl);
2438                 else{
2439                   emit_loadreg(rs2[i],tl);
2440                   emit_not(tl,tl);
2441                 }
2442                 if(s2h>=0) emit_not(s2h,th);
2443                 else{
2444                   emit_loadreg(rs2[i]|64,th);
2445                   emit_not(th,th);
2446                 }
2447               }
2448               else {
2449                 emit_movimm(-1,tl);
2450                 emit_movimm(-1,th);
2451               }
2452             }
2453           }
2454         }
2455       }
2456       else
2457       {
2458         // 32 bit
2459         if(tl>=0) {
2460           s1l=get_reg(i_regs->regmap,rs1[i]);
2461           s2l=get_reg(i_regs->regmap,rs2[i]);
2462           if(rs1[i]&&rs2[i]) {
2463             assert(s1l>=0);
2464             assert(s2l>=0);
2465             if(opcode2[i]==0x24) { // AND
2466               emit_and(s1l,s2l,tl);
2467             } else
2468             if(opcode2[i]==0x25) { // OR
2469               emit_or(s1l,s2l,tl);
2470             } else
2471             if(opcode2[i]==0x26) { // XOR
2472               emit_xor(s1l,s2l,tl);
2473             } else
2474             if(opcode2[i]==0x27) { // NOR
2475               emit_or(s1l,s2l,tl);
2476               emit_not(tl,tl);
2477             }
2478           }
2479           else
2480           {
2481             if(opcode2[i]==0x24) { // AND
2482               emit_zeroreg(tl);
2483             } else
2484             if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR
2485               if(rs1[i]){
2486                 if(s1l>=0) emit_mov(s1l,tl);
2487                 else emit_loadreg(rs1[i],tl); // CHECK: regmap_entry?
2488               }
2489               else
2490               if(rs2[i]){
2491                 if(s2l>=0) emit_mov(s2l,tl);
2492                 else emit_loadreg(rs2[i],tl); // CHECK: regmap_entry?
2493               }
2494               else emit_zeroreg(tl);
2495             } else
2496             if(opcode2[i]==0x27) { // NOR
2497               if(rs1[i]){
2498                 if(s1l>=0) emit_not(s1l,tl);
2499                 else {
2500                   emit_loadreg(rs1[i],tl);
2501                   emit_not(tl,tl);
2502                 }
2503               }
2504               else
2505               if(rs2[i]){
2506                 if(s2l>=0) emit_not(s2l,tl);
2507                 else {
2508                   emit_loadreg(rs2[i],tl);
2509                   emit_not(tl,tl);
2510                 }
2511               }
2512               else emit_movimm(-1,tl);
2513             }
2514           }
2515         }
2516       }
2517     }
2518   }
2519 }
2520
2521 void imm16_assemble(int i,struct regstat *i_regs)
2522 {
2523   if (opcode[i]==0x0f) { // LUI
2524     if(rt1[i]) {
2525       signed char t;
2526       t=get_reg(i_regs->regmap,rt1[i]);
2527       //assert(t>=0);
2528       if(t>=0) {
2529         if(!((i_regs->isconst>>t)&1))
2530           emit_movimm(imm[i]<<16,t);
2531       }
2532     }
2533   }
2534   if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU
2535     if(rt1[i]) {
2536       signed char s,t;
2537       t=get_reg(i_regs->regmap,rt1[i]);
2538       s=get_reg(i_regs->regmap,rs1[i]);
2539       if(rs1[i]) {
2540         //assert(t>=0);
2541         //assert(s>=0);
2542         if(t>=0) {
2543           if(!((i_regs->isconst>>t)&1)) {
2544             if(s<0) {
2545               if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2546               emit_addimm(t,imm[i],t);
2547             }else{
2548               if(!((i_regs->wasconst>>s)&1))
2549                 emit_addimm(s,imm[i],t);
2550               else
2551                 emit_movimm(constmap[i][s]+imm[i],t);
2552             }
2553           }
2554         }
2555       } else {
2556         if(t>=0) {
2557           if(!((i_regs->isconst>>t)&1))
2558             emit_movimm(imm[i],t);
2559         }
2560       }
2561     }
2562   }
2563   if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU
2564     if(rt1[i]) {
2565       signed char sh,sl,th,tl;
2566       th=get_reg(i_regs->regmap,rt1[i]|64);
2567       tl=get_reg(i_regs->regmap,rt1[i]);
2568       sh=get_reg(i_regs->regmap,rs1[i]|64);
2569       sl=get_reg(i_regs->regmap,rs1[i]);
2570       if(tl>=0) {
2571         if(rs1[i]) {
2572           assert(sh>=0);
2573           assert(sl>=0);
2574           if(th>=0) {
2575             emit_addimm64_32(sh,sl,imm[i],th,tl);
2576           }
2577           else {
2578             emit_addimm(sl,imm[i],tl);
2579           }
2580         } else {
2581           emit_movimm(imm[i],tl);
2582           if(th>=0) emit_movimm(((signed int)imm[i])>>31,th);
2583         }
2584       }
2585     }
2586   }
2587   else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU
2588     if(rt1[i]) {
2589       //assert(rs1[i]!=0); // r0 might be valid, but it's probably a bug
2590       signed char sh,sl,t;
2591       t=get_reg(i_regs->regmap,rt1[i]);
2592       sh=get_reg(i_regs->regmap,rs1[i]|64);
2593       sl=get_reg(i_regs->regmap,rs1[i]);
2594       //assert(t>=0);
2595       if(t>=0) {
2596         if(rs1[i]>0) {
2597           if(sh<0) assert((i_regs->was32>>rs1[i])&1);
2598           if(sh<0||((i_regs->was32>>rs1[i])&1)) {
2599             if(opcode[i]==0x0a) { // SLTI
2600               if(sl<0) {
2601                 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2602                 emit_slti32(t,imm[i],t);
2603               }else{
2604                 emit_slti32(sl,imm[i],t);
2605               }
2606             }
2607             else { // SLTIU
2608               if(sl<0) {
2609                 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2610                 emit_sltiu32(t,imm[i],t);
2611               }else{
2612                 emit_sltiu32(sl,imm[i],t);
2613               }
2614             }
2615           }else{ // 64-bit
2616             assert(sl>=0);
2617             if(opcode[i]==0x0a) // SLTI
2618               emit_slti64_32(sh,sl,imm[i],t);
2619             else // SLTIU
2620               emit_sltiu64_32(sh,sl,imm[i],t);
2621           }
2622         }else{
2623           // SLTI(U) with r0 is just stupid,
2624           // nonetheless examples can be found
2625           if(opcode[i]==0x0a) // SLTI
2626             if(0<imm[i]) emit_movimm(1,t);
2627             else emit_zeroreg(t);
2628           else // SLTIU
2629           {
2630             if(imm[i]) emit_movimm(1,t);
2631             else emit_zeroreg(t);
2632           }
2633         }
2634       }
2635     }
2636   }
2637   else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI
2638     if(rt1[i]) {
2639       signed char sh,sl,th,tl;
2640       th=get_reg(i_regs->regmap,rt1[i]|64);
2641       tl=get_reg(i_regs->regmap,rt1[i]);
2642       sh=get_reg(i_regs->regmap,rs1[i]|64);
2643       sl=get_reg(i_regs->regmap,rs1[i]);
2644       if(tl>=0 && !((i_regs->isconst>>tl)&1)) {
2645         if(opcode[i]==0x0c) //ANDI
2646         {
2647           if(rs1[i]) {
2648             if(sl<0) {
2649               if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl);
2650               emit_andimm(tl,imm[i],tl);
2651             }else{
2652               if(!((i_regs->wasconst>>sl)&1))
2653                 emit_andimm(sl,imm[i],tl);
2654               else
2655                 emit_movimm(constmap[i][sl]&imm[i],tl);
2656             }
2657           }
2658           else
2659             emit_zeroreg(tl);
2660           if(th>=0) emit_zeroreg(th);
2661         }
2662         else
2663         {
2664           if(rs1[i]) {
2665             if(sl<0) {
2666               if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl);
2667             }
2668             if(th>=0) {
2669               if(sh<0) {
2670                 emit_loadreg(rs1[i]|64,th);
2671               }else{
2672                 emit_mov(sh,th);
2673               }
2674             }
2675             if(opcode[i]==0x0d) //ORI
2676             if(sl<0) {
2677               emit_orimm(tl,imm[i],tl);
2678             }else{
2679               if(!((i_regs->wasconst>>sl)&1))
2680                 emit_orimm(sl,imm[i],tl);
2681               else
2682                 emit_movimm(constmap[i][sl]|imm[i],tl);
2683             }
2684             if(opcode[i]==0x0e) //XORI
2685             if(sl<0) {
2686               emit_xorimm(tl,imm[i],tl);
2687             }else{
2688               if(!((i_regs->wasconst>>sl)&1))
2689                 emit_xorimm(sl,imm[i],tl);
2690               else
2691                 emit_movimm(constmap[i][sl]^imm[i],tl);
2692             }
2693           }
2694           else {
2695             emit_movimm(imm[i],tl);
2696             if(th>=0) emit_zeroreg(th);
2697           }
2698         }
2699       }
2700     }
2701   }
2702 }
2703
2704 void shiftimm_assemble(int i,struct regstat *i_regs)
2705 {
2706   if(opcode2[i]<=0x3) // SLL/SRL/SRA
2707   {
2708     if(rt1[i]) {
2709       signed char s,t;
2710       t=get_reg(i_regs->regmap,rt1[i]);
2711       s=get_reg(i_regs->regmap,rs1[i]);
2712       //assert(t>=0);
2713       if(t>=0&&!((i_regs->isconst>>t)&1)){
2714         if(rs1[i]==0)
2715         {
2716           emit_zeroreg(t);
2717         }
2718         else
2719         {
2720           if(s<0&&i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2721           if(imm[i]) {
2722             if(opcode2[i]==0) // SLL
2723             {
2724               emit_shlimm(s<0?t:s,imm[i],t);
2725             }
2726             if(opcode2[i]==2) // SRL
2727             {
2728               emit_shrimm(s<0?t:s,imm[i],t);
2729             }
2730             if(opcode2[i]==3) // SRA
2731             {
2732               emit_sarimm(s<0?t:s,imm[i],t);
2733             }
2734           }else{
2735             // Shift by zero
2736             if(s>=0 && s!=t) emit_mov(s,t);
2737           }
2738         }
2739       }
2740       //emit_storereg(rt1[i],t); //DEBUG
2741     }
2742   }
2743   if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA
2744   {
2745     if(rt1[i]) {
2746       signed char sh,sl,th,tl;
2747       th=get_reg(i_regs->regmap,rt1[i]|64);
2748       tl=get_reg(i_regs->regmap,rt1[i]);
2749       sh=get_reg(i_regs->regmap,rs1[i]|64);
2750       sl=get_reg(i_regs->regmap,rs1[i]);
2751       if(tl>=0) {
2752         if(rs1[i]==0)
2753         {
2754           emit_zeroreg(tl);
2755           if(th>=0) emit_zeroreg(th);
2756         }
2757         else
2758         {
2759           assert(sl>=0);
2760           assert(sh>=0);
2761           if(imm[i]) {
2762             if(opcode2[i]==0x38) // DSLL
2763             {
2764               if(th>=0) emit_shldimm(sh,sl,imm[i],th);
2765               emit_shlimm(sl,imm[i],tl);
2766             }
2767             if(opcode2[i]==0x3a) // DSRL
2768             {
2769               emit_shrdimm(sl,sh,imm[i],tl);
2770               if(th>=0) emit_shrimm(sh,imm[i],th);
2771             }
2772             if(opcode2[i]==0x3b) // DSRA
2773             {
2774               emit_shrdimm(sl,sh,imm[i],tl);
2775               if(th>=0) emit_sarimm(sh,imm[i],th);
2776             }
2777           }else{
2778             // Shift by zero
2779             if(sl!=tl) emit_mov(sl,tl);
2780             if(th>=0&&sh!=th) emit_mov(sh,th);
2781           }
2782         }
2783       }
2784     }
2785   }
2786   if(opcode2[i]==0x3c) // DSLL32
2787   {
2788     if(rt1[i]) {
2789       signed char sl,tl,th;
2790       tl=get_reg(i_regs->regmap,rt1[i]);
2791       th=get_reg(i_regs->regmap,rt1[i]|64);
2792       sl=get_reg(i_regs->regmap,rs1[i]);
2793       if(th>=0||tl>=0){
2794         assert(tl>=0);
2795         assert(th>=0);
2796         assert(sl>=0);
2797         emit_mov(sl,th);
2798         emit_zeroreg(tl);
2799         if(imm[i]>32)
2800         {
2801           emit_shlimm(th,imm[i]&31,th);
2802         }
2803       }
2804     }
2805   }
2806   if(opcode2[i]==0x3e) // DSRL32
2807   {
2808     if(rt1[i]) {
2809       signed char sh,tl,th;
2810       tl=get_reg(i_regs->regmap,rt1[i]);
2811       th=get_reg(i_regs->regmap,rt1[i]|64);
2812       sh=get_reg(i_regs->regmap,rs1[i]|64);
2813       if(tl>=0){
2814         assert(sh>=0);
2815         emit_mov(sh,tl);
2816         if(th>=0) emit_zeroreg(th);
2817         if(imm[i]>32)
2818         {
2819           emit_shrimm(tl,imm[i]&31,tl);
2820         }
2821       }
2822     }
2823   }
2824   if(opcode2[i]==0x3f) // DSRA32
2825   {
2826     if(rt1[i]) {
2827       signed char sh,tl;
2828       tl=get_reg(i_regs->regmap,rt1[i]);
2829       sh=get_reg(i_regs->regmap,rs1[i]|64);
2830       if(tl>=0){
2831         assert(sh>=0);
2832         emit_mov(sh,tl);
2833         if(imm[i]>32)
2834         {
2835           emit_sarimm(tl,imm[i]&31,tl);
2836         }
2837       }
2838     }
2839   }
2840 }
2841
2842 #ifndef shift_assemble
2843 void shift_assemble(int i,struct regstat *i_regs)
2844 {
2845   printf("Need shift_assemble for this architecture.\n");
2846   exit(1);
2847 }
2848 #endif
2849
2850 void load_assemble(int i,struct regstat *i_regs)
2851 {
2852   int s,th,tl,addr,map=-1;
2853   int offset;
2854   int jaddr=0;
2855   int memtarget=0,c=0;
2856   int fastload_reg_override=0;
2857   u_int hr,reglist=0;
2858   th=get_reg(i_regs->regmap,rt1[i]|64);
2859   tl=get_reg(i_regs->regmap,rt1[i]);
2860   s=get_reg(i_regs->regmap,rs1[i]);
2861   offset=imm[i];
2862   for(hr=0;hr<HOST_REGS;hr++) {
2863     if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
2864   }
2865   if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
2866   if(s>=0) {
2867     c=(i_regs->wasconst>>s)&1;
2868     if (c) {
2869       memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
2870       if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
2871     }
2872   }
2873   //printf("load_assemble: c=%d\n",c);
2874   //if(c) printf("load_assemble: const=%x\n",(int)constmap[i][s]+offset);
2875   // FIXME: Even if the load is a NOP, we should check for pagefaults...
2876 #ifdef PCSX
2877   if(tl<0&&(!c||(((u_int)constmap[i][s]+offset)>>16)==0x1f80)
2878     ||rt1[i]==0) {
2879       // could be FIFO, must perform the read
2880       // ||dummy read
2881       assem_debug("(forced read)\n");
2882       tl=get_reg(i_regs->regmap,-1);
2883       assert(tl>=0);
2884   }
2885 #endif
2886   if(offset||s<0||c) addr=tl;
2887   else addr=s;
2888   //if(tl<0) tl=get_reg(i_regs->regmap,-1);
2889  if(tl>=0) {
2890   //printf("load_assemble: c=%d\n",c);
2891   //if(c) printf("load_assemble: const=%x\n",(int)constmap[i][s]+offset);
2892   assert(tl>=0); // Even if the load is a NOP, we must check for pagefaults and I/O
2893   reglist&=~(1<<tl);
2894   if(th>=0) reglist&=~(1<<th);
2895   if(!using_tlb) {
2896     if(!c) {
2897       #ifdef RAM_OFFSET
2898       map=get_reg(i_regs->regmap,ROREG);
2899       if(map<0) emit_loadreg(ROREG,map=HOST_TEMPREG);
2900       #endif
2901 //#define R29_HACK 1
2902       #ifdef R29_HACK
2903       // Strmnnrmn's speed hack
2904       if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
2905       #endif
2906       {
2907         jaddr=emit_fastpath_cmp_jump(i,addr,&fastload_reg_override);
2908       }
2909     }
2910   }else{ // using tlb
2911     int x=0;
2912     if (opcode[i]==0x20||opcode[i]==0x24) x=3; // LB/LBU
2913     if (opcode[i]==0x21||opcode[i]==0x25) x=2; // LH/LHU
2914     map=get_reg(i_regs->regmap,TLREG);
2915     assert(map>=0);
2916     reglist&=~(1<<map);
2917     map=do_tlb_r(addr,tl,map,x,-1,-1,c,constmap[i][s]+offset);
2918     do_tlb_r_branch(map,c,constmap[i][s]+offset,&jaddr);
2919   }
2920   int dummy=(rt1[i]==0)||(tl!=get_reg(i_regs->regmap,rt1[i])); // ignore loads to r0 and unneeded reg
2921   if (opcode[i]==0x20) { // LB
2922     if(!c||memtarget) {
2923       if(!dummy) {
2924         #ifdef HOST_IMM_ADDR32
2925         if(c)
2926           emit_movsbl_tlb((constmap[i][s]+offset)^3,map,tl);
2927         else
2928         #endif
2929         {
2930           //emit_xorimm(addr,3,tl);
2931           //gen_tlb_addr_r(tl,map);
2932           //emit_movsbl_indexed((int)rdram-0x80000000,tl,tl);
2933           int x=0,a=tl;
2934 #ifdef BIG_ENDIAN_MIPS
2935           if(!c) emit_xorimm(addr,3,tl);
2936           else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2937 #else
2938           if(!c) a=addr;
2939 #endif
2940           if(fastload_reg_override) a=fastload_reg_override;
2941
2942           emit_movsbl_indexed_tlb(x,a,map,tl);
2943         }
2944       }
2945       if(jaddr)
2946         add_stub(LOADB_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2947     }
2948     else
2949       inline_readstub(LOADB_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2950   }
2951   if (opcode[i]==0x21) { // LH
2952     if(!c||memtarget) {
2953       if(!dummy) {
2954         #ifdef HOST_IMM_ADDR32
2955         if(c)
2956           emit_movswl_tlb((constmap[i][s]+offset)^2,map,tl);
2957         else
2958         #endif
2959         {
2960           int x=0,a=tl;
2961 #ifdef BIG_ENDIAN_MIPS
2962           if(!c) emit_xorimm(addr,2,tl);
2963           else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
2964 #else
2965           if(!c) a=addr;
2966 #endif
2967           if(fastload_reg_override) a=fastload_reg_override;
2968           //#ifdef
2969           //emit_movswl_indexed_tlb(x,tl,map,tl);
2970           //else
2971           if(map>=0) {
2972             gen_tlb_addr_r(a,map);
2973             emit_movswl_indexed(x,a,tl);
2974           }else{
2975             #ifdef RAM_OFFSET
2976             emit_movswl_indexed(x,a,tl);
2977             #else
2978             emit_movswl_indexed((int)rdram-0x80000000+x,a,tl);
2979             #endif
2980           }
2981         }
2982       }
2983       if(jaddr)
2984         add_stub(LOADH_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2985     }
2986     else
2987       inline_readstub(LOADH_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2988   }
2989   if (opcode[i]==0x23) { // LW
2990     if(!c||memtarget) {
2991       if(!dummy) {
2992         int a=addr;
2993         if(fastload_reg_override) a=fastload_reg_override;
2994         //emit_readword_indexed((int)rdram-0x80000000,addr,tl);
2995         #ifdef HOST_IMM_ADDR32
2996         if(c)
2997           emit_readword_tlb(constmap[i][s]+offset,map,tl);
2998         else
2999         #endif
3000         emit_readword_indexed_tlb(0,a,map,tl);
3001       }
3002       if(jaddr)
3003         add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3004     }
3005     else
3006       inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3007   }
3008   if (opcode[i]==0x24) { // LBU
3009     if(!c||memtarget) {
3010       if(!dummy) {
3011         #ifdef HOST_IMM_ADDR32
3012         if(c)
3013           emit_movzbl_tlb((constmap[i][s]+offset)^3,map,tl);
3014         else
3015         #endif
3016         {
3017           //emit_xorimm(addr,3,tl);
3018           //gen_tlb_addr_r(tl,map);
3019           //emit_movzbl_indexed((int)rdram-0x80000000,tl,tl);
3020           int x=0,a=tl;
3021 #ifdef BIG_ENDIAN_MIPS
3022           if(!c) emit_xorimm(addr,3,tl);
3023           else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
3024 #else
3025           if(!c) a=addr;
3026 #endif
3027           if(fastload_reg_override) a=fastload_reg_override;
3028
3029           emit_movzbl_indexed_tlb(x,a,map,tl);
3030         }
3031       }
3032       if(jaddr)
3033         add_stub(LOADBU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3034     }
3035     else
3036       inline_readstub(LOADBU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3037   }
3038   if (opcode[i]==0x25) { // LHU
3039     if(!c||memtarget) {
3040       if(!dummy) {
3041         #ifdef HOST_IMM_ADDR32
3042         if(c)
3043           emit_movzwl_tlb((constmap[i][s]+offset)^2,map,tl);
3044         else
3045         #endif
3046         {
3047           int x=0,a=tl;
3048 #ifdef BIG_ENDIAN_MIPS
3049           if(!c) emit_xorimm(addr,2,tl);
3050           else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
3051 #else
3052           if(!c) a=addr;
3053 #endif
3054           if(fastload_reg_override) a=fastload_reg_override;
3055           //#ifdef
3056           //emit_movzwl_indexed_tlb(x,tl,map,tl);
3057           //#else
3058           if(map>=0) {
3059             gen_tlb_addr_r(a,map);
3060             emit_movzwl_indexed(x,a,tl);
3061           }else{
3062             #ifdef RAM_OFFSET
3063             emit_movzwl_indexed(x,a,tl);
3064             #else
3065             emit_movzwl_indexed((int)rdram-0x80000000+x,a,tl);
3066             #endif
3067           }
3068         }
3069       }
3070       if(jaddr)
3071         add_stub(LOADHU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3072     }
3073     else
3074       inline_readstub(LOADHU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3075   }
3076   if (opcode[i]==0x27) { // LWU
3077     assert(th>=0);
3078     if(!c||memtarget) {
3079       if(!dummy) {
3080         int a=addr;
3081         if(fastload_reg_override) a=fastload_reg_override;
3082         //emit_readword_indexed((int)rdram-0x80000000,addr,tl);
3083         #ifdef HOST_IMM_ADDR32
3084         if(c)
3085           emit_readword_tlb(constmap[i][s]+offset,map,tl);
3086         else
3087         #endif
3088         emit_readword_indexed_tlb(0,a,map,tl);
3089       }
3090       if(jaddr)
3091         add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3092     }
3093     else {
3094       inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3095     }
3096     emit_zeroreg(th);
3097   }
3098   if (opcode[i]==0x37) { // LD
3099     if(!c||memtarget) {
3100       if(!dummy) {
3101         int a=addr;
3102         if(fastload_reg_override) a=fastload_reg_override;
3103         //gen_tlb_addr_r(tl,map);
3104         //if(th>=0) emit_readword_indexed((int)rdram-0x80000000,addr,th);
3105         //emit_readword_indexed((int)rdram-0x7FFFFFFC,addr,tl);
3106         #ifdef HOST_IMM_ADDR32
3107         if(c)
3108           emit_readdword_tlb(constmap[i][s]+offset,map,th,tl);
3109         else
3110         #endif
3111         emit_readdword_indexed_tlb(0,a,map,th,tl);
3112       }
3113       if(jaddr)
3114         add_stub(LOADD_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3115     }
3116     else
3117       inline_readstub(LOADD_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3118   }
3119  }
3120   //emit_storereg(rt1[i],tl); // DEBUG
3121   //if(opcode[i]==0x23)
3122   //if(opcode[i]==0x24)
3123   //if(opcode[i]==0x23||opcode[i]==0x24)
3124   /*if(opcode[i]==0x21||opcode[i]==0x23||opcode[i]==0x24)
3125   {
3126     //emit_pusha();
3127     save_regs(0x100f);
3128         emit_readword((int)&last_count,ECX);
3129         #ifdef __i386__
3130         if(get_reg(i_regs->regmap,CCREG)<0)
3131           emit_loadreg(CCREG,HOST_CCREG);
3132         emit_add(HOST_CCREG,ECX,HOST_CCREG);
3133         emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3134         emit_writeword(HOST_CCREG,(int)&Count);
3135         #endif
3136         #ifdef __arm__
3137         if(get_reg(i_regs->regmap,CCREG)<0)
3138           emit_loadreg(CCREG,0);
3139         else
3140           emit_mov(HOST_CCREG,0);
3141         emit_add(0,ECX,0);
3142         emit_addimm(0,2*ccadj[i],0);
3143         emit_writeword(0,(int)&Count);
3144         #endif
3145     emit_call((int)memdebug);
3146     //emit_popa();
3147     restore_regs(0x100f);
3148   }/**/
3149 }
3150
3151 #ifndef loadlr_assemble
3152 void loadlr_assemble(int i,struct regstat *i_regs)
3153 {
3154   printf("Need loadlr_assemble for this architecture.\n");
3155   exit(1);
3156 }
3157 #endif
3158
3159 void store_assemble(int i,struct regstat *i_regs)
3160 {
3161   int s,th,tl,map=-1;
3162   int addr,temp;
3163   int offset;
3164   int jaddr=0,jaddr2,type;
3165   int memtarget=0,c=0;
3166   int agr=AGEN1+(i&1);
3167   int faststore_reg_override=0;
3168   u_int hr,reglist=0;
3169   th=get_reg(i_regs->regmap,rs2[i]|64);
3170   tl=get_reg(i_regs->regmap,rs2[i]);
3171   s=get_reg(i_regs->regmap,rs1[i]);
3172   temp=get_reg(i_regs->regmap,agr);
3173   if(temp<0) temp=get_reg(i_regs->regmap,-1);
3174   offset=imm[i];
3175   if(s>=0) {
3176     c=(i_regs->wasconst>>s)&1;
3177     if(c) {
3178       memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
3179       if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
3180     }
3181   }
3182   assert(tl>=0);
3183   assert(temp>=0);
3184   for(hr=0;hr<HOST_REGS;hr++) {
3185     if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3186   }
3187   if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
3188   if(offset||s<0||c) addr=temp;
3189   else addr=s;
3190   if(!using_tlb) {
3191     if(!c) {
3192       #ifndef PCSX
3193       #ifdef R29_HACK
3194       // Strmnnrmn's speed hack
3195       if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
3196       #endif
3197       emit_cmpimm(addr,RAM_SIZE);
3198       #ifdef DESTRUCTIVE_SHIFT
3199       if(s==addr) emit_mov(s,temp);
3200       #endif
3201       #ifdef R29_HACK
3202       memtarget=1;
3203       if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
3204       #endif
3205       {
3206         jaddr=(int)out;
3207         #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
3208         // Hint to branch predictor that the branch is unlikely to be taken
3209         if(rs1[i]>=28)
3210           emit_jno_unlikely(0);
3211         else
3212         #endif
3213         emit_jno(0);
3214       }
3215       #else
3216         jaddr=emit_fastpath_cmp_jump(i,addr,&faststore_reg_override);
3217       #endif
3218     }
3219   }else{ // using tlb
3220     int x=0;
3221     if (opcode[i]==0x28) x=3; // SB
3222     if (opcode[i]==0x29) x=2; // SH
3223     map=get_reg(i_regs->regmap,TLREG);
3224     assert(map>=0);
3225     reglist&=~(1<<map);
3226     map=do_tlb_w(addr,temp,map,x,c,constmap[i][s]+offset);
3227     do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr);
3228   }
3229
3230   if (opcode[i]==0x28) { // SB
3231     if(!c||memtarget) {
3232       int x=0,a=temp;
3233 #ifdef BIG_ENDIAN_MIPS
3234       if(!c) emit_xorimm(addr,3,temp);
3235       else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
3236 #else
3237       if(!c) a=addr;
3238 #endif
3239       if(faststore_reg_override) a=faststore_reg_override;
3240       //gen_tlb_addr_w(temp,map);
3241       //emit_writebyte_indexed(tl,(int)rdram-0x80000000,temp);
3242       emit_writebyte_indexed_tlb(tl,x,a,map,a);
3243     }
3244     type=STOREB_STUB;
3245   }
3246   if (opcode[i]==0x29) { // SH
3247     if(!c||memtarget) {
3248       int x=0,a=temp;
3249 #ifdef BIG_ENDIAN_MIPS
3250       if(!c) emit_xorimm(addr,2,temp);
3251       else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
3252 #else
3253       if(!c) a=addr;
3254 #endif
3255       if(faststore_reg_override) a=faststore_reg_override;
3256       //#ifdef
3257       //emit_writehword_indexed_tlb(tl,x,temp,map,temp);
3258       //#else
3259       if(map>=0) {
3260         gen_tlb_addr_w(a,map);
3261         emit_writehword_indexed(tl,x,a);
3262       }else
3263         emit_writehword_indexed(tl,(int)rdram-0x80000000+x,a);
3264     }
3265     type=STOREH_STUB;
3266   }
3267   if (opcode[i]==0x2B) { // SW
3268     if(!c||memtarget) {
3269       int a=addr;
3270       if(faststore_reg_override) a=faststore_reg_override;
3271       //emit_writeword_indexed(tl,(int)rdram-0x80000000,addr);
3272       emit_writeword_indexed_tlb(tl,0,a,map,temp);
3273     }
3274     type=STOREW_STUB;
3275   }
3276   if (opcode[i]==0x3F) { // SD
3277     if(!c||memtarget) {
3278       int a=addr;
3279       if(faststore_reg_override) a=faststore_reg_override;
3280       if(rs2[i]) {
3281         assert(th>=0);
3282         //emit_writeword_indexed(th,(int)rdram-0x80000000,addr);
3283         //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,addr);
3284         emit_writedword_indexed_tlb(th,tl,0,a,map,temp);
3285       }else{
3286         // Store zero
3287         //emit_writeword_indexed(tl,(int)rdram-0x80000000,temp);
3288         //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,temp);
3289         emit_writedword_indexed_tlb(tl,tl,0,a,map,temp);
3290       }
3291     }
3292     type=STORED_STUB;
3293   }
3294 #ifdef PCSX
3295   if(jaddr) {
3296     // PCSX store handlers don't check invcode again
3297     reglist|=1<<addr;
3298     add_stub(type,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3299     jaddr=0;
3300   }
3301 #endif
3302   if(!using_tlb&&!(i_regs->waswritten&(1<<rs1[i]))) {
3303     if(!c||memtarget) {
3304       #ifdef DESTRUCTIVE_SHIFT
3305       // The x86 shift operation is 'destructive'; it overwrites the
3306       // source register, so we need to make a copy first and use that.
3307       addr=temp;
3308       #endif
3309       #if defined(HOST_IMM8)
3310       int ir=get_reg(i_regs->regmap,INVCP);
3311       assert(ir>=0);
3312       emit_cmpmem_indexedsr12_reg(ir,addr,1);
3313       #else
3314       emit_cmpmem_indexedsr12_imm((int)invalid_code,addr,1);
3315       #endif
3316       #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3317       emit_callne(invalidate_addr_reg[addr]);
3318       #else
3319       jaddr2=(int)out;
3320       emit_jne(0);
3321       add_stub(INVCODE_STUB,jaddr2,(int)out,reglist|(1<<HOST_CCREG),addr,0,0,0);
3322       #endif
3323     }
3324   }
3325   if(jaddr) {
3326     add_stub(type,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3327   } else if(c&&!memtarget) {
3328     inline_writestub(type,i,constmap[i][s]+offset,i_regs->regmap,rs2[i],ccadj[i],reglist);
3329   }
3330   //if(opcode[i]==0x2B || opcode[i]==0x3F)
3331   //if(opcode[i]==0x2B || opcode[i]==0x28)
3332   //if(opcode[i]==0x2B || opcode[i]==0x29)
3333   //if(opcode[i]==0x2B)
3334   /*if(opcode[i]==0x2B || opcode[i]==0x28 || opcode[i]==0x29 || opcode[i]==0x3F)
3335   {
3336     #ifdef __i386__
3337     emit_pusha();
3338     #endif
3339     #ifdef __arm__
3340     save_regs(0x100f);
3341     #endif
3342         emit_readword((int)&last_count,ECX);
3343         #ifdef __i386__
3344         if(get_reg(i_regs->regmap,CCREG)<0)
3345           emit_loadreg(CCREG,HOST_CCREG);
3346         emit_add(HOST_CCREG,ECX,HOST_CCREG);
3347         emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3348         emit_writeword(HOST_CCREG,(int)&Count);
3349         #endif
3350         #ifdef __arm__
3351         if(get_reg(i_regs->regmap,CCREG)<0)
3352           emit_loadreg(CCREG,0);
3353         else
3354           emit_mov(HOST_CCREG,0);
3355         emit_add(0,ECX,0);
3356         emit_addimm(0,2*ccadj[i],0);
3357         emit_writeword(0,(int)&Count);
3358         #endif
3359     emit_call((int)memdebug);
3360     #ifdef __i386__
3361     emit_popa();
3362     #endif
3363     #ifdef __arm__
3364     restore_regs(0x100f);
3365     #endif
3366   }/**/
3367 }
3368
3369 void storelr_assemble(int i,struct regstat *i_regs)
3370 {
3371   int s,th,tl;
3372   int temp;
3373   int temp2;
3374   int offset;
3375   int jaddr=0,jaddr2;
3376   int case1,case2,case3;
3377   int done0,done1,done2;
3378   int memtarget=0,c=0;
3379   int agr=AGEN1+(i&1);
3380   u_int hr,reglist=0;
3381   th=get_reg(i_regs->regmap,rs2[i]|64);
3382   tl=get_reg(i_regs->regmap,rs2[i]);
3383   s=get_reg(i_regs->regmap,rs1[i]);
3384   temp=get_reg(i_regs->regmap,agr);
3385   if(temp<0) temp=get_reg(i_regs->regmap,-1);
3386   offset=imm[i];
3387   if(s>=0) {
3388     c=(i_regs->isconst>>s)&1;
3389     if(c) {
3390       memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
3391       if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
3392     }
3393   }
3394   assert(tl>=0);
3395   for(hr=0;hr<HOST_REGS;hr++) {
3396     if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3397   }
3398   assert(temp>=0);
3399   if(!using_tlb) {
3400     if(!c) {
3401       emit_cmpimm(s<0||offset?temp:s,RAM_SIZE);
3402       if(!offset&&s!=temp) emit_mov(s,temp);
3403       jaddr=(int)out;
3404       emit_jno(0);
3405     }
3406     else
3407     {
3408       if(!memtarget||!rs1[i]) {
3409         jaddr=(int)out;
3410         emit_jmp(0);
3411       }
3412     }
3413     #ifdef RAM_OFFSET
3414     int map=get_reg(i_regs->regmap,ROREG);
3415     if(map<0) emit_loadreg(ROREG,map=HOST_TEMPREG);
3416     gen_tlb_addr_w(temp,map);
3417     #else
3418     if((u_int)rdram!=0x80000000)
3419       emit_addimm_no_flags((u_int)rdram-(u_int)0x80000000,temp);
3420     #endif
3421   }else{ // using tlb
3422     int map=get_reg(i_regs->regmap,TLREG);
3423     assert(map>=0);
3424     reglist&=~(1<<map);
3425     map=do_tlb_w(c||s<0||offset?temp:s,temp,map,0,c,constmap[i][s]+offset);
3426     if(!c&&!offset&&s>=0) emit_mov(s,temp);
3427     do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr);
3428     if(!jaddr&&!memtarget) {
3429       jaddr=(int)out;
3430       emit_jmp(0);
3431     }
3432     gen_tlb_addr_w(temp,map);
3433   }
3434
3435   if (opcode[i]==0x2C||opcode[i]==0x2D) { // SDL/SDR
3436     temp2=get_reg(i_regs->regmap,FTEMP);
3437     if(!rs2[i]) temp2=th=tl;
3438   }
3439
3440 #ifndef BIG_ENDIAN_MIPS
3441     emit_xorimm(temp,3,temp);
3442 #endif
3443   emit_testimm(temp,2);
3444   case2=(int)out;
3445   emit_jne(0);
3446   emit_testimm(temp,1);
3447   case1=(int)out;
3448   emit_jne(0);
3449   // 0
3450   if (opcode[i]==0x2A) { // SWL
3451     emit_writeword_indexed(tl,0,temp);
3452   }
3453   if (opcode[i]==0x2E) { // SWR
3454     emit_writebyte_indexed(tl,3,temp);
3455   }
3456   if (opcode[i]==0x2C) { // SDL
3457     emit_writeword_indexed(th,0,temp);
3458     if(rs2[i]) emit_mov(tl,temp2);
3459   }
3460   if (opcode[i]==0x2D) { // SDR
3461     emit_writebyte_indexed(tl,3,temp);
3462     if(rs2[i]) emit_shldimm(th,tl,24,temp2);
3463   }
3464   done0=(int)out;
3465   emit_jmp(0);
3466   // 1
3467   set_jump_target(case1,(int)out);
3468   if (opcode[i]==0x2A) { // SWL
3469     // Write 3 msb into three least significant bytes
3470     if(rs2[i]) emit_rorimm(tl,8,tl);
3471     emit_writehword_indexed(tl,-1,temp);
3472     if(rs2[i]) emit_rorimm(tl,16,tl);
3473     emit_writebyte_indexed(tl,1,temp);
3474     if(rs2[i]) emit_rorimm(tl,8,tl);
3475   }
3476   if (opcode[i]==0x2E) { // SWR
3477     // Write two lsb into two most significant bytes
3478     emit_writehword_indexed(tl,1,temp);
3479   }
3480   if (opcode[i]==0x2C) { // SDL
3481     if(rs2[i]) emit_shrdimm(tl,th,8,temp2);
3482     // Write 3 msb into three least significant bytes
3483     if(rs2[i]) emit_rorimm(th,8,th);
3484     emit_writehword_indexed(th,-1,temp);
3485     if(rs2[i]) emit_rorimm(th,16,th);
3486     emit_writebyte_indexed(th,1,temp);
3487     if(rs2[i]) emit_rorimm(th,8,th);
3488   }
3489   if (opcode[i]==0x2D) { // SDR
3490     if(rs2[i]) emit_shldimm(th,tl,16,temp2);
3491     // Write two lsb into two most significant bytes
3492     emit_writehword_indexed(tl,1,temp);
3493   }
3494   done1=(int)out;
3495   emit_jmp(0);
3496   // 2
3497   set_jump_target(case2,(int)out);
3498   emit_testimm(temp,1);
3499   case3=(int)out;
3500   emit_jne(0);
3501   if (opcode[i]==0x2A) { // SWL
3502     // Write two msb into two least significant bytes
3503     if(rs2[i]) emit_rorimm(tl,16,tl);
3504     emit_writehword_indexed(tl,-2,temp);
3505     if(rs2[i]) emit_rorimm(tl,16,tl);
3506   }
3507   if (opcode[i]==0x2E) { // SWR
3508     // Write 3 lsb into three most significant bytes
3509     emit_writebyte_indexed(tl,-1,temp);
3510     if(rs2[i]) emit_rorimm(tl,8,tl);
3511     emit_writehword_indexed(tl,0,temp);
3512     if(rs2[i]) emit_rorimm(tl,24,tl);
3513   }
3514   if (opcode[i]==0x2C) { // SDL
3515     if(rs2[i]) emit_shrdimm(tl,th,16,temp2);
3516     // Write two msb into two least significant bytes
3517     if(rs2[i]) emit_rorimm(th,16,th);
3518     emit_writehword_indexed(th,-2,temp);
3519     if(rs2[i]) emit_rorimm(th,16,th);
3520   }
3521   if (opcode[i]==0x2D) { // SDR
3522     if(rs2[i]) emit_shldimm(th,tl,8,temp2);
3523     // Write 3 lsb into three most significant bytes
3524     emit_writebyte_indexed(tl,-1,temp);
3525     if(rs2[i]) emit_rorimm(tl,8,tl);
3526     emit_writehword_indexed(tl,0,temp);
3527     if(rs2[i]) emit_rorimm(tl,24,tl);
3528   }
3529   done2=(int)out;
3530   emit_jmp(0);
3531   // 3
3532   set_jump_target(case3,(int)out);
3533   if (opcode[i]==0x2A) { // SWL
3534     // Write msb into least significant byte
3535     if(rs2[i]) emit_rorimm(tl,24,tl);
3536     emit_writebyte_indexed(tl,-3,temp);
3537     if(rs2[i]) emit_rorimm(tl,8,tl);
3538   }
3539   if (opcode[i]==0x2E) { // SWR
3540     // Write entire word
3541     emit_writeword_indexed(tl,-3,temp);
3542   }
3543   if (opcode[i]==0x2C) { // SDL
3544     if(rs2[i]) emit_shrdimm(tl,th,24,temp2);
3545     // Write msb into least significant byte
3546     if(rs2[i]) emit_rorimm(th,24,th);
3547     emit_writebyte_indexed(th,-3,temp);
3548     if(rs2[i]) emit_rorimm(th,8,th);
3549   }
3550   if (opcode[i]==0x2D) { // SDR
3551     if(rs2[i]) emit_mov(th,temp2);
3552     // Write entire word
3553     emit_writeword_indexed(tl,-3,temp);
3554   }
3555   set_jump_target(done0,(int)out);
3556   set_jump_target(done1,(int)out);
3557   set_jump_target(done2,(int)out);
3558   if (opcode[i]==0x2C) { // SDL
3559     emit_testimm(temp,4);
3560     done0=(int)out;
3561     emit_jne(0);
3562     emit_andimm(temp,~3,temp);
3563     emit_writeword_indexed(temp2,4,temp);
3564     set_jump_target(done0,(int)out);
3565   }
3566   if (opcode[i]==0x2D) { // SDR
3567     emit_testimm(temp,4);
3568     done0=(int)out;
3569     emit_jeq(0);
3570     emit_andimm(temp,~3,temp);
3571     emit_writeword_indexed(temp2,-4,temp);
3572     set_jump_target(done0,(int)out);
3573   }
3574   if(!c||!memtarget)
3575     add_stub(STORELR_STUB,jaddr,(int)out,i,(int)i_regs,temp,ccadj[i],reglist);
3576   if(!using_tlb&&!(i_regs->waswritten&(1<<rs1[i]))) {
3577     #ifdef RAM_OFFSET
3578     int map=get_reg(i_regs->regmap,ROREG);
3579     if(map<0) map=HOST_TEMPREG;
3580     gen_orig_addr_w(temp,map);
3581     #else
3582     emit_addimm_no_flags((u_int)0x80000000-(u_int)rdram,temp);
3583     #endif
3584     #if defined(HOST_IMM8)
3585     int ir=get_reg(i_regs->regmap,INVCP);
3586     assert(ir>=0);
3587     emit_cmpmem_indexedsr12_reg(ir,temp,1);
3588     #else
3589     emit_cmpmem_indexedsr12_imm((int)invalid_code,temp,1);
3590     #endif
3591     #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3592     emit_callne(invalidate_addr_reg[temp]);
3593     #else
3594     jaddr2=(int)out;
3595     emit_jne(0);
3596     add_stub(INVCODE_STUB,jaddr2,(int)out,reglist|(1<<HOST_CCREG),temp,0,0,0);
3597     #endif
3598   }
3599   /*
3600     emit_pusha();
3601     //save_regs(0x100f);
3602         emit_readword((int)&last_count,ECX);
3603         if(get_reg(i_regs->regmap,CCREG)<0)
3604           emit_loadreg(CCREG,HOST_CCREG);
3605         emit_add(HOST_CCREG,ECX,HOST_CCREG);
3606         emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3607         emit_writeword(HOST_CCREG,(int)&Count);
3608     emit_call((int)memdebug);
3609     emit_popa();
3610     //restore_regs(0x100f);
3611   /**/
3612 }
3613
3614 void c1ls_assemble(int i,struct regstat *i_regs)
3615 {
3616 #ifndef DISABLE_COP1
3617   int s,th,tl;
3618   int temp,ar;
3619   int map=-1;
3620   int offset;
3621   int c=0;
3622   int jaddr,jaddr2=0,jaddr3,type;
3623   int agr=AGEN1+(i&1);
3624   u_int hr,reglist=0;
3625   th=get_reg(i_regs->regmap,FTEMP|64);
3626   tl=get_reg(i_regs->regmap,FTEMP);
3627   s=get_reg(i_regs->regmap,rs1[i]);
3628   temp=get_reg(i_regs->regmap,agr);
3629   if(temp<0) temp=get_reg(i_regs->regmap,-1);
3630   offset=imm[i];
3631   assert(tl>=0);
3632   assert(rs1[i]>0);
3633   assert(temp>=0);
3634   for(hr=0;hr<HOST_REGS;hr++) {
3635     if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3636   }
3637   if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
3638   if (opcode[i]==0x31||opcode[i]==0x35) // LWC1/LDC1
3639   {
3640     // Loads use a temporary register which we need to save
3641     reglist|=1<<temp;
3642   }
3643   if (opcode[i]==0x39||opcode[i]==0x3D) // SWC1/SDC1
3644     ar=temp;
3645   else // LWC1/LDC1
3646     ar=tl;
3647   //if(s<0) emit_loadreg(rs1[i],ar); //address_generation does this now
3648   //else c=(i_regs->wasconst>>s)&1;
3649   if(s>=0) c=(i_regs->wasconst>>s)&1;
3650   // Check cop1 unusable
3651   if(!cop1_usable) {
3652     signed char rs=get_reg(i_regs->regmap,CSREG);
3653     assert(rs>=0);
3654     emit_testimm(rs,0x20000000);
3655     jaddr=(int)out;
3656     emit_jeq(0);
3657     add_stub(FP_STUB,jaddr,(int)out,i,rs,(int)i_regs,is_delayslot,0);
3658     cop1_usable=1;
3659   }
3660   if (opcode[i]==0x39) { // SWC1 (get float address)
3661     emit_readword((int)&reg_cop1_simple[(source[i]>>16)&0x1f],tl);
3662   }
3663   if (opcode[i]==0x3D) { // SDC1 (get double address)
3664     emit_readword((int)&reg_cop1_double[(source[i]>>16)&0x1f],tl);
3665   }
3666   // Generate address + offset
3667   if(!using_tlb) {
3668     if(!c)
3669       emit_cmpimm(offset||c||s<0?ar:s,RAM_SIZE);
3670   }
3671   else
3672   {
3673     map=get_reg(i_regs->regmap,TLREG);
3674     assert(map>=0);
3675     reglist&=~(1<<map);
3676     if (opcode[i]==0x31||opcode[i]==0x35) { // LWC1/LDC1
3677       map=do_tlb_r(offset||c||s<0?ar:s,ar,map,0,-1,-1,c,constmap[i][s]+offset);
3678     }
3679     if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3680       map=do_tlb_w(offset||c||s<0?ar:s,ar,map,0,c,constmap[i][s]+offset);
3681     }
3682   }
3683   if (opcode[i]==0x39) { // SWC1 (read float)
3684     emit_readword_indexed(0,tl,tl);
3685   }
3686   if (opcode[i]==0x3D) { // SDC1 (read double)
3687     emit_readword_indexed(4,tl,th);
3688     emit_readword_indexed(0,tl,tl);
3689   }
3690   if (opcode[i]==0x31) { // LWC1 (get target address)
3691     emit_readword((int)&reg_cop1_simple[(source[i]>>16)&0x1f],temp);
3692   }
3693   if (opcode[i]==0x35) { // LDC1 (get target address)
3694     emit_readword((int)&reg_cop1_double[(source[i]>>16)&0x1f],temp);
3695   }
3696   if(!using_tlb) {
3697     if(!c) {
3698       jaddr2=(int)out;
3699       emit_jno(0);
3700     }
3701     else if(((signed int)(constmap[i][s]+offset))>=(signed int)0x80000000+RAM_SIZE) {
3702       jaddr2=(int)out;
3703       emit_jmp(0); // inline_readstub/inline_writestub?  Very rare case
3704     }
3705     #ifdef DESTRUCTIVE_SHIFT
3706     if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3707       if(!offset&&!c&&s>=0) emit_mov(s,ar);
3708     }
3709     #endif
3710   }else{
3711     if (opcode[i]==0x31||opcode[i]==0x35) { // LWC1/LDC1
3712       do_tlb_r_branch(map,c,constmap[i][s]+offset,&jaddr2);
3713     }
3714     if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3715       do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr2);
3716     }
3717   }
3718   if (opcode[i]==0x31) { // LWC1
3719     //if(s>=0&&!c&&!offset) emit_mov(s,tl);
3720     //gen_tlb_addr_r(ar,map);
3721     //emit_readword_indexed((int)rdram-0x80000000,tl,tl);
3722     #ifdef HOST_IMM_ADDR32
3723     if(c) emit_readword_tlb(constmap[i][s]+offset,map,tl);
3724     else
3725     #endif
3726     emit_readword_indexed_tlb(0,offset||c||s<0?tl:s,map,tl);
3727     type=LOADW_STUB;
3728   }
3729   if (opcode[i]==0x35) { // LDC1
3730     assert(th>=0);
3731     //if(s>=0&&!c&&!offset) emit_mov(s,tl);
3732     //gen_tlb_addr_r(ar,map);
3733     //emit_readword_indexed((int)rdram-0x80000000,tl,th);
3734     //emit_readword_indexed((int)rdram-0x7FFFFFFC,tl,tl);
3735     #ifdef HOST_IMM_ADDR32
3736     if(c) emit_readdword_tlb(constmap[i][s]+offset,map,th,tl);
3737     else
3738     #endif
3739     emit_readdword_indexed_tlb(0,offset||c||s<0?tl:s,map,th,tl);
3740     type=LOADD_STUB;
3741   }
3742   if (opcode[i]==0x39) { // SWC1
3743     //emit_writeword_indexed(tl,(int)rdram-0x80000000,temp);
3744     emit_writeword_indexed_tlb(tl,0,offset||c||s<0?temp:s,map,temp);
3745     type=STOREW_STUB;
3746   }
3747   if (opcode[i]==0x3D) { // SDC1
3748     assert(th>=0);
3749     //emit_writeword_indexed(th,(int)rdram-0x80000000,temp);
3750     //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,temp);
3751     emit_writedword_indexed_tlb(th,tl,0,offset||c||s<0?temp:s,map,temp);
3752     type=STORED_STUB;
3753   }
3754   if(!using_tlb&&!(i_regs->waswritten&(1<<rs1[i]))) {
3755     if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3756       #ifndef DESTRUCTIVE_SHIFT
3757       temp=offset||c||s<0?ar:s;
3758       #endif
3759       #if defined(HOST_IMM8)
3760       int ir=get_reg(i_regs->regmap,INVCP);
3761       assert(ir>=0);
3762       emit_cmpmem_indexedsr12_reg(ir,temp,1);
3763       #else
3764       emit_cmpmem_indexedsr12_imm((int)invalid_code,temp,1);
3765       #endif
3766       #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3767       emit_callne(invalidate_addr_reg[temp]);
3768       #else
3769       jaddr3=(int)out;
3770       emit_jne(0);
3771       add_stub(INVCODE_STUB,jaddr3,(int)out,reglist|(1<<HOST_CCREG),temp,0,0,0);
3772       #endif
3773     }
3774   }
3775   if(jaddr2) add_stub(type,jaddr2,(int)out,i,offset||c||s<0?ar:s,(int)i_regs,ccadj[i],reglist);
3776   if (opcode[i]==0x31) { // LWC1 (write float)
3777     emit_writeword_indexed(tl,0,temp);
3778   }
3779   if (opcode[i]==0x35) { // LDC1 (write double)
3780     emit_writeword_indexed(th,4,temp);
3781     emit_writeword_indexed(tl,0,temp);
3782   }
3783   //if(opcode[i]==0x39)
3784   /*if(opcode[i]==0x39||opcode[i]==0x31)
3785   {
3786     emit_pusha();
3787         emit_readword((int)&last_count,ECX);
3788         if(get_reg(i_regs->regmap,CCREG)<0)
3789           emit_loadreg(CCREG,HOST_CCREG);
3790         emit_add(HOST_CCREG,ECX,HOST_CCREG);
3791         emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3792         emit_writeword(HOST_CCREG,(int)&Count);
3793     emit_call((int)memdebug);
3794     emit_popa();
3795   }/**/
3796 #else
3797   cop1_unusable(i, i_regs);
3798 #endif
3799 }
3800
3801 void c2ls_assemble(int i,struct regstat *i_regs)
3802 {
3803   int s,tl;
3804   int ar;
3805   int offset;
3806   int memtarget=0,c=0;
3807   int jaddr2=0,jaddr3,type;
3808   int agr=AGEN1+(i&1);
3809   int fastio_reg_override=0;
3810   u_int hr,reglist=0;
3811   u_int copr=(source[i]>>16)&0x1f;
3812   s=get_reg(i_regs->regmap,rs1[i]);
3813   tl=get_reg(i_regs->regmap,FTEMP);
3814   offset=imm[i];
3815   assert(rs1[i]>0);
3816   assert(tl>=0);
3817   assert(!using_tlb);
3818
3819   for(hr=0;hr<HOST_REGS;hr++) {
3820     if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3821   }
3822   if(i_regs->regmap[HOST_CCREG]==CCREG)
3823     reglist&=~(1<<HOST_CCREG);
3824
3825   // get the address
3826   if (opcode[i]==0x3a) { // SWC2
3827     ar=get_reg(i_regs->regmap,agr);
3828     if(ar<0) ar=get_reg(i_regs->regmap,-1);
3829     reglist|=1<<ar;
3830   } else { // LWC2
3831     ar=tl;
3832   }
3833   if(s>=0) c=(i_regs->wasconst>>s)&1;
3834   memtarget=c&&(((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE);
3835   if (!offset&&!c&&s>=0) ar=s;
3836   assert(ar>=0);
3837
3838   if (opcode[i]==0x3a) { // SWC2
3839     cop2_get_dreg(copr,tl,HOST_TEMPREG);
3840     type=STOREW_STUB;
3841   }
3842   else
3843     type=LOADW_STUB;
3844
3845   if(c&&!memtarget) {
3846     jaddr2=(int)out;
3847     emit_jmp(0); // inline_readstub/inline_writestub?
3848   }
3849   else {
3850     if(!c) {
3851       jaddr2=emit_fastpath_cmp_jump(i,ar,&fastio_reg_override);
3852     }
3853     if (opcode[i]==0x32) { // LWC2
3854       #ifdef HOST_IMM_ADDR32
3855       if(c) emit_readword_tlb(constmap[i][s]+offset,-1,tl);
3856       else
3857       #endif
3858       int a=ar;
3859       if(fastio_reg_override) a=fastio_reg_override;
3860       emit_readword_indexed(0,a,tl);
3861     }
3862     if (opcode[i]==0x3a) { // SWC2
3863       #ifdef DESTRUCTIVE_SHIFT
3864       if(!offset&&!c&&s>=0) emit_mov(s,ar);
3865       #endif
3866       int a=ar;
3867       if(fastio_reg_override) a=fastio_reg_override;
3868       emit_writeword_indexed(tl,0,a);
3869     }
3870   }
3871   if(jaddr2)
3872     add_stub(type,jaddr2,(int)out,i,ar,(int)i_regs,ccadj[i],reglist);
3873   if (!(i_regs->waswritten&(1<<rs1[i]))&&opcode[i]==0x3a) { // SWC2
3874 #if defined(HOST_IMM8)
3875     int ir=get_reg(i_regs->regmap,INVCP);
3876     assert(ir>=0);
3877     emit_cmpmem_indexedsr12_reg(ir,ar,1);
3878 #else
3879     emit_cmpmem_indexedsr12_imm((int)invalid_code,ar,1);
3880 #endif
3881     #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3882     emit_callne(invalidate_addr_reg[ar]);
3883     #else
3884     jaddr3=(int)out;
3885     emit_jne(0);
3886     add_stub(INVCODE_STUB,jaddr3,(int)out,reglist|(1<<HOST_CCREG),ar,0,0,0);
3887     #endif
3888   }
3889   if (opcode[i]==0x32) { // LWC2
3890     cop2_put_dreg(copr,tl,HOST_TEMPREG);
3891   }
3892 }
3893
3894 #ifndef multdiv_assemble
3895 void multdiv_assemble(int i,struct regstat *i_regs)
3896 {
3897   printf("Need multdiv_assemble for this architecture.\n");
3898   exit(1);
3899 }
3900 #endif
3901
3902 void mov_assemble(int i,struct regstat *i_regs)
3903 {
3904   //if(opcode2[i]==0x10||opcode2[i]==0x12) { // MFHI/MFLO
3905   //if(opcode2[i]==0x11||opcode2[i]==0x13) { // MTHI/MTLO
3906   if(rt1[i]) {
3907     signed char sh,sl,th,tl;
3908     th=get_reg(i_regs->regmap,rt1[i]|64);
3909     tl=get_reg(i_regs->regmap,rt1[i]);
3910     //assert(tl>=0);
3911     if(tl>=0) {
3912       sh=get_reg(i_regs->regmap,rs1[i]|64);
3913       sl=get_reg(i_regs->regmap,rs1[i]);
3914       if(sl>=0) emit_mov(sl,tl);
3915       else emit_loadreg(rs1[i],tl);
3916       if(th>=0) {
3917         if(sh>=0) emit_mov(sh,th);
3918         else emit_loadreg(rs1[i]|64,th);
3919       }
3920     }
3921   }
3922 }
3923
3924 #ifndef fconv_assemble
3925 void fconv_assemble(int i,struct regstat *i_regs)
3926 {
3927   printf("Need fconv_assemble for this architecture.\n");
3928   exit(1);
3929 }
3930 #endif
3931
3932 #if 0
3933 void float_assemble(int i,struct regstat *i_regs)
3934 {
3935   printf("Need float_assemble for this architecture.\n");
3936   exit(1);
3937 }
3938 #endif
3939
3940 void syscall_assemble(int i,struct regstat *i_regs)
3941 {
3942   signed char ccreg=get_reg(i_regs->regmap,CCREG);
3943   assert(ccreg==HOST_CCREG);
3944   assert(!is_delayslot);
3945   emit_movimm(start+i*4,EAX); // Get PC
3946   emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i]),HOST_CCREG); // CHECK: is this right?  There should probably be an extra cycle...
3947   emit_jmp((int)jump_syscall_hle); // XXX
3948 }
3949
3950 void hlecall_assemble(int i,struct regstat *i_regs)
3951 {
3952   signed char ccreg=get_reg(i_regs->regmap,CCREG);
3953   assert(ccreg==HOST_CCREG);
3954   assert(!is_delayslot);
3955   emit_movimm(start+i*4+4,0); // Get PC
3956   emit_movimm((int)psxHLEt[source[i]&7],1);
3957   emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i]),HOST_CCREG); // XXX
3958   emit_jmp((int)jump_hlecall);
3959 }
3960
3961 void intcall_assemble(int i,struct regstat *i_regs)
3962 {
3963   signed char ccreg=get_reg(i_regs->regmap,CCREG);
3964   assert(ccreg==HOST_CCREG);
3965   assert(!is_delayslot);
3966   emit_movimm(start+i*4,0); // Get PC
3967   emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i]),HOST_CCREG);
3968   emit_jmp((int)jump_intcall);
3969 }
3970
3971 void ds_assemble(int i,struct regstat *i_regs)
3972 {
3973   speculate_register_values(i);
3974   is_delayslot=1;
3975   switch(itype[i]) {
3976     case ALU:
3977       alu_assemble(i,i_regs);break;
3978     case IMM16:
3979       imm16_assemble(i,i_regs);break;
3980     case SHIFT:
3981       shift_assemble(i,i_regs);break;
3982     case SHIFTIMM:
3983       shiftimm_assemble(i,i_regs);break;
3984     case LOAD:
3985       load_assemble(i,i_regs);break;
3986     case LOADLR:
3987       loadlr_assemble(i,i_regs);break;
3988     case STORE:
3989       store_assemble(i,i_regs);break;
3990     case STORELR:
3991       storelr_assemble(i,i_regs);break;
3992     case COP0:
3993       cop0_assemble(i,i_regs);break;
3994     case COP1:
3995       cop1_assemble(i,i_regs);break;
3996     case C1LS:
3997       c1ls_assemble(i,i_regs);break;
3998     case COP2:
3999       cop2_assemble(i,i_regs);break;
4000     case C2LS:
4001       c2ls_assemble(i,i_regs);break;
4002     case C2OP:
4003       c2op_assemble(i,i_regs);break;
4004     case FCONV:
4005       fconv_assemble(i,i_regs);break;
4006     case FLOAT:
4007       float_assemble(i,i_regs);break;
4008     case FCOMP:
4009       fcomp_assemble(i,i_regs);break;
4010     case MULTDIV:
4011       multdiv_assemble(i,i_regs);break;
4012     case MOV:
4013       mov_assemble(i,i_regs);break;
4014     case SYSCALL:
4015     case HLECALL:
4016     case INTCALL:
4017     case SPAN:
4018     case UJUMP:
4019     case RJUMP:
4020     case CJUMP:
4021     case SJUMP:
4022     case FJUMP:
4023       printf("Jump in the delay slot.  This is probably a bug.\n");
4024   }
4025   is_delayslot=0;
4026 }
4027
4028 // Is the branch target a valid internal jump?
4029 int internal_branch(uint64_t i_is32,int addr)
4030 {
4031   if(addr&1) return 0; // Indirect (register) jump
4032   if(addr>=start && addr<start+slen*4-4)
4033   {
4034     int t=(addr-start)>>2;
4035     // Delay slots are not valid branch targets
4036     //if(t>0&&(itype[t-1]==RJUMP||itype[t-1]==UJUMP||itype[t-1]==CJUMP||itype[t-1]==SJUMP||itype[t-1]==FJUMP)) return 0;
4037     // 64 -> 32 bit transition requires a recompile
4038     /*if(is32[t]&~unneeded_reg_upper[t]&~i_is32)
4039     {
4040       if(requires_32bit[t]&~i_is32) printf("optimizable: no\n");
4041       else printf("optimizable: yes\n");
4042     }*/
4043     //if(is32[t]&~unneeded_reg_upper[t]&~i_is32) return 0;
4044 #ifndef FORCE32
4045     if(requires_32bit[t]&~i_is32) return 0;
4046     else
4047 #endif
4048       return 1;
4049   }
4050   return 0;
4051 }
4052
4053 #ifndef wb_invalidate
4054 void wb_invalidate(signed char pre[],signed char entry[],uint64_t dirty,uint64_t is32,
4055   uint64_t u,uint64_t uu)
4056 {
4057   int hr;
4058   for(hr=0;hr<HOST_REGS;hr++) {
4059     if(hr!=EXCLUDE_REG) {
4060       if(pre[hr]!=entry[hr]) {
4061         if(pre[hr]>=0) {
4062           if((dirty>>hr)&1) {
4063             if(get_reg(entry,pre[hr])<0) {
4064               if(pre[hr]<64) {
4065                 if(!((u>>pre[hr])&1)) {
4066                   emit_storereg(pre[hr],hr);
4067                   if( ((is32>>pre[hr])&1) && !((uu>>pre[hr])&1) ) {
4068                     emit_sarimm(hr,31,hr);
4069                     emit_storereg(pre[hr]|64,hr);
4070                   }
4071                 }
4072               }else{
4073                 if(!((uu>>(pre[hr]&63))&1) && !((is32>>(pre[hr]&63))&1)) {
4074                   emit_storereg(pre[hr],hr);
4075                 }
4076               }
4077             }
4078           }
4079         }
4080       }
4081     }
4082   }
4083   // Move from one register to another (no writeback)
4084   for(hr=0;hr<HOST_REGS;hr++) {
4085     if(hr!=EXCLUDE_REG) {
4086       if(pre[hr]!=entry[hr]) {
4087         if(pre[hr]>=0&&(pre[hr]&63)<TEMPREG) {
4088           int nr;
4089           if((nr=get_reg(entry,pre[hr]))>=0) {
4090             emit_mov(hr,nr);
4091           }
4092         }
4093       }
4094     }
4095   }
4096 }
4097 #endif
4098
4099 // Load the specified registers
4100 // This only loads the registers given as arguments because
4101 // we don't want to load things that will be overwritten
4102 void load_regs(signed char entry[],signed char regmap[],int is32,int rs1,int rs2)
4103 {
4104   int hr;
4105   // Load 32-bit regs
4106   for(hr=0;hr<HOST_REGS;hr++) {
4107     if(hr!=EXCLUDE_REG&&regmap[hr]>=0) {
4108       if(entry[hr]!=regmap[hr]) {
4109         if(regmap[hr]==rs1||regmap[hr]==rs2)
4110         {
4111           if(regmap[hr]==0) {
4112             emit_zeroreg(hr);
4113           }
4114           else
4115           {
4116             emit_loadreg(regmap[hr],hr);
4117           }
4118         }
4119       }
4120     }
4121   }
4122   //Load 64-bit regs
4123   for(hr=0;hr<HOST_REGS;hr++) {
4124     if(hr!=EXCLUDE_REG&&regmap[hr]>=0) {
4125       if(entry[hr]!=regmap[hr]) {
4126         if(regmap[hr]-64==rs1||regmap[hr]-64==rs2)
4127         {
4128           assert(regmap[hr]!=64);
4129           if((is32>>(regmap[hr]&63))&1) {
4130             int lr=get_reg(regmap,regmap[hr]-64);
4131             if(lr>=0)
4132               emit_sarimm(lr,31,hr);
4133             else
4134               emit_loadreg(regmap[hr],hr);
4135           }
4136           else
4137           {
4138             emit_loadreg(regmap[hr],hr);
4139           }
4140         }
4141       }
4142     }
4143   }
4144 }
4145
4146 // Load registers prior to the start of a loop
4147 // so that they are not loaded within the loop
4148 static void loop_preload(signed char pre[],signed char entry[])
4149 {
4150   int hr;
4151   for(hr=0;hr<HOST_REGS;hr++) {
4152     if(hr!=EXCLUDE_REG) {
4153       if(pre[hr]!=entry[hr]) {
4154         if(entry[hr]>=0) {
4155           if(get_reg(pre,entry[hr])<0) {
4156             assem_debug("loop preload:\n");
4157             //printf("loop preload: %d\n",hr);
4158             if(entry[hr]==0) {
4159               emit_zeroreg(hr);
4160             }
4161             else if(entry[hr]<TEMPREG)
4162             {
4163               emit_loadreg(entry[hr],hr);
4164             }
4165             else if(entry[hr]-64<TEMPREG)
4166             {
4167               emit_loadreg(entry[hr],hr);
4168             }
4169           }
4170         }
4171       }
4172     }
4173   }
4174 }
4175
4176 // Generate address for load/store instruction
4177 // goes to AGEN for writes, FTEMP for LOADLR and cop1/2 loads
4178 void address_generation(int i,struct regstat *i_regs,signed char entry[])
4179 {
4180   if(itype[i]==LOAD||itype[i]==LOADLR||itype[i]==STORE||itype[i]==STORELR||itype[i]==C1LS||itype[i]==C2LS) {
4181     int ra=-1;
4182     int agr=AGEN1+(i&1);
4183     int mgr=MGEN1+(i&1);
4184     if(itype[i]==LOAD) {
4185       ra=get_reg(i_regs->regmap,rt1[i]);
4186       if(ra<0) ra=get_reg(i_regs->regmap,-1);
4187       assert(ra>=0);
4188     }
4189     if(itype[i]==LOADLR) {
4190       ra=get_reg(i_regs->regmap,FTEMP);
4191     }
4192     if(itype[i]==STORE||itype[i]==STORELR) {
4193       ra=get_reg(i_regs->regmap,agr);
4194       if(ra<0) ra=get_reg(i_regs->regmap,-1);
4195     }
4196     if(itype[i]==C1LS||itype[i]==C2LS) {
4197       if ((opcode[i]&0x3b)==0x31||(opcode[i]&0x3b)==0x32) // LWC1/LDC1/LWC2/LDC2
4198         ra=get_reg(i_regs->regmap,FTEMP);
4199       else { // SWC1/SDC1/SWC2/SDC2
4200         ra=get_reg(i_regs->regmap,agr);
4201         if(ra<0) ra=get_reg(i_regs->regmap,-1);
4202       }
4203     }
4204     int rs=get_reg(i_regs->regmap,rs1[i]);
4205     int rm=get_reg(i_regs->regmap,TLREG);
4206     if(ra>=0) {
4207       int offset=imm[i];
4208       int c=(i_regs->wasconst>>rs)&1;
4209       if(rs1[i]==0) {
4210         // Using r0 as a base address
4211         /*if(rm>=0) {
4212           if(!entry||entry[rm]!=mgr) {
4213             generate_map_const(offset,rm);
4214           } // else did it in the previous cycle
4215         }*/
4216         if(!entry||entry[ra]!=agr) {
4217           if (opcode[i]==0x22||opcode[i]==0x26) {
4218             emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR
4219           }else if (opcode[i]==0x1a||opcode[i]==0x1b) {
4220             emit_movimm(offset&0xFFFFFFF8,ra); // LDL/LDR
4221           }else{
4222             emit_movimm(offset,ra);
4223           }
4224         } // else did it in the previous cycle
4225       }
4226       else if(rs<0) {
4227         if(!entry||entry[ra]!=rs1[i])
4228           emit_loadreg(rs1[i],ra);
4229         //if(!entry||entry[ra]!=rs1[i])
4230         //  printf("poor load scheduling!\n");
4231       }
4232       else if(c) {
4233 #ifndef DISABLE_TLB
4234         if(rm>=0) {
4235           if(!entry||entry[rm]!=mgr) {
4236             if(itype[i]==STORE||itype[i]==STORELR||(opcode[i]&0x3b)==0x39||(opcode[i]&0x3b)==0x3a) {
4237               // Stores to memory go thru the mapper to detect self-modifying
4238               // code, loads don't.
4239               if((unsigned int)(constmap[i][rs]+offset)>=0xC0000000 ||
4240                  (unsigned int)(constmap[i][rs]+offset)<0x80000000+RAM_SIZE )
4241                 generate_map_const(constmap[i][rs]+offset,rm);
4242             }else{
4243               if((signed int)(constmap[i][rs]+offset)>=(signed int)0xC0000000)
4244                 generate_map_const(constmap[i][rs]+offset,rm);
4245             }
4246           }
4247         }
4248 #endif
4249         if(rs1[i]!=rt1[i]||itype[i]!=LOAD) {
4250           if(!entry||entry[ra]!=agr) {
4251             if (opcode[i]==0x22||opcode[i]==0x26) {
4252               emit_movimm((constmap[i][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR
4253             }else if (opcode[i]==0x1a||opcode[i]==0x1b) {
4254               emit_movimm((constmap[i][rs]+offset)&0xFFFFFFF8,ra); // LDL/LDR
4255             }else{
4256               #ifdef HOST_IMM_ADDR32
4257               if((itype[i]!=LOAD&&(opcode[i]&0x3b)!=0x31&&(opcode[i]&0x3b)!=0x32) || // LWC1/LDC1/LWC2/LDC2
4258                  (using_tlb&&((signed int)constmap[i][rs]+offset)>=(signed int)0xC0000000))
4259               #endif
4260               emit_movimm(constmap[i][rs]+offset,ra);
4261             }
4262           } // else did it in the previous cycle
4263         } // else load_consts already did it
4264       }
4265       if(offset&&!c&&rs1[i]) {
4266         if(rs>=0) {
4267           emit_addimm(rs,offset,ra);
4268         }else{
4269           emit_addimm(ra,offset,ra);
4270         }
4271       }
4272     }
4273   }
4274   // Preload constants for next instruction
4275   if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS||itype[i+1]==C2LS) {
4276     int agr,ra;
4277     #if !defined(HOST_IMM_ADDR32) && !defined(DISABLE_TLB)
4278     // Mapper entry
4279     agr=MGEN1+((i+1)&1);
4280     ra=get_reg(i_regs->regmap,agr);
4281     if(ra>=0) {
4282       int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
4283       int offset=imm[i+1];
4284       int c=(regs[i+1].wasconst>>rs)&1;
4285       if(c) {
4286         if(itype[i+1]==STORE||itype[i+1]==STORELR
4287            ||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a) { // SWC1/SDC1, SWC2/SDC2
4288           // Stores to memory go thru the mapper to detect self-modifying
4289           // code, loads don't.
4290           if((unsigned int)(constmap[i+1][rs]+offset)>=0xC0000000 ||
4291              (unsigned int)(constmap[i+1][rs]+offset)<0x80000000+RAM_SIZE )
4292             generate_map_const(constmap[i+1][rs]+offset,ra);
4293         }else{
4294           if((signed int)(constmap[i+1][rs]+offset)>=(signed int)0xC0000000)
4295             generate_map_const(constmap[i+1][rs]+offset,ra);
4296         }
4297       }
4298       /*else if(rs1[i]==0) {
4299         generate_map_const(offset,ra);
4300       }*/
4301     }
4302     #endif
4303     // Actual address
4304     agr=AGEN1+((i+1)&1);
4305     ra=get_reg(i_regs->regmap,agr);
4306     if(ra>=0) {
4307       int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
4308       int offset=imm[i+1];
4309       int c=(regs[i+1].wasconst>>rs)&1;
4310       if(c&&(rs1[i+1]!=rt1[i+1]||itype[i+1]!=LOAD)) {
4311         if (opcode[i+1]==0x22||opcode[i+1]==0x26) {
4312           emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR
4313         }else if (opcode[i+1]==0x1a||opcode[i+1]==0x1b) {
4314           emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFF8,ra); // LDL/LDR
4315         }else{
4316           #ifdef HOST_IMM_ADDR32
4317           if((itype[i+1]!=LOAD&&(opcode[i+1]&0x3b)!=0x31&&(opcode[i+1]&0x3b)!=0x32) || // LWC1/LDC1/LWC2/LDC2
4318              (using_tlb&&((signed int)constmap[i+1][rs]+offset)>=(signed int)0xC0000000))
4319           #endif
4320           emit_movimm(constmap[i+1][rs]+offset,ra);
4321         }
4322       }
4323       else if(rs1[i+1]==0) {
4324         // Using r0 as a base address
4325         if (opcode[i+1]==0x22||opcode[i+1]==0x26) {
4326           emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR
4327         }else if (opcode[i+1]==0x1a||opcode[i+1]==0x1b) {
4328           emit_movimm(offset&0xFFFFFFF8,ra); // LDL/LDR
4329         }else{
4330           emit_movimm(offset,ra);
4331         }
4332       }
4333     }
4334   }
4335 }
4336
4337 int get_final_value(int hr, int i, int *value)
4338 {
4339   int reg=regs[i].regmap[hr];
4340   while(i<slen-1) {
4341     if(regs[i+1].regmap[hr]!=reg) break;
4342     if(!((regs[i+1].isconst>>hr)&1)) break;
4343     if(bt[i+1]) break;
4344     i++;
4345   }
4346   if(i<slen-1) {
4347     if(itype[i]==UJUMP||itype[i]==RJUMP||itype[i]==CJUMP||itype[i]==SJUMP) {
4348       *value=constmap[i][hr];
4349       return 1;
4350     }
4351     if(!bt[i+1]) {
4352       if(itype[i+1]==UJUMP||itype[i+1]==RJUMP||itype[i+1]==CJUMP||itype[i+1]==SJUMP) {
4353         // Load in delay slot, out-of-order execution
4354         if(itype[i+2]==LOAD&&rs1[i+2]==reg&&rt1[i+2]==reg&&((regs[i+1].wasconst>>hr)&1))
4355         {
4356           #ifdef HOST_IMM_ADDR32
4357           if(!using_tlb||((signed int)constmap[i][hr]+imm[i+2])<(signed int)0xC0000000) return 0;
4358           #endif
4359           // Precompute load address
4360           *value=constmap[i][hr]+imm[i+2];
4361           return 1;
4362         }
4363       }
4364       if(itype[i+1]==LOAD&&rs1[i+1]==reg&&rt1[i+1]==reg)
4365       {
4366         #ifdef HOST_IMM_ADDR32
4367         if(!using_tlb||((signed int)constmap[i][hr]+imm[i+1])<(signed int)0xC0000000) return 0;
4368         #endif
4369         // Precompute load address
4370         *value=constmap[i][hr]+imm[i+1];
4371         //printf("c=%x imm=%x\n",(int)constmap[i][hr],imm[i+1]);
4372         return 1;
4373       }
4374     }
4375   }
4376   *value=constmap[i][hr];
4377   //printf("c=%x\n",(int)constmap[i][hr]);
4378   if(i==slen-1) return 1;
4379   if(reg<64) {
4380     return !((unneeded_reg[i+1]>>reg)&1);
4381   }else{
4382     return !((unneeded_reg_upper[i+1]>>reg)&1);
4383   }
4384 }
4385
4386 // Load registers with known constants
4387 void load_consts(signed char pre[],signed char regmap[],int is32,int i)
4388 {
4389   int hr;
4390   // Load 32-bit regs
4391   for(hr=0;hr<HOST_REGS;hr++) {
4392     if(hr!=EXCLUDE_REG&&regmap[hr]>=0) {
4393       //if(entry[hr]!=regmap[hr]) {
4394       if(i==0||!((regs[i-1].isconst>>hr)&1)||pre[hr]!=regmap[hr]||bt[i]) {
4395         if(((regs[i].isconst>>hr)&1)&&regmap[hr]<64&&regmap[hr]>0) {
4396           int value;
4397           if(get_final_value(hr,i,&value)) {
4398             if(value==0) {
4399               emit_zeroreg(hr);
4400             }
4401             else {
4402               emit_movimm(value,hr);
4403             }
4404           }
4405         }
4406       }
4407     }
4408   }
4409   // Load 64-bit regs
4410   for(hr=0;hr<HOST_REGS;hr++) {
4411     if(hr!=EXCLUDE_REG&&regmap[hr]>=0) {
4412       //if(entry[hr]!=regmap[hr]) {
4413       if(i==0||!((regs[i-1].isconst>>hr)&1)||pre[hr]!=regmap[hr]||bt[i]) {
4414         if(((regs[i].isconst>>hr)&1)&&regmap[hr]>64) {
4415           if((is32>>(regmap[hr]&63))&1) {
4416             int lr=get_reg(regmap,regmap[hr]-64);
4417             assert(lr>=0);
4418             emit_sarimm(lr,31,hr);
4419           }
4420           else
4421           {
4422             int value;
4423             if(get_final_value(hr,i,&value)) {
4424               if(value==0) {
4425                 emit_zeroreg(hr);
4426               }
4427               else {
4428                 emit_movimm(value,hr);
4429               }
4430             }
4431           }
4432         }
4433       }
4434     }
4435   }
4436 }
4437 void load_all_consts(signed char regmap[],int is32,u_int dirty,int i)
4438 {
4439   int hr;
4440   // Load 32-bit regs
4441   for(hr=0;hr<HOST_REGS;hr++) {
4442     if(hr!=EXCLUDE_REG&&regmap[hr]>=0&&((dirty>>hr)&1)) {
4443       if(((regs[i].isconst>>hr)&1)&&regmap[hr]<64&&regmap[hr]>0) {
4444         int value=constmap[i][hr];
4445         if(value==0) {
4446           emit_zeroreg(hr);
4447         }
4448         else {
4449           emit_movimm(value,hr);
4450         }
4451       }
4452     }
4453   }
4454   // Load 64-bit regs
4455   for(hr=0;hr<HOST_REGS;hr++) {
4456     if(hr!=EXCLUDE_REG&&regmap[hr]>=0&&((dirty>>hr)&1)) {
4457       if(((regs[i].isconst>>hr)&1)&&regmap[hr]>64) {
4458         if((is32>>(regmap[hr]&63))&1) {
4459           int lr=get_reg(regmap,regmap[hr]-64);
4460           assert(lr>=0);
4461           emit_sarimm(lr,31,hr);
4462         }
4463         else
4464         {
4465           int value=constmap[i][hr];
4466           if(value==0) {
4467             emit_zeroreg(hr);
4468           }
4469           else {
4470             emit_movimm(value,hr);
4471           }
4472         }
4473       }
4474     }
4475   }
4476 }
4477
4478 // Write out all dirty registers (except cycle count)
4479 void wb_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty)
4480 {
4481   int hr;
4482   for(hr=0;hr<HOST_REGS;hr++) {
4483     if(hr!=EXCLUDE_REG) {
4484       if(i_regmap[hr]>0) {
4485         if(i_regmap[hr]!=CCREG) {
4486           if((i_dirty>>hr)&1) {
4487             if(i_regmap[hr]<64) {
4488               emit_storereg(i_regmap[hr],hr);
4489 #ifndef FORCE32
4490               if( ((i_is32>>i_regmap[hr])&1) ) {
4491                 #ifdef DESTRUCTIVE_WRITEBACK
4492                 emit_sarimm(hr,31,hr);
4493                 emit_storereg(i_regmap[hr]|64,hr);
4494                 #else
4495                 emit_sarimm(hr,31,HOST_TEMPREG);
4496                 emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
4497                 #endif
4498               }
4499 #endif
4500             }else{
4501               if( !((i_is32>>(i_regmap[hr]&63))&1) ) {
4502                 emit_storereg(i_regmap[hr],hr);
4503               }
4504             }
4505           }
4506         }
4507       }
4508     }
4509   }
4510 }
4511 // Write out dirty registers that we need to reload (pair with load_needed_regs)
4512 // This writes the registers not written by store_regs_bt
4513 void wb_needed_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4514 {
4515   int hr;
4516   int t=(addr-start)>>2;
4517   for(hr=0;hr<HOST_REGS;hr++) {
4518     if(hr!=EXCLUDE_REG) {
4519       if(i_regmap[hr]>0) {
4520         if(i_regmap[hr]!=CCREG) {
4521           if(i_regmap[hr]==regs[t].regmap_entry[hr] && ((regs[t].dirty>>hr)&1) && !(((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) {
4522             if((i_dirty>>hr)&1) {
4523               if(i_regmap[hr]<64) {
4524                 emit_storereg(i_regmap[hr],hr);
4525 #ifndef FORCE32
4526                 if( ((i_is32>>i_regmap[hr])&1) ) {
4527                   #ifdef DESTRUCTIVE_WRITEBACK
4528                   emit_sarimm(hr,31,hr);
4529                   emit_storereg(i_regmap[hr]|64,hr);
4530                   #else
4531                   emit_sarimm(hr,31,HOST_TEMPREG);
4532                   emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
4533                   #endif
4534                 }
4535 #endif
4536               }else{
4537                 if( !((i_is32>>(i_regmap[hr]&63))&1) ) {
4538                   emit_storereg(i_regmap[hr],hr);
4539                 }
4540               }
4541             }
4542           }
4543         }
4544       }
4545     }
4546   }
4547 }
4548
4549 // Load all registers (except cycle count)
4550 void load_all_regs(signed char i_regmap[])
4551 {
4552   int hr;
4553   for(hr=0;hr<HOST_REGS;hr++) {
4554     if(hr!=EXCLUDE_REG) {
4555       if(i_regmap[hr]==0) {
4556         emit_zeroreg(hr);
4557       }
4558       else
4559       if(i_regmap[hr]>0 && (i_regmap[hr]&63)<TEMPREG && i_regmap[hr]!=CCREG)
4560       {
4561         emit_loadreg(i_regmap[hr],hr);
4562       }
4563     }
4564   }
4565 }
4566
4567 // Load all current registers also needed by next instruction
4568 void load_needed_regs(signed char i_regmap[],signed char next_regmap[])
4569 {
4570   int hr;
4571   for(hr=0;hr<HOST_REGS;hr++) {
4572     if(hr!=EXCLUDE_REG) {
4573       if(get_reg(next_regmap,i_regmap[hr])>=0) {
4574         if(i_regmap[hr]==0) {
4575           emit_zeroreg(hr);
4576         }
4577         else
4578         if(i_regmap[hr]>0 && (i_regmap[hr]&63)<TEMPREG && i_regmap[hr]!=CCREG)
4579         {
4580           emit_loadreg(i_regmap[hr],hr);
4581         }
4582       }
4583     }
4584   }
4585 }
4586
4587 // Load all regs, storing cycle count if necessary
4588 void load_regs_entry(int t)
4589 {
4590   int hr;
4591   if(is_ds[t]) emit_addimm(HOST_CCREG,CLOCK_ADJUST(1),HOST_CCREG);
4592   else if(ccadj[t]) emit_addimm(HOST_CCREG,-CLOCK_ADJUST(ccadj[t]),HOST_CCREG);
4593   if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) {
4594     emit_storereg(CCREG,HOST_CCREG);
4595   }
4596   // Load 32-bit regs
4597   for(hr=0;hr<HOST_REGS;hr++) {
4598     if(regs[t].regmap_entry[hr]>=0&&regs[t].regmap_entry[hr]<TEMPREG) {
4599       if(regs[t].regmap_entry[hr]==0) {
4600         emit_zeroreg(hr);
4601       }
4602       else if(regs[t].regmap_entry[hr]!=CCREG)
4603       {
4604         emit_loadreg(regs[t].regmap_entry[hr],hr);
4605       }
4606     }
4607   }
4608   // Load 64-bit regs
4609   for(hr=0;hr<HOST_REGS;hr++) {
4610     if(regs[t].regmap_entry[hr]>=64&&regs[t].regmap_entry[hr]<TEMPREG+64) {
4611       assert(regs[t].regmap_entry[hr]!=64);
4612       if((regs[t].was32>>(regs[t].regmap_entry[hr]&63))&1) {
4613         int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64);
4614         if(lr<0) {
4615           emit_loadreg(regs[t].regmap_entry[hr],hr);
4616         }
4617         else
4618         {
4619           emit_sarimm(lr,31,hr);
4620         }
4621       }
4622       else
4623       {
4624         emit_loadreg(regs[t].regmap_entry[hr],hr);
4625       }
4626     }
4627   }
4628 }
4629
4630 // Store dirty registers prior to branch
4631 void store_regs_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4632 {
4633   if(internal_branch(i_is32,addr))
4634   {
4635     int t=(addr-start)>>2;
4636     int hr;
4637     for(hr=0;hr<HOST_REGS;hr++) {
4638       if(hr!=EXCLUDE_REG) {
4639         if(i_regmap[hr]>0 && i_regmap[hr]!=CCREG) {
4640           if(i_regmap[hr]!=regs[t].regmap_entry[hr] || !((regs[t].dirty>>hr)&1) || (((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) {
4641             if((i_dirty>>hr)&1) {
4642               if(i_regmap[hr]<64) {
4643                 if(!((unneeded_reg[t]>>i_regmap[hr])&1)) {
4644                   emit_storereg(i_regmap[hr],hr);
4645                   if( ((i_is32>>i_regmap[hr])&1) && !((unneeded_reg_upper[t]>>i_regmap[hr])&1) ) {
4646                     #ifdef DESTRUCTIVE_WRITEBACK
4647                     emit_sarimm(hr,31,hr);
4648                     emit_storereg(i_regmap[hr]|64,hr);
4649                     #else
4650                     emit_sarimm(hr,31,HOST_TEMPREG);
4651                     emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
4652                     #endif
4653                   }
4654                 }
4655               }else{
4656                 if( !((i_is32>>(i_regmap[hr]&63))&1) && !((unneeded_reg_upper[t]>>(i_regmap[hr]&63))&1) ) {
4657                   emit_storereg(i_regmap[hr],hr);
4658                 }
4659               }
4660             }
4661           }
4662         }
4663       }
4664     }
4665   }
4666   else
4667   {
4668     // Branch out of this block, write out all dirty regs
4669     wb_dirtys(i_regmap,i_is32,i_dirty);
4670   }
4671 }
4672
4673 // Load all needed registers for branch target
4674 void load_regs_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4675 {
4676   //if(addr>=start && addr<(start+slen*4))
4677   if(internal_branch(i_is32,addr))
4678   {
4679     int t=(addr-start)>>2;
4680     int hr;
4681     // Store the cycle count before loading something else
4682     if(i_regmap[HOST_CCREG]!=CCREG) {
4683       assert(i_regmap[HOST_CCREG]==-1);
4684     }
4685     if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) {
4686       emit_storereg(CCREG,HOST_CCREG);
4687     }
4688     // Load 32-bit regs
4689     for(hr=0;hr<HOST_REGS;hr++) {
4690       if(hr!=EXCLUDE_REG&&regs[t].regmap_entry[hr]>=0&&regs[t].regmap_entry[hr]<TEMPREG) {
4691         #ifdef DESTRUCTIVE_WRITEBACK
4692         if(i_regmap[hr]!=regs[t].regmap_entry[hr] || ( !((regs[t].dirty>>hr)&1) && ((i_dirty>>hr)&1) && (((i_is32&~unneeded_reg_upper[t])>>i_regmap[hr])&1) ) || (((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) {
4693         #else
4694         if(i_regmap[hr]!=regs[t].regmap_entry[hr] ) {
4695         #endif
4696           if(regs[t].regmap_entry[hr]==0) {
4697             emit_zeroreg(hr);
4698           }
4699           else if(regs[t].regmap_entry[hr]!=CCREG)
4700           {
4701             emit_loadreg(regs[t].regmap_entry[hr],hr);
4702           }
4703         }
4704       }
4705     }
4706     //Load 64-bit regs
4707     for(hr=0;hr<HOST_REGS;hr++) {
4708       if(hr!=EXCLUDE_REG&&regs[t].regmap_entry[hr]>=64&&regs[t].regmap_entry[hr]<TEMPREG+64) {
4709         if(i_regmap[hr]!=regs[t].regmap_entry[hr]) {
4710           assert(regs[t].regmap_entry[hr]!=64);
4711           if((i_is32>>(regs[t].regmap_entry[hr]&63))&1) {
4712             int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64);
4713             if(lr<0) {
4714               emit_loadreg(regs[t].regmap_entry[hr],hr);
4715             }
4716             else
4717             {
4718               emit_sarimm(lr,31,hr);
4719             }
4720           }
4721           else
4722           {
4723             emit_loadreg(regs[t].regmap_entry[hr],hr);
4724           }
4725         }
4726         else if((i_is32>>(regs[t].regmap_entry[hr]&63))&1) {
4727           int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64);
4728           assert(lr>=0);
4729           emit_sarimm(lr,31,hr);
4730         }
4731       }
4732     }
4733   }
4734 }
4735
4736 int match_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4737 {
4738   if(addr>=start && addr<start+slen*4-4)
4739   {
4740     int t=(addr-start)>>2;
4741     int hr;
4742     if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) return 0;
4743     for(hr=0;hr<HOST_REGS;hr++)
4744     {
4745       if(hr!=EXCLUDE_REG)
4746       {
4747         if(i_regmap[hr]!=regs[t].regmap_entry[hr])
4748         {
4749           if(regs[t].regmap_entry[hr]>=0&&(regs[t].regmap_entry[hr]|64)<TEMPREG+64)
4750           {
4751             return 0;
4752           }
4753           else
4754           if((i_dirty>>hr)&1)
4755           {
4756             if(i_regmap[hr]<TEMPREG)
4757             {
4758               if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4759                 return 0;
4760             }
4761             else if(i_regmap[hr]>=64&&i_regmap[hr]<TEMPREG+64)
4762             {
4763               if(!((unneeded_reg_upper[t]>>(i_regmap[hr]&63))&1))
4764                 return 0;
4765             }
4766           }
4767         }
4768         else // Same register but is it 32-bit or dirty?
4769         if(i_regmap[hr]>=0)
4770         {
4771           if(!((regs[t].dirty>>hr)&1))
4772           {
4773             if((i_dirty>>hr)&1)
4774             {
4775               if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4776               {
4777                 //printf("%x: dirty no match\n",addr);
4778                 return 0;
4779               }
4780             }
4781           }
4782           if((((regs[t].was32^i_is32)&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)
4783           {
4784             //printf("%x: is32 no match\n",addr);
4785             return 0;
4786           }
4787         }
4788       }
4789     }
4790     //if(is32[t]&~unneeded_reg_upper[t]&~i_is32) return 0;
4791 #ifndef FORCE32
4792     if(requires_32bit[t]&~i_is32) return 0;
4793 #endif
4794     // Delay slots are not valid branch targets
4795     //if(t>0&&(itype[t-1]==RJUMP||itype[t-1]==UJUMP||itype[t-1]==CJUMP||itype[t-1]==SJUMP||itype[t-1]==FJUMP)) return 0;
4796     // Delay slots require additional processing, so do not match
4797     if(is_ds[t]) return 0;
4798   }
4799   else
4800   {
4801     int hr;
4802     for(hr=0;hr<HOST_REGS;hr++)
4803     {
4804       if(hr!=EXCLUDE_REG)
4805       {
4806         if(i_regmap[hr]>=0)
4807         {
4808           if(hr!=HOST_CCREG||i_regmap[hr]!=CCREG)
4809           {
4810             if((i_dirty>>hr)&1)
4811             {
4812               return 0;
4813             }
4814           }
4815         }
4816       }
4817     }
4818   }
4819   return 1;
4820 }
4821
4822 // Used when a branch jumps into the delay slot of another branch
4823 void ds_assemble_entry(int i)
4824 {
4825   int t=(ba[i]-start)>>2;
4826   if(!instr_addr[t]) instr_addr[t]=(u_int)out;
4827   assem_debug("Assemble delay slot at %x\n",ba[i]);
4828   assem_debug("<->\n");
4829   if(regs[t].regmap_entry[HOST_CCREG]==CCREG&&regs[t].regmap[HOST_CCREG]!=CCREG)
4830     wb_register(CCREG,regs[t].regmap_entry,regs[t].wasdirty,regs[t].was32);
4831   load_regs(regs[t].regmap_entry,regs[t].regmap,regs[t].was32,rs1[t],rs2[t]);
4832   address_generation(t,&regs[t],regs[t].regmap_entry);
4833   if(itype[t]==STORE||itype[t]==STORELR||(opcode[t]&0x3b)==0x39||(opcode[t]&0x3b)==0x3a)
4834     load_regs(regs[t].regmap_entry,regs[t].regmap,regs[t].was32,INVCP,INVCP);
4835   cop1_usable=0;
4836   is_delayslot=0;
4837   switch(itype[t]) {
4838     case ALU:
4839       alu_assemble(t,&regs[t]);break;
4840     case IMM16:
4841       imm16_assemble(t,&regs[t]);break;
4842     case SHIFT:
4843       shift_assemble(t,&regs[t]);break;
4844     case SHIFTIMM:
4845       shiftimm_assemble(t,&regs[t]);break;
4846     case LOAD:
4847       load_assemble(t,&regs[t]);break;
4848     case LOADLR:
4849       loadlr_assemble(t,&regs[t]);break;
4850     case STORE:
4851       store_assemble(t,&regs[t]);break;
4852     case STORELR:
4853       storelr_assemble(t,&regs[t]);break;
4854     case COP0:
4855       cop0_assemble(t,&regs[t]);break;
4856     case COP1:
4857       cop1_assemble(t,&regs[t]);break;
4858     case C1LS:
4859       c1ls_assemble(t,&regs[t]);break;
4860     case COP2:
4861       cop2_assemble(t,&regs[t]);break;
4862     case C2LS:
4863       c2ls_assemble(t,&regs[t]);break;
4864     case C2OP:
4865       c2op_assemble(t,&regs[t]);break;
4866     case FCONV:
4867       fconv_assemble(t,&regs[t]);break;
4868     case FLOAT:
4869       float_assemble(t,&regs[t]);break;
4870     case FCOMP:
4871       fcomp_assemble(t,&regs[t]);break;
4872     case MULTDIV:
4873       multdiv_assemble(t,&regs[t]);break;
4874     case MOV:
4875       mov_assemble(t,&regs[t]);break;
4876     case SYSCALL:
4877     case HLECALL:
4878     case INTCALL:
4879     case SPAN:
4880     case UJUMP:
4881     case RJUMP:
4882     case CJUMP:
4883     case SJUMP:
4884     case FJUMP:
4885       printf("Jump in the delay slot.  This is probably a bug.\n");
4886   }
4887   store_regs_bt(regs[t].regmap,regs[t].is32,regs[t].dirty,ba[i]+4);
4888   load_regs_bt(regs[t].regmap,regs[t].is32,regs[t].dirty,ba[i]+4);
4889   if(internal_branch(regs[t].is32,ba[i]+4))
4890     assem_debug("branch: internal\n");
4891   else
4892     assem_debug("branch: external\n");
4893   assert(internal_branch(regs[t].is32,ba[i]+4));
4894   add_to_linker((int)out,ba[i]+4,internal_branch(regs[t].is32,ba[i]+4));
4895   emit_jmp(0);
4896 }
4897
4898 void do_cc(int i,signed char i_regmap[],int *adj,int addr,int taken,int invert)
4899 {
4900   int count;
4901   int jaddr;
4902   int idle=0;
4903   if(itype[i]==RJUMP)
4904   {
4905     *adj=0;
4906   }
4907   //if(ba[i]>=start && ba[i]<(start+slen*4))
4908   if(internal_branch(branch_regs[i].is32,ba[i]))
4909   {
4910     int t=(ba[i]-start)>>2;
4911     if(is_ds[t]) *adj=-1; // Branch into delay slot adds an extra cycle
4912     else *adj=ccadj[t];
4913   }
4914   else
4915   {
4916     *adj=0;
4917   }
4918   count=ccadj[i];
4919   if(taken==TAKEN && i==(ba[i]-start)>>2 && source[i+1]==0) {
4920     // Idle loop
4921     if(count&1) emit_addimm_and_set_flags(2*(count+2),HOST_CCREG);
4922     idle=(int)out;
4923     //emit_subfrommem(&idlecount,HOST_CCREG); // Count idle cycles
4924     emit_andimm(HOST_CCREG,3,HOST_CCREG);
4925     jaddr=(int)out;
4926     emit_jmp(0);
4927   }
4928   else if(*adj==0||invert) {
4929     emit_addimm_and_set_flags(CLOCK_ADJUST(count+2),HOST_CCREG);
4930     jaddr=(int)out;
4931     emit_jns(0);
4932   }
4933   else
4934   {
4935     emit_cmpimm(HOST_CCREG,-CLOCK_ADJUST(count+2));
4936     jaddr=(int)out;
4937     emit_jns(0);
4938   }
4939   add_stub(CC_STUB,jaddr,idle?idle:(int)out,(*adj==0||invert||idle)?0:(count+2),i,addr,taken,0);
4940 }
4941
4942 void do_ccstub(int n)
4943 {
4944   literal_pool(256);
4945   assem_debug("do_ccstub %x\n",start+stubs[n][4]*4);
4946   set_jump_target(stubs[n][1],(int)out);
4947   int i=stubs[n][4];
4948   if(stubs[n][6]==NULLDS) {
4949     // Delay slot instruction is nullified ("likely" branch)
4950     wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty);
4951   }
4952   else if(stubs[n][6]!=TAKEN) {
4953     wb_dirtys(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty);
4954   }
4955   else {
4956     if(internal_branch(branch_regs[i].is32,ba[i]))
4957       wb_needed_dirtys(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
4958   }
4959   if(stubs[n][5]!=-1)
4960   {
4961     // Save PC as return address
4962     emit_movimm(stubs[n][5],EAX);
4963     emit_writeword(EAX,(int)&pcaddr);
4964   }
4965   else
4966   {
4967     // Return address depends on which way the branch goes
4968     if(itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
4969     {
4970       int s1l=get_reg(branch_regs[i].regmap,rs1[i]);
4971       int s1h=get_reg(branch_regs[i].regmap,rs1[i]|64);
4972       int s2l=get_reg(branch_regs[i].regmap,rs2[i]);
4973       int s2h=get_reg(branch_regs[i].regmap,rs2[i]|64);
4974       if(rs1[i]==0)
4975       {
4976         s1l=s2l;s1h=s2h;
4977         s2l=s2h=-1;
4978       }
4979       else if(rs2[i]==0)
4980       {
4981         s2l=s2h=-1;
4982       }
4983       if((branch_regs[i].is32>>rs1[i])&(branch_regs[i].is32>>rs2[i])&1) {
4984         s1h=s2h=-1;
4985       }
4986       assert(s1l>=0);
4987       #ifdef DESTRUCTIVE_WRITEBACK
4988       if(rs1[i]) {
4989         if((branch_regs[i].dirty>>s1l)&(branch_regs[i].is32>>rs1[i])&1)
4990           emit_loadreg(rs1[i],s1l);
4991       }
4992       else {
4993         if((branch_regs[i].dirty>>s1l)&(branch_regs[i].is32>>rs2[i])&1)
4994           emit_loadreg(rs2[i],s1l);
4995       }
4996       if(s2l>=0)
4997         if((branch_regs[i].dirty>>s2l)&(branch_regs[i].is32>>rs2[i])&1)
4998           emit_loadreg(rs2[i],s2l);
4999       #endif
5000       int hr=0;
5001       int addr=-1,alt=-1,ntaddr=-1;
5002       while(hr<HOST_REGS)
5003       {
5004         if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
5005            (branch_regs[i].regmap[hr]&63)!=rs1[i] &&
5006            (branch_regs[i].regmap[hr]&63)!=rs2[i] )
5007         {
5008           addr=hr++;break;
5009         }
5010         hr++;
5011       }
5012       while(hr<HOST_REGS)
5013       {
5014         if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
5015            (branch_regs[i].regmap[hr]&63)!=rs1[i] &&
5016            (branch_regs[i].regmap[hr]&63)!=rs2[i] )
5017         {
5018           alt=hr++;break;
5019         }
5020         hr++;
5021       }
5022       if((opcode[i]&0x2E)==6) // BLEZ/BGTZ needs another register
5023       {
5024         while(hr<HOST_REGS)
5025         {
5026           if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
5027              (branch_regs[i].regmap[hr]&63)!=rs1[i] &&
5028              (branch_regs[i].regmap[hr]&63)!=rs2[i] )
5029           {
5030             ntaddr=hr;break;
5031           }
5032           hr++;
5033         }
5034         assert(hr<HOST_REGS);
5035       }
5036       if((opcode[i]&0x2f)==4) // BEQ
5037       {
5038         #ifdef HAVE_CMOV_IMM
5039         if(s1h<0) {
5040           if(s2l>=0) emit_cmp(s1l,s2l);
5041           else emit_test(s1l,s1l);
5042           emit_cmov2imm_e_ne_compact(ba[i],start+i*4+8,addr);
5043         }
5044         else
5045         #endif
5046         {
5047           emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
5048           if(s1h>=0) {
5049             if(s2h>=0) emit_cmp(s1h,s2h);
5050             else emit_test(s1h,s1h);
5051             emit_cmovne_reg(alt,addr);
5052           }
5053           if(s2l>=0) emit_cmp(s1l,s2l);
5054           else emit_test(s1l,s1l);
5055           emit_cmovne_reg(alt,addr);
5056         }
5057       }
5058       if((opcode[i]&0x2f)==5) // BNE
5059       {
5060         #ifdef HAVE_CMOV_IMM
5061         if(s1h<0) {
5062           if(s2l>=0) emit_cmp(s1l,s2l);
5063           else emit_test(s1l,s1l);
5064           emit_cmov2imm_e_ne_compact(start+i*4+8,ba[i],addr);
5065         }
5066         else
5067         #endif
5068         {
5069           emit_mov2imm_compact(start+i*4+8,addr,ba[i],alt);
5070           if(s1h>=0) {
5071             if(s2h>=0) emit_cmp(s1h,s2h);
5072             else emit_test(s1h,s1h);
5073             emit_cmovne_reg(alt,addr);
5074           }
5075           if(s2l>=0) emit_cmp(s1l,s2l);
5076           else emit_test(s1l,s1l);
5077           emit_cmovne_reg(alt,addr);
5078         }
5079       }
5080       if((opcode[i]&0x2f)==6) // BLEZ
5081       {
5082         //emit_movimm(ba[i],alt);
5083         //emit_movimm(start+i*4+8,addr);
5084         emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
5085         emit_cmpimm(s1l,1);
5086         if(s1h>=0) emit_mov(addr,ntaddr);
5087         emit_cmovl_reg(alt,addr);
5088         if(s1h>=0) {
5089           emit_test(s1h,s1h);
5090           emit_cmovne_reg(ntaddr,addr);
5091           emit_cmovs_reg(alt,addr);
5092         }
5093       }
5094       if((opcode[i]&0x2f)==7) // BGTZ
5095       {
5096         //emit_movimm(ba[i],addr);
5097         //emit_movimm(start+i*4+8,ntaddr);
5098         emit_mov2imm_compact(ba[i],addr,start+i*4+8,ntaddr);
5099         emit_cmpimm(s1l,1);
5100         if(s1h>=0) emit_mov(addr,alt);
5101         emit_cmovl_reg(ntaddr,addr);
5102         if(s1h>=0) {
5103           emit_test(s1h,s1h);
5104           emit_cmovne_reg(alt,addr);
5105           emit_cmovs_reg(ntaddr,addr);
5106         }
5107       }
5108       if((opcode[i]==1)&&(opcode2[i]&0x2D)==0) // BLTZ
5109       {
5110         //emit_movimm(ba[i],alt);
5111         //emit_movimm(start+i*4+8,addr);
5112         emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
5113         if(s1h>=0) emit_test(s1h,s1h);
5114         else emit_test(s1l,s1l);
5115         emit_cmovs_reg(alt,addr);
5116       }
5117       if((opcode[i]==1)&&(opcode2[i]&0x2D)==1) // BGEZ
5118       {
5119         //emit_movimm(ba[i],addr);
5120         //emit_movimm(start+i*4+8,alt);
5121         emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
5122         if(s1h>=0) emit_test(s1h,s1h);
5123         else emit_test(s1l,s1l);
5124         emit_cmovs_reg(alt,addr);
5125       }
5126       if(opcode[i]==0x11 && opcode2[i]==0x08 ) {
5127         if(source[i]&0x10000) // BC1T
5128         {
5129           //emit_movimm(ba[i],alt);
5130           //emit_movimm(start+i*4+8,addr);
5131           emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
5132           emit_testimm(s1l,0x800000);
5133           emit_cmovne_reg(alt,addr);
5134         }
5135         else // BC1F
5136         {
5137           //emit_movimm(ba[i],addr);
5138           //emit_movimm(start+i*4+8,alt);
5139           emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
5140           emit_testimm(s1l,0x800000);
5141           emit_cmovne_reg(alt,addr);
5142         }
5143       }
5144       emit_writeword(addr,(int)&pcaddr);
5145     }
5146     else
5147     if(itype[i]==RJUMP)
5148     {
5149       int r=get_reg(branch_regs[i].regmap,rs1[i]);
5150       if(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]) {
5151         r=get_reg(branch_regs[i].regmap,RTEMP);
5152       }
5153       emit_writeword(r,(int)&pcaddr);
5154     }
5155     else {printf("Unknown branch type in do_ccstub\n");exit(1);}
5156   }
5157   // Update cycle count
5158   assert(branch_regs[i].regmap[HOST_CCREG]==CCREG||branch_regs[i].regmap[HOST_CCREG]==-1);
5159   if(stubs[n][3]) emit_addimm(HOST_CCREG,CLOCK_ADJUST((int)stubs[n][3]),HOST_CCREG);
5160   emit_call((int)cc_interrupt);
5161   if(stubs[n][3]) emit_addimm(HOST_CCREG,-CLOCK_ADJUST((int)stubs[n][3]),HOST_CCREG);
5162   if(stubs[n][6]==TAKEN) {
5163     if(internal_branch(branch_regs[i].is32,ba[i]))
5164       load_needed_regs(branch_regs[i].regmap,regs[(ba[i]-start)>>2].regmap_entry);
5165     else if(itype[i]==RJUMP) {
5166       if(get_reg(branch_regs[i].regmap,RTEMP)>=0)
5167         emit_readword((int)&pcaddr,get_reg(branch_regs[i].regmap,RTEMP));
5168       else
5169         emit_loadreg(rs1[i],get_reg(branch_regs[i].regmap,rs1[i]));
5170     }
5171   }else if(stubs[n][6]==NOTTAKEN) {
5172     if(i<slen-2) load_needed_regs(branch_regs[i].regmap,regmap_pre[i+2]);
5173     else load_all_regs(branch_regs[i].regmap);
5174   }else if(stubs[n][6]==NULLDS) {
5175     // Delay slot instruction is nullified ("likely" branch)
5176     if(i<slen-2) load_needed_regs(regs[i].regmap,regmap_pre[i+2]);
5177     else load_all_regs(regs[i].regmap);
5178   }else{
5179     load_all_regs(branch_regs[i].regmap);
5180   }
5181   emit_jmp(stubs[n][2]); // return address
5182
5183   /* This works but uses a lot of memory...
5184   emit_readword((int)&last_count,ECX);
5185   emit_add(HOST_CCREG,ECX,EAX);
5186   emit_writeword(EAX,(int)&Count);
5187   emit_call((int)gen_interupt);
5188   emit_readword((int)&Count,HOST_CCREG);
5189   emit_readword((int)&next_interupt,EAX);
5190   emit_readword((int)&pending_exception,EBX);
5191   emit_writeword(EAX,(int)&last_count);
5192   emit_sub(HOST_CCREG,EAX,HOST_CCREG);
5193   emit_test(EBX,EBX);
5194   int jne_instr=(int)out;
5195   emit_jne(0);
5196   if(stubs[n][3]) emit_addimm(HOST_CCREG,-2*stubs[n][3],HOST_CCREG);
5197   load_all_regs(branch_regs[i].regmap);
5198   emit_jmp(stubs[n][2]); // return address
5199   set_jump_target(jne_instr,(int)out);
5200   emit_readword((int)&pcaddr,EAX);
5201   // Call get_addr_ht instead of doing the hash table here.
5202   // This code is executed infrequently and takes up a lot of space
5203   // so smaller is better.
5204   emit_storereg(CCREG,HOST_CCREG);
5205   emit_pushreg(EAX);
5206   emit_call((int)get_addr_ht);
5207   emit_loadreg(CCREG,HOST_CCREG);
5208   emit_addimm(ESP,4,ESP);
5209   emit_jmpreg(EAX);*/
5210 }
5211
5212 add_to_linker(int addr,int target,int ext)
5213 {
5214   link_addr[linkcount][0]=addr;
5215   link_addr[linkcount][1]=target;
5216   link_addr[linkcount][2]=ext;
5217   linkcount++;
5218 }
5219
5220 static void ujump_assemble_write_ra(int i)
5221 {
5222   int rt;
5223   unsigned int return_address;
5224   rt=get_reg(branch_regs[i].regmap,31);
5225   assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5226   //assert(rt>=0);
5227   return_address=start+i*4+8;
5228   if(rt>=0) {
5229     #ifdef USE_MINI_HT
5230     if(internal_branch(branch_regs[i].is32,return_address)&&rt1[i+1]!=31) {
5231       int temp=-1; // note: must be ds-safe
5232       #ifdef HOST_TEMPREG
5233       temp=HOST_TEMPREG;
5234       #endif
5235       if(temp>=0) do_miniht_insert(return_address,rt,temp);
5236       else emit_movimm(return_address,rt);
5237     }
5238     else
5239     #endif
5240     {
5241       #ifdef REG_PREFETCH
5242       if(temp>=0)
5243       {
5244         if(i_regmap[temp]!=PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5245       }
5246       #endif
5247       emit_movimm(return_address,rt); // PC into link register
5248       #ifdef IMM_PREFETCH
5249       emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
5250       #endif
5251     }
5252   }
5253 }
5254
5255 void ujump_assemble(int i,struct regstat *i_regs)
5256 {
5257   signed char *i_regmap=i_regs->regmap;
5258   int ra_done=0;
5259   if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
5260   address_generation(i+1,i_regs,regs[i].regmap_entry);
5261   #ifdef REG_PREFETCH
5262   int temp=get_reg(branch_regs[i].regmap,PTEMP);
5263   if(rt1[i]==31&&temp>=0)
5264   {
5265     int return_address=start+i*4+8;
5266     if(get_reg(branch_regs[i].regmap,31)>0)
5267     if(i_regmap[temp]==PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5268   }
5269   #endif
5270   if(rt1[i]==31&&(rt1[i]==rs1[i+1]||rt1[i]==rs2[i+1])) {
5271     ujump_assemble_write_ra(i); // writeback ra for DS
5272     ra_done=1;
5273   }
5274   ds_assemble(i+1,i_regs);
5275   uint64_t bc_unneeded=branch_regs[i].u;
5276   uint64_t bc_unneeded_upper=branch_regs[i].uu;
5277   bc_unneeded|=1|(1LL<<rt1[i]);
5278   bc_unneeded_upper|=1|(1LL<<rt1[i]);
5279   wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5280                 bc_unneeded,bc_unneeded_upper);
5281   load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5282   if(!ra_done&&rt1[i]==31)
5283     ujump_assemble_write_ra(i);
5284   int cc,adj;
5285   cc=get_reg(branch_regs[i].regmap,CCREG);
5286   assert(cc==HOST_CCREG);
5287   store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5288   #ifdef REG_PREFETCH
5289   if(rt1[i]==31&&temp>=0) emit_prefetchreg(temp);
5290   #endif
5291   do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5292   if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
5293   load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5294   if(internal_branch(branch_regs[i].is32,ba[i]))
5295     assem_debug("branch: internal\n");
5296   else
5297     assem_debug("branch: external\n");
5298   if(internal_branch(branch_regs[i].is32,ba[i])&&is_ds[(ba[i]-start)>>2]) {
5299     ds_assemble_entry(i);
5300   }
5301   else {
5302     add_to_linker((int)out,ba[i],internal_branch(branch_regs[i].is32,ba[i]));
5303     emit_jmp(0);
5304   }
5305 }
5306
5307 static void rjump_assemble_write_ra(int i)
5308 {
5309   int rt,return_address;
5310   assert(rt1[i+1]!=rt1[i]);
5311   assert(rt2[i+1]!=rt1[i]);
5312   rt=get_reg(branch_regs[i].regmap,rt1[i]);
5313   assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5314   assert(rt>=0);
5315   return_address=start+i*4+8;
5316   #ifdef REG_PREFETCH
5317   if(temp>=0)
5318   {
5319     if(i_regmap[temp]!=PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5320   }
5321   #endif
5322   emit_movimm(return_address,rt); // PC into link register
5323   #ifdef IMM_PREFETCH
5324   emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
5325   #endif
5326 }
5327
5328 void rjump_assemble(int i,struct regstat *i_regs)
5329 {
5330   signed char *i_regmap=i_regs->regmap;
5331   int temp;
5332   int rs,cc,adj;
5333   int ra_done=0;
5334   rs=get_reg(branch_regs[i].regmap,rs1[i]);
5335   assert(rs>=0);
5336   if(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]) {
5337     // Delay slot abuse, make a copy of the branch address register
5338     temp=get_reg(branch_regs[i].regmap,RTEMP);
5339     assert(temp>=0);
5340     assert(regs[i].regmap[temp]==RTEMP);
5341     emit_mov(rs,temp);
5342     rs=temp;
5343   }
5344   address_generation(i+1,i_regs,regs[i].regmap_entry);
5345   #ifdef REG_PREFETCH
5346   if(rt1[i]==31)
5347   {
5348     if((temp=get_reg(branch_regs[i].regmap,PTEMP))>=0) {
5349       int return_address=start+i*4+8;
5350       if(i_regmap[temp]==PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5351     }
5352   }
5353   #endif
5354   #ifdef USE_MINI_HT
5355   if(rs1[i]==31) {
5356     int rh=get_reg(regs[i].regmap,RHASH);
5357     if(rh>=0) do_preload_rhash(rh);
5358   }
5359   #endif
5360   if(rt1[i]!=0&&(rt1[i]==rs1[i+1]||rt1[i]==rs2[i+1])) {
5361     rjump_assemble_write_ra(i);
5362     ra_done=1;
5363   }
5364   ds_assemble(i+1,i_regs);
5365   uint64_t bc_unneeded=branch_regs[i].u;
5366   uint64_t bc_unneeded_upper=branch_regs[i].uu;
5367   bc_unneeded|=1|(1LL<<rt1[i]);
5368   bc_unneeded_upper|=1|(1LL<<rt1[i]);
5369   bc_unneeded&=~(1LL<<rs1[i]);
5370   wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5371                 bc_unneeded,bc_unneeded_upper);
5372   load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],CCREG);
5373   if(!ra_done&&rt1[i]!=0)
5374     rjump_assemble_write_ra(i);
5375   cc=get_reg(branch_regs[i].regmap,CCREG);
5376   assert(cc==HOST_CCREG);
5377   #ifdef USE_MINI_HT
5378   int rh=get_reg(branch_regs[i].regmap,RHASH);
5379   int ht=get_reg(branch_regs[i].regmap,RHTBL);
5380   if(rs1[i]==31) {
5381     if(regs[i].regmap[rh]!=RHASH) do_preload_rhash(rh);
5382     do_preload_rhtbl(ht);
5383     do_rhash(rs,rh);
5384   }
5385   #endif
5386   store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,-1);
5387   #ifdef DESTRUCTIVE_WRITEBACK
5388   if((branch_regs[i].dirty>>rs)&(branch_regs[i].is32>>rs1[i])&1) {
5389     if(rs1[i]!=rt1[i+1]&&rs1[i]!=rt2[i+1]) {
5390       emit_loadreg(rs1[i],rs);
5391     }
5392   }
5393   #endif
5394   #ifdef REG_PREFETCH
5395   if(rt1[i]==31&&temp>=0) emit_prefetchreg(temp);
5396   #endif
5397   #ifdef USE_MINI_HT
5398   if(rs1[i]==31) {
5399     do_miniht_load(ht,rh);
5400   }
5401   #endif
5402   //do_cc(i,branch_regs[i].regmap,&adj,-1,TAKEN);
5403   //if(adj) emit_addimm(cc,2*(ccadj[i]+2-adj),cc); // ??? - Shouldn't happen
5404   //assert(adj==0);
5405   emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),HOST_CCREG);
5406   add_stub(CC_STUB,(int)out,jump_vaddr_reg[rs],0,i,-1,TAKEN,0);
5407 #ifdef PCSX
5408   if(itype[i+1]==COP0&&(source[i+1]&0x3f)==0x10)
5409     // special case for RFE
5410     emit_jmp(0);
5411   else
5412 #endif
5413   emit_jns(0);
5414   //load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,-1);
5415   #ifdef USE_MINI_HT
5416   if(rs1[i]==31) {
5417     do_miniht_jump(rs,rh,ht);
5418   }
5419   else
5420   #endif
5421   {
5422     //if(rs!=EAX) emit_mov(rs,EAX);
5423     //emit_jmp((int)jump_vaddr_eax);
5424     emit_jmp(jump_vaddr_reg[rs]);
5425   }
5426   /* Check hash table
5427   temp=!rs;
5428   emit_mov(rs,temp);
5429   emit_shrimm(rs,16,rs);
5430   emit_xor(temp,rs,rs);
5431   emit_movzwl_reg(rs,rs);
5432   emit_shlimm(rs,4,rs);
5433   emit_cmpmem_indexed((int)hash_table,rs,temp);
5434   emit_jne((int)out+14);
5435   emit_readword_indexed((int)hash_table+4,rs,rs);
5436   emit_jmpreg(rs);
5437   emit_cmpmem_indexed((int)hash_table+8,rs,temp);
5438   emit_addimm_no_flags(8,rs);
5439   emit_jeq((int)out-17);
5440   // No hit on hash table, call compiler
5441   emit_pushreg(temp);
5442 //DEBUG >
5443 #ifdef DEBUG_CYCLE_COUNT
5444   emit_readword((int)&last_count,ECX);
5445   emit_add(HOST_CCREG,ECX,HOST_CCREG);
5446   emit_readword((int)&next_interupt,ECX);
5447   emit_writeword(HOST_CCREG,(int)&Count);
5448   emit_sub(HOST_CCREG,ECX,HOST_CCREG);
5449   emit_writeword(ECX,(int)&last_count);
5450 #endif
5451 //DEBUG <
5452   emit_storereg(CCREG,HOST_CCREG);
5453   emit_call((int)get_addr);
5454   emit_loadreg(CCREG,HOST_CCREG);
5455   emit_addimm(ESP,4,ESP);
5456   emit_jmpreg(EAX);*/
5457   #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5458   if(rt1[i]!=31&&i<slen-2&&(((u_int)out)&7)) emit_mov(13,13);
5459   #endif
5460 }
5461
5462 void cjump_assemble(int i,struct regstat *i_regs)
5463 {
5464   signed char *i_regmap=i_regs->regmap;
5465   int cc;
5466   int match;
5467   match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5468   assem_debug("match=%d\n",match);
5469   int s1h,s1l,s2h,s2l;
5470   int prev_cop1_usable=cop1_usable;
5471   int unconditional=0,nop=0;
5472   int only32=0;
5473   int invert=0;
5474   int internal=internal_branch(branch_regs[i].is32,ba[i]);
5475   if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
5476   if(!match) invert=1;
5477   #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5478   if(i>(ba[i]-start)>>2) invert=1;
5479   #endif
5480
5481   if(ooo[i]) {
5482     s1l=get_reg(branch_regs[i].regmap,rs1[i]);
5483     s1h=get_reg(branch_regs[i].regmap,rs1[i]|64);
5484     s2l=get_reg(branch_regs[i].regmap,rs2[i]);
5485     s2h=get_reg(branch_regs[i].regmap,rs2[i]|64);
5486   }
5487   else {
5488     s1l=get_reg(i_regmap,rs1[i]);
5489     s1h=get_reg(i_regmap,rs1[i]|64);
5490     s2l=get_reg(i_regmap,rs2[i]);
5491     s2h=get_reg(i_regmap,rs2[i]|64);
5492   }
5493   if(rs1[i]==0&&rs2[i]==0)
5494   {
5495     if(opcode[i]&1) nop=1;
5496     else unconditional=1;
5497     //assert(opcode[i]!=5);
5498     //assert(opcode[i]!=7);
5499     //assert(opcode[i]!=0x15);
5500     //assert(opcode[i]!=0x17);
5501   }
5502   else if(rs1[i]==0)
5503   {
5504     s1l=s2l;s1h=s2h;
5505     s2l=s2h=-1;
5506     only32=(regs[i].was32>>rs2[i])&1;
5507   }
5508   else if(rs2[i]==0)
5509   {
5510     s2l=s2h=-1;
5511     only32=(regs[i].was32>>rs1[i])&1;
5512   }
5513   else {
5514     only32=(regs[i].was32>>rs1[i])&(regs[i].was32>>rs2[i])&1;
5515   }
5516
5517   if(ooo[i]) {
5518     // Out of order execution (delay slot first)
5519     //printf("OOOE\n");
5520     address_generation(i+1,i_regs,regs[i].regmap_entry);
5521     ds_assemble(i+1,i_regs);
5522     int adj;
5523     uint64_t bc_unneeded=branch_regs[i].u;
5524     uint64_t bc_unneeded_upper=branch_regs[i].uu;
5525     bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
5526     bc_unneeded_upper&=~((1LL<<us1[i])|(1LL<<us2[i]));
5527     bc_unneeded|=1;
5528     bc_unneeded_upper|=1;
5529     wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5530                   bc_unneeded,bc_unneeded_upper);
5531     load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],rs2[i]);
5532     load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5533     cc=get_reg(branch_regs[i].regmap,CCREG);
5534     assert(cc==HOST_CCREG);
5535     if(unconditional)
5536       store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5537     //do_cc(i,branch_regs[i].regmap,&adj,unconditional?ba[i]:-1,unconditional);
5538     //assem_debug("cycle count (adj)\n");
5539     if(unconditional) {
5540       do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5541       if(i!=(ba[i]-start)>>2 || source[i+1]!=0) {
5542         if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
5543         load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5544         if(internal)
5545           assem_debug("branch: internal\n");
5546         else
5547           assem_debug("branch: external\n");
5548         if(internal&&is_ds[(ba[i]-start)>>2]) {
5549           ds_assemble_entry(i);
5550         }
5551         else {
5552           add_to_linker((int)out,ba[i],internal);
5553           emit_jmp(0);
5554         }
5555         #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5556         if(((u_int)out)&7) emit_addnop(0);
5557         #endif
5558       }
5559     }
5560     else if(nop) {
5561       emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),cc);
5562       int jaddr=(int)out;
5563       emit_jns(0);
5564       add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
5565     }
5566     else {
5567       int taken=0,nottaken=0,nottaken1=0;
5568       do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
5569       if(adj&&!invert) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
5570       if(!only32)
5571       {
5572         assert(s1h>=0);
5573         if(opcode[i]==4) // BEQ
5574         {
5575           if(s2h>=0) emit_cmp(s1h,s2h);
5576           else emit_test(s1h,s1h);
5577           nottaken1=(int)out;
5578           emit_jne(1);
5579         }
5580         if(opcode[i]==5) // BNE
5581         {
5582           if(s2h>=0) emit_cmp(s1h,s2h);
5583           else emit_test(s1h,s1h);
5584           if(invert) taken=(int)out;
5585           else add_to_linker((int)out,ba[i],internal);
5586           emit_jne(0);
5587         }
5588         if(opcode[i]==6) // BLEZ
5589         {
5590           emit_test(s1h,s1h);
5591           if(invert) taken=(int)out;
5592           else add_to_linker((int)out,ba[i],internal);
5593           emit_js(0);
5594           nottaken1=(int)out;
5595           emit_jne(1);
5596         }
5597         if(opcode[i]==7) // BGTZ
5598         {
5599           emit_test(s1h,s1h);
5600           nottaken1=(int)out;
5601           emit_js(1);
5602           if(invert) taken=(int)out;
5603           else add_to_linker((int)out,ba[i],internal);
5604           emit_jne(0);
5605         }
5606       } // if(!only32)
5607
5608       //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5609       assert(s1l>=0);
5610       if(opcode[i]==4) // BEQ
5611       {
5612         if(s2l>=0) emit_cmp(s1l,s2l);
5613         else emit_test(s1l,s1l);
5614         if(invert){
5615           nottaken=(int)out;
5616           emit_jne(1);
5617         }else{
5618           add_to_linker((int)out,ba[i],internal);
5619           emit_jeq(0);
5620         }
5621       }
5622       if(opcode[i]==5) // BNE
5623       {
5624         if(s2l>=0) emit_cmp(s1l,s2l);
5625         else emit_test(s1l,s1l);
5626         if(invert){
5627           nottaken=(int)out;
5628           emit_jeq(1);
5629         }else{
5630           add_to_linker((int)out,ba[i],internal);
5631           emit_jne(0);
5632         }
5633       }
5634       if(opcode[i]==6) // BLEZ
5635       {
5636         emit_cmpimm(s1l,1);
5637         if(invert){
5638           nottaken=(int)out;
5639           emit_jge(1);
5640         }else{
5641           add_to_linker((int)out,ba[i],internal);
5642           emit_jl(0);
5643         }
5644       }
5645       if(opcode[i]==7) // BGTZ
5646       {
5647         emit_cmpimm(s1l,1);
5648         if(invert){
5649           nottaken=(int)out;
5650           emit_jl(1);
5651         }else{
5652           add_to_linker((int)out,ba[i],internal);
5653           emit_jge(0);
5654         }
5655       }
5656       if(invert) {
5657         if(taken) set_jump_target(taken,(int)out);
5658         #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5659         if(match&&(!internal||!is_ds[(ba[i]-start)>>2])) {
5660           if(adj) {
5661             emit_addimm(cc,-CLOCK_ADJUST(adj),cc);
5662             add_to_linker((int)out,ba[i],internal);
5663           }else{
5664             emit_addnop(13);
5665             add_to_linker((int)out,ba[i],internal*2);
5666           }
5667           emit_jmp(0);
5668         }else
5669         #endif
5670         {
5671           if(adj) emit_addimm(cc,-CLOCK_ADJUST(adj),cc);
5672           store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5673           load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5674           if(internal)
5675             assem_debug("branch: internal\n");
5676           else
5677             assem_debug("branch: external\n");
5678           if(internal&&is_ds[(ba[i]-start)>>2]) {
5679             ds_assemble_entry(i);
5680           }
5681           else {
5682             add_to_linker((int)out,ba[i],internal);
5683             emit_jmp(0);
5684           }
5685         }
5686         set_jump_target(nottaken,(int)out);
5687       }
5688
5689       if(nottaken1) set_jump_target(nottaken1,(int)out);
5690       if(adj) {
5691         if(!invert) emit_addimm(cc,CLOCK_ADJUST(adj),cc);
5692       }
5693     } // (!unconditional)
5694   } // if(ooo)
5695   else
5696   {
5697     // In-order execution (branch first)
5698     //if(likely[i]) printf("IOL\n");
5699     //else
5700     //printf("IOE\n");
5701     int taken=0,nottaken=0,nottaken1=0;
5702     if(!unconditional&&!nop) {
5703       if(!only32)
5704       {
5705         assert(s1h>=0);
5706         if((opcode[i]&0x2f)==4) // BEQ
5707         {
5708           if(s2h>=0) emit_cmp(s1h,s2h);
5709           else emit_test(s1h,s1h);
5710           nottaken1=(int)out;
5711           emit_jne(2);
5712         }
5713         if((opcode[i]&0x2f)==5) // BNE
5714         {
5715           if(s2h>=0) emit_cmp(s1h,s2h);
5716           else emit_test(s1h,s1h);
5717           taken=(int)out;
5718           emit_jne(1);
5719         }
5720         if((opcode[i]&0x2f)==6) // BLEZ
5721         {
5722           emit_test(s1h,s1h);
5723           taken=(int)out;
5724           emit_js(1);
5725           nottaken1=(int)out;
5726           emit_jne(2);
5727         }
5728         if((opcode[i]&0x2f)==7) // BGTZ
5729         {
5730           emit_test(s1h,s1h);
5731           nottaken1=(int)out;
5732           emit_js(2);
5733           taken=(int)out;
5734           emit_jne(1);
5735         }
5736       } // if(!only32)
5737
5738       //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5739       assert(s1l>=0);
5740       if((opcode[i]&0x2f)==4) // BEQ
5741       {
5742         if(s2l>=0) emit_cmp(s1l,s2l);
5743         else emit_test(s1l,s1l);
5744         nottaken=(int)out;
5745         emit_jne(2);
5746       }
5747       if((opcode[i]&0x2f)==5) // BNE
5748       {
5749         if(s2l>=0) emit_cmp(s1l,s2l);
5750         else emit_test(s1l,s1l);
5751         nottaken=(int)out;
5752         emit_jeq(2);
5753       }
5754       if((opcode[i]&0x2f)==6) // BLEZ
5755       {
5756         emit_cmpimm(s1l,1);
5757         nottaken=(int)out;
5758         emit_jge(2);
5759       }
5760       if((opcode[i]&0x2f)==7) // BGTZ
5761       {
5762         emit_cmpimm(s1l,1);
5763         nottaken=(int)out;
5764         emit_jl(2);
5765       }
5766     } // if(!unconditional)
5767     int adj;
5768     uint64_t ds_unneeded=branch_regs[i].u;
5769     uint64_t ds_unneeded_upper=branch_regs[i].uu;
5770     ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
5771     ds_unneeded_upper&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
5772     if((~ds_unneeded_upper>>rt1[i+1])&1) ds_unneeded_upper&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
5773     ds_unneeded|=1;
5774     ds_unneeded_upper|=1;
5775     // branch taken
5776     if(!nop) {
5777       if(taken) set_jump_target(taken,(int)out);
5778       assem_debug("1:\n");
5779       wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5780                     ds_unneeded,ds_unneeded_upper);
5781       // load regs
5782       load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
5783       address_generation(i+1,&branch_regs[i],0);
5784       load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,INVCP);
5785       ds_assemble(i+1,&branch_regs[i]);
5786       cc=get_reg(branch_regs[i].regmap,CCREG);
5787       if(cc==-1) {
5788         emit_loadreg(CCREG,cc=HOST_CCREG);
5789         // CHECK: Is the following instruction (fall thru) allocated ok?
5790       }
5791       assert(cc==HOST_CCREG);
5792       store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5793       do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
5794       assem_debug("cycle count (adj)\n");
5795       if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
5796       load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5797       if(internal)
5798         assem_debug("branch: internal\n");
5799       else
5800         assem_debug("branch: external\n");
5801       if(internal&&is_ds[(ba[i]-start)>>2]) {
5802         ds_assemble_entry(i);
5803       }
5804       else {
5805         add_to_linker((int)out,ba[i],internal);
5806         emit_jmp(0);
5807       }
5808     }
5809     // branch not taken
5810     cop1_usable=prev_cop1_usable;
5811     if(!unconditional) {
5812       if(nottaken1) set_jump_target(nottaken1,(int)out);
5813       set_jump_target(nottaken,(int)out);
5814       assem_debug("2:\n");
5815       if(!likely[i]) {
5816         wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5817                       ds_unneeded,ds_unneeded_upper);
5818         load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
5819         address_generation(i+1,&branch_regs[i],0);
5820         load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5821         ds_assemble(i+1,&branch_regs[i]);
5822       }
5823       cc=get_reg(branch_regs[i].regmap,CCREG);
5824       if(cc==-1&&!likely[i]) {
5825         // Cycle count isn't in a register, temporarily load it then write it out
5826         emit_loadreg(CCREG,HOST_CCREG);
5827         emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),HOST_CCREG);
5828         int jaddr=(int)out;
5829         emit_jns(0);
5830         add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
5831         emit_storereg(CCREG,HOST_CCREG);
5832       }
5833       else{
5834         cc=get_reg(i_regmap,CCREG);
5835         assert(cc==HOST_CCREG);
5836         emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),cc);
5837         int jaddr=(int)out;
5838         emit_jns(0);
5839         add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
5840       }
5841     }
5842   }
5843 }
5844
5845 void sjump_assemble(int i,struct regstat *i_regs)
5846 {
5847   signed char *i_regmap=i_regs->regmap;
5848   int cc;
5849   int match;
5850   match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5851   assem_debug("smatch=%d\n",match);
5852   int s1h,s1l;
5853   int prev_cop1_usable=cop1_usable;
5854   int unconditional=0,nevertaken=0;
5855   int only32=0;
5856   int invert=0;
5857   int internal=internal_branch(branch_regs[i].is32,ba[i]);
5858   if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
5859   if(!match) invert=1;
5860   #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5861   if(i>(ba[i]-start)>>2) invert=1;
5862   #endif
5863
5864   //if(opcode2[i]>=0x10) return; // FIXME (BxxZAL)
5865   //assert(opcode2[i]<0x10||rs1[i]==0); // FIXME (BxxZAL)
5866
5867   if(ooo[i]) {
5868     s1l=get_reg(branch_regs[i].regmap,rs1[i]);
5869     s1h=get_reg(branch_regs[i].regmap,rs1[i]|64);
5870   }
5871   else {
5872     s1l=get_reg(i_regmap,rs1[i]);
5873     s1h=get_reg(i_regmap,rs1[i]|64);
5874   }
5875   if(rs1[i]==0)
5876   {
5877     if(opcode2[i]&1) unconditional=1;
5878     else nevertaken=1;
5879     // These are never taken (r0 is never less than zero)
5880     //assert(opcode2[i]!=0);
5881     //assert(opcode2[i]!=2);
5882     //assert(opcode2[i]!=0x10);
5883     //assert(opcode2[i]!=0x12);
5884   }
5885   else {
5886     only32=(regs[i].was32>>rs1[i])&1;
5887   }
5888
5889   if(ooo[i]) {
5890     // Out of order execution (delay slot first)
5891     //printf("OOOE\n");
5892     address_generation(i+1,i_regs,regs[i].regmap_entry);
5893     ds_assemble(i+1,i_regs);
5894     int adj;
5895     uint64_t bc_unneeded=branch_regs[i].u;
5896     uint64_t bc_unneeded_upper=branch_regs[i].uu;
5897     bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
5898     bc_unneeded_upper&=~((1LL<<us1[i])|(1LL<<us2[i]));
5899     bc_unneeded|=1;
5900     bc_unneeded_upper|=1;
5901     wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5902                   bc_unneeded,bc_unneeded_upper);
5903     load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],rs1[i]);
5904     load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5905     if(rt1[i]==31) {
5906       int rt,return_address;
5907       rt=get_reg(branch_regs[i].regmap,31);
5908       assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5909       if(rt>=0) {
5910         // Save the PC even if the branch is not taken
5911         return_address=start+i*4+8;
5912         emit_movimm(return_address,rt); // PC into link register
5913         #ifdef IMM_PREFETCH
5914         if(!nevertaken) emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
5915         #endif
5916       }
5917     }
5918     cc=get_reg(branch_regs[i].regmap,CCREG);
5919     assert(cc==HOST_CCREG);
5920     if(unconditional)
5921       store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5922     //do_cc(i,branch_regs[i].regmap,&adj,unconditional?ba[i]:-1,unconditional);
5923     assem_debug("cycle count (adj)\n");
5924     if(unconditional) {
5925       do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5926       if(i!=(ba[i]-start)>>2 || source[i+1]!=0) {
5927         if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
5928         load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5929         if(internal)
5930           assem_debug("branch: internal\n");
5931         else
5932           assem_debug("branch: external\n");
5933         if(internal&&is_ds[(ba[i]-start)>>2]) {
5934           ds_assemble_entry(i);
5935         }
5936         else {
5937           add_to_linker((int)out,ba[i],internal);
5938           emit_jmp(0);
5939         }
5940         #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5941         if(((u_int)out)&7) emit_addnop(0);
5942         #endif
5943       }
5944     }
5945     else if(nevertaken) {
5946       emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),cc);
5947       int jaddr=(int)out;
5948       emit_jns(0);
5949       add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
5950     }
5951     else {
5952       int nottaken=0;
5953       do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
5954       if(adj&&!invert) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
5955       if(!only32)
5956       {
5957         assert(s1h>=0);
5958         if((opcode2[i]&0xf)==0) // BLTZ/BLTZAL
5959         {
5960           emit_test(s1h,s1h);
5961           if(invert){
5962             nottaken=(int)out;
5963             emit_jns(1);
5964           }else{
5965             add_to_linker((int)out,ba[i],internal);
5966             emit_js(0);
5967           }
5968         }
5969         if((opcode2[i]&0xf)==1) // BGEZ/BLTZAL
5970         {
5971           emit_test(s1h,s1h);
5972           if(invert){
5973             nottaken=(int)out;
5974             emit_js(1);
5975           }else{
5976             add_to_linker((int)out,ba[i],internal);
5977             emit_jns(0);
5978           }
5979         }
5980       } // if(!only32)
5981       else
5982       {
5983         assert(s1l>=0);
5984         if((opcode2[i]&0xf)==0) // BLTZ/BLTZAL
5985         {
5986           emit_test(s1l,s1l);
5987           if(invert){
5988             nottaken=(int)out;
5989             emit_jns(1);
5990           }else{
5991             add_to_linker((int)out,ba[i],internal);
5992             emit_js(0);
5993           }
5994         }
5995         if((opcode2[i]&0xf)==1) // BGEZ/BLTZAL
5996         {
5997           emit_test(s1l,s1l);
5998           if(invert){
5999             nottaken=(int)out;
6000             emit_js(1);
6001           }else{
6002             add_to_linker((int)out,ba[i],internal);
6003             emit_jns(0);
6004           }
6005         }
6006       } // if(!only32)
6007
6008       if(invert) {
6009         #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
6010         if(match&&(!internal||!is_ds[(ba[i]-start)>>2])) {
6011           if(adj) {
6012             emit_addimm(cc,-CLOCK_ADJUST(adj),cc);
6013             add_to_linker((int)out,ba[i],internal);
6014           }else{
6015             emit_addnop(13);
6016             add_to_linker((int)out,ba[i],internal*2);
6017           }
6018           emit_jmp(0);
6019         }else
6020         #endif
6021         {
6022           if(adj) emit_addimm(cc,-CLOCK_ADJUST(adj),cc);
6023           store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6024           load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6025           if(internal)
6026             assem_debug("branch: internal\n");
6027           else
6028             assem_debug("branch: external\n");
6029           if(internal&&is_ds[(ba[i]-start)>>2]) {
6030             ds_assemble_entry(i);
6031           }
6032           else {
6033             add_to_linker((int)out,ba[i],internal);
6034             emit_jmp(0);
6035           }
6036         }
6037         set_jump_target(nottaken,(int)out);
6038       }
6039
6040       if(adj) {
6041         if(!invert) emit_addimm(cc,CLOCK_ADJUST(adj),cc);
6042       }
6043     } // (!unconditional)
6044   } // if(ooo)
6045   else
6046   {
6047     // In-order execution (branch first)
6048     //printf("IOE\n");
6049     int nottaken=0;
6050     if(rt1[i]==31) {
6051       int rt,return_address;
6052       rt=get_reg(branch_regs[i].regmap,31);
6053       if(rt>=0) {
6054         // Save the PC even if the branch is not taken
6055         return_address=start+i*4+8;
6056         emit_movimm(return_address,rt); // PC into link register
6057         #ifdef IMM_PREFETCH
6058         emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
6059         #endif
6060       }
6061     }
6062     if(!unconditional) {
6063       //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
6064       if(!only32)
6065       {
6066         assert(s1h>=0);
6067         if((opcode2[i]&0x0d)==0) // BLTZ/BLTZL/BLTZAL/BLTZALL
6068         {
6069           emit_test(s1h,s1h);
6070           nottaken=(int)out;
6071           emit_jns(1);
6072         }
6073         if((opcode2[i]&0x0d)==1) // BGEZ/BGEZL/BGEZAL/BGEZALL
6074         {
6075           emit_test(s1h,s1h);
6076           nottaken=(int)out;
6077           emit_js(1);
6078         }
6079       } // if(!only32)
6080       else
6081       {
6082         assert(s1l>=0);
6083         if((opcode2[i]&0x0d)==0) // BLTZ/BLTZL/BLTZAL/BLTZALL
6084         {
6085           emit_test(s1l,s1l);
6086           nottaken=(int)out;
6087           emit_jns(1);
6088         }
6089         if((opcode2[i]&0x0d)==1) // BGEZ/BGEZL/BGEZAL/BGEZALL
6090         {
6091           emit_test(s1l,s1l);
6092           nottaken=(int)out;
6093           emit_js(1);
6094         }
6095       }
6096     } // if(!unconditional)
6097     int adj;
6098     uint64_t ds_unneeded=branch_regs[i].u;
6099     uint64_t ds_unneeded_upper=branch_regs[i].uu;
6100     ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6101     ds_unneeded_upper&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6102     if((~ds_unneeded_upper>>rt1[i+1])&1) ds_unneeded_upper&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
6103     ds_unneeded|=1;
6104     ds_unneeded_upper|=1;
6105     // branch taken
6106     if(!nevertaken) {
6107       //assem_debug("1:\n");
6108       wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6109                     ds_unneeded,ds_unneeded_upper);
6110       // load regs
6111       load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
6112       address_generation(i+1,&branch_regs[i],0);
6113       load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,INVCP);
6114       ds_assemble(i+1,&branch_regs[i]);
6115       cc=get_reg(branch_regs[i].regmap,CCREG);
6116       if(cc==-1) {
6117         emit_loadreg(CCREG,cc=HOST_CCREG);
6118         // CHECK: Is the following instruction (fall thru) allocated ok?
6119       }
6120       assert(cc==HOST_CCREG);
6121       store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6122       do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
6123       assem_debug("cycle count (adj)\n");
6124       if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
6125       load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6126       if(internal)
6127         assem_debug("branch: internal\n");
6128       else
6129         assem_debug("branch: external\n");
6130       if(internal&&is_ds[(ba[i]-start)>>2]) {
6131         ds_assemble_entry(i);
6132       }
6133       else {
6134         add_to_linker((int)out,ba[i],internal);
6135         emit_jmp(0);
6136       }
6137     }
6138     // branch not taken
6139     cop1_usable=prev_cop1_usable;
6140     if(!unconditional) {
6141       set_jump_target(nottaken,(int)out);
6142       assem_debug("1:\n");
6143       if(!likely[i]) {
6144         wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6145                       ds_unneeded,ds_unneeded_upper);
6146         load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
6147         address_generation(i+1,&branch_regs[i],0);
6148         load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
6149         ds_assemble(i+1,&branch_regs[i]);
6150       }
6151       cc=get_reg(branch_regs[i].regmap,CCREG);
6152       if(cc==-1&&!likely[i]) {
6153         // Cycle count isn't in a register, temporarily load it then write it out
6154         emit_loadreg(CCREG,HOST_CCREG);
6155         emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),HOST_CCREG);
6156         int jaddr=(int)out;
6157         emit_jns(0);
6158         add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
6159         emit_storereg(CCREG,HOST_CCREG);
6160       }
6161       else{
6162         cc=get_reg(i_regmap,CCREG);
6163         assert(cc==HOST_CCREG);
6164         emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),cc);
6165         int jaddr=(int)out;
6166         emit_jns(0);
6167         add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
6168       }
6169     }
6170   }
6171 }
6172
6173 void fjump_assemble(int i,struct regstat *i_regs)
6174 {
6175   signed char *i_regmap=i_regs->regmap;
6176   int cc;
6177   int match;
6178   match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6179   assem_debug("fmatch=%d\n",match);
6180   int fs,cs;
6181   int eaddr;
6182   int invert=0;
6183   int internal=internal_branch(branch_regs[i].is32,ba[i]);
6184   if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
6185   if(!match) invert=1;
6186   #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
6187   if(i>(ba[i]-start)>>2) invert=1;
6188   #endif
6189
6190   if(ooo[i]) {
6191     fs=get_reg(branch_regs[i].regmap,FSREG);
6192     address_generation(i+1,i_regs,regs[i].regmap_entry); // Is this okay?
6193   }
6194   else {
6195     fs=get_reg(i_regmap,FSREG);
6196   }
6197
6198   // Check cop1 unusable
6199   if(!cop1_usable) {
6200     cs=get_reg(i_regmap,CSREG);
6201     assert(cs>=0);
6202     emit_testimm(cs,0x20000000);
6203     eaddr=(int)out;
6204     emit_jeq(0);
6205     add_stub(FP_STUB,eaddr,(int)out,i,cs,(int)i_regs,0,0);
6206     cop1_usable=1;
6207   }
6208
6209   if(ooo[i]) {
6210     // Out of order execution (delay slot first)
6211     //printf("OOOE\n");
6212     ds_assemble(i+1,i_regs);
6213     int adj;
6214     uint64_t bc_unneeded=branch_regs[i].u;
6215     uint64_t bc_unneeded_upper=branch_regs[i].uu;
6216     bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
6217     bc_unneeded_upper&=~((1LL<<us1[i])|(1LL<<us2[i]));
6218     bc_unneeded|=1;
6219     bc_unneeded_upper|=1;
6220     wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6221                   bc_unneeded,bc_unneeded_upper);
6222     load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],rs1[i]);
6223     load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
6224     cc=get_reg(branch_regs[i].regmap,CCREG);
6225     assert(cc==HOST_CCREG);
6226     do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
6227     assem_debug("cycle count (adj)\n");
6228     if(1) {
6229       int nottaken=0;
6230       if(adj&&!invert) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
6231       if(1) {
6232         assert(fs>=0);
6233         emit_testimm(fs,0x800000);
6234         if(source[i]&0x10000) // BC1T
6235         {
6236           if(invert){
6237             nottaken=(int)out;
6238             emit_jeq(1);
6239           }else{
6240             add_to_linker((int)out,ba[i],internal);
6241             emit_jne(0);
6242           }
6243         }
6244         else // BC1F
6245           if(invert){
6246             nottaken=(int)out;
6247             emit_jne(1);
6248           }else{
6249             add_to_linker((int)out,ba[i],internal);
6250             emit_jeq(0);
6251           }
6252         {
6253         }
6254       } // if(!only32)
6255
6256       if(invert) {
6257         if(adj) emit_addimm(cc,-CLOCK_ADJUST(adj),cc);
6258         #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
6259         else if(match) emit_addnop(13);
6260         #endif
6261         store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6262         load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6263         if(internal)
6264           assem_debug("branch: internal\n");
6265         else
6266           assem_debug("branch: external\n");
6267         if(internal&&is_ds[(ba[i]-start)>>2]) {
6268           ds_assemble_entry(i);
6269         }
6270         else {
6271           add_to_linker((int)out,ba[i],internal);
6272           emit_jmp(0);
6273         }
6274         set_jump_target(nottaken,(int)out);
6275       }
6276
6277       if(adj) {
6278         if(!invert) emit_addimm(cc,CLOCK_ADJUST(adj),cc);
6279       }
6280     } // (!unconditional)
6281   } // if(ooo)
6282   else
6283   {
6284     // In-order execution (branch first)
6285     //printf("IOE\n");
6286     int nottaken=0;
6287     if(1) {
6288       //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
6289       if(1) {
6290         assert(fs>=0);
6291         emit_testimm(fs,0x800000);
6292         if(source[i]&0x10000) // BC1T
6293         {
6294           nottaken=(int)out;
6295           emit_jeq(1);
6296         }
6297         else // BC1F
6298         {
6299           nottaken=(int)out;
6300           emit_jne(1);
6301         }
6302       }
6303     } // if(!unconditional)
6304     int adj;
6305     uint64_t ds_unneeded=branch_regs[i].u;
6306     uint64_t ds_unneeded_upper=branch_regs[i].uu;
6307     ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6308     ds_unneeded_upper&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6309     if((~ds_unneeded_upper>>rt1[i+1])&1) ds_unneeded_upper&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
6310     ds_unneeded|=1;
6311     ds_unneeded_upper|=1;
6312     // branch taken
6313     //assem_debug("1:\n");
6314     wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6315                   ds_unneeded,ds_unneeded_upper);
6316     // load regs
6317     load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
6318     address_generation(i+1,&branch_regs[i],0);
6319     load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,INVCP);
6320     ds_assemble(i+1,&branch_regs[i]);
6321     cc=get_reg(branch_regs[i].regmap,CCREG);
6322     if(cc==-1) {
6323       emit_loadreg(CCREG,cc=HOST_CCREG);
6324       // CHECK: Is the following instruction (fall thru) allocated ok?
6325     }
6326     assert(cc==HOST_CCREG);
6327     store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6328     do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
6329     assem_debug("cycle count (adj)\n");
6330     if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
6331     load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6332     if(internal)
6333       assem_debug("branch: internal\n");
6334     else
6335       assem_debug("branch: external\n");
6336     if(internal&&is_ds[(ba[i]-start)>>2]) {
6337       ds_assemble_entry(i);
6338     }
6339     else {
6340       add_to_linker((int)out,ba[i],internal);
6341       emit_jmp(0);
6342     }
6343
6344     // branch not taken
6345     if(1) { // <- FIXME (don't need this)
6346       set_jump_target(nottaken,(int)out);
6347       assem_debug("1:\n");
6348       if(!likely[i]) {
6349         wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6350                       ds_unneeded,ds_unneeded_upper);
6351         load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
6352         address_generation(i+1,&branch_regs[i],0);
6353         load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
6354         ds_assemble(i+1,&branch_regs[i]);
6355       }
6356       cc=get_reg(branch_regs[i].regmap,CCREG);
6357       if(cc==-1&&!likely[i]) {
6358         // Cycle count isn't in a register, temporarily load it then write it out
6359         emit_loadreg(CCREG,HOST_CCREG);
6360         emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),HOST_CCREG);
6361         int jaddr=(int)out;
6362         emit_jns(0);
6363         add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
6364         emit_storereg(CCREG,HOST_CCREG);
6365       }
6366       else{
6367         cc=get_reg(i_regmap,CCREG);
6368         assert(cc==HOST_CCREG);
6369         emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),cc);
6370         int jaddr=(int)out;
6371         emit_jns(0);
6372         add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
6373       }
6374     }
6375   }
6376 }
6377
6378 static void pagespan_assemble(int i,struct regstat *i_regs)
6379 {
6380   int s1l=get_reg(i_regs->regmap,rs1[i]);
6381   int s1h=get_reg(i_regs->regmap,rs1[i]|64);
6382   int s2l=get_reg(i_regs->regmap,rs2[i]);
6383   int s2h=get_reg(i_regs->regmap,rs2[i]|64);
6384   void *nt_branch=NULL;
6385   int taken=0;
6386   int nottaken=0;
6387   int unconditional=0;
6388   if(rs1[i]==0)
6389   {
6390     s1l=s2l;s1h=s2h;
6391     s2l=s2h=-1;
6392   }
6393   else if(rs2[i]==0)
6394   {
6395     s2l=s2h=-1;
6396   }
6397   if((i_regs->is32>>rs1[i])&(i_regs->is32>>rs2[i])&1) {
6398     s1h=s2h=-1;
6399   }
6400   int hr=0;
6401   int addr,alt,ntaddr;
6402   if(i_regs->regmap[HOST_BTREG]<0) {addr=HOST_BTREG;}
6403   else {
6404     while(hr<HOST_REGS)
6405     {
6406       if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
6407          (i_regs->regmap[hr]&63)!=rs1[i] &&
6408          (i_regs->regmap[hr]&63)!=rs2[i] )
6409       {
6410         addr=hr++;break;
6411       }
6412       hr++;
6413     }
6414   }
6415   while(hr<HOST_REGS)
6416   {
6417     if(hr!=EXCLUDE_REG && hr!=HOST_CCREG && hr!=HOST_BTREG &&
6418        (i_regs->regmap[hr]&63)!=rs1[i] &&
6419        (i_regs->regmap[hr]&63)!=rs2[i] )
6420     {
6421       alt=hr++;break;
6422     }
6423     hr++;
6424   }
6425   if((opcode[i]&0x2E)==6) // BLEZ/BGTZ needs another register
6426   {
6427     while(hr<HOST_REGS)
6428     {
6429       if(hr!=EXCLUDE_REG && hr!=HOST_CCREG && hr!=HOST_BTREG &&
6430          (i_regs->regmap[hr]&63)!=rs1[i] &&
6431          (i_regs->regmap[hr]&63)!=rs2[i] )
6432       {
6433         ntaddr=hr;break;
6434       }
6435       hr++;
6436     }
6437   }
6438   assert(hr<HOST_REGS);
6439   if((opcode[i]&0x2e)==4||opcode[i]==0x11) { // BEQ/BNE/BEQL/BNEL/BC1
6440     load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,CCREG,CCREG);
6441   }
6442   emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i]+2),HOST_CCREG);
6443   if(opcode[i]==2) // J
6444   {
6445     unconditional=1;
6446   }
6447   if(opcode[i]==3) // JAL
6448   {
6449     // TODO: mini_ht
6450     int rt=get_reg(i_regs->regmap,31);
6451     emit_movimm(start+i*4+8,rt);
6452     unconditional=1;
6453   }
6454   if(opcode[i]==0&&(opcode2[i]&0x3E)==8) // JR/JALR
6455   {
6456     emit_mov(s1l,addr);
6457     if(opcode2[i]==9) // JALR
6458     {
6459       int rt=get_reg(i_regs->regmap,rt1[i]);
6460       emit_movimm(start+i*4+8,rt);
6461     }
6462   }
6463   if((opcode[i]&0x3f)==4) // BEQ
6464   {
6465     if(rs1[i]==rs2[i])
6466     {
6467       unconditional=1;
6468     }
6469     else
6470     #ifdef HAVE_CMOV_IMM
6471     if(s1h<0) {
6472       if(s2l>=0) emit_cmp(s1l,s2l);
6473       else emit_test(s1l,s1l);
6474       emit_cmov2imm_e_ne_compact(ba[i],start+i*4+8,addr);
6475     }
6476     else
6477     #endif
6478     {
6479       assert(s1l>=0);
6480       emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
6481       if(s1h>=0) {
6482         if(s2h>=0) emit_cmp(s1h,s2h);
6483         else emit_test(s1h,s1h);
6484         emit_cmovne_reg(alt,addr);
6485       }
6486       if(s2l>=0) emit_cmp(s1l,s2l);
6487       else emit_test(s1l,s1l);
6488       emit_cmovne_reg(alt,addr);
6489     }
6490   }
6491   if((opcode[i]&0x3f)==5) // BNE
6492   {
6493     #ifdef HAVE_CMOV_IMM
6494     if(s1h<0) {
6495       if(s2l>=0) emit_cmp(s1l,s2l);
6496       else emit_test(s1l,s1l);
6497       emit_cmov2imm_e_ne_compact(start+i*4+8,ba[i],addr);
6498     }
6499     else
6500     #endif
6501     {
6502       assert(s1l>=0);
6503       emit_mov2imm_compact(start+i*4+8,addr,ba[i],alt);
6504       if(s1h>=0) {
6505         if(s2h>=0) emit_cmp(s1h,s2h);
6506         else emit_test(s1h,s1h);
6507         emit_cmovne_reg(alt,addr);
6508       }
6509       if(s2l>=0) emit_cmp(s1l,s2l);
6510       else emit_test(s1l,s1l);
6511       emit_cmovne_reg(alt,addr);
6512     }
6513   }
6514   if((opcode[i]&0x3f)==0x14) // BEQL
6515   {
6516     if(s1h>=0) {
6517       if(s2h>=0) emit_cmp(s1h,s2h);
6518       else emit_test(s1h,s1h);
6519       nottaken=(int)out;
6520       emit_jne(0);
6521     }
6522     if(s2l>=0) emit_cmp(s1l,s2l);
6523     else emit_test(s1l,s1l);
6524     if(nottaken) set_jump_target(nottaken,(int)out);
6525     nottaken=(int)out;
6526     emit_jne(0);
6527   }
6528   if((opcode[i]&0x3f)==0x15) // BNEL
6529   {
6530     if(s1h>=0) {
6531       if(s2h>=0) emit_cmp(s1h,s2h);
6532       else emit_test(s1h,s1h);
6533       taken=(int)out;
6534       emit_jne(0);
6535     }
6536     if(s2l>=0) emit_cmp(s1l,s2l);
6537     else emit_test(s1l,s1l);
6538     nottaken=(int)out;
6539     emit_jeq(0);
6540     if(taken) set_jump_target(taken,(int)out);
6541   }
6542   if((opcode[i]&0x3f)==6) // BLEZ
6543   {
6544     emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
6545     emit_cmpimm(s1l,1);
6546     if(s1h>=0) emit_mov(addr,ntaddr);
6547     emit_cmovl_reg(alt,addr);
6548     if(s1h>=0) {
6549       emit_test(s1h,s1h);
6550       emit_cmovne_reg(ntaddr,addr);
6551       emit_cmovs_reg(alt,addr);
6552     }
6553   }
6554   if((opcode[i]&0x3f)==7) // BGTZ
6555   {
6556     emit_mov2imm_compact(ba[i],addr,start+i*4+8,ntaddr);
6557     emit_cmpimm(s1l,1);
6558     if(s1h>=0) emit_mov(addr,alt);
6559     emit_cmovl_reg(ntaddr,addr);
6560     if(s1h>=0) {
6561       emit_test(s1h,s1h);
6562       emit_cmovne_reg(alt,addr);
6563       emit_cmovs_reg(ntaddr,addr);
6564     }
6565   }
6566   if((opcode[i]&0x3f)==0x16) // BLEZL
6567   {
6568     assert((opcode[i]&0x3f)!=0x16);
6569   }
6570   if((opcode[i]&0x3f)==0x17) // BGTZL
6571   {
6572     assert((opcode[i]&0x3f)!=0x17);
6573   }
6574   assert(opcode[i]!=1); // BLTZ/BGEZ
6575
6576   //FIXME: Check CSREG
6577   if(opcode[i]==0x11 && opcode2[i]==0x08 ) {
6578     if((source[i]&0x30000)==0) // BC1F
6579     {
6580       emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
6581       emit_testimm(s1l,0x800000);
6582       emit_cmovne_reg(alt,addr);
6583     }
6584     if((source[i]&0x30000)==0x10000) // BC1T
6585     {
6586       emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
6587       emit_testimm(s1l,0x800000);
6588       emit_cmovne_reg(alt,addr);
6589     }
6590     if((source[i]&0x30000)==0x20000) // BC1FL
6591     {
6592       emit_testimm(s1l,0x800000);
6593       nottaken=(int)out;
6594       emit_jne(0);
6595     }
6596     if((source[i]&0x30000)==0x30000) // BC1TL
6597     {
6598       emit_testimm(s1l,0x800000);
6599       nottaken=(int)out;
6600       emit_jeq(0);
6601     }
6602   }
6603
6604   assert(i_regs->regmap[HOST_CCREG]==CCREG);
6605   wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty);
6606   if(likely[i]||unconditional)
6607   {
6608     emit_movimm(ba[i],HOST_BTREG);
6609   }
6610   else if(addr!=HOST_BTREG)
6611   {
6612     emit_mov(addr,HOST_BTREG);
6613   }
6614   void *branch_addr=out;
6615   emit_jmp(0);
6616   int target_addr=start+i*4+5;
6617   void *stub=out;
6618   void *compiled_target_addr=check_addr(target_addr);
6619   emit_extjump_ds((int)branch_addr,target_addr);
6620   if(compiled_target_addr) {
6621     set_jump_target((int)branch_addr,(int)compiled_target_addr);
6622     add_link(target_addr,stub);
6623   }
6624   else set_jump_target((int)branch_addr,(int)stub);
6625   if(likely[i]) {
6626     // Not-taken path
6627     set_jump_target((int)nottaken,(int)out);
6628     wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty);
6629     void *branch_addr=out;
6630     emit_jmp(0);
6631     int target_addr=start+i*4+8;
6632     void *stub=out;
6633     void *compiled_target_addr=check_addr(target_addr);
6634     emit_extjump_ds((int)branch_addr,target_addr);
6635     if(compiled_target_addr) {
6636       set_jump_target((int)branch_addr,(int)compiled_target_addr);
6637       add_link(target_addr,stub);
6638     }
6639     else set_jump_target((int)branch_addr,(int)stub);
6640   }
6641 }
6642
6643 // Assemble the delay slot for the above
6644 static void pagespan_ds()
6645 {
6646   assem_debug("initial delay slot:\n");
6647   u_int vaddr=start+1;
6648   u_int page=get_page(vaddr);
6649   u_int vpage=get_vpage(vaddr);
6650   ll_add(jump_dirty+vpage,vaddr,(void *)out);
6651   do_dirty_stub_ds();
6652   ll_add(jump_in+page,vaddr,(void *)out);
6653   assert(regs[0].regmap_entry[HOST_CCREG]==CCREG);
6654   if(regs[0].regmap[HOST_CCREG]!=CCREG)
6655     wb_register(CCREG,regs[0].regmap_entry,regs[0].wasdirty,regs[0].was32);
6656   if(regs[0].regmap[HOST_BTREG]!=BTREG)
6657     emit_writeword(HOST_BTREG,(int)&branch_target);
6658   load_regs(regs[0].regmap_entry,regs[0].regmap,regs[0].was32,rs1[0],rs2[0]);
6659   address_generation(0,&regs[0],regs[0].regmap_entry);
6660   if(itype[0]==STORE||itype[0]==STORELR||(opcode[0]&0x3b)==0x39||(opcode[0]&0x3b)==0x3a)
6661     load_regs(regs[0].regmap_entry,regs[0].regmap,regs[0].was32,INVCP,INVCP);
6662   cop1_usable=0;
6663   is_delayslot=0;
6664   switch(itype[0]) {
6665     case ALU:
6666       alu_assemble(0,&regs[0]);break;
6667     case IMM16:
6668       imm16_assemble(0,&regs[0]);break;
6669     case SHIFT:
6670       shift_assemble(0,&regs[0]);break;
6671     case SHIFTIMM:
6672       shiftimm_assemble(0,&regs[0]);break;
6673     case LOAD:
6674       load_assemble(0,&regs[0]);break;
6675     case LOADLR:
6676       loadlr_assemble(0,&regs[0]);break;
6677     case STORE:
6678       store_assemble(0,&regs[0]);break;
6679     case STORELR:
6680       storelr_assemble(0,&regs[0]);break;
6681     case COP0:
6682       cop0_assemble(0,&regs[0]);break;
6683     case COP1:
6684       cop1_assemble(0,&regs[0]);break;
6685     case C1LS:
6686       c1ls_assemble(0,&regs[0]);break;
6687     case COP2:
6688       cop2_assemble(0,&regs[0]);break;
6689     case C2LS:
6690       c2ls_assemble(0,&regs[0]);break;
6691     case C2OP:
6692       c2op_assemble(0,&regs[0]);break;
6693     case FCONV:
6694       fconv_assemble(0,&regs[0]);break;
6695     case FLOAT:
6696       float_assemble(0,&regs[0]);break;
6697     case FCOMP:
6698       fcomp_assemble(0,&regs[0]);break;
6699     case MULTDIV:
6700       multdiv_assemble(0,&regs[0]);break;
6701     case MOV:
6702       mov_assemble(0,&regs[0]);break;
6703     case SYSCALL:
6704     case HLECALL:
6705     case INTCALL:
6706     case SPAN:
6707     case UJUMP:
6708     case RJUMP:
6709     case CJUMP:
6710     case SJUMP:
6711     case FJUMP:
6712       printf("Jump in the delay slot.  This is probably a bug.\n");
6713   }
6714   int btaddr=get_reg(regs[0].regmap,BTREG);
6715   if(btaddr<0) {
6716     btaddr=get_reg(regs[0].regmap,-1);
6717     emit_readword((int)&branch_target,btaddr);
6718   }
6719   assert(btaddr!=HOST_CCREG);
6720   if(regs[0].regmap[HOST_CCREG]!=CCREG) emit_loadreg(CCREG,HOST_CCREG);
6721 #ifdef HOST_IMM8
6722   emit_movimm(start+4,HOST_TEMPREG);
6723   emit_cmp(btaddr,HOST_TEMPREG);
6724 #else
6725   emit_cmpimm(btaddr,start+4);
6726 #endif
6727   int branch=(int)out;
6728   emit_jeq(0);
6729   store_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,-1);
6730   emit_jmp(jump_vaddr_reg[btaddr]);
6731   set_jump_target(branch,(int)out);
6732   store_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,start+4);
6733   load_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,start+4);
6734 }
6735
6736 // Basic liveness analysis for MIPS registers
6737 void unneeded_registers(int istart,int iend,int r)
6738 {
6739   int i;
6740   uint64_t u,uu,gte_u,b,bu,gte_bu;
6741   uint64_t temp_u,temp_uu,temp_gte_u;
6742   uint64_t tdep;
6743   if(iend==slen-1) {
6744     u=1;uu=1;
6745   }else{
6746     u=unneeded_reg[iend+1];
6747     uu=unneeded_reg_upper[iend+1];
6748     u=1;uu=1;
6749   }
6750   gte_u=temp_gte_u=0;
6751
6752   for (i=iend;i>=istart;i--)
6753   {
6754     //printf("unneeded registers i=%d (%d,%d) r=%d\n",i,istart,iend,r);
6755     if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
6756     {
6757       // If subroutine call, flag return address as a possible branch target
6758       if(rt1[i]==31 && i<slen-2) bt[i+2]=1;
6759
6760       if(ba[i]<start || ba[i]>=(start+slen*4))
6761       {
6762         // Branch out of this block, flush all regs
6763         u=1;
6764         uu=1;
6765         gte_u=0;
6766         /* Hexagon hack
6767         if(itype[i]==UJUMP&&rt1[i]==31)
6768         {
6769           uu=u=0x300C00F; // Discard at, v0-v1, t6-t9
6770         }
6771         if(itype[i]==RJUMP&&rs1[i]==31)
6772         {
6773           uu=u=0x300C0F3; // Discard at, a0-a3, t6-t9
6774         }
6775         if(start>0x80000400&&start<0x80000000+RAM_SIZE) {
6776           if(itype[i]==UJUMP&&rt1[i]==31)
6777           {
6778             //uu=u=0x30300FF0FLL; // Discard at, v0-v1, t0-t9, lo, hi
6779             uu=u=0x300FF0F; // Discard at, v0-v1, t0-t9
6780           }
6781           if(itype[i]==RJUMP&&rs1[i]==31)
6782           {
6783             //uu=u=0x30300FFF3LL; // Discard at, a0-a3, t0-t9, lo, hi
6784             uu=u=0x300FFF3; // Discard at, a0-a3, t0-t9
6785           }
6786         }*/
6787         branch_unneeded_reg[i]=u;
6788         branch_unneeded_reg_upper[i]=uu;
6789         // Merge in delay slot
6790         tdep=(~uu>>rt1[i+1])&1;
6791         u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6792         uu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6793         u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6794         uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6795         uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6796         u|=1;uu|=1;
6797         gte_u|=gte_rt[i+1];
6798         gte_u&=~gte_rs[i+1];
6799         // If branch is "likely" (and conditional)
6800         // then we skip the delay slot on the fall-thru path
6801         if(likely[i]) {
6802           if(i<slen-1) {
6803             u&=unneeded_reg[i+2];
6804             uu&=unneeded_reg_upper[i+2];
6805             gte_u&=gte_unneeded[i+2];
6806           }
6807           else
6808           {
6809             u=1;
6810             uu=1;
6811             gte_u=0;
6812           }
6813         }
6814       }
6815       else
6816       {
6817         // Internal branch, flag target
6818         bt[(ba[i]-start)>>2]=1;
6819         if(ba[i]<=start+i*4) {
6820           // Backward branch
6821           if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
6822           {
6823             // Unconditional branch
6824             temp_u=1;temp_uu=1;
6825             temp_gte_u=0;
6826           } else {
6827             // Conditional branch (not taken case)
6828             temp_u=unneeded_reg[i+2];
6829             temp_uu=unneeded_reg_upper[i+2];
6830             temp_gte_u&=gte_unneeded[i+2];
6831           }
6832           // Merge in delay slot
6833           tdep=(~temp_uu>>rt1[i+1])&1;
6834           temp_u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6835           temp_uu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6836           temp_u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6837           temp_uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6838           temp_uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6839           temp_u|=1;temp_uu|=1;
6840           temp_gte_u|=gte_rt[i+1];
6841           temp_gte_u&=~gte_rs[i+1];
6842           // If branch is "likely" (and conditional)
6843           // then we skip the delay slot on the fall-thru path
6844           if(likely[i]) {
6845             if(i<slen-1) {
6846               temp_u&=unneeded_reg[i+2];
6847               temp_uu&=unneeded_reg_upper[i+2];
6848               temp_gte_u&=gte_unneeded[i+2];
6849             }
6850             else
6851             {
6852               temp_u=1;
6853               temp_uu=1;
6854               temp_gte_u=0;
6855             }
6856           }
6857           tdep=(~temp_uu>>rt1[i])&1;
6858           temp_u|=(1LL<<rt1[i])|(1LL<<rt2[i]);
6859           temp_uu|=(1LL<<rt1[i])|(1LL<<rt2[i]);
6860           temp_u&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
6861           temp_uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
6862           temp_uu&=~((tdep<<dep1[i])|(tdep<<dep2[i]));
6863           temp_u|=1;temp_uu|=1;
6864           temp_gte_u|=gte_rt[i];
6865           temp_gte_u&=~gte_rs[i];
6866           unneeded_reg[i]=temp_u;
6867           unneeded_reg_upper[i]=temp_uu;
6868           gte_unneeded[i]=temp_gte_u;
6869           // Only go three levels deep.  This recursion can take an
6870           // excessive amount of time if there are a lot of nested loops.
6871           if(r<2) {
6872             unneeded_registers((ba[i]-start)>>2,i-1,r+1);
6873           }else{
6874             unneeded_reg[(ba[i]-start)>>2]=1;
6875             unneeded_reg_upper[(ba[i]-start)>>2]=1;
6876             gte_unneeded[(ba[i]-start)>>2]=0;
6877           }
6878         } /*else*/ if(1) {
6879           if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
6880           {
6881             // Unconditional branch
6882             u=unneeded_reg[(ba[i]-start)>>2];
6883             uu=unneeded_reg_upper[(ba[i]-start)>>2];
6884             gte_u=gte_unneeded[(ba[i]-start)>>2];
6885             branch_unneeded_reg[i]=u;
6886             branch_unneeded_reg_upper[i]=uu;
6887         //u=1;
6888         //uu=1;
6889         //branch_unneeded_reg[i]=u;
6890         //branch_unneeded_reg_upper[i]=uu;
6891             // Merge in delay slot
6892             tdep=(~uu>>rt1[i+1])&1;
6893             u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6894             uu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6895             u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6896             uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6897             uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6898             u|=1;uu|=1;
6899             gte_u|=gte_rt[i+1];
6900             gte_u&=~gte_rs[i+1];
6901           } else {
6902             // Conditional branch
6903             b=unneeded_reg[(ba[i]-start)>>2];
6904             bu=unneeded_reg_upper[(ba[i]-start)>>2];
6905             gte_bu=gte_unneeded[(ba[i]-start)>>2];
6906             branch_unneeded_reg[i]=b;
6907             branch_unneeded_reg_upper[i]=bu;
6908         //b=1;
6909         //bu=1;
6910         //branch_unneeded_reg[i]=b;
6911         //branch_unneeded_reg_upper[i]=bu;
6912             // Branch delay slot
6913             tdep=(~uu>>rt1[i+1])&1;
6914             b|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6915             bu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6916             b&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6917             bu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6918             bu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6919             b|=1;bu|=1;
6920             gte_bu|=gte_rt[i+1];
6921             gte_bu&=~gte_rs[i+1];
6922             // If branch is "likely" then we skip the
6923             // delay slot on the fall-thru path
6924             if(likely[i]) {
6925               u=b;
6926               uu=bu;
6927               gte_u=gte_bu;
6928               if(i<slen-1) {
6929                 u&=unneeded_reg[i+2];
6930                 uu&=unneeded_reg_upper[i+2];
6931                 gte_u&=gte_unneeded[i+2];
6932         //u=1;
6933         //uu=1;
6934               }
6935             } else {
6936               u&=b;
6937               uu&=bu;
6938               gte_u&=gte_bu;
6939         //u=1;
6940         //uu=1;
6941             }
6942             if(i<slen-1) {
6943               branch_unneeded_reg[i]&=unneeded_reg[i+2];
6944               branch_unneeded_reg_upper[i]&=unneeded_reg_upper[i+2];
6945         //branch_unneeded_reg[i]=1;
6946         //branch_unneeded_reg_upper[i]=1;
6947             } else {
6948               branch_unneeded_reg[i]=1;
6949               branch_unneeded_reg_upper[i]=1;
6950             }
6951           }
6952         }
6953       }
6954     }
6955     else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
6956     {
6957       // SYSCALL instruction (software interrupt)
6958       u=1;
6959       uu=1;
6960     }
6961     else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
6962     {
6963       // ERET instruction (return from interrupt)
6964       u=1;
6965       uu=1;
6966     }
6967     //u=uu=1; // DEBUG
6968     tdep=(~uu>>rt1[i])&1;
6969     // Written registers are unneeded
6970     u|=1LL<<rt1[i];
6971     u|=1LL<<rt2[i];
6972     uu|=1LL<<rt1[i];
6973     uu|=1LL<<rt2[i];
6974     gte_u|=gte_rt[i];
6975     // Accessed registers are needed
6976     u&=~(1LL<<rs1[i]);
6977     u&=~(1LL<<rs2[i]);
6978     uu&=~(1LL<<us1[i]);
6979     uu&=~(1LL<<us2[i]);
6980     gte_u&=~gte_rs[i];
6981     // Source-target dependencies
6982     uu&=~(tdep<<dep1[i]);
6983     uu&=~(tdep<<dep2[i]);
6984     // R0 is always unneeded
6985     u|=1;uu|=1;
6986     // Save it
6987     unneeded_reg[i]=u;
6988     unneeded_reg_upper[i]=uu;
6989     gte_unneeded[i]=gte_u;
6990     /*
6991     printf("ur (%d,%d) %x: ",istart,iend,start+i*4);
6992     printf("U:");
6993     int r;
6994     for(r=1;r<=CCREG;r++) {
6995       if((unneeded_reg[i]>>r)&1) {
6996         if(r==HIREG) printf(" HI");
6997         else if(r==LOREG) printf(" LO");
6998         else printf(" r%d",r);
6999       }
7000     }
7001     printf(" UU:");
7002     for(r=1;r<=CCREG;r++) {
7003       if(((unneeded_reg_upper[i]&~unneeded_reg[i])>>r)&1) {
7004         if(r==HIREG) printf(" HI");
7005         else if(r==LOREG) printf(" LO");
7006         else printf(" r%d",r);
7007       }
7008     }
7009     printf("\n");*/
7010   }
7011 #ifdef FORCE32
7012   for (i=iend;i>=istart;i--)
7013   {
7014     unneeded_reg_upper[i]=branch_unneeded_reg_upper[i]=-1LL;
7015   }
7016 #endif
7017 }
7018
7019 // Identify registers which are likely to contain 32-bit values
7020 // This is used to predict whether any branches will jump to a
7021 // location with 64-bit values in registers.
7022 static void provisional_32bit()
7023 {
7024   int i,j;
7025   uint64_t is32=1;
7026   uint64_t lastbranch=1;
7027
7028   for(i=0;i<slen;i++)
7029   {
7030     if(i>0) {
7031       if(itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP) {
7032         if(i>1) is32=lastbranch;
7033         else is32=1;
7034       }
7035     }
7036     if(i>1)
7037     {
7038       if(itype[i-2]==CJUMP||itype[i-2]==SJUMP||itype[i-2]==FJUMP) {
7039         if(likely[i-2]) {
7040           if(i>2) is32=lastbranch;
7041           else is32=1;
7042         }
7043       }
7044       if((opcode[i-2]&0x2f)==0x05) // BNE/BNEL
7045       {
7046         if(rs1[i-2]==0||rs2[i-2]==0)
7047         {
7048           if(rs1[i-2]) {
7049             is32|=1LL<<rs1[i-2];
7050           }
7051           if(rs2[i-2]) {
7052             is32|=1LL<<rs2[i-2];
7053           }
7054         }
7055       }
7056     }
7057     // If something jumps here with 64-bit values
7058     // then promote those registers to 64 bits
7059     if(bt[i])
7060     {
7061       uint64_t temp_is32=is32;
7062       for(j=i-1;j>=0;j--)
7063       {
7064         if(ba[j]==start+i*4)
7065           //temp_is32&=branch_regs[j].is32;
7066           temp_is32&=p32[j];
7067       }
7068       for(j=i;j<slen;j++)
7069       {
7070         if(ba[j]==start+i*4)
7071           temp_is32=1;
7072       }
7073       is32=temp_is32;
7074     }
7075     int type=itype[i];
7076     int op=opcode[i];
7077     int op2=opcode2[i];
7078     int rt=rt1[i];
7079     int s1=rs1[i];
7080     int s2=rs2[i];
7081     if(type==UJUMP||type==RJUMP||type==CJUMP||type==SJUMP||type==FJUMP) {
7082       // Branches don't write registers, consider the delay slot instead.
7083       type=itype[i+1];
7084       op=opcode[i+1];
7085       op2=opcode2[i+1];
7086       rt=rt1[i+1];
7087       s1=rs1[i+1];
7088       s2=rs2[i+1];
7089       lastbranch=is32;
7090     }
7091     switch(type) {
7092       case LOAD:
7093         if(opcode[i]==0x27||opcode[i]==0x37|| // LWU/LD
7094            opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
7095           is32&=~(1LL<<rt);
7096         else
7097           is32|=1LL<<rt;
7098         break;
7099       case STORE:
7100       case STORELR:
7101         break;
7102       case LOADLR:
7103         if(op==0x1a||op==0x1b) is32&=~(1LL<<rt); // LDR/LDL
7104         if(op==0x22) is32|=1LL<<rt; // LWL
7105         break;
7106       case IMM16:
7107         if (op==0x08||op==0x09|| // ADDI/ADDIU
7108             op==0x0a||op==0x0b|| // SLTI/SLTIU
7109             op==0x0c|| // ANDI
7110             op==0x0f)  // LUI
7111         {
7112           is32|=1LL<<rt;
7113         }
7114         if(op==0x18||op==0x19) { // DADDI/DADDIU
7115           is32&=~(1LL<<rt);
7116           //if(imm[i]==0)
7117           //  is32|=((is32>>s1)&1LL)<<rt;
7118         }
7119         if(op==0x0d||op==0x0e) { // ORI/XORI
7120           uint64_t sr=((is32>>s1)&1LL);
7121           is32&=~(1LL<<rt);
7122           is32|=sr<<rt;
7123         }
7124         break;
7125       case UJUMP:
7126         break;
7127       case RJUMP:
7128         break;
7129       case CJUMP:
7130         break;
7131       case SJUMP:
7132         break;
7133       case FJUMP:
7134         break;
7135       case ALU:
7136         if(op2>=0x20&&op2<=0x23) { // ADD/ADDU/SUB/SUBU
7137           is32|=1LL<<rt;
7138         }
7139         if(op2==0x2a||op2==0x2b) { // SLT/SLTU
7140           is32|=1LL<<rt;
7141         }
7142         else if(op2>=0x24&&op2<=0x27) { // AND/OR/XOR/NOR
7143           uint64_t sr=((is32>>s1)&(is32>>s2)&1LL);
7144           is32&=~(1LL<<rt);
7145           is32|=sr<<rt;
7146         }
7147         else if(op2>=0x2c&&op2<=0x2d) { // DADD/DADDU
7148           if(s1==0&&s2==0) {
7149             is32|=1LL<<rt;
7150           }
7151           else if(s2==0) {
7152             uint64_t sr=((is32>>s1)&1LL);
7153             is32&=~(1LL<<rt);
7154             is32|=sr<<rt;
7155           }
7156           else if(s1==0) {
7157             uint64_t sr=((is32>>s2)&1LL);
7158             is32&=~(1LL<<rt);
7159             is32|=sr<<rt;
7160           }
7161           else {
7162             is32&=~(1LL<<rt);
7163           }
7164         }
7165         else if(op2>=0x2e&&op2<=0x2f) { // DSUB/DSUBU
7166           if(s1==0&&s2==0) {
7167             is32|=1LL<<rt;
7168           }
7169           else if(s2==0) {
7170             uint64_t sr=((is32>>s1)&1LL);
7171             is32&=~(1LL<<rt);
7172             is32|=sr<<rt;
7173           }
7174           else {
7175             is32&=~(1LL<<rt);
7176           }
7177         }
7178         break;
7179       case MULTDIV:
7180         if (op2>=0x1c&&op2<=0x1f) { // DMULT/DMULTU/DDIV/DDIVU
7181           is32&=~((1LL<<HIREG)|(1LL<<LOREG));
7182         }
7183         else {
7184           is32|=(1LL<<HIREG)|(1LL<<LOREG);
7185         }
7186         break;
7187       case MOV:
7188         {
7189           uint64_t sr=((is32>>s1)&1LL);
7190           is32&=~(1LL<<rt);
7191           is32|=sr<<rt;
7192         }
7193         break;
7194       case SHIFT:
7195         if(op2>=0x14&&op2<=0x17) is32&=~(1LL<<rt); // DSLLV/DSRLV/DSRAV
7196         else is32|=1LL<<rt; // SLLV/SRLV/SRAV
7197         break;
7198       case SHIFTIMM:
7199         is32|=1LL<<rt;
7200         // DSLL/DSRL/DSRA/DSLL32/DSRL32 but not DSRA32 have 64-bit result
7201         if(op2>=0x38&&op2<0x3f) is32&=~(1LL<<rt);
7202         break;
7203       case COP0:
7204         if(op2==0) is32|=1LL<<rt; // MFC0
7205         break;
7206       case COP1:
7207       case COP2:
7208         if(op2==0) is32|=1LL<<rt; // MFC1
7209         if(op2==1) is32&=~(1LL<<rt); // DMFC1
7210         if(op2==2) is32|=1LL<<rt; // CFC1
7211         break;
7212       case C1LS:
7213       case C2LS:
7214         break;
7215       case FLOAT:
7216       case FCONV:
7217         break;
7218       case FCOMP:
7219         break;
7220       case C2OP:
7221       case SYSCALL:
7222       case HLECALL:
7223         break;
7224       default:
7225         break;
7226     }
7227     is32|=1;
7228     p32[i]=is32;
7229
7230     if(i>0)
7231     {
7232       if(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)
7233       {
7234         if(rt1[i-1]==31) // JAL/JALR
7235         {
7236           // Subroutine call will return here, don't alloc any registers
7237           is32=1;
7238         }
7239         else if(i+1<slen)
7240         {
7241           // Internal branch will jump here, match registers to caller
7242           is32=0x3FFFFFFFFLL;
7243         }
7244       }
7245     }
7246   }
7247 }
7248
7249 // Identify registers which may be assumed to contain 32-bit values
7250 // and where optimizations will rely on this.
7251 // This is used to determine whether backward branches can safely
7252 // jump to a location with 64-bit values in registers.
7253 static void provisional_r32()
7254 {
7255   u_int r32=0;
7256   int i;
7257
7258   for (i=slen-1;i>=0;i--)
7259   {
7260     int hr;
7261     if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
7262     {
7263       if(ba[i]<start || ba[i]>=(start+slen*4))
7264       {
7265         // Branch out of this block, don't need anything
7266         r32=0;
7267       }
7268       else
7269       {
7270         // Internal branch
7271         // Need whatever matches the target
7272         // (and doesn't get overwritten by the delay slot instruction)
7273         r32=0;
7274         int t=(ba[i]-start)>>2;
7275         if(ba[i]>start+i*4) {
7276           // Forward branch
7277           //if(!(requires_32bit[t]&~regs[i].was32))
7278           //  r32|=requires_32bit[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
7279           if(!(pr32[t]&~regs[i].was32))
7280             r32|=pr32[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
7281         }else{
7282           // Backward branch
7283           if(!(regs[t].was32&~unneeded_reg_upper[t]&~regs[i].was32))
7284             r32|=regs[t].was32&~unneeded_reg_upper[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
7285         }
7286       }
7287       // Conditional branch may need registers for following instructions
7288       if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
7289       {
7290         if(i<slen-2) {
7291           //r32|=requires_32bit[i+2];
7292           r32|=pr32[i+2];
7293           r32&=regs[i].was32;
7294           // Mark this address as a branch target since it may be called
7295           // upon return from interrupt
7296           //bt[i+2]=1;
7297         }
7298       }
7299       // Merge in delay slot
7300       if(!likely[i]) {
7301         // These are overwritten unless the branch is "likely"
7302         // and the delay slot is nullified if not taken
7303         r32&=~(1LL<<rt1[i+1]);
7304         r32&=~(1LL<<rt2[i+1]);
7305       }
7306       // Assume these are needed (delay slot)
7307       if(us1[i+1]>0)
7308       {
7309         if((regs[i].was32>>us1[i+1])&1) r32|=1LL<<us1[i+1];
7310       }
7311       if(us2[i+1]>0)
7312       {
7313         if((regs[i].was32>>us2[i+1])&1) r32|=1LL<<us2[i+1];
7314       }
7315       if(dep1[i+1]&&!((unneeded_reg_upper[i]>>dep1[i+1])&1))
7316       {
7317         if((regs[i].was32>>dep1[i+1])&1) r32|=1LL<<dep1[i+1];
7318       }
7319       if(dep2[i+1]&&!((unneeded_reg_upper[i]>>dep2[i+1])&1))
7320       {
7321         if((regs[i].was32>>dep2[i+1])&1) r32|=1LL<<dep2[i+1];
7322       }
7323     }
7324     else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
7325     {
7326       // SYSCALL instruction (software interrupt)
7327       r32=0;
7328     }
7329     else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
7330     {
7331       // ERET instruction (return from interrupt)
7332       r32=0;
7333     }
7334     // Check 32 bits
7335     r32&=~(1LL<<rt1[i]);
7336     r32&=~(1LL<<rt2[i]);
7337     if(us1[i]>0)
7338     {
7339       if((regs[i].was32>>us1[i])&1) r32|=1LL<<us1[i];
7340     }
7341     if(us2[i]>0)
7342     {
7343       if((regs[i].was32>>us2[i])&1) r32|=1LL<<us2[i];
7344     }
7345     if(dep1[i]&&!((unneeded_reg_upper[i]>>dep1[i])&1))
7346     {
7347       if((regs[i].was32>>dep1[i])&1) r32|=1LL<<dep1[i];
7348     }
7349     if(dep2[i]&&!((unneeded_reg_upper[i]>>dep2[i])&1))
7350     {
7351       if((regs[i].was32>>dep2[i])&1) r32|=1LL<<dep2[i];
7352     }
7353     //requires_32bit[i]=r32;
7354     pr32[i]=r32;
7355
7356     // Dirty registers which are 32-bit, require 32-bit input
7357     // as they will be written as 32-bit values
7358     for(hr=0;hr<HOST_REGS;hr++)
7359     {
7360       if(regs[i].regmap_entry[hr]>0&&regs[i].regmap_entry[hr]<64) {
7361         if((regs[i].was32>>regs[i].regmap_entry[hr])&(regs[i].wasdirty>>hr)&1) {
7362           if(!((unneeded_reg_upper[i]>>regs[i].regmap_entry[hr])&1))
7363           pr32[i]|=1LL<<regs[i].regmap_entry[hr];
7364           //requires_32bit[i]|=1LL<<regs[i].regmap_entry[hr];
7365         }
7366       }
7367     }
7368   }
7369 }
7370
7371 // Write back dirty registers as soon as we will no longer modify them,
7372 // so that we don't end up with lots of writes at the branches.
7373 void clean_registers(int istart,int iend,int wr)
7374 {
7375   int i;
7376   int r;
7377   u_int will_dirty_i,will_dirty_next,temp_will_dirty;
7378   u_int wont_dirty_i,wont_dirty_next,temp_wont_dirty;
7379   if(iend==slen-1) {
7380     will_dirty_i=will_dirty_next=0;
7381     wont_dirty_i=wont_dirty_next=0;
7382   }else{
7383     will_dirty_i=will_dirty_next=will_dirty[iend+1];
7384     wont_dirty_i=wont_dirty_next=wont_dirty[iend+1];
7385   }
7386   for (i=iend;i>=istart;i--)
7387   {
7388     if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
7389     {
7390       if(ba[i]<start || ba[i]>=(start+slen*4))
7391       {
7392         // Branch out of this block, flush all regs
7393         if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
7394         {
7395           // Unconditional branch
7396           will_dirty_i=0;
7397           wont_dirty_i=0;
7398           // Merge in delay slot (will dirty)
7399           for(r=0;r<HOST_REGS;r++) {
7400             if(r!=EXCLUDE_REG) {
7401               if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7402               if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7403               if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7404               if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7405               if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7406               if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7407               if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7408               if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7409               if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7410               if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7411               if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7412               if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7413               if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7414               if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7415             }
7416           }
7417         }
7418         else
7419         {
7420           // Conditional branch
7421           will_dirty_i=0;
7422           wont_dirty_i=wont_dirty_next;
7423           // Merge in delay slot (will dirty)
7424           for(r=0;r<HOST_REGS;r++) {
7425             if(r!=EXCLUDE_REG) {
7426               if(!likely[i]) {
7427                 // Might not dirty if likely branch is not taken
7428                 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7429                 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7430                 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7431                 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7432                 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7433                 if(branch_regs[i].regmap[r]==0) will_dirty_i&=~(1<<r);
7434                 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7435                 //if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7436                 //if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7437                 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7438                 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7439                 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7440                 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7441                 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7442               }
7443             }
7444           }
7445         }
7446         // Merge in delay slot (wont dirty)
7447         for(r=0;r<HOST_REGS;r++) {
7448           if(r!=EXCLUDE_REG) {
7449             if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7450             if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7451             if((regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7452             if((regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7453             if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7454             if((branch_regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7455             if((branch_regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7456             if((branch_regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7457             if((branch_regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7458             if(branch_regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7459           }
7460         }
7461         if(wr) {
7462           #ifndef DESTRUCTIVE_WRITEBACK
7463           branch_regs[i].dirty&=wont_dirty_i;
7464           #endif
7465           branch_regs[i].dirty|=will_dirty_i;
7466         }
7467       }
7468       else
7469       {
7470         // Internal branch
7471         if(ba[i]<=start+i*4) {
7472           // Backward branch
7473           if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
7474           {
7475             // Unconditional branch
7476             temp_will_dirty=0;
7477             temp_wont_dirty=0;
7478             // Merge in delay slot (will dirty)
7479             for(r=0;r<HOST_REGS;r++) {
7480               if(r!=EXCLUDE_REG) {
7481                 if((branch_regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7482                 if((branch_regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7483                 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7484                 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7485                 if((branch_regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7486                 if(branch_regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
7487                 if(branch_regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7488                 if((regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7489                 if((regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7490                 if((regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7491                 if((regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7492                 if((regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7493                 if(regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
7494                 if(regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7495               }
7496             }
7497           } else {
7498             // Conditional branch (not taken case)
7499             temp_will_dirty=will_dirty_next;
7500             temp_wont_dirty=wont_dirty_next;
7501             // Merge in delay slot (will dirty)
7502             for(r=0;r<HOST_REGS;r++) {
7503               if(r!=EXCLUDE_REG) {
7504                 if(!likely[i]) {
7505                   // Will not dirty if likely branch is not taken
7506                   if((branch_regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7507                   if((branch_regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7508                   if((branch_regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7509                   if((branch_regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7510                   if((branch_regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7511                   if(branch_regs[i].regmap[r]==0) temp_will_dirty&=~(1<<r);
7512                   if(branch_regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7513                   //if((regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7514                   //if((regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7515                   if((regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7516                   if((regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7517                   if((regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7518                   if(regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
7519                   if(regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7520                 }
7521               }
7522             }
7523           }
7524           // Merge in delay slot (wont dirty)
7525           for(r=0;r<HOST_REGS;r++) {
7526             if(r!=EXCLUDE_REG) {
7527               if((regs[i].regmap[r]&63)==rt1[i]) temp_wont_dirty|=1<<r;
7528               if((regs[i].regmap[r]&63)==rt2[i]) temp_wont_dirty|=1<<r;
7529               if((regs[i].regmap[r]&63)==rt1[i+1]) temp_wont_dirty|=1<<r;
7530               if((regs[i].regmap[r]&63)==rt2[i+1]) temp_wont_dirty|=1<<r;
7531               if(regs[i].regmap[r]==CCREG) temp_wont_dirty|=1<<r;
7532               if((branch_regs[i].regmap[r]&63)==rt1[i]) temp_wont_dirty|=1<<r;
7533               if((branch_regs[i].regmap[r]&63)==rt2[i]) temp_wont_dirty|=1<<r;
7534               if((branch_regs[i].regmap[r]&63)==rt1[i+1]) temp_wont_dirty|=1<<r;
7535               if((branch_regs[i].regmap[r]&63)==rt2[i+1]) temp_wont_dirty|=1<<r;
7536               if(branch_regs[i].regmap[r]==CCREG) temp_wont_dirty|=1<<r;
7537             }
7538           }
7539           // Deal with changed mappings
7540           if(i<iend) {
7541             for(r=0;r<HOST_REGS;r++) {
7542               if(r!=EXCLUDE_REG) {
7543                 if(regs[i].regmap[r]!=regmap_pre[i][r]) {
7544                   temp_will_dirty&=~(1<<r);
7545                   temp_wont_dirty&=~(1<<r);
7546                   if((regmap_pre[i][r]&63)>0 && (regmap_pre[i][r]&63)<34) {
7547                     temp_will_dirty|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7548                     temp_wont_dirty|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7549                   } else {
7550                     temp_will_dirty|=1<<r;
7551                     temp_wont_dirty|=1<<r;
7552                   }
7553                 }
7554               }
7555             }
7556           }
7557           if(wr) {
7558             will_dirty[i]=temp_will_dirty;
7559             wont_dirty[i]=temp_wont_dirty;
7560             clean_registers((ba[i]-start)>>2,i-1,0);
7561           }else{
7562             // Limit recursion.  It can take an excessive amount
7563             // of time if there are a lot of nested loops.
7564             will_dirty[(ba[i]-start)>>2]=0;
7565             wont_dirty[(ba[i]-start)>>2]=-1;
7566           }
7567         }
7568         /*else*/ if(1)
7569         {
7570           if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
7571           {
7572             // Unconditional branch
7573             will_dirty_i=0;
7574             wont_dirty_i=0;
7575           //if(ba[i]>start+i*4) { // Disable recursion (for debugging)
7576             for(r=0;r<HOST_REGS;r++) {
7577               if(r!=EXCLUDE_REG) {
7578                 if(branch_regs[i].regmap[r]==regs[(ba[i]-start)>>2].regmap_entry[r]) {
7579                   will_dirty_i|=will_dirty[(ba[i]-start)>>2]&(1<<r);
7580                   wont_dirty_i|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
7581                 }
7582                 if(branch_regs[i].regmap[r]>=0) {
7583                   will_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>(branch_regs[i].regmap[r]&63))&1)<<r;
7584                   wont_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>(branch_regs[i].regmap[r]&63))&1)<<r;
7585                 }
7586               }
7587             }
7588           //}
7589             // Merge in delay slot
7590             for(r=0;r<HOST_REGS;r++) {
7591               if(r!=EXCLUDE_REG) {
7592                 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7593                 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7594                 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7595                 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7596                 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7597                 if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7598                 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7599                 if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7600                 if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7601                 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7602                 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7603                 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7604                 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7605                 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7606               }
7607             }
7608           } else {
7609             // Conditional branch
7610             will_dirty_i=will_dirty_next;
7611             wont_dirty_i=wont_dirty_next;
7612           //if(ba[i]>start+i*4) { // Disable recursion (for debugging)
7613             for(r=0;r<HOST_REGS;r++) {
7614               if(r!=EXCLUDE_REG) {
7615                 signed char target_reg=branch_regs[i].regmap[r];
7616                 if(target_reg==regs[(ba[i]-start)>>2].regmap_entry[r]) {
7617                   will_dirty_i&=will_dirty[(ba[i]-start)>>2]&(1<<r);
7618                   wont_dirty_i|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
7619                 }
7620                 else if(target_reg>=0) {
7621                   will_dirty_i&=((unneeded_reg[(ba[i]-start)>>2]>>(target_reg&63))&1)<<r;
7622                   wont_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>(target_reg&63))&1)<<r;
7623                 }
7624                 // Treat delay slot as part of branch too
7625                 /*if(regs[i+1].regmap[r]==regs[(ba[i]-start)>>2].regmap_entry[r]) {
7626                   will_dirty[i+1]&=will_dirty[(ba[i]-start)>>2]&(1<<r);
7627                   wont_dirty[i+1]|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
7628                 }
7629                 else
7630                 {
7631                   will_dirty[i+1]&=~(1<<r);
7632                 }*/
7633               }
7634             }
7635           //}
7636             // Merge in delay slot
7637             for(r=0;r<HOST_REGS;r++) {
7638               if(r!=EXCLUDE_REG) {
7639                 if(!likely[i]) {
7640                   // Might not dirty if likely branch is not taken
7641                   if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7642                   if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7643                   if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7644                   if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7645                   if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7646                   if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7647                   if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7648                   //if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7649                   //if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7650                   if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7651                   if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7652                   if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7653                   if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7654                   if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7655                 }
7656               }
7657             }
7658           }
7659           // Merge in delay slot (won't dirty)
7660           for(r=0;r<HOST_REGS;r++) {
7661             if(r!=EXCLUDE_REG) {
7662               if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7663               if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7664               if((regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7665               if((regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7666               if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7667               if((branch_regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7668               if((branch_regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7669               if((branch_regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7670               if((branch_regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7671               if(branch_regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7672             }
7673           }
7674           if(wr) {
7675             #ifndef DESTRUCTIVE_WRITEBACK
7676             branch_regs[i].dirty&=wont_dirty_i;
7677             #endif
7678             branch_regs[i].dirty|=will_dirty_i;
7679           }
7680         }
7681       }
7682     }
7683     else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
7684     {
7685       // SYSCALL instruction (software interrupt)
7686       will_dirty_i=0;
7687       wont_dirty_i=0;
7688     }
7689     else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
7690     {
7691       // ERET instruction (return from interrupt)
7692       will_dirty_i=0;
7693       wont_dirty_i=0;
7694     }
7695     will_dirty_next=will_dirty_i;
7696     wont_dirty_next=wont_dirty_i;
7697     for(r=0;r<HOST_REGS;r++) {
7698       if(r!=EXCLUDE_REG) {
7699         if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7700         if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7701         if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7702         if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7703         if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7704         if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7705         if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7706         if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7707         if(i>istart) {
7708           if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=FJUMP)
7709           {
7710             // Don't store a register immediately after writing it,
7711             // may prevent dual-issue.
7712             if((regs[i].regmap[r]&63)==rt1[i-1]) wont_dirty_i|=1<<r;
7713             if((regs[i].regmap[r]&63)==rt2[i-1]) wont_dirty_i|=1<<r;
7714           }
7715         }
7716       }
7717     }
7718     // Save it
7719     will_dirty[i]=will_dirty_i;
7720     wont_dirty[i]=wont_dirty_i;
7721     // Mark registers that won't be dirtied as not dirty
7722     if(wr) {
7723       /*printf("wr (%d,%d) %x will:",istart,iend,start+i*4);
7724       for(r=0;r<HOST_REGS;r++) {
7725         if((will_dirty_i>>r)&1) {
7726           printf(" r%d",r);
7727         }
7728       }
7729       printf("\n");*/
7730
7731       //if(i==istart||(itype[i-1]!=RJUMP&&itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=FJUMP)) {
7732         regs[i].dirty|=will_dirty_i;
7733         #ifndef DESTRUCTIVE_WRITEBACK
7734         regs[i].dirty&=wont_dirty_i;
7735         if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
7736         {
7737           if(i<iend-1&&itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000) {
7738             for(r=0;r<HOST_REGS;r++) {
7739               if(r!=EXCLUDE_REG) {
7740                 if(regs[i].regmap[r]==regmap_pre[i+2][r]) {
7741                   regs[i+2].wasdirty&=wont_dirty_i|~(1<<r);
7742                 }else {/*printf("i: %x (%d) mismatch(+2): %d\n",start+i*4,i,r);/*assert(!((wont_dirty_i>>r)&1));*/}
7743               }
7744             }
7745           }
7746         }
7747         else
7748         {
7749           if(i<iend) {
7750             for(r=0;r<HOST_REGS;r++) {
7751               if(r!=EXCLUDE_REG) {
7752                 if(regs[i].regmap[r]==regmap_pre[i+1][r]) {
7753                   regs[i+1].wasdirty&=wont_dirty_i|~(1<<r);
7754                 }else {/*printf("i: %x (%d) mismatch(+1): %d\n",start+i*4,i,r);/*assert(!((wont_dirty_i>>r)&1));*/}
7755               }
7756             }
7757           }
7758         }
7759         #endif
7760       //}
7761     }
7762     // Deal with changed mappings
7763     temp_will_dirty=will_dirty_i;
7764     temp_wont_dirty=wont_dirty_i;
7765     for(r=0;r<HOST_REGS;r++) {
7766       if(r!=EXCLUDE_REG) {
7767         int nr;
7768         if(regs[i].regmap[r]==regmap_pre[i][r]) {
7769           if(wr) {
7770             #ifndef DESTRUCTIVE_WRITEBACK
7771             regs[i].wasdirty&=wont_dirty_i|~(1<<r);
7772             #endif
7773             regs[i].wasdirty|=will_dirty_i&(1<<r);
7774           }
7775         }
7776         else if(regmap_pre[i][r]>=0&&(nr=get_reg(regs[i].regmap,regmap_pre[i][r]))>=0) {
7777           // Register moved to a different register
7778           will_dirty_i&=~(1<<r);
7779           wont_dirty_i&=~(1<<r);
7780           will_dirty_i|=((temp_will_dirty>>nr)&1)<<r;
7781           wont_dirty_i|=((temp_wont_dirty>>nr)&1)<<r;
7782           if(wr) {
7783             #ifndef DESTRUCTIVE_WRITEBACK
7784             regs[i].wasdirty&=wont_dirty_i|~(1<<r);
7785             #endif
7786             regs[i].wasdirty|=will_dirty_i&(1<<r);
7787           }
7788         }
7789         else {
7790           will_dirty_i&=~(1<<r);
7791           wont_dirty_i&=~(1<<r);
7792           if((regmap_pre[i][r]&63)>0 && (regmap_pre[i][r]&63)<34) {
7793             will_dirty_i|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7794             wont_dirty_i|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7795           } else {
7796             wont_dirty_i|=1<<r;
7797             /*printf("i: %x (%d) mismatch: %d\n",start+i*4,i,r);/*assert(!((will_dirty>>r)&1));*/
7798           }
7799         }
7800       }
7801     }
7802   }
7803 }
7804
7805 #ifdef DISASM
7806   /* disassembly */
7807 void disassemble_inst(int i)
7808 {
7809     if (bt[i]) printf("*"); else printf(" ");
7810     switch(itype[i]) {
7811       case UJUMP:
7812         printf (" %x: %s %8x\n",start+i*4,insn[i],ba[i]);break;
7813       case CJUMP:
7814         printf (" %x: %s r%d,r%d,%8x\n",start+i*4,insn[i],rs1[i],rs2[i],i?start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14):*ba);break;
7815       case SJUMP:
7816         printf (" %x: %s r%d,%8x\n",start+i*4,insn[i],rs1[i],start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14));break;
7817       case FJUMP:
7818         printf (" %x: %s %8x\n",start+i*4,insn[i],ba[i]);break;
7819       case RJUMP:
7820         if (opcode[i]==0x9&&rt1[i]!=31)
7821           printf (" %x: %s r%d,r%d\n",start+i*4,insn[i],rt1[i],rs1[i]);
7822         else
7823           printf (" %x: %s r%d\n",start+i*4,insn[i],rs1[i]);
7824         break;
7825       case SPAN:
7826         printf (" %x: %s (pagespan) r%d,r%d,%8x\n",start+i*4,insn[i],rs1[i],rs2[i],ba[i]);break;
7827       case IMM16:
7828         if(opcode[i]==0xf) //LUI
7829           printf (" %x: %s r%d,%4x0000\n",start+i*4,insn[i],rt1[i],imm[i]&0xffff);
7830         else
7831           printf (" %x: %s r%d,r%d,%d\n",start+i*4,insn[i],rt1[i],rs1[i],imm[i]);
7832         break;
7833       case LOAD:
7834       case LOADLR:
7835         printf (" %x: %s r%d,r%d+%x\n",start+i*4,insn[i],rt1[i],rs1[i],imm[i]);
7836         break;
7837       case STORE:
7838       case STORELR:
7839         printf (" %x: %s r%d,r%d+%x\n",start+i*4,insn[i],rs2[i],rs1[i],imm[i]);
7840         break;
7841       case ALU:
7842       case SHIFT:
7843         printf (" %x: %s r%d,r%d,r%d\n",start+i*4,insn[i],rt1[i],rs1[i],rs2[i]);
7844         break;
7845       case MULTDIV:
7846         printf (" %x: %s r%d,r%d\n",start+i*4,insn[i],rs1[i],rs2[i]);
7847         break;
7848       case SHIFTIMM:
7849         printf (" %x: %s r%d,r%d,%d\n",start+i*4,insn[i],rt1[i],rs1[i],imm[i]);
7850         break;
7851       case MOV:
7852         if((opcode2[i]&0x1d)==0x10)
7853           printf (" %x: %s r%d\n",start+i*4,insn[i],rt1[i]);
7854         else if((opcode2[i]&0x1d)==0x11)
7855           printf (" %x: %s r%d\n",start+i*4,insn[i],rs1[i]);
7856         else
7857           printf (" %x: %s\n",start+i*4,insn[i]);
7858         break;
7859       case COP0:
7860         if(opcode2[i]==0)
7861           printf (" %x: %s r%d,cpr0[%d]\n",start+i*4,insn[i],rt1[i],(source[i]>>11)&0x1f); // MFC0
7862         else if(opcode2[i]==4)
7863           printf (" %x: %s r%d,cpr0[%d]\n",start+i*4,insn[i],rs1[i],(source[i]>>11)&0x1f); // MTC0
7864         else printf (" %x: %s\n",start+i*4,insn[i]);
7865         break;
7866       case COP1:
7867         if(opcode2[i]<3)
7868           printf (" %x: %s r%d,cpr1[%d]\n",start+i*4,insn[i],rt1[i],(source[i]>>11)&0x1f); // MFC1
7869         else if(opcode2[i]>3)
7870           printf (" %x: %s r%d,cpr1[%d]\n",start+i*4,insn[i],rs1[i],(source[i]>>11)&0x1f); // MTC1
7871         else printf (" %x: %s\n",start+i*4,insn[i]);
7872         break;
7873       case COP2:
7874         if(opcode2[i]<3)
7875           printf (" %x: %s r%d,cpr2[%d]\n",start+i*4,insn[i],rt1[i],(source[i]>>11)&0x1f); // MFC2
7876         else if(opcode2[i]>3)
7877           printf (" %x: %s r%d,cpr2[%d]\n",start+i*4,insn[i],rs1[i],(source[i]>>11)&0x1f); // MTC2
7878         else printf (" %x: %s\n",start+i*4,insn[i]);
7879         break;
7880       case C1LS:
7881         printf (" %x: %s cpr1[%d],r%d+%x\n",start+i*4,insn[i],(source[i]>>16)&0x1f,rs1[i],imm[i]);
7882         break;
7883       case C2LS:
7884         printf (" %x: %s cpr2[%d],r%d+%x\n",start+i*4,insn[i],(source[i]>>16)&0x1f,rs1[i],imm[i]);
7885         break;
7886       case INTCALL:
7887         printf (" %x: %s (INTCALL)\n",start+i*4,insn[i]);
7888         break;
7889       default:
7890         //printf (" %s %8x\n",insn[i],source[i]);
7891         printf (" %x: %s\n",start+i*4,insn[i]);
7892     }
7893 }
7894 #else
7895 static void disassemble_inst(int i) {}
7896 #endif // DISASM
7897
7898 // clear the state completely, instead of just marking
7899 // things invalid like invalidate_all_pages() does
7900 void new_dynarec_clear_full()
7901 {
7902   int n;
7903   out=(u_char *)BASE_ADDR;
7904   memset(invalid_code,1,sizeof(invalid_code));
7905   memset(hash_table,0xff,sizeof(hash_table));
7906   memset(mini_ht,-1,sizeof(mini_ht));
7907   memset(restore_candidate,0,sizeof(restore_candidate));
7908   memset(shadow,0,sizeof(shadow));
7909   copy=shadow;
7910   expirep=16384; // Expiry pointer, +2 blocks
7911   pending_exception=0;
7912   literalcount=0;
7913   stop_after_jal=0;
7914   inv_code_start=inv_code_end=~0;
7915   gte_reads_flags=0;
7916   // TLB
7917 #ifndef DISABLE_TLB
7918   using_tlb=0;
7919   for(n=0;n<524288;n++) // 0 .. 0x7FFFFFFF
7920     memory_map[n]=-1;
7921   for(n=524288;n<526336;n++) // 0x80000000 .. 0x807FFFFF
7922     memory_map[n]=((u_int)rdram-0x80000000)>>2;
7923   for(n=526336;n<1048576;n++) // 0x80800000 .. 0xFFFFFFFF
7924     memory_map[n]=-1;
7925 #endif
7926   for(n=0;n<4096;n++) ll_clear(jump_in+n);
7927   for(n=0;n<4096;n++) ll_clear(jump_out+n);
7928   for(n=0;n<4096;n++) ll_clear(jump_dirty+n);
7929 }
7930
7931 void new_dynarec_init()
7932 {
7933   printf("Init new dynarec\n");
7934   out=(u_char *)BASE_ADDR;
7935   if (mmap (out, 1<<TARGET_SIZE_2,
7936             PROT_READ | PROT_WRITE | PROT_EXEC,
7937             MAP_FIXED | MAP_PRIVATE | MAP_ANONYMOUS,
7938             -1, 0) <= 0) {printf("mmap() failed\n");}
7939 #ifdef MUPEN64
7940   rdword=&readmem_dword;
7941   fake_pc.f.r.rs=&readmem_dword;
7942   fake_pc.f.r.rt=&readmem_dword;
7943   fake_pc.f.r.rd=&readmem_dword;
7944 #endif
7945   int n;
7946   cycle_multiplier=200;
7947   new_dynarec_clear_full();
7948 #ifdef HOST_IMM8
7949   // Copy this into local area so we don't have to put it in every literal pool
7950   invc_ptr=invalid_code;
7951 #endif
7952 #ifdef MUPEN64
7953   for(n=0;n<0x8000;n++) { // 0 .. 0x7FFFFFFF
7954     writemem[n] = write_nomem_new;
7955     writememb[n] = write_nomemb_new;
7956     writememh[n] = write_nomemh_new;
7957 #ifndef FORCE32
7958     writememd[n] = write_nomemd_new;
7959 #endif
7960     readmem[n] = read_nomem_new;
7961     readmemb[n] = read_nomemb_new;
7962     readmemh[n] = read_nomemh_new;
7963 #ifndef FORCE32
7964     readmemd[n] = read_nomemd_new;
7965 #endif
7966   }
7967   for(n=0x8000;n<0x8080;n++) { // 0x80000000 .. 0x807FFFFF
7968     writemem[n] = write_rdram_new;
7969     writememb[n] = write_rdramb_new;
7970     writememh[n] = write_rdramh_new;
7971 #ifndef FORCE32
7972     writememd[n] = write_rdramd_new;
7973 #endif
7974   }
7975   for(n=0xC000;n<0x10000;n++) { // 0xC0000000 .. 0xFFFFFFFF
7976     writemem[n] = write_nomem_new;
7977     writememb[n] = write_nomemb_new;
7978     writememh[n] = write_nomemh_new;
7979 #ifndef FORCE32
7980     writememd[n] = write_nomemd_new;
7981 #endif
7982     readmem[n] = read_nomem_new;
7983     readmemb[n] = read_nomemb_new;
7984     readmemh[n] = read_nomemh_new;
7985 #ifndef FORCE32
7986     readmemd[n] = read_nomemd_new;
7987 #endif
7988   }
7989 #endif
7990   tlb_hacks();
7991   arch_init();
7992 }
7993
7994 void new_dynarec_cleanup()
7995 {
7996   int n;
7997   if (munmap ((void *)BASE_ADDR, 1<<TARGET_SIZE_2) < 0) {printf("munmap() failed\n");}
7998   for(n=0;n<4096;n++) ll_clear(jump_in+n);
7999   for(n=0;n<4096;n++) ll_clear(jump_out+n);
8000   for(n=0;n<4096;n++) ll_clear(jump_dirty+n);
8001   #ifdef ROM_COPY
8002   if (munmap (ROM_COPY, 67108864) < 0) {printf("munmap() failed\n");}
8003   #endif
8004 }
8005
8006 int new_recompile_block(int addr)
8007 {
8008 /*
8009   if(addr==0x800cd050) {
8010     int block;
8011     for(block=0x80000;block<0x80800;block++) invalidate_block(block);
8012     int n;
8013     for(n=0;n<=2048;n++) ll_clear(jump_dirty+n);
8014   }
8015 */
8016   //if(Count==365117028) tracedebug=1;
8017   assem_debug("NOTCOMPILED: addr = %x -> %x\n", (int)addr, (int)out);
8018   //printf("NOTCOMPILED: addr = %x -> %x\n", (int)addr, (int)out);
8019   //printf("TRACE: count=%d next=%d (compile %x)\n",Count,next_interupt,addr);
8020   //if(debug)
8021   //printf("TRACE: count=%d next=%d (checksum %x)\n",Count,next_interupt,mchecksum());
8022   //printf("fpu mapping=%x enabled=%x\n",(Status & 0x04000000)>>26,(Status & 0x20000000)>>29);
8023   /*if(Count>=312978186) {
8024     rlist();
8025   }*/
8026   //rlist();
8027   start = (u_int)addr&~3;
8028   //assert(((u_int)addr&1)==0);
8029   new_dynarec_did_compile=1;
8030 #ifdef PCSX
8031   if (Config.HLE && start == 0x80001000) // hlecall
8032   {
8033     // XXX: is this enough? Maybe check hleSoftCall?
8034     u_int beginning=(u_int)out;
8035     u_int page=get_page(start);
8036     invalid_code[start>>12]=0;
8037     emit_movimm(start,0);
8038     emit_writeword(0,(int)&pcaddr);
8039     emit_jmp((int)new_dyna_leave);
8040     literal_pool(0);
8041 #ifdef __arm__
8042     __clear_cache((void *)beginning,out);
8043 #endif
8044     ll_add(jump_in+page,start,(void *)beginning);
8045     return 0;
8046   }
8047   else if ((u_int)addr < 0x00200000 ||
8048     (0xa0000000 <= addr && addr < 0xa0200000)) {
8049     // used for BIOS calls mostly?
8050     source = (u_int *)((u_int)rdram+(start&0x1fffff));
8051     pagelimit = (addr&0xa0000000)|0x00200000;
8052   }
8053   else if (!Config.HLE && (
8054 /*    (0x9fc00000 <= addr && addr < 0x9fc80000) ||*/
8055     (0xbfc00000 <= addr && addr < 0xbfc80000))) {
8056     // BIOS
8057     source = (u_int *)((u_int)psxR+(start&0x7ffff));
8058     pagelimit = (addr&0xfff00000)|0x80000;
8059   }
8060   else
8061 #endif
8062 #ifdef MUPEN64
8063   if ((int)addr >= 0xa4000000 && (int)addr < 0xa4001000) {
8064     source = (u_int *)((u_int)SP_DMEM+start-0xa4000000);
8065     pagelimit = 0xa4001000;
8066   }
8067   else
8068 #endif
8069   if ((int)addr >= 0x80000000 && (int)addr < 0x80000000+RAM_SIZE) {
8070     source = (u_int *)((u_int)rdram+start-0x80000000);
8071     pagelimit = 0x80000000+RAM_SIZE;
8072   }
8073 #ifndef DISABLE_TLB
8074   else if ((signed int)addr >= (signed int)0xC0000000) {
8075     //printf("addr=%x mm=%x\n",(u_int)addr,(memory_map[start>>12]<<2));
8076     //if(tlb_LUT_r[start>>12])
8077       //source = (u_int *)(((int)rdram)+(tlb_LUT_r[start>>12]&0xFFFFF000)+(((int)addr)&0xFFF)-0x80000000);
8078     if((signed int)memory_map[start>>12]>=0) {
8079       source = (u_int *)((u_int)(start+(memory_map[start>>12]<<2)));
8080       pagelimit=(start+4096)&0xFFFFF000;
8081       int map=memory_map[start>>12];
8082       int i;
8083       for(i=0;i<5;i++) {
8084         //printf("start: %x next: %x\n",map,memory_map[pagelimit>>12]);
8085         if((map&0xBFFFFFFF)==(memory_map[pagelimit>>12]&0xBFFFFFFF)) pagelimit+=4096;
8086       }
8087       assem_debug("pagelimit=%x\n",pagelimit);
8088       assem_debug("mapping=%x (%x)\n",memory_map[start>>12],(memory_map[start>>12]<<2)+start);
8089     }
8090     else {
8091       assem_debug("Compile at unmapped memory address: %x \n", (int)addr);
8092       //assem_debug("start: %x next: %x\n",memory_map[start>>12],memory_map[(start+4096)>>12]);
8093       return -1; // Caller will invoke exception handler
8094     }
8095     //printf("source= %x\n",(int)source);
8096   }
8097 #endif
8098   else {
8099     printf("Compile at bogus memory address: %x \n", (int)addr);
8100     exit(1);
8101   }
8102
8103   /* Pass 1: disassemble */
8104   /* Pass 2: register dependencies, branch targets */
8105   /* Pass 3: register allocation */
8106   /* Pass 4: branch dependencies */
8107   /* Pass 5: pre-alloc */
8108   /* Pass 6: optimize clean/dirty state */
8109   /* Pass 7: flag 32-bit registers */
8110   /* Pass 8: assembly */
8111   /* Pass 9: linker */
8112   /* Pass 10: garbage collection / free memory */
8113
8114   int i,j;
8115   int done=0;
8116   unsigned int type,op,op2;
8117
8118   //printf("addr = %x source = %x %x\n", addr,source,source[0]);
8119
8120   /* Pass 1 disassembly */
8121
8122   for(i=0;!done;i++) {
8123     bt[i]=0;likely[i]=0;ooo[i]=0;op2=0;
8124     minimum_free_regs[i]=0;
8125     opcode[i]=op=source[i]>>26;
8126     switch(op)
8127     {
8128       case 0x00: strcpy(insn[i],"special"); type=NI;
8129         op2=source[i]&0x3f;
8130         switch(op2)
8131         {
8132           case 0x00: strcpy(insn[i],"SLL"); type=SHIFTIMM; break;
8133           case 0x02: strcpy(insn[i],"SRL"); type=SHIFTIMM; break;
8134           case 0x03: strcpy(insn[i],"SRA"); type=SHIFTIMM; break;
8135           case 0x04: strcpy(insn[i],"SLLV"); type=SHIFT; break;
8136           case 0x06: strcpy(insn[i],"SRLV"); type=SHIFT; break;
8137           case 0x07: strcpy(insn[i],"SRAV"); type=SHIFT; break;
8138           case 0x08: strcpy(insn[i],"JR"); type=RJUMP; break;
8139           case 0x09: strcpy(insn[i],"JALR"); type=RJUMP; break;
8140           case 0x0C: strcpy(insn[i],"SYSCALL"); type=SYSCALL; break;
8141           case 0x0D: strcpy(insn[i],"BREAK"); type=OTHER; break;
8142           case 0x0F: strcpy(insn[i],"SYNC"); type=OTHER; break;
8143           case 0x10: strcpy(insn[i],"MFHI"); type=MOV; break;
8144           case 0x11: strcpy(insn[i],"MTHI"); type=MOV; break;
8145           case 0x12: strcpy(insn[i],"MFLO"); type=MOV; break;
8146           case 0x13: strcpy(insn[i],"MTLO"); type=MOV; break;
8147           case 0x18: strcpy(insn[i],"MULT"); type=MULTDIV; break;
8148           case 0x19: strcpy(insn[i],"MULTU"); type=MULTDIV; break;
8149           case 0x1A: strcpy(insn[i],"DIV"); type=MULTDIV; break;
8150           case 0x1B: strcpy(insn[i],"DIVU"); type=MULTDIV; break;
8151           case 0x20: strcpy(insn[i],"ADD"); type=ALU; break;
8152           case 0x21: strcpy(insn[i],"ADDU"); type=ALU; break;
8153           case 0x22: strcpy(insn[i],"SUB"); type=ALU; break;
8154           case 0x23: strcpy(insn[i],"SUBU"); type=ALU; break;
8155           case 0x24: strcpy(insn[i],"AND"); type=ALU; break;
8156           case 0x25: strcpy(insn[i],"OR"); type=ALU; break;
8157           case 0x26: strcpy(insn[i],"XOR"); type=ALU; break;
8158           case 0x27: strcpy(insn[i],"NOR"); type=ALU; break;
8159           case 0x2A: strcpy(insn[i],"SLT"); type=ALU; break;
8160           case 0x2B: strcpy(insn[i],"SLTU"); type=ALU; break;
8161           case 0x30: strcpy(insn[i],"TGE"); type=NI; break;
8162           case 0x31: strcpy(insn[i],"TGEU"); type=NI; break;
8163           case 0x32: strcpy(insn[i],"TLT"); type=NI; break;
8164           case 0x33: strcpy(insn[i],"TLTU"); type=NI; break;
8165           case 0x34: strcpy(insn[i],"TEQ"); type=NI; break;
8166           case 0x36: strcpy(insn[i],"TNE"); type=NI; break;
8167 #ifndef FORCE32
8168           case 0x14: strcpy(insn[i],"DSLLV"); type=SHIFT; break;
8169           case 0x16: strcpy(insn[i],"DSRLV"); type=SHIFT; break;
8170           case 0x17: strcpy(insn[i],"DSRAV"); type=SHIFT; break;
8171           case 0x1C: strcpy(insn[i],"DMULT"); type=MULTDIV; break;
8172           case 0x1D: strcpy(insn[i],"DMULTU"); type=MULTDIV; break;
8173           case 0x1E: strcpy(insn[i],"DDIV"); type=MULTDIV; break;
8174           case 0x1F: strcpy(insn[i],"DDIVU"); type=MULTDIV; break;
8175           case 0x2C: strcpy(insn[i],"DADD"); type=ALU; break;
8176           case 0x2D: strcpy(insn[i],"DADDU"); type=ALU; break;
8177           case 0x2E: strcpy(insn[i],"DSUB"); type=ALU; break;
8178           case 0x2F: strcpy(insn[i],"DSUBU"); type=ALU; break;
8179           case 0x38: strcpy(insn[i],"DSLL"); type=SHIFTIMM; break;
8180           case 0x3A: strcpy(insn[i],"DSRL"); type=SHIFTIMM; break;
8181           case 0x3B: strcpy(insn[i],"DSRA"); type=SHIFTIMM; break;
8182           case 0x3C: strcpy(insn[i],"DSLL32"); type=SHIFTIMM; break;
8183           case 0x3E: strcpy(insn[i],"DSRL32"); type=SHIFTIMM; break;
8184           case 0x3F: strcpy(insn[i],"DSRA32"); type=SHIFTIMM; break;
8185 #endif
8186         }
8187         break;
8188       case 0x01: strcpy(insn[i],"regimm"); type=NI;
8189         op2=(source[i]>>16)&0x1f;
8190         switch(op2)
8191         {
8192           case 0x00: strcpy(insn[i],"BLTZ"); type=SJUMP; break;
8193           case 0x01: strcpy(insn[i],"BGEZ"); type=SJUMP; break;
8194           case 0x02: strcpy(insn[i],"BLTZL"); type=SJUMP; break;
8195           case 0x03: strcpy(insn[i],"BGEZL"); type=SJUMP; break;
8196           case 0x08: strcpy(insn[i],"TGEI"); type=NI; break;
8197           case 0x09: strcpy(insn[i],"TGEIU"); type=NI; break;
8198           case 0x0A: strcpy(insn[i],"TLTI"); type=NI; break;
8199           case 0x0B: strcpy(insn[i],"TLTIU"); type=NI; break;
8200           case 0x0C: strcpy(insn[i],"TEQI"); type=NI; break;
8201           case 0x0E: strcpy(insn[i],"TNEI"); type=NI; break;
8202           case 0x10: strcpy(insn[i],"BLTZAL"); type=SJUMP; break;
8203           case 0x11: strcpy(insn[i],"BGEZAL"); type=SJUMP; break;
8204           case 0x12: strcpy(insn[i],"BLTZALL"); type=SJUMP; break;
8205           case 0x13: strcpy(insn[i],"BGEZALL"); type=SJUMP; break;
8206         }
8207         break;
8208       case 0x02: strcpy(insn[i],"J"); type=UJUMP; break;
8209       case 0x03: strcpy(insn[i],"JAL"); type=UJUMP; break;
8210       case 0x04: strcpy(insn[i],"BEQ"); type=CJUMP; break;
8211       case 0x05: strcpy(insn[i],"BNE"); type=CJUMP; break;
8212       case 0x06: strcpy(insn[i],"BLEZ"); type=CJUMP; break;
8213       case 0x07: strcpy(insn[i],"BGTZ"); type=CJUMP; break;
8214       case 0x08: strcpy(insn[i],"ADDI"); type=IMM16; break;
8215       case 0x09: strcpy(insn[i],"ADDIU"); type=IMM16; break;
8216       case 0x0A: strcpy(insn[i],"SLTI"); type=IMM16; break;
8217       case 0x0B: strcpy(insn[i],"SLTIU"); type=IMM16; break;
8218       case 0x0C: strcpy(insn[i],"ANDI"); type=IMM16; break;
8219       case 0x0D: strcpy(insn[i],"ORI"); type=IMM16; break;
8220       case 0x0E: strcpy(insn[i],"XORI"); type=IMM16; break;
8221       case 0x0F: strcpy(insn[i],"LUI"); type=IMM16; break;
8222       case 0x10: strcpy(insn[i],"cop0"); type=NI;
8223         op2=(source[i]>>21)&0x1f;
8224         switch(op2)
8225         {
8226           case 0x00: strcpy(insn[i],"MFC0"); type=COP0; break;
8227           case 0x04: strcpy(insn[i],"MTC0"); type=COP0; break;
8228           case 0x10: strcpy(insn[i],"tlb"); type=NI;
8229           switch(source[i]&0x3f)
8230           {
8231             case 0x01: strcpy(insn[i],"TLBR"); type=COP0; break;
8232             case 0x02: strcpy(insn[i],"TLBWI"); type=COP0; break;
8233             case 0x06: strcpy(insn[i],"TLBWR"); type=COP0; break;
8234             case 0x08: strcpy(insn[i],"TLBP"); type=COP0; break;
8235 #ifdef PCSX
8236             case 0x10: strcpy(insn[i],"RFE"); type=COP0; break;
8237 #else
8238             case 0x18: strcpy(insn[i],"ERET"); type=COP0; break;
8239 #endif
8240           }
8241         }
8242         break;
8243       case 0x11: strcpy(insn[i],"cop1"); type=NI;
8244         op2=(source[i]>>21)&0x1f;
8245         switch(op2)
8246         {
8247           case 0x00: strcpy(insn[i],"MFC1"); type=COP1; break;
8248           case 0x01: strcpy(insn[i],"DMFC1"); type=COP1; break;
8249           case 0x02: strcpy(insn[i],"CFC1"); type=COP1; break;
8250           case 0x04: strcpy(insn[i],"MTC1"); type=COP1; break;
8251           case 0x05: strcpy(insn[i],"DMTC1"); type=COP1; break;
8252           case 0x06: strcpy(insn[i],"CTC1"); type=COP1; break;
8253           case 0x08: strcpy(insn[i],"BC1"); type=FJUMP;
8254           switch((source[i]>>16)&0x3)
8255           {
8256             case 0x00: strcpy(insn[i],"BC1F"); break;
8257             case 0x01: strcpy(insn[i],"BC1T"); break;
8258             case 0x02: strcpy(insn[i],"BC1FL"); break;
8259             case 0x03: strcpy(insn[i],"BC1TL"); break;
8260           }
8261           break;
8262           case 0x10: strcpy(insn[i],"C1.S"); type=NI;
8263           switch(source[i]&0x3f)
8264           {
8265             case 0x00: strcpy(insn[i],"ADD.S"); type=FLOAT; break;
8266             case 0x01: strcpy(insn[i],"SUB.S"); type=FLOAT; break;
8267             case 0x02: strcpy(insn[i],"MUL.S"); type=FLOAT; break;
8268             case 0x03: strcpy(insn[i],"DIV.S"); type=FLOAT; break;
8269             case 0x04: strcpy(insn[i],"SQRT.S"); type=FLOAT; break;
8270             case 0x05: strcpy(insn[i],"ABS.S"); type=FLOAT; break;
8271             case 0x06: strcpy(insn[i],"MOV.S"); type=FLOAT; break;
8272             case 0x07: strcpy(insn[i],"NEG.S"); type=FLOAT; break;
8273             case 0x08: strcpy(insn[i],"ROUND.L.S"); type=FCONV; break;
8274             case 0x09: strcpy(insn[i],"TRUNC.L.S"); type=FCONV; break;
8275             case 0x0A: strcpy(insn[i],"CEIL.L.S"); type=FCONV; break;
8276             case 0x0B: strcpy(insn[i],"FLOOR.L.S"); type=FCONV; break;
8277             case 0x0C: strcpy(insn[i],"ROUND.W.S"); type=FCONV; break;
8278             case 0x0D: strcpy(insn[i],"TRUNC.W.S"); type=FCONV; break;
8279             case 0x0E: strcpy(insn[i],"CEIL.W.S"); type=FCONV; break;
8280             case 0x0F: strcpy(insn[i],"FLOOR.W.S"); type=FCONV; break;
8281             case 0x21: strcpy(insn[i],"CVT.D.S"); type=FCONV; break;
8282             case 0x24: strcpy(insn[i],"CVT.W.S"); type=FCONV; break;
8283             case 0x25: strcpy(insn[i],"CVT.L.S"); type=FCONV; break;
8284             case 0x30: strcpy(insn[i],"C.F.S"); type=FCOMP; break;
8285             case 0x31: strcpy(insn[i],"C.UN.S"); type=FCOMP; break;
8286             case 0x32: strcpy(insn[i],"C.EQ.S"); type=FCOMP; break;
8287             case 0x33: strcpy(insn[i],"C.UEQ.S"); type=FCOMP; break;
8288             case 0x34: strcpy(insn[i],"C.OLT.S"); type=FCOMP; break;
8289             case 0x35: strcpy(insn[i],"C.ULT.S"); type=FCOMP; break;
8290             case 0x36: strcpy(insn[i],"C.OLE.S"); type=FCOMP; break;
8291             case 0x37: strcpy(insn[i],"C.ULE.S"); type=FCOMP; break;
8292             case 0x38: strcpy(insn[i],"C.SF.S"); type=FCOMP; break;
8293             case 0x39: strcpy(insn[i],"C.NGLE.S"); type=FCOMP; break;
8294             case 0x3A: strcpy(insn[i],"C.SEQ.S"); type=FCOMP; break;
8295             case 0x3B: strcpy(insn[i],"C.NGL.S"); type=FCOMP; break;
8296             case 0x3C: strcpy(insn[i],"C.LT.S"); type=FCOMP; break;
8297             case 0x3D: strcpy(insn[i],"C.NGE.S"); type=FCOMP; break;
8298             case 0x3E: strcpy(insn[i],"C.LE.S"); type=FCOMP; break;
8299             case 0x3F: strcpy(insn[i],"C.NGT.S"); type=FCOMP; break;
8300           }
8301           break;
8302           case 0x11: strcpy(insn[i],"C1.D"); type=NI;
8303           switch(source[i]&0x3f)
8304           {
8305             case 0x00: strcpy(insn[i],"ADD.D"); type=FLOAT; break;
8306             case 0x01: strcpy(insn[i],"SUB.D"); type=FLOAT; break;
8307             case 0x02: strcpy(insn[i],"MUL.D"); type=FLOAT; break;
8308             case 0x03: strcpy(insn[i],"DIV.D"); type=FLOAT; break;
8309             case 0x04: strcpy(insn[i],"SQRT.D"); type=FLOAT; break;
8310             case 0x05: strcpy(insn[i],"ABS.D"); type=FLOAT; break;
8311             case 0x06: strcpy(insn[i],"MOV.D"); type=FLOAT; break;
8312             case 0x07: strcpy(insn[i],"NEG.D"); type=FLOAT; break;
8313             case 0x08: strcpy(insn[i],"ROUND.L.D"); type=FCONV; break;
8314             case 0x09: strcpy(insn[i],"TRUNC.L.D"); type=FCONV; break;
8315             case 0x0A: strcpy(insn[i],"CEIL.L.D"); type=FCONV; break;
8316             case 0x0B: strcpy(insn[i],"FLOOR.L.D"); type=FCONV; break;
8317             case 0x0C: strcpy(insn[i],"ROUND.W.D"); type=FCONV; break;
8318             case 0x0D: strcpy(insn[i],"TRUNC.W.D"); type=FCONV; break;
8319             case 0x0E: strcpy(insn[i],"CEIL.W.D"); type=FCONV; break;
8320             case 0x0F: strcpy(insn[i],"FLOOR.W.D"); type=FCONV; break;
8321             case 0x20: strcpy(insn[i],"CVT.S.D"); type=FCONV; break;
8322             case 0x24: strcpy(insn[i],"CVT.W.D"); type=FCONV; break;
8323             case 0x25: strcpy(insn[i],"CVT.L.D"); type=FCONV; break;
8324             case 0x30: strcpy(insn[i],"C.F.D"); type=FCOMP; break;
8325             case 0x31: strcpy(insn[i],"C.UN.D"); type=FCOMP; break;
8326             case 0x32: strcpy(insn[i],"C.EQ.D"); type=FCOMP; break;
8327             case 0x33: strcpy(insn[i],"C.UEQ.D"); type=FCOMP; break;
8328             case 0x34: strcpy(insn[i],"C.OLT.D"); type=FCOMP; break;
8329             case 0x35: strcpy(insn[i],"C.ULT.D"); type=FCOMP; break;
8330             case 0x36: strcpy(insn[i],"C.OLE.D"); type=FCOMP; break;
8331             case 0x37: strcpy(insn[i],"C.ULE.D"); type=FCOMP; break;
8332             case 0x38: strcpy(insn[i],"C.SF.D"); type=FCOMP; break;
8333             case 0x39: strcpy(insn[i],"C.NGLE.D"); type=FCOMP; break;
8334             case 0x3A: strcpy(insn[i],"C.SEQ.D"); type=FCOMP; break;
8335             case 0x3B: strcpy(insn[i],"C.NGL.D"); type=FCOMP; break;
8336             case 0x3C: strcpy(insn[i],"C.LT.D"); type=FCOMP; break;
8337             case 0x3D: strcpy(insn[i],"C.NGE.D"); type=FCOMP; break;
8338             case 0x3E: strcpy(insn[i],"C.LE.D"); type=FCOMP; break;
8339             case 0x3F: strcpy(insn[i],"C.NGT.D"); type=FCOMP; break;
8340           }
8341           break;
8342           case 0x14: strcpy(insn[i],"C1.W"); type=NI;
8343           switch(source[i]&0x3f)
8344           {
8345             case 0x20: strcpy(insn[i],"CVT.S.W"); type=FCONV; break;
8346             case 0x21: strcpy(insn[i],"CVT.D.W"); type=FCONV; break;
8347           }
8348           break;
8349           case 0x15: strcpy(insn[i],"C1.L"); type=NI;
8350           switch(source[i]&0x3f)
8351           {
8352             case 0x20: strcpy(insn[i],"CVT.S.L"); type=FCONV; break;
8353             case 0x21: strcpy(insn[i],"CVT.D.L"); type=FCONV; break;
8354           }
8355           break;
8356         }
8357         break;
8358 #ifndef FORCE32
8359       case 0x14: strcpy(insn[i],"BEQL"); type=CJUMP; break;
8360       case 0x15: strcpy(insn[i],"BNEL"); type=CJUMP; break;
8361       case 0x16: strcpy(insn[i],"BLEZL"); type=CJUMP; break;
8362       case 0x17: strcpy(insn[i],"BGTZL"); type=CJUMP; break;
8363       case 0x18: strcpy(insn[i],"DADDI"); type=IMM16; break;
8364       case 0x19: strcpy(insn[i],"DADDIU"); type=IMM16; break;
8365       case 0x1A: strcpy(insn[i],"LDL"); type=LOADLR; break;
8366       case 0x1B: strcpy(insn[i],"LDR"); type=LOADLR; break;
8367 #endif
8368       case 0x20: strcpy(insn[i],"LB"); type=LOAD; break;
8369       case 0x21: strcpy(insn[i],"LH"); type=LOAD; break;
8370       case 0x22: strcpy(insn[i],"LWL"); type=LOADLR; break;
8371       case 0x23: strcpy(insn[i],"LW"); type=LOAD; break;
8372       case 0x24: strcpy(insn[i],"LBU"); type=LOAD; break;
8373       case 0x25: strcpy(insn[i],"LHU"); type=LOAD; break;
8374       case 0x26: strcpy(insn[i],"LWR"); type=LOADLR; break;
8375 #ifndef FORCE32
8376       case 0x27: strcpy(insn[i],"LWU"); type=LOAD; break;
8377 #endif
8378       case 0x28: strcpy(insn[i],"SB"); type=STORE; break;
8379       case 0x29: strcpy(insn[i],"SH"); type=STORE; break;
8380       case 0x2A: strcpy(insn[i],"SWL"); type=STORELR; break;
8381       case 0x2B: strcpy(insn[i],"SW"); type=STORE; break;
8382 #ifndef FORCE32
8383       case 0x2C: strcpy(insn[i],"SDL"); type=STORELR; break;
8384       case 0x2D: strcpy(insn[i],"SDR"); type=STORELR; break;
8385 #endif
8386       case 0x2E: strcpy(insn[i],"SWR"); type=STORELR; break;
8387       case 0x2F: strcpy(insn[i],"CACHE"); type=NOP; break;
8388       case 0x30: strcpy(insn[i],"LL"); type=NI; break;
8389       case 0x31: strcpy(insn[i],"LWC1"); type=C1LS; break;
8390 #ifndef FORCE32
8391       case 0x34: strcpy(insn[i],"LLD"); type=NI; break;
8392       case 0x35: strcpy(insn[i],"LDC1"); type=C1LS; break;
8393       case 0x37: strcpy(insn[i],"LD"); type=LOAD; break;
8394 #endif
8395       case 0x38: strcpy(insn[i],"SC"); type=NI; break;
8396       case 0x39: strcpy(insn[i],"SWC1"); type=C1LS; break;
8397 #ifndef FORCE32
8398       case 0x3C: strcpy(insn[i],"SCD"); type=NI; break;
8399       case 0x3D: strcpy(insn[i],"SDC1"); type=C1LS; break;
8400       case 0x3F: strcpy(insn[i],"SD"); type=STORE; break;
8401 #endif
8402 #ifdef PCSX
8403       case 0x12: strcpy(insn[i],"COP2"); type=NI;
8404         op2=(source[i]>>21)&0x1f;
8405         //if (op2 & 0x10) {
8406         if (source[i]&0x3f) { // use this hack to support old savestates with patched gte insns
8407           if (gte_handlers[source[i]&0x3f]!=NULL) {
8408             if (gte_regnames[source[i]&0x3f]!=NULL)
8409               strcpy(insn[i],gte_regnames[source[i]&0x3f]);
8410             else
8411               snprintf(insn[i], sizeof(insn[i]), "COP2 %x", source[i]&0x3f);
8412             type=C2OP;
8413           }
8414         }
8415         else switch(op2)
8416         {
8417           case 0x00: strcpy(insn[i],"MFC2"); type=COP2; break;
8418           case 0x02: strcpy(insn[i],"CFC2"); type=COP2; break;
8419           case 0x04: strcpy(insn[i],"MTC2"); type=COP2; break;
8420           case 0x06: strcpy(insn[i],"CTC2"); type=COP2; break;
8421         }
8422         break;
8423       case 0x32: strcpy(insn[i],"LWC2"); type=C2LS; break;
8424       case 0x3A: strcpy(insn[i],"SWC2"); type=C2LS; break;
8425       case 0x3B: strcpy(insn[i],"HLECALL"); type=HLECALL; break;
8426 #endif
8427       default: strcpy(insn[i],"???"); type=NI;
8428         printf("NI %08x @%08x (%08x)\n", source[i], addr + i*4, addr);
8429         break;
8430     }
8431     itype[i]=type;
8432     opcode2[i]=op2;
8433     /* Get registers/immediates */
8434     lt1[i]=0;
8435     us1[i]=0;
8436     us2[i]=0;
8437     dep1[i]=0;
8438     dep2[i]=0;
8439     gte_rs[i]=gte_rt[i]=0;
8440     switch(type) {
8441       case LOAD:
8442         rs1[i]=(source[i]>>21)&0x1f;
8443         rs2[i]=0;
8444         rt1[i]=(source[i]>>16)&0x1f;
8445         rt2[i]=0;
8446         imm[i]=(short)source[i];
8447         break;
8448       case STORE:
8449       case STORELR:
8450         rs1[i]=(source[i]>>21)&0x1f;
8451         rs2[i]=(source[i]>>16)&0x1f;
8452         rt1[i]=0;
8453         rt2[i]=0;
8454         imm[i]=(short)source[i];
8455         if(op==0x2c||op==0x2d||op==0x3f) us1[i]=rs2[i]; // 64-bit SDL/SDR/SD
8456         break;
8457       case LOADLR:
8458         // LWL/LWR only load part of the register,
8459         // therefore the target register must be treated as a source too
8460         rs1[i]=(source[i]>>21)&0x1f;
8461         rs2[i]=(source[i]>>16)&0x1f;
8462         rt1[i]=(source[i]>>16)&0x1f;
8463         rt2[i]=0;
8464         imm[i]=(short)source[i];
8465         if(op==0x1a||op==0x1b) us1[i]=rs2[i]; // LDR/LDL
8466         if(op==0x26) dep1[i]=rt1[i]; // LWR
8467         break;
8468       case IMM16:
8469         if (op==0x0f) rs1[i]=0; // LUI instruction has no source register
8470         else rs1[i]=(source[i]>>21)&0x1f;
8471         rs2[i]=0;
8472         rt1[i]=(source[i]>>16)&0x1f;
8473         rt2[i]=0;
8474         if(op>=0x0c&&op<=0x0e) { // ANDI/ORI/XORI
8475           imm[i]=(unsigned short)source[i];
8476         }else{
8477           imm[i]=(short)source[i];
8478         }
8479         if(op==0x18||op==0x19) us1[i]=rs1[i]; // DADDI/DADDIU
8480         if(op==0x0a||op==0x0b) us1[i]=rs1[i]; // SLTI/SLTIU
8481         if(op==0x0d||op==0x0e) dep1[i]=rs1[i]; // ORI/XORI
8482         break;
8483       case UJUMP:
8484         rs1[i]=0;
8485         rs2[i]=0;
8486         rt1[i]=0;
8487         rt2[i]=0;
8488         // The JAL instruction writes to r31.
8489         if (op&1) {
8490           rt1[i]=31;
8491         }
8492         rs2[i]=CCREG;
8493         break;
8494       case RJUMP:
8495         rs1[i]=(source[i]>>21)&0x1f;
8496         rs2[i]=0;
8497         rt1[i]=0;
8498         rt2[i]=0;
8499         // The JALR instruction writes to rd.
8500         if (op2&1) {
8501           rt1[i]=(source[i]>>11)&0x1f;
8502         }
8503         rs2[i]=CCREG;
8504         break;
8505       case CJUMP:
8506         rs1[i]=(source[i]>>21)&0x1f;
8507         rs2[i]=(source[i]>>16)&0x1f;
8508         rt1[i]=0;
8509         rt2[i]=0;
8510         if(op&2) { // BGTZ/BLEZ
8511           rs2[i]=0;
8512         }
8513         us1[i]=rs1[i];
8514         us2[i]=rs2[i];
8515         likely[i]=op>>4;
8516         break;
8517       case SJUMP:
8518         rs1[i]=(source[i]>>21)&0x1f;
8519         rs2[i]=CCREG;
8520         rt1[i]=0;
8521         rt2[i]=0;
8522         us1[i]=rs1[i];
8523         if(op2&0x10) { // BxxAL
8524           rt1[i]=31;
8525           // NOTE: If the branch is not taken, r31 is still overwritten
8526         }
8527         likely[i]=(op2&2)>>1;
8528         break;
8529       case FJUMP:
8530         rs1[i]=FSREG;
8531         rs2[i]=CSREG;
8532         rt1[i]=0;
8533         rt2[i]=0;
8534         likely[i]=((source[i])>>17)&1;
8535         break;
8536       case ALU:
8537         rs1[i]=(source[i]>>21)&0x1f; // source
8538         rs2[i]=(source[i]>>16)&0x1f; // subtract amount
8539         rt1[i]=(source[i]>>11)&0x1f; // destination
8540         rt2[i]=0;
8541         if(op2==0x2a||op2==0x2b) { // SLT/SLTU
8542           us1[i]=rs1[i];us2[i]=rs2[i];
8543         }
8544         else if(op2>=0x24&&op2<=0x27) { // AND/OR/XOR/NOR
8545           dep1[i]=rs1[i];dep2[i]=rs2[i];
8546         }
8547         else if(op2>=0x2c&&op2<=0x2f) { // DADD/DSUB
8548           dep1[i]=rs1[i];dep2[i]=rs2[i];
8549         }
8550         break;
8551       case MULTDIV:
8552         rs1[i]=(source[i]>>21)&0x1f; // source
8553         rs2[i]=(source[i]>>16)&0x1f; // divisor
8554         rt1[i]=HIREG;
8555         rt2[i]=LOREG;
8556         if (op2>=0x1c&&op2<=0x1f) { // DMULT/DMULTU/DDIV/DDIVU
8557           us1[i]=rs1[i];us2[i]=rs2[i];
8558         }
8559         break;
8560       case MOV:
8561         rs1[i]=0;
8562         rs2[i]=0;
8563         rt1[i]=0;
8564         rt2[i]=0;
8565         if(op2==0x10) rs1[i]=HIREG; // MFHI
8566         if(op2==0x11) rt1[i]=HIREG; // MTHI
8567         if(op2==0x12) rs1[i]=LOREG; // MFLO
8568         if(op2==0x13) rt1[i]=LOREG; // MTLO
8569         if((op2&0x1d)==0x10) rt1[i]=(source[i]>>11)&0x1f; // MFxx
8570         if((op2&0x1d)==0x11) rs1[i]=(source[i]>>21)&0x1f; // MTxx
8571         dep1[i]=rs1[i];
8572         break;
8573       case SHIFT:
8574         rs1[i]=(source[i]>>16)&0x1f; // target of shift
8575         rs2[i]=(source[i]>>21)&0x1f; // shift amount
8576         rt1[i]=(source[i]>>11)&0x1f; // destination
8577         rt2[i]=0;
8578         // DSLLV/DSRLV/DSRAV are 64-bit
8579         if(op2>=0x14&&op2<=0x17) us1[i]=rs1[i];
8580         break;
8581       case SHIFTIMM:
8582         rs1[i]=(source[i]>>16)&0x1f;
8583         rs2[i]=0;
8584         rt1[i]=(source[i]>>11)&0x1f;
8585         rt2[i]=0;
8586         imm[i]=(source[i]>>6)&0x1f;
8587         // DSxx32 instructions
8588         if(op2>=0x3c) imm[i]|=0x20;
8589         // DSLL/DSRL/DSRA/DSRA32/DSRL32 but not DSLL32 require 64-bit source
8590         if(op2>=0x38&&op2!=0x3c) us1[i]=rs1[i];
8591         break;
8592       case COP0:
8593         rs1[i]=0;
8594         rs2[i]=0;
8595         rt1[i]=0;
8596         rt2[i]=0;
8597         if(op2==0) rt1[i]=(source[i]>>16)&0x1F; // MFC0
8598         if(op2==4) rs1[i]=(source[i]>>16)&0x1F; // MTC0
8599         if(op2==4&&((source[i]>>11)&0x1f)==12) rt2[i]=CSREG; // Status
8600         if(op2==16) if((source[i]&0x3f)==0x18) rs2[i]=CCREG; // ERET
8601         break;
8602       case COP1:
8603         rs1[i]=0;
8604         rs2[i]=0;
8605         rt1[i]=0;
8606         rt2[i]=0;
8607         if(op2<3) rt1[i]=(source[i]>>16)&0x1F; // MFC1/DMFC1/CFC1
8608         if(op2>3) rs1[i]=(source[i]>>16)&0x1F; // MTC1/DMTC1/CTC1
8609         if(op2==5) us1[i]=rs1[i]; // DMTC1
8610         rs2[i]=CSREG;
8611         break;
8612       case COP2:
8613         rs1[i]=0;
8614         rs2[i]=0;
8615         rt1[i]=0;
8616         rt2[i]=0;
8617         if(op2<3) rt1[i]=(source[i]>>16)&0x1F; // MFC2/CFC2
8618         if(op2>3) rs1[i]=(source[i]>>16)&0x1F; // MTC2/CTC2
8619         rs2[i]=CSREG;
8620         int gr=(source[i]>>11)&0x1F;
8621         switch(op2)
8622         {
8623           case 0x00: gte_rs[i]=1ll<<gr; break; // MFC2
8624           case 0x04: gte_rt[i]=1ll<<gr; break; // MTC2
8625           case 0x02: gte_rs[i]=1ll<<(gr+32); // CFC2
8626             if(gr==31&&!gte_reads_flags) {
8627               assem_debug("gte flag read encountered @%08x\n",addr + i*4);
8628               gte_reads_flags=1;
8629             }
8630             break;
8631           case 0x06: gte_rt[i]=1ll<<(gr+32); break; // CTC2
8632         }
8633         break;
8634       case C1LS:
8635         rs1[i]=(source[i]>>21)&0x1F;
8636         rs2[i]=CSREG;
8637         rt1[i]=0;
8638         rt2[i]=0;
8639         imm[i]=(short)source[i];
8640         break;
8641       case C2LS:
8642         rs1[i]=(source[i]>>21)&0x1F;
8643         rs2[i]=0;
8644         rt1[i]=0;
8645         rt2[i]=0;
8646         imm[i]=(short)source[i];
8647         if(op==0x32) gte_rt[i]=1ll<<((source[i]>>16)&0x1F); // LWC2
8648         else gte_rs[i]=1ll<<((source[i]>>16)&0x1F); // SWC2
8649         break;
8650       case C2OP:
8651         rs1[i]=0;
8652         rs2[i]=0;
8653         rt1[i]=0;
8654         rt2[i]=0;
8655         gte_rs[i]=gte_reg_reads[source[i]&0x3f];
8656         gte_rt[i]=gte_reg_writes[source[i]&0x3f];
8657         gte_rt[i]|=1ll<<63; // every op changes flags
8658         break;
8659       case FLOAT:
8660       case FCONV:
8661         rs1[i]=0;
8662         rs2[i]=CSREG;
8663         rt1[i]=0;
8664         rt2[i]=0;
8665         break;
8666       case FCOMP:
8667         rs1[i]=FSREG;
8668         rs2[i]=CSREG;
8669         rt1[i]=FSREG;
8670         rt2[i]=0;
8671         break;
8672       case SYSCALL:
8673       case HLECALL:
8674       case INTCALL:
8675         rs1[i]=CCREG;
8676         rs2[i]=0;
8677         rt1[i]=0;
8678         rt2[i]=0;
8679         break;
8680       default:
8681         rs1[i]=0;
8682         rs2[i]=0;
8683         rt1[i]=0;
8684         rt2[i]=0;
8685     }
8686     /* Calculate branch target addresses */
8687     if(type==UJUMP)
8688       ba[i]=((start+i*4+4)&0xF0000000)|(((unsigned int)source[i]<<6)>>4);
8689     else if(type==CJUMP&&rs1[i]==rs2[i]&&(op&1))
8690       ba[i]=start+i*4+8; // Ignore never taken branch
8691     else if(type==SJUMP&&rs1[i]==0&&!(op2&1))
8692       ba[i]=start+i*4+8; // Ignore never taken branch
8693     else if(type==CJUMP||type==SJUMP||type==FJUMP)
8694       ba[i]=start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14);
8695     else ba[i]=-1;
8696 #ifdef PCSX
8697     if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)) {
8698       int do_in_intrp=0;
8699       // branch in delay slot?
8700       if(type==RJUMP||type==UJUMP||type==CJUMP||type==SJUMP||type==FJUMP) {
8701         // don't handle first branch and call interpreter if it's hit
8702         printf("branch in delay slot @%08x (%08x)\n", addr + i*4, addr);
8703         do_in_intrp=1;
8704       }
8705       // basic load delay detection
8706       else if((type==LOAD||type==LOADLR||type==COP0||type==COP2||type==C2LS)&&rt1[i]!=0) {
8707         int t=(ba[i-1]-start)/4;
8708         if(0 <= t && t < i &&(rt1[i]==rs1[t]||rt1[i]==rs2[t])&&itype[t]!=CJUMP&&itype[t]!=SJUMP) {
8709           // jump target wants DS result - potential load delay effect
8710           printf("load delay @%08x (%08x)\n", addr + i*4, addr);
8711           do_in_intrp=1;
8712           bt[t+1]=1; // expected return from interpreter
8713         }
8714         else if(i>=2&&rt1[i-2]==2&&rt1[i]==2&&rs1[i]!=2&&rs2[i]!=2&&rs1[i-1]!=2&&rs2[i-1]!=2&&
8715               !(i>=3&&(itype[i-3]==RJUMP||itype[i-3]==UJUMP||itype[i-3]==CJUMP||itype[i-3]==SJUMP))) {
8716           // v0 overwrite like this is a sign of trouble, bail out
8717           printf("v0 overwrite @%08x (%08x)\n", addr + i*4, addr);
8718           do_in_intrp=1;
8719         }
8720       }
8721       if(do_in_intrp) {
8722         rs1[i-1]=CCREG;
8723         rs2[i-1]=rt1[i-1]=rt2[i-1]=0;
8724         ba[i-1]=-1;
8725         itype[i-1]=INTCALL;
8726         done=2;
8727         i--; // don't compile the DS
8728       }
8729     }
8730 #endif
8731     /* Is this the end of the block? */
8732     if(i>0&&(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)) {
8733       if(rt1[i-1]==0) { // Continue past subroutine call (JAL)
8734         done=2;
8735       }
8736       else {
8737         if(stop_after_jal) done=1;
8738         // Stop on BREAK
8739         if((source[i+1]&0xfc00003f)==0x0d) done=1;
8740       }
8741       // Don't recompile stuff that's already compiled
8742       if(check_addr(start+i*4+4)) done=1;
8743       // Don't get too close to the limit
8744       if(i>MAXBLOCK/2) done=1;
8745     }
8746     if(itype[i]==SYSCALL&&stop_after_jal) done=1;
8747     if(itype[i]==HLECALL||itype[i]==INTCALL) done=2;
8748     if(done==2) {
8749       // Does the block continue due to a branch?
8750       for(j=i-1;j>=0;j--)
8751       {
8752         if(ba[j]==start+i*4) done=j=0; // Branch into delay slot
8753         if(ba[j]==start+i*4+4) done=j=0;
8754         if(ba[j]==start+i*4+8) done=j=0;
8755       }
8756     }
8757     //assert(i<MAXBLOCK-1);
8758     if(start+i*4==pagelimit-4) done=1;
8759     assert(start+i*4<pagelimit);
8760     if (i==MAXBLOCK-1) done=1;
8761     // Stop if we're compiling junk
8762     if(itype[i]==NI&&opcode[i]==0x11) {
8763       done=stop_after_jal=1;
8764       printf("Disabled speculative precompilation\n");
8765     }
8766   }
8767   slen=i;
8768   if(itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==RJUMP||itype[i-1]==FJUMP) {
8769     if(start+i*4==pagelimit) {
8770       itype[i-1]=SPAN;
8771     }
8772   }
8773   assert(slen>0);
8774
8775   /* Pass 2 - Register dependencies and branch targets */
8776
8777   unneeded_registers(0,slen-1,0);
8778
8779   /* Pass 3 - Register allocation */
8780
8781   struct regstat current; // Current register allocations/status
8782   current.is32=1;
8783   current.dirty=0;
8784   current.u=unneeded_reg[0];
8785   current.uu=unneeded_reg_upper[0];
8786   clear_all_regs(current.regmap);
8787   alloc_reg(&current,0,CCREG);
8788   dirty_reg(&current,CCREG);
8789   current.isconst=0;
8790   current.wasconst=0;
8791   current.waswritten=0;
8792   int ds=0;
8793   int cc=0;
8794   int hr=-1;
8795
8796 #ifndef FORCE32
8797   provisional_32bit();
8798 #endif
8799   if((u_int)addr&1) {
8800     // First instruction is delay slot
8801     cc=-1;
8802     bt[1]=1;
8803     ds=1;
8804     unneeded_reg[0]=1;
8805     unneeded_reg_upper[0]=1;
8806     current.regmap[HOST_BTREG]=BTREG;
8807   }
8808
8809   for(i=0;i<slen;i++)
8810   {
8811     if(bt[i])
8812     {
8813       int hr;
8814       for(hr=0;hr<HOST_REGS;hr++)
8815       {
8816         // Is this really necessary?
8817         if(current.regmap[hr]==0) current.regmap[hr]=-1;
8818       }
8819       current.isconst=0;
8820       current.waswritten=0;
8821     }
8822     if(i>1)
8823     {
8824       if((opcode[i-2]&0x2f)==0x05) // BNE/BNEL
8825       {
8826         if(rs1[i-2]==0||rs2[i-2]==0)
8827         {
8828           if(rs1[i-2]) {
8829             current.is32|=1LL<<rs1[i-2];
8830             int hr=get_reg(current.regmap,rs1[i-2]|64);
8831             if(hr>=0) current.regmap[hr]=-1;
8832           }
8833           if(rs2[i-2]) {
8834             current.is32|=1LL<<rs2[i-2];
8835             int hr=get_reg(current.regmap,rs2[i-2]|64);
8836             if(hr>=0) current.regmap[hr]=-1;
8837           }
8838         }
8839       }
8840     }
8841 #ifndef FORCE32
8842     // If something jumps here with 64-bit values
8843     // then promote those registers to 64 bits
8844     if(bt[i])
8845     {
8846       uint64_t temp_is32=current.is32;
8847       for(j=i-1;j>=0;j--)
8848       {
8849         if(ba[j]==start+i*4)
8850           temp_is32&=branch_regs[j].is32;
8851       }
8852       for(j=i;j<slen;j++)
8853       {
8854         if(ba[j]==start+i*4)
8855           //temp_is32=1;
8856           temp_is32&=p32[j];
8857       }
8858       if(temp_is32!=current.is32) {
8859         //printf("dumping 32-bit regs (%x)\n",start+i*4);
8860         #ifndef DESTRUCTIVE_WRITEBACK
8861         if(ds)
8862         #endif
8863         for(hr=0;hr<HOST_REGS;hr++)
8864         {
8865           int r=current.regmap[hr];
8866           if(r>0&&r<64)
8867           {
8868             if((current.dirty>>hr)&((current.is32&~temp_is32)>>r)&1) {
8869               temp_is32|=1LL<<r;
8870               //printf("restore %d\n",r);
8871             }
8872           }
8873         }
8874         current.is32=temp_is32;
8875       }
8876     }
8877 #else
8878     current.is32=-1LL;
8879 #endif
8880
8881     memcpy(regmap_pre[i],current.regmap,sizeof(current.regmap));
8882     regs[i].wasconst=current.isconst;
8883     regs[i].was32=current.is32;
8884     regs[i].wasdirty=current.dirty;
8885     #if defined(DESTRUCTIVE_WRITEBACK) && !defined(FORCE32)
8886     // To change a dirty register from 32 to 64 bits, we must write
8887     // it out during the previous cycle (for branches, 2 cycles)
8888     if(i<slen-1&&bt[i+1]&&itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP)
8889     {
8890       uint64_t temp_is32=current.is32;
8891       for(j=i-1;j>=0;j--)
8892       {
8893         if(ba[j]==start+i*4+4)
8894           temp_is32&=branch_regs[j].is32;
8895       }
8896       for(j=i;j<slen;j++)
8897       {
8898         if(ba[j]==start+i*4+4)
8899           //temp_is32=1;
8900           temp_is32&=p32[j];
8901       }
8902       if(temp_is32!=current.is32) {
8903         //printf("pre-dumping 32-bit regs (%x)\n",start+i*4);
8904         for(hr=0;hr<HOST_REGS;hr++)
8905         {
8906           int r=current.regmap[hr];
8907           if(r>0)
8908           {
8909             if((current.dirty>>hr)&((current.is32&~temp_is32)>>(r&63))&1) {
8910               if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP)
8911               {
8912                 if(rs1[i]!=(r&63)&&rs2[i]!=(r&63))
8913                 {
8914                   //printf("dump %d/r%d\n",hr,r);
8915                   current.regmap[hr]=-1;
8916                   if(get_reg(current.regmap,r|64)>=0)
8917                     current.regmap[get_reg(current.regmap,r|64)]=-1;
8918                 }
8919               }
8920             }
8921           }
8922         }
8923       }
8924     }
8925     else if(i<slen-2&&bt[i+2]&&(source[i-1]>>16)!=0x1000&&(itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP))
8926     {
8927       uint64_t temp_is32=current.is32;
8928       for(j=i-1;j>=0;j--)
8929       {
8930         if(ba[j]==start+i*4+8)
8931           temp_is32&=branch_regs[j].is32;
8932       }
8933       for(j=i;j<slen;j++)
8934       {
8935         if(ba[j]==start+i*4+8)
8936           //temp_is32=1;
8937           temp_is32&=p32[j];
8938       }
8939       if(temp_is32!=current.is32) {
8940         //printf("pre-dumping 32-bit regs (%x)\n",start+i*4);
8941         for(hr=0;hr<HOST_REGS;hr++)
8942         {
8943           int r=current.regmap[hr];
8944           if(r>0)
8945           {
8946             if((current.dirty>>hr)&((current.is32&~temp_is32)>>(r&63))&1) {
8947               if(rs1[i]!=(r&63)&&rs2[i]!=(r&63)&&rs1[i+1]!=(r&63)&&rs2[i+1]!=(r&63))
8948               {
8949                 //printf("dump %d/r%d\n",hr,r);
8950                 current.regmap[hr]=-1;
8951                 if(get_reg(current.regmap,r|64)>=0)
8952                   current.regmap[get_reg(current.regmap,r|64)]=-1;
8953               }
8954             }
8955           }
8956         }
8957       }
8958     }
8959     #endif
8960     if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP) {
8961       if(i+1<slen) {
8962         current.u=unneeded_reg[i+1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
8963         current.uu=unneeded_reg_upper[i+1]&~((1LL<<us1[i])|(1LL<<us2[i]));
8964         if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
8965         current.u|=1;
8966         current.uu|=1;
8967       } else {
8968         current.u=1;
8969         current.uu=1;
8970       }
8971     } else {
8972       if(i+1<slen) {
8973         current.u=branch_unneeded_reg[i]&~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
8974         current.uu=branch_unneeded_reg_upper[i]&~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
8975         if((~current.uu>>rt1[i+1])&1) current.uu&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
8976         current.u&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
8977         current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
8978         current.u|=1;
8979         current.uu|=1;
8980       } else { printf("oops, branch at end of block with no delay slot\n");exit(1); }
8981     }
8982     is_ds[i]=ds;
8983     if(ds) {
8984       ds=0; // Skip delay slot, already allocated as part of branch
8985       // ...but we need to alloc it in case something jumps here
8986       if(i+1<slen) {
8987         current.u=branch_unneeded_reg[i-1]&unneeded_reg[i+1];
8988         current.uu=branch_unneeded_reg_upper[i-1]&unneeded_reg_upper[i+1];
8989       }else{
8990         current.u=branch_unneeded_reg[i-1];
8991         current.uu=branch_unneeded_reg_upper[i-1];
8992       }
8993       current.u&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
8994       current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
8995       if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
8996       current.u|=1;
8997       current.uu|=1;
8998       struct regstat temp;
8999       memcpy(&temp,&current,sizeof(current));
9000       temp.wasdirty=temp.dirty;
9001       temp.was32=temp.is32;
9002       // TODO: Take into account unconditional branches, as below
9003       delayslot_alloc(&temp,i);
9004       memcpy(regs[i].regmap,temp.regmap,sizeof(temp.regmap));
9005       regs[i].wasdirty=temp.wasdirty;
9006       regs[i].was32=temp.was32;
9007       regs[i].dirty=temp.dirty;
9008       regs[i].is32=temp.is32;
9009       regs[i].isconst=0;
9010       regs[i].wasconst=0;
9011       current.isconst=0;
9012       // Create entry (branch target) regmap
9013       for(hr=0;hr<HOST_REGS;hr++)
9014       {
9015         int r=temp.regmap[hr];
9016         if(r>=0) {
9017           if(r!=regmap_pre[i][hr]) {
9018             regs[i].regmap_entry[hr]=-1;
9019           }
9020           else
9021           {
9022             if(r<64){
9023               if((current.u>>r)&1) {
9024                 regs[i].regmap_entry[hr]=-1;
9025                 regs[i].regmap[hr]=-1;
9026                 //Don't clear regs in the delay slot as the branch might need them
9027                 //current.regmap[hr]=-1;
9028               }else
9029                 regs[i].regmap_entry[hr]=r;
9030             }
9031             else {
9032               if((current.uu>>(r&63))&1) {
9033                 regs[i].regmap_entry[hr]=-1;
9034                 regs[i].regmap[hr]=-1;
9035                 //Don't clear regs in the delay slot as the branch might need them
9036                 //current.regmap[hr]=-1;
9037               }else
9038                 regs[i].regmap_entry[hr]=r;
9039             }
9040           }
9041         } else {
9042           // First instruction expects CCREG to be allocated
9043           if(i==0&&hr==HOST_CCREG)
9044             regs[i].regmap_entry[hr]=CCREG;
9045           else
9046             regs[i].regmap_entry[hr]=-1;
9047         }
9048       }
9049     }
9050     else { // Not delay slot
9051       switch(itype[i]) {
9052         case UJUMP:
9053           //current.isconst=0; // DEBUG
9054           //current.wasconst=0; // DEBUG
9055           //regs[i].wasconst=0; // DEBUG
9056           clear_const(&current,rt1[i]);
9057           alloc_cc(&current,i);
9058           dirty_reg(&current,CCREG);
9059           if (rt1[i]==31) {
9060             alloc_reg(&current,i,31);
9061             dirty_reg(&current,31);
9062             //assert(rs1[i+1]!=31&&rs2[i+1]!=31);
9063             //assert(rt1[i+1]!=rt1[i]);
9064             #ifdef REG_PREFETCH
9065             alloc_reg(&current,i,PTEMP);
9066             #endif
9067             //current.is32|=1LL<<rt1[i];
9068           }
9069           ooo[i]=1;
9070           delayslot_alloc(&current,i+1);
9071           //current.isconst=0; // DEBUG
9072           ds=1;
9073           //printf("i=%d, isconst=%x\n",i,current.isconst);
9074           break;
9075         case RJUMP:
9076           //current.isconst=0;
9077           //current.wasconst=0;
9078           //regs[i].wasconst=0;
9079           clear_const(&current,rs1[i]);
9080           clear_const(&current,rt1[i]);
9081           alloc_cc(&current,i);
9082           dirty_reg(&current,CCREG);
9083           if(rs1[i]!=rt1[i+1]&&rs1[i]!=rt2[i+1]) {
9084             alloc_reg(&current,i,rs1[i]);
9085             if (rt1[i]!=0) {
9086               alloc_reg(&current,i,rt1[i]);
9087               dirty_reg(&current,rt1[i]);
9088               assert(rs1[i+1]!=rt1[i]&&rs2[i+1]!=rt1[i]);
9089               assert(rt1[i+1]!=rt1[i]);
9090               #ifdef REG_PREFETCH
9091               alloc_reg(&current,i,PTEMP);
9092               #endif
9093             }
9094             #ifdef USE_MINI_HT
9095             if(rs1[i]==31) { // JALR
9096               alloc_reg(&current,i,RHASH);
9097               #ifndef HOST_IMM_ADDR32
9098               alloc_reg(&current,i,RHTBL);
9099               #endif
9100             }
9101             #endif
9102             delayslot_alloc(&current,i+1);
9103           } else {
9104             // The delay slot overwrites our source register,
9105             // allocate a temporary register to hold the old value.
9106             current.isconst=0;
9107             current.wasconst=0;
9108             regs[i].wasconst=0;
9109             delayslot_alloc(&current,i+1);
9110             current.isconst=0;
9111             alloc_reg(&current,i,RTEMP);
9112           }
9113           //current.isconst=0; // DEBUG
9114           ooo[i]=1;
9115           ds=1;
9116           break;
9117         case CJUMP:
9118           //current.isconst=0;
9119           //current.wasconst=0;
9120           //regs[i].wasconst=0;
9121           clear_const(&current,rs1[i]);
9122           clear_const(&current,rs2[i]);
9123           if((opcode[i]&0x3E)==4) // BEQ/BNE
9124           {
9125             alloc_cc(&current,i);
9126             dirty_reg(&current,CCREG);
9127             if(rs1[i]) alloc_reg(&current,i,rs1[i]);
9128             if(rs2[i]) alloc_reg(&current,i,rs2[i]);
9129             if(!((current.is32>>rs1[i])&(current.is32>>rs2[i])&1))
9130             {
9131               if(rs1[i]) alloc_reg64(&current,i,rs1[i]);
9132               if(rs2[i]) alloc_reg64(&current,i,rs2[i]);
9133             }
9134             if((rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]))||
9135                (rs2[i]&&(rs2[i]==rt1[i+1]||rs2[i]==rt2[i+1]))) {
9136               // The delay slot overwrites one of our conditions.
9137               // Allocate the branch condition registers instead.
9138               current.isconst=0;
9139               current.wasconst=0;
9140               regs[i].wasconst=0;
9141               if(rs1[i]) alloc_reg(&current,i,rs1[i]);
9142               if(rs2[i]) alloc_reg(&current,i,rs2[i]);
9143               if(!((current.is32>>rs1[i])&(current.is32>>rs2[i])&1))
9144               {
9145                 if(rs1[i]) alloc_reg64(&current,i,rs1[i]);
9146                 if(rs2[i]) alloc_reg64(&current,i,rs2[i]);
9147               }
9148             }
9149             else
9150             {
9151               ooo[i]=1;
9152               delayslot_alloc(&current,i+1);
9153             }
9154           }
9155           else
9156           if((opcode[i]&0x3E)==6) // BLEZ/BGTZ
9157           {
9158             alloc_cc(&current,i);
9159             dirty_reg(&current,CCREG);
9160             alloc_reg(&current,i,rs1[i]);
9161             if(!(current.is32>>rs1[i]&1))
9162             {
9163               alloc_reg64(&current,i,rs1[i]);
9164             }
9165             if(rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1])) {
9166               // The delay slot overwrites one of our conditions.
9167               // Allocate the branch condition registers instead.
9168               current.isconst=0;
9169               current.wasconst=0;
9170               regs[i].wasconst=0;
9171               if(rs1[i]) alloc_reg(&current,i,rs1[i]);
9172               if(!((current.is32>>rs1[i])&1))
9173               {
9174                 if(rs1[i]) alloc_reg64(&current,i,rs1[i]);
9175               }
9176             }
9177             else
9178             {
9179               ooo[i]=1;
9180               delayslot_alloc(&current,i+1);
9181             }
9182           }
9183           else
9184           // Don't alloc the delay slot yet because we might not execute it
9185           if((opcode[i]&0x3E)==0x14) // BEQL/BNEL
9186           {
9187             current.isconst=0;
9188             current.wasconst=0;
9189             regs[i].wasconst=0;
9190             alloc_cc(&current,i);
9191             dirty_reg(&current,CCREG);
9192             alloc_reg(&current,i,rs1[i]);
9193             alloc_reg(&current,i,rs2[i]);
9194             if(!((current.is32>>rs1[i])&(current.is32>>rs2[i])&1))
9195             {
9196               alloc_reg64(&current,i,rs1[i]);
9197               alloc_reg64(&current,i,rs2[i]);
9198             }
9199           }
9200           else
9201           if((opcode[i]&0x3E)==0x16) // BLEZL/BGTZL
9202           {
9203             current.isconst=0;
9204             current.wasconst=0;
9205             regs[i].wasconst=0;
9206             alloc_cc(&current,i);
9207             dirty_reg(&current,CCREG);
9208             alloc_reg(&current,i,rs1[i]);
9209             if(!(current.is32>>rs1[i]&1))
9210             {
9211               alloc_reg64(&current,i,rs1[i]);
9212             }
9213           }
9214           ds=1;
9215           //current.isconst=0;
9216           break;
9217         case SJUMP:
9218           //current.isconst=0;
9219           //current.wasconst=0;
9220           //regs[i].wasconst=0;
9221           clear_const(&current,rs1[i]);
9222           clear_const(&current,rt1[i]);
9223           //if((opcode2[i]&0x1E)==0x0) // BLTZ/BGEZ
9224           if((opcode2[i]&0x0E)==0x0) // BLTZ/BGEZ
9225           {
9226             alloc_cc(&current,i);
9227             dirty_reg(&current,CCREG);
9228             alloc_reg(&current,i,rs1[i]);
9229             if(!(current.is32>>rs1[i]&1))
9230             {
9231               alloc_reg64(&current,i,rs1[i]);
9232             }
9233             if (rt1[i]==31) { // BLTZAL/BGEZAL
9234               alloc_reg(&current,i,31);
9235               dirty_reg(&current,31);
9236               //#ifdef REG_PREFETCH
9237               //alloc_reg(&current,i,PTEMP);
9238               //#endif
9239               //current.is32|=1LL<<rt1[i];
9240             }
9241             if((rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1])) // The delay slot overwrites the branch condition.
9242                ||(rt1[i]==31&&(rs1[i+1]==31||rs2[i+1]==31||rt1[i+1]==31||rt2[i+1]==31))) { // DS touches $ra
9243               // Allocate the branch condition registers instead.
9244               current.isconst=0;
9245               current.wasconst=0;
9246               regs[i].wasconst=0;
9247               if(rs1[i]) alloc_reg(&current,i,rs1[i]);
9248               if(!((current.is32>>rs1[i])&1))
9249               {
9250                 if(rs1[i]) alloc_reg64(&current,i,rs1[i]);
9251               }
9252             }
9253             else
9254             {
9255               ooo[i]=1;
9256               delayslot_alloc(&current,i+1);
9257             }
9258           }
9259           else
9260           // Don't alloc the delay slot yet because we might not execute it
9261           if((opcode2[i]&0x1E)==0x2) // BLTZL/BGEZL
9262           {
9263             current.isconst=0;
9264             current.wasconst=0;
9265             regs[i].wasconst=0;
9266             alloc_cc(&current,i);
9267             dirty_reg(&current,CCREG);
9268             alloc_reg(&current,i,rs1[i]);
9269             if(!(current.is32>>rs1[i]&1))
9270             {
9271               alloc_reg64(&current,i,rs1[i]);
9272             }
9273           }
9274           ds=1;
9275           //current.isconst=0;
9276           break;
9277         case FJUMP:
9278           current.isconst=0;
9279           current.wasconst=0;
9280           regs[i].wasconst=0;
9281           if(likely[i]==0) // BC1F/BC1T
9282           {
9283             // TODO: Theoretically we can run out of registers here on x86.
9284             // The delay slot can allocate up to six, and we need to check
9285             // CSREG before executing the delay slot.  Possibly we can drop
9286             // the cycle count and then reload it after checking that the
9287             // FPU is in a usable state, or don't do out-of-order execution.
9288             alloc_cc(&current,i);
9289             dirty_reg(&current,CCREG);
9290             alloc_reg(&current,i,FSREG);
9291             alloc_reg(&current,i,CSREG);
9292             if(itype[i+1]==FCOMP) {
9293               // The delay slot overwrites the branch condition.
9294               // Allocate the branch condition registers instead.
9295               alloc_cc(&current,i);
9296               dirty_reg(&current,CCREG);
9297               alloc_reg(&current,i,CSREG);
9298               alloc_reg(&current,i,FSREG);
9299             }
9300             else {
9301               ooo[i]=1;
9302               delayslot_alloc(&current,i+1);
9303               alloc_reg(&current,i+1,CSREG);
9304             }
9305           }
9306           else
9307           // Don't alloc the delay slot yet because we might not execute it
9308           if(likely[i]) // BC1FL/BC1TL
9309           {
9310             alloc_cc(&current,i);
9311             dirty_reg(&current,CCREG);
9312             alloc_reg(&current,i,CSREG);
9313             alloc_reg(&current,i,FSREG);
9314           }
9315           ds=1;
9316           current.isconst=0;
9317           break;
9318         case IMM16:
9319           imm16_alloc(&current,i);
9320           break;
9321         case LOAD:
9322         case LOADLR:
9323           load_alloc(&current,i);
9324           break;
9325         case STORE:
9326         case STORELR:
9327           store_alloc(&current,i);
9328           break;
9329         case ALU:
9330           alu_alloc(&current,i);
9331           break;
9332         case SHIFT:
9333           shift_alloc(&current,i);
9334           break;
9335         case MULTDIV:
9336           multdiv_alloc(&current,i);
9337           break;
9338         case SHIFTIMM:
9339           shiftimm_alloc(&current,i);
9340           break;
9341         case MOV:
9342           mov_alloc(&current,i);
9343           break;
9344         case COP0:
9345           cop0_alloc(&current,i);
9346           break;
9347         case COP1:
9348         case COP2:
9349           cop1_alloc(&current,i);
9350           break;
9351         case C1LS:
9352           c1ls_alloc(&current,i);
9353           break;
9354         case C2LS:
9355           c2ls_alloc(&current,i);
9356           break;
9357         case C2OP:
9358           c2op_alloc(&current,i);
9359           break;
9360         case FCONV:
9361           fconv_alloc(&current,i);
9362           break;
9363         case FLOAT:
9364           float_alloc(&current,i);
9365           break;
9366         case FCOMP:
9367           fcomp_alloc(&current,i);
9368           break;
9369         case SYSCALL:
9370         case HLECALL:
9371         case INTCALL:
9372           syscall_alloc(&current,i);
9373           break;
9374         case SPAN:
9375           pagespan_alloc(&current,i);
9376           break;
9377       }
9378
9379       // Drop the upper half of registers that have become 32-bit
9380       current.uu|=current.is32&((1LL<<rt1[i])|(1LL<<rt2[i]));
9381       if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP) {
9382         current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
9383         if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9384         current.uu|=1;
9385       } else {
9386         current.uu|=current.is32&((1LL<<rt1[i+1])|(1LL<<rt2[i+1]));
9387         current.uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
9388         if((~current.uu>>rt1[i+1])&1) current.uu&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
9389         current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
9390         current.uu|=1;
9391       }
9392
9393       // Create entry (branch target) regmap
9394       for(hr=0;hr<HOST_REGS;hr++)
9395       {
9396         int r,or,er;
9397         r=current.regmap[hr];
9398         if(r>=0) {
9399           if(r!=regmap_pre[i][hr]) {
9400             // TODO: delay slot (?)
9401             or=get_reg(regmap_pre[i],r); // Get old mapping for this register
9402             if(or<0||(r&63)>=TEMPREG){
9403               regs[i].regmap_entry[hr]=-1;
9404             }
9405             else
9406             {
9407               // Just move it to a different register
9408               regs[i].regmap_entry[hr]=r;
9409               // If it was dirty before, it's still dirty
9410               if((regs[i].wasdirty>>or)&1) dirty_reg(&current,r&63);
9411             }
9412           }
9413           else
9414           {
9415             // Unneeded
9416             if(r==0){
9417               regs[i].regmap_entry[hr]=0;
9418             }
9419             else
9420             if(r<64){
9421               if((current.u>>r)&1) {
9422                 regs[i].regmap_entry[hr]=-1;
9423                 //regs[i].regmap[hr]=-1;
9424                 current.regmap[hr]=-1;
9425               }else
9426                 regs[i].regmap_entry[hr]=r;
9427             }
9428             else {
9429               if((current.uu>>(r&63))&1) {
9430                 regs[i].regmap_entry[hr]=-1;
9431                 //regs[i].regmap[hr]=-1;
9432                 current.regmap[hr]=-1;
9433               }else
9434                 regs[i].regmap_entry[hr]=r;
9435             }
9436           }
9437         } else {
9438           // Branches expect CCREG to be allocated at the target
9439           if(regmap_pre[i][hr]==CCREG)
9440             regs[i].regmap_entry[hr]=CCREG;
9441           else
9442             regs[i].regmap_entry[hr]=-1;
9443         }
9444       }
9445       memcpy(regs[i].regmap,current.regmap,sizeof(current.regmap));
9446     }
9447
9448     if(i>0&&(itype[i-1]==STORE||itype[i-1]==STORELR||(itype[i-1]==C2LS&&opcode[i-1]==0x3a))&&(u_int)imm[i-1]<0x800)
9449       current.waswritten|=1<<rs1[i-1];
9450     current.waswritten&=~(1<<rt1[i]);
9451     current.waswritten&=~(1<<rt2[i]);
9452     if((itype[i]==STORE||itype[i]==STORELR||(itype[i]==C2LS&&opcode[i]==0x3a))&&(u_int)imm[i]>=0x800)
9453       current.waswritten&=~(1<<rs1[i]);
9454
9455     /* Branch post-alloc */
9456     if(i>0)
9457     {
9458       current.was32=current.is32;
9459       current.wasdirty=current.dirty;
9460       switch(itype[i-1]) {
9461         case UJUMP:
9462           memcpy(&branch_regs[i-1],&current,sizeof(current));
9463           branch_regs[i-1].isconst=0;
9464           branch_regs[i-1].wasconst=0;
9465           branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1]));
9466           branch_regs[i-1].uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i-1])|(1LL<<us2[i-1]));
9467           alloc_cc(&branch_regs[i-1],i-1);
9468           dirty_reg(&branch_regs[i-1],CCREG);
9469           if(rt1[i-1]==31) { // JAL
9470             alloc_reg(&branch_regs[i-1],i-1,31);
9471             dirty_reg(&branch_regs[i-1],31);
9472             branch_regs[i-1].is32|=1LL<<31;
9473           }
9474           memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9475           memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9476           break;
9477         case RJUMP:
9478           memcpy(&branch_regs[i-1],&current,sizeof(current));
9479           branch_regs[i-1].isconst=0;
9480           branch_regs[i-1].wasconst=0;
9481           branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1]));
9482           branch_regs[i-1].uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i-1])|(1LL<<us2[i-1]));
9483           alloc_cc(&branch_regs[i-1],i-1);
9484           dirty_reg(&branch_regs[i-1],CCREG);
9485           alloc_reg(&branch_regs[i-1],i-1,rs1[i-1]);
9486           if(rt1[i-1]!=0) { // JALR
9487             alloc_reg(&branch_regs[i-1],i-1,rt1[i-1]);
9488             dirty_reg(&branch_regs[i-1],rt1[i-1]);
9489             branch_regs[i-1].is32|=1LL<<rt1[i-1];
9490           }
9491           #ifdef USE_MINI_HT
9492           if(rs1[i-1]==31) { // JALR
9493             alloc_reg(&branch_regs[i-1],i-1,RHASH);
9494             #ifndef HOST_IMM_ADDR32
9495             alloc_reg(&branch_regs[i-1],i-1,RHTBL);
9496             #endif
9497           }
9498           #endif
9499           memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9500           memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9501           break;
9502         case CJUMP:
9503           if((opcode[i-1]&0x3E)==4) // BEQ/BNE
9504           {
9505             alloc_cc(&current,i-1);
9506             dirty_reg(&current,CCREG);
9507             if((rs1[i-1]&&(rs1[i-1]==rt1[i]||rs1[i-1]==rt2[i]))||
9508                (rs2[i-1]&&(rs2[i-1]==rt1[i]||rs2[i-1]==rt2[i]))) {
9509               // The delay slot overwrote one of our conditions
9510               // Delay slot goes after the test (in order)
9511               current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
9512               current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i]));
9513               if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9514               current.u|=1;
9515               current.uu|=1;
9516               delayslot_alloc(&current,i);
9517               current.isconst=0;
9518             }
9519             else
9520             {
9521               current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1]));
9522               current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i-1])|(1LL<<us2[i-1]));
9523               // Alloc the branch condition registers
9524               if(rs1[i-1]) alloc_reg(&current,i-1,rs1[i-1]);
9525               if(rs2[i-1]) alloc_reg(&current,i-1,rs2[i-1]);
9526               if(!((current.is32>>rs1[i-1])&(current.is32>>rs2[i-1])&1))
9527               {
9528                 if(rs1[i-1]) alloc_reg64(&current,i-1,rs1[i-1]);
9529                 if(rs2[i-1]) alloc_reg64(&current,i-1,rs2[i-1]);
9530               }
9531             }
9532             memcpy(&branch_regs[i-1],&current,sizeof(current));
9533             branch_regs[i-1].isconst=0;
9534             branch_regs[i-1].wasconst=0;
9535             memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
9536             memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9537           }
9538           else
9539           if((opcode[i-1]&0x3E)==6) // BLEZ/BGTZ
9540           {
9541             alloc_cc(&current,i-1);
9542             dirty_reg(&current,CCREG);
9543             if(rs1[i-1]==rt1[i]||rs1[i-1]==rt2[i]) {
9544               // The delay slot overwrote the branch condition
9545               // Delay slot goes after the test (in order)
9546               current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
9547               current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i]));
9548               if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9549               current.u|=1;
9550               current.uu|=1;
9551               delayslot_alloc(&current,i);
9552               current.isconst=0;
9553             }
9554             else
9555             {
9556               current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]);
9557               current.uu=branch_unneeded_reg_upper[i-1]&~(1LL<<us1[i-1]);
9558               // Alloc the branch condition register
9559               alloc_reg(&current,i-1,rs1[i-1]);
9560               if(!(current.is32>>rs1[i-1]&1))
9561               {
9562                 alloc_reg64(&current,i-1,rs1[i-1]);
9563               }
9564             }
9565             memcpy(&branch_regs[i-1],&current,sizeof(current));
9566             branch_regs[i-1].isconst=0;
9567             branch_regs[i-1].wasconst=0;
9568             memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
9569             memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9570           }
9571           else
9572           // Alloc the delay slot in case the branch is taken
9573           if((opcode[i-1]&0x3E)==0x14) // BEQL/BNEL
9574           {
9575             memcpy(&branch_regs[i-1],&current,sizeof(current));
9576             branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9577             branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9578             if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9579             alloc_cc(&branch_regs[i-1],i);
9580             dirty_reg(&branch_regs[i-1],CCREG);
9581             delayslot_alloc(&branch_regs[i-1],i);
9582             branch_regs[i-1].isconst=0;
9583             alloc_reg(&current,i,CCREG); // Not taken path
9584             dirty_reg(&current,CCREG);
9585             memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9586           }
9587           else
9588           if((opcode[i-1]&0x3E)==0x16) // BLEZL/BGTZL
9589           {
9590             memcpy(&branch_regs[i-1],&current,sizeof(current));
9591             branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9592             branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9593             if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9594             alloc_cc(&branch_regs[i-1],i);
9595             dirty_reg(&branch_regs[i-1],CCREG);
9596             delayslot_alloc(&branch_regs[i-1],i);
9597             branch_regs[i-1].isconst=0;
9598             alloc_reg(&current,i,CCREG); // Not taken path
9599             dirty_reg(&current,CCREG);
9600             memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9601           }
9602           break;
9603         case SJUMP:
9604           //if((opcode2[i-1]&0x1E)==0) // BLTZ/BGEZ
9605           if((opcode2[i-1]&0x0E)==0) // BLTZ/BGEZ
9606           {
9607             alloc_cc(&current,i-1);
9608             dirty_reg(&current,CCREG);
9609             if(rs1[i-1]==rt1[i]||rs1[i-1]==rt2[i]) {
9610               // The delay slot overwrote the branch condition
9611               // Delay slot goes after the test (in order)
9612               current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
9613               current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i]));
9614               if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9615               current.u|=1;
9616               current.uu|=1;
9617               delayslot_alloc(&current,i);
9618               current.isconst=0;
9619             }
9620             else
9621             {
9622               current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]);
9623               current.uu=branch_unneeded_reg_upper[i-1]&~(1LL<<us1[i-1]);
9624               // Alloc the branch condition register
9625               alloc_reg(&current,i-1,rs1[i-1]);
9626               if(!(current.is32>>rs1[i-1]&1))
9627               {
9628                 alloc_reg64(&current,i-1,rs1[i-1]);
9629               }
9630             }
9631             memcpy(&branch_regs[i-1],&current,sizeof(current));
9632             branch_regs[i-1].isconst=0;
9633             branch_regs[i-1].wasconst=0;
9634             memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
9635             memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9636           }
9637           else
9638           // Alloc the delay slot in case the branch is taken
9639           if((opcode2[i-1]&0x1E)==2) // BLTZL/BGEZL
9640           {
9641             memcpy(&branch_regs[i-1],&current,sizeof(current));
9642             branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9643             branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9644             if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9645             alloc_cc(&branch_regs[i-1],i);
9646             dirty_reg(&branch_regs[i-1],CCREG);
9647             delayslot_alloc(&branch_regs[i-1],i);
9648             branch_regs[i-1].isconst=0;
9649             alloc_reg(&current,i,CCREG); // Not taken path
9650             dirty_reg(&current,CCREG);
9651             memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9652           }
9653           // FIXME: BLTZAL/BGEZAL
9654           if(opcode2[i-1]&0x10) { // BxxZAL
9655             alloc_reg(&branch_regs[i-1],i-1,31);
9656             dirty_reg(&branch_regs[i-1],31);
9657             branch_regs[i-1].is32|=1LL<<31;
9658           }
9659           break;
9660         case FJUMP:
9661           if(likely[i-1]==0) // BC1F/BC1T
9662           {
9663             alloc_cc(&current,i-1);
9664             dirty_reg(&current,CCREG);
9665             if(itype[i]==FCOMP) {
9666               // The delay slot overwrote the branch condition
9667               // Delay slot goes after the test (in order)
9668               delayslot_alloc(&current,i);
9669               current.isconst=0;
9670             }
9671             else
9672             {
9673               current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]);
9674               current.uu=branch_unneeded_reg_upper[i-1]&~(1LL<<us1[i-1]);
9675               // Alloc the branch condition register
9676               alloc_reg(&current,i-1,FSREG);
9677             }
9678             memcpy(&branch_regs[i-1],&current,sizeof(current));
9679             memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
9680           }
9681           else // BC1FL/BC1TL
9682           {
9683             // Alloc the delay slot in case the branch is taken
9684             memcpy(&branch_regs[i-1],&current,sizeof(current));
9685             branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9686             branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9687             if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9688             alloc_cc(&branch_regs[i-1],i);
9689             dirty_reg(&branch_regs[i-1],CCREG);
9690             delayslot_alloc(&branch_regs[i-1],i);
9691             branch_regs[i-1].isconst=0;
9692             alloc_reg(&current,i,CCREG); // Not taken path
9693             dirty_reg(&current,CCREG);
9694             memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9695           }
9696           break;
9697       }
9698
9699       if(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)
9700       {
9701         if(rt1[i-1]==31) // JAL/JALR
9702         {
9703           // Subroutine call will return here, don't alloc any registers
9704           current.is32=1;
9705           current.dirty=0;
9706           clear_all_regs(current.regmap);
9707           alloc_reg(&current,i,CCREG);
9708           dirty_reg(&current,CCREG);
9709         }
9710         else if(i+1<slen)
9711         {
9712           // Internal branch will jump here, match registers to caller
9713           current.is32=0x3FFFFFFFFLL;
9714           current.dirty=0;
9715           clear_all_regs(current.regmap);
9716           alloc_reg(&current,i,CCREG);
9717           dirty_reg(&current,CCREG);
9718           for(j=i-1;j>=0;j--)
9719           {
9720             if(ba[j]==start+i*4+4) {
9721               memcpy(current.regmap,branch_regs[j].regmap,sizeof(current.regmap));
9722               current.is32=branch_regs[j].is32;
9723               current.dirty=branch_regs[j].dirty;
9724               break;
9725             }
9726           }
9727           while(j>=0) {
9728             if(ba[j]==start+i*4+4) {
9729               for(hr=0;hr<HOST_REGS;hr++) {
9730                 if(current.regmap[hr]!=branch_regs[j].regmap[hr]) {
9731                   current.regmap[hr]=-1;
9732                 }
9733                 current.is32&=branch_regs[j].is32;
9734                 current.dirty&=branch_regs[j].dirty;
9735               }
9736             }
9737             j--;
9738           }
9739         }
9740       }
9741     }
9742
9743     // Count cycles in between branches
9744     ccadj[i]=cc;
9745     if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP||itype[i]==SYSCALL||itype[i]==HLECALL))
9746     {
9747       cc=0;
9748     }
9749 #ifdef PCSX
9750     else if(itype[i]==C2OP&&gte_cycletab[source[i]&0x3f]>2)
9751     {
9752       // GTE runs in parallel until accessed, divide by 2 for a rough guess
9753       cc+=gte_cycletab[source[i]&0x3f]/2;
9754     }
9755     else if(/*itype[i]==LOAD||*/itype[i]==STORE||itype[i]==C1LS) // load causes weird timing issues
9756     {
9757       cc+=2; // 2 cycle penalty (after CLOCK_DIVIDER)
9758     }
9759     else if(itype[i]==C2LS)
9760     {
9761       cc+=4;
9762     }
9763 #endif
9764     else
9765     {
9766       cc++;
9767     }
9768
9769     flush_dirty_uppers(&current);
9770     if(!is_ds[i]) {
9771       regs[i].is32=current.is32;
9772       regs[i].dirty=current.dirty;
9773       regs[i].isconst=current.isconst;
9774       memcpy(constmap[i],current.constmap,sizeof(current.constmap));
9775     }
9776     for(hr=0;hr<HOST_REGS;hr++) {
9777       if(hr!=EXCLUDE_REG&&regs[i].regmap[hr]>=0) {
9778         if(regmap_pre[i][hr]!=regs[i].regmap[hr]) {
9779           regs[i].wasconst&=~(1<<hr);
9780         }
9781       }
9782     }
9783     if(current.regmap[HOST_BTREG]==BTREG) current.regmap[HOST_BTREG]=-1;
9784     regs[i].waswritten=current.waswritten;
9785   }
9786
9787   /* Pass 4 - Cull unused host registers */
9788
9789   uint64_t nr=0;
9790
9791   for (i=slen-1;i>=0;i--)
9792   {
9793     int hr;
9794     if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
9795     {
9796       if(ba[i]<start || ba[i]>=(start+slen*4))
9797       {
9798         // Branch out of this block, don't need anything
9799         nr=0;
9800       }
9801       else
9802       {
9803         // Internal branch
9804         // Need whatever matches the target
9805         nr=0;
9806         int t=(ba[i]-start)>>2;
9807         for(hr=0;hr<HOST_REGS;hr++)
9808         {
9809           if(regs[i].regmap_entry[hr]>=0) {
9810             if(regs[i].regmap_entry[hr]==regs[t].regmap_entry[hr]) nr|=1<<hr;
9811           }
9812         }
9813       }
9814       // Conditional branch may need registers for following instructions
9815       if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
9816       {
9817         if(i<slen-2) {
9818           nr|=needed_reg[i+2];
9819           for(hr=0;hr<HOST_REGS;hr++)
9820           {
9821             if(regmap_pre[i+2][hr]>=0&&get_reg(regs[i+2].regmap_entry,regmap_pre[i+2][hr])<0) nr&=~(1<<hr);
9822             //if((regmap_entry[i+2][hr])>=0) if(!((nr>>hr)&1)) printf("%x-bogus(%d=%d)\n",start+i*4,hr,regmap_entry[i+2][hr]);
9823           }
9824         }
9825       }
9826       // Don't need stuff which is overwritten
9827       //if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr);
9828       //if(regs[i].regmap[hr]<0) nr&=~(1<<hr);
9829       // Merge in delay slot
9830       for(hr=0;hr<HOST_REGS;hr++)
9831       {
9832         if(!likely[i]) {
9833           // These are overwritten unless the branch is "likely"
9834           // and the delay slot is nullified if not taken
9835           if(rt1[i+1]&&rt1[i+1]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9836           if(rt2[i+1]&&rt2[i+1]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9837         }
9838         if(us1[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9839         if(us2[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9840         if(rs1[i+1]==regmap_pre[i][hr]) nr|=1<<hr;
9841         if(rs2[i+1]==regmap_pre[i][hr]) nr|=1<<hr;
9842         if(us1[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9843         if(us2[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9844         if(rs1[i+1]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9845         if(rs2[i+1]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9846         if(dep1[i+1]&&!((unneeded_reg_upper[i]>>dep1[i+1])&1)) {
9847           if(dep1[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9848           if(dep2[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9849         }
9850         if(dep2[i+1]&&!((unneeded_reg_upper[i]>>dep2[i+1])&1)) {
9851           if(dep1[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9852           if(dep2[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9853         }
9854         if(itype[i+1]==STORE || itype[i+1]==STORELR || (opcode[i+1]&0x3b)==0x39 || (opcode[i+1]&0x3b)==0x3a) {
9855           if(regmap_pre[i][hr]==INVCP) nr|=1<<hr;
9856           if(regs[i].regmap_entry[hr]==INVCP) nr|=1<<hr;
9857         }
9858       }
9859     }
9860     else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
9861     {
9862       // SYSCALL instruction (software interrupt)
9863       nr=0;
9864     }
9865     else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
9866     {
9867       // ERET instruction (return from interrupt)
9868       nr=0;
9869     }
9870     else // Non-branch
9871     {
9872       if(i<slen-1) {
9873         for(hr=0;hr<HOST_REGS;hr++) {
9874           if(regmap_pre[i+1][hr]>=0&&get_reg(regs[i+1].regmap_entry,regmap_pre[i+1][hr])<0) nr&=~(1<<hr);
9875           if(regs[i].regmap[hr]!=regmap_pre[i+1][hr]) nr&=~(1<<hr);
9876           if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr);
9877           if(regs[i].regmap[hr]<0) nr&=~(1<<hr);
9878         }
9879       }
9880     }
9881     for(hr=0;hr<HOST_REGS;hr++)
9882     {
9883       // Overwritten registers are not needed
9884       if(rt1[i]&&rt1[i]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9885       if(rt2[i]&&rt2[i]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9886       if(FTEMP==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9887       // Source registers are needed
9888       if(us1[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9889       if(us2[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9890       if(rs1[i]==regmap_pre[i][hr]) nr|=1<<hr;
9891       if(rs2[i]==regmap_pre[i][hr]) nr|=1<<hr;
9892       if(us1[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9893       if(us2[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9894       if(rs1[i]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9895       if(rs2[i]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9896       if(dep1[i]&&!((unneeded_reg_upper[i]>>dep1[i])&1)) {
9897         if(dep1[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9898         if(dep1[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9899       }
9900       if(dep2[i]&&!((unneeded_reg_upper[i]>>dep2[i])&1)) {
9901         if(dep2[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9902         if(dep2[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9903       }
9904       if(itype[i]==STORE || itype[i]==STORELR || (opcode[i]&0x3b)==0x39 || (opcode[i]&0x3b)==0x3a) {
9905         if(regmap_pre[i][hr]==INVCP) nr|=1<<hr;
9906         if(regs[i].regmap_entry[hr]==INVCP) nr|=1<<hr;
9907       }
9908       // Don't store a register immediately after writing it,
9909       // may prevent dual-issue.
9910       // But do so if this is a branch target, otherwise we
9911       // might have to load the register before the branch.
9912       if(i>0&&!bt[i]&&((regs[i].wasdirty>>hr)&1)) {
9913         if((regmap_pre[i][hr]>0&&regmap_pre[i][hr]<64&&!((unneeded_reg[i]>>regmap_pre[i][hr])&1)) ||
9914            (regmap_pre[i][hr]>64&&!((unneeded_reg_upper[i]>>(regmap_pre[i][hr]&63))&1)) ) {
9915           if(rt1[i-1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9916           if(rt2[i-1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9917         }
9918         if((regs[i].regmap_entry[hr]>0&&regs[i].regmap_entry[hr]<64&&!((unneeded_reg[i]>>regs[i].regmap_entry[hr])&1)) ||
9919            (regs[i].regmap_entry[hr]>64&&!((unneeded_reg_upper[i]>>(regs[i].regmap_entry[hr]&63))&1)) ) {
9920           if(rt1[i-1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9921           if(rt2[i-1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9922         }
9923       }
9924     }
9925     // Cycle count is needed at branches.  Assume it is needed at the target too.
9926     if(i==0||bt[i]||itype[i]==CJUMP||itype[i]==FJUMP||itype[i]==SPAN) {
9927       if(regmap_pre[i][HOST_CCREG]==CCREG) nr|=1<<HOST_CCREG;
9928       if(regs[i].regmap_entry[HOST_CCREG]==CCREG) nr|=1<<HOST_CCREG;
9929     }
9930     // Save it
9931     needed_reg[i]=nr;
9932
9933     // Deallocate unneeded registers
9934     for(hr=0;hr<HOST_REGS;hr++)
9935     {
9936       if(!((nr>>hr)&1)) {
9937         if(regs[i].regmap_entry[hr]!=CCREG) regs[i].regmap_entry[hr]=-1;
9938         if((regs[i].regmap[hr]&63)!=rs1[i] && (regs[i].regmap[hr]&63)!=rs2[i] &&
9939            (regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] &&
9940            (regs[i].regmap[hr]&63)!=PTEMP && (regs[i].regmap[hr]&63)!=CCREG)
9941         {
9942           if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
9943           {
9944             if(likely[i]) {
9945               regs[i].regmap[hr]=-1;
9946               regs[i].isconst&=~(1<<hr);
9947               if(i<slen-2) {
9948                 regmap_pre[i+2][hr]=-1;
9949                 regs[i+2].wasconst&=~(1<<hr);
9950               }
9951             }
9952           }
9953         }
9954         if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
9955         {
9956           int d1=0,d2=0,map=0,temp=0;
9957           if(get_reg(regs[i].regmap,rt1[i+1]|64)>=0||get_reg(branch_regs[i].regmap,rt1[i+1]|64)>=0)
9958           {
9959             d1=dep1[i+1];
9960             d2=dep2[i+1];
9961           }
9962           if(using_tlb) {
9963             if(itype[i+1]==LOAD || itype[i+1]==LOADLR ||
9964                itype[i+1]==STORE || itype[i+1]==STORELR ||
9965                itype[i+1]==C1LS || itype[i+1]==C2LS)
9966             map=TLREG;
9967           } else
9968           if(itype[i+1]==STORE || itype[i+1]==STORELR ||
9969              (opcode[i+1]&0x3b)==0x39 || (opcode[i+1]&0x3b)==0x3a) { // SWC1/SDC1 || SWC2/SDC2
9970             map=INVCP;
9971           }
9972           if(itype[i+1]==LOADLR || itype[i+1]==STORELR ||
9973              itype[i+1]==C1LS || itype[i+1]==C2LS)
9974             temp=FTEMP;
9975           if((regs[i].regmap[hr]&63)!=rs1[i] && (regs[i].regmap[hr]&63)!=rs2[i] &&
9976              (regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] &&
9977              (regs[i].regmap[hr]&63)!=rt1[i+1] && (regs[i].regmap[hr]&63)!=rt2[i+1] &&
9978              (regs[i].regmap[hr]^64)!=us1[i+1] && (regs[i].regmap[hr]^64)!=us2[i+1] &&
9979              (regs[i].regmap[hr]^64)!=d1 && (regs[i].regmap[hr]^64)!=d2 &&
9980              regs[i].regmap[hr]!=rs1[i+1] && regs[i].regmap[hr]!=rs2[i+1] &&
9981              (regs[i].regmap[hr]&63)!=temp && regs[i].regmap[hr]!=PTEMP &&
9982              regs[i].regmap[hr]!=RHASH && regs[i].regmap[hr]!=RHTBL &&
9983              regs[i].regmap[hr]!=RTEMP && regs[i].regmap[hr]!=CCREG &&
9984              regs[i].regmap[hr]!=map )
9985           {
9986             regs[i].regmap[hr]=-1;
9987             regs[i].isconst&=~(1<<hr);
9988             if((branch_regs[i].regmap[hr]&63)!=rs1[i] && (branch_regs[i].regmap[hr]&63)!=rs2[i] &&
9989                (branch_regs[i].regmap[hr]&63)!=rt1[i] && (branch_regs[i].regmap[hr]&63)!=rt2[i] &&
9990                (branch_regs[i].regmap[hr]&63)!=rt1[i+1] && (branch_regs[i].regmap[hr]&63)!=rt2[i+1] &&
9991                (branch_regs[i].regmap[hr]^64)!=us1[i+1] && (branch_regs[i].regmap[hr]^64)!=us2[i+1] &&
9992                (branch_regs[i].regmap[hr]^64)!=d1 && (branch_regs[i].regmap[hr]^64)!=d2 &&
9993                branch_regs[i].regmap[hr]!=rs1[i+1] && branch_regs[i].regmap[hr]!=rs2[i+1] &&
9994                (branch_regs[i].regmap[hr]&63)!=temp && branch_regs[i].regmap[hr]!=PTEMP &&
9995                branch_regs[i].regmap[hr]!=RHASH && branch_regs[i].regmap[hr]!=RHTBL &&
9996                branch_regs[i].regmap[hr]!=RTEMP && branch_regs[i].regmap[hr]!=CCREG &&
9997                branch_regs[i].regmap[hr]!=map)
9998             {
9999               branch_regs[i].regmap[hr]=-1;
10000               branch_regs[i].regmap_entry[hr]=-1;
10001               if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
10002               {
10003                 if(!likely[i]&&i<slen-2) {
10004                   regmap_pre[i+2][hr]=-1;
10005                   regs[i+2].wasconst&=~(1<<hr);
10006                 }
10007               }
10008             }
10009           }
10010         }
10011         else
10012         {
10013           // Non-branch
10014           if(i>0)
10015           {
10016             int d1=0,d2=0,map=-1,temp=-1;
10017             if(get_reg(regs[i].regmap,rt1[i]|64)>=0)
10018             {
10019               d1=dep1[i];
10020               d2=dep2[i];
10021             }
10022             if(using_tlb) {
10023               if(itype[i]==LOAD || itype[i]==LOADLR ||
10024                  itype[i]==STORE || itype[i]==STORELR ||
10025                  itype[i]==C1LS || itype[i]==C2LS)
10026               map=TLREG;
10027             } else if(itype[i]==STORE || itype[i]==STORELR ||
10028                       (opcode[i]&0x3b)==0x39 || (opcode[i]&0x3b)==0x3a) { // SWC1/SDC1 || SWC2/SDC2
10029               map=INVCP;
10030             }
10031             if(itype[i]==LOADLR || itype[i]==STORELR ||
10032                itype[i]==C1LS || itype[i]==C2LS)
10033               temp=FTEMP;
10034             if((regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] &&
10035                (regs[i].regmap[hr]^64)!=us1[i] && (regs[i].regmap[hr]^64)!=us2[i] &&
10036                (regs[i].regmap[hr]^64)!=d1 && (regs[i].regmap[hr]^64)!=d2 &&
10037                regs[i].regmap[hr]!=rs1[i] && regs[i].regmap[hr]!=rs2[i] &&
10038                (regs[i].regmap[hr]&63)!=temp && regs[i].regmap[hr]!=map &&
10039                (itype[i]!=SPAN||regs[i].regmap[hr]!=CCREG))
10040             {
10041               if(i<slen-1&&!is_ds[i]) {
10042                 if(regmap_pre[i+1][hr]!=-1 || regs[i].regmap[hr]!=-1)
10043                 if(regmap_pre[i+1][hr]!=regs[i].regmap[hr])
10044                 if(regs[i].regmap[hr]<64||!((regs[i].was32>>(regs[i].regmap[hr]&63))&1))
10045                 {
10046                   printf("fail: %x (%d %d!=%d)\n",start+i*4,hr,regmap_pre[i+1][hr],regs[i].regmap[hr]);
10047                   assert(regmap_pre[i+1][hr]==regs[i].regmap[hr]);
10048                 }
10049                 regmap_pre[i+1][hr]=-1;
10050                 if(regs[i+1].regmap_entry[hr]==CCREG) regs[i+1].regmap_entry[hr]=-1;
10051                 regs[i+1].wasconst&=~(1<<hr);
10052               }
10053               regs[i].regmap[hr]=-1;
10054               regs[i].isconst&=~(1<<hr);
10055             }
10056           }
10057         }
10058       }
10059     }
10060   }
10061
10062   /* Pass 5 - Pre-allocate registers */
10063
10064   // If a register is allocated during a loop, try to allocate it for the
10065   // entire loop, if possible.  This avoids loading/storing registers
10066   // inside of the loop.
10067
10068   signed char f_regmap[HOST_REGS];
10069   clear_all_regs(f_regmap);
10070   for(i=0;i<slen-1;i++)
10071   {
10072     if(itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
10073     {
10074       if(ba[i]>=start && ba[i]<(start+i*4))
10075       if(itype[i+1]==NOP||itype[i+1]==MOV||itype[i+1]==ALU
10076       ||itype[i+1]==SHIFTIMM||itype[i+1]==IMM16||itype[i+1]==LOAD
10077       ||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS
10078       ||itype[i+1]==SHIFT||itype[i+1]==COP1||itype[i+1]==FLOAT
10079       ||itype[i+1]==FCOMP||itype[i+1]==FCONV
10080       ||itype[i+1]==COP2||itype[i+1]==C2LS||itype[i+1]==C2OP)
10081       {
10082         int t=(ba[i]-start)>>2;
10083         if(t>0&&(itype[t-1]!=UJUMP&&itype[t-1]!=RJUMP&&itype[t-1]!=CJUMP&&itype[t-1]!=SJUMP&&itype[t-1]!=FJUMP)) // loop_preload can't handle jumps into delay slots
10084         if(t<2||(itype[t-2]!=UJUMP&&itype[t-2]!=RJUMP)||rt1[t-2]!=31) // call/ret assumes no registers allocated
10085         for(hr=0;hr<HOST_REGS;hr++)
10086         {
10087           if(regs[i].regmap[hr]>64) {
10088             if(!((regs[i].dirty>>hr)&1))
10089               f_regmap[hr]=regs[i].regmap[hr];
10090             else f_regmap[hr]=-1;
10091           }
10092           else if(regs[i].regmap[hr]>=0) {
10093             if(f_regmap[hr]!=regs[i].regmap[hr]) {
10094               // dealloc old register
10095               int n;
10096               for(n=0;n<HOST_REGS;n++)
10097               {
10098                 if(f_regmap[n]==regs[i].regmap[hr]) {f_regmap[n]=-1;}
10099               }
10100               // and alloc new one
10101               f_regmap[hr]=regs[i].regmap[hr];
10102             }
10103           }
10104           if(branch_regs[i].regmap[hr]>64) {
10105             if(!((branch_regs[i].dirty>>hr)&1))
10106               f_regmap[hr]=branch_regs[i].regmap[hr];
10107             else f_regmap[hr]=-1;
10108           }
10109           else if(branch_regs[i].regmap[hr]>=0) {
10110             if(f_regmap[hr]!=branch_regs[i].regmap[hr]) {
10111               // dealloc old register
10112               int n;
10113               for(n=0;n<HOST_REGS;n++)
10114               {
10115                 if(f_regmap[n]==branch_regs[i].regmap[hr]) {f_regmap[n]=-1;}
10116               }
10117               // and alloc new one
10118               f_regmap[hr]=branch_regs[i].regmap[hr];
10119             }
10120           }
10121           if(ooo[i]) {
10122             if(count_free_regs(regs[i].regmap)<=minimum_free_regs[i+1])
10123               f_regmap[hr]=branch_regs[i].regmap[hr];
10124           }else{
10125             if(count_free_regs(branch_regs[i].regmap)<=minimum_free_regs[i+1])
10126               f_regmap[hr]=branch_regs[i].regmap[hr];
10127           }
10128           // Avoid dirty->clean transition
10129           #ifdef DESTRUCTIVE_WRITEBACK
10130           if(t>0) if(get_reg(regmap_pre[t],f_regmap[hr])>=0) if((regs[t].wasdirty>>get_reg(regmap_pre[t],f_regmap[hr]))&1) f_regmap[hr]=-1;
10131           #endif
10132           // This check is only strictly required in the DESTRUCTIVE_WRITEBACK
10133           // case above, however it's always a good idea.  We can't hoist the
10134           // load if the register was already allocated, so there's no point
10135           // wasting time analyzing most of these cases.  It only "succeeds"
10136           // when the mapping was different and the load can be replaced with
10137           // a mov, which is of negligible benefit.  So such cases are
10138           // skipped below.
10139           if(f_regmap[hr]>0) {
10140             if(regs[t].regmap[hr]==f_regmap[hr]||(regs[t].regmap_entry[hr]<0&&get_reg(regmap_pre[t],f_regmap[hr])<0)) {
10141               int r=f_regmap[hr];
10142               for(j=t;j<=i;j++)
10143               {
10144                 //printf("Test %x -> %x, %x %d/%d\n",start+i*4,ba[i],start+j*4,hr,r);
10145                 if(r<34&&((unneeded_reg[j]>>r)&1)) break;
10146                 if(r>63&&((unneeded_reg_upper[j]>>(r&63))&1)) break;
10147                 if(r>63) {
10148                   // NB This can exclude the case where the upper-half
10149                   // register is lower numbered than the lower-half
10150                   // register.  Not sure if it's worth fixing...
10151                   if(get_reg(regs[j].regmap,r&63)<0) break;
10152                   if(get_reg(regs[j].regmap_entry,r&63)<0) break;
10153                   if(regs[j].is32&(1LL<<(r&63))) break;
10154                 }
10155                 if(regs[j].regmap[hr]==f_regmap[hr]&&(f_regmap[hr]&63)<TEMPREG) {
10156                   //printf("Hit %x -> %x, %x %d/%d\n",start+i*4,ba[i],start+j*4,hr,r);
10157                   int k;
10158                   if(regs[i].regmap[hr]==-1&&branch_regs[i].regmap[hr]==-1) {
10159                     if(get_reg(regs[i+2].regmap,f_regmap[hr])>=0) break;
10160                     if(r>63) {
10161                       if(get_reg(regs[i].regmap,r&63)<0) break;
10162                       if(get_reg(branch_regs[i].regmap,r&63)<0) break;
10163                     }
10164                     k=i;
10165                     while(k>1&&regs[k-1].regmap[hr]==-1) {
10166                       if(count_free_regs(regs[k-1].regmap)<=minimum_free_regs[k-1]) {
10167                         //printf("no free regs for store %x\n",start+(k-1)*4);
10168                         break;
10169                       }
10170                       if(get_reg(regs[k-1].regmap,f_regmap[hr])>=0) {
10171                         //printf("no-match due to different register\n");
10172                         break;
10173                       }
10174                       if(itype[k-2]==UJUMP||itype[k-2]==RJUMP||itype[k-2]==CJUMP||itype[k-2]==SJUMP||itype[k-2]==FJUMP) {
10175                         //printf("no-match due to branch\n");
10176                         break;
10177                       }
10178                       // call/ret fast path assumes no registers allocated
10179                       if(k>2&&(itype[k-3]==UJUMP||itype[k-3]==RJUMP)&&rt1[k-3]==31) {
10180                         break;
10181                       }
10182                       if(r>63) {
10183                         // NB This can exclude the case where the upper-half
10184                         // register is lower numbered than the lower-half
10185                         // register.  Not sure if it's worth fixing...
10186                         if(get_reg(regs[k-1].regmap,r&63)<0) break;
10187                         if(regs[k-1].is32&(1LL<<(r&63))) break;
10188                       }
10189                       k--;
10190                     }
10191                     if(i<slen-1) {
10192                       if((regs[k].is32&(1LL<<f_regmap[hr]))!=
10193                         (regs[i+2].was32&(1LL<<f_regmap[hr]))) {
10194                         //printf("bad match after branch\n");
10195                         break;
10196                       }
10197                     }
10198                     if(regs[k-1].regmap[hr]==f_regmap[hr]&&regmap_pre[k][hr]==f_regmap[hr]) {
10199                       //printf("Extend r%d, %x ->\n",hr,start+k*4);
10200                       while(k<i) {
10201                         regs[k].regmap_entry[hr]=f_regmap[hr];
10202                         regs[k].regmap[hr]=f_regmap[hr];
10203                         regmap_pre[k+1][hr]=f_regmap[hr];
10204                         regs[k].wasdirty&=~(1<<hr);
10205                         regs[k].dirty&=~(1<<hr);
10206                         regs[k].wasdirty|=(1<<hr)&regs[k-1].dirty;
10207                         regs[k].dirty|=(1<<hr)&regs[k].wasdirty;
10208                         regs[k].wasconst&=~(1<<hr);
10209                         regs[k].isconst&=~(1<<hr);
10210                         k++;
10211                       }
10212                     }
10213                     else {
10214                       //printf("Fail Extend r%d, %x ->\n",hr,start+k*4);
10215                       break;
10216                     }
10217                     assert(regs[i-1].regmap[hr]==f_regmap[hr]);
10218                     if(regs[i-1].regmap[hr]==f_regmap[hr]&&regmap_pre[i][hr]==f_regmap[hr]) {
10219                       //printf("OK fill %x (r%d)\n",start+i*4,hr);
10220                       regs[i].regmap_entry[hr]=f_regmap[hr];
10221                       regs[i].regmap[hr]=f_regmap[hr];
10222                       regs[i].wasdirty&=~(1<<hr);
10223                       regs[i].dirty&=~(1<<hr);
10224                       regs[i].wasdirty|=(1<<hr)&regs[i-1].dirty;
10225                       regs[i].dirty|=(1<<hr)&regs[i-1].dirty;
10226                       regs[i].wasconst&=~(1<<hr);
10227                       regs[i].isconst&=~(1<<hr);
10228                       branch_regs[i].regmap_entry[hr]=f_regmap[hr];
10229                       branch_regs[i].wasdirty&=~(1<<hr);
10230                       branch_regs[i].wasdirty|=(1<<hr)&regs[i].dirty;
10231                       branch_regs[i].regmap[hr]=f_regmap[hr];
10232                       branch_regs[i].dirty&=~(1<<hr);
10233                       branch_regs[i].dirty|=(1<<hr)&regs[i].dirty;
10234                       branch_regs[i].wasconst&=~(1<<hr);
10235                       branch_regs[i].isconst&=~(1<<hr);
10236                       if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000) {
10237                         regmap_pre[i+2][hr]=f_regmap[hr];
10238                         regs[i+2].wasdirty&=~(1<<hr);
10239                         regs[i+2].wasdirty|=(1<<hr)&regs[i].dirty;
10240                         assert((branch_regs[i].is32&(1LL<<f_regmap[hr]))==
10241                           (regs[i+2].was32&(1LL<<f_regmap[hr])));
10242                       }
10243                     }
10244                   }
10245                   for(k=t;k<j;k++) {
10246                     // Alloc register clean at beginning of loop,
10247                     // but may dirty it in pass 6
10248                     regs[k].regmap_entry[hr]=f_regmap[hr];
10249                     regs[k].regmap[hr]=f_regmap[hr];
10250                     regs[k].dirty&=~(1<<hr);
10251                     regs[k].wasconst&=~(1<<hr);
10252                     regs[k].isconst&=~(1<<hr);
10253                     if(itype[k]==UJUMP||itype[k]==RJUMP||itype[k]==CJUMP||itype[k]==SJUMP||itype[k]==FJUMP) {
10254                       branch_regs[k].regmap_entry[hr]=f_regmap[hr];
10255                       branch_regs[k].regmap[hr]=f_regmap[hr];
10256                       branch_regs[k].dirty&=~(1<<hr);
10257                       branch_regs[k].wasconst&=~(1<<hr);
10258                       branch_regs[k].isconst&=~(1<<hr);
10259                       if(itype[k]!=RJUMP&&itype[k]!=UJUMP&&(source[k]>>16)!=0x1000) {
10260                         regmap_pre[k+2][hr]=f_regmap[hr];
10261                         regs[k+2].wasdirty&=~(1<<hr);
10262                         assert((branch_regs[k].is32&(1LL<<f_regmap[hr]))==
10263                           (regs[k+2].was32&(1LL<<f_regmap[hr])));
10264                       }
10265                     }
10266                     else
10267                     {
10268                       regmap_pre[k+1][hr]=f_regmap[hr];
10269                       regs[k+1].wasdirty&=~(1<<hr);
10270                     }
10271                   }
10272                   if(regs[j].regmap[hr]==f_regmap[hr])
10273                     regs[j].regmap_entry[hr]=f_regmap[hr];
10274                   break;
10275                 }
10276                 if(j==i) break;
10277                 if(regs[j].regmap[hr]>=0)
10278                   break;
10279                 if(get_reg(regs[j].regmap,f_regmap[hr])>=0) {
10280                   //printf("no-match due to different register\n");
10281                   break;
10282                 }
10283                 if((regs[j+1].is32&(1LL<<f_regmap[hr]))!=(regs[j].is32&(1LL<<f_regmap[hr]))) {
10284                   //printf("32/64 mismatch %x %d\n",start+j*4,hr);
10285                   break;
10286                 }
10287                 if(itype[j]==UJUMP||itype[j]==RJUMP||(source[j]>>16)==0x1000)
10288                 {
10289                   // Stop on unconditional branch
10290                   break;
10291                 }
10292                 if(itype[j]==CJUMP||itype[j]==SJUMP||itype[j]==FJUMP)
10293                 {
10294                   if(ooo[j]) {
10295                     if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j+1])
10296                       break;
10297                   }else{
10298                     if(count_free_regs(branch_regs[j].regmap)<=minimum_free_regs[j+1])
10299                       break;
10300                   }
10301                   if(get_reg(branch_regs[j].regmap,f_regmap[hr])>=0) {
10302                     //printf("no-match due to different register (branch)\n");
10303                     break;
10304                   }
10305                 }
10306                 if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j]) {
10307                   //printf("No free regs for store %x\n",start+j*4);
10308                   break;
10309                 }
10310                 if(f_regmap[hr]>=64) {
10311                   if(regs[j].is32&(1LL<<(f_regmap[hr]&63))) {
10312                     break;
10313                   }
10314                   else
10315                   {
10316                     if(get_reg(regs[j].regmap,f_regmap[hr]&63)<0) {
10317                       break;
10318                     }
10319                   }
10320                 }
10321               }
10322             }
10323           }
10324         }
10325       }
10326     }else{
10327       // Non branch or undetermined branch target
10328       for(hr=0;hr<HOST_REGS;hr++)
10329       {
10330         if(hr!=EXCLUDE_REG) {
10331           if(regs[i].regmap[hr]>64) {
10332             if(!((regs[i].dirty>>hr)&1))
10333               f_regmap[hr]=regs[i].regmap[hr];
10334           }
10335           else if(regs[i].regmap[hr]>=0) {
10336             if(f_regmap[hr]!=regs[i].regmap[hr]) {
10337               // dealloc old register
10338               int n;
10339               for(n=0;n<HOST_REGS;n++)
10340               {
10341                 if(f_regmap[n]==regs[i].regmap[hr]) {f_regmap[n]=-1;}
10342               }
10343               // and alloc new one
10344               f_regmap[hr]=regs[i].regmap[hr];
10345             }
10346           }
10347         }
10348       }
10349       // Try to restore cycle count at branch targets
10350       if(bt[i]) {
10351         for(j=i;j<slen-1;j++) {
10352           if(regs[j].regmap[HOST_CCREG]!=-1) break;
10353           if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j]) {
10354             //printf("no free regs for store %x\n",start+j*4);
10355             break;
10356           }
10357         }
10358         if(regs[j].regmap[HOST_CCREG]==CCREG) {
10359           int k=i;
10360           //printf("Extend CC, %x -> %x\n",start+k*4,start+j*4);
10361           while(k<j) {
10362             regs[k].regmap_entry[HOST_CCREG]=CCREG;
10363             regs[k].regmap[HOST_CCREG]=CCREG;
10364             regmap_pre[k+1][HOST_CCREG]=CCREG;
10365             regs[k+1].wasdirty|=1<<HOST_CCREG;
10366             regs[k].dirty|=1<<HOST_CCREG;
10367             regs[k].wasconst&=~(1<<HOST_CCREG);
10368             regs[k].isconst&=~(1<<HOST_CCREG);
10369             k++;
10370           }
10371           regs[j].regmap_entry[HOST_CCREG]=CCREG;
10372         }
10373         // Work backwards from the branch target
10374         if(j>i&&f_regmap[HOST_CCREG]==CCREG)
10375         {
10376           //printf("Extend backwards\n");
10377           int k;
10378           k=i;
10379           while(regs[k-1].regmap[HOST_CCREG]==-1) {
10380             if(count_free_regs(regs[k-1].regmap)<=minimum_free_regs[k-1]) {
10381               //printf("no free regs for store %x\n",start+(k-1)*4);
10382               break;
10383             }
10384             k--;
10385           }
10386           if(regs[k-1].regmap[HOST_CCREG]==CCREG) {
10387             //printf("Extend CC, %x ->\n",start+k*4);
10388             while(k<=i) {
10389               regs[k].regmap_entry[HOST_CCREG]=CCREG;
10390               regs[k].regmap[HOST_CCREG]=CCREG;
10391               regmap_pre[k+1][HOST_CCREG]=CCREG;
10392               regs[k+1].wasdirty|=1<<HOST_CCREG;
10393               regs[k].dirty|=1<<HOST_CCREG;
10394               regs[k].wasconst&=~(1<<HOST_CCREG);
10395               regs[k].isconst&=~(1<<HOST_CCREG);
10396               k++;
10397             }
10398           }
10399           else {
10400             //printf("Fail Extend CC, %x ->\n",start+k*4);
10401           }
10402         }
10403       }
10404       if(itype[i]!=STORE&&itype[i]!=STORELR&&itype[i]!=C1LS&&itype[i]!=SHIFT&&
10405          itype[i]!=NOP&&itype[i]!=MOV&&itype[i]!=ALU&&itype[i]!=SHIFTIMM&&
10406          itype[i]!=IMM16&&itype[i]!=LOAD&&itype[i]!=COP1&&itype[i]!=FLOAT&&
10407          itype[i]!=FCONV&&itype[i]!=FCOMP)
10408       {
10409         memcpy(f_regmap,regs[i].regmap,sizeof(f_regmap));
10410       }
10411     }
10412   }
10413
10414   // Cache memory offset or tlb map pointer if a register is available
10415   #ifndef HOST_IMM_ADDR32
10416   #ifndef RAM_OFFSET
10417   if(using_tlb)
10418   #endif
10419   {
10420     int earliest_available[HOST_REGS];
10421     int loop_start[HOST_REGS];
10422     int score[HOST_REGS];
10423     int end[HOST_REGS];
10424     int reg=using_tlb?MMREG:ROREG;
10425
10426     // Init
10427     for(hr=0;hr<HOST_REGS;hr++) {
10428       score[hr]=0;earliest_available[hr]=0;
10429       loop_start[hr]=MAXBLOCK;
10430     }
10431     for(i=0;i<slen-1;i++)
10432     {
10433       // Can't do anything if no registers are available
10434       if(count_free_regs(regs[i].regmap)<=minimum_free_regs[i]) {
10435         for(hr=0;hr<HOST_REGS;hr++) {
10436           score[hr]=0;earliest_available[hr]=i+1;
10437           loop_start[hr]=MAXBLOCK;
10438         }
10439       }
10440       if(itype[i]==UJUMP||itype[i]==RJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP) {
10441         if(!ooo[i]) {
10442           if(count_free_regs(branch_regs[i].regmap)<=minimum_free_regs[i+1]) {
10443             for(hr=0;hr<HOST_REGS;hr++) {
10444               score[hr]=0;earliest_available[hr]=i+1;
10445               loop_start[hr]=MAXBLOCK;
10446             }
10447           }
10448         }else{
10449           if(count_free_regs(regs[i].regmap)<=minimum_free_regs[i+1]) {
10450             for(hr=0;hr<HOST_REGS;hr++) {
10451               score[hr]=0;earliest_available[hr]=i+1;
10452               loop_start[hr]=MAXBLOCK;
10453             }
10454           }
10455         }
10456       }
10457       // Mark unavailable registers
10458       for(hr=0;hr<HOST_REGS;hr++) {
10459         if(regs[i].regmap[hr]>=0) {
10460           score[hr]=0;earliest_available[hr]=i+1;
10461           loop_start[hr]=MAXBLOCK;
10462         }
10463         if(itype[i]==UJUMP||itype[i]==RJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP) {
10464           if(branch_regs[i].regmap[hr]>=0) {
10465             score[hr]=0;earliest_available[hr]=i+2;
10466             loop_start[hr]=MAXBLOCK;
10467           }
10468         }
10469       }
10470       // No register allocations after unconditional jumps
10471       if(itype[i]==UJUMP||itype[i]==RJUMP||(source[i]>>16)==0x1000)
10472       {
10473         for(hr=0;hr<HOST_REGS;hr++) {
10474           score[hr]=0;earliest_available[hr]=i+2;
10475           loop_start[hr]=MAXBLOCK;
10476         }
10477         i++; // Skip delay slot too
10478         //printf("skip delay slot: %x\n",start+i*4);
10479       }
10480       else
10481       // Possible match
10482       if(itype[i]==LOAD||itype[i]==LOADLR||
10483          itype[i]==STORE||itype[i]==STORELR||itype[i]==C1LS) {
10484         for(hr=0;hr<HOST_REGS;hr++) {
10485           if(hr!=EXCLUDE_REG) {
10486             end[hr]=i-1;
10487             for(j=i;j<slen-1;j++) {
10488               if(regs[j].regmap[hr]>=0) break;
10489               if(itype[j]==UJUMP||itype[j]==RJUMP||itype[j]==CJUMP||itype[j]==SJUMP||itype[j]==FJUMP) {
10490                 if(branch_regs[j].regmap[hr]>=0) break;
10491                 if(ooo[j]) {
10492                   if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j+1]) break;
10493                 }else{
10494                   if(count_free_regs(branch_regs[j].regmap)<=minimum_free_regs[j+1]) break;
10495                 }
10496               }
10497               else if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j]) break;
10498               if(itype[j]==UJUMP||itype[j]==RJUMP||itype[j]==CJUMP||itype[j]==SJUMP||itype[j]==FJUMP) {
10499                 int t=(ba[j]-start)>>2;
10500                 if(t<j&&t>=earliest_available[hr]) {
10501                   if(t==1||(t>1&&itype[t-2]!=UJUMP&&itype[t-2]!=RJUMP)||(t>1&&rt1[t-2]!=31)) { // call/ret assumes no registers allocated
10502                     // Score a point for hoisting loop invariant
10503                     if(t<loop_start[hr]) loop_start[hr]=t;
10504                     //printf("set loop_start: i=%x j=%x (%x)\n",start+i*4,start+j*4,start+t*4);
10505                     score[hr]++;
10506                     end[hr]=j;
10507                   }
10508                 }
10509                 else if(t<j) {
10510                   if(regs[t].regmap[hr]==reg) {
10511                     // Score a point if the branch target matches this register
10512                     score[hr]++;
10513                     end[hr]=j;
10514                   }
10515                 }
10516                 if(itype[j+1]==LOAD||itype[j+1]==LOADLR||
10517                    itype[j+1]==STORE||itype[j+1]==STORELR||itype[j+1]==C1LS) {
10518                   score[hr]++;
10519                   end[hr]=j;
10520                 }
10521               }
10522               if(itype[j]==UJUMP||itype[j]==RJUMP||(source[j]>>16)==0x1000)
10523               {
10524                 // Stop on unconditional branch
10525                 break;
10526               }
10527               else
10528               if(itype[j]==LOAD||itype[j]==LOADLR||
10529                  itype[j]==STORE||itype[j]==STORELR||itype[j]==C1LS) {
10530                 score[hr]++;
10531                 end[hr]=j;
10532               }
10533             }
10534           }
10535         }
10536         // Find highest score and allocate that register
10537         int maxscore=0;
10538         for(hr=0;hr<HOST_REGS;hr++) {
10539           if(hr!=EXCLUDE_REG) {
10540             if(score[hr]>score[maxscore]) {
10541               maxscore=hr;
10542               //printf("highest score: %d %d (%x->%x)\n",score[hr],hr,start+i*4,start+end[hr]*4);
10543             }
10544           }
10545         }
10546         if(score[maxscore]>1)
10547         {
10548           if(i<loop_start[maxscore]) loop_start[maxscore]=i;
10549           for(j=loop_start[maxscore];j<slen&&j<=end[maxscore];j++) {
10550             //if(regs[j].regmap[maxscore]>=0) {printf("oops: %x %x was %d=%d\n",loop_start[maxscore]*4+start,j*4+start,maxscore,regs[j].regmap[maxscore]);}
10551             assert(regs[j].regmap[maxscore]<0);
10552             if(j>loop_start[maxscore]) regs[j].regmap_entry[maxscore]=reg;
10553             regs[j].regmap[maxscore]=reg;
10554             regs[j].dirty&=~(1<<maxscore);
10555             regs[j].wasconst&=~(1<<maxscore);
10556             regs[j].isconst&=~(1<<maxscore);
10557             if(itype[j]==UJUMP||itype[j]==RJUMP||itype[j]==CJUMP||itype[j]==SJUMP||itype[j]==FJUMP) {
10558               branch_regs[j].regmap[maxscore]=reg;
10559               branch_regs[j].wasdirty&=~(1<<maxscore);
10560               branch_regs[j].dirty&=~(1<<maxscore);
10561               branch_regs[j].wasconst&=~(1<<maxscore);
10562               branch_regs[j].isconst&=~(1<<maxscore);
10563               if(itype[j]!=RJUMP&&itype[j]!=UJUMP&&(source[j]>>16)!=0x1000) {
10564                 regmap_pre[j+2][maxscore]=reg;
10565                 regs[j+2].wasdirty&=~(1<<maxscore);
10566               }
10567               // loop optimization (loop_preload)
10568               int t=(ba[j]-start)>>2;
10569               if(t==loop_start[maxscore]) {
10570                 if(t==1||(t>1&&itype[t-2]!=UJUMP&&itype[t-2]!=RJUMP)||(t>1&&rt1[t-2]!=31)) // call/ret assumes no registers allocated
10571                   regs[t].regmap_entry[maxscore]=reg;
10572               }
10573             }
10574             else
10575             {
10576               if(j<1||(itype[j-1]!=RJUMP&&itype[j-1]!=UJUMP&&itype[j-1]!=CJUMP&&itype[j-1]!=SJUMP&&itype[j-1]!=FJUMP)) {
10577                 regmap_pre[j+1][maxscore]=reg;
10578                 regs[j+1].wasdirty&=~(1<<maxscore);
10579               }
10580             }
10581           }
10582           i=j-1;
10583           if(itype[j-1]==RJUMP||itype[j-1]==UJUMP||itype[j-1]==CJUMP||itype[j-1]==SJUMP||itype[j-1]==FJUMP) i++; // skip delay slot
10584           for(hr=0;hr<HOST_REGS;hr++) {
10585             score[hr]=0;earliest_available[hr]=i+i;
10586             loop_start[hr]=MAXBLOCK;
10587           }
10588         }
10589       }
10590     }
10591   }
10592   #endif
10593
10594   // This allocates registers (if possible) one instruction prior
10595   // to use, which can avoid a load-use penalty on certain CPUs.
10596   for(i=0;i<slen-1;i++)
10597   {
10598     if(!i||(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP))
10599     {
10600       if(!bt[i+1])
10601       {
10602         if(itype[i]==ALU||itype[i]==MOV||itype[i]==LOAD||itype[i]==SHIFTIMM||itype[i]==IMM16
10603            ||((itype[i]==COP1||itype[i]==COP2)&&opcode2[i]<3))
10604         {
10605           if(rs1[i+1]) {
10606             if((hr=get_reg(regs[i+1].regmap,rs1[i+1]))>=0)
10607             {
10608               if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10609               {
10610                 regs[i].regmap[hr]=regs[i+1].regmap[hr];
10611                 regmap_pre[i+1][hr]=regs[i+1].regmap[hr];
10612                 regs[i+1].regmap_entry[hr]=regs[i+1].regmap[hr];
10613                 regs[i].isconst&=~(1<<hr);
10614                 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10615                 constmap[i][hr]=constmap[i+1][hr];
10616                 regs[i+1].wasdirty&=~(1<<hr);
10617                 regs[i].dirty&=~(1<<hr);
10618               }
10619             }
10620           }
10621           if(rs2[i+1]) {
10622             if((hr=get_reg(regs[i+1].regmap,rs2[i+1]))>=0)
10623             {
10624               if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10625               {
10626                 regs[i].regmap[hr]=regs[i+1].regmap[hr];
10627                 regmap_pre[i+1][hr]=regs[i+1].regmap[hr];
10628                 regs[i+1].regmap_entry[hr]=regs[i+1].regmap[hr];
10629                 regs[i].isconst&=~(1<<hr);
10630                 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10631                 constmap[i][hr]=constmap[i+1][hr];
10632                 regs[i+1].wasdirty&=~(1<<hr);
10633                 regs[i].dirty&=~(1<<hr);
10634               }
10635             }
10636           }
10637           // Preload target address for load instruction (non-constant)
10638           if(itype[i+1]==LOAD&&rs1[i+1]&&get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10639             if((hr=get_reg(regs[i+1].regmap,rt1[i+1]))>=0)
10640             {
10641               if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10642               {
10643                 regs[i].regmap[hr]=rs1[i+1];
10644                 regmap_pre[i+1][hr]=rs1[i+1];
10645                 regs[i+1].regmap_entry[hr]=rs1[i+1];
10646                 regs[i].isconst&=~(1<<hr);
10647                 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10648                 constmap[i][hr]=constmap[i+1][hr];
10649                 regs[i+1].wasdirty&=~(1<<hr);
10650                 regs[i].dirty&=~(1<<hr);
10651               }
10652             }
10653           }
10654           // Load source into target register
10655           if(lt1[i+1]&&get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10656             if((hr=get_reg(regs[i+1].regmap,rt1[i+1]))>=0)
10657             {
10658               if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10659               {
10660                 regs[i].regmap[hr]=rs1[i+1];
10661                 regmap_pre[i+1][hr]=rs1[i+1];
10662                 regs[i+1].regmap_entry[hr]=rs1[i+1];
10663                 regs[i].isconst&=~(1<<hr);
10664                 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10665                 constmap[i][hr]=constmap[i+1][hr];
10666                 regs[i+1].wasdirty&=~(1<<hr);
10667                 regs[i].dirty&=~(1<<hr);
10668               }
10669             }
10670           }
10671           // Preload map address
10672           #ifndef HOST_IMM_ADDR32
10673           if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS||itype[i+1]==C2LS) {
10674             hr=get_reg(regs[i+1].regmap,TLREG);
10675             if(hr>=0) {
10676               int sr=get_reg(regs[i+1].regmap,rs1[i+1]);
10677               if(sr>=0&&((regs[i+1].wasconst>>sr)&1)) {
10678                 int nr;
10679                 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10680                 {
10681                   regs[i].regmap[hr]=MGEN1+((i+1)&1);
10682                   regmap_pre[i+1][hr]=MGEN1+((i+1)&1);
10683                   regs[i+1].regmap_entry[hr]=MGEN1+((i+1)&1);
10684                   regs[i].isconst&=~(1<<hr);
10685                   regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10686                   constmap[i][hr]=constmap[i+1][hr];
10687                   regs[i+1].wasdirty&=~(1<<hr);
10688                   regs[i].dirty&=~(1<<hr);
10689                 }
10690                 else if((nr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1))>=0)
10691                 {
10692                   // move it to another register
10693                   regs[i+1].regmap[hr]=-1;
10694                   regmap_pre[i+2][hr]=-1;
10695                   regs[i+1].regmap[nr]=TLREG;
10696                   regmap_pre[i+2][nr]=TLREG;
10697                   regs[i].regmap[nr]=MGEN1+((i+1)&1);
10698                   regmap_pre[i+1][nr]=MGEN1+((i+1)&1);
10699                   regs[i+1].regmap_entry[nr]=MGEN1+((i+1)&1);
10700                   regs[i].isconst&=~(1<<nr);
10701                   regs[i+1].isconst&=~(1<<nr);
10702                   regs[i].dirty&=~(1<<nr);
10703                   regs[i+1].wasdirty&=~(1<<nr);
10704                   regs[i+1].dirty&=~(1<<nr);
10705                   regs[i+2].wasdirty&=~(1<<nr);
10706                 }
10707               }
10708             }
10709           }
10710           #endif
10711           // Address for store instruction (non-constant)
10712           if(itype[i+1]==STORE||itype[i+1]==STORELR
10713              ||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a) { // SB/SH/SW/SD/SWC1/SDC1/SWC2/SDC2
10714             if(get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10715               hr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1);
10716               if(hr<0) hr=get_reg(regs[i+1].regmap,-1);
10717               else {regs[i+1].regmap[hr]=AGEN1+((i+1)&1);regs[i+1].isconst&=~(1<<hr);}
10718               assert(hr>=0);
10719               if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10720               {
10721                 regs[i].regmap[hr]=rs1[i+1];
10722                 regmap_pre[i+1][hr]=rs1[i+1];
10723                 regs[i+1].regmap_entry[hr]=rs1[i+1];
10724                 regs[i].isconst&=~(1<<hr);
10725                 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10726                 constmap[i][hr]=constmap[i+1][hr];
10727                 regs[i+1].wasdirty&=~(1<<hr);
10728                 regs[i].dirty&=~(1<<hr);
10729               }
10730             }
10731           }
10732           if(itype[i+1]==LOADLR||(opcode[i+1]&0x3b)==0x31||(opcode[i+1]&0x3b)==0x32) { // LWC1/LDC1, LWC2/LDC2
10733             if(get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10734               int nr;
10735               hr=get_reg(regs[i+1].regmap,FTEMP);
10736               assert(hr>=0);
10737               if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10738               {
10739                 regs[i].regmap[hr]=rs1[i+1];
10740                 regmap_pre[i+1][hr]=rs1[i+1];
10741                 regs[i+1].regmap_entry[hr]=rs1[i+1];
10742                 regs[i].isconst&=~(1<<hr);
10743                 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10744                 constmap[i][hr]=constmap[i+1][hr];
10745                 regs[i+1].wasdirty&=~(1<<hr);
10746                 regs[i].dirty&=~(1<<hr);
10747               }
10748               else if((nr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1))>=0)
10749               {
10750                 // move it to another register
10751                 regs[i+1].regmap[hr]=-1;
10752                 regmap_pre[i+2][hr]=-1;
10753                 regs[i+1].regmap[nr]=FTEMP;
10754                 regmap_pre[i+2][nr]=FTEMP;
10755                 regs[i].regmap[nr]=rs1[i+1];
10756                 regmap_pre[i+1][nr]=rs1[i+1];
10757                 regs[i+1].regmap_entry[nr]=rs1[i+1];
10758                 regs[i].isconst&=~(1<<nr);
10759                 regs[i+1].isconst&=~(1<<nr);
10760                 regs[i].dirty&=~(1<<nr);
10761                 regs[i+1].wasdirty&=~(1<<nr);
10762                 regs[i+1].dirty&=~(1<<nr);
10763                 regs[i+2].wasdirty&=~(1<<nr);
10764               }
10765             }
10766           }
10767           if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR/*||itype[i+1]==C1LS||||itype[i+1]==C2LS*/) {
10768             if(itype[i+1]==LOAD)
10769               hr=get_reg(regs[i+1].regmap,rt1[i+1]);
10770             if(itype[i+1]==LOADLR||(opcode[i+1]&0x3b)==0x31||(opcode[i+1]&0x3b)==0x32) // LWC1/LDC1, LWC2/LDC2
10771               hr=get_reg(regs[i+1].regmap,FTEMP);
10772             if(itype[i+1]==STORE||itype[i+1]==STORELR||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a) { // SWC1/SDC1/SWC2/SDC2
10773               hr=get_reg(regs[i+1].regmap,AGEN1+((i+1)&1));
10774               if(hr<0) hr=get_reg(regs[i+1].regmap,-1);
10775             }
10776             if(hr>=0&&regs[i].regmap[hr]<0) {
10777               int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
10778               if(rs>=0&&((regs[i+1].wasconst>>rs)&1)) {
10779                 regs[i].regmap[hr]=AGEN1+((i+1)&1);
10780                 regmap_pre[i+1][hr]=AGEN1+((i+1)&1);
10781                 regs[i+1].regmap_entry[hr]=AGEN1+((i+1)&1);
10782                 regs[i].isconst&=~(1<<hr);
10783                 regs[i+1].wasdirty&=~(1<<hr);
10784                 regs[i].dirty&=~(1<<hr);
10785               }
10786             }
10787           }
10788         }
10789       }
10790     }
10791   }
10792
10793   /* Pass 6 - Optimize clean/dirty state */
10794   clean_registers(0,slen-1,1);
10795
10796   /* Pass 7 - Identify 32-bit registers */
10797 #ifndef FORCE32
10798   provisional_r32();
10799
10800   u_int r32=0;
10801
10802   for (i=slen-1;i>=0;i--)
10803   {
10804     int hr;
10805     if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
10806     {
10807       if(ba[i]<start || ba[i]>=(start+slen*4))
10808       {
10809         // Branch out of this block, don't need anything
10810         r32=0;
10811       }
10812       else
10813       {
10814         // Internal branch
10815         // Need whatever matches the target
10816         // (and doesn't get overwritten by the delay slot instruction)
10817         r32=0;
10818         int t=(ba[i]-start)>>2;
10819         if(ba[i]>start+i*4) {
10820           // Forward branch
10821           if(!(requires_32bit[t]&~regs[i].was32))
10822             r32|=requires_32bit[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
10823         }else{
10824           // Backward branch
10825           //if(!(regs[t].was32&~unneeded_reg_upper[t]&~regs[i].was32))
10826           //  r32|=regs[t].was32&~unneeded_reg_upper[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
10827           if(!(pr32[t]&~regs[i].was32))
10828             r32|=pr32[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
10829         }
10830       }
10831       // Conditional branch may need registers for following instructions
10832       if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
10833       {
10834         if(i<slen-2) {
10835           r32|=requires_32bit[i+2];
10836           r32&=regs[i].was32;
10837           // Mark this address as a branch target since it may be called
10838           // upon return from interrupt
10839           bt[i+2]=1;
10840         }
10841       }
10842       // Merge in delay slot
10843       if(!likely[i]) {
10844         // These are overwritten unless the branch is "likely"
10845         // and the delay slot is nullified if not taken
10846         r32&=~(1LL<<rt1[i+1]);
10847         r32&=~(1LL<<rt2[i+1]);
10848       }
10849       // Assume these are needed (delay slot)
10850       if(us1[i+1]>0)
10851       {
10852         if((regs[i].was32>>us1[i+1])&1) r32|=1LL<<us1[i+1];
10853       }
10854       if(us2[i+1]>0)
10855       {
10856         if((regs[i].was32>>us2[i+1])&1) r32|=1LL<<us2[i+1];
10857       }
10858       if(dep1[i+1]&&!((unneeded_reg_upper[i]>>dep1[i+1])&1))
10859       {
10860         if((regs[i].was32>>dep1[i+1])&1) r32|=1LL<<dep1[i+1];
10861       }
10862       if(dep2[i+1]&&!((unneeded_reg_upper[i]>>dep2[i+1])&1))
10863       {
10864         if((regs[i].was32>>dep2[i+1])&1) r32|=1LL<<dep2[i+1];
10865       }
10866     }
10867     else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
10868     {
10869       // SYSCALL instruction (software interrupt)
10870       r32=0;
10871     }
10872     else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
10873     {
10874       // ERET instruction (return from interrupt)
10875       r32=0;
10876     }
10877     // Check 32 bits
10878     r32&=~(1LL<<rt1[i]);
10879     r32&=~(1LL<<rt2[i]);
10880     if(us1[i]>0)
10881     {
10882       if((regs[i].was32>>us1[i])&1) r32|=1LL<<us1[i];
10883     }
10884     if(us2[i]>0)
10885     {
10886       if((regs[i].was32>>us2[i])&1) r32|=1LL<<us2[i];
10887     }
10888     if(dep1[i]&&!((unneeded_reg_upper[i]>>dep1[i])&1))
10889     {
10890       if((regs[i].was32>>dep1[i])&1) r32|=1LL<<dep1[i];
10891     }
10892     if(dep2[i]&&!((unneeded_reg_upper[i]>>dep2[i])&1))
10893     {
10894       if((regs[i].was32>>dep2[i])&1) r32|=1LL<<dep2[i];
10895     }
10896     requires_32bit[i]=r32;
10897
10898     // Dirty registers which are 32-bit, require 32-bit input
10899     // as they will be written as 32-bit values
10900     for(hr=0;hr<HOST_REGS;hr++)
10901     {
10902       if(regs[i].regmap_entry[hr]>0&&regs[i].regmap_entry[hr]<64) {
10903         if((regs[i].was32>>regs[i].regmap_entry[hr])&(regs[i].wasdirty>>hr)&1) {
10904           if(!((unneeded_reg_upper[i]>>regs[i].regmap_entry[hr])&1))
10905           requires_32bit[i]|=1LL<<regs[i].regmap_entry[hr];
10906         }
10907       }
10908     }
10909     //requires_32bit[i]=is32[i]&~unneeded_reg_upper[i]; // DEBUG
10910   }
10911 #else
10912   for (i=slen-1;i>=0;i--)
10913   {
10914     if(itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
10915     {
10916       // Conditional branch
10917       if((source[i]>>16)!=0x1000&&i<slen-2) {
10918         // Mark this address as a branch target since it may be called
10919         // upon return from interrupt
10920         bt[i+2]=1;
10921       }
10922     }
10923   }
10924 #endif
10925
10926   if(itype[slen-1]==SPAN) {
10927     bt[slen-1]=1; // Mark as a branch target so instruction can restart after exception
10928   }
10929
10930 #ifdef DISASM
10931   /* Debug/disassembly */
10932   for(i=0;i<slen;i++)
10933   {
10934     printf("U:");
10935     int r;
10936     for(r=1;r<=CCREG;r++) {
10937       if((unneeded_reg[i]>>r)&1) {
10938         if(r==HIREG) printf(" HI");
10939         else if(r==LOREG) printf(" LO");
10940         else printf(" r%d",r);
10941       }
10942     }
10943 #ifndef FORCE32
10944     printf(" UU:");
10945     for(r=1;r<=CCREG;r++) {
10946       if(((unneeded_reg_upper[i]&~unneeded_reg[i])>>r)&1) {
10947         if(r==HIREG) printf(" HI");
10948         else if(r==LOREG) printf(" LO");
10949         else printf(" r%d",r);
10950       }
10951     }
10952     printf(" 32:");
10953     for(r=0;r<=CCREG;r++) {
10954       //if(((is32[i]>>r)&(~unneeded_reg[i]>>r))&1) {
10955       if((regs[i].was32>>r)&1) {
10956         if(r==CCREG) printf(" CC");
10957         else if(r==HIREG) printf(" HI");
10958         else if(r==LOREG) printf(" LO");
10959         else printf(" r%d",r);
10960       }
10961     }
10962 #endif
10963     printf("\n");
10964     #if defined(__i386__) || defined(__x86_64__)
10965     printf("pre: eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",regmap_pre[i][0],regmap_pre[i][1],regmap_pre[i][2],regmap_pre[i][3],regmap_pre[i][5],regmap_pre[i][6],regmap_pre[i][7]);
10966     #endif
10967     #ifdef __arm__
10968     printf("pre: r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d\n",regmap_pre[i][0],regmap_pre[i][1],regmap_pre[i][2],regmap_pre[i][3],regmap_pre[i][4],regmap_pre[i][5],regmap_pre[i][6],regmap_pre[i][7],regmap_pre[i][8],regmap_pre[i][9],regmap_pre[i][10],regmap_pre[i][12]);
10969     #endif
10970     printf("needs: ");
10971     if(needed_reg[i]&1) printf("eax ");
10972     if((needed_reg[i]>>1)&1) printf("ecx ");
10973     if((needed_reg[i]>>2)&1) printf("edx ");
10974     if((needed_reg[i]>>3)&1) printf("ebx ");
10975     if((needed_reg[i]>>5)&1) printf("ebp ");
10976     if((needed_reg[i]>>6)&1) printf("esi ");
10977     if((needed_reg[i]>>7)&1) printf("edi ");
10978     printf("r:");
10979     for(r=0;r<=CCREG;r++) {
10980       //if(((requires_32bit[i]>>r)&(~unneeded_reg[i]>>r))&1) {
10981       if((requires_32bit[i]>>r)&1) {
10982         if(r==CCREG) printf(" CC");
10983         else if(r==HIREG) printf(" HI");
10984         else if(r==LOREG) printf(" LO");
10985         else printf(" r%d",r);
10986       }
10987     }
10988     printf("\n");
10989     /*printf("pr:");
10990     for(r=0;r<=CCREG;r++) {
10991       //if(((requires_32bit[i]>>r)&(~unneeded_reg[i]>>r))&1) {
10992       if((pr32[i]>>r)&1) {
10993         if(r==CCREG) printf(" CC");
10994         else if(r==HIREG) printf(" HI");
10995         else if(r==LOREG) printf(" LO");
10996         else printf(" r%d",r);
10997       }
10998     }
10999     if(pr32[i]!=requires_32bit[i]) printf(" OOPS");
11000     printf("\n");*/
11001     #if defined(__i386__) || defined(__x86_64__)
11002     printf("entry: eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",regs[i].regmap_entry[0],regs[i].regmap_entry[1],regs[i].regmap_entry[2],regs[i].regmap_entry[3],regs[i].regmap_entry[5],regs[i].regmap_entry[6],regs[i].regmap_entry[7]);
11003     printf("dirty: ");
11004     if(regs[i].wasdirty&1) printf("eax ");
11005     if((regs[i].wasdirty>>1)&1) printf("ecx ");
11006     if((regs[i].wasdirty>>2)&1) printf("edx ");
11007     if((regs[i].wasdirty>>3)&1) printf("ebx ");
11008     if((regs[i].wasdirty>>5)&1) printf("ebp ");
11009     if((regs[i].wasdirty>>6)&1) printf("esi ");
11010     if((regs[i].wasdirty>>7)&1) printf("edi ");
11011     #endif
11012     #ifdef __arm__
11013     printf("entry: r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d\n",regs[i].regmap_entry[0],regs[i].regmap_entry[1],regs[i].regmap_entry[2],regs[i].regmap_entry[3],regs[i].regmap_entry[4],regs[i].regmap_entry[5],regs[i].regmap_entry[6],regs[i].regmap_entry[7],regs[i].regmap_entry[8],regs[i].regmap_entry[9],regs[i].regmap_entry[10],regs[i].regmap_entry[12]);
11014     printf("dirty: ");
11015     if(regs[i].wasdirty&1) printf("r0 ");
11016     if((regs[i].wasdirty>>1)&1) printf("r1 ");
11017     if((regs[i].wasdirty>>2)&1) printf("r2 ");
11018     if((regs[i].wasdirty>>3)&1) printf("r3 ");
11019     if((regs[i].wasdirty>>4)&1) printf("r4 ");
11020     if((regs[i].wasdirty>>5)&1) printf("r5 ");
11021     if((regs[i].wasdirty>>6)&1) printf("r6 ");
11022     if((regs[i].wasdirty>>7)&1) printf("r7 ");
11023     if((regs[i].wasdirty>>8)&1) printf("r8 ");
11024     if((regs[i].wasdirty>>9)&1) printf("r9 ");
11025     if((regs[i].wasdirty>>10)&1) printf("r10 ");
11026     if((regs[i].wasdirty>>12)&1) printf("r12 ");
11027     #endif
11028     printf("\n");
11029     disassemble_inst(i);
11030     //printf ("ccadj[%d] = %d\n",i,ccadj[i]);
11031     #if defined(__i386__) || defined(__x86_64__)
11032     printf("eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d dirty: ",regs[i].regmap[0],regs[i].regmap[1],regs[i].regmap[2],regs[i].regmap[3],regs[i].regmap[5],regs[i].regmap[6],regs[i].regmap[7]);
11033     if(regs[i].dirty&1) printf("eax ");
11034     if((regs[i].dirty>>1)&1) printf("ecx ");
11035     if((regs[i].dirty>>2)&1) printf("edx ");
11036     if((regs[i].dirty>>3)&1) printf("ebx ");
11037     if((regs[i].dirty>>5)&1) printf("ebp ");
11038     if((regs[i].dirty>>6)&1) printf("esi ");
11039     if((regs[i].dirty>>7)&1) printf("edi ");
11040     #endif
11041     #ifdef __arm__
11042     printf("r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d dirty: ",regs[i].regmap[0],regs[i].regmap[1],regs[i].regmap[2],regs[i].regmap[3],regs[i].regmap[4],regs[i].regmap[5],regs[i].regmap[6],regs[i].regmap[7],regs[i].regmap[8],regs[i].regmap[9],regs[i].regmap[10],regs[i].regmap[12]);
11043     if(regs[i].dirty&1) printf("r0 ");
11044     if((regs[i].dirty>>1)&1) printf("r1 ");
11045     if((regs[i].dirty>>2)&1) printf("r2 ");
11046     if((regs[i].dirty>>3)&1) printf("r3 ");
11047     if((regs[i].dirty>>4)&1) printf("r4 ");
11048     if((regs[i].dirty>>5)&1) printf("r5 ");
11049     if((regs[i].dirty>>6)&1) printf("r6 ");
11050     if((regs[i].dirty>>7)&1) printf("r7 ");
11051     if((regs[i].dirty>>8)&1) printf("r8 ");
11052     if((regs[i].dirty>>9)&1) printf("r9 ");
11053     if((regs[i].dirty>>10)&1) printf("r10 ");
11054     if((regs[i].dirty>>12)&1) printf("r12 ");
11055     #endif
11056     printf("\n");
11057     if(regs[i].isconst) {
11058       printf("constants: ");
11059       #if defined(__i386__) || defined(__x86_64__)
11060       if(regs[i].isconst&1) printf("eax=%x ",(int)constmap[i][0]);
11061       if((regs[i].isconst>>1)&1) printf("ecx=%x ",(int)constmap[i][1]);
11062       if((regs[i].isconst>>2)&1) printf("edx=%x ",(int)constmap[i][2]);
11063       if((regs[i].isconst>>3)&1) printf("ebx=%x ",(int)constmap[i][3]);
11064       if((regs[i].isconst>>5)&1) printf("ebp=%x ",(int)constmap[i][5]);
11065       if((regs[i].isconst>>6)&1) printf("esi=%x ",(int)constmap[i][6]);
11066       if((regs[i].isconst>>7)&1) printf("edi=%x ",(int)constmap[i][7]);
11067       #endif
11068       #ifdef __arm__
11069       if(regs[i].isconst&1) printf("r0=%x ",(int)constmap[i][0]);
11070       if((regs[i].isconst>>1)&1) printf("r1=%x ",(int)constmap[i][1]);
11071       if((regs[i].isconst>>2)&1) printf("r2=%x ",(int)constmap[i][2]);
11072       if((regs[i].isconst>>3)&1) printf("r3=%x ",(int)constmap[i][3]);
11073       if((regs[i].isconst>>4)&1) printf("r4=%x ",(int)constmap[i][4]);
11074       if((regs[i].isconst>>5)&1) printf("r5=%x ",(int)constmap[i][5]);
11075       if((regs[i].isconst>>6)&1) printf("r6=%x ",(int)constmap[i][6]);
11076       if((regs[i].isconst>>7)&1) printf("r7=%x ",(int)constmap[i][7]);
11077       if((regs[i].isconst>>8)&1) printf("r8=%x ",(int)constmap[i][8]);
11078       if((regs[i].isconst>>9)&1) printf("r9=%x ",(int)constmap[i][9]);
11079       if((regs[i].isconst>>10)&1) printf("r10=%x ",(int)constmap[i][10]);
11080       if((regs[i].isconst>>12)&1) printf("r12=%x ",(int)constmap[i][12]);
11081       #endif
11082       printf("\n");
11083     }
11084 #ifndef FORCE32
11085     printf(" 32:");
11086     for(r=0;r<=CCREG;r++) {
11087       if((regs[i].is32>>r)&1) {
11088         if(r==CCREG) printf(" CC");
11089         else if(r==HIREG) printf(" HI");
11090         else if(r==LOREG) printf(" LO");
11091         else printf(" r%d",r);
11092       }
11093     }
11094     printf("\n");
11095 #endif
11096     /*printf(" p32:");
11097     for(r=0;r<=CCREG;r++) {
11098       if((p32[i]>>r)&1) {
11099         if(r==CCREG) printf(" CC");
11100         else if(r==HIREG) printf(" HI");
11101         else if(r==LOREG) printf(" LO");
11102         else printf(" r%d",r);
11103       }
11104     }
11105     if(p32[i]!=regs[i].is32) printf(" NO MATCH\n");
11106     else printf("\n");*/
11107     if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP) {
11108       #if defined(__i386__) || defined(__x86_64__)
11109       printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d dirty: ",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
11110       if(branch_regs[i].dirty&1) printf("eax ");
11111       if((branch_regs[i].dirty>>1)&1) printf("ecx ");
11112       if((branch_regs[i].dirty>>2)&1) printf("edx ");
11113       if((branch_regs[i].dirty>>3)&1) printf("ebx ");
11114       if((branch_regs[i].dirty>>5)&1) printf("ebp ");
11115       if((branch_regs[i].dirty>>6)&1) printf("esi ");
11116       if((branch_regs[i].dirty>>7)&1) printf("edi ");
11117       #endif
11118       #ifdef __arm__
11119       printf("branch(%d): r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d dirty: ",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[4],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7],branch_regs[i].regmap[8],branch_regs[i].regmap[9],branch_regs[i].regmap[10],branch_regs[i].regmap[12]);
11120       if(branch_regs[i].dirty&1) printf("r0 ");
11121       if((branch_regs[i].dirty>>1)&1) printf("r1 ");
11122       if((branch_regs[i].dirty>>2)&1) printf("r2 ");
11123       if((branch_regs[i].dirty>>3)&1) printf("r3 ");
11124       if((branch_regs[i].dirty>>4)&1) printf("r4 ");
11125       if((branch_regs[i].dirty>>5)&1) printf("r5 ");
11126       if((branch_regs[i].dirty>>6)&1) printf("r6 ");
11127       if((branch_regs[i].dirty>>7)&1) printf("r7 ");
11128       if((branch_regs[i].dirty>>8)&1) printf("r8 ");
11129       if((branch_regs[i].dirty>>9)&1) printf("r9 ");
11130       if((branch_regs[i].dirty>>10)&1) printf("r10 ");
11131       if((branch_regs[i].dirty>>12)&1) printf("r12 ");
11132       #endif
11133 #ifndef FORCE32
11134       printf(" 32:");
11135       for(r=0;r<=CCREG;r++) {
11136         if((branch_regs[i].is32>>r)&1) {
11137           if(r==CCREG) printf(" CC");
11138           else if(r==HIREG) printf(" HI");
11139           else if(r==LOREG) printf(" LO");
11140           else printf(" r%d",r);
11141         }
11142       }
11143       printf("\n");
11144 #endif
11145     }
11146   }
11147 #endif // DISASM
11148
11149   /* Pass 8 - Assembly */
11150   linkcount=0;stubcount=0;
11151   ds=0;is_delayslot=0;
11152   cop1_usable=0;
11153   uint64_t is32_pre=0;
11154   u_int dirty_pre=0;
11155   u_int beginning=(u_int)out;
11156   if((u_int)addr&1) {
11157     ds=1;
11158     pagespan_ds();
11159   }
11160   u_int instr_addr0_override=0;
11161
11162 #ifdef PCSX
11163   if (start == 0x80030000) {
11164     // nasty hack for fastbios thing
11165     // override block entry to this code
11166     instr_addr0_override=(u_int)out;
11167     emit_movimm(start,0);
11168     // abuse io address var as a flag that we
11169     // have already returned here once
11170     emit_readword((int)&address,1);
11171     emit_writeword(0,(int)&pcaddr);
11172     emit_writeword(0,(int)&address);
11173     emit_cmp(0,1);
11174     emit_jne((int)new_dyna_leave);
11175   }
11176 #endif
11177   for(i=0;i<slen;i++)
11178   {
11179     //if(ds) printf("ds: ");
11180     disassemble_inst(i);
11181     if(ds) {
11182       ds=0; // Skip delay slot
11183       if(bt[i]) assem_debug("OOPS - branch into delay slot\n");
11184       instr_addr[i]=0;
11185     } else {
11186       speculate_register_values(i);
11187       #ifndef DESTRUCTIVE_WRITEBACK
11188       if(i<2||(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000))
11189       {
11190         wb_sx(regmap_pre[i],regs[i].regmap_entry,regs[i].wasdirty,is32_pre,regs[i].was32,
11191               unneeded_reg[i],unneeded_reg_upper[i]);
11192         wb_valid(regmap_pre[i],regs[i].regmap_entry,dirty_pre,regs[i].wasdirty,is32_pre,
11193               unneeded_reg[i],unneeded_reg_upper[i]);
11194       }
11195       if((itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)&&!likely[i]) {
11196         is32_pre=branch_regs[i].is32;
11197         dirty_pre=branch_regs[i].dirty;
11198       }else{
11199         is32_pre=regs[i].is32;
11200         dirty_pre=regs[i].dirty;
11201       }
11202       #endif
11203       // write back
11204       if(i<2||(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000))
11205       {
11206         wb_invalidate(regmap_pre[i],regs[i].regmap_entry,regs[i].wasdirty,regs[i].was32,
11207                       unneeded_reg[i],unneeded_reg_upper[i]);
11208         loop_preload(regmap_pre[i],regs[i].regmap_entry);
11209       }
11210       // branch target entry point
11211       instr_addr[i]=(u_int)out;
11212       assem_debug("<->\n");
11213       // load regs
11214       if(regs[i].regmap_entry[HOST_CCREG]==CCREG&&regs[i].regmap[HOST_CCREG]!=CCREG)
11215         wb_register(CCREG,regs[i].regmap_entry,regs[i].wasdirty,regs[i].was32);
11216       load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs1[i],rs2[i]);
11217       address_generation(i,&regs[i],regs[i].regmap_entry);
11218       load_consts(regmap_pre[i],regs[i].regmap,regs[i].was32,i);
11219       if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
11220       {
11221         // Load the delay slot registers if necessary
11222         if(rs1[i+1]!=rs1[i]&&rs1[i+1]!=rs2[i]&&(rs1[i+1]!=rt1[i]||rt1[i]==0))
11223           load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs1[i+1],rs1[i+1]);
11224         if(rs2[i+1]!=rs1[i+1]&&rs2[i+1]!=rs1[i]&&rs2[i+1]!=rs2[i]&&(rs2[i+1]!=rt1[i]||rt1[i]==0))
11225           load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs2[i+1],rs2[i+1]);
11226         if(itype[i+1]==STORE||itype[i+1]==STORELR||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a)
11227           load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,INVCP,INVCP);
11228       }
11229       else if(i+1<slen)
11230       {
11231         // Preload registers for following instruction
11232         if(rs1[i+1]!=rs1[i]&&rs1[i+1]!=rs2[i])
11233           if(rs1[i+1]!=rt1[i]&&rs1[i+1]!=rt2[i])
11234             load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs1[i+1],rs1[i+1]);
11235         if(rs2[i+1]!=rs1[i+1]&&rs2[i+1]!=rs1[i]&&rs2[i+1]!=rs2[i])
11236           if(rs2[i+1]!=rt1[i]&&rs2[i+1]!=rt2[i])
11237             load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs2[i+1],rs2[i+1]);
11238       }
11239       // TODO: if(is_ooo(i)) address_generation(i+1);
11240       if(itype[i]==CJUMP||itype[i]==FJUMP)
11241         load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,CCREG,CCREG);
11242       if(itype[i]==STORE||itype[i]==STORELR||(opcode[i]&0x3b)==0x39||(opcode[i]&0x3b)==0x3a)
11243         load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,INVCP,INVCP);
11244       if(bt[i]) cop1_usable=0;
11245       // assemble
11246       switch(itype[i]) {
11247         case ALU:
11248           alu_assemble(i,&regs[i]);break;
11249         case IMM16:
11250           imm16_assemble(i,&regs[i]);break;
11251         case SHIFT:
11252           shift_assemble(i,&regs[i]);break;
11253         case SHIFTIMM:
11254           shiftimm_assemble(i,&regs[i]);break;
11255         case LOAD:
11256           load_assemble(i,&regs[i]);break;
11257         case LOADLR:
11258           loadlr_assemble(i,&regs[i]);break;
11259         case STORE:
11260           store_assemble(i,&regs[i]);break;
11261         case STORELR:
11262           storelr_assemble(i,&regs[i]);break;
11263         case COP0:
11264           cop0_assemble(i,&regs[i]);break;
11265         case COP1:
11266           cop1_assemble(i,&regs[i]);break;
11267         case C1LS:
11268           c1ls_assemble(i,&regs[i]);break;
11269         case COP2:
11270           cop2_assemble(i,&regs[i]);break;
11271         case C2LS:
11272           c2ls_assemble(i,&regs[i]);break;
11273         case C2OP:
11274           c2op_assemble(i,&regs[i]);break;
11275         case FCONV:
11276           fconv_assemble(i,&regs[i]);break;
11277         case FLOAT:
11278           float_assemble(i,&regs[i]);break;
11279         case FCOMP:
11280           fcomp_assemble(i,&regs[i]);break;
11281         case MULTDIV:
11282           multdiv_assemble(i,&regs[i]);break;
11283         case MOV:
11284           mov_assemble(i,&regs[i]);break;
11285         case SYSCALL:
11286           syscall_assemble(i,&regs[i]);break;
11287         case HLECALL:
11288           hlecall_assemble(i,&regs[i]);break;
11289         case INTCALL:
11290           intcall_assemble(i,&regs[i]);break;
11291         case UJUMP:
11292           ujump_assemble(i,&regs[i]);ds=1;break;
11293         case RJUMP:
11294           rjump_assemble(i,&regs[i]);ds=1;break;
11295         case CJUMP:
11296           cjump_assemble(i,&regs[i]);ds=1;break;
11297         case SJUMP:
11298           sjump_assemble(i,&regs[i]);ds=1;break;
11299         case FJUMP:
11300           fjump_assemble(i,&regs[i]);ds=1;break;
11301         case SPAN:
11302           pagespan_assemble(i,&regs[i]);break;
11303       }
11304       if(itype[i]==UJUMP||itype[i]==RJUMP||(source[i]>>16)==0x1000)
11305         literal_pool(1024);
11306       else
11307         literal_pool_jumpover(256);
11308     }
11309   }
11310   //assert(itype[i-2]==UJUMP||itype[i-2]==RJUMP||(source[i-2]>>16)==0x1000);
11311   // If the block did not end with an unconditional branch,
11312   // add a jump to the next instruction.
11313   if(i>1) {
11314     if(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000&&itype[i-1]!=SPAN) {
11315       assert(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP);
11316       assert(i==slen);
11317       if(itype[i-2]!=CJUMP&&itype[i-2]!=SJUMP&&itype[i-2]!=FJUMP) {
11318         store_regs_bt(regs[i-1].regmap,regs[i-1].is32,regs[i-1].dirty,start+i*4);
11319         if(regs[i-1].regmap[HOST_CCREG]!=CCREG)
11320           emit_loadreg(CCREG,HOST_CCREG);
11321         emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i-1]+1),HOST_CCREG);
11322       }
11323       else if(!likely[i-2])
11324       {
11325         store_regs_bt(branch_regs[i-2].regmap,branch_regs[i-2].is32,branch_regs[i-2].dirty,start+i*4);
11326         assert(branch_regs[i-2].regmap[HOST_CCREG]==CCREG);
11327       }
11328       else
11329       {
11330         store_regs_bt(regs[i-2].regmap,regs[i-2].is32,regs[i-2].dirty,start+i*4);
11331         assert(regs[i-2].regmap[HOST_CCREG]==CCREG);
11332       }
11333       add_to_linker((int)out,start+i*4,0);
11334       emit_jmp(0);
11335     }
11336   }
11337   else
11338   {
11339     assert(i>0);
11340     assert(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP);
11341     store_regs_bt(regs[i-1].regmap,regs[i-1].is32,regs[i-1].dirty,start+i*4);
11342     if(regs[i-1].regmap[HOST_CCREG]!=CCREG)
11343       emit_loadreg(CCREG,HOST_CCREG);
11344     emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i-1]+1),HOST_CCREG);
11345     add_to_linker((int)out,start+i*4,0);
11346     emit_jmp(0);
11347   }
11348
11349   // TODO: delay slot stubs?
11350   // Stubs
11351   for(i=0;i<stubcount;i++)
11352   {
11353     switch(stubs[i][0])
11354     {
11355       case LOADB_STUB:
11356       case LOADH_STUB:
11357       case LOADW_STUB:
11358       case LOADD_STUB:
11359       case LOADBU_STUB:
11360       case LOADHU_STUB:
11361         do_readstub(i);break;
11362       case STOREB_STUB:
11363       case STOREH_STUB:
11364       case STOREW_STUB:
11365       case STORED_STUB:
11366         do_writestub(i);break;
11367       case CC_STUB:
11368         do_ccstub(i);break;
11369       case INVCODE_STUB:
11370         do_invstub(i);break;
11371       case FP_STUB:
11372         do_cop1stub(i);break;
11373       case STORELR_STUB:
11374         do_unalignedwritestub(i);break;
11375     }
11376   }
11377
11378   if (instr_addr0_override)
11379     instr_addr[0] = instr_addr0_override;
11380
11381   /* Pass 9 - Linker */
11382   for(i=0;i<linkcount;i++)
11383   {
11384     assem_debug("%8x -> %8x\n",link_addr[i][0],link_addr[i][1]);
11385     literal_pool(64);
11386     if(!link_addr[i][2])
11387     {
11388       void *stub=out;
11389       void *addr=check_addr(link_addr[i][1]);
11390       emit_extjump(link_addr[i][0],link_addr[i][1]);
11391       if(addr) {
11392         set_jump_target(link_addr[i][0],(int)addr);
11393         add_link(link_addr[i][1],stub);
11394       }
11395       else set_jump_target(link_addr[i][0],(int)stub);
11396     }
11397     else
11398     {
11399       // Internal branch
11400       int target=(link_addr[i][1]-start)>>2;
11401       assert(target>=0&&target<slen);
11402       assert(instr_addr[target]);
11403       //#ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
11404       //set_jump_target_fillslot(link_addr[i][0],instr_addr[target],link_addr[i][2]>>1);
11405       //#else
11406       set_jump_target(link_addr[i][0],instr_addr[target]);
11407       //#endif
11408     }
11409   }
11410   // External Branch Targets (jump_in)
11411   if(copy+slen*4>(void *)shadow+sizeof(shadow)) copy=shadow;
11412   for(i=0;i<slen;i++)
11413   {
11414     if(bt[i]||i==0)
11415     {
11416       if(instr_addr[i]) // TODO - delay slots (=null)
11417       {
11418         u_int vaddr=start+i*4;
11419         u_int page=get_page(vaddr);
11420         u_int vpage=get_vpage(vaddr);
11421         literal_pool(256);
11422         //if(!(is32[i]&(~unneeded_reg_upper[i])&~(1LL<<CCREG)))
11423 #ifndef FORCE32
11424         if(!requires_32bit[i])
11425 #else
11426         if(1)
11427 #endif
11428         {
11429           assem_debug("%8x (%d) <- %8x\n",instr_addr[i],i,start+i*4);
11430           assem_debug("jump_in: %x\n",start+i*4);
11431           ll_add(jump_dirty+vpage,vaddr,(void *)out);
11432           int entry_point=do_dirty_stub(i);
11433           ll_add(jump_in+page,vaddr,(void *)entry_point);
11434           // If there was an existing entry in the hash table,
11435           // replace it with the new address.
11436           // Don't add new entries.  We'll insert the
11437           // ones that actually get used in check_addr().
11438           int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
11439           if(ht_bin[0]==vaddr) {
11440             ht_bin[1]=entry_point;
11441           }
11442           if(ht_bin[2]==vaddr) {
11443             ht_bin[3]=entry_point;
11444           }
11445         }
11446         else
11447         {
11448           u_int r=requires_32bit[i]|!!(requires_32bit[i]>>32);
11449           assem_debug("%8x (%d) <- %8x\n",instr_addr[i],i,start+i*4);
11450           assem_debug("jump_in: %x (restricted - %x)\n",start+i*4,r);
11451           //int entry_point=(int)out;
11452           ////assem_debug("entry_point: %x\n",entry_point);
11453           //load_regs_entry(i);
11454           //if(entry_point==(int)out)
11455           //  entry_point=instr_addr[i];
11456           //else
11457           //  emit_jmp(instr_addr[i]);
11458           //ll_add_32(jump_in+page,vaddr,r,(void *)entry_point);
11459           ll_add_32(jump_dirty+vpage,vaddr,r,(void *)out);
11460           int entry_point=do_dirty_stub(i);
11461           ll_add_32(jump_in+page,vaddr,r,(void *)entry_point);
11462         }
11463       }
11464     }
11465   }
11466   // Write out the literal pool if necessary
11467   literal_pool(0);
11468   #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
11469   // Align code
11470   if(((u_int)out)&7) emit_addnop(13);
11471   #endif
11472   assert((u_int)out-beginning<MAX_OUTPUT_BLOCK_SIZE);
11473   //printf("shadow buffer: %x-%x\n",(int)copy,(int)copy+slen*4);
11474   memcpy(copy,source,slen*4);
11475   copy+=slen*4;
11476
11477   #ifdef __arm__
11478   __clear_cache((void *)beginning,out);
11479   #endif
11480
11481   // If we're within 256K of the end of the buffer,
11482   // start over from the beginning. (Is 256K enough?)
11483   if((int)out>BASE_ADDR+(1<<TARGET_SIZE_2)-MAX_OUTPUT_BLOCK_SIZE) out=(u_char *)BASE_ADDR;
11484
11485   // Trap writes to any of the pages we compiled
11486   for(i=start>>12;i<=(start+slen*4)>>12;i++) {
11487     invalid_code[i]=0;
11488 #ifndef DISABLE_TLB
11489     memory_map[i]|=0x40000000;
11490     if((signed int)start>=(signed int)0xC0000000) {
11491       assert(using_tlb);
11492       j=(((u_int)i<<12)+(memory_map[i]<<2)-(u_int)rdram+(u_int)0x80000000)>>12;
11493       invalid_code[j]=0;
11494       memory_map[j]|=0x40000000;
11495       //printf("write protect physical page: %x (virtual %x)\n",j<<12,start);
11496     }
11497 #endif
11498   }
11499   inv_code_start=inv_code_end=~0;
11500 #ifdef PCSX
11501   // for PCSX we need to mark all mirrors too
11502   if(get_page(start)<(RAM_SIZE>>12))
11503     for(i=start>>12;i<=(start+slen*4)>>12;i++)
11504       invalid_code[((u_int)0x00000000>>12)|(i&0x1ff)]=
11505       invalid_code[((u_int)0x80000000>>12)|(i&0x1ff)]=
11506       invalid_code[((u_int)0xa0000000>>12)|(i&0x1ff)]=0;
11507 #endif
11508
11509   /* Pass 10 - Free memory by expiring oldest blocks */
11510
11511   int end=((((int)out-BASE_ADDR)>>(TARGET_SIZE_2-16))+16384)&65535;
11512   while(expirep!=end)
11513   {
11514     int shift=TARGET_SIZE_2-3; // Divide into 8 blocks
11515     int base=BASE_ADDR+((expirep>>13)<<shift); // Base address of this block
11516     inv_debug("EXP: Phase %d\n",expirep);
11517     switch((expirep>>11)&3)
11518     {
11519       case 0:
11520         // Clear jump_in and jump_dirty
11521         ll_remove_matching_addrs(jump_in+(expirep&2047),base,shift);
11522         ll_remove_matching_addrs(jump_dirty+(expirep&2047),base,shift);
11523         ll_remove_matching_addrs(jump_in+2048+(expirep&2047),base,shift);
11524         ll_remove_matching_addrs(jump_dirty+2048+(expirep&2047),base,shift);
11525         break;
11526       case 1:
11527         // Clear pointers
11528         ll_kill_pointers(jump_out[expirep&2047],base,shift);
11529         ll_kill_pointers(jump_out[(expirep&2047)+2048],base,shift);
11530         break;
11531       case 2:
11532         // Clear hash table
11533         for(i=0;i<32;i++) {
11534           int *ht_bin=hash_table[((expirep&2047)<<5)+i];
11535           if((ht_bin[3]>>shift)==(base>>shift) ||
11536              ((ht_bin[3]-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(base>>shift)) {
11537             inv_debug("EXP: Remove hash %x -> %x\n",ht_bin[2],ht_bin[3]);
11538             ht_bin[2]=ht_bin[3]=-1;
11539           }
11540           if((ht_bin[1]>>shift)==(base>>shift) ||
11541              ((ht_bin[1]-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(base>>shift)) {
11542             inv_debug("EXP: Remove hash %x -> %x\n",ht_bin[0],ht_bin[1]);
11543             ht_bin[0]=ht_bin[2];
11544             ht_bin[1]=ht_bin[3];
11545             ht_bin[2]=ht_bin[3]=-1;
11546           }
11547         }
11548         break;
11549       case 3:
11550         // Clear jump_out
11551         #ifdef __arm__
11552         if((expirep&2047)==0)
11553           do_clear_cache();
11554         #endif
11555         ll_remove_matching_addrs(jump_out+(expirep&2047),base,shift);
11556         ll_remove_matching_addrs(jump_out+2048+(expirep&2047),base,shift);
11557         break;
11558     }
11559     expirep=(expirep+1)&65535;
11560   }
11561   return 0;
11562 }
11563
11564 // vim:shiftwidth=2:expandtab