1 /* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
2 * Mupen64plus - new_dynarec.c *
3 * Copyright (C) 2009-2010 Ari64 *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. *
19 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
22 #include <stdint.h> //include for uint64_t
25 #include "emu_if.h" //emulator interface
30 #include "assem_x86.h"
33 #include "assem_x64.h"
36 #include "assem_arm.h"
40 #define MAX_OUTPUT_BLOCK_SIZE 262144
41 #define CLOCK_DIVIDER 2
45 signed char regmap_entry[HOST_REGS];
46 signed char regmap[HOST_REGS];
55 uint64_t constmap[HOST_REGS];
63 struct ll_entry *next;
69 char insn[MAXBLOCK][10];
70 u_char itype[MAXBLOCK];
71 u_char opcode[MAXBLOCK];
72 u_char opcode2[MAXBLOCK];
80 u_char dep1[MAXBLOCK];
81 u_char dep2[MAXBLOCK];
85 char likely[MAXBLOCK];
87 uint64_t unneeded_reg[MAXBLOCK];
88 uint64_t unneeded_reg_upper[MAXBLOCK];
89 uint64_t branch_unneeded_reg[MAXBLOCK];
90 uint64_t branch_unneeded_reg_upper[MAXBLOCK];
91 uint64_t p32[MAXBLOCK];
92 uint64_t pr32[MAXBLOCK];
93 signed char regmap_pre[MAXBLOCK][HOST_REGS];
94 signed char regmap[MAXBLOCK][HOST_REGS];
95 signed char regmap_entry[MAXBLOCK][HOST_REGS];
96 uint64_t constmap[MAXBLOCK][HOST_REGS];
97 uint64_t known_value[HOST_REGS];
99 struct regstat regs[MAXBLOCK];
100 struct regstat branch_regs[MAXBLOCK];
101 u_int needed_reg[MAXBLOCK];
102 uint64_t requires_32bit[MAXBLOCK];
103 u_int wont_dirty[MAXBLOCK];
104 u_int will_dirty[MAXBLOCK];
107 u_int instr_addr[MAXBLOCK];
108 u_int link_addr[MAXBLOCK][3];
110 u_int stubs[MAXBLOCK*3][8];
112 u_int literals[1024][2];
117 struct ll_entry *jump_in[4096];
118 struct ll_entry *jump_out[4096];
119 struct ll_entry *jump_dirty[4096];
120 u_int hash_table[65536][4] __attribute__((aligned(16)));
121 char shadow[1048576] __attribute__((aligned(16)));
125 u_int stop_after_jal;
126 extern u_char restore_candidate[512];
127 extern int cycle_count;
129 /* registers that may be allocated */
131 #define HIREG 32 // hi
132 #define LOREG 33 // lo
133 #define FSREG 34 // FPU status (FCSR)
134 #define CSREG 35 // Coprocessor status
135 #define CCREG 36 // Cycle count
136 #define INVCP 37 // Pointer to invalid_code
138 #define FTEMP 38 // FPU temporary register
139 #define PTEMP 39 // Prefetch temporary register
140 #define TLREG 40 // TLB mapping offset
141 #define RHASH 41 // Return address hash
142 #define RHTBL 42 // Return address hash table address
143 #define RTEMP 43 // JR/JALR address register
145 #define AGEN1 44 // Address generation temporary register
146 #define AGEN2 45 // Address generation temporary register
147 #define MGEN1 46 // Maptable address generation temporary register
148 #define MGEN2 47 // Maptable address generation temporary register
149 #define BTREG 48 // Branch target temporary register
151 /* instruction types */
152 #define NOP 0 // No operation
153 #define LOAD 1 // Load
154 #define STORE 2 // Store
155 #define LOADLR 3 // Unaligned load
156 #define STORELR 4 // Unaligned store
157 #define MOV 5 // Move
158 #define ALU 6 // Arithmetic/logic
159 #define MULTDIV 7 // Multiply/divide
160 #define SHIFT 8 // Shift by register
161 #define SHIFTIMM 9// Shift by immediate
162 #define IMM16 10 // 16-bit immediate
163 #define RJUMP 11 // Unconditional jump to register
164 #define UJUMP 12 // Unconditional jump
165 #define CJUMP 13 // Conditional branch (BEQ/BNE/BGTZ/BLEZ)
166 #define SJUMP 14 // Conditional branch (regimm format)
167 #define COP0 15 // Coprocessor 0
168 #define COP1 16 // Coprocessor 1
169 #define C1LS 17 // Coprocessor 1 load/store
170 #define FJUMP 18 // Conditional branch (floating point)
171 #define FLOAT 19 // Floating point unit
172 #define FCONV 20 // Convert integer to float
173 #define FCOMP 21 // Floating point compare (sets FSREG)
174 #define SYSCALL 22// SYSCALL
175 #define OTHER 23 // Other
176 #define SPAN 24 // Branch/delay slot spans 2 pages
177 #define NI 25 // Not implemented
186 #define LOADBU_STUB 7
187 #define LOADHU_STUB 8
188 #define STOREB_STUB 9
189 #define STOREH_STUB 10
190 #define STOREW_STUB 11
191 #define STORED_STUB 12
192 #define STORELR_STUB 13
193 #define INVCODE_STUB 14
201 int new_recompile_block(int addr);
202 void *get_addr_ht(u_int vaddr);
203 void invalidate_block(u_int block);
204 void invalidate_addr(u_int addr);
205 void remove_hash(int vaddr);
208 void dyna_linker_ds();
210 void verify_code_vm();
211 void verify_code_ds();
214 void fp_exception_ds();
221 void read_nomem_new();
222 void read_nomemb_new();
223 void read_nomemh_new();
224 void read_nomemd_new();
225 void write_nomem_new();
226 void write_nomemb_new();
227 void write_nomemh_new();
228 void write_nomemd_new();
229 void write_rdram_new();
230 void write_rdramb_new();
231 void write_rdramh_new();
232 void write_rdramd_new();
233 extern u_int memory_map[1048576];
235 // Needed by assembler
236 void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32);
237 void wb_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty);
238 void wb_needed_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr);
239 void load_all_regs(signed char i_regmap[]);
240 void load_needed_regs(signed char i_regmap[],signed char next_regmap[]);
241 void load_regs_entry(int t);
242 void load_all_consts(signed char regmap[],int is32,u_int dirty,int i);
246 //#define DEBUG_CYCLE_COUNT 1
249 //#define assem_debug printf
250 //#define inv_debug printf
251 #define assem_debug nullf
252 #define inv_debug nullf
254 static void tlb_hacks()
258 if (strncmp((char *) ROM_HEADER->nom, "GOLDENEYE",9) == 0)
262 switch (ROM_HEADER->Country_code&0xFF)
274 // Unknown country code
278 u_int rom_addr=(u_int)rom;
280 // Since memory_map is 32-bit, on 64-bit systems the rom needs to be
281 // in the lower 4G of memory to use this hack. Copy it if necessary.
282 if((void *)rom>(void *)0xffffffff) {
283 munmap(ROM_COPY, 67108864);
284 if(mmap(ROM_COPY, 12582912,
285 PROT_READ | PROT_WRITE,
286 MAP_FIXED | MAP_PRIVATE | MAP_ANONYMOUS,
287 -1, 0) <= 0) {printf("mmap() failed\n");}
288 memcpy(ROM_COPY,rom,12582912);
289 rom_addr=(u_int)ROM_COPY;
293 for(n=0x7F000;n<0x80000;n++) {
294 memory_map[n]=(((u_int)(rom_addr+addr-0x7F000000))>>2)|0x40000000;
301 static u_int get_page(u_int vaddr)
303 u_int page=(vaddr^0x80000000)>>12;
305 if(page>262143&&tlb_LUT_r[vaddr>>12]) page=(tlb_LUT_r[vaddr>>12]^0x80000000)>>12;
307 if(page>2048) page=2048+(page&2047);
311 static u_int get_vpage(u_int vaddr)
313 u_int vpage=(vaddr^0x80000000)>>12;
315 if(vpage>262143&&tlb_LUT_r[vaddr>>12]) vpage&=2047; // jump_dirty uses a hash of the virtual address instead
317 if(vpage>2048) vpage=2048+(vpage&2047);
321 // Get address from virtual address
322 // This is called from the recompiled JR/JALR instructions
323 void *get_addr(u_int vaddr)
325 u_int page=get_page(vaddr);
326 u_int vpage=get_vpage(vaddr);
327 struct ll_entry *head;
328 //printf("TRACE: count=%d next=%d (get_addr %x,page %d)\n",Count,next_interupt,vaddr,page);
331 if(head->vaddr==vaddr&&head->reg32==0) {
332 //printf("TRACE: count=%d next=%d (get_addr match %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
333 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
336 ht_bin[1]=(int)head->addr;
342 head=jump_dirty[vpage];
344 if(head->vaddr==vaddr&&head->reg32==0) {
345 //printf("TRACE: count=%d next=%d (get_addr match dirty %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
346 // Don't restore blocks which are about to expire from the cache
347 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
348 if(verify_dirty(head->addr)) {
349 //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]);
350 invalid_code[vaddr>>12]=0;
351 memory_map[vaddr>>12]|=0x40000000;
354 if(tlb_LUT_r[vaddr>>12]) {
355 invalid_code[tlb_LUT_r[vaddr>>12]>>12]=0;
356 memory_map[tlb_LUT_r[vaddr>>12]>>12]|=0x40000000;
359 restore_candidate[vpage>>3]|=1<<(vpage&7);
361 else restore_candidate[page>>3]|=1<<(page&7);
362 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
363 if(ht_bin[0]==vaddr) {
364 ht_bin[1]=(int)head->addr; // Replace existing entry
370 ht_bin[1]=(int)head->addr;
378 //printf("TRACE: count=%d next=%d (get_addr no-match %x)\n",Count,next_interupt,vaddr);
379 int r=new_recompile_block(vaddr);
380 if(r==0) return get_addr(vaddr);
381 // Execute in unmapped page, generate pagefault execption
383 Cause=(vaddr<<31)|0x8;
384 EPC=(vaddr&1)?vaddr-5:vaddr;
386 Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0);
387 EntryHi=BadVAddr&0xFFFFE000;
388 return get_addr_ht(0x80000000);
390 // Look up address in hash table first
391 void *get_addr_ht(u_int vaddr)
393 //printf("TRACE: count=%d next=%d (get_addr_ht %x)\n",Count,next_interupt,vaddr);
394 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
395 if(ht_bin[0]==vaddr) return (void *)ht_bin[1];
396 if(ht_bin[2]==vaddr) return (void *)ht_bin[3];
397 return get_addr(vaddr);
400 void *get_addr_32(u_int vaddr,u_int flags)
402 //printf("TRACE: count=%d next=%d (get_addr_32 %x,flags %x)\n",Count,next_interupt,vaddr,flags);
403 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
404 if(ht_bin[0]==vaddr) return (void *)ht_bin[1];
405 if(ht_bin[2]==vaddr) return (void *)ht_bin[3];
406 u_int page=get_page(vaddr);
407 u_int vpage=get_vpage(vaddr);
408 struct ll_entry *head;
411 if(head->vaddr==vaddr&&(head->reg32&flags)==0) {
412 //printf("TRACE: count=%d next=%d (get_addr_32 match %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
414 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
416 ht_bin[1]=(int)head->addr;
418 }else if(ht_bin[2]==-1) {
419 ht_bin[3]=(int)head->addr;
422 //ht_bin[3]=ht_bin[1];
423 //ht_bin[2]=ht_bin[0];
424 //ht_bin[1]=(int)head->addr;
431 head=jump_dirty[vpage];
433 if(head->vaddr==vaddr&&(head->reg32&flags)==0) {
434 //printf("TRACE: count=%d next=%d (get_addr_32 match dirty %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
435 // Don't restore blocks which are about to expire from the cache
436 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
437 if(verify_dirty(head->addr)) {
438 //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]);
439 invalid_code[vaddr>>12]=0;
440 memory_map[vaddr>>12]|=0x40000000;
443 if(tlb_LUT_r[vaddr>>12]) {
444 invalid_code[tlb_LUT_r[vaddr>>12]>>12]=0;
445 memory_map[tlb_LUT_r[vaddr>>12]>>12]|=0x40000000;
448 restore_candidate[vpage>>3]|=1<<(vpage&7);
450 else restore_candidate[page>>3]|=1<<(page&7);
452 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
454 ht_bin[1]=(int)head->addr;
456 }else if(ht_bin[2]==-1) {
457 ht_bin[3]=(int)head->addr;
460 //ht_bin[3]=ht_bin[1];
461 //ht_bin[2]=ht_bin[0];
462 //ht_bin[1]=(int)head->addr;
470 //printf("TRACE: count=%d next=%d (get_addr_32 no-match %x,flags %x)\n",Count,next_interupt,vaddr,flags);
471 int r=new_recompile_block(vaddr);
472 if(r==0) return get_addr(vaddr);
473 // Execute in unmapped page, generate pagefault execption
475 Cause=(vaddr<<31)|0x8;
476 EPC=(vaddr&1)?vaddr-5:vaddr;
478 Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0);
479 EntryHi=BadVAddr&0xFFFFE000;
480 return get_addr_ht(0x80000000);
483 void clear_all_regs(signed char regmap[])
486 for (hr=0;hr<HOST_REGS;hr++) regmap[hr]=-1;
489 signed char get_reg(signed char regmap[],int r)
492 for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&®map[hr]==r) return hr;
496 // Find a register that is available for two consecutive cycles
497 signed char get_reg2(signed char regmap1[],signed char regmap2[],int r)
500 for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&®map1[hr]==r&®map2[hr]==r) return hr;
504 int count_free_regs(signed char regmap[])
508 for(hr=0;hr<HOST_REGS;hr++)
510 if(hr!=EXCLUDE_REG) {
511 if(regmap[hr]<0) count++;
517 void dirty_reg(struct regstat *cur,signed char reg)
521 for (hr=0;hr<HOST_REGS;hr++) {
522 if((cur->regmap[hr]&63)==reg) {
528 // If we dirty the lower half of a 64 bit register which is now being
529 // sign-extended, we need to dump the upper half.
530 // Note: Do this only after completion of the instruction, because
531 // some instructions may need to read the full 64-bit value even if
532 // overwriting it (eg SLTI, DSRA32).
533 static void flush_dirty_uppers(struct regstat *cur)
536 for (hr=0;hr<HOST_REGS;hr++) {
537 if((cur->dirty>>hr)&1) {
540 if((cur->is32>>(reg&63))&1) cur->regmap[hr]=-1;
545 void set_const(struct regstat *cur,signed char reg,uint64_t value)
549 for (hr=0;hr<HOST_REGS;hr++) {
550 if(cur->regmap[hr]==reg) {
552 cur->constmap[hr]=value;
554 else if((cur->regmap[hr]^64)==reg) {
556 cur->constmap[hr]=value>>32;
561 void clear_const(struct regstat *cur,signed char reg)
565 for (hr=0;hr<HOST_REGS;hr++) {
566 if((cur->regmap[hr]&63)==reg) {
567 cur->isconst&=~(1<<hr);
572 int is_const(struct regstat *cur,signed char reg)
576 for (hr=0;hr<HOST_REGS;hr++) {
577 if((cur->regmap[hr]&63)==reg) {
578 return (cur->isconst>>hr)&1;
583 uint64_t get_const(struct regstat *cur,signed char reg)
587 for (hr=0;hr<HOST_REGS;hr++) {
588 if(cur->regmap[hr]==reg) {
589 return cur->constmap[hr];
592 printf("Unknown constant in r%d\n",reg);
596 // Least soon needed registers
597 // Look at the next ten instructions and see which registers
598 // will be used. Try not to reallocate these.
599 void lsn(u_char hsn[], int i, int *preferred_reg)
609 if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
611 // Don't go past an unconditonal jump
618 if(rs1[i+j]) hsn[rs1[i+j]]=j;
619 if(rs2[i+j]) hsn[rs2[i+j]]=j;
620 if(rt1[i+j]) hsn[rt1[i+j]]=j;
621 if(rt2[i+j]) hsn[rt2[i+j]]=j;
622 if(itype[i+j]==STORE || itype[i+j]==STORELR) {
623 // Stores can allocate zero
627 // On some architectures stores need invc_ptr
628 #if defined(HOST_IMM8)
629 if(itype[i+j]==STORE || itype[i+j]==STORELR || (opcode[i+j]&0x3b)==0x39) {
633 if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP))
641 if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
643 // Follow first branch
644 int t=(ba[i+b]-start)>>2;
645 j=7-b;if(t+j>=slen) j=slen-t-1;
648 if(rs1[t+j]) if(hsn[rs1[t+j]]>j+b+2) hsn[rs1[t+j]]=j+b+2;
649 if(rs2[t+j]) if(hsn[rs2[t+j]]>j+b+2) hsn[rs2[t+j]]=j+b+2;
650 //if(rt1[t+j]) if(hsn[rt1[t+j]]>j+b+2) hsn[rt1[t+j]]=j+b+2;
651 //if(rt2[t+j]) if(hsn[rt2[t+j]]>j+b+2) hsn[rt2[t+j]]=j+b+2;
654 // TODO: preferred register based on backward branch
656 // Delay slot should preferably not overwrite branch conditions or cycle count
657 if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)) {
658 if(rs1[i-1]) if(hsn[rs1[i-1]]>1) hsn[rs1[i-1]]=1;
659 if(rs2[i-1]) if(hsn[rs2[i-1]]>1) hsn[rs2[i-1]]=1;
665 // Coprocessor load/store needs FTEMP, even if not declared
669 // Load L/R also uses FTEMP as a temporary register
670 if(itype[i]==LOADLR) {
673 // Also 64-bit SDL/SDR
674 if(opcode[i]==0x2c||opcode[i]==0x2d) {
677 // Don't remove the TLB registers either
678 if(itype[i]==LOAD || itype[i]==LOADLR || itype[i]==STORE || itype[i]==STORELR || itype[i]==C1LS ) {
681 // Don't remove the miniht registers
682 if(itype[i]==UJUMP||itype[i]==RJUMP)
689 // We only want to allocate registers if we're going to use them again soon
690 int needed_again(int r, int i)
696 u_char hsn[MAXREG+1];
699 memset(hsn,10,sizeof(hsn));
700 lsn(hsn,i,&preferred_reg);
702 if(i>0&&(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000))
704 if(ba[i-1]<start || ba[i-1]>start+slen*4-4)
705 return 0; // Don't need any registers if exiting the block
713 if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
715 // Don't go past an unconditonal jump
719 if(itype[i+j]==SYSCALL||((source[i+j]&0xfc00003f)==0x0d))
726 if(rs1[i+j]==r) rn=j;
727 if(rs2[i+j]==r) rn=j;
728 if((unneeded_reg[i+j]>>r)&1) rn=10;
729 if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP))
737 if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
739 // Follow first branch
741 int t=(ba[i+b]-start)>>2;
742 j=7-b;if(t+j>=slen) j=slen-t-1;
745 if(!((unneeded_reg[t+j]>>r)&1)) {
746 if(rs1[t+j]==r) if(rn>j+b+2) rn=j+b+2;
747 if(rs2[t+j]==r) if(rn>j+b+2) rn=j+b+2;
753 for(hr=0;hr<HOST_REGS;hr++) {
754 if(hr!=EXCLUDE_REG) {
755 if(rn<hsn[hr]) return 1;
761 // Try to match register allocations at the end of a loop with those
763 int loop_reg(int i, int r, int hr)
772 if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
774 // Don't go past an unconditonal jump
781 if(itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)
786 if(r<64&&((unneeded_reg[i+k]>>r)&1)) return hr;
787 if(r>64&&((unneeded_reg_upper[i+k]>>r)&1)) return hr;
788 if(i+k>=0&&(itype[i+k]==UJUMP||itype[i+k]==CJUMP||itype[i+k]==SJUMP||itype[i+k]==FJUMP))
790 if(ba[i+k]>=start && ba[i+k]<(start+i*4))
792 int t=(ba[i+k]-start)>>2;
793 int reg=get_reg(regs[t].regmap_entry,r);
794 if(reg>=0) return reg;
795 //reg=get_reg(regs[t+1].regmap_entry,r);
796 //if(reg>=0) return reg;
804 // Allocate every register, preserving source/target regs
805 void alloc_all(struct regstat *cur,int i)
809 for(hr=0;hr<HOST_REGS;hr++) {
810 if(hr!=EXCLUDE_REG) {
811 if(((cur->regmap[hr]&63)!=rs1[i])&&((cur->regmap[hr]&63)!=rs2[i])&&
812 ((cur->regmap[hr]&63)!=rt1[i])&&((cur->regmap[hr]&63)!=rt2[i]))
815 cur->dirty&=~(1<<hr);
818 if((cur->regmap[hr]&63)==0)
821 cur->dirty&=~(1<<hr);
828 void div64(int64_t dividend,int64_t divisor)
832 //printf("TRACE: ddiv %8x%8x %8x%8x\n" ,(int)reg[HIREG],(int)(reg[HIREG]>>32)
833 // ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
835 void divu64(uint64_t dividend,uint64_t divisor)
839 //printf("TRACE: ddivu %8x%8x %8x%8x\n",(int)reg[HIREG],(int)(reg[HIREG]>>32)
840 // ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
843 void mult64(uint64_t m1,uint64_t m2)
845 unsigned long long int op1, op2, op3, op4;
846 unsigned long long int result1, result2, result3, result4;
847 unsigned long long int temp1, temp2, temp3, temp4;
863 op1 = op2 & 0xFFFFFFFF;
864 op2 = (op2 >> 32) & 0xFFFFFFFF;
865 op3 = op4 & 0xFFFFFFFF;
866 op4 = (op4 >> 32) & 0xFFFFFFFF;
869 temp2 = (temp1 >> 32) + op1 * op4;
871 temp4 = (temp3 >> 32) + op2 * op4;
873 result1 = temp1 & 0xFFFFFFFF;
874 result2 = temp2 + (temp3 & 0xFFFFFFFF);
875 result3 = (result2 >> 32) + temp4;
876 result4 = (result3 >> 32);
878 lo = result1 | (result2 << 32);
879 hi = (result3 & 0xFFFFFFFF) | (result4 << 32);
888 void multu64(uint64_t m1,uint64_t m2)
890 unsigned long long int op1, op2, op3, op4;
891 unsigned long long int result1, result2, result3, result4;
892 unsigned long long int temp1, temp2, temp3, temp4;
894 op1 = m1 & 0xFFFFFFFF;
895 op2 = (m1 >> 32) & 0xFFFFFFFF;
896 op3 = m2 & 0xFFFFFFFF;
897 op4 = (m2 >> 32) & 0xFFFFFFFF;
900 temp2 = (temp1 >> 32) + op1 * op4;
902 temp4 = (temp3 >> 32) + op2 * op4;
904 result1 = temp1 & 0xFFFFFFFF;
905 result2 = temp2 + (temp3 & 0xFFFFFFFF);
906 result3 = (result2 >> 32) + temp4;
907 result4 = (result3 >> 32);
909 lo = result1 | (result2 << 32);
910 hi = (result3 & 0xFFFFFFFF) | (result4 << 32);
912 //printf("TRACE: dmultu %8x%8x %8x%8x\n",(int)reg[HIREG],(int)(reg[HIREG]>>32)
913 // ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
916 uint64_t ldl_merge(uint64_t original,uint64_t loaded,u_int bits)
924 else original=loaded;
927 uint64_t ldr_merge(uint64_t original,uint64_t loaded,u_int bits)
930 original>>=64-(bits^56);
931 original<<=64-(bits^56);
935 else original=loaded;
940 #include "assem_x86.c"
943 #include "assem_x64.c"
946 #include "assem_arm.c"
949 // Add virtual address mapping to linked list
950 void ll_add(struct ll_entry **head,int vaddr,void *addr)
952 struct ll_entry *new_entry;
953 new_entry=malloc(sizeof(struct ll_entry));
954 assert(new_entry!=NULL);
955 new_entry->vaddr=vaddr;
957 new_entry->addr=addr;
958 new_entry->next=*head;
962 // Add virtual address mapping for 32-bit compiled block
963 void ll_add_32(struct ll_entry **head,int vaddr,u_int reg32,void *addr)
965 struct ll_entry *new_entry;
966 new_entry=malloc(sizeof(struct ll_entry));
967 assert(new_entry!=NULL);
968 new_entry->vaddr=vaddr;
969 new_entry->reg32=reg32;
970 new_entry->addr=addr;
971 new_entry->next=*head;
975 // Check if an address is already compiled
976 // but don't return addresses which are about to expire from the cache
977 void *check_addr(u_int vaddr)
979 u_int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
980 if(ht_bin[0]==vaddr) {
981 if(((ht_bin[1]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
982 if(isclean(ht_bin[1])) return (void *)ht_bin[1];
984 if(ht_bin[2]==vaddr) {
985 if(((ht_bin[3]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
986 if(isclean(ht_bin[3])) return (void *)ht_bin[3];
988 u_int page=get_page(vaddr);
989 struct ll_entry *head;
992 if(head->vaddr==vaddr&&head->reg32==0) {
993 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
994 // Update existing entry with current address
995 if(ht_bin[0]==vaddr) {
996 ht_bin[1]=(int)head->addr;
999 if(ht_bin[2]==vaddr) {
1000 ht_bin[3]=(int)head->addr;
1003 // Insert into hash table with low priority.
1004 // Don't evict existing entries, as they are probably
1005 // addresses that are being accessed frequently.
1007 ht_bin[1]=(int)head->addr;
1009 }else if(ht_bin[2]==-1) {
1010 ht_bin[3]=(int)head->addr;
1021 void remove_hash(int vaddr)
1023 //printf("remove hash: %x\n",vaddr);
1024 int *ht_bin=hash_table[(((vaddr)>>16)^vaddr)&0xFFFF];
1025 if(ht_bin[2]==vaddr) {
1026 ht_bin[2]=ht_bin[3]=-1;
1028 if(ht_bin[0]==vaddr) {
1029 ht_bin[0]=ht_bin[2];
1030 ht_bin[1]=ht_bin[3];
1031 ht_bin[2]=ht_bin[3]=-1;
1035 void ll_remove_matching_addrs(struct ll_entry **head,int addr,int shift)
1037 struct ll_entry *next;
1039 if(((u_int)((*head)->addr)>>shift)==(addr>>shift) ||
1040 ((u_int)((*head)->addr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift))
1042 inv_debug("EXP: Remove pointer to %x (%x)\n",(int)(*head)->addr,(*head)->vaddr);
1043 remove_hash((*head)->vaddr);
1050 head=&((*head)->next);
1055 // Remove all entries from linked list
1056 void ll_clear(struct ll_entry **head)
1058 struct ll_entry *cur;
1059 struct ll_entry *next;
1070 // Dereference the pointers and remove if it matches
1071 void ll_kill_pointers(struct ll_entry *head,int addr,int shift)
1074 int ptr=get_pointer(head->addr);
1075 inv_debug("EXP: Lookup pointer to %x at %x (%x)\n",(int)ptr,(int)head->addr,head->vaddr);
1076 if(((ptr>>shift)==(addr>>shift)) ||
1077 (((ptr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift)))
1079 inv_debug("EXP: Kill pointer at %x (%x)\n",(int)head->addr,head->vaddr);
1080 kill_pointer(head->addr);
1086 // This is called when we write to a compiled block (see do_invstub)
1087 int invalidate_page(u_int page)
1090 struct ll_entry *head;
1091 struct ll_entry *next;
1095 inv_debug("INVALIDATE: %x\n",head->vaddr);
1096 remove_hash(head->vaddr);
1101 head=jump_out[page];
1104 inv_debug("INVALIDATE: kill pointer to %x (%x)\n",head->vaddr,(int)head->addr);
1105 kill_pointer(head->addr);
1113 void invalidate_block(u_int block)
1116 u_int page=get_page(block<<12);
1117 u_int vpage=get_vpage(block<<12);
1118 inv_debug("INVALIDATE: %x (%d)\n",block<<12,page);
1119 //inv_debug("invalid_code[block]=%d\n",invalid_code[block]);
1122 struct ll_entry *head;
1123 head=jump_dirty[vpage];
1124 //printf("page=%d vpage=%d\n",page,vpage);
1127 if(vpage>2047||(head->vaddr>>12)==block) { // Ignore vaddr hash collision
1128 get_bounds((int)head->addr,&start,&end);
1129 //printf("start: %x end: %x\n",start,end);
1130 if(page<2048&&start>=0x80000000&&end<0x80800000) {
1131 if(((start-(u_int)rdram)>>12)<=page&&((end-1-(u_int)rdram)>>12)>=page) {
1132 if((((start-(u_int)rdram)>>12)&2047)<first) first=((start-(u_int)rdram)>>12)&2047;
1133 if((((end-1-(u_int)rdram)>>12)&2047)>last) last=((end-1-(u_int)rdram)>>12)&2047;
1136 if(page<2048&&(signed int)start>=(signed int)0xC0000000&&(signed int)end>=(signed int)0xC0000000) {
1137 if(((start+memory_map[start>>12]-(u_int)rdram)>>12)<=page&&((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)>=page) {
1138 if((((start+memory_map[start>>12]-(u_int)rdram)>>12)&2047)<first) first=((start+memory_map[start>>12]-(u_int)rdram)>>12)&2047;
1139 if((((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)&2047)>last) last=((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)&2047;
1145 //printf("first=%d last=%d\n",first,last);
1146 modified=invalidate_page(page);
1147 assert(first+5>page); // NB: this assumes MAXBLOCK<=4096 (4 pages)
1148 assert(last<page+5);
1149 // Invalidate the adjacent pages if a block crosses a 4K boundary
1151 invalidate_page(first);
1154 for(first=page+1;first<last;first++) {
1155 invalidate_page(first);
1158 // Don't trap writes
1159 invalid_code[block]=1;
1161 // If there is a valid TLB entry for this page, remove write protect
1162 if(tlb_LUT_w[block]) {
1163 assert(tlb_LUT_r[block]==tlb_LUT_w[block]);
1164 // CHECK: Is this right?
1165 memory_map[block]=((tlb_LUT_w[block]&0xFFFFF000)-(block<<12)+(unsigned int)rdram-0x80000000)>>2;
1166 u_int real_block=tlb_LUT_w[block]>>12;
1167 invalid_code[real_block]=1;
1168 if(real_block>=0x80000&&real_block<0x80800) memory_map[real_block]=((u_int)rdram-0x80000000)>>2;
1170 else if(block>=0x80000&&block<0x80800) memory_map[block]=((u_int)rdram-0x80000000)>>2;
1174 __clear_cache((void *)BASE_ADDR,(void *)BASE_ADDR+(1<<TARGET_SIZE_2));
1177 memset(mini_ht,-1,sizeof(mini_ht));
1180 void invalidate_addr(u_int addr)
1182 invalidate_block(addr>>12);
1184 void invalidate_all_pages()
1187 for(page=0;page<4096;page++)
1188 invalidate_page(page);
1189 for(page=0;page<1048576;page++)
1190 if(!invalid_code[page]) {
1191 restore_candidate[(page&2047)>>3]|=1<<(page&7);
1192 restore_candidate[((page&2047)>>3)+256]|=1<<(page&7);
1195 __clear_cache((void *)BASE_ADDR,(void *)BASE_ADDR+(1<<TARGET_SIZE_2));
1198 memset(mini_ht,-1,sizeof(mini_ht));
1202 for(page=0;page<0x100000;page++) {
1203 if(tlb_LUT_r[page]) {
1204 memory_map[page]=((tlb_LUT_r[page]&0xFFFFF000)-(page<<12)+(unsigned int)rdram-0x80000000)>>2;
1205 if(!tlb_LUT_w[page]||!invalid_code[page])
1206 memory_map[page]|=0x40000000; // Write protect
1208 else memory_map[page]=-1;
1209 if(page==0x80000) page=0xC0000;
1215 // Add an entry to jump_out after making a link
1216 void add_link(u_int vaddr,void *src)
1218 u_int page=get_page(vaddr);
1219 inv_debug("add_link: %x -> %x (%d)\n",(int)src,vaddr,page);
1220 ll_add(jump_out+page,vaddr,src);
1221 //int ptr=get_pointer(src);
1222 //inv_debug("add_link: Pointer is to %x\n",(int)ptr);
1225 // If a code block was found to be unmodified (bit was set in
1226 // restore_candidate) and it remains unmodified (bit is clear
1227 // in invalid_code) then move the entries for that 4K page from
1228 // the dirty list to the clean list.
1229 void clean_blocks(u_int page)
1231 struct ll_entry *head;
1232 inv_debug("INV: clean_blocks page=%d\n",page);
1233 head=jump_dirty[page];
1235 if(!invalid_code[head->vaddr>>12]) {
1236 // Don't restore blocks which are about to expire from the cache
1237 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1239 if(verify_dirty((int)head->addr)) {
1240 //printf("Possibly Restore %x (%x)\n",head->vaddr, (int)head->addr);
1243 get_bounds((int)head->addr,&start,&end);
1244 if(start-(u_int)rdram<0x800000) {
1245 for(i=(start-(u_int)rdram+0x80000000)>>12;i<=(end-1-(u_int)rdram+0x80000000)>>12;i++) {
1246 inv|=invalid_code[i];
1249 if((signed int)head->vaddr>=(signed int)0xC0000000) {
1250 u_int addr = (head->vaddr+(memory_map[head->vaddr>>12]<<2));
1251 //printf("addr=%x start=%x end=%x\n",addr,start,end);
1252 if(addr<start||addr>=end) inv=1;
1254 else if((signed int)head->vaddr>=(signed int)0x80800000) {
1258 void * clean_addr=(void *)get_clean_addr((int)head->addr);
1259 if((((u_int)clean_addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1262 if(page<2048&&tlb_LUT_r[head->vaddr>>12]) ppage=(tlb_LUT_r[head->vaddr>>12]^0x80000000)>>12;
1264 inv_debug("INV: Restored %x (%x/%x)\n",head->vaddr, (int)head->addr, (int)clean_addr);
1265 //printf("page=%x, addr=%x\n",page,head->vaddr);
1266 //assert(head->vaddr>>12==(page|0x80000));
1267 ll_add_32(jump_in+ppage,head->vaddr,head->reg32,clean_addr);
1268 int *ht_bin=hash_table[((head->vaddr>>16)^head->vaddr)&0xFFFF];
1270 if(ht_bin[0]==head->vaddr) {
1271 ht_bin[1]=(int)clean_addr; // Replace existing entry
1273 if(ht_bin[2]==head->vaddr) {
1274 ht_bin[3]=(int)clean_addr; // Replace existing entry
1287 void mov_alloc(struct regstat *current,int i)
1289 // Note: Don't need to actually alloc the source registers
1290 if((~current->is32>>rs1[i])&1) {
1291 //alloc_reg64(current,i,rs1[i]);
1292 alloc_reg64(current,i,rt1[i]);
1293 current->is32&=~(1LL<<rt1[i]);
1295 //alloc_reg(current,i,rs1[i]);
1296 alloc_reg(current,i,rt1[i]);
1297 current->is32|=(1LL<<rt1[i]);
1299 clear_const(current,rs1[i]);
1300 clear_const(current,rt1[i]);
1301 dirty_reg(current,rt1[i]);
1304 void shiftimm_alloc(struct regstat *current,int i)
1306 clear_const(current,rs1[i]);
1307 clear_const(current,rt1[i]);
1308 if(opcode2[i]<=0x3) // SLL/SRL/SRA
1311 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1313 alloc_reg(current,i,rt1[i]);
1314 current->is32|=1LL<<rt1[i];
1315 dirty_reg(current,rt1[i]);
1318 if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA
1321 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1322 alloc_reg64(current,i,rt1[i]);
1323 current->is32&=~(1LL<<rt1[i]);
1324 dirty_reg(current,rt1[i]);
1327 if(opcode2[i]==0x3c) // DSLL32
1330 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1331 alloc_reg64(current,i,rt1[i]);
1332 current->is32&=~(1LL<<rt1[i]);
1333 dirty_reg(current,rt1[i]);
1336 if(opcode2[i]==0x3e) // DSRL32
1339 alloc_reg64(current,i,rs1[i]);
1341 alloc_reg64(current,i,rt1[i]);
1342 current->is32&=~(1LL<<rt1[i]);
1344 alloc_reg(current,i,rt1[i]);
1345 current->is32|=1LL<<rt1[i];
1347 dirty_reg(current,rt1[i]);
1350 if(opcode2[i]==0x3f) // DSRA32
1353 alloc_reg64(current,i,rs1[i]);
1354 alloc_reg(current,i,rt1[i]);
1355 current->is32|=1LL<<rt1[i];
1356 dirty_reg(current,rt1[i]);
1361 void shift_alloc(struct regstat *current,int i)
1364 if(opcode2[i]<=0x07) // SLLV/SRLV/SRAV
1366 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1367 if(rs2[i]) alloc_reg(current,i,rs2[i]);
1368 alloc_reg(current,i,rt1[i]);
1369 if(rt1[i]==rs2[i]) alloc_reg_temp(current,i,-1);
1370 current->is32|=1LL<<rt1[i];
1371 } else { // DSLLV/DSRLV/DSRAV
1372 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1373 if(rs2[i]) alloc_reg(current,i,rs2[i]);
1374 alloc_reg64(current,i,rt1[i]);
1375 current->is32&=~(1LL<<rt1[i]);
1376 if(opcode2[i]==0x16||opcode2[i]==0x17) // DSRLV and DSRAV need a temporary register
1377 alloc_reg_temp(current,i,-1);
1379 clear_const(current,rs1[i]);
1380 clear_const(current,rs2[i]);
1381 clear_const(current,rt1[i]);
1382 dirty_reg(current,rt1[i]);
1386 void alu_alloc(struct regstat *current,int i)
1388 if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
1390 if(rs1[i]&&rs2[i]) {
1391 alloc_reg(current,i,rs1[i]);
1392 alloc_reg(current,i,rs2[i]);
1395 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1396 if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]);
1398 alloc_reg(current,i,rt1[i]);
1400 current->is32|=1LL<<rt1[i];
1402 if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU
1404 if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1406 alloc_reg64(current,i,rs1[i]);
1407 alloc_reg64(current,i,rs2[i]);
1408 alloc_reg(current,i,rt1[i]);
1410 alloc_reg(current,i,rs1[i]);
1411 alloc_reg(current,i,rs2[i]);
1412 alloc_reg(current,i,rt1[i]);
1415 current->is32|=1LL<<rt1[i];
1417 if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR
1419 if(rs1[i]&&rs2[i]) {
1420 alloc_reg(current,i,rs1[i]);
1421 alloc_reg(current,i,rs2[i]);
1425 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1426 if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]);
1428 alloc_reg(current,i,rt1[i]);
1429 if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1431 if(!((current->uu>>rt1[i])&1)) {
1432 alloc_reg64(current,i,rt1[i]);
1434 if(get_reg(current->regmap,rt1[i]|64)>=0) {
1435 if(rs1[i]&&rs2[i]) {
1436 alloc_reg64(current,i,rs1[i]);
1437 alloc_reg64(current,i,rs2[i]);
1441 // Is is really worth it to keep 64-bit values in registers?
1443 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]);
1444 if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg64(current,i,rs2[i]);
1448 current->is32&=~(1LL<<rt1[i]);
1450 current->is32|=1LL<<rt1[i];
1454 if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU
1456 if(rs1[i]&&rs2[i]) {
1457 if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1458 alloc_reg64(current,i,rs1[i]);
1459 alloc_reg64(current,i,rs2[i]);
1460 alloc_reg64(current,i,rt1[i]);
1462 alloc_reg(current,i,rs1[i]);
1463 alloc_reg(current,i,rs2[i]);
1464 alloc_reg(current,i,rt1[i]);
1468 alloc_reg(current,i,rt1[i]);
1469 if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1470 // DADD used as move, or zeroing
1471 // If we have a 64-bit source, then make the target 64 bits too
1472 if(rs1[i]&&!((current->is32>>rs1[i])&1)) {
1473 if(get_reg(current->regmap,rs1[i])>=0) alloc_reg64(current,i,rs1[i]);
1474 alloc_reg64(current,i,rt1[i]);
1475 } else if(rs2[i]&&!((current->is32>>rs2[i])&1)) {
1476 if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]);
1477 alloc_reg64(current,i,rt1[i]);
1479 if(opcode2[i]>=0x2e&&rs2[i]) {
1480 // DSUB used as negation - 64-bit result
1481 // If we have a 32-bit register, extend it to 64 bits
1482 if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]);
1483 alloc_reg64(current,i,rt1[i]);
1487 if(rs1[i]&&rs2[i]) {
1488 current->is32&=~(1LL<<rt1[i]);
1490 current->is32&=~(1LL<<rt1[i]);
1491 if((current->is32>>rs1[i])&1)
1492 current->is32|=1LL<<rt1[i];
1494 current->is32&=~(1LL<<rt1[i]);
1495 if((current->is32>>rs2[i])&1)
1496 current->is32|=1LL<<rt1[i];
1498 current->is32|=1LL<<rt1[i];
1502 clear_const(current,rs1[i]);
1503 clear_const(current,rs2[i]);
1504 clear_const(current,rt1[i]);
1505 dirty_reg(current,rt1[i]);
1508 void imm16_alloc(struct regstat *current,int i)
1510 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1512 if(rt1[i]) alloc_reg(current,i,rt1[i]);
1513 if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU
1514 current->is32&=~(1LL<<rt1[i]);
1515 if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1516 // TODO: Could preserve the 32-bit flag if the immediate is zero
1517 alloc_reg64(current,i,rt1[i]);
1518 alloc_reg64(current,i,rs1[i]);
1520 clear_const(current,rs1[i]);
1521 clear_const(current,rt1[i]);
1523 else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU
1524 if((~current->is32>>rs1[i])&1) alloc_reg64(current,i,rs1[i]);
1525 current->is32|=1LL<<rt1[i];
1526 clear_const(current,rs1[i]);
1527 clear_const(current,rt1[i]);
1529 else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI
1530 if(((~current->is32>>rs1[i])&1)&&opcode[i]>0x0c) {
1531 if(rs1[i]!=rt1[i]) {
1532 if(needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]);
1533 alloc_reg64(current,i,rt1[i]);
1534 current->is32&=~(1LL<<rt1[i]);
1537 else current->is32|=1LL<<rt1[i]; // ANDI clears upper bits
1538 if(is_const(current,rs1[i])) {
1539 int v=get_const(current,rs1[i]);
1540 if(opcode[i]==0x0c) set_const(current,rt1[i],v&imm[i]);
1541 if(opcode[i]==0x0d) set_const(current,rt1[i],v|imm[i]);
1542 if(opcode[i]==0x0e) set_const(current,rt1[i],v^imm[i]);
1544 else clear_const(current,rt1[i]);
1546 else if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU
1547 if(is_const(current,rs1[i])) {
1548 int v=get_const(current,rs1[i]);
1549 set_const(current,rt1[i],v+imm[i]);
1551 else clear_const(current,rt1[i]);
1552 current->is32|=1LL<<rt1[i];
1555 set_const(current,rt1[i],((long long)((short)imm[i]))<<16); // LUI
1556 current->is32|=1LL<<rt1[i];
1558 dirty_reg(current,rt1[i]);
1561 void load_alloc(struct regstat *current,int i)
1563 clear_const(current,rt1[i]);
1564 //if(rs1[i]!=rt1[i]&&needed_again(rs1[i],i)) clear_const(current,rs1[i]); // Does this help or hurt?
1565 if(!rs1[i]) current->u&=~1LL; // Allow allocating r0 if it's the source register
1566 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1568 alloc_reg(current,i,rt1[i]);
1569 if(opcode[i]==0x27||opcode[i]==0x37) // LWU/LD
1571 current->is32&=~(1LL<<rt1[i]);
1572 alloc_reg64(current,i,rt1[i]);
1574 else if(opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
1576 current->is32&=~(1LL<<rt1[i]);
1577 alloc_reg64(current,i,rt1[i]);
1578 alloc_all(current,i);
1579 alloc_reg64(current,i,FTEMP);
1581 else current->is32|=1LL<<rt1[i];
1582 dirty_reg(current,rt1[i]);
1583 // If using TLB, need a register for pointer to the mapping table
1584 if(using_tlb) alloc_reg(current,i,TLREG);
1585 // LWL/LWR need a temporary register for the old value
1586 if(opcode[i]==0x22||opcode[i]==0x26)
1588 alloc_reg(current,i,FTEMP);
1589 alloc_reg_temp(current,i,-1);
1594 // Load to r0 (dummy load)
1595 // but we still need a register to calculate the address
1596 alloc_reg_temp(current,i,-1);
1600 void store_alloc(struct regstat *current,int i)
1602 clear_const(current,rs2[i]);
1603 if(!(rs2[i])) current->u&=~1LL; // Allow allocating r0 if necessary
1604 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1605 alloc_reg(current,i,rs2[i]);
1606 if(opcode[i]==0x2c||opcode[i]==0x2d||opcode[i]==0x3f) { // 64-bit SDL/SDR/SD
1607 alloc_reg64(current,i,rs2[i]);
1608 if(rs2[i]) alloc_reg(current,i,FTEMP);
1610 // If using TLB, need a register for pointer to the mapping table
1611 if(using_tlb) alloc_reg(current,i,TLREG);
1612 #if defined(HOST_IMM8)
1613 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1614 else alloc_reg(current,i,INVCP);
1616 if(opcode[i]==0x2c||opcode[i]==0x2d) { // 64-bit SDL/SDR
1617 alloc_reg(current,i,FTEMP);
1619 // We need a temporary register for address generation
1620 alloc_reg_temp(current,i,-1);
1623 void c1ls_alloc(struct regstat *current,int i)
1625 //clear_const(current,rs1[i]); // FIXME
1626 clear_const(current,rt1[i]);
1627 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1628 alloc_reg(current,i,CSREG); // Status
1629 alloc_reg(current,i,FTEMP);
1630 if(opcode[i]==0x35||opcode[i]==0x3d) { // 64-bit LDC1/SDC1
1631 alloc_reg64(current,i,FTEMP);
1633 // If using TLB, need a register for pointer to the mapping table
1634 if(using_tlb) alloc_reg(current,i,TLREG);
1635 #if defined(HOST_IMM8)
1636 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1637 else if((opcode[i]&0x3b)==0x39) // SWC1/SDC1
1638 alloc_reg(current,i,INVCP);
1640 // We need a temporary register for address generation
1641 alloc_reg_temp(current,i,-1);
1644 #ifndef multdiv_alloc
1645 void multdiv_alloc(struct regstat *current,int i)
1652 // case 0x1D: DMULTU
1655 clear_const(current,rs1[i]);
1656 clear_const(current,rs2[i]);
1659 if((opcode2[i]&4)==0) // 32-bit
1661 current->u&=~(1LL<<HIREG);
1662 current->u&=~(1LL<<LOREG);
1663 alloc_reg(current,i,HIREG);
1664 alloc_reg(current,i,LOREG);
1665 alloc_reg(current,i,rs1[i]);
1666 alloc_reg(current,i,rs2[i]);
1667 current->is32|=1LL<<HIREG;
1668 current->is32|=1LL<<LOREG;
1669 dirty_reg(current,HIREG);
1670 dirty_reg(current,LOREG);
1674 current->u&=~(1LL<<HIREG);
1675 current->u&=~(1LL<<LOREG);
1676 current->uu&=~(1LL<<HIREG);
1677 current->uu&=~(1LL<<LOREG);
1678 alloc_reg64(current,i,HIREG);
1679 //if(HOST_REGS>10) alloc_reg64(current,i,LOREG);
1680 alloc_reg64(current,i,rs1[i]);
1681 alloc_reg64(current,i,rs2[i]);
1682 alloc_all(current,i);
1683 current->is32&=~(1LL<<HIREG);
1684 current->is32&=~(1LL<<LOREG);
1685 dirty_reg(current,HIREG);
1686 dirty_reg(current,LOREG);
1691 // Multiply by zero is zero.
1692 // MIPS does not have a divide by zero exception.
1693 // The result is undefined, we return zero.
1694 alloc_reg(current,i,HIREG);
1695 alloc_reg(current,i,LOREG);
1696 current->is32|=1LL<<HIREG;
1697 current->is32|=1LL<<LOREG;
1698 dirty_reg(current,HIREG);
1699 dirty_reg(current,LOREG);
1704 void cop0_alloc(struct regstat *current,int i)
1706 if(opcode2[i]==0) // MFC0
1709 clear_const(current,rt1[i]);
1710 alloc_all(current,i);
1711 alloc_reg(current,i,rt1[i]);
1712 current->is32|=1LL<<rt1[i];
1713 dirty_reg(current,rt1[i]);
1716 else if(opcode2[i]==4) // MTC0
1719 clear_const(current,rs1[i]);
1720 alloc_reg(current,i,rs1[i]);
1721 alloc_all(current,i);
1724 alloc_all(current,i); // FIXME: Keep r0
1726 alloc_reg(current,i,0);
1731 // TLBR/TLBWI/TLBWR/TLBP/ERET
1732 assert(opcode2[i]==0x10);
1733 alloc_all(current,i);
1737 void cop1_alloc(struct regstat *current,int i)
1739 alloc_reg(current,i,CSREG); // Load status
1740 if(opcode2[i]<3) // MFC1/DMFC1/CFC1
1743 clear_const(current,rt1[i]);
1745 alloc_reg64(current,i,rt1[i]); // DMFC1
1746 current->is32&=~(1LL<<rt1[i]);
1748 alloc_reg(current,i,rt1[i]); // MFC1/CFC1
1749 current->is32|=1LL<<rt1[i];
1751 dirty_reg(current,rt1[i]);
1752 alloc_reg_temp(current,i,-1);
1754 else if(opcode2[i]>3) // MTC1/DMTC1/CTC1
1757 clear_const(current,rs1[i]);
1759 alloc_reg64(current,i,rs1[i]); // DMTC1
1761 alloc_reg(current,i,rs1[i]); // MTC1/CTC1
1762 alloc_reg_temp(current,i,-1);
1766 alloc_reg(current,i,0);
1767 alloc_reg_temp(current,i,-1);
1771 void fconv_alloc(struct regstat *current,int i)
1773 alloc_reg(current,i,CSREG); // Load status
1774 alloc_reg_temp(current,i,-1);
1776 void float_alloc(struct regstat *current,int i)
1778 alloc_reg(current,i,CSREG); // Load status
1779 alloc_reg_temp(current,i,-1);
1781 void fcomp_alloc(struct regstat *current,int i)
1783 alloc_reg(current,i,CSREG); // Load status
1784 alloc_reg(current,i,FSREG); // Load flags
1785 dirty_reg(current,FSREG); // Flag will be modified
1786 alloc_reg_temp(current,i,-1);
1789 void syscall_alloc(struct regstat *current,int i)
1791 alloc_cc(current,i);
1792 dirty_reg(current,CCREG);
1793 alloc_all(current,i);
1797 void delayslot_alloc(struct regstat *current,int i)
1807 assem_debug("jump in the delay slot. this shouldn't happen.\n");//exit(1);
1808 printf("Disabled speculative precompilation\n");
1812 imm16_alloc(current,i);
1816 load_alloc(current,i);
1820 store_alloc(current,i);
1823 alu_alloc(current,i);
1826 shift_alloc(current,i);
1829 multdiv_alloc(current,i);
1832 shiftimm_alloc(current,i);
1835 mov_alloc(current,i);
1838 cop0_alloc(current,i);
1841 cop1_alloc(current,i);
1844 c1ls_alloc(current,i);
1847 fconv_alloc(current,i);
1850 float_alloc(current,i);
1853 fcomp_alloc(current,i);
1858 // Special case where a branch and delay slot span two pages in virtual memory
1859 static void pagespan_alloc(struct regstat *current,int i)
1862 current->wasconst=0;
1864 alloc_all(current,i);
1865 alloc_cc(current,i);
1866 dirty_reg(current,CCREG);
1867 if(opcode[i]==3) // JAL
1869 alloc_reg(current,i,31);
1870 dirty_reg(current,31);
1872 if(opcode[i]==0&&(opcode2[i]&0x3E)==8) // JR/JALR
1874 alloc_reg(current,i,rs1[i]);
1876 alloc_reg(current,i,31);
1877 dirty_reg(current,31);
1880 if((opcode[i]&0x2E)==4) // BEQ/BNE/BEQL/BNEL
1882 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1883 if(rs2[i]) alloc_reg(current,i,rs2[i]);
1884 if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1886 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1887 if(rs2[i]) alloc_reg64(current,i,rs2[i]);
1891 if((opcode[i]&0x2E)==6) // BLEZ/BGTZ/BLEZL/BGTZL
1893 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1894 if(!((current->is32>>rs1[i])&1))
1896 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1900 if(opcode[i]==0x11) // BC1
1902 alloc_reg(current,i,FSREG);
1903 alloc_reg(current,i,CSREG);
1908 add_stub(int type,int addr,int retaddr,int a,int b,int c,int d,int e)
1910 stubs[stubcount][0]=type;
1911 stubs[stubcount][1]=addr;
1912 stubs[stubcount][2]=retaddr;
1913 stubs[stubcount][3]=a;
1914 stubs[stubcount][4]=b;
1915 stubs[stubcount][5]=c;
1916 stubs[stubcount][6]=d;
1917 stubs[stubcount][7]=e;
1921 // Write out a single register
1922 void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32)
1925 for(hr=0;hr<HOST_REGS;hr++) {
1926 if(hr!=EXCLUDE_REG) {
1927 if((regmap[hr]&63)==r) {
1930 emit_storereg(r,hr);
1932 if((is32>>regmap[hr])&1) {
1933 emit_sarimm(hr,31,hr);
1934 emit_storereg(r|64,hr);
1938 emit_storereg(r|64,hr);
1948 //if(!tracedebug) return 0;
1951 for(i=0;i<2097152;i++) {
1952 unsigned int temp=sum;
1955 sum^=((u_int *)rdram)[i];
1964 sum^=((u_int *)reg)[i];
1972 printf("r%d:%8x%8x ",i,((int *)(reg+i))[1],((int *)(reg+i))[0]);
1974 #ifndef DISABLE_COP1
1977 printf("f%d:%8x%8x ",i,((int*)reg_cop1_simple[i])[1],*((int*)reg_cop1_simple[i]));
1987 void memdebug(int i)
1989 //printf("TRACE: count=%d next=%d (checksum %x) lo=%8x%8x\n",Count,next_interupt,mchecksum(),(int)(reg[LOREG]>>32),(int)reg[LOREG]);
1990 //printf("TRACE: count=%d next=%d (rchecksum %x)\n",Count,next_interupt,rchecksum());
1993 //if(Count>=-2084597794) {
1994 if((signed int)Count>=-2084597794&&(signed int)Count<0) {
1996 printf("TRACE: count=%d next=%d (checksum %x)\n",Count,next_interupt,mchecksum());
1997 //printf("TRACE: count=%d next=%d (checksum %x) Status=%x\n",Count,next_interupt,mchecksum(),Status);
1998 //printf("TRACE: count=%d next=%d (checksum %x) hi=%8x%8x\n",Count,next_interupt,mchecksum(),(int)(reg[HIREG]>>32),(int)reg[HIREG]);
2001 printf("TRACE: %x\n",(&i)[-1]);
2005 printf("TRACE: %x \n",(&j)[10]);
2006 printf("TRACE: %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x\n",(&j)[1],(&j)[2],(&j)[3],(&j)[4],(&j)[5],(&j)[6],(&j)[7],(&j)[8],(&j)[9],(&j)[10],(&j)[11],(&j)[12],(&j)[13],(&j)[14],(&j)[15],(&j)[16],(&j)[17],(&j)[18],(&j)[19],(&j)[20]);
2010 //printf("TRACE: %x\n",(&i)[-1]);
2013 void tlb_debug(u_int cause, u_int addr, u_int iaddr)
2015 printf("TLB Exception: instruction=%x addr=%x cause=%x\n",iaddr, addr, cause);
2018 void alu_assemble(int i,struct regstat *i_regs)
2020 if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
2022 signed char s1,s2,t;
2023 t=get_reg(i_regs->regmap,rt1[i]);
2025 s1=get_reg(i_regs->regmap,rs1[i]);
2026 s2=get_reg(i_regs->regmap,rs2[i]);
2027 if(rs1[i]&&rs2[i]) {
2030 if(opcode2[i]&2) emit_sub(s1,s2,t);
2031 else emit_add(s1,s2,t);
2034 if(s1>=0) emit_mov(s1,t);
2035 else emit_loadreg(rs1[i],t);
2039 if(opcode2[i]&2) emit_neg(s2,t);
2040 else emit_mov(s2,t);
2043 emit_loadreg(rs2[i],t);
2044 if(opcode2[i]&2) emit_neg(t,t);
2047 else emit_zeroreg(t);
2051 if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU
2053 signed char s1l,s2l,s1h,s2h,tl,th;
2054 tl=get_reg(i_regs->regmap,rt1[i]);
2055 th=get_reg(i_regs->regmap,rt1[i]|64);
2057 s1l=get_reg(i_regs->regmap,rs1[i]);
2058 s2l=get_reg(i_regs->regmap,rs2[i]);
2059 s1h=get_reg(i_regs->regmap,rs1[i]|64);
2060 s2h=get_reg(i_regs->regmap,rs2[i]|64);
2061 if(rs1[i]&&rs2[i]) {
2064 if(opcode2[i]&2) emit_subs(s1l,s2l,tl);
2065 else emit_adds(s1l,s2l,tl);
2067 #ifdef INVERTED_CARRY
2068 if(opcode2[i]&2) {if(s1h!=th) emit_mov(s1h,th);emit_sbb(th,s2h);}
2070 if(opcode2[i]&2) emit_sbc(s1h,s2h,th);
2072 else emit_add(s1h,s2h,th);
2076 if(s1l>=0) emit_mov(s1l,tl);
2077 else emit_loadreg(rs1[i],tl);
2079 if(s1h>=0) emit_mov(s1h,th);
2080 else emit_loadreg(rs1[i]|64,th);
2085 if(opcode2[i]&2) emit_negs(s2l,tl);
2086 else emit_mov(s2l,tl);
2089 emit_loadreg(rs2[i],tl);
2090 if(opcode2[i]&2) emit_negs(tl,tl);
2093 #ifdef INVERTED_CARRY
2094 if(s2h>=0) emit_mov(s2h,th);
2095 else emit_loadreg(rs2[i]|64,th);
2097 emit_adcimm(-1,th); // x86 has inverted carry flag
2102 if(s2h>=0) emit_rscimm(s2h,0,th);
2104 emit_loadreg(rs2[i]|64,th);
2105 emit_rscimm(th,0,th);
2108 if(s2h>=0) emit_mov(s2h,th);
2109 else emit_loadreg(rs2[i]|64,th);
2116 if(th>=0) emit_zeroreg(th);
2121 if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU
2123 signed char s1l,s1h,s2l,s2h,t;
2124 if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1))
2126 t=get_reg(i_regs->regmap,rt1[i]);
2129 s1l=get_reg(i_regs->regmap,rs1[i]);
2130 s1h=get_reg(i_regs->regmap,rs1[i]|64);
2131 s2l=get_reg(i_regs->regmap,rs2[i]);
2132 s2h=get_reg(i_regs->regmap,rs2[i]|64);
2133 if(rs2[i]==0) // rx<r0
2136 if(opcode2[i]==0x2a) // SLT
2137 emit_shrimm(s1h,31,t);
2138 else // SLTU (unsigned can not be less than zero)
2141 else if(rs1[i]==0) // r0<rx
2144 if(opcode2[i]==0x2a) // SLT
2145 emit_set_gz64_32(s2h,s2l,t);
2146 else // SLTU (set if not zero)
2147 emit_set_nz64_32(s2h,s2l,t);
2150 assert(s1l>=0);assert(s1h>=0);
2151 assert(s2l>=0);assert(s2h>=0);
2152 if(opcode2[i]==0x2a) // SLT
2153 emit_set_if_less64_32(s1h,s1l,s2h,s2l,t);
2155 emit_set_if_carry64_32(s1h,s1l,s2h,s2l,t);
2159 t=get_reg(i_regs->regmap,rt1[i]);
2162 s1l=get_reg(i_regs->regmap,rs1[i]);
2163 s2l=get_reg(i_regs->regmap,rs2[i]);
2164 if(rs2[i]==0) // rx<r0
2167 if(opcode2[i]==0x2a) // SLT
2168 emit_shrimm(s1l,31,t);
2169 else // SLTU (unsigned can not be less than zero)
2172 else if(rs1[i]==0) // r0<rx
2175 if(opcode2[i]==0x2a) // SLT
2176 emit_set_gz32(s2l,t);
2177 else // SLTU (set if not zero)
2178 emit_set_nz32(s2l,t);
2181 assert(s1l>=0);assert(s2l>=0);
2182 if(opcode2[i]==0x2a) // SLT
2183 emit_set_if_less32(s1l,s2l,t);
2185 emit_set_if_carry32(s1l,s2l,t);
2191 if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR
2193 signed char s1l,s1h,s2l,s2h,th,tl;
2194 tl=get_reg(i_regs->regmap,rt1[i]);
2195 th=get_reg(i_regs->regmap,rt1[i]|64);
2196 if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1)&&th>=0)
2200 s1l=get_reg(i_regs->regmap,rs1[i]);
2201 s1h=get_reg(i_regs->regmap,rs1[i]|64);
2202 s2l=get_reg(i_regs->regmap,rs2[i]);
2203 s2h=get_reg(i_regs->regmap,rs2[i]|64);
2204 if(rs1[i]&&rs2[i]) {
2205 assert(s1l>=0);assert(s1h>=0);
2206 assert(s2l>=0);assert(s2h>=0);
2207 if(opcode2[i]==0x24) { // AND
2208 emit_and(s1l,s2l,tl);
2209 emit_and(s1h,s2h,th);
2211 if(opcode2[i]==0x25) { // OR
2212 emit_or(s1l,s2l,tl);
2213 emit_or(s1h,s2h,th);
2215 if(opcode2[i]==0x26) { // XOR
2216 emit_xor(s1l,s2l,tl);
2217 emit_xor(s1h,s2h,th);
2219 if(opcode2[i]==0x27) { // NOR
2220 emit_or(s1l,s2l,tl);
2221 emit_or(s1h,s2h,th);
2228 if(opcode2[i]==0x24) { // AND
2232 if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR
2234 if(s1l>=0) emit_mov(s1l,tl);
2235 else emit_loadreg(rs1[i],tl);
2236 if(s1h>=0) emit_mov(s1h,th);
2237 else emit_loadreg(rs1[i]|64,th);
2241 if(s2l>=0) emit_mov(s2l,tl);
2242 else emit_loadreg(rs2[i],tl);
2243 if(s2h>=0) emit_mov(s2h,th);
2244 else emit_loadreg(rs2[i]|64,th);
2251 if(opcode2[i]==0x27) { // NOR
2253 if(s1l>=0) emit_not(s1l,tl);
2255 emit_loadreg(rs1[i],tl);
2258 if(s1h>=0) emit_not(s1h,th);
2260 emit_loadreg(rs1[i]|64,th);
2266 if(s2l>=0) emit_not(s2l,tl);
2268 emit_loadreg(rs2[i],tl);
2271 if(s2h>=0) emit_not(s2h,th);
2273 emit_loadreg(rs2[i]|64,th);
2289 s1l=get_reg(i_regs->regmap,rs1[i]);
2290 s2l=get_reg(i_regs->regmap,rs2[i]);
2291 if(rs1[i]&&rs2[i]) {
2294 if(opcode2[i]==0x24) { // AND
2295 emit_and(s1l,s2l,tl);
2297 if(opcode2[i]==0x25) { // OR
2298 emit_or(s1l,s2l,tl);
2300 if(opcode2[i]==0x26) { // XOR
2301 emit_xor(s1l,s2l,tl);
2303 if(opcode2[i]==0x27) { // NOR
2304 emit_or(s1l,s2l,tl);
2310 if(opcode2[i]==0x24) { // AND
2313 if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR
2315 if(s1l>=0) emit_mov(s1l,tl);
2316 else emit_loadreg(rs1[i],tl); // CHECK: regmap_entry?
2320 if(s2l>=0) emit_mov(s2l,tl);
2321 else emit_loadreg(rs2[i],tl); // CHECK: regmap_entry?
2323 else emit_zeroreg(tl);
2325 if(opcode2[i]==0x27) { // NOR
2327 if(s1l>=0) emit_not(s1l,tl);
2329 emit_loadreg(rs1[i],tl);
2335 if(s2l>=0) emit_not(s2l,tl);
2337 emit_loadreg(rs2[i],tl);
2341 else emit_movimm(-1,tl);
2350 void imm16_assemble(int i,struct regstat *i_regs)
2352 if (opcode[i]==0x0f) { // LUI
2355 t=get_reg(i_regs->regmap,rt1[i]);
2358 if(!((i_regs->isconst>>t)&1))
2359 emit_movimm(imm[i]<<16,t);
2363 if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU
2366 t=get_reg(i_regs->regmap,rt1[i]);
2367 s=get_reg(i_regs->regmap,rs1[i]);
2372 if(!((i_regs->isconst>>t)&1)) {
2374 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2375 emit_addimm(t,imm[i],t);
2377 if(!((i_regs->wasconst>>s)&1))
2378 emit_addimm(s,imm[i],t);
2380 emit_movimm(constmap[i][s]+imm[i],t);
2386 if(!((i_regs->isconst>>t)&1))
2387 emit_movimm(imm[i],t);
2392 if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU
2394 signed char sh,sl,th,tl;
2395 th=get_reg(i_regs->regmap,rt1[i]|64);
2396 tl=get_reg(i_regs->regmap,rt1[i]);
2397 sh=get_reg(i_regs->regmap,rs1[i]|64);
2398 sl=get_reg(i_regs->regmap,rs1[i]);
2404 emit_addimm64_32(sh,sl,imm[i],th,tl);
2407 emit_addimm(sl,imm[i],tl);
2410 emit_movimm(imm[i],tl);
2411 if(th>=0) emit_movimm(((signed int)imm[i])>>31,th);
2416 else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU
2418 //assert(rs1[i]!=0); // r0 might be valid, but it's probably a bug
2419 signed char sh,sl,t;
2420 t=get_reg(i_regs->regmap,rt1[i]);
2421 sh=get_reg(i_regs->regmap,rs1[i]|64);
2422 sl=get_reg(i_regs->regmap,rs1[i]);
2426 if(sh<0) assert((i_regs->was32>>rs1[i])&1);
2427 if(sh<0||((i_regs->was32>>rs1[i])&1)) {
2428 if(opcode[i]==0x0a) { // SLTI
2430 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2431 emit_slti32(t,imm[i],t);
2433 emit_slti32(sl,imm[i],t);
2438 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2439 emit_sltiu32(t,imm[i],t);
2441 emit_sltiu32(sl,imm[i],t);
2446 if(opcode[i]==0x0a) // SLTI
2447 emit_slti64_32(sh,sl,imm[i],t);
2449 emit_sltiu64_32(sh,sl,imm[i],t);
2452 // SLTI(U) with r0 is just stupid,
2453 // nonetheless examples can be found
2454 if(opcode[i]==0x0a) // SLTI
2455 if(0<imm[i]) emit_movimm(1,t);
2456 else emit_zeroreg(t);
2459 if(imm[i]) emit_movimm(1,t);
2460 else emit_zeroreg(t);
2466 else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI
2468 signed char sh,sl,th,tl;
2469 th=get_reg(i_regs->regmap,rt1[i]|64);
2470 tl=get_reg(i_regs->regmap,rt1[i]);
2471 sh=get_reg(i_regs->regmap,rs1[i]|64);
2472 sl=get_reg(i_regs->regmap,rs1[i]);
2473 if(tl>=0 && !((i_regs->isconst>>tl)&1)) {
2474 if(opcode[i]==0x0c) //ANDI
2478 if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl);
2479 emit_andimm(tl,imm[i],tl);
2481 if(!((i_regs->wasconst>>sl)&1))
2482 emit_andimm(sl,imm[i],tl);
2484 emit_movimm(constmap[i][sl]&imm[i],tl);
2489 if(th>=0) emit_zeroreg(th);
2495 if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl);
2499 emit_loadreg(rs1[i]|64,th);
2504 if(opcode[i]==0x0d) //ORI
2506 emit_orimm(tl,imm[i],tl);
2508 if(!((i_regs->wasconst>>sl)&1))
2509 emit_orimm(sl,imm[i],tl);
2511 emit_movimm(constmap[i][sl]|imm[i],tl);
2513 if(opcode[i]==0x0e) //XORI
2515 emit_xorimm(tl,imm[i],tl);
2517 if(!((i_regs->wasconst>>sl)&1))
2518 emit_xorimm(sl,imm[i],tl);
2520 emit_movimm(constmap[i][sl]^imm[i],tl);
2524 emit_movimm(imm[i],tl);
2525 if(th>=0) emit_zeroreg(th);
2533 void shiftimm_assemble(int i,struct regstat *i_regs)
2535 if(opcode2[i]<=0x3) // SLL/SRL/SRA
2539 t=get_reg(i_regs->regmap,rt1[i]);
2540 s=get_reg(i_regs->regmap,rs1[i]);
2549 if(s<0&&i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2551 if(opcode2[i]==0) // SLL
2553 emit_shlimm(s<0?t:s,imm[i],t);
2555 if(opcode2[i]==2) // SRL
2557 emit_shrimm(s<0?t:s,imm[i],t);
2559 if(opcode2[i]==3) // SRA
2561 emit_sarimm(s<0?t:s,imm[i],t);
2565 if(s>=0 && s!=t) emit_mov(s,t);
2569 //emit_storereg(rt1[i],t); //DEBUG
2572 if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA
2575 signed char sh,sl,th,tl;
2576 th=get_reg(i_regs->regmap,rt1[i]|64);
2577 tl=get_reg(i_regs->regmap,rt1[i]);
2578 sh=get_reg(i_regs->regmap,rs1[i]|64);
2579 sl=get_reg(i_regs->regmap,rs1[i]);
2584 if(th>=0) emit_zeroreg(th);
2591 if(opcode2[i]==0x38) // DSLL
2593 if(th>=0) emit_shldimm(sh,sl,imm[i],th);
2594 emit_shlimm(sl,imm[i],tl);
2596 if(opcode2[i]==0x3a) // DSRL
2598 emit_shrdimm(sl,sh,imm[i],tl);
2599 if(th>=0) emit_shrimm(sh,imm[i],th);
2601 if(opcode2[i]==0x3b) // DSRA
2603 emit_shrdimm(sl,sh,imm[i],tl);
2604 if(th>=0) emit_sarimm(sh,imm[i],th);
2608 if(sl!=tl) emit_mov(sl,tl);
2609 if(th>=0&&sh!=th) emit_mov(sh,th);
2615 if(opcode2[i]==0x3c) // DSLL32
2618 signed char sl,tl,th;
2619 tl=get_reg(i_regs->regmap,rt1[i]);
2620 th=get_reg(i_regs->regmap,rt1[i]|64);
2621 sl=get_reg(i_regs->regmap,rs1[i]);
2630 emit_shlimm(th,imm[i]&31,th);
2635 if(opcode2[i]==0x3e) // DSRL32
2638 signed char sh,tl,th;
2639 tl=get_reg(i_regs->regmap,rt1[i]);
2640 th=get_reg(i_regs->regmap,rt1[i]|64);
2641 sh=get_reg(i_regs->regmap,rs1[i]|64);
2645 if(th>=0) emit_zeroreg(th);
2648 emit_shrimm(tl,imm[i]&31,tl);
2653 if(opcode2[i]==0x3f) // DSRA32
2657 tl=get_reg(i_regs->regmap,rt1[i]);
2658 sh=get_reg(i_regs->regmap,rs1[i]|64);
2664 emit_sarimm(tl,imm[i]&31,tl);
2671 #ifndef shift_assemble
2672 void shift_assemble(int i,struct regstat *i_regs)
2674 printf("Need shift_assemble for this architecture.\n");
2679 void load_assemble(int i,struct regstat *i_regs)
2681 int s,th,tl,addr,map=-1;
2686 th=get_reg(i_regs->regmap,rt1[i]|64);
2687 tl=get_reg(i_regs->regmap,rt1[i]);
2688 s=get_reg(i_regs->regmap,rs1[i]);
2690 for(hr=0;hr<HOST_REGS;hr++) {
2691 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
2693 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
2695 c=(i_regs->wasconst>>s)&1;
2696 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80800000;
2697 if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
2699 if(offset||s<0||c) addr=tl;
2701 //printf("load_assemble: c=%d\n",c);
2702 //if(c) printf("load_assemble: const=%x\n",(int)constmap[i][s]+offset);
2703 // FIXME: Even if the load is a NOP, we should check for pagefaults...
2708 if(th>=0) reglist&=~(1<<th);
2711 //#define R29_HACK 1
2713 // Strmnnrmn's speed hack
2714 if(rs1[i]!=29||start<0x80001000||start>=0x80800000)
2717 emit_cmpimm(addr,0x800000);
2719 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
2720 // Hint to branch predictor that the branch is unlikely to be taken
2722 emit_jno_unlikely(0);
2730 if (opcode[i]==0x20||opcode[i]==0x24) x=3; // LB/LBU
2731 if (opcode[i]==0x21||opcode[i]==0x25) x=2; // LH/LHU
2732 map=get_reg(i_regs->regmap,TLREG);
2734 map=do_tlb_r(addr,tl,map,x,-1,-1,c,constmap[i][s]+offset);
2735 do_tlb_r_branch(map,c,constmap[i][s]+offset,&jaddr);
2737 if (opcode[i]==0x20) { // LB
2739 #ifdef HOST_IMM_ADDR32
2741 emit_movsbl_tlb((constmap[i][s]+offset)^3,map,tl);
2745 //emit_xorimm(addr,3,tl);
2746 //gen_tlb_addr_r(tl,map);
2747 //emit_movsbl_indexed((int)rdram-0x80000000,tl,tl);
2749 if(!c) emit_xorimm(addr,3,tl);
2750 else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2751 emit_movsbl_indexed_tlb(x,tl,map,tl);
2754 add_stub(LOADB_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2757 inline_readstub(LOADB_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2759 if (opcode[i]==0x21) { // LH
2761 #ifdef HOST_IMM_ADDR32
2763 emit_movswl_tlb((constmap[i][s]+offset)^2,map,tl);
2768 if(!c) emit_xorimm(addr,2,tl);
2769 else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
2771 //emit_movswl_indexed_tlb(x,tl,map,tl);
2774 gen_tlb_addr_r(tl,map);
2775 emit_movswl_indexed(x,tl,tl);
2777 emit_movswl_indexed((int)rdram-0x80000000+x,tl,tl);
2780 add_stub(LOADH_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2783 inline_readstub(LOADH_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2785 if (opcode[i]==0x23) { // LW
2787 //emit_readword_indexed((int)rdram-0x80000000,addr,tl);
2788 #ifdef HOST_IMM_ADDR32
2790 emit_readword_tlb(constmap[i][s]+offset,map,tl);
2793 emit_readword_indexed_tlb(0,addr,map,tl);
2795 add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2798 inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2800 if (opcode[i]==0x24) { // LBU
2802 #ifdef HOST_IMM_ADDR32
2804 emit_movzbl_tlb((constmap[i][s]+offset)^3,map,tl);
2808 //emit_xorimm(addr,3,tl);
2809 //gen_tlb_addr_r(tl,map);
2810 //emit_movzbl_indexed((int)rdram-0x80000000,tl,tl);
2812 if(!c) emit_xorimm(addr,3,tl);
2813 else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2814 emit_movzbl_indexed_tlb(x,tl,map,tl);
2817 add_stub(LOADBU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2820 inline_readstub(LOADBU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2822 if (opcode[i]==0x25) { // LHU
2824 #ifdef HOST_IMM_ADDR32
2826 emit_movzwl_tlb((constmap[i][s]+offset)^2,map,tl);
2831 if(!c) emit_xorimm(addr,2,tl);
2832 else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
2834 //emit_movzwl_indexed_tlb(x,tl,map,tl);
2837 gen_tlb_addr_r(tl,map);
2838 emit_movzwl_indexed(x,tl,tl);
2840 emit_movzwl_indexed((int)rdram-0x80000000+x,tl,tl);
2842 add_stub(LOADHU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2846 inline_readstub(LOADHU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2848 if (opcode[i]==0x27) { // LWU
2851 //emit_readword_indexed((int)rdram-0x80000000,addr,tl);
2852 #ifdef HOST_IMM_ADDR32
2854 emit_readword_tlb(constmap[i][s]+offset,map,tl);
2857 emit_readword_indexed_tlb(0,addr,map,tl);
2859 add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2862 inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2866 if (opcode[i]==0x37) { // LD
2868 //gen_tlb_addr_r(tl,map);
2869 //if(th>=0) emit_readword_indexed((int)rdram-0x80000000,addr,th);
2870 //emit_readword_indexed((int)rdram-0x7FFFFFFC,addr,tl);
2871 #ifdef HOST_IMM_ADDR32
2873 emit_readdword_tlb(constmap[i][s]+offset,map,th,tl);
2876 emit_readdword_indexed_tlb(0,addr,map,th,tl);
2878 add_stub(LOADD_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2881 inline_readstub(LOADD_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2883 //emit_storereg(rt1[i],tl); // DEBUG
2885 //if(opcode[i]==0x23)
2886 //if(opcode[i]==0x24)
2887 //if(opcode[i]==0x23||opcode[i]==0x24)
2888 /*if(opcode[i]==0x21||opcode[i]==0x23||opcode[i]==0x24)
2892 emit_readword((int)&last_count,ECX);
2894 if(get_reg(i_regs->regmap,CCREG)<0)
2895 emit_loadreg(CCREG,HOST_CCREG);
2896 emit_add(HOST_CCREG,ECX,HOST_CCREG);
2897 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
2898 emit_writeword(HOST_CCREG,(int)&Count);
2901 if(get_reg(i_regs->regmap,CCREG)<0)
2902 emit_loadreg(CCREG,0);
2904 emit_mov(HOST_CCREG,0);
2906 emit_addimm(0,2*ccadj[i],0);
2907 emit_writeword(0,(int)&Count);
2909 emit_call((int)memdebug);
2911 restore_regs(0x100f);
2915 #ifndef loadlr_assemble
2916 void loadlr_assemble(int i,struct regstat *i_regs)
2918 printf("Need loadlr_assemble for this architecture.\n");
2923 void store_assemble(int i,struct regstat *i_regs)
2928 int jaddr=0,jaddr2,type;
2930 int agr=AGEN1+(i&1);
2932 th=get_reg(i_regs->regmap,rs2[i]|64);
2933 tl=get_reg(i_regs->regmap,rs2[i]);
2934 s=get_reg(i_regs->regmap,rs1[i]);
2935 temp=get_reg(i_regs->regmap,agr);
2936 if(temp<0) temp=get_reg(i_regs->regmap,-1);
2939 c=(i_regs->wasconst>>s)&1;
2940 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80800000;
2941 if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
2945 for(hr=0;hr<HOST_REGS;hr++) {
2946 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
2948 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
2949 if(offset||s<0||c) addr=temp;
2954 // Strmnnrmn's speed hack
2956 if(rs1[i]!=29||start<0x80001000||start>=0x80800000)
2958 emit_cmpimm(addr,0x800000);
2959 #ifdef DESTRUCTIVE_SHIFT
2960 if(s==addr) emit_mov(s,temp);
2963 if(rs1[i]!=29||start<0x80001000||start>=0x80800000)
2967 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
2968 // Hint to branch predictor that the branch is unlikely to be taken
2970 emit_jno_unlikely(0);
2978 if (opcode[i]==0x28) x=3; // SB
2979 if (opcode[i]==0x29) x=2; // SH
2980 map=get_reg(i_regs->regmap,TLREG);
2982 map=do_tlb_w(addr,temp,map,x,c,constmap[i][s]+offset);
2983 do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr);
2986 if (opcode[i]==0x28) { // SB
2989 if(!c) emit_xorimm(addr,3,temp);
2990 else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2991 //gen_tlb_addr_w(temp,map);
2992 //emit_writebyte_indexed(tl,(int)rdram-0x80000000,temp);
2993 emit_writebyte_indexed_tlb(tl,x,temp,map,temp);
2997 if (opcode[i]==0x29) { // SH
3000 if(!c) emit_xorimm(addr,2,temp);
3001 else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
3003 //emit_writehword_indexed_tlb(tl,x,temp,map,temp);
3006 gen_tlb_addr_w(temp,map);
3007 emit_writehword_indexed(tl,x,temp);
3009 emit_writehword_indexed(tl,(int)rdram-0x80000000+x,temp);
3013 if (opcode[i]==0x2B) { // SW
3015 //emit_writeword_indexed(tl,(int)rdram-0x80000000,addr);
3016 emit_writeword_indexed_tlb(tl,0,addr,map,temp);
3019 if (opcode[i]==0x3F) { // SD
3023 //emit_writeword_indexed(th,(int)rdram-0x80000000,addr);
3024 //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,addr);
3025 emit_writedword_indexed_tlb(th,tl,0,addr,map,temp);
3028 //emit_writeword_indexed(tl,(int)rdram-0x80000000,temp);
3029 //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,temp);
3030 emit_writedword_indexed_tlb(tl,tl,0,addr,map,temp);
3036 add_stub(type,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3037 } else if(!memtarget) {
3038 inline_writestub(type,i,constmap[i][s]+offset,i_regs->regmap,rs2[i],ccadj[i],reglist);
3042 #ifdef DESTRUCTIVE_SHIFT
3043 // The x86 shift operation is 'destructive'; it overwrites the
3044 // source register, so we need to make a copy first and use that.
3047 #if defined(HOST_IMM8)
3048 int ir=get_reg(i_regs->regmap,INVCP);
3050 emit_cmpmem_indexedsr12_reg(ir,addr,1);
3052 emit_cmpmem_indexedsr12_imm((int)invalid_code,addr,1);
3056 add_stub(INVCODE_STUB,jaddr2,(int)out,reglist|(1<<HOST_CCREG),addr,0,0,0);
3059 //if(opcode[i]==0x2B || opcode[i]==0x3F)
3060 //if(opcode[i]==0x2B || opcode[i]==0x28)
3061 //if(opcode[i]==0x2B || opcode[i]==0x29)
3062 //if(opcode[i]==0x2B)
3063 /*if(opcode[i]==0x2B || opcode[i]==0x28 || opcode[i]==0x29 || opcode[i]==0x3F)
3067 emit_readword((int)&last_count,ECX);
3069 if(get_reg(i_regs->regmap,CCREG)<0)
3070 emit_loadreg(CCREG,HOST_CCREG);
3071 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3072 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3073 emit_writeword(HOST_CCREG,(int)&Count);
3076 if(get_reg(i_regs->regmap,CCREG)<0)
3077 emit_loadreg(CCREG,0);
3079 emit_mov(HOST_CCREG,0);
3081 emit_addimm(0,2*ccadj[i],0);
3082 emit_writeword(0,(int)&Count);
3084 emit_call((int)memdebug);
3086 restore_regs(0x100f);
3090 void storelr_assemble(int i,struct regstat *i_regs)
3097 int case1,case2,case3;
3098 int done0,done1,done2;
3101 th=get_reg(i_regs->regmap,rs2[i]|64);
3102 tl=get_reg(i_regs->regmap,rs2[i]);
3103 s=get_reg(i_regs->regmap,rs1[i]);
3104 temp=get_reg(i_regs->regmap,-1);
3107 c=(i_regs->isconst>>s)&1;
3108 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80800000;
3109 if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
3112 for(hr=0;hr<HOST_REGS;hr++) {
3113 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3119 emit_cmpimm(s<0||offset?temp:s,0x800000);
3120 if(!offset&&s!=temp) emit_mov(s,temp);
3126 if(!memtarget||!rs1[i]) {
3131 if((u_int)rdram!=0x80000000)
3132 emit_addimm_no_flags((u_int)rdram-(u_int)0x80000000,temp);
3134 int map=get_reg(i_regs->regmap,TLREG);
3136 map=do_tlb_w(c||s<0||offset?temp:s,temp,map,0,c,constmap[i][s]+offset);
3137 if(!c&&!offset&&s>=0) emit_mov(s,temp);
3138 do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr);
3139 if(!jaddr&&!memtarget) {
3143 gen_tlb_addr_w(temp,map);
3146 if (opcode[i]==0x2C||opcode[i]==0x2D) { // SDL/SDR
3147 temp2=get_reg(i_regs->regmap,FTEMP);
3148 if(!rs2[i]) temp2=th=tl;
3151 emit_testimm(temp,2);
3154 emit_testimm(temp,1);
3158 if (opcode[i]==0x2A) { // SWL
3159 emit_writeword_indexed(tl,0,temp);
3161 if (opcode[i]==0x2E) { // SWR
3162 emit_writebyte_indexed(tl,3,temp);
3164 if (opcode[i]==0x2C) { // SDL
3165 emit_writeword_indexed(th,0,temp);
3166 if(rs2[i]) emit_mov(tl,temp2);
3168 if (opcode[i]==0x2D) { // SDR
3169 emit_writebyte_indexed(tl,3,temp);
3170 if(rs2[i]) emit_shldimm(th,tl,24,temp2);
3175 set_jump_target(case1,(int)out);
3176 if (opcode[i]==0x2A) { // SWL
3177 // Write 3 msb into three least significant bytes
3178 if(rs2[i]) emit_rorimm(tl,8,tl);
3179 emit_writehword_indexed(tl,-1,temp);
3180 if(rs2[i]) emit_rorimm(tl,16,tl);
3181 emit_writebyte_indexed(tl,1,temp);
3182 if(rs2[i]) emit_rorimm(tl,8,tl);
3184 if (opcode[i]==0x2E) { // SWR
3185 // Write two lsb into two most significant bytes
3186 emit_writehword_indexed(tl,1,temp);
3188 if (opcode[i]==0x2C) { // SDL
3189 if(rs2[i]) emit_shrdimm(tl,th,8,temp2);
3190 // Write 3 msb into three least significant bytes
3191 if(rs2[i]) emit_rorimm(th,8,th);
3192 emit_writehword_indexed(th,-1,temp);
3193 if(rs2[i]) emit_rorimm(th,16,th);
3194 emit_writebyte_indexed(th,1,temp);
3195 if(rs2[i]) emit_rorimm(th,8,th);
3197 if (opcode[i]==0x2D) { // SDR
3198 if(rs2[i]) emit_shldimm(th,tl,16,temp2);
3199 // Write two lsb into two most significant bytes
3200 emit_writehword_indexed(tl,1,temp);
3205 set_jump_target(case2,(int)out);
3206 emit_testimm(temp,1);
3209 if (opcode[i]==0x2A) { // SWL
3210 // Write two msb into two least significant bytes
3211 if(rs2[i]) emit_rorimm(tl,16,tl);
3212 emit_writehword_indexed(tl,-2,temp);
3213 if(rs2[i]) emit_rorimm(tl,16,tl);
3215 if (opcode[i]==0x2E) { // SWR
3216 // Write 3 lsb into three most significant bytes
3217 emit_writebyte_indexed(tl,-1,temp);
3218 if(rs2[i]) emit_rorimm(tl,8,tl);
3219 emit_writehword_indexed(tl,0,temp);
3220 if(rs2[i]) emit_rorimm(tl,24,tl);
3222 if (opcode[i]==0x2C) { // SDL
3223 if(rs2[i]) emit_shrdimm(tl,th,16,temp2);
3224 // Write two msb into two least significant bytes
3225 if(rs2[i]) emit_rorimm(th,16,th);
3226 emit_writehword_indexed(th,-2,temp);
3227 if(rs2[i]) emit_rorimm(th,16,th);
3229 if (opcode[i]==0x2D) { // SDR
3230 if(rs2[i]) emit_shldimm(th,tl,8,temp2);
3231 // Write 3 lsb into three most significant bytes
3232 emit_writebyte_indexed(tl,-1,temp);
3233 if(rs2[i]) emit_rorimm(tl,8,tl);
3234 emit_writehword_indexed(tl,0,temp);
3235 if(rs2[i]) emit_rorimm(tl,24,tl);
3240 set_jump_target(case3,(int)out);
3241 if (opcode[i]==0x2A) { // SWL
3242 // Write msb into least significant byte
3243 if(rs2[i]) emit_rorimm(tl,24,tl);
3244 emit_writebyte_indexed(tl,-3,temp);
3245 if(rs2[i]) emit_rorimm(tl,8,tl);
3247 if (opcode[i]==0x2E) { // SWR
3248 // Write entire word
3249 emit_writeword_indexed(tl,-3,temp);
3251 if (opcode[i]==0x2C) { // SDL
3252 if(rs2[i]) emit_shrdimm(tl,th,24,temp2);
3253 // Write msb into least significant byte
3254 if(rs2[i]) emit_rorimm(th,24,th);
3255 emit_writebyte_indexed(th,-3,temp);
3256 if(rs2[i]) emit_rorimm(th,8,th);
3258 if (opcode[i]==0x2D) { // SDR
3259 if(rs2[i]) emit_mov(th,temp2);
3260 // Write entire word
3261 emit_writeword_indexed(tl,-3,temp);
3263 set_jump_target(done0,(int)out);
3264 set_jump_target(done1,(int)out);
3265 set_jump_target(done2,(int)out);
3266 if (opcode[i]==0x2C) { // SDL
3267 emit_testimm(temp,4);
3270 emit_andimm(temp,~3,temp);
3271 emit_writeword_indexed(temp2,4,temp);
3272 set_jump_target(done0,(int)out);
3274 if (opcode[i]==0x2D) { // SDR
3275 emit_testimm(temp,4);
3278 emit_andimm(temp,~3,temp);
3279 emit_writeword_indexed(temp2,-4,temp);
3280 set_jump_target(done0,(int)out);
3283 add_stub(STORELR_STUB,jaddr,(int)out,0,(int)i_regs,rs2[i],ccadj[i],reglist);
3286 emit_addimm_no_flags((u_int)0x80000000-(u_int)rdram,temp);
3287 #if defined(HOST_IMM8)
3288 int ir=get_reg(i_regs->regmap,INVCP);
3290 emit_cmpmem_indexedsr12_reg(ir,temp,1);
3292 emit_cmpmem_indexedsr12_imm((int)invalid_code,temp,1);
3296 add_stub(INVCODE_STUB,jaddr2,(int)out,reglist|(1<<HOST_CCREG),temp,0,0,0);
3300 //save_regs(0x100f);
3301 emit_readword((int)&last_count,ECX);
3302 if(get_reg(i_regs->regmap,CCREG)<0)
3303 emit_loadreg(CCREG,HOST_CCREG);
3304 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3305 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3306 emit_writeword(HOST_CCREG,(int)&Count);
3307 emit_call((int)memdebug);
3309 //restore_regs(0x100f);
3313 void c1ls_assemble(int i,struct regstat *i_regs)
3315 #ifndef DISABLE_COP1
3321 int jaddr,jaddr2=0,jaddr3,type;
3322 int agr=AGEN1+(i&1);
3324 th=get_reg(i_regs->regmap,FTEMP|64);
3325 tl=get_reg(i_regs->regmap,FTEMP);
3326 s=get_reg(i_regs->regmap,rs1[i]);
3327 temp=get_reg(i_regs->regmap,agr);
3328 if(temp<0) temp=get_reg(i_regs->regmap,-1);
3333 for(hr=0;hr<HOST_REGS;hr++) {
3334 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3336 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
3337 if (opcode[i]==0x31||opcode[i]==0x35) // LWC1/LDC1
3339 // Loads use a temporary register which we need to save
3342 if (opcode[i]==0x39||opcode[i]==0x3D) // SWC1/SDC1
3346 //if(s<0) emit_loadreg(rs1[i],ar); //address_generation does this now
3347 //else c=(i_regs->wasconst>>s)&1;
3348 if(s>=0) c=(i_regs->wasconst>>s)&1;
3349 // Check cop1 unusable
3351 signed char rs=get_reg(i_regs->regmap,CSREG);
3353 emit_testimm(rs,0x20000000);
3356 add_stub(FP_STUB,jaddr,(int)out,i,rs,(int)i_regs,is_delayslot,0);
3359 if (opcode[i]==0x39) { // SWC1 (get float address)
3360 emit_readword((int)®_cop1_simple[(source[i]>>16)&0x1f],tl);
3362 if (opcode[i]==0x3D) { // SDC1 (get double address)
3363 emit_readword((int)®_cop1_double[(source[i]>>16)&0x1f],tl);
3365 // Generate address + offset
3368 emit_cmpimm(offset||c||s<0?ar:s,0x800000);
3372 map=get_reg(i_regs->regmap,TLREG);
3374 if (opcode[i]==0x31||opcode[i]==0x35) { // LWC1/LDC1
3375 map=do_tlb_r(offset||c||s<0?ar:s,ar,map,0,-1,-1,c,constmap[i][s]+offset);
3377 if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3378 map=do_tlb_w(offset||c||s<0?ar:s,ar,map,0,c,constmap[i][s]+offset);
3381 if (opcode[i]==0x39) { // SWC1 (read float)
3382 emit_readword_indexed(0,tl,tl);
3384 if (opcode[i]==0x3D) { // SDC1 (read double)
3385 emit_readword_indexed(4,tl,th);
3386 emit_readword_indexed(0,tl,tl);
3388 if (opcode[i]==0x31) { // LWC1 (get target address)
3389 emit_readword((int)®_cop1_simple[(source[i]>>16)&0x1f],temp);
3391 if (opcode[i]==0x35) { // LDC1 (get target address)
3392 emit_readword((int)®_cop1_double[(source[i]>>16)&0x1f],temp);
3399 else if(((signed int)(constmap[i][s]+offset))>=(signed int)0x80800000) {
3401 emit_jmp(0); // inline_readstub/inline_writestub? Very rare case
3403 #ifdef DESTRUCTIVE_SHIFT
3404 if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3405 if(!offset&&!c&&s>=0) emit_mov(s,ar);
3409 if (opcode[i]==0x31||opcode[i]==0x35) { // LWC1/LDC1
3410 do_tlb_r_branch(map,c,constmap[i][s]+offset,&jaddr2);
3412 if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3413 do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr2);
3416 if (opcode[i]==0x31) { // LWC1
3417 //if(s>=0&&!c&&!offset) emit_mov(s,tl);
3418 //gen_tlb_addr_r(ar,map);
3419 //emit_readword_indexed((int)rdram-0x80000000,tl,tl);
3420 #ifdef HOST_IMM_ADDR32
3421 if(c) emit_readword_tlb(constmap[i][s]+offset,map,tl);
3424 emit_readword_indexed_tlb(0,offset||c||s<0?tl:s,map,tl);
3427 if (opcode[i]==0x35) { // LDC1
3429 //if(s>=0&&!c&&!offset) emit_mov(s,tl);
3430 //gen_tlb_addr_r(ar,map);
3431 //emit_readword_indexed((int)rdram-0x80000000,tl,th);
3432 //emit_readword_indexed((int)rdram-0x7FFFFFFC,tl,tl);
3433 #ifdef HOST_IMM_ADDR32
3434 if(c) emit_readdword_tlb(constmap[i][s]+offset,map,th,tl);
3437 emit_readdword_indexed_tlb(0,offset||c||s<0?tl:s,map,th,tl);
3440 if (opcode[i]==0x39) { // SWC1
3441 //emit_writeword_indexed(tl,(int)rdram-0x80000000,temp);
3442 emit_writeword_indexed_tlb(tl,0,offset||c||s<0?temp:s,map,temp);
3445 if (opcode[i]==0x3D) { // SDC1
3447 //emit_writeword_indexed(th,(int)rdram-0x80000000,temp);
3448 //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,temp);
3449 emit_writedword_indexed_tlb(th,tl,0,offset||c||s<0?temp:s,map,temp);
3453 if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3454 #ifndef DESTRUCTIVE_SHIFT
3455 temp=offset||c||s<0?ar:s;
3457 #if defined(HOST_IMM8)
3458 int ir=get_reg(i_regs->regmap,INVCP);
3460 emit_cmpmem_indexedsr12_reg(ir,temp,1);
3462 emit_cmpmem_indexedsr12_imm((int)invalid_code,temp,1);
3466 add_stub(INVCODE_STUB,jaddr3,(int)out,reglist|(1<<HOST_CCREG),temp,0,0,0);
3469 if(jaddr2) add_stub(type,jaddr2,(int)out,i,offset||c||s<0?ar:s,(int)i_regs,ccadj[i],reglist);
3470 if (opcode[i]==0x31) { // LWC1 (write float)
3471 emit_writeword_indexed(tl,0,temp);
3473 if (opcode[i]==0x35) { // LDC1 (write double)
3474 emit_writeword_indexed(th,4,temp);
3475 emit_writeword_indexed(tl,0,temp);
3477 //if(opcode[i]==0x39)
3478 /*if(opcode[i]==0x39||opcode[i]==0x31)
3481 emit_readword((int)&last_count,ECX);
3482 if(get_reg(i_regs->regmap,CCREG)<0)
3483 emit_loadreg(CCREG,HOST_CCREG);
3484 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3485 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3486 emit_writeword(HOST_CCREG,(int)&Count);
3487 emit_call((int)memdebug);
3491 cop1_unusable(i, i_regs);
3495 #ifndef multdiv_assemble
3496 void multdiv_assemble(int i,struct regstat *i_regs)
3498 printf("Need multdiv_assemble for this architecture.\n");
3503 void mov_assemble(int i,struct regstat *i_regs)
3505 //if(opcode2[i]==0x10||opcode2[i]==0x12) { // MFHI/MFLO
3506 //if(opcode2[i]==0x11||opcode2[i]==0x13) { // MTHI/MTLO
3509 signed char sh,sl,th,tl;
3510 th=get_reg(i_regs->regmap,rt1[i]|64);
3511 tl=get_reg(i_regs->regmap,rt1[i]);
3514 sh=get_reg(i_regs->regmap,rs1[i]|64);
3515 sl=get_reg(i_regs->regmap,rs1[i]);
3516 if(sl>=0) emit_mov(sl,tl);
3517 else emit_loadreg(rs1[i],tl);
3519 if(sh>=0) emit_mov(sh,th);
3520 else emit_loadreg(rs1[i]|64,th);
3526 #ifndef fconv_assemble
3527 void fconv_assemble(int i,struct regstat *i_regs)
3529 printf("Need fconv_assemble for this architecture.\n");
3535 void float_assemble(int i,struct regstat *i_regs)
3537 printf("Need float_assemble for this architecture.\n");
3542 void syscall_assemble(int i,struct regstat *i_regs)
3544 signed char ccreg=get_reg(i_regs->regmap,CCREG);
3545 assert(ccreg==HOST_CCREG);
3546 assert(!is_delayslot);
3547 emit_movimm(start+i*4,EAX); // Get PC
3548 emit_addimm(HOST_CCREG,CLOCK_DIVIDER*ccadj[i],HOST_CCREG); // CHECK: is this right? There should probably be an extra cycle...
3549 emit_jmp((int)jump_syscall);
3552 void ds_assemble(int i,struct regstat *i_regs)
3557 alu_assemble(i,i_regs);break;
3559 imm16_assemble(i,i_regs);break;
3561 shift_assemble(i,i_regs);break;
3563 shiftimm_assemble(i,i_regs);break;
3565 load_assemble(i,i_regs);break;
3567 loadlr_assemble(i,i_regs);break;
3569 store_assemble(i,i_regs);break;
3571 storelr_assemble(i,i_regs);break;
3573 cop0_assemble(i,i_regs);break;
3575 cop1_assemble(i,i_regs);break;
3577 c1ls_assemble(i,i_regs);break;
3579 fconv_assemble(i,i_regs);break;
3581 float_assemble(i,i_regs);break;
3583 fcomp_assemble(i,i_regs);break;
3585 multdiv_assemble(i,i_regs);break;
3587 mov_assemble(i,i_regs);break;
3595 printf("Jump in the delay slot. This is probably a bug.\n");
3600 // Is the branch target a valid internal jump?
3601 int internal_branch(uint64_t i_is32,int addr)
3603 if(addr&1) return 0; // Indirect (register) jump
3604 if(addr>=start && addr<start+slen*4-4)
3606 int t=(addr-start)>>2;
3607 // Delay slots are not valid branch targets
3608 //if(t>0&&(itype[t-1]==RJUMP||itype[t-1]==UJUMP||itype[t-1]==CJUMP||itype[t-1]==SJUMP||itype[t-1]==FJUMP)) return 0;
3609 // 64 -> 32 bit transition requires a recompile
3610 /*if(is32[t]&~unneeded_reg_upper[t]&~i_is32)
3612 if(requires_32bit[t]&~i_is32) printf("optimizable: no\n");
3613 else printf("optimizable: yes\n");
3615 //if(is32[t]&~unneeded_reg_upper[t]&~i_is32) return 0;
3616 if(requires_32bit[t]&~i_is32) return 0;
3622 #ifndef wb_invalidate
3623 void wb_invalidate(signed char pre[],signed char entry[],uint64_t dirty,uint64_t is32,
3624 uint64_t u,uint64_t uu)
3627 for(hr=0;hr<HOST_REGS;hr++) {
3628 if(hr!=EXCLUDE_REG) {
3629 if(pre[hr]!=entry[hr]) {
3632 if(get_reg(entry,pre[hr])<0) {
3634 if(!((u>>pre[hr])&1)) {
3635 emit_storereg(pre[hr],hr);
3636 if( ((is32>>pre[hr])&1) && !((uu>>pre[hr])&1) ) {
3637 emit_sarimm(hr,31,hr);
3638 emit_storereg(pre[hr]|64,hr);
3642 if(!((uu>>(pre[hr]&63))&1) && !((is32>>(pre[hr]&63))&1)) {
3643 emit_storereg(pre[hr],hr);
3652 // Move from one register to another (no writeback)
3653 for(hr=0;hr<HOST_REGS;hr++) {
3654 if(hr!=EXCLUDE_REG) {
3655 if(pre[hr]!=entry[hr]) {
3656 if(pre[hr]>=0&&(pre[hr]&63)<TEMPREG) {
3658 if((nr=get_reg(entry,pre[hr]))>=0) {
3668 // Load the specified registers
3669 // This only loads the registers given as arguments because
3670 // we don't want to load things that will be overwritten
3671 void load_regs(signed char entry[],signed char regmap[],int is32,int rs1,int rs2)
3675 for(hr=0;hr<HOST_REGS;hr++) {
3676 if(hr!=EXCLUDE_REG&®map[hr]>=0) {
3677 if(entry[hr]!=regmap[hr]) {
3678 if(regmap[hr]==rs1||regmap[hr]==rs2)
3685 emit_loadreg(regmap[hr],hr);
3692 for(hr=0;hr<HOST_REGS;hr++) {
3693 if(hr!=EXCLUDE_REG&®map[hr]>=0) {
3694 if(entry[hr]!=regmap[hr]) {
3695 if(regmap[hr]-64==rs1||regmap[hr]-64==rs2)
3697 assert(regmap[hr]!=64);
3698 if((is32>>(regmap[hr]&63))&1) {
3699 int lr=get_reg(regmap,regmap[hr]-64);
3701 emit_sarimm(lr,31,hr);
3703 emit_loadreg(regmap[hr],hr);
3707 emit_loadreg(regmap[hr],hr);
3715 // Load registers prior to the start of a loop
3716 // so that they are not loaded within the loop
3717 static void loop_preload(signed char pre[],signed char entry[])
3720 for(hr=0;hr<HOST_REGS;hr++) {
3721 if(hr!=EXCLUDE_REG) {
3722 if(pre[hr]!=entry[hr]) {
3724 if(get_reg(pre,entry[hr])<0) {
3725 assem_debug("loop preload:\n");
3726 //printf("loop preload: %d\n",hr);
3730 else if(entry[hr]<TEMPREG)
3732 emit_loadreg(entry[hr],hr);
3734 else if(entry[hr]-64<TEMPREG)
3736 emit_loadreg(entry[hr],hr);
3745 // Generate address for load/store instruction
3746 void address_generation(int i,struct regstat *i_regs,signed char entry[])
3748 if(itype[i]==LOAD||itype[i]==LOADLR||itype[i]==STORE||itype[i]==STORELR||itype[i]==C1LS) {
3750 int agr=AGEN1+(i&1);
3751 int mgr=MGEN1+(i&1);
3752 if(itype[i]==LOAD) {
3753 ra=get_reg(i_regs->regmap,rt1[i]);
3754 //if(rt1[i]) assert(ra>=0);
3756 if(itype[i]==LOADLR) {
3757 ra=get_reg(i_regs->regmap,FTEMP);
3759 if(itype[i]==STORE||itype[i]==STORELR) {
3760 ra=get_reg(i_regs->regmap,agr);
3761 if(ra<0) ra=get_reg(i_regs->regmap,-1);
3763 if(itype[i]==C1LS) {
3764 if (opcode[i]==0x31||opcode[i]==0x35) // LWC1/LDC1
3765 ra=get_reg(i_regs->regmap,FTEMP);
3767 ra=get_reg(i_regs->regmap,agr);
3768 if(ra<0) ra=get_reg(i_regs->regmap,-1);
3771 int rs=get_reg(i_regs->regmap,rs1[i]);
3772 int rm=get_reg(i_regs->regmap,TLREG);
3775 int c=(i_regs->wasconst>>rs)&1;
3777 // Using r0 as a base address
3779 if(!entry||entry[rm]!=mgr) {
3780 generate_map_const(offset,rm);
3781 } // else did it in the previous cycle
3783 if(!entry||entry[ra]!=agr) {
3784 if (opcode[i]==0x22||opcode[i]==0x26) {
3785 emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR
3786 }else if (opcode[i]==0x1a||opcode[i]==0x1b) {
3787 emit_movimm(offset&0xFFFFFFF8,ra); // LDL/LDR
3789 emit_movimm(offset,ra);
3791 } // else did it in the previous cycle
3794 if(!entry||entry[ra]!=rs1[i])
3795 emit_loadreg(rs1[i],ra);
3796 //if(!entry||entry[ra]!=rs1[i])
3797 // printf("poor load scheduling!\n");
3801 if(!entry||entry[rm]!=mgr) {
3802 if(itype[i]==STORE||itype[i]==STORELR||opcode[i]==0x39||opcode[i]==0x3D) {
3803 // Stores to memory go thru the mapper to detect self-modifying
3804 // code, loads don't.
3805 if((unsigned int)(constmap[i][rs]+offset)>=0xC0000000 ||
3806 (unsigned int)(constmap[i][rs]+offset)<0x80800000 )
3807 generate_map_const(constmap[i][rs]+offset,rm);
3809 if((signed int)(constmap[i][rs]+offset)>=(signed int)0xC0000000)
3810 generate_map_const(constmap[i][rs]+offset,rm);
3814 if(rs1[i]!=rt1[i]||itype[i]!=LOAD) {
3815 if(!entry||entry[ra]!=agr) {
3816 if (opcode[i]==0x22||opcode[i]==0x26) {
3817 emit_movimm((constmap[i][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR
3818 }else if (opcode[i]==0x1a||opcode[i]==0x1b) {
3819 emit_movimm((constmap[i][rs]+offset)&0xFFFFFFF8,ra); // LDL/LDR
3821 #ifdef HOST_IMM_ADDR32
3822 if((itype[i]!=LOAD&&opcode[i]!=0x31&&opcode[i]!=0x35) ||
3823 (using_tlb&&((signed int)constmap[i][rs]+offset)>=(signed int)0xC0000000))
3825 emit_movimm(constmap[i][rs]+offset,ra);
3827 } // else did it in the previous cycle
3828 } // else load_consts already did it
3830 if(offset&&!c&&rs1[i]) {
3832 emit_addimm(rs,offset,ra);
3834 emit_addimm(ra,offset,ra);
3839 // Preload constants for next instruction
3840 if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS) {
3842 #ifndef HOST_IMM_ADDR32
3844 agr=MGEN1+((i+1)&1);
3845 ra=get_reg(i_regs->regmap,agr);
3847 int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
3848 int offset=imm[i+1];
3849 int c=(regs[i+1].wasconst>>rs)&1;
3851 if(itype[i+1]==STORE||itype[i+1]==STORELR||opcode[i+1]==0x39||opcode[i+1]==0x3D) {
3852 // Stores to memory go thru the mapper to detect self-modifying
3853 // code, loads don't.
3854 if((unsigned int)(constmap[i+1][rs]+offset)>=0xC0000000 ||
3855 (unsigned int)(constmap[i+1][rs]+offset)<0x80800000 )
3856 generate_map_const(constmap[i+1][rs]+offset,ra);
3858 if((signed int)(constmap[i+1][rs]+offset)>=(signed int)0xC0000000)
3859 generate_map_const(constmap[i+1][rs]+offset,ra);
3862 /*else if(rs1[i]==0) {
3863 generate_map_const(offset,ra);
3868 agr=AGEN1+((i+1)&1);
3869 ra=get_reg(i_regs->regmap,agr);
3871 int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
3872 int offset=imm[i+1];
3873 int c=(regs[i+1].wasconst>>rs)&1;
3874 if(c&&(rs1[i+1]!=rt1[i+1]||itype[i+1]!=LOAD)) {
3875 if (opcode[i+1]==0x22||opcode[i+1]==0x26) {
3876 emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR
3877 }else if (opcode[i+1]==0x1a||opcode[i+1]==0x1b) {
3878 emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFF8,ra); // LDL/LDR
3880 #ifdef HOST_IMM_ADDR32
3881 if((itype[i+1]!=LOAD&&opcode[i+1]!=0x31&&opcode[i+1]!=0x35) ||
3882 (using_tlb&&((signed int)constmap[i+1][rs]+offset)>=(signed int)0xC0000000))
3884 emit_movimm(constmap[i+1][rs]+offset,ra);
3887 else if(rs1[i+1]==0) {
3888 // Using r0 as a base address
3889 if (opcode[i+1]==0x22||opcode[i+1]==0x26) {
3890 emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR
3891 }else if (opcode[i+1]==0x1a||opcode[i+1]==0x1b) {
3892 emit_movimm(offset&0xFFFFFFF8,ra); // LDL/LDR
3894 emit_movimm(offset,ra);
3901 int get_final_value(int hr, int i, int *value)
3903 int reg=regs[i].regmap[hr];
3905 if(regs[i+1].regmap[hr]!=reg) break;
3906 if(!((regs[i+1].isconst>>hr)&1)) break;
3911 if(itype[i]==UJUMP||itype[i]==RJUMP||itype[i]==CJUMP||itype[i]==SJUMP) {