libpcsxcore/new_dynarec/new_dynarec.c

   1 /* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
   2  *   Mupen64plus - new_dynarec.c                                           *
   3  *   Copyright (C) 2009-2010 Ari64                                         *
   4  *                                                                         *
   5  *   This program is free software; you can redistribute it and/or modify  *
   6  *   it under the terms of the GNU General Public License as published by  *
   7  *   the Free Software Foundation; either version 2 of the License, or     *
   8  *   (at your option) any later version.                                   *
   9  *                                                                         *
  10  *   This program is distributed in the hope that it will be useful,       *
  11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  13  *   GNU General Public License for more details.                          *
  14  *                                                                         *
  15  *   You should have received a copy of the GNU General Public License     *
  16  *   along with this program; if not, write to the                         *
  17  *   Free Software Foundation, Inc.,                                       *
  18  *   51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.          *
  19  * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
  20
  21 #include <stdlib.h>
  22 #include <stdint.h> //include for uint64_t
  23 #include <assert.h>
  24
  25 #include "emu_if.h" //emulator interface
  26
  27 #include <sys/mman.h>
  28
  29 #ifdef __i386__
  30 #include "assem_x86.h"
  31 #endif
  32 #ifdef __x86_64__
  33 #include "assem_x64.h"
  34 #endif
  35 #ifdef __arm__
  36 #include "assem_arm.h"
  37 #endif
  38
  39 #define MAXBLOCK 4096
  40 #define MAX_OUTPUT_BLOCK_SIZE 262144
  41 #define CLOCK_DIVIDER 2
  42
  43 struct regstat
  44 {
  45   signed char regmap_entry[HOST_REGS];
  46   signed char regmap[HOST_REGS];
  47   uint64_t was32;
  48   uint64_t is32;
  49   uint64_t wasdirty;
  50   uint64_t dirty;
  51   uint64_t u;
  52   uint64_t uu;
  53   u_int wasconst;
  54   u_int isconst;
  55   uint64_t constmap[HOST_REGS];
  56 };
  57
  58 struct ll_entry
  59 {
  60   u_int vaddr;
  61   u_int reg32;
  62   void *addr;
  63   struct ll_entry *next;
  64 };
  65
  66   u_int start;
  67   u_int *source;
  68   u_int pagelimit;
  69   char insn[MAXBLOCK][10];
  70   u_char itype[MAXBLOCK];
  71   u_char opcode[MAXBLOCK];
  72   u_char opcode2[MAXBLOCK];
  73   u_char bt[MAXBLOCK];
  74   u_char rs1[MAXBLOCK];
  75   u_char rs2[MAXBLOCK];
  76   u_char rt1[MAXBLOCK];
  77   u_char rt2[MAXBLOCK];
  78   u_char us1[MAXBLOCK];
  79   u_char us2[MAXBLOCK];
  80   u_char dep1[MAXBLOCK];
  81   u_char dep2[MAXBLOCK];
  82   u_char lt1[MAXBLOCK];
  83   int imm[MAXBLOCK];
  84   u_int ba[MAXBLOCK];
  85   char likely[MAXBLOCK];
  86   char is_ds[MAXBLOCK];
  87   uint64_t unneeded_reg[MAXBLOCK];
  88   uint64_t unneeded_reg_upper[MAXBLOCK];
  89   uint64_t branch_unneeded_reg[MAXBLOCK];
  90   uint64_t branch_unneeded_reg_upper[MAXBLOCK];
  91   uint64_t p32[MAXBLOCK];
  92   uint64_t pr32[MAXBLOCK];
  93   signed char regmap_pre[MAXBLOCK][HOST_REGS];
  94   signed char regmap[MAXBLOCK][HOST_REGS];
  95   signed char regmap_entry[MAXBLOCK][HOST_REGS];
  96   uint64_t constmap[MAXBLOCK][HOST_REGS];
  97   uint64_t known_value[HOST_REGS];
  98   u_int known_reg;
  99   struct regstat regs[MAXBLOCK];
 100   struct regstat branch_regs[MAXBLOCK];
 101   u_int needed_reg[MAXBLOCK];
 102   uint64_t requires_32bit[MAXBLOCK];
 103   u_int wont_dirty[MAXBLOCK];
 104   u_int will_dirty[MAXBLOCK];
 105   int ccadj[MAXBLOCK];
 106   int slen;
 107   u_int instr_addr[MAXBLOCK];
 108   u_int link_addr[MAXBLOCK][3];
 109   int linkcount;
 110   u_int stubs[MAXBLOCK*3][8];
 111   int stubcount;
 112   u_int literals[1024][2];
 113   int literalcount;
 114   int is_delayslot;
 115   int cop1_usable;
 116   u_char *out;
 117   struct ll_entry *jump_in[4096];
 118   struct ll_entry *jump_out[4096];
 119   struct ll_entry *jump_dirty[4096];
 120   u_int hash_table[65536][4]  __attribute__((aligned(16)));
 121   char shadow[1048576]  __attribute__((aligned(16)));
 122   void *copy;
 123   int expirep;
 124   u_int using_tlb;
 125   u_int stop_after_jal;
 126   extern u_char restore_candidate[512];
 127   extern int cycle_count;
 128
 129   /* registers that may be allocated */
 130   /* 1-31 gpr */
 131 #define HIREG 32 // hi
 132 #define LOREG 33 // lo
 133 #define FSREG 34 // FPU status (FCSR)
 134 #define CSREG 35 // Coprocessor status
 135 #define CCREG 36 // Cycle count
 136 #define INVCP 37 // Pointer to invalid_code
 137 #define TEMPREG 38
 138 #define FTEMP 38 // FPU temporary register
 139 #define PTEMP 39 // Prefetch temporary register
 140 #define TLREG 40 // TLB mapping offset
 141 #define RHASH 41 // Return address hash
 142 #define RHTBL 42 // Return address hash table address
 143 #define RTEMP 43 // JR/JALR address register
 144 #define MAXREG 43
 145 #define AGEN1 44 // Address generation temporary register
 146 #define AGEN2 45 // Address generation temporary register
 147 #define MGEN1 46 // Maptable address generation temporary register
 148 #define MGEN2 47 // Maptable address generation temporary register
 149 #define BTREG 48 // Branch target temporary register
 150
 151   /* instruction types */
 152 #define NOP 0     // No operation
 153 #define LOAD 1    // Load
 154 #define STORE 2   // Store
 155 #define LOADLR 3  // Unaligned load
 156 #define STORELR 4 // Unaligned store
 157 #define MOV 5     // Move
 158 #define ALU 6     // Arithmetic/logic
 159 #define MULTDIV 7 // Multiply/divide
 160 #define SHIFT 8   // Shift by register
 161 #define SHIFTIMM 9// Shift by immediate
 162 #define IMM16 10  // 16-bit immediate
 163 #define RJUMP 11  // Unconditional jump to register
 164 #define UJUMP 12  // Unconditional jump
 165 #define CJUMP 13  // Conditional branch (BEQ/BNE/BGTZ/BLEZ)
 166 #define SJUMP 14  // Conditional branch (regimm format)
 167 #define COP0 15   // Coprocessor 0
 168 #define COP1 16   // Coprocessor 1
 169 #define C1LS 17   // Coprocessor 1 load/store
 170 #define FJUMP 18  // Conditional branch (floating point)
 171 #define FLOAT 19  // Floating point unit
 172 #define FCONV 20  // Convert integer to float
 173 #define FCOMP 21  // Floating point compare (sets FSREG)
 174 #define SYSCALL 22// SYSCALL
 175 #define OTHER 23  // Other
 176 #define SPAN 24   // Branch/delay slot spans 2 pages
 177 #define NI 25     // Not implemented
 178
 179   /* stubs */
 180 #define CC_STUB 1
 181 #define FP_STUB 2
 182 #define LOADB_STUB 3
 183 #define LOADH_STUB 4
 184 #define LOADW_STUB 5
 185 #define LOADD_STUB 6
 186 #define LOADBU_STUB 7
 187 #define LOADHU_STUB 8
 188 #define STOREB_STUB 9
 189 #define STOREH_STUB 10
 190 #define STOREW_STUB 11
 191 #define STORED_STUB 12
 192 #define STORELR_STUB 13
 193 #define INVCODE_STUB 14
 194
 195   /* branch codes */
 196 #define TAKEN 1
 197 #define NOTTAKEN 2
 198 #define NULLDS 3
 199
 200 // asm linkage
 201 int new_recompile_block(int addr);
 202 void *get_addr_ht(u_int vaddr);
 203 void invalidate_block(u_int block);
 204 void invalidate_addr(u_int addr);
 205 void remove_hash(int vaddr);
 206 void jump_vaddr();
 207 void dyna_linker();
 208 void dyna_linker_ds();
 209 void verify_code();
 210 void verify_code_vm();
 211 void verify_code_ds();
 212 void cc_interrupt();
 213 void fp_exception();
 214 void fp_exception_ds();
 215 void jump_syscall();
 216 void jump_eret();
 217
 218 // TLB
 219 void TLBWI_new();
 220 void TLBWR_new();
 221 void read_nomem_new();
 222 void read_nomemb_new();
 223 void read_nomemh_new();
 224 void read_nomemd_new();
 225 void write_nomem_new();
 226 void write_nomemb_new();
 227 void write_nomemh_new();
 228 void write_nomemd_new();
 229 void write_rdram_new();
 230 void write_rdramb_new();
 231 void write_rdramh_new();
 232 void write_rdramd_new();
 233 extern u_int memory_map[1048576];
 234
 235 // Needed by assembler
 236 void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32);
 237 void wb_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty);
 238 void wb_needed_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr);
 239 void load_all_regs(signed char i_regmap[]);
 240 void load_needed_regs(signed char i_regmap[],signed char next_regmap[]);
 241 void load_regs_entry(int t);
 242 void load_all_consts(signed char regmap[],int is32,u_int dirty,int i);
 243
 244 int tracedebug=0;
 245
 246 //#define DEBUG_CYCLE_COUNT 1
 247
 248 void nullf() {}
 249 //#define assem_debug printf
 250 //#define inv_debug printf
 251 #define assem_debug nullf
 252 #define inv_debug nullf
 253
 254 static void tlb_hacks()
 255 {
 256 #ifndef DISABLE_TLB
 257   // Goldeneye hack
 258   if (strncmp((char *) ROM_HEADER->nom, "GOLDENEYE",9) == 0)
 259   {
 260     u_int addr;
 261     int n;
 262     switch (ROM_HEADER->Country_code&0xFF)
 263     {
 264       case 0x45: // U
 265         addr=0x34b30;
 266         break;
 267       case 0x4A: // J
 268         addr=0x34b70;
 269         break;
 270       case 0x50: // E
 271         addr=0x329f0;
 272         break;
 273       default:
 274         // Unknown country code
 275         addr=0;
 276         break;
 277     }
 278     u_int rom_addr=(u_int)rom;
 279     #ifdef ROM_COPY
 280     // Since memory_map is 32-bit, on 64-bit systems the rom needs to be
 281     // in the lower 4G of memory to use this hack.  Copy it if necessary.
 282     if((void *)rom>(void *)0xffffffff) {
 283       munmap(ROM_COPY, 67108864);
 284       if(mmap(ROM_COPY, 12582912,
 285               PROT_READ | PROT_WRITE,
 286               MAP_FIXED | MAP_PRIVATE | MAP_ANONYMOUS,
 287               -1, 0) <= 0) {printf("mmap() failed\n");}
 288       memcpy(ROM_COPY,rom,12582912);
 289       rom_addr=(u_int)ROM_COPY;
 290     }
 291     #endif
 292     if(addr) {
 293       for(n=0x7F000;n<0x80000;n++) {
 294         memory_map[n]=(((u_int)(rom_addr+addr-0x7F000000))>>2)|0x40000000;
 295       }
 296     }
 297   }
 298 #endif
 299 }
 300
 301 static u_int get_page(u_int vaddr)
 302 {
 303   u_int page=(vaddr^0x80000000)>>12;
 304 #ifndef DISABLE_TLB
 305   if(page>262143&&tlb_LUT_r[vaddr>>12]) page=(tlb_LUT_r[vaddr>>12]^0x80000000)>>12;
 306 #endif
 307   if(page>2048) page=2048+(page&2047);
 308   return page;
 309 }
 310
 311 static u_int get_vpage(u_int vaddr)
 312 {
 313   u_int vpage=(vaddr^0x80000000)>>12;
 314 #ifndef DISABLE_TLB
 315   if(vpage>262143&&tlb_LUT_r[vaddr>>12]) vpage&=2047; // jump_dirty uses a hash of the virtual address instead
 316 #endif
 317   if(vpage>2048) vpage=2048+(vpage&2047);
 318   return vpage;
 319 }
 320
 321 // Get address from virtual address
 322 // This is called from the recompiled JR/JALR instructions
 323 void *get_addr(u_int vaddr)
 324 {
 325   u_int page=get_page(vaddr);
 326   u_int vpage=get_vpage(vaddr);
 327   struct ll_entry *head;
 328   //printf("TRACE: count=%d next=%d (get_addr %x,page %d)\n",Count,next_interupt,vaddr,page);
 329   head=jump_in[page];
 330   while(head!=NULL) {
 331     if(head->vaddr==vaddr&&head->reg32==0) {
 332   //printf("TRACE: count=%d next=%d (get_addr match %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
 333       int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
 334       ht_bin[3]=ht_bin[1];
 335       ht_bin[2]=ht_bin[0];
 336       ht_bin[1]=(int)head->addr;
 337       ht_bin[0]=vaddr;
 338       return head->addr;
 339     }
 340     head=head->next;
 341   }
 342   head=jump_dirty[vpage];
 343   while(head!=NULL) {
 344     if(head->vaddr==vaddr&&head->reg32==0) {
 345       //printf("TRACE: count=%d next=%d (get_addr match dirty %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
 346       // Don't restore blocks which are about to expire from the cache
 347       if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
 348       if(verify_dirty(head->addr)) {
 349         //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]);
 350         invalid_code[vaddr>>12]=0;
 351         memory_map[vaddr>>12]|=0x40000000;
 352         if(vpage<2048) {
 353 #ifndef DISABLE_TLB
 354           if(tlb_LUT_r[vaddr>>12]) {
 355             invalid_code[tlb_LUT_r[vaddr>>12]>>12]=0;
 356             memory_map[tlb_LUT_r[vaddr>>12]>>12]|=0x40000000;
 357           }
 358 #endif
 359           restore_candidate[vpage>>3]|=1<<(vpage&7);
 360         }
 361         else restore_candidate[page>>3]|=1<<(page&7);
 362         int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
 363         if(ht_bin[0]==vaddr) {
 364           ht_bin[1]=(int)head->addr; // Replace existing entry
 365         }
 366         else
 367         {
 368           ht_bin[3]=ht_bin[1];
 369           ht_bin[2]=ht_bin[0];
 370           ht_bin[1]=(int)head->addr;
 371           ht_bin[0]=vaddr;
 372         }
 373         return head->addr;
 374       }
 375     }
 376     head=head->next;
 377   }
 378   //printf("TRACE: count=%d next=%d (get_addr no-match %x)\n",Count,next_interupt,vaddr);
 379   int r=new_recompile_block(vaddr);
 380   if(r==0) return get_addr(vaddr);
 381   // Execute in unmapped page, generate pagefault execption
 382   Status|=2;
 383   Cause=(vaddr<<31)|0x8;
 384   EPC=(vaddr&1)?vaddr-5:vaddr;
 385   BadVAddr=(vaddr&~1);
 386   Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0);
 387   EntryHi=BadVAddr&0xFFFFE000;
 388   return get_addr_ht(0x80000000);
 389 }
 390 // Look up address in hash table first
 391 void *get_addr_ht(u_int vaddr)
 392 {
 393   //printf("TRACE: count=%d next=%d (get_addr_ht %x)\n",Count,next_interupt,vaddr);
 394   int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
 395   if(ht_bin[0]==vaddr) return (void *)ht_bin[1];
 396   if(ht_bin[2]==vaddr) return (void *)ht_bin[3];
 397   return get_addr(vaddr);
 398 }
 399
 400 void *get_addr_32(u_int vaddr,u_int flags)
 401 {
 402   //printf("TRACE: count=%d next=%d (get_addr_32 %x,flags %x)\n",Count,next_interupt,vaddr,flags);
 403   int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
 404   if(ht_bin[0]==vaddr) return (void *)ht_bin[1];
 405   if(ht_bin[2]==vaddr) return (void *)ht_bin[3];
 406   u_int page=get_page(vaddr);
 407   u_int vpage=get_vpage(vaddr);
 408   struct ll_entry *head;
 409   head=jump_in[page];
 410   while(head!=NULL) {
 411     if(head->vaddr==vaddr&&(head->reg32&flags)==0) {
 412       //printf("TRACE: count=%d next=%d (get_addr_32 match %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
 413       if(head->reg32==0) {
 414         int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
 415         if(ht_bin[0]==-1) {
 416           ht_bin[1]=(int)head->addr;
 417           ht_bin[0]=vaddr;
 418         }else if(ht_bin[2]==-1) {
 419           ht_bin[3]=(int)head->addr;
 420           ht_bin[2]=vaddr;
 421         }
 422         //ht_bin[3]=ht_bin[1];
 423         //ht_bin[2]=ht_bin[0];
 424         //ht_bin[1]=(int)head->addr;
 425         //ht_bin[0]=vaddr;
 426       }
 427       return head->addr;
 428     }
 429     head=head->next;
 430   }
 431   head=jump_dirty[vpage];
 432   while(head!=NULL) {
 433     if(head->vaddr==vaddr&&(head->reg32&flags)==0) {
 434       //printf("TRACE: count=%d next=%d (get_addr_32 match dirty %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
 435       // Don't restore blocks which are about to expire from the cache
 436       if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
 437       if(verify_dirty(head->addr)) {
 438         //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]);
 439         invalid_code[vaddr>>12]=0;
 440         memory_map[vaddr>>12]|=0x40000000;
 441         if(vpage<2048) {
 442 #ifndef DISABLE_TLB
 443           if(tlb_LUT_r[vaddr>>12]) {
 444             invalid_code[tlb_LUT_r[vaddr>>12]>>12]=0;
 445             memory_map[tlb_LUT_r[vaddr>>12]>>12]|=0x40000000;
 446           }
 447 #endif
 448           restore_candidate[vpage>>3]|=1<<(vpage&7);
 449         }
 450         else restore_candidate[page>>3]|=1<<(page&7);
 451         if(head->reg32==0) {
 452           int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
 453           if(ht_bin[0]==-1) {
 454             ht_bin[1]=(int)head->addr;
 455             ht_bin[0]=vaddr;
 456           }else if(ht_bin[2]==-1) {
 457             ht_bin[3]=(int)head->addr;
 458             ht_bin[2]=vaddr;
 459           }
 460           //ht_bin[3]=ht_bin[1];
 461           //ht_bin[2]=ht_bin[0];
 462           //ht_bin[1]=(int)head->addr;
 463           //ht_bin[0]=vaddr;
 464         }
 465         return head->addr;
 466       }
 467     }
 468     head=head->next;
 469   }
 470   //printf("TRACE: count=%d next=%d (get_addr_32 no-match %x,flags %x)\n",Count,next_interupt,vaddr,flags);
 471   int r=new_recompile_block(vaddr);
 472   if(r==0) return get_addr(vaddr);
 473   // Execute in unmapped page, generate pagefault execption
 474   Status|=2;
 475   Cause=(vaddr<<31)|0x8;
 476   EPC=(vaddr&1)?vaddr-5:vaddr;
 477   BadVAddr=(vaddr&~1);
 478   Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0);
 479   EntryHi=BadVAddr&0xFFFFE000;
 480   return get_addr_ht(0x80000000);
 481 }
 482
 483 void clear_all_regs(signed char regmap[])
 484 {
 485   int hr;
 486   for (hr=0;hr<HOST_REGS;hr++) regmap[hr]=-1;
 487 }
 488
 489 signed char get_reg(signed char regmap[],int r)
 490 {
 491   int hr;
 492   for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&&regmap[hr]==r) return hr;
 493   return -1;
 494 }
 495
 496 // Find a register that is available for two consecutive cycles
 497 signed char get_reg2(signed char regmap1[],signed char regmap2[],int r)
 498 {
 499   int hr;
 500   for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&&regmap1[hr]==r&&regmap2[hr]==r) return hr;
 501   return -1;
 502 }
 503
 504 int count_free_regs(signed char regmap[])
 505 {
 506   int count=0;
 507   int hr;
 508   for(hr=0;hr<HOST_REGS;hr++)
 509   {
 510     if(hr!=EXCLUDE_REG) {
 511       if(regmap[hr]<0) count++;
 512     }
 513   }
 514   return count;
 515 }
 516
 517 void dirty_reg(struct regstat *cur,signed char reg)
 518 {
 519   int hr;
 520   if(!reg) return;
 521   for (hr=0;hr<HOST_REGS;hr++) {
 522     if((cur->regmap[hr]&63)==reg) {
 523       cur->dirty|=1<<hr;
 524     }
 525   }
 526 }
 527
 528 // If we dirty the lower half of a 64 bit register which is now being
 529 // sign-extended, we need to dump the upper half.
 530 // Note: Do this only after completion of the instruction, because
 531 // some instructions may need to read the full 64-bit value even if
 532 // overwriting it (eg SLTI, DSRA32).
 533 static void flush_dirty_uppers(struct regstat *cur)
 534 {
 535   int hr,reg;
 536   for (hr=0;hr<HOST_REGS;hr++) {
 537     if((cur->dirty>>hr)&1) {
 538       reg=cur->regmap[hr];
 539       if(reg>=64)
 540         if((cur->is32>>(reg&63))&1) cur->regmap[hr]=-1;
 541     }
 542   }
 543 }
 544
 545 void set_const(struct regstat *cur,signed char reg,uint64_t value)
 546 {
 547   int hr;
 548   if(!reg) return;
 549   for (hr=0;hr<HOST_REGS;hr++) {
 550     if(cur->regmap[hr]==reg) {
 551       cur->isconst|=1<<hr;
 552       cur->constmap[hr]=value;
 553     }
 554     else if((cur->regmap[hr]^64)==reg) {
 555       cur->isconst|=1<<hr;
 556       cur->constmap[hr]=value>>32;
 557     }
 558   }
 559 }
 560
 561 void clear_const(struct regstat *cur,signed char reg)
 562 {
 563   int hr;
 564   if(!reg) return;
 565   for (hr=0;hr<HOST_REGS;hr++) {
 566     if((cur->regmap[hr]&63)==reg) {
 567       cur->isconst&=~(1<<hr);
 568     }
 569   }
 570 }
 571
 572 int is_const(struct regstat *cur,signed char reg)
 573 {
 574   int hr;
 575   if(!reg) return 1;
 576   for (hr=0;hr<HOST_REGS;hr++) {
 577     if((cur->regmap[hr]&63)==reg) {
 578       return (cur->isconst>>hr)&1;
 579     }
 580   }
 581   return 0;
 582 }
 583 uint64_t get_const(struct regstat *cur,signed char reg)
 584 {
 585   int hr;
 586   if(!reg) return 0;
 587   for (hr=0;hr<HOST_REGS;hr++) {
 588     if(cur->regmap[hr]==reg) {
 589       return cur->constmap[hr];
 590     }
 591   }
 592   printf("Unknown constant in r%d\n",reg);
 593   exit(1);
 594 }
 595
 596 // Least soon needed registers
 597 // Look at the next ten instructions and see which registers
 598 // will be used.  Try not to reallocate these.
 599 void lsn(u_char hsn[], int i, int *preferred_reg)
 600 {
 601   int j;
 602   int b=-1;
 603   for(j=0;j<9;j++)
 604   {
 605     if(i+j>=slen) {
 606       j=slen-i-1;
 607       break;
 608     }
 609     if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
 610     {
 611       // Don't go past an unconditonal jump
 612       j++;
 613       break;
 614     }
 615   }
 616   for(;j>=0;j--)
 617   {
 618     if(rs1[i+j]) hsn[rs1[i+j]]=j;
 619     if(rs2[i+j]) hsn[rs2[i+j]]=j;
 620     if(rt1[i+j]) hsn[rt1[i+j]]=j;
 621     if(rt2[i+j]) hsn[rt2[i+j]]=j;
 622     if(itype[i+j]==STORE || itype[i+j]==STORELR) {
 623       // Stores can allocate zero
 624       hsn[rs1[i+j]]=j;
 625       hsn[rs2[i+j]]=j;
 626     }
 627     // On some architectures stores need invc_ptr
 628     #if defined(HOST_IMM8)
 629     if(itype[i+j]==STORE || itype[i+j]==STORELR || (opcode[i+j]&0x3b)==0x39) {
 630       hsn[INVCP]=j;
 631     }
 632     #endif
 633     if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP))
 634     {
 635       hsn[CCREG]=j;
 636       b=j;
 637     }
 638   }
 639   if(b>=0)
 640   {
 641     if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
 642     {
 643       // Follow first branch
 644       int t=(ba[i+b]-start)>>2;
 645       j=7-b;if(t+j>=slen) j=slen-t-1;
 646       for(;j>=0;j--)
 647       {
 648         if(rs1[t+j]) if(hsn[rs1[t+j]]>j+b+2) hsn[rs1[t+j]]=j+b+2;
 649         if(rs2[t+j]) if(hsn[rs2[t+j]]>j+b+2) hsn[rs2[t+j]]=j+b+2;
 650         //if(rt1[t+j]) if(hsn[rt1[t+j]]>j+b+2) hsn[rt1[t+j]]=j+b+2;
 651         //if(rt2[t+j]) if(hsn[rt2[t+j]]>j+b+2) hsn[rt2[t+j]]=j+b+2;
 652       }
 653     }
 654     // TODO: preferred register based on backward branch
 655   }
 656   // Delay slot should preferably not overwrite branch conditions or cycle count
 657   if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)) {
 658     if(rs1[i-1]) if(hsn[rs1[i-1]]>1) hsn[rs1[i-1]]=1;
 659     if(rs2[i-1]) if(hsn[rs2[i-1]]>1) hsn[rs2[i-1]]=1;
 660     hsn[CCREG]=1;
 661     // ...or hash tables
 662     hsn[RHASH]=1;
 663     hsn[RHTBL]=1;
 664   }
 665   // Coprocessor load/store needs FTEMP, even if not declared
 666   if(itype[i]==C1LS) {
 667     hsn[FTEMP]=0;
 668   }
 669   // Load L/R also uses FTEMP as a temporary register
 670   if(itype[i]==LOADLR) {
 671     hsn[FTEMP]=0;
 672   }
 673   // Also 64-bit SDL/SDR
 674   if(opcode[i]==0x2c||opcode[i]==0x2d) {
 675     hsn[FTEMP]=0;
 676   }
 677   // Don't remove the TLB registers either
 678   if(itype[i]==LOAD || itype[i]==LOADLR || itype[i]==STORE || itype[i]==STORELR || itype[i]==C1LS ) {
 679     hsn[TLREG]=0;
 680   }
 681   // Don't remove the miniht registers
 682   if(itype[i]==UJUMP||itype[i]==RJUMP)
 683   {
 684     hsn[RHASH]=0;
 685     hsn[RHTBL]=0;
 686   }
 687 }
 688
 689 // We only want to allocate registers if we're going to use them again soon
 690 int needed_again(int r, int i)
 691 {
 692   int j;
 693   int b=-1;
 694   int rn=10;
 695   int hr;
 696   u_char hsn[MAXREG+1];
 697   int preferred_reg;
 698
 699   memset(hsn,10,sizeof(hsn));
 700   lsn(hsn,i,&preferred_reg);
 701
 702   if(i>0&&(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000))
 703   {
 704     if(ba[i-1]<start || ba[i-1]>start+slen*4-4)
 705       return 0; // Don't need any registers if exiting the block
 706   }
 707   for(j=0;j<9;j++)
 708   {
 709     if(i+j>=slen) {
 710       j=slen-i-1;
 711       break;
 712     }
 713     if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
 714     {
 715       // Don't go past an unconditonal jump
 716       j++;
 717       break;
 718     }
 719     if(itype[i+j]==SYSCALL||((source[i+j]&0xfc00003f)==0x0d))
 720     {
 721       break;
 722     }
 723   }
 724   for(;j>=1;j--)
 725   {
 726     if(rs1[i+j]==r) rn=j;
 727     if(rs2[i+j]==r) rn=j;
 728     if((unneeded_reg[i+j]>>r)&1) rn=10;
 729     if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP))
 730     {
 731       b=j;
 732     }
 733   }
 734   /*
 735   if(b>=0)
 736   {
 737     if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
 738     {
 739       // Follow first branch
 740       int o=rn;
 741       int t=(ba[i+b]-start)>>2;
 742       j=7-b;if(t+j>=slen) j=slen-t-1;
 743       for(;j>=0;j--)
 744       {
 745         if(!((unneeded_reg[t+j]>>r)&1)) {
 746           if(rs1[t+j]==r) if(rn>j+b+2) rn=j+b+2;
 747           if(rs2[t+j]==r) if(rn>j+b+2) rn=j+b+2;
 748         }
 749         else rn=o;
 750       }
 751     }
 752   }*/
 753   for(hr=0;hr<HOST_REGS;hr++) {
 754     if(hr!=EXCLUDE_REG) {
 755       if(rn<hsn[hr]) return 1;
 756     }
 757   }
 758   return 0;
 759 }
 760
 761 // Try to match register allocations at the end of a loop with those
 762 // at the beginning
 763 int loop_reg(int i, int r, int hr)
 764 {
 765   int j,k;
 766   for(j=0;j<9;j++)
 767   {
 768     if(i+j>=slen) {
 769       j=slen-i-1;
 770       break;
 771     }
 772     if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
 773     {
 774       // Don't go past an unconditonal jump
 775       j++;
 776       break;
 777     }
 778   }
 779   k=0;
 780   if(i>0){
 781     if(itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)
 782       k--;
 783   }
 784   for(;k<j;k++)
 785   {
 786     if(r<64&&((unneeded_reg[i+k]>>r)&1)) return hr;
 787     if(r>64&&((unneeded_reg_upper[i+k]>>r)&1)) return hr;
 788     if(i+k>=0&&(itype[i+k]==UJUMP||itype[i+k]==CJUMP||itype[i+k]==SJUMP||itype[i+k]==FJUMP))
 789     {
 790       if(ba[i+k]>=start && ba[i+k]<(start+i*4))
 791       {
 792         int t=(ba[i+k]-start)>>2;
 793         int reg=get_reg(regs[t].regmap_entry,r);
 794         if(reg>=0) return reg;
 795         //reg=get_reg(regs[t+1].regmap_entry,r);
 796         //if(reg>=0) return reg;
 797       }
 798     }
 799   }
 800   return hr;
 801 }
 802
 803
 804 // Allocate every register, preserving source/target regs
 805 void alloc_all(struct regstat *cur,int i)
 806 {
 807   int hr;
 808
 809   for(hr=0;hr<HOST_REGS;hr++) {
 810     if(hr!=EXCLUDE_REG) {
 811       if(((cur->regmap[hr]&63)!=rs1[i])&&((cur->regmap[hr]&63)!=rs2[i])&&
 812          ((cur->regmap[hr]&63)!=rt1[i])&&((cur->regmap[hr]&63)!=rt2[i]))
 813       {
 814         cur->regmap[hr]=-1;
 815         cur->dirty&=~(1<<hr);
 816       }
 817       // Don't need zeros
 818       if((cur->regmap[hr]&63)==0)
 819       {
 820         cur->regmap[hr]=-1;
 821         cur->dirty&=~(1<<hr);
 822       }
 823     }
 824   }
 825 }
 826
 827
 828 void div64(int64_t dividend,int64_t divisor)
 829 {
 830   lo=dividend/divisor;
 831   hi=dividend%divisor;
 832   //printf("TRACE: ddiv %8x%8x %8x%8x\n" ,(int)reg[HIREG],(int)(reg[HIREG]>>32)
 833   //                                     ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
 834 }
 835 void divu64(uint64_t dividend,uint64_t divisor)
 836 {
 837   lo=dividend/divisor;
 838   hi=dividend%divisor;
 839   //printf("TRACE: ddivu %8x%8x %8x%8x\n",(int)reg[HIREG],(int)(reg[HIREG]>>32)
 840   //                                     ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
 841 }
 842
 843 void mult64(uint64_t m1,uint64_t m2)
 844 {
 845    unsigned long long int op1, op2, op3, op4;
 846    unsigned long long int result1, result2, result3, result4;
 847    unsigned long long int temp1, temp2, temp3, temp4;
 848    int sign = 0;
 849
 850    if (m1 < 0)
 851      {
 852     op2 = -m1;
 853     sign = 1 - sign;
 854      }
 855    else op2 = m1;
 856    if (m2 < 0)
 857      {
 858     op4 = -m2;
 859     sign = 1 - sign;
 860      }
 861    else op4 = m2;
 862
 863    op1 = op2 & 0xFFFFFFFF;
 864    op2 = (op2 >> 32) & 0xFFFFFFFF;
 865    op3 = op4 & 0xFFFFFFFF;
 866    op4 = (op4 >> 32) & 0xFFFFFFFF;
 867
 868    temp1 = op1 * op3;
 869    temp2 = (temp1 >> 32) + op1 * op4;
 870    temp3 = op2 * op3;
 871    temp4 = (temp3 >> 32) + op2 * op4;
 872
 873    result1 = temp1 & 0xFFFFFFFF;
 874    result2 = temp2 + (temp3 & 0xFFFFFFFF);
 875    result3 = (result2 >> 32) + temp4;
 876    result4 = (result3 >> 32);
 877
 878    lo = result1 | (result2 << 32);
 879    hi = (result3 & 0xFFFFFFFF) | (result4 << 32);
 880    if (sign)
 881      {
 882     hi = ~hi;
 883     if (!lo) hi++;
 884     else lo = ~lo + 1;
 885      }
 886 }
 887
 888 void multu64(uint64_t m1,uint64_t m2)
 889 {
 890    unsigned long long int op1, op2, op3, op4;
 891    unsigned long long int result1, result2, result3, result4;
 892    unsigned long long int temp1, temp2, temp3, temp4;
 893
 894    op1 = m1 & 0xFFFFFFFF;
 895    op2 = (m1 >> 32) & 0xFFFFFFFF;
 896    op3 = m2 & 0xFFFFFFFF;
 897    op4 = (m2 >> 32) & 0xFFFFFFFF;
 898
 899    temp1 = op1 * op3;
 900    temp2 = (temp1 >> 32) + op1 * op4;
 901    temp3 = op2 * op3;
 902    temp4 = (temp3 >> 32) + op2 * op4;
 903
 904    result1 = temp1 & 0xFFFFFFFF;
 905    result2 = temp2 + (temp3 & 0xFFFFFFFF);
 906    result3 = (result2 >> 32) + temp4;
 907    result4 = (result3 >> 32);
 908
 909    lo = result1 | (result2 << 32);
 910    hi = (result3 & 0xFFFFFFFF) | (result4 << 32);
 911
 912   //printf("TRACE: dmultu %8x%8x %8x%8x\n",(int)reg[HIREG],(int)(reg[HIREG]>>32)
 913   //                                      ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
 914 }
 915
 916 uint64_t ldl_merge(uint64_t original,uint64_t loaded,u_int bits)
 917 {
 918   if(bits) {
 919     original<<=64-bits;
 920     original>>=64-bits;
 921     loaded<<=bits;
 922     original|=loaded;
 923   }
 924   else original=loaded;
 925   return original;
 926 }
 927 uint64_t ldr_merge(uint64_t original,uint64_t loaded,u_int bits)
 928 {
 929   if(bits^56) {
 930     original>>=64-(bits^56);
 931     original<<=64-(bits^56);
 932     loaded>>=bits^56;
 933     original|=loaded;
 934   }
 935   else original=loaded;
 936   return original;
 937 }
 938
 939 #ifdef __i386__
 940 #include "assem_x86.c"
 941 #endif
 942 #ifdef __x86_64__
 943 #include "assem_x64.c"
 944 #endif
 945 #ifdef __arm__
 946 #include "assem_arm.c"
 947 #endif
 948
 949 // Add virtual address mapping to linked list
 950 void ll_add(struct ll_entry **head,int vaddr,void *addr)
 951 {
 952   struct ll_entry *new_entry;
 953   new_entry=malloc(sizeof(struct ll_entry));
 954   assert(new_entry!=NULL);
 955   new_entry->vaddr=vaddr;
 956   new_entry->reg32=0;
 957   new_entry->addr=addr;
 958   new_entry->next=*head;
 959   *head=new_entry;
 960 }
 961
 962 // Add virtual address mapping for 32-bit compiled block
 963 void ll_add_32(struct ll_entry **head,int vaddr,u_int reg32,void *addr)
 964 {
 965   struct ll_entry *new_entry;
 966   new_entry=malloc(sizeof(struct ll_entry));
 967   assert(new_entry!=NULL);
 968   new_entry->vaddr=vaddr;
 969   new_entry->reg32=reg32;
 970   new_entry->addr=addr;
 971   new_entry->next=*head;
 972   *head=new_entry;
 973 }
 974
 975 // Check if an address is already compiled
 976 // but don't return addresses which are about to expire from the cache
 977 void *check_addr(u_int vaddr)
 978 {
 979   u_int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
 980   if(ht_bin[0]==vaddr) {
 981     if(((ht_bin[1]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
 982       if(isclean(ht_bin[1])) return (void *)ht_bin[1];
 983   }
 984   if(ht_bin[2]==vaddr) {
 985     if(((ht_bin[3]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
 986       if(isclean(ht_bin[3])) return (void *)ht_bin[3];
 987   }
 988   u_int page=get_page(vaddr);
 989   struct ll_entry *head;
 990   head=jump_in[page];
 991   while(head!=NULL) {
 992     if(head->vaddr==vaddr&&head->reg32==0) {
 993       if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
 994         // Update existing entry with current address
 995         if(ht_bin[0]==vaddr) {
 996           ht_bin[1]=(int)head->addr;
 997           return head->addr;
 998         }
 999         if(ht_bin[2]==vaddr) {
1000           ht_bin[3]=(int)head->addr;
1001           return head->addr;
1002         }
1003         // Insert into hash table with low priority.
1004         // Don't evict existing entries, as they are probably
1005         // addresses that are being accessed frequently.
1006         if(ht_bin[0]==-1) {
1007           ht_bin[1]=(int)head->addr;
1008           ht_bin[0]=vaddr;
1009         }else if(ht_bin[2]==-1) {
1010           ht_bin[3]=(int)head->addr;
1011           ht_bin[2]=vaddr;
1012         }
1013         return head->addr;
1014       }
1015     }
1016     head=head->next;
1017   }
1018   return 0;
1019 }
1020
1021 void remove_hash(int vaddr)
1022 {
1023   //printf("remove hash: %x\n",vaddr);
1024   int *ht_bin=hash_table[(((vaddr)>>16)^vaddr)&0xFFFF];
1025   if(ht_bin[2]==vaddr) {
1026     ht_bin[2]=ht_bin[3]=-1;
1027   }
1028   if(ht_bin[0]==vaddr) {
1029     ht_bin[0]=ht_bin[2];
1030     ht_bin[1]=ht_bin[3];
1031     ht_bin[2]=ht_bin[3]=-1;
1032   }
1033 }
1034
1035 void ll_remove_matching_addrs(struct ll_entry **head,int addr,int shift)
1036 {
1037   struct ll_entry *next;
1038   while(*head) {
1039     if(((u_int)((*head)->addr)>>shift)==(addr>>shift) ||
1040        ((u_int)((*head)->addr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift))
1041     {
1042       inv_debug("EXP: Remove pointer to %x (%x)\n",(int)(*head)->addr,(*head)->vaddr);
1043       remove_hash((*head)->vaddr);
1044       next=(*head)->next;
1045       free(*head);
1046       *head=next;
1047     }
1048     else
1049     {
1050       head=&((*head)->next);
1051     }
1052   }
1053 }
1054
1055 // Remove all entries from linked list
1056 void ll_clear(struct ll_entry **head)
1057 {
1058   struct ll_entry *cur;
1059   struct ll_entry *next;
1060   if(cur=*head) {
1061     *head=0;
1062     while(cur) {
1063       next=cur->next;
1064       free(cur);
1065       cur=next;
1066     }
1067   }
1068 }
1069
1070 // Dereference the pointers and remove if it matches
1071 void ll_kill_pointers(struct ll_entry *head,int addr,int shift)
1072 {
1073   while(head) {
1074     int ptr=get_pointer(head->addr);
1075     inv_debug("EXP: Lookup pointer to %x at %x (%x)\n",(int)ptr,(int)head->addr,head->vaddr);
1076     if(((ptr>>shift)==(addr>>shift)) ||
1077        (((ptr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift)))
1078     {
1079       inv_debug("EXP: Kill pointer at %x (%x)\n",(int)head->addr,head->vaddr);
1080       kill_pointer(head->addr);
1081     }
1082     head=head->next;
1083   }
1084 }
1085
1086 // This is called when we write to a compiled block (see do_invstub)
1087 int invalidate_page(u_int page)
1088 {
1089   int modified=0;
1090   struct ll_entry *head;
1091   struct ll_entry *next;
1092   head=jump_in[page];
1093   jump_in[page]=0;
1094   while(head!=NULL) {
1095     inv_debug("INVALIDATE: %x\n",head->vaddr);
1096     remove_hash(head->vaddr);
1097     next=head->next;
1098     free(head);
1099     head=next;
1100   }
1101   head=jump_out[page];
1102   jump_out[page]=0;
1103   while(head!=NULL) {
1104     inv_debug("INVALIDATE: kill pointer to %x (%x)\n",head->vaddr,(int)head->addr);
1105     kill_pointer(head->addr);
1106     modified=1;
1107     next=head->next;
1108     free(head);
1109     head=next;
1110   }
1111   return modified;
1112 }
1113 void invalidate_block(u_int block)
1114 {
1115   int modified;
1116   u_int page=get_page(block<<12);
1117   u_int vpage=get_vpage(block<<12);
1118   inv_debug("INVALIDATE: %x (%d)\n",block<<12,page);
1119   //inv_debug("invalid_code[block]=%d\n",invalid_code[block]);
1120   u_int first,last;
1121   first=last=page;
1122   struct ll_entry *head;
1123   head=jump_dirty[vpage];
1124   //printf("page=%d vpage=%d\n",page,vpage);
1125   while(head!=NULL) {
1126     u_int start,end;
1127     if(vpage>2047||(head->vaddr>>12)==block) { // Ignore vaddr hash collision
1128       get_bounds((int)head->addr,&start,&end);
1129       //printf("start: %x end: %x\n",start,end);
1130       if(page<2048&&start>=0x80000000&&end<0x80800000) {
1131         if(((start-(u_int)rdram)>>12)<=page&&((end-1-(u_int)rdram)>>12)>=page) {
1132           if((((start-(u_int)rdram)>>12)&2047)<first) first=((start-(u_int)rdram)>>12)&2047;
1133           if((((end-1-(u_int)rdram)>>12)&2047)>last) last=((end-1-(u_int)rdram)>>12)&2047;
1134         }
1135       }
1136       if(page<2048&&(signed int)start>=(signed int)0xC0000000&&(signed int)end>=(signed int)0xC0000000) {
1137         if(((start+memory_map[start>>12]-(u_int)rdram)>>12)<=page&&((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)>=page) {
1138           if((((start+memory_map[start>>12]-(u_int)rdram)>>12)&2047)<first) first=((start+memory_map[start>>12]-(u_int)rdram)>>12)&2047;
1139           if((((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)&2047)>last) last=((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)&2047;
1140         }
1141       }
1142     }
1143     head=head->next;
1144   }
1145   //printf("first=%d last=%d\n",first,last);
1146   modified=invalidate_page(page);
1147   assert(first+5>page); // NB: this assumes MAXBLOCK<=4096 (4 pages)
1148   assert(last<page+5);
1149   // Invalidate the adjacent pages if a block crosses a 4K boundary
1150   while(first<page) {
1151     invalidate_page(first);
1152     first++;
1153   }
1154   for(first=page+1;first<last;first++) {
1155     invalidate_page(first);
1156   }
1157
1158   // Don't trap writes
1159   invalid_code[block]=1;
1160 #ifndef DISABLE_TLB
1161   // If there is a valid TLB entry for this page, remove write protect
1162   if(tlb_LUT_w[block]) {
1163     assert(tlb_LUT_r[block]==tlb_LUT_w[block]);
1164     // CHECK: Is this right?
1165     memory_map[block]=((tlb_LUT_w[block]&0xFFFFF000)-(block<<12)+(unsigned int)rdram-0x80000000)>>2;
1166     u_int real_block=tlb_LUT_w[block]>>12;
1167     invalid_code[real_block]=1;
1168     if(real_block>=0x80000&&real_block<0x80800) memory_map[real_block]=((u_int)rdram-0x80000000)>>2;
1169   }
1170   else if(block>=0x80000&&block<0x80800) memory_map[block]=((u_int)rdram-0x80000000)>>2;
1171 #endif
1172   #ifdef __arm__
1173   if(modified)
1174     __clear_cache((void *)BASE_ADDR,(void *)BASE_ADDR+(1<<TARGET_SIZE_2));
1175   #endif
1176   #ifdef USE_MINI_HT
1177   memset(mini_ht,-1,sizeof(mini_ht));
1178   #endif
1179 }
1180 void invalidate_addr(u_int addr)
1181 {
1182   invalidate_block(addr>>12);
1183 }
1184 void invalidate_all_pages()
1185 {
1186   u_int page,n;
1187   for(page=0;page<4096;page++)
1188     invalidate_page(page);
1189   for(page=0;page<1048576;page++)
1190     if(!invalid_code[page]) {
1191       restore_candidate[(page&2047)>>3]|=1<<(page&7);
1192       restore_candidate[((page&2047)>>3)+256]|=1<<(page&7);
1193     }
1194   #ifdef __arm__
1195   __clear_cache((void *)BASE_ADDR,(void *)BASE_ADDR+(1<<TARGET_SIZE_2));
1196   #endif
1197   #ifdef USE_MINI_HT
1198   memset(mini_ht,-1,sizeof(mini_ht));
1199   #endif
1200   #ifndef DISABLE_TLB
1201   // TLB
1202   for(page=0;page<0x100000;page++) {
1203     if(tlb_LUT_r[page]) {
1204       memory_map[page]=((tlb_LUT_r[page]&0xFFFFF000)-(page<<12)+(unsigned int)rdram-0x80000000)>>2;
1205       if(!tlb_LUT_w[page]||!invalid_code[page])
1206         memory_map[page]|=0x40000000; // Write protect
1207     }
1208     else memory_map[page]=-1;
1209     if(page==0x80000) page=0xC0000;
1210   }
1211   tlb_hacks();
1212   #endif
1213 }
1214
1215 // Add an entry to jump_out after making a link
1216 void add_link(u_int vaddr,void *src)
1217 {
1218   u_int page=get_page(vaddr);
1219   inv_debug("add_link: %x -> %x (%d)\n",(int)src,vaddr,page);
1220   ll_add(jump_out+page,vaddr,src);
1221   //int ptr=get_pointer(src);
1222   //inv_debug("add_link: Pointer is to %x\n",(int)ptr);
1223 }
1224
1225 // If a code block was found to be unmodified (bit was set in
1226 // restore_candidate) and it remains unmodified (bit is clear
1227 // in invalid_code) then move the entries for that 4K page from
1228 // the dirty list to the clean list.
1229 void clean_blocks(u_int page)
1230 {
1231   struct ll_entry *head;
1232   inv_debug("INV: clean_blocks page=%d\n",page);
1233   head=jump_dirty[page];
1234   while(head!=NULL) {
1235     if(!invalid_code[head->vaddr>>12]) {
1236       // Don't restore blocks which are about to expire from the cache
1237       if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1238         u_int start,end;
1239         if(verify_dirty((int)head->addr)) {
1240           //printf("Possibly Restore %x (%x)\n",head->vaddr, (int)head->addr);
1241           u_int i;
1242           u_int inv=0;
1243           get_bounds((int)head->addr,&start,&end);
1244           if(start-(u_int)rdram<0x800000) {
1245             for(i=(start-(u_int)rdram+0x80000000)>>12;i<=(end-1-(u_int)rdram+0x80000000)>>12;i++) {
1246               inv|=invalid_code[i];
1247             }
1248           }
1249           if((signed int)head->vaddr>=(signed int)0xC0000000) {
1250             u_int addr = (head->vaddr+(memory_map[head->vaddr>>12]<<2));
1251             //printf("addr=%x start=%x end=%x\n",addr,start,end);
1252             if(addr<start||addr>=end) inv=1;
1253           }
1254           else if((signed int)head->vaddr>=(signed int)0x80800000) {
1255             inv=1;
1256           }
1257           if(!inv) {
1258             void * clean_addr=(void *)get_clean_addr((int)head->addr);
1259             if((((u_int)clean_addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1260               u_int ppage=page;
1261 #ifndef DISABLE_TLB
1262               if(page<2048&&tlb_LUT_r[head->vaddr>>12]) ppage=(tlb_LUT_r[head->vaddr>>12]^0x80000000)>>12;
1263 #endif
1264               inv_debug("INV: Restored %x (%x/%x)\n",head->vaddr, (int)head->addr, (int)clean_addr);
1265               //printf("page=%x, addr=%x\n",page,head->vaddr);
1266               //assert(head->vaddr>>12==(page|0x80000));
1267               ll_add_32(jump_in+ppage,head->vaddr,head->reg32,clean_addr);
1268               int *ht_bin=hash_table[((head->vaddr>>16)^head->vaddr)&0xFFFF];
1269               if(!head->reg32) {
1270                 if(ht_bin[0]==head->vaddr) {
1271                   ht_bin[1]=(int)clean_addr; // Replace existing entry
1272                 }
1273                 if(ht_bin[2]==head->vaddr) {
1274                   ht_bin[3]=(int)clean_addr; // Replace existing entry
1275                 }
1276               }
1277             }
1278           }
1279         }
1280       }
1281     }
1282     head=head->next;
1283   }
1284 }
1285
1286
1287 void mov_alloc(struct regstat *current,int i)
1288 {
1289   // Note: Don't need to actually alloc the source registers
1290   if((~current->is32>>rs1[i])&1) {
1291     //alloc_reg64(current,i,rs1[i]);
1292     alloc_reg64(current,i,rt1[i]);
1293     current->is32&=~(1LL<<rt1[i]);
1294   } else {
1295     //alloc_reg(current,i,rs1[i]);
1296     alloc_reg(current,i,rt1[i]);
1297     current->is32|=(1LL<<rt1[i]);
1298   }
1299   clear_const(current,rs1[i]);
1300   clear_const(current,rt1[i]);
1301   dirty_reg(current,rt1[i]);
1302 }
1303
1304 void shiftimm_alloc(struct regstat *current,int i)
1305 {
1306   clear_const(current,rs1[i]);
1307   clear_const(current,rt1[i]);
1308   if(opcode2[i]<=0x3) // SLL/SRL/SRA
1309   {
1310     if(rt1[i]) {
1311       if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1312       else lt1[i]=rs1[i];
1313       alloc_reg(current,i,rt1[i]);
1314       current->is32|=1LL<<rt1[i];
1315       dirty_reg(current,rt1[i]);
1316     }
1317   }
1318   if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA
1319   {
1320     if(rt1[i]) {
1321       if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1322       alloc_reg64(current,i,rt1[i]);
1323       current->is32&=~(1LL<<rt1[i]);
1324       dirty_reg(current,rt1[i]);
1325     }
1326   }
1327   if(opcode2[i]==0x3c) // DSLL32
1328   {
1329     if(rt1[i]) {
1330       if(rs1[i]) alloc_reg(current,i,rs1[i]);
1331       alloc_reg64(current,i,rt1[i]);
1332       current->is32&=~(1LL<<rt1[i]);
1333       dirty_reg(current,rt1[i]);
1334     }
1335   }
1336   if(opcode2[i]==0x3e) // DSRL32
1337   {
1338     if(rt1[i]) {
1339       alloc_reg64(current,i,rs1[i]);
1340       if(imm[i]==32) {
1341         alloc_reg64(current,i,rt1[i]);
1342         current->is32&=~(1LL<<rt1[i]);
1343       } else {
1344         alloc_reg(current,i,rt1[i]);
1345         current->is32|=1LL<<rt1[i];
1346       }
1347       dirty_reg(current,rt1[i]);
1348     }
1349   }
1350   if(opcode2[i]==0x3f) // DSRA32
1351   {
1352     if(rt1[i]) {
1353       alloc_reg64(current,i,rs1[i]);
1354       alloc_reg(current,i,rt1[i]);
1355       current->is32|=1LL<<rt1[i];
1356       dirty_reg(current,rt1[i]);
1357     }
1358   }
1359 }
1360
1361 void shift_alloc(struct regstat *current,int i)
1362 {
1363   if(rt1[i]) {
1364     if(opcode2[i]<=0x07) // SLLV/SRLV/SRAV
1365     {
1366       if(rs1[i]) alloc_reg(current,i,rs1[i]);
1367       if(rs2[i]) alloc_reg(current,i,rs2[i]);
1368       alloc_reg(current,i,rt1[i]);
1369       if(rt1[i]==rs2[i]) alloc_reg_temp(current,i,-1);
1370       current->is32|=1LL<<rt1[i];
1371     } else { // DSLLV/DSRLV/DSRAV
1372       if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1373       if(rs2[i]) alloc_reg(current,i,rs2[i]);
1374       alloc_reg64(current,i,rt1[i]);
1375       current->is32&=~(1LL<<rt1[i]);
1376       if(opcode2[i]==0x16||opcode2[i]==0x17) // DSRLV and DSRAV need a temporary register
1377         alloc_reg_temp(current,i,-1);
1378     }
1379     clear_const(current,rs1[i]);
1380     clear_const(current,rs2[i]);
1381     clear_const(current,rt1[i]);
1382     dirty_reg(current,rt1[i]);
1383   }
1384 }
1385
1386 void alu_alloc(struct regstat *current,int i)
1387 {
1388   if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
1389     if(rt1[i]) {
1390       if(rs1[i]&&rs2[i]) {
1391         alloc_reg(current,i,rs1[i]);
1392         alloc_reg(current,i,rs2[i]);
1393       }
1394       else {
1395         if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1396         if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]);
1397       }
1398       alloc_reg(current,i,rt1[i]);
1399     }
1400     current->is32|=1LL<<rt1[i];
1401   }
1402   if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU
1403     if(rt1[i]) {
1404       if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1405       {
1406         alloc_reg64(current,i,rs1[i]);
1407         alloc_reg64(current,i,rs2[i]);
1408         alloc_reg(current,i,rt1[i]);
1409       } else {
1410         alloc_reg(current,i,rs1[i]);
1411         alloc_reg(current,i,rs2[i]);
1412         alloc_reg(current,i,rt1[i]);
1413       }
1414     }
1415     current->is32|=1LL<<rt1[i];
1416   }
1417   if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR
1418     if(rt1[i]) {
1419       if(rs1[i]&&rs2[i]) {
1420         alloc_reg(current,i,rs1[i]);
1421         alloc_reg(current,i,rs2[i]);
1422       }
1423       else
1424       {
1425         if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1426         if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]);
1427       }
1428       alloc_reg(current,i,rt1[i]);
1429       if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1430       {
1431         if(!((current->uu>>rt1[i])&1)) {
1432           alloc_reg64(current,i,rt1[i]);
1433         }
1434         if(get_reg(current->regmap,rt1[i]|64)>=0) {
1435           if(rs1[i]&&rs2[i]) {
1436             alloc_reg64(current,i,rs1[i]);
1437             alloc_reg64(current,i,rs2[i]);
1438           }
1439           else
1440           {
1441             // Is is really worth it to keep 64-bit values in registers?
1442             #ifdef NATIVE_64BIT
1443             if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]);
1444             if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg64(current,i,rs2[i]);
1445             #endif
1446           }
1447         }
1448         current->is32&=~(1LL<<rt1[i]);
1449       } else {
1450         current->is32|=1LL<<rt1[i];
1451       }
1452     }
1453   }
1454   if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU
1455     if(rt1[i]) {
1456       if(rs1[i]&&rs2[i]) {
1457         if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1458           alloc_reg64(current,i,rs1[i]);
1459           alloc_reg64(current,i,rs2[i]);
1460           alloc_reg64(current,i,rt1[i]);
1461         } else {
1462           alloc_reg(current,i,rs1[i]);
1463           alloc_reg(current,i,rs2[i]);
1464           alloc_reg(current,i,rt1[i]);
1465         }
1466       }
1467       else {
1468         alloc_reg(current,i,rt1[i]);
1469         if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1470           // DADD used as move, or zeroing
1471           // If we have a 64-bit source, then make the target 64 bits too
1472           if(rs1[i]&&!((current->is32>>rs1[i])&1)) {
1473             if(get_reg(current->regmap,rs1[i])>=0) alloc_reg64(current,i,rs1[i]);
1474             alloc_reg64(current,i,rt1[i]);
1475           } else if(rs2[i]&&!((current->is32>>rs2[i])&1)) {
1476             if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]);
1477             alloc_reg64(current,i,rt1[i]);
1478           }
1479           if(opcode2[i]>=0x2e&&rs2[i]) {
1480             // DSUB used as negation - 64-bit result
1481             // If we have a 32-bit register, extend it to 64 bits
1482             if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]);
1483             alloc_reg64(current,i,rt1[i]);
1484           }
1485         }
1486       }
1487       if(rs1[i]&&rs2[i]) {
1488         current->is32&=~(1LL<<rt1[i]);
1489       } else if(rs1[i]) {
1490         current->is32&=~(1LL<<rt1[i]);
1491         if((current->is32>>rs1[i])&1)
1492           current->is32|=1LL<<rt1[i];
1493       } else if(rs2[i]) {
1494         current->is32&=~(1LL<<rt1[i]);
1495         if((current->is32>>rs2[i])&1)
1496           current->is32|=1LL<<rt1[i];
1497       } else {
1498         current->is32|=1LL<<rt1[i];
1499       }
1500     }
1501   }
1502   clear_const(current,rs1[i]);
1503   clear_const(current,rs2[i]);
1504   clear_const(current,rt1[i]);
1505   dirty_reg(current,rt1[i]);
1506 }
1507
1508 void imm16_alloc(struct regstat *current,int i)
1509 {
1510   if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1511   else lt1[i]=rs1[i];
1512   if(rt1[i]) alloc_reg(current,i,rt1[i]);
1513   if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU
1514     current->is32&=~(1LL<<rt1[i]);
1515     if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1516       // TODO: Could preserve the 32-bit flag if the immediate is zero
1517       alloc_reg64(current,i,rt1[i]);
1518       alloc_reg64(current,i,rs1[i]);
1519     }
1520     clear_const(current,rs1[i]);
1521     clear_const(current,rt1[i]);
1522   }
1523   else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU
1524     if((~current->is32>>rs1[i])&1) alloc_reg64(current,i,rs1[i]);
1525     current->is32|=1LL<<rt1[i];
1526     clear_const(current,rs1[i]);
1527     clear_const(current,rt1[i]);
1528   }
1529   else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI
1530     if(((~current->is32>>rs1[i])&1)&&opcode[i]>0x0c) {
1531       if(rs1[i]!=rt1[i]) {
1532         if(needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]);
1533         alloc_reg64(current,i,rt1[i]);
1534         current->is32&=~(1LL<<rt1[i]);
1535       }
1536     }
1537     else current->is32|=1LL<<rt1[i]; // ANDI clears upper bits
1538     if(is_const(current,rs1[i])) {
1539       int v=get_const(current,rs1[i]);
1540       if(opcode[i]==0x0c) set_const(current,rt1[i],v&imm[i]);
1541       if(opcode[i]==0x0d) set_const(current,rt1[i],v|imm[i]);
1542       if(opcode[i]==0x0e) set_const(current,rt1[i],v^imm[i]);
1543     }
1544     else clear_const(current,rt1[i]);
1545   }
1546   else if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU
1547     if(is_const(current,rs1[i])) {
1548       int v=get_const(current,rs1[i]);
1549       set_const(current,rt1[i],v+imm[i]);
1550     }
1551     else clear_const(current,rt1[i]);
1552     current->is32|=1LL<<rt1[i];
1553   }
1554   else {
1555     set_const(current,rt1[i],((long long)((short)imm[i]))<<16); // LUI
1556     current->is32|=1LL<<rt1[i];
1557   }
1558   dirty_reg(current,rt1[i]);
1559 }
1560
1561 void load_alloc(struct regstat *current,int i)
1562 {
1563   clear_const(current,rt1[i]);
1564   //if(rs1[i]!=rt1[i]&&needed_again(rs1[i],i)) clear_const(current,rs1[i]); // Does this help or hurt?
1565   if(!rs1[i]) current->u&=~1LL; // Allow allocating r0 if it's the source register
1566   if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1567   if(rt1[i]) {
1568     alloc_reg(current,i,rt1[i]);
1569     if(opcode[i]==0x27||opcode[i]==0x37) // LWU/LD
1570     {
1571       current->is32&=~(1LL<<rt1[i]);
1572       alloc_reg64(current,i,rt1[i]);
1573     }
1574     else if(opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
1575     {
1576       current->is32&=~(1LL<<rt1[i]);
1577       alloc_reg64(current,i,rt1[i]);
1578       alloc_all(current,i);
1579       alloc_reg64(current,i,FTEMP);
1580     }
1581     else current->is32|=1LL<<rt1[i];
1582     dirty_reg(current,rt1[i]);
1583     // If using TLB, need a register for pointer to the mapping table
1584     if(using_tlb) alloc_reg(current,i,TLREG);
1585     // LWL/LWR need a temporary register for the old value
1586     if(opcode[i]==0x22||opcode[i]==0x26)
1587     {
1588       alloc_reg(current,i,FTEMP);
1589       alloc_reg_temp(current,i,-1);
1590     }
1591   }
1592   else
1593   {
1594     // Load to r0 (dummy load)
1595     // but we still need a register to calculate the address
1596     alloc_reg_temp(current,i,-1);
1597   }
1598 }
1599
1600 void store_alloc(struct regstat *current,int i)
1601 {
1602   clear_const(current,rs2[i]);
1603   if(!(rs2[i])) current->u&=~1LL; // Allow allocating r0 if necessary
1604   if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1605   alloc_reg(current,i,rs2[i]);
1606   if(opcode[i]==0x2c||opcode[i]==0x2d||opcode[i]==0x3f) { // 64-bit SDL/SDR/SD
1607     alloc_reg64(current,i,rs2[i]);
1608     if(rs2[i]) alloc_reg(current,i,FTEMP);
1609   }
1610   // If using TLB, need a register for pointer to the mapping table
1611   if(using_tlb) alloc_reg(current,i,TLREG);
1612   #if defined(HOST_IMM8)
1613   // On CPUs without 32-bit immediates we need a pointer to invalid_code
1614   else alloc_reg(current,i,INVCP);
1615   #endif
1616   if(opcode[i]==0x2c||opcode[i]==0x2d) { // 64-bit SDL/SDR
1617     alloc_reg(current,i,FTEMP);
1618   }
1619   // We need a temporary register for address generation
1620   alloc_reg_temp(current,i,-1);
1621 }
1622
1623 void c1ls_alloc(struct regstat *current,int i)
1624 {
1625   //clear_const(current,rs1[i]); // FIXME
1626   clear_const(current,rt1[i]);
1627   if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1628   alloc_reg(current,i,CSREG); // Status
1629   alloc_reg(current,i,FTEMP);
1630   if(opcode[i]==0x35||opcode[i]==0x3d) { // 64-bit LDC1/SDC1
1631     alloc_reg64(current,i,FTEMP);
1632   }
1633   // If using TLB, need a register for pointer to the mapping table
1634   if(using_tlb) alloc_reg(current,i,TLREG);
1635   #if defined(HOST_IMM8)
1636   // On CPUs without 32-bit immediates we need a pointer to invalid_code
1637   else if((opcode[i]&0x3b)==0x39) // SWC1/SDC1
1638     alloc_reg(current,i,INVCP);
1639   #endif
1640   // We need a temporary register for address generation
1641   alloc_reg_temp(current,i,-1);
1642 }
1643
1644 #ifndef multdiv_alloc
1645 void multdiv_alloc(struct regstat *current,int i)
1646 {
1647   //  case 0x18: MULT
1648   //  case 0x19: MULTU
1649   //  case 0x1A: DIV
1650   //  case 0x1B: DIVU
1651   //  case 0x1C: DMULT
1652   //  case 0x1D: DMULTU
1653   //  case 0x1E: DDIV
1654   //  case 0x1F: DDIVU
1655   clear_const(current,rs1[i]);
1656   clear_const(current,rs2[i]);
1657   if(rs1[i]&&rs2[i])
1658   {
1659     if((opcode2[i]&4)==0) // 32-bit
1660     {
1661       current->u&=~(1LL<<HIREG);
1662       current->u&=~(1LL<<LOREG);
1663       alloc_reg(current,i,HIREG);
1664       alloc_reg(current,i,LOREG);
1665       alloc_reg(current,i,rs1[i]);
1666       alloc_reg(current,i,rs2[i]);
1667       current->is32|=1LL<<HIREG;
1668       current->is32|=1LL<<LOREG;
1669       dirty_reg(current,HIREG);
1670       dirty_reg(current,LOREG);
1671     }
1672     else // 64-bit
1673     {
1674       current->u&=~(1LL<<HIREG);
1675       current->u&=~(1LL<<LOREG);
1676       current->uu&=~(1LL<<HIREG);
1677       current->uu&=~(1LL<<LOREG);
1678       alloc_reg64(current,i,HIREG);
1679       //if(HOST_REGS>10) alloc_reg64(current,i,LOREG);
1680       alloc_reg64(current,i,rs1[i]);
1681       alloc_reg64(current,i,rs2[i]);
1682       alloc_all(current,i);
1683       current->is32&=~(1LL<<HIREG);
1684       current->is32&=~(1LL<<LOREG);
1685       dirty_reg(current,HIREG);
1686       dirty_reg(current,LOREG);
1687     }
1688   }
1689   else
1690   {
1691     // Multiply by zero is zero.
1692     // MIPS does not have a divide by zero exception.
1693     // The result is undefined, we return zero.
1694     alloc_reg(current,i,HIREG);
1695     alloc_reg(current,i,LOREG);
1696     current->is32|=1LL<<HIREG;
1697     current->is32|=1LL<<LOREG;
1698     dirty_reg(current,HIREG);
1699     dirty_reg(current,LOREG);
1700   }
1701 }
1702 #endif
1703
1704 void cop0_alloc(struct regstat *current,int i)
1705 {
1706   if(opcode2[i]==0) // MFC0
1707   {
1708     if(rt1[i]) {
1709       clear_const(current,rt1[i]);
1710       alloc_all(current,i);
1711       alloc_reg(current,i,rt1[i]);
1712       current->is32|=1LL<<rt1[i];
1713       dirty_reg(current,rt1[i]);
1714     }
1715   }
1716   else if(opcode2[i]==4) // MTC0
1717   {
1718     if(rs1[i]){
1719       clear_const(current,rs1[i]);
1720       alloc_reg(current,i,rs1[i]);
1721       alloc_all(current,i);
1722     }
1723     else {
1724       alloc_all(current,i); // FIXME: Keep r0
1725       current->u&=~1LL;
1726       alloc_reg(current,i,0);
1727     }
1728   }
1729   else
1730   {
1731     // TLBR/TLBWI/TLBWR/TLBP/ERET
1732     assert(opcode2[i]==0x10);
1733     alloc_all(current,i);
1734   }
1735 }
1736
1737 void cop1_alloc(struct regstat *current,int i)
1738 {
1739   alloc_reg(current,i,CSREG); // Load status
1740   if(opcode2[i]<3) // MFC1/DMFC1/CFC1
1741   {
1742     assert(rt1[i]);
1743     clear_const(current,rt1[i]);
1744     if(opcode2[i]==1) {
1745       alloc_reg64(current,i,rt1[i]); // DMFC1
1746       current->is32&=~(1LL<<rt1[i]);
1747     }else{
1748       alloc_reg(current,i,rt1[i]); // MFC1/CFC1
1749       current->is32|=1LL<<rt1[i];
1750     }
1751     dirty_reg(current,rt1[i]);
1752     alloc_reg_temp(current,i,-1);
1753   }
1754   else if(opcode2[i]>3) // MTC1/DMTC1/CTC1
1755   {
1756     if(rs1[i]){
1757       clear_const(current,rs1[i]);
1758       if(opcode2[i]==5)
1759         alloc_reg64(current,i,rs1[i]); // DMTC1
1760       else
1761         alloc_reg(current,i,rs1[i]); // MTC1/CTC1
1762       alloc_reg_temp(current,i,-1);
1763     }
1764     else {
1765       current->u&=~1LL;
1766       alloc_reg(current,i,0);
1767       alloc_reg_temp(current,i,-1);
1768     }
1769   }
1770 }
1771 void fconv_alloc(struct regstat *current,int i)
1772 {
1773   alloc_reg(current,i,CSREG); // Load status
1774   alloc_reg_temp(current,i,-1);
1775 }
1776 void float_alloc(struct regstat *current,int i)
1777 {
1778   alloc_reg(current,i,CSREG); // Load status
1779   alloc_reg_temp(current,i,-1);
1780 }
1781 void fcomp_alloc(struct regstat *current,int i)
1782 {
1783   alloc_reg(current,i,CSREG); // Load status
1784   alloc_reg(current,i,FSREG); // Load flags
1785   dirty_reg(current,FSREG); // Flag will be modified
1786   alloc_reg_temp(current,i,-1);
1787 }
1788
1789 void syscall_alloc(struct regstat *current,int i)
1790 {
1791   alloc_cc(current,i);
1792   dirty_reg(current,CCREG);
1793   alloc_all(current,i);
1794   current->isconst=0;
1795 }
1796
1797 void delayslot_alloc(struct regstat *current,int i)
1798 {
1799   switch(itype[i]) {
1800     case UJUMP:
1801     case CJUMP:
1802     case SJUMP:
1803     case RJUMP:
1804     case FJUMP:
1805     case SYSCALL:
1806     case SPAN:
1807       assem_debug("jump in the delay slot.  this shouldn't happen.\n");//exit(1);
1808       printf("Disabled speculative precompilation\n");
1809       stop_after_jal=1;
1810       break;
1811     case IMM16:
1812       imm16_alloc(current,i);
1813       break;
1814     case LOAD:
1815     case LOADLR:
1816       load_alloc(current,i);
1817       break;
1818     case STORE:
1819     case STORELR:
1820       store_alloc(current,i);
1821       break;
1822     case ALU:
1823       alu_alloc(current,i);
1824       break;
1825     case SHIFT:
1826       shift_alloc(current,i);
1827       break;
1828     case MULTDIV:
1829       multdiv_alloc(current,i);
1830       break;
1831     case SHIFTIMM:
1832       shiftimm_alloc(current,i);
1833       break;
1834     case MOV:
1835       mov_alloc(current,i);
1836       break;
1837     case COP0:
1838       cop0_alloc(current,i);
1839       break;
1840     case COP1:
1841       cop1_alloc(current,i);
1842       break;
1843     case C1LS:
1844       c1ls_alloc(current,i);
1845       break;
1846     case FCONV:
1847       fconv_alloc(current,i);
1848       break;
1849     case FLOAT:
1850       float_alloc(current,i);
1851       break;
1852     case FCOMP:
1853       fcomp_alloc(current,i);
1854       break;
1855   }
1856 }
1857
1858 // Special case where a branch and delay slot span two pages in virtual memory
1859 static void pagespan_alloc(struct regstat *current,int i)
1860 {
1861   current->isconst=0;
1862   current->wasconst=0;
1863   regs[i].wasconst=0;
1864   alloc_all(current,i);
1865   alloc_cc(current,i);
1866   dirty_reg(current,CCREG);
1867   if(opcode[i]==3) // JAL
1868   {
1869     alloc_reg(current,i,31);
1870     dirty_reg(current,31);
1871   }
1872   if(opcode[i]==0&&(opcode2[i]&0x3E)==8) // JR/JALR
1873   {
1874     alloc_reg(current,i,rs1[i]);
1875     if (rt1[i]==31) {
1876       alloc_reg(current,i,31);
1877       dirty_reg(current,31);
1878     }
1879   }
1880   if((opcode[i]&0x2E)==4) // BEQ/BNE/BEQL/BNEL
1881   {
1882     if(rs1[i]) alloc_reg(current,i,rs1[i]);
1883     if(rs2[i]) alloc_reg(current,i,rs2[i]);
1884     if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1885     {
1886       if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1887       if(rs2[i]) alloc_reg64(current,i,rs2[i]);
1888     }
1889   }
1890   else
1891   if((opcode[i]&0x2E)==6) // BLEZ/BGTZ/BLEZL/BGTZL
1892   {
1893     if(rs1[i]) alloc_reg(current,i,rs1[i]);
1894     if(!((current->is32>>rs1[i])&1))
1895     {
1896       if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1897     }
1898   }
1899   else
1900   if(opcode[i]==0x11) // BC1
1901   {
1902     alloc_reg(current,i,FSREG);
1903     alloc_reg(current,i,CSREG);
1904   }
1905   //else ...
1906 }
1907
1908 add_stub(int type,int addr,int retaddr,int a,int b,int c,int d,int e)
1909 {
1910   stubs[stubcount][0]=type;
1911   stubs[stubcount][1]=addr;
1912   stubs[stubcount][2]=retaddr;
1913   stubs[stubcount][3]=a;
1914   stubs[stubcount][4]=b;
1915   stubs[stubcount][5]=c;
1916   stubs[stubcount][6]=d;
1917   stubs[stubcount][7]=e;
1918   stubcount++;
1919 }
1920
1921 // Write out a single register
1922 void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32)
1923 {
1924   int hr;
1925   for(hr=0;hr<HOST_REGS;hr++) {
1926     if(hr!=EXCLUDE_REG) {
1927       if((regmap[hr]&63)==r) {
1928         if((dirty>>hr)&1) {
1929           if(regmap[hr]<64) {
1930             emit_storereg(r,hr);
1931 #ifndef FORCE32
1932             if((is32>>regmap[hr])&1) {
1933               emit_sarimm(hr,31,hr);
1934               emit_storereg(r|64,hr);
1935             }
1936 #endif
1937           }else{
1938             emit_storereg(r|64,hr);
1939           }
1940         }
1941       }
1942     }
1943   }
1944 }
1945
1946 int mchecksum()
1947 {
1948   //if(!tracedebug) return 0;
1949   int i;
1950   int sum=0;
1951   for(i=0;i<2097152;i++) {
1952     unsigned int temp=sum;
1953     sum<<=1;
1954     sum|=(~temp)>>31;
1955     sum^=((u_int *)rdram)[i];
1956   }
1957   return sum;
1958 }
1959 int rchecksum()
1960 {
1961   int i;
1962   int sum=0;
1963   for(i=0;i<64;i++)
1964     sum^=((u_int *)reg)[i];
1965   return sum;
1966 }
1967 void rlist()
1968 {
1969   int i;
1970   printf("TRACE: ");
1971   for(i=0;i<32;i++)
1972     printf("r%d:%8x%8x ",i,((int *)(reg+i))[1],((int *)(reg+i))[0]);
1973   printf("\n");
1974 #ifndef DISABLE_COP1
1975   printf("TRACE: ");
1976   for(i=0;i<32;i++)
1977     printf("f%d:%8x%8x ",i,((int*)reg_cop1_simple[i])[1],*((int*)reg_cop1_simple[i]));
1978   printf("\n");
1979 #endif
1980 }
1981
1982 void enabletrace()
1983 {
1984   tracedebug=1;
1985 }
1986
1987 void memdebug(int i)
1988 {
1989   //printf("TRACE: count=%d next=%d (checksum %x) lo=%8x%8x\n",Count,next_interupt,mchecksum(),(int)(reg[LOREG]>>32),(int)reg[LOREG]);
1990   //printf("TRACE: count=%d next=%d (rchecksum %x)\n",Count,next_interupt,rchecksum());
1991   //rlist();
1992   //if(tracedebug) {
1993   //if(Count>=-2084597794) {
1994   if((signed int)Count>=-2084597794&&(signed int)Count<0) {
1995   //if(0) {
1996     printf("TRACE: count=%d next=%d (checksum %x)\n",Count,next_interupt,mchecksum());
1997     //printf("TRACE: count=%d next=%d (checksum %x) Status=%x\n",Count,next_interupt,mchecksum(),Status);
1998     //printf("TRACE: count=%d next=%d (checksum %x) hi=%8x%8x\n",Count,next_interupt,mchecksum(),(int)(reg[HIREG]>>32),(int)reg[HIREG]);
1999     rlist();
2000     #ifdef __i386__
2001     printf("TRACE: %x\n",(&i)[-1]);
2002     #endif
2003     #ifdef __arm__
2004     int j;
2005     printf("TRACE: %x \n",(&j)[10]);
2006     printf("TRACE: %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x\n",(&j)[1],(&j)[2],(&j)[3],(&j)[4],(&j)[5],(&j)[6],(&j)[7],(&j)[8],(&j)[9],(&j)[10],(&j)[11],(&j)[12],(&j)[13],(&j)[14],(&j)[15],(&j)[16],(&j)[17],(&j)[18],(&j)[19],(&j)[20]);
2007     #endif
2008     //fflush(stdout);
2009   }
2010   //printf("TRACE: %x\n",(&i)[-1]);
2011 }
2012
2013 void tlb_debug(u_int cause, u_int addr, u_int iaddr)
2014 {
2015   printf("TLB Exception: instruction=%x addr=%x cause=%x\n",iaddr, addr, cause);
2016 }
2017
2018 void alu_assemble(int i,struct regstat *i_regs)
2019 {
2020   if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
2021     if(rt1[i]) {
2022       signed char s1,s2,t;
2023       t=get_reg(i_regs->regmap,rt1[i]);
2024       if(t>=0) {
2025         s1=get_reg(i_regs->regmap,rs1[i]);
2026         s2=get_reg(i_regs->regmap,rs2[i]);
2027         if(rs1[i]&&rs2[i]) {
2028           assert(s1>=0);
2029           assert(s2>=0);
2030           if(opcode2[i]&2) emit_sub(s1,s2,t);
2031           else emit_add(s1,s2,t);
2032         }
2033         else if(rs1[i]) {
2034           if(s1>=0) emit_mov(s1,t);
2035           else emit_loadreg(rs1[i],t);
2036         }
2037         else if(rs2[i]) {
2038           if(s2>=0) {
2039             if(opcode2[i]&2) emit_neg(s2,t);
2040             else emit_mov(s2,t);
2041           }
2042           else {
2043             emit_loadreg(rs2[i],t);
2044             if(opcode2[i]&2) emit_neg(t,t);
2045           }
2046         }
2047         else emit_zeroreg(t);
2048       }
2049     }
2050   }
2051   if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU
2052     if(rt1[i]) {
2053       signed char s1l,s2l,s1h,s2h,tl,th;
2054       tl=get_reg(i_regs->regmap,rt1[i]);
2055       th=get_reg(i_regs->regmap,rt1[i]|64);
2056       if(tl>=0) {
2057         s1l=get_reg(i_regs->regmap,rs1[i]);
2058         s2l=get_reg(i_regs->regmap,rs2[i]);
2059         s1h=get_reg(i_regs->regmap,rs1[i]|64);
2060         s2h=get_reg(i_regs->regmap,rs2[i]|64);
2061         if(rs1[i]&&rs2[i]) {
2062           assert(s1l>=0);
2063           assert(s2l>=0);
2064           if(opcode2[i]&2) emit_subs(s1l,s2l,tl);
2065           else emit_adds(s1l,s2l,tl);
2066           if(th>=0) {
2067             #ifdef INVERTED_CARRY
2068             if(opcode2[i]&2) {if(s1h!=th) emit_mov(s1h,th);emit_sbb(th,s2h);}
2069             #else
2070             if(opcode2[i]&2) emit_sbc(s1h,s2h,th);
2071             #endif
2072             else emit_add(s1h,s2h,th);
2073           }
2074         }
2075         else if(rs1[i]) {
2076           if(s1l>=0) emit_mov(s1l,tl);
2077           else emit_loadreg(rs1[i],tl);
2078           if(th>=0) {
2079             if(s1h>=0) emit_mov(s1h,th);
2080             else emit_loadreg(rs1[i]|64,th);
2081           }
2082         }
2083         else if(rs2[i]) {
2084           if(s2l>=0) {
2085             if(opcode2[i]&2) emit_negs(s2l,tl);
2086             else emit_mov(s2l,tl);
2087           }
2088           else {
2089             emit_loadreg(rs2[i],tl);
2090             if(opcode2[i]&2) emit_negs(tl,tl);
2091           }
2092           if(th>=0) {
2093             #ifdef INVERTED_CARRY
2094             if(s2h>=0) emit_mov(s2h,th);
2095             else emit_loadreg(rs2[i]|64,th);
2096             if(opcode2[i]&2) {
2097               emit_adcimm(-1,th); // x86 has inverted carry flag
2098               emit_not(th,th);
2099             }
2100             #else
2101             if(opcode2[i]&2) {
2102               if(s2h>=0) emit_rscimm(s2h,0,th);
2103               else {
2104                 emit_loadreg(rs2[i]|64,th);
2105                 emit_rscimm(th,0,th);
2106               }
2107             }else{
2108               if(s2h>=0) emit_mov(s2h,th);
2109               else emit_loadreg(rs2[i]|64,th);
2110             }
2111             #endif
2112           }
2113         }
2114         else {
2115           emit_zeroreg(tl);
2116           if(th>=0) emit_zeroreg(th);
2117         }
2118       }
2119     }
2120   }
2121   if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU
2122     if(rt1[i]) {
2123       signed char s1l,s1h,s2l,s2h,t;
2124       if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1))
2125       {
2126         t=get_reg(i_regs->regmap,rt1[i]);
2127         //assert(t>=0);
2128         if(t>=0) {
2129           s1l=get_reg(i_regs->regmap,rs1[i]);
2130           s1h=get_reg(i_regs->regmap,rs1[i]|64);
2131           s2l=get_reg(i_regs->regmap,rs2[i]);
2132           s2h=get_reg(i_regs->regmap,rs2[i]|64);
2133           if(rs2[i]==0) // rx<r0
2134           {
2135             assert(s1h>=0);
2136             if(opcode2[i]==0x2a) // SLT
2137               emit_shrimm(s1h,31,t);
2138             else // SLTU (unsigned can not be less than zero)
2139               emit_zeroreg(t);
2140           }
2141           else if(rs1[i]==0) // r0<rx
2142           {
2143             assert(s2h>=0);
2144             if(opcode2[i]==0x2a) // SLT
2145               emit_set_gz64_32(s2h,s2l,t);
2146             else // SLTU (set if not zero)
2147               emit_set_nz64_32(s2h,s2l,t);
2148           }
2149           else {
2150             assert(s1l>=0);assert(s1h>=0);
2151             assert(s2l>=0);assert(s2h>=0);
2152             if(opcode2[i]==0x2a) // SLT
2153               emit_set_if_less64_32(s1h,s1l,s2h,s2l,t);
2154             else // SLTU
2155               emit_set_if_carry64_32(s1h,s1l,s2h,s2l,t);
2156           }
2157         }
2158       } else {
2159         t=get_reg(i_regs->regmap,rt1[i]);
2160         //assert(t>=0);
2161         if(t>=0) {
2162           s1l=get_reg(i_regs->regmap,rs1[i]);
2163           s2l=get_reg(i_regs->regmap,rs2[i]);
2164           if(rs2[i]==0) // rx<r0
2165           {
2166             assert(s1l>=0);
2167             if(opcode2[i]==0x2a) // SLT
2168               emit_shrimm(s1l,31,t);
2169             else // SLTU (unsigned can not be less than zero)
2170               emit_zeroreg(t);
2171           }
2172           else if(rs1[i]==0) // r0<rx
2173           {
2174             assert(s2l>=0);
2175             if(opcode2[i]==0x2a) // SLT
2176               emit_set_gz32(s2l,t);
2177             else // SLTU (set if not zero)
2178               emit_set_nz32(s2l,t);
2179           }
2180           else{
2181             assert(s1l>=0);assert(s2l>=0);
2182             if(opcode2[i]==0x2a) // SLT
2183               emit_set_if_less32(s1l,s2l,t);
2184             else // SLTU
2185               emit_set_if_carry32(s1l,s2l,t);
2186           }
2187         }
2188       }
2189     }
2190   }
2191   if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR
2192     if(rt1[i]) {
2193       signed char s1l,s1h,s2l,s2h,th,tl;
2194       tl=get_reg(i_regs->regmap,rt1[i]);
2195       th=get_reg(i_regs->regmap,rt1[i]|64);
2196       if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1)&&th>=0)
2197       {
2198         assert(tl>=0);
2199         if(tl>=0) {
2200           s1l=get_reg(i_regs->regmap,rs1[i]);
2201           s1h=get_reg(i_regs->regmap,rs1[i]|64);
2202           s2l=get_reg(i_regs->regmap,rs2[i]);
2203           s2h=get_reg(i_regs->regmap,rs2[i]|64);
2204           if(rs1[i]&&rs2[i]) {
2205             assert(s1l>=0);assert(s1h>=0);
2206             assert(s2l>=0);assert(s2h>=0);
2207             if(opcode2[i]==0x24) { // AND
2208               emit_and(s1l,s2l,tl);
2209               emit_and(s1h,s2h,th);
2210             } else
2211             if(opcode2[i]==0x25) { // OR
2212               emit_or(s1l,s2l,tl);
2213               emit_or(s1h,s2h,th);
2214             } else
2215             if(opcode2[i]==0x26) { // XOR
2216               emit_xor(s1l,s2l,tl);
2217               emit_xor(s1h,s2h,th);
2218             } else
2219             if(opcode2[i]==0x27) { // NOR
2220               emit_or(s1l,s2l,tl);
2221               emit_or(s1h,s2h,th);
2222               emit_not(tl,tl);
2223               emit_not(th,th);
2224             }
2225           }
2226           else
2227           {
2228             if(opcode2[i]==0x24) { // AND
2229               emit_zeroreg(tl);
2230               emit_zeroreg(th);
2231             } else
2232             if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR
2233               if(rs1[i]){
2234                 if(s1l>=0) emit_mov(s1l,tl);
2235                 else emit_loadreg(rs1[i],tl);
2236                 if(s1h>=0) emit_mov(s1h,th);
2237                 else emit_loadreg(rs1[i]|64,th);
2238               }
2239               else
2240               if(rs2[i]){
2241                 if(s2l>=0) emit_mov(s2l,tl);
2242                 else emit_loadreg(rs2[i],tl);
2243                 if(s2h>=0) emit_mov(s2h,th);
2244                 else emit_loadreg(rs2[i]|64,th);
2245               }
2246               else{
2247                 emit_zeroreg(tl);
2248                 emit_zeroreg(th);
2249               }
2250             } else
2251             if(opcode2[i]==0x27) { // NOR
2252               if(rs1[i]){
2253                 if(s1l>=0) emit_not(s1l,tl);
2254                 else{
2255                   emit_loadreg(rs1[i],tl);
2256                   emit_not(tl,tl);
2257                 }
2258                 if(s1h>=0) emit_not(s1h,th);
2259                 else{
2260                   emit_loadreg(rs1[i]|64,th);
2261                   emit_not(th,th);
2262                 }
2263               }
2264               else
2265               if(rs2[i]){
2266                 if(s2l>=0) emit_not(s2l,tl);
2267                 else{
2268                   emit_loadreg(rs2[i],tl);
2269                   emit_not(tl,tl);
2270                 }
2271                 if(s2h>=0) emit_not(s2h,th);
2272                 else{
2273                   emit_loadreg(rs2[i]|64,th);
2274                   emit_not(th,th);
2275                 }
2276               }
2277               else {
2278                 emit_movimm(-1,tl);
2279                 emit_movimm(-1,th);
2280               }
2281             }
2282           }
2283         }
2284       }
2285       else
2286       {
2287         // 32 bit
2288         if(tl>=0) {
2289           s1l=get_reg(i_regs->regmap,rs1[i]);
2290           s2l=get_reg(i_regs->regmap,rs2[i]);
2291           if(rs1[i]&&rs2[i]) {
2292             assert(s1l>=0);
2293             assert(s2l>=0);
2294             if(opcode2[i]==0x24) { // AND
2295               emit_and(s1l,s2l,tl);
2296             } else
2297             if(opcode2[i]==0x25) { // OR
2298               emit_or(s1l,s2l,tl);
2299             } else
2300             if(opcode2[i]==0x26) { // XOR
2301               emit_xor(s1l,s2l,tl);
2302             } else
2303             if(opcode2[i]==0x27) { // NOR
2304               emit_or(s1l,s2l,tl);
2305               emit_not(tl,tl);
2306             }
2307           }
2308           else
2309           {
2310             if(opcode2[i]==0x24) { // AND
2311               emit_zeroreg(tl);
2312             } else
2313             if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR
2314               if(rs1[i]){
2315                 if(s1l>=0) emit_mov(s1l,tl);
2316                 else emit_loadreg(rs1[i],tl); // CHECK: regmap_entry?
2317               }
2318               else
2319               if(rs2[i]){
2320                 if(s2l>=0) emit_mov(s2l,tl);
2321                 else emit_loadreg(rs2[i],tl); // CHECK: regmap_entry?
2322               }
2323               else emit_zeroreg(tl);
2324             } else
2325             if(opcode2[i]==0x27) { // NOR
2326               if(rs1[i]){
2327                 if(s1l>=0) emit_not(s1l,tl);
2328                 else {
2329                   emit_loadreg(rs1[i],tl);
2330                   emit_not(tl,tl);
2331                 }
2332               }
2333               else
2334               if(rs2[i]){
2335                 if(s2l>=0) emit_not(s2l,tl);
2336                 else {
2337                   emit_loadreg(rs2[i],tl);
2338                   emit_not(tl,tl);
2339                 }
2340               }
2341               else emit_movimm(-1,tl);
2342             }
2343           }
2344         }
2345       }
2346     }
2347   }
2348 }
2349
2350 void imm16_assemble(int i,struct regstat *i_regs)
2351 {
2352   if (opcode[i]==0x0f) { // LUI
2353     if(rt1[i]) {
2354       signed char t;
2355       t=get_reg(i_regs->regmap,rt1[i]);
2356       //assert(t>=0);
2357       if(t>=0) {
2358         if(!((i_regs->isconst>>t)&1))
2359           emit_movimm(imm[i]<<16,t);
2360       }
2361     }
2362   }
2363   if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU
2364     if(rt1[i]) {
2365       signed char s,t;
2366       t=get_reg(i_regs->regmap,rt1[i]);
2367       s=get_reg(i_regs->regmap,rs1[i]);
2368       if(rs1[i]) {
2369         //assert(t>=0);
2370         //assert(s>=0);
2371         if(t>=0) {
2372           if(!((i_regs->isconst>>t)&1)) {
2373             if(s<0) {
2374               if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2375               emit_addimm(t,imm[i],t);
2376             }else{
2377               if(!((i_regs->wasconst>>s)&1))
2378                 emit_addimm(s,imm[i],t);
2379               else
2380                 emit_movimm(constmap[i][s]+imm[i],t);
2381             }
2382           }
2383         }
2384       } else {
2385         if(t>=0) {
2386           if(!((i_regs->isconst>>t)&1))
2387             emit_movimm(imm[i],t);
2388         }
2389       }
2390     }
2391   }
2392   if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU
2393     if(rt1[i]) {
2394       signed char sh,sl,th,tl;
2395       th=get_reg(i_regs->regmap,rt1[i]|64);
2396       tl=get_reg(i_regs->regmap,rt1[i]);
2397       sh=get_reg(i_regs->regmap,rs1[i]|64);
2398       sl=get_reg(i_regs->regmap,rs1[i]);
2399       if(tl>=0) {
2400         if(rs1[i]) {
2401           assert(sh>=0);
2402           assert(sl>=0);
2403           if(th>=0) {
2404             emit_addimm64_32(sh,sl,imm[i],th,tl);
2405           }
2406           else {
2407             emit_addimm(sl,imm[i],tl);
2408           }
2409         } else {
2410           emit_movimm(imm[i],tl);
2411           if(th>=0) emit_movimm(((signed int)imm[i])>>31,th);
2412         }
2413       }
2414     }
2415   }
2416   else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU
2417     if(rt1[i]) {
2418       //assert(rs1[i]!=0); // r0 might be valid, but it's probably a bug
2419       signed char sh,sl,t;
2420       t=get_reg(i_regs->regmap,rt1[i]);
2421       sh=get_reg(i_regs->regmap,rs1[i]|64);
2422       sl=get_reg(i_regs->regmap,rs1[i]);
2423       //assert(t>=0);
2424       if(t>=0) {
2425         if(rs1[i]>0) {
2426           if(sh<0) assert((i_regs->was32>>rs1[i])&1);
2427           if(sh<0||((i_regs->was32>>rs1[i])&1)) {
2428             if(opcode[i]==0x0a) { // SLTI
2429               if(sl<0) {
2430                 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2431                 emit_slti32(t,imm[i],t);
2432               }else{
2433                 emit_slti32(sl,imm[i],t);
2434               }
2435             }
2436             else { // SLTIU
2437               if(sl<0) {
2438                 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2439                 emit_sltiu32(t,imm[i],t);
2440               }else{
2441                 emit_sltiu32(sl,imm[i],t);
2442               }
2443             }
2444           }else{ // 64-bit
2445             assert(sl>=0);
2446             if(opcode[i]==0x0a) // SLTI
2447               emit_slti64_32(sh,sl,imm[i],t);
2448             else // SLTIU
2449               emit_sltiu64_32(sh,sl,imm[i],t);
2450           }
2451         }else{
2452           // SLTI(U) with r0 is just stupid,
2453           // nonetheless examples can be found
2454           if(opcode[i]==0x0a) // SLTI
2455             if(0<imm[i]) emit_movimm(1,t);
2456             else emit_zeroreg(t);
2457           else // SLTIU
2458           {
2459             if(imm[i]) emit_movimm(1,t);
2460             else emit_zeroreg(t);
2461           }
2462         }
2463       }
2464     }
2465   }
2466   else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI
2467     if(rt1[i]) {
2468       signed char sh,sl,th,tl;
2469       th=get_reg(i_regs->regmap,rt1[i]|64);
2470       tl=get_reg(i_regs->regmap,rt1[i]);
2471       sh=get_reg(i_regs->regmap,rs1[i]|64);
2472       sl=get_reg(i_regs->regmap,rs1[i]);
2473       if(tl>=0 && !((i_regs->isconst>>tl)&1)) {
2474         if(opcode[i]==0x0c) //ANDI
2475         {
2476           if(rs1[i]) {
2477             if(sl<0) {
2478               if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl);
2479               emit_andimm(tl,imm[i],tl);
2480             }else{
2481               if(!((i_regs->wasconst>>sl)&1))
2482                 emit_andimm(sl,imm[i],tl);
2483               else
2484                 emit_movimm(constmap[i][sl]&imm[i],tl);
2485             }
2486           }
2487           else
2488             emit_zeroreg(tl);
2489           if(th>=0) emit_zeroreg(th);
2490         }
2491         else
2492         {
2493           if(rs1[i]) {
2494             if(sl<0) {
2495               if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl);
2496             }
2497             if(th>=0) {
2498               if(sh<0) {
2499                 emit_loadreg(rs1[i]|64,th);
2500               }else{
2501                 emit_mov(sh,th);
2502               }
2503             }
2504             if(opcode[i]==0x0d) //ORI
2505             if(sl<0) {
2506               emit_orimm(tl,imm[i],tl);
2507             }else{
2508               if(!((i_regs->wasconst>>sl)&1))
2509                 emit_orimm(sl,imm[i],tl);
2510               else
2511                 emit_movimm(constmap[i][sl]|imm[i],tl);
2512             }
2513             if(opcode[i]==0x0e) //XORI
2514             if(sl<0) {
2515               emit_xorimm(tl,imm[i],tl);
2516             }else{
2517               if(!((i_regs->wasconst>>sl)&1))
2518                 emit_xorimm(sl,imm[i],tl);
2519               else
2520                 emit_movimm(constmap[i][sl]^imm[i],tl);
2521             }
2522           }
2523           else {
2524             emit_movimm(imm[i],tl);
2525             if(th>=0) emit_zeroreg(th);
2526           }
2527         }
2528       }
2529     }
2530   }
2531 }
2532
2533 void shiftimm_assemble(int i,struct regstat *i_regs)
2534 {
2535   if(opcode2[i]<=0x3) // SLL/SRL/SRA
2536   {
2537     if(rt1[i]) {
2538       signed char s,t;
2539       t=get_reg(i_regs->regmap,rt1[i]);
2540       s=get_reg(i_regs->regmap,rs1[i]);
2541       //assert(t>=0);
2542       if(t>=0){
2543         if(rs1[i]==0)
2544         {
2545           emit_zeroreg(t);
2546         }
2547         else
2548         {
2549           if(s<0&&i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2550           if(imm[i]) {
2551             if(opcode2[i]==0) // SLL
2552             {
2553               emit_shlimm(s<0?t:s,imm[i],t);
2554             }
2555             if(opcode2[i]==2) // SRL
2556             {
2557               emit_shrimm(s<0?t:s,imm[i],t);
2558             }
2559             if(opcode2[i]==3) // SRA
2560             {
2561               emit_sarimm(s<0?t:s,imm[i],t);
2562             }
2563           }else{
2564             // Shift by zero
2565             if(s>=0 && s!=t) emit_mov(s,t);
2566           }
2567         }
2568       }
2569       //emit_storereg(rt1[i],t); //DEBUG
2570     }
2571   }
2572   if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA
2573   {
2574     if(rt1[i]) {
2575       signed char sh,sl,th,tl;
2576       th=get_reg(i_regs->regmap,rt1[i]|64);
2577       tl=get_reg(i_regs->regmap,rt1[i]);
2578       sh=get_reg(i_regs->regmap,rs1[i]|64);
2579       sl=get_reg(i_regs->regmap,rs1[i]);
2580       if(tl>=0) {
2581         if(rs1[i]==0)
2582         {
2583           emit_zeroreg(tl);
2584           if(th>=0) emit_zeroreg(th);
2585         }
2586         else
2587         {
2588           assert(sl>=0);
2589           assert(sh>=0);
2590           if(imm[i]) {
2591             if(opcode2[i]==0x38) // DSLL
2592             {
2593               if(th>=0) emit_shldimm(sh,sl,imm[i],th);
2594               emit_shlimm(sl,imm[i],tl);
2595             }
2596             if(opcode2[i]==0x3a) // DSRL
2597             {
2598               emit_shrdimm(sl,sh,imm[i],tl);
2599               if(th>=0) emit_shrimm(sh,imm[i],th);
2600             }
2601             if(opcode2[i]==0x3b) // DSRA
2602             {
2603               emit_shrdimm(sl,sh,imm[i],tl);
2604               if(th>=0) emit_sarimm(sh,imm[i],th);
2605             }
2606           }else{
2607             // Shift by zero
2608             if(sl!=tl) emit_mov(sl,tl);
2609             if(th>=0&&sh!=th) emit_mov(sh,th);
2610           }
2611         }
2612       }
2613     }
2614   }
2615   if(opcode2[i]==0x3c) // DSLL32
2616   {
2617     if(rt1[i]) {
2618       signed char sl,tl,th;
2619       tl=get_reg(i_regs->regmap,rt1[i]);
2620       th=get_reg(i_regs->regmap,rt1[i]|64);
2621       sl=get_reg(i_regs->regmap,rs1[i]);
2622       if(th>=0||tl>=0){
2623         assert(tl>=0);
2624         assert(th>=0);
2625         assert(sl>=0);
2626         emit_mov(sl,th);
2627         emit_zeroreg(tl);
2628         if(imm[i]>32)
2629         {
2630           emit_shlimm(th,imm[i]&31,th);
2631         }
2632       }
2633     }
2634   }
2635   if(opcode2[i]==0x3e) // DSRL32
2636   {
2637     if(rt1[i]) {
2638       signed char sh,tl,th;
2639       tl=get_reg(i_regs->regmap,rt1[i]);
2640       th=get_reg(i_regs->regmap,rt1[i]|64);
2641       sh=get_reg(i_regs->regmap,rs1[i]|64);
2642       if(tl>=0){
2643         assert(sh>=0);
2644         emit_mov(sh,tl);
2645         if(th>=0) emit_zeroreg(th);
2646         if(imm[i]>32)
2647         {
2648           emit_shrimm(tl,imm[i]&31,tl);
2649         }
2650       }
2651     }
2652   }
2653   if(opcode2[i]==0x3f) // DSRA32
2654   {
2655     if(rt1[i]) {
2656       signed char sh,tl;
2657       tl=get_reg(i_regs->regmap,rt1[i]);
2658       sh=get_reg(i_regs->regmap,rs1[i]|64);
2659       if(tl>=0){
2660         assert(sh>=0);
2661         emit_mov(sh,tl);
2662         if(imm[i]>32)
2663         {
2664           emit_sarimm(tl,imm[i]&31,tl);
2665         }
2666       }
2667     }
2668   }
2669 }
2670
2671 #ifndef shift_assemble
2672 void shift_assemble(int i,struct regstat *i_regs)
2673 {
2674   printf("Need shift_assemble for this architecture.\n");
2675   exit(1);
2676 }
2677 #endif
2678
2679 void load_assemble(int i,struct regstat *i_regs)
2680 {
2681   int s,th,tl,addr,map=-1;
2682   int offset;
2683   int jaddr=0;
2684   int memtarget,c=0;
2685   u_int hr,reglist=0;
2686   th=get_reg(i_regs->regmap,rt1[i]|64);
2687   tl=get_reg(i_regs->regmap,rt1[i]);
2688   s=get_reg(i_regs->regmap,rs1[i]);
2689   offset=imm[i];
2690   for(hr=0;hr<HOST_REGS;hr++) {
2691     if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
2692   }
2693   if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
2694   if(s>=0) {
2695     c=(i_regs->wasconst>>s)&1;
2696     memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80800000;
2697     if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
2698   }
2699   if(offset||s<0||c) addr=tl;
2700   else addr=s;
2701   //printf("load_assemble: c=%d\n",c);
2702   //if(c) printf("load_assemble: const=%x\n",(int)constmap[i][s]+offset);
2703   // FIXME: Even if the load is a NOP, we should check for pagefaults...
2704   if(tl>=0) {
2705     //assert(tl>=0);
2706     //assert(rt1[i]);
2707     reglist&=~(1<<tl);
2708     if(th>=0) reglist&=~(1<<th);
2709     if(!using_tlb) {
2710       if(!c) {
2711 //#define R29_HACK 1
2712         #ifdef R29_HACK
2713         // Strmnnrmn's speed hack
2714         if(rs1[i]!=29||start<0x80001000||start>=0x80800000)
2715         #endif
2716         {
2717           emit_cmpimm(addr,0x800000);
2718           jaddr=(int)out;
2719           #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
2720           // Hint to branch predictor that the branch is unlikely to be taken
2721           if(rs1[i]>=28)
2722             emit_jno_unlikely(0);
2723           else
2724           #endif
2725           emit_jno(0);
2726         }
2727       }
2728     }else{ // using tlb
2729       int x=0;
2730       if (opcode[i]==0x20||opcode[i]==0x24) x=3; // LB/LBU
2731       if (opcode[i]==0x21||opcode[i]==0x25) x=2; // LH/LHU
2732       map=get_reg(i_regs->regmap,TLREG);
2733       assert(map>=0);
2734       map=do_tlb_r(addr,tl,map,x,-1,-1,c,constmap[i][s]+offset);
2735       do_tlb_r_branch(map,c,constmap[i][s]+offset,&jaddr);
2736     }
2737     if (opcode[i]==0x20) { // LB
2738       if(!c||memtarget) {
2739         #ifdef HOST_IMM_ADDR32
2740         if(c)
2741           emit_movsbl_tlb((constmap[i][s]+offset)^3,map,tl);
2742         else
2743         #endif
2744         {
2745           //emit_xorimm(addr,3,tl);
2746           //gen_tlb_addr_r(tl,map);
2747           //emit_movsbl_indexed((int)rdram-0x80000000,tl,tl);
2748           int x=0;
2749           if(!c) emit_xorimm(addr,3,tl);
2750           else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2751           emit_movsbl_indexed_tlb(x,tl,map,tl);
2752         }
2753         if(jaddr)
2754           add_stub(LOADB_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2755       }
2756       else
2757         inline_readstub(LOADB_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2758     }
2759     if (opcode[i]==0x21) { // LH
2760       if(!c||memtarget) {
2761         #ifdef HOST_IMM_ADDR32
2762         if(c)
2763           emit_movswl_tlb((constmap[i][s]+offset)^2,map,tl);
2764         else
2765         #endif
2766         {
2767           int x=0;
2768           if(!c) emit_xorimm(addr,2,tl);
2769           else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
2770           //#ifdef
2771           //emit_movswl_indexed_tlb(x,tl,map,tl);
2772           //else
2773           if(map>=0) {
2774             gen_tlb_addr_r(tl,map);
2775             emit_movswl_indexed(x,tl,tl);
2776           }else
2777             emit_movswl_indexed((int)rdram-0x80000000+x,tl,tl);
2778         }
2779         if(jaddr)
2780           add_stub(LOADH_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2781       }
2782       else
2783         inline_readstub(LOADH_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2784     }
2785     if (opcode[i]==0x23) { // LW
2786       if(!c||memtarget) {
2787         //emit_readword_indexed((int)rdram-0x80000000,addr,tl);
2788         #ifdef HOST_IMM_ADDR32
2789         if(c)
2790           emit_readword_tlb(constmap[i][s]+offset,map,tl);
2791         else
2792         #endif
2793         emit_readword_indexed_tlb(0,addr,map,tl);
2794         if(jaddr)
2795           add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2796       }
2797       else
2798         inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2799     }
2800     if (opcode[i]==0x24) { // LBU
2801       if(!c||memtarget) {
2802         #ifdef HOST_IMM_ADDR32
2803         if(c)
2804           emit_movzbl_tlb((constmap[i][s]+offset)^3,map,tl);
2805         else
2806         #endif
2807         {
2808           //emit_xorimm(addr,3,tl);
2809           //gen_tlb_addr_r(tl,map);
2810           //emit_movzbl_indexed((int)rdram-0x80000000,tl,tl);
2811           int x=0;
2812           if(!c) emit_xorimm(addr,3,tl);
2813           else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2814           emit_movzbl_indexed_tlb(x,tl,map,tl);
2815         }
2816         if(jaddr)
2817           add_stub(LOADBU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2818       }
2819       else
2820         inline_readstub(LOADBU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2821     }
2822     if (opcode[i]==0x25) { // LHU
2823       if(!c||memtarget) {
2824         #ifdef HOST_IMM_ADDR32
2825         if(c)
2826           emit_movzwl_tlb((constmap[i][s]+offset)^2,map,tl);
2827         else
2828         #endif
2829         {
2830           int x=0;
2831           if(!c) emit_xorimm(addr,2,tl);
2832           else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
2833           //#ifdef
2834           //emit_movzwl_indexed_tlb(x,tl,map,tl);
2835           //#else
2836           if(map>=0) {
2837             gen_tlb_addr_r(tl,map);
2838             emit_movzwl_indexed(x,tl,tl);
2839           }else
2840             emit_movzwl_indexed((int)rdram-0x80000000+x,tl,tl);
2841           if(jaddr)
2842             add_stub(LOADHU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2843         }
2844       }
2845       else
2846         inline_readstub(LOADHU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2847     }
2848     if (opcode[i]==0x27) { // LWU
2849       assert(th>=0);
2850       if(!c||memtarget) {
2851         //emit_readword_indexed((int)rdram-0x80000000,addr,tl);
2852         #ifdef HOST_IMM_ADDR32
2853         if(c)
2854           emit_readword_tlb(constmap[i][s]+offset,map,tl);
2855         else
2856         #endif
2857         emit_readword_indexed_tlb(0,addr,map,tl);
2858         if(jaddr)
2859           add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2860       }
2861       else {
2862         inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2863       }
2864       emit_zeroreg(th);
2865     }
2866     if (opcode[i]==0x37) { // LD
2867       if(!c||memtarget) {
2868         //gen_tlb_addr_r(tl,map);
2869         //if(th>=0) emit_readword_indexed((int)rdram-0x80000000,addr,th);
2870         //emit_readword_indexed((int)rdram-0x7FFFFFFC,addr,tl);
2871         #ifdef HOST_IMM_ADDR32
2872         if(c)
2873           emit_readdword_tlb(constmap[i][s]+offset,map,th,tl);
2874         else
2875         #endif
2876         emit_readdword_indexed_tlb(0,addr,map,th,tl);
2877         if(jaddr)
2878           add_stub(LOADD_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2879       }
2880       else
2881         inline_readstub(LOADD_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2882     }
2883     //emit_storereg(rt1[i],tl); // DEBUG
2884   }
2885   //if(opcode[i]==0x23)
2886   //if(opcode[i]==0x24)
2887   //if(opcode[i]==0x23||opcode[i]==0x24)
2888   /*if(opcode[i]==0x21||opcode[i]==0x23||opcode[i]==0x24)
2889   {
2890     //emit_pusha();
2891     save_regs(0x100f);
2892         emit_readword((int)&last_count,ECX);
2893         #ifdef __i386__
2894         if(get_reg(i_regs->regmap,CCREG)<0)
2895           emit_loadreg(CCREG,HOST_CCREG);
2896         emit_add(HOST_CCREG,ECX,HOST_CCREG);
2897         emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
2898         emit_writeword(HOST_CCREG,(int)&Count);
2899         #endif
2900         #ifdef __arm__
2901         if(get_reg(i_regs->regmap,CCREG)<0)
2902           emit_loadreg(CCREG,0);
2903         else
2904           emit_mov(HOST_CCREG,0);
2905         emit_add(0,ECX,0);
2906         emit_addimm(0,2*ccadj[i],0);
2907         emit_writeword(0,(int)&Count);
2908         #endif
2909     emit_call((int)memdebug);
2910     //emit_popa();
2911     restore_regs(0x100f);
2912   }/**/
2913 }
2914
2915 #ifndef loadlr_assemble
2916 void loadlr_assemble(int i,struct regstat *i_regs)
2917 {
2918   printf("Need loadlr_assemble for this architecture.\n");
2919   exit(1);
2920 }
2921 #endif
2922
2923 void store_assemble(int i,struct regstat *i_regs)
2924 {
2925   int s,th,tl,map=-1;
2926   int addr,temp;
2927   int offset;
2928   int jaddr=0,jaddr2,type;
2929   int memtarget,c=0;
2930   int agr=AGEN1+(i&1);
2931   u_int hr,reglist=0;
2932   th=get_reg(i_regs->regmap,rs2[i]|64);
2933   tl=get_reg(i_regs->regmap,rs2[i]);
2934   s=get_reg(i_regs->regmap,rs1[i]);
2935   temp=get_reg(i_regs->regmap,agr);
2936   if(temp<0) temp=get_reg(i_regs->regmap,-1);
2937   offset=imm[i];
2938   if(s>=0) {
2939     c=(i_regs->wasconst>>s)&1;
2940     memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80800000;
2941     if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
2942   }
2943   assert(tl>=0);
2944   assert(temp>=0);
2945   for(hr=0;hr<HOST_REGS;hr++) {
2946     if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
2947   }
2948   if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
2949   if(offset||s<0||c) addr=temp;
2950   else addr=s;
2951   if(!using_tlb) {
2952     if(!c) {
2953       #ifdef R29_HACK
2954       // Strmnnrmn's speed hack
2955       memtarget=1;
2956       if(rs1[i]!=29||start<0x80001000||start>=0x80800000)
2957       #endif
2958       emit_cmpimm(addr,0x800000);
2959       #ifdef DESTRUCTIVE_SHIFT
2960       if(s==addr) emit_mov(s,temp);
2961       #endif
2962       #ifdef R29_HACK
2963       if(rs1[i]!=29||start<0x80001000||start>=0x80800000)
2964       #endif
2965       {
2966         jaddr=(int)out;
2967         #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
2968         // Hint to branch predictor that the branch is unlikely to be taken
2969         if(rs1[i]>=28)
2970           emit_jno_unlikely(0);
2971         else
2972         #endif
2973         emit_jno(0);
2974       }
2975     }
2976   }else{ // using tlb
2977     int x=0;
2978     if (opcode[i]==0x28) x=3; // SB
2979     if (opcode[i]==0x29) x=2; // SH
2980     map=get_reg(i_regs->regmap,TLREG);
2981     assert(map>=0);
2982     map=do_tlb_w(addr,temp,map,x,c,constmap[i][s]+offset);
2983     do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr);
2984   }
2985
2986   if (opcode[i]==0x28) { // SB
2987     if(!c||memtarget) {
2988       int x=0;
2989       if(!c) emit_xorimm(addr,3,temp);
2990       else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2991       //gen_tlb_addr_w(temp,map);
2992       //emit_writebyte_indexed(tl,(int)rdram-0x80000000,temp);
2993       emit_writebyte_indexed_tlb(tl,x,temp,map,temp);
2994     }
2995     type=STOREB_STUB;
2996   }
2997   if (opcode[i]==0x29) { // SH
2998     if(!c||memtarget) {
2999       int x=0;
3000       if(!c) emit_xorimm(addr,2,temp);
3001       else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
3002       //#ifdef
3003       //emit_writehword_indexed_tlb(tl,x,temp,map,temp);
3004       //#else
3005       if(map>=0) {
3006         gen_tlb_addr_w(temp,map);
3007         emit_writehword_indexed(tl,x,temp);
3008       }else
3009         emit_writehword_indexed(tl,(int)rdram-0x80000000+x,temp);
3010     }
3011     type=STOREH_STUB;
3012   }
3013   if (opcode[i]==0x2B) { // SW
3014     if(!c||memtarget)
3015       //emit_writeword_indexed(tl,(int)rdram-0x80000000,addr);
3016       emit_writeword_indexed_tlb(tl,0,addr,map,temp);
3017     type=STOREW_STUB;
3018   }
3019   if (opcode[i]==0x3F) { // SD
3020     if(!c||memtarget) {
3021       if(rs2[i]) {
3022         assert(th>=0);
3023         //emit_writeword_indexed(th,(int)rdram-0x80000000,addr);
3024         //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,addr);
3025         emit_writedword_indexed_tlb(th,tl,0,addr,map,temp);
3026       }else{
3027         // Store zero
3028         //emit_writeword_indexed(tl,(int)rdram-0x80000000,temp);
3029         //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,temp);
3030         emit_writedword_indexed_tlb(tl,tl,0,addr,map,temp);
3031       }
3032     }
3033     type=STORED_STUB;
3034   }
3035   if(jaddr) {
3036     add_stub(type,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3037   } else if(!memtarget) {
3038     inline_writestub(type,i,constmap[i][s]+offset,i_regs->regmap,rs2[i],ccadj[i],reglist);
3039   }
3040   if(!using_tlb) {
3041     if(!c||memtarget) {
3042       #ifdef DESTRUCTIVE_SHIFT
3043       // The x86 shift operation is 'destructive'; it overwrites the
3044       // source register, so we need to make a copy first and use that.
3045       addr=temp;
3046       #endif
3047       #if defined(HOST_IMM8)
3048       int ir=get_reg(i_regs->regmap,INVCP);
3049       assert(ir>=0);
3050       emit_cmpmem_indexedsr12_reg(ir,addr,1);
3051       #else
3052       emit_cmpmem_indexedsr12_imm((int)invalid_code,addr,1);
3053       #endif
3054       jaddr2=(int)out;
3055       emit_jne(0);
3056       add_stub(INVCODE_STUB,jaddr2,(int)out,reglist|(1<<HOST_CCREG),addr,0,0,0);
3057     }
3058   }
3059   //if(opcode[i]==0x2B || opcode[i]==0x3F)
3060   //if(opcode[i]==0x2B || opcode[i]==0x28)
3061   //if(opcode[i]==0x2B || opcode[i]==0x29)
3062   //if(opcode[i]==0x2B)
3063   /*if(opcode[i]==0x2B || opcode[i]==0x28 || opcode[i]==0x29 || opcode[i]==0x3F)
3064   {
3065     //emit_pusha();
3066     save_regs(0x100f);
3067         emit_readword((int)&last_count,ECX);
3068         #ifdef __i386__
3069         if(get_reg(i_regs->regmap,CCREG)<0)
3070           emit_loadreg(CCREG,HOST_CCREG);
3071         emit_add(HOST_CCREG,ECX,HOST_CCREG);
3072         emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3073         emit_writeword(HOST_CCREG,(int)&Count);
3074         #endif
3075         #ifdef __arm__
3076         if(get_reg(i_regs->regmap,CCREG)<0)
3077           emit_loadreg(CCREG,0);
3078         else
3079           emit_mov(HOST_CCREG,0);
3080         emit_add(0,ECX,0);
3081         emit_addimm(0,2*ccadj[i],0);
3082         emit_writeword(0,(int)&Count);
3083         #endif
3084     emit_call((int)memdebug);
3085     //emit_popa();
3086     restore_regs(0x100f);
3087   }/**/
3088 }
3089
3090 void storelr_assemble(int i,struct regstat *i_regs)
3091 {
3092   int s,th,tl;
3093   int temp;
3094   int temp2;
3095   int offset;
3096   int jaddr=0,jaddr2;
3097   int case1,case2,case3;
3098   int done0,done1,done2;
3099   int memtarget,c=0;
3100   u_int hr,reglist=0;
3101   th=get_reg(i_regs->regmap,rs2[i]|64);
3102   tl=get_reg(i_regs->regmap,rs2[i]);
3103   s=get_reg(i_regs->regmap,rs1[i]);
3104   temp=get_reg(i_regs->regmap,-1);
3105   offset=imm[i];
3106   if(s>=0) {
3107     c=(i_regs->isconst>>s)&1;
3108     memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80800000;
3109     if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
3110   }
3111   assert(tl>=0);
3112   for(hr=0;hr<HOST_REGS;hr++) {
3113     if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3114   }
3115   if(tl>=0) {
3116     assert(temp>=0);
3117     if(!using_tlb) {
3118       if(!c) {
3119         emit_cmpimm(s<0||offset?temp:s,0x800000);
3120         if(!offset&&s!=temp) emit_mov(s,temp);
3121         jaddr=(int)out;
3122         emit_jno(0);
3123       }
3124       else
3125       {
3126         if(!memtarget||!rs1[i]) {
3127           jaddr=(int)out;
3128           emit_jmp(0);
3129         }
3130       }
3131       if((u_int)rdram!=0x80000000)
3132         emit_addimm_no_flags((u_int)rdram-(u_int)0x80000000,temp);
3133     }else{ // using tlb
3134       int map=get_reg(i_regs->regmap,TLREG);
3135       assert(map>=0);
3136       map=do_tlb_w(c||s<0||offset?temp:s,temp,map,0,c,constmap[i][s]+offset);
3137       if(!c&&!offset&&s>=0) emit_mov(s,temp);
3138       do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr);
3139       if(!jaddr&&!memtarget) {
3140         jaddr=(int)out;
3141         emit_jmp(0);
3142       }
3143       gen_tlb_addr_w(temp,map);
3144     }
3145
3146     if (opcode[i]==0x2C||opcode[i]==0x2D) { // SDL/SDR
3147       temp2=get_reg(i_regs->regmap,FTEMP);
3148       if(!rs2[i]) temp2=th=tl;
3149     }
3150
3151     emit_testimm(temp,2);
3152     case2=(int)out;
3153     emit_jne(0);
3154     emit_testimm(temp,1);
3155     case1=(int)out;
3156     emit_jne(0);
3157     // 0
3158     if (opcode[i]==0x2A) { // SWL
3159       emit_writeword_indexed(tl,0,temp);
3160     }
3161     if (opcode[i]==0x2E) { // SWR
3162       emit_writebyte_indexed(tl,3,temp);
3163     }
3164     if (opcode[i]==0x2C) { // SDL
3165       emit_writeword_indexed(th,0,temp);
3166       if(rs2[i]) emit_mov(tl,temp2);
3167     }
3168     if (opcode[i]==0x2D) { // SDR
3169       emit_writebyte_indexed(tl,3,temp);
3170       if(rs2[i]) emit_shldimm(th,tl,24,temp2);
3171     }
3172     done0=(int)out;
3173     emit_jmp(0);
3174     // 1
3175     set_jump_target(case1,(int)out);
3176     if (opcode[i]==0x2A) { // SWL
3177       // Write 3 msb into three least significant bytes
3178       if(rs2[i]) emit_rorimm(tl,8,tl);
3179       emit_writehword_indexed(tl,-1,temp);
3180       if(rs2[i]) emit_rorimm(tl,16,tl);
3181       emit_writebyte_indexed(tl,1,temp);
3182       if(rs2[i]) emit_rorimm(tl,8,tl);
3183     }
3184     if (opcode[i]==0x2E) { // SWR
3185       // Write two lsb into two most significant bytes
3186       emit_writehword_indexed(tl,1,temp);
3187     }
3188     if (opcode[i]==0x2C) { // SDL
3189       if(rs2[i]) emit_shrdimm(tl,th,8,temp2);
3190       // Write 3 msb into three least significant bytes
3191       if(rs2[i]) emit_rorimm(th,8,th);
3192       emit_writehword_indexed(th,-1,temp);
3193       if(rs2[i]) emit_rorimm(th,16,th);
3194       emit_writebyte_indexed(th,1,temp);
3195       if(rs2[i]) emit_rorimm(th,8,th);
3196     }
3197     if (opcode[i]==0x2D) { // SDR
3198       if(rs2[i]) emit_shldimm(th,tl,16,temp2);
3199       // Write two lsb into two most significant bytes
3200       emit_writehword_indexed(tl,1,temp);
3201     }
3202     done1=(int)out;
3203     emit_jmp(0);
3204     // 2
3205     set_jump_target(case2,(int)out);
3206     emit_testimm(temp,1);
3207     case3=(int)out;
3208     emit_jne(0);
3209     if (opcode[i]==0x2A) { // SWL
3210       // Write two msb into two least significant bytes
3211       if(rs2[i]) emit_rorimm(tl,16,tl);
3212       emit_writehword_indexed(tl,-2,temp);
3213       if(rs2[i]) emit_rorimm(tl,16,tl);
3214     }
3215     if (opcode[i]==0x2E) { // SWR
3216       // Write 3 lsb into three most significant bytes
3217       emit_writebyte_indexed(tl,-1,temp);
3218       if(rs2[i]) emit_rorimm(tl,8,tl);
3219       emit_writehword_indexed(tl,0,temp);
3220       if(rs2[i]) emit_rorimm(tl,24,tl);
3221     }
3222     if (opcode[i]==0x2C) { // SDL
3223       if(rs2[i]) emit_shrdimm(tl,th,16,temp2);
3224       // Write two msb into two least significant bytes
3225       if(rs2[i]) emit_rorimm(th,16,th);
3226       emit_writehword_indexed(th,-2,temp);
3227       if(rs2[i]) emit_rorimm(th,16,th);
3228     }
3229     if (opcode[i]==0x2D) { // SDR
3230       if(rs2[i]) emit_shldimm(th,tl,8,temp2);
3231       // Write 3 lsb into three most significant bytes
3232       emit_writebyte_indexed(tl,-1,temp);
3233       if(rs2[i]) emit_rorimm(tl,8,tl);
3234       emit_writehword_indexed(tl,0,temp);
3235       if(rs2[i]) emit_rorimm(tl,24,tl);
3236     }
3237     done2=(int)out;
3238     emit_jmp(0);
3239     // 3
3240     set_jump_target(case3,(int)out);
3241     if (opcode[i]==0x2A) { // SWL
3242       // Write msb into least significant byte
3243       if(rs2[i]) emit_rorimm(tl,24,tl);
3244       emit_writebyte_indexed(tl,-3,temp);
3245       if(rs2[i]) emit_rorimm(tl,8,tl);
3246     }
3247     if (opcode[i]==0x2E) { // SWR
3248       // Write entire word
3249       emit_writeword_indexed(tl,-3,temp);
3250     }
3251     if (opcode[i]==0x2C) { // SDL
3252       if(rs2[i]) emit_shrdimm(tl,th,24,temp2);
3253       // Write msb into least significant byte
3254       if(rs2[i]) emit_rorimm(th,24,th);
3255       emit_writebyte_indexed(th,-3,temp);
3256       if(rs2[i]) emit_rorimm(th,8,th);
3257     }
3258     if (opcode[i]==0x2D) { // SDR
3259       if(rs2[i]) emit_mov(th,temp2);
3260       // Write entire word
3261       emit_writeword_indexed(tl,-3,temp);
3262     }
3263     set_jump_target(done0,(int)out);
3264     set_jump_target(done1,(int)out);
3265     set_jump_target(done2,(int)out);
3266     if (opcode[i]==0x2C) { // SDL
3267       emit_testimm(temp,4);
3268       done0=(int)out;
3269       emit_jne(0);
3270       emit_andimm(temp,~3,temp);
3271       emit_writeword_indexed(temp2,4,temp);
3272       set_jump_target(done0,(int)out);
3273     }
3274     if (opcode[i]==0x2D) { // SDR
3275       emit_testimm(temp,4);
3276       done0=(int)out;
3277       emit_jeq(0);
3278       emit_andimm(temp,~3,temp);
3279       emit_writeword_indexed(temp2,-4,temp);
3280       set_jump_target(done0,(int)out);
3281     }
3282     if(!c||!memtarget)
3283       add_stub(STORELR_STUB,jaddr,(int)out,0,(int)i_regs,rs2[i],ccadj[i],reglist);
3284   }
3285   if(!using_tlb) {
3286     emit_addimm_no_flags((u_int)0x80000000-(u_int)rdram,temp);
3287     #if defined(HOST_IMM8)
3288     int ir=get_reg(i_regs->regmap,INVCP);
3289     assert(ir>=0);
3290     emit_cmpmem_indexedsr12_reg(ir,temp,1);
3291     #else
3292     emit_cmpmem_indexedsr12_imm((int)invalid_code,temp,1);
3293     #endif
3294     jaddr2=(int)out;
3295     emit_jne(0);
3296     add_stub(INVCODE_STUB,jaddr2,(int)out,reglist|(1<<HOST_CCREG),temp,0,0,0);
3297   }
3298   /*
3299     emit_pusha();
3300     //save_regs(0x100f);
3301         emit_readword((int)&last_count,ECX);
3302         if(get_reg(i_regs->regmap,CCREG)<0)
3303           emit_loadreg(CCREG,HOST_CCREG);
3304         emit_add(HOST_CCREG,ECX,HOST_CCREG);
3305         emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3306         emit_writeword(HOST_CCREG,(int)&Count);
3307     emit_call((int)memdebug);
3308     emit_popa();
3309     //restore_regs(0x100f);
3310   /**/
3311 }
3312
3313 void c1ls_assemble(int i,struct regstat *i_regs)
3314 {
3315 #ifndef DISABLE_COP1
3316   int s,th,tl;
3317   int temp,ar;
3318   int map=-1;
3319   int offset;
3320   int c=0;
3321   int jaddr,jaddr2=0,jaddr3,type;
3322   int agr=AGEN1+(i&1);
3323   u_int hr,reglist=0;
3324   th=get_reg(i_regs->regmap,FTEMP|64);
3325   tl=get_reg(i_regs->regmap,FTEMP);
3326   s=get_reg(i_regs->regmap,rs1[i]);
3327   temp=get_reg(i_regs->regmap,agr);
3328   if(temp<0) temp=get_reg(i_regs->regmap,-1);
3329   offset=imm[i];
3330   assert(tl>=0);
3331   assert(rs1[i]>0);
3332   assert(temp>=0);
3333   for(hr=0;hr<HOST_REGS;hr++) {
3334     if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3335   }
3336   if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
3337   if (opcode[i]==0x31||opcode[i]==0x35) // LWC1/LDC1
3338   {
3339     // Loads use a temporary register which we need to save
3340     reglist|=1<<temp;
3341   }
3342   if (opcode[i]==0x39||opcode[i]==0x3D) // SWC1/SDC1
3343     ar=temp;
3344   else // LWC1/LDC1
3345     ar=tl;
3346   //if(s<0) emit_loadreg(rs1[i],ar); //address_generation does this now
3347   //else c=(i_regs->wasconst>>s)&1;
3348   if(s>=0) c=(i_regs->wasconst>>s)&1;
3349   // Check cop1 unusable
3350   if(!cop1_usable) {
3351     signed char rs=get_reg(i_regs->regmap,CSREG);
3352     assert(rs>=0);
3353     emit_testimm(rs,0x20000000);
3354     jaddr=(int)out;
3355     emit_jeq(0);
3356     add_stub(FP_STUB,jaddr,(int)out,i,rs,(int)i_regs,is_delayslot,0);
3357     cop1_usable=1;
3358   }
3359   if (opcode[i]==0x39) { // SWC1 (get float address)
3360     emit_readword((int)&reg_cop1_simple[(source[i]>>16)&0x1f],tl);
3361   }
3362   if (opcode[i]==0x3D) { // SDC1 (get double address)
3363     emit_readword((int)&reg_cop1_double[(source[i]>>16)&0x1f],tl);
3364   }
3365   // Generate address + offset
3366   if(!using_tlb) {
3367     if(!c)
3368       emit_cmpimm(offset||c||s<0?ar:s,0x800000);
3369   }
3370   else
3371   {
3372     map=get_reg(i_regs->regmap,TLREG);
3373     assert(map>=0);
3374     if (opcode[i]==0x31||opcode[i]==0x35) { // LWC1/LDC1
3375       map=do_tlb_r(offset||c||s<0?ar:s,ar,map,0,-1,-1,c,constmap[i][s]+offset);
3376     }
3377     if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3378       map=do_tlb_w(offset||c||s<0?ar:s,ar,map,0,c,constmap[i][s]+offset);
3379     }
3380   }
3381   if (opcode[i]==0x39) { // SWC1 (read float)
3382     emit_readword_indexed(0,tl,tl);
3383   }
3384   if (opcode[i]==0x3D) { // SDC1 (read double)
3385     emit_readword_indexed(4,tl,th);
3386     emit_readword_indexed(0,tl,tl);
3387   }
3388   if (opcode[i]==0x31) { // LWC1 (get target address)
3389     emit_readword((int)&reg_cop1_simple[(source[i]>>16)&0x1f],temp);
3390   }
3391   if (opcode[i]==0x35) { // LDC1 (get target address)
3392     emit_readword((int)&reg_cop1_double[(source[i]>>16)&0x1f],temp);
3393   }
3394   if(!using_tlb) {
3395     if(!c) {
3396       jaddr2=(int)out;
3397       emit_jno(0);
3398     }
3399     else if(((signed int)(constmap[i][s]+offset))>=(signed int)0x80800000) {
3400       jaddr2=(int)out;
3401       emit_jmp(0); // inline_readstub/inline_writestub?  Very rare case
3402     }
3403     #ifdef DESTRUCTIVE_SHIFT
3404     if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3405       if(!offset&&!c&&s>=0) emit_mov(s,ar);
3406     }
3407     #endif
3408   }else{
3409     if (opcode[i]==0x31||opcode[i]==0x35) { // LWC1/LDC1
3410       do_tlb_r_branch(map,c,constmap[i][s]+offset,&jaddr2);
3411     }
3412     if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3413       do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr2);
3414     }
3415   }
3416   if (opcode[i]==0x31) { // LWC1
3417     //if(s>=0&&!c&&!offset) emit_mov(s,tl);
3418     //gen_tlb_addr_r(ar,map);
3419     //emit_readword_indexed((int)rdram-0x80000000,tl,tl);
3420     #ifdef HOST_IMM_ADDR32
3421     if(c) emit_readword_tlb(constmap[i][s]+offset,map,tl);
3422     else
3423     #endif
3424     emit_readword_indexed_tlb(0,offset||c||s<0?tl:s,map,tl);
3425     type=LOADW_STUB;
3426   }
3427   if (opcode[i]==0x35) { // LDC1
3428     assert(th>=0);
3429     //if(s>=0&&!c&&!offset) emit_mov(s,tl);
3430     //gen_tlb_addr_r(ar,map);
3431     //emit_readword_indexed((int)rdram-0x80000000,tl,th);
3432     //emit_readword_indexed((int)rdram-0x7FFFFFFC,tl,tl);
3433     #ifdef HOST_IMM_ADDR32
3434     if(c) emit_readdword_tlb(constmap[i][s]+offset,map,th,tl);
3435     else
3436     #endif
3437     emit_readdword_indexed_tlb(0,offset||c||s<0?tl:s,map,th,tl);
3438     type=LOADD_STUB;
3439   }
3440   if (opcode[i]==0x39) { // SWC1
3441     //emit_writeword_indexed(tl,(int)rdram-0x80000000,temp);
3442     emit_writeword_indexed_tlb(tl,0,offset||c||s<0?temp:s,map,temp);
3443     type=STOREW_STUB;
3444   }
3445   if (opcode[i]==0x3D) { // SDC1
3446     assert(th>=0);
3447     //emit_writeword_indexed(th,(int)rdram-0x80000000,temp);
3448     //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,temp);
3449     emit_writedword_indexed_tlb(th,tl,0,offset||c||s<0?temp:s,map,temp);
3450     type=STORED_STUB;
3451   }
3452   if(!using_tlb) {
3453     if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3454       #ifndef DESTRUCTIVE_SHIFT
3455       temp=offset||c||s<0?ar:s;
3456       #endif
3457       #if defined(HOST_IMM8)
3458       int ir=get_reg(i_regs->regmap,INVCP);
3459       assert(ir>=0);
3460       emit_cmpmem_indexedsr12_reg(ir,temp,1);
3461       #else
3462       emit_cmpmem_indexedsr12_imm((int)invalid_code,temp,1);
3463       #endif
3464       jaddr3=(int)out;
3465       emit_jne(0);
3466       add_stub(INVCODE_STUB,jaddr3,(int)out,reglist|(1<<HOST_CCREG),temp,0,0,0);
3467     }
3468   }
3469   if(jaddr2) add_stub(type,jaddr2,(int)out,i,offset||c||s<0?ar:s,(int)i_regs,ccadj[i],reglist);
3470   if (opcode[i]==0x31) { // LWC1 (write float)
3471     emit_writeword_indexed(tl,0,temp);
3472   }
3473   if (opcode[i]==0x35) { // LDC1 (write double)
3474     emit_writeword_indexed(th,4,temp);
3475     emit_writeword_indexed(tl,0,temp);
3476   }
3477   //if(opcode[i]==0x39)
3478   /*if(opcode[i]==0x39||opcode[i]==0x31)
3479   {
3480     emit_pusha();
3481         emit_readword((int)&last_count,ECX);
3482         if(get_reg(i_regs->regmap,CCREG)<0)
3483           emit_loadreg(CCREG,HOST_CCREG);
3484         emit_add(HOST_CCREG,ECX,HOST_CCREG);
3485         emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3486         emit_writeword(HOST_CCREG,(int)&Count);
3487     emit_call((int)memdebug);
3488     emit_popa();
3489   }/**/
3490 #else
3491   cop1_unusable(i, i_regs);
3492 #endif
3493 }
3494
3495 #ifndef multdiv_assemble
3496 void multdiv_assemble(int i,struct regstat *i_regs)
3497 {
3498   printf("Need multdiv_assemble for this architecture.\n");
3499   exit(1);
3500 }
3501 #endif
3502
3503 void mov_assemble(int i,struct regstat *i_regs)
3504 {
3505   //if(opcode2[i]==0x10||opcode2[i]==0x12) { // MFHI/MFLO
3506   //if(opcode2[i]==0x11||opcode2[i]==0x13) { // MTHI/MTLO
3507   assert(rt1[i]>0);
3508   if(rt1[i]) {
3509     signed char sh,sl,th,tl;
3510     th=get_reg(i_regs->regmap,rt1[i]|64);
3511     tl=get_reg(i_regs->regmap,rt1[i]);
3512     //assert(tl>=0);
3513     if(tl>=0) {
3514       sh=get_reg(i_regs->regmap,rs1[i]|64);
3515       sl=get_reg(i_regs->regmap,rs1[i]);
3516       if(sl>=0) emit_mov(sl,tl);
3517       else emit_loadreg(rs1[i],tl);
3518       if(th>=0) {
3519         if(sh>=0) emit_mov(sh,th);
3520         else emit_loadreg(rs1[i]|64,th);
3521       }
3522     }
3523   }
3524 }
3525
3526 #ifndef fconv_assemble
3527 void fconv_assemble(int i,struct regstat *i_regs)
3528 {
3529   printf("Need fconv_assemble for this architecture.\n");
3530   exit(1);
3531 }
3532 #endif
3533
3534 #if 0
3535 void float_assemble(int i,struct regstat *i_regs)
3536 {
3537   printf("Need float_assemble for this architecture.\n");
3538   exit(1);
3539 }
3540 #endif
3541
3542 void syscall_assemble(int i,struct regstat *i_regs)
3543 {
3544   signed char ccreg=get_reg(i_regs->regmap,CCREG);
3545   assert(ccreg==HOST_CCREG);
3546   assert(!is_delayslot);
3547   emit_movimm(start+i*4,EAX); // Get PC
3548   emit_addimm(HOST_CCREG,CLOCK_DIVIDER*ccadj[i],HOST_CCREG); // CHECK: is this right?  There should probably be an extra cycle...
3549   emit_jmp((int)jump_syscall);
3550 }
3551
3552 void ds_assemble(int i,struct regstat *i_regs)
3553 {
3554   is_delayslot=1;
3555   switch(itype[i]) {
3556     case ALU:
3557       alu_assemble(i,i_regs);break;
3558     case IMM16:
3559       imm16_assemble(i,i_regs);break;
3560     case SHIFT:
3561       shift_assemble(i,i_regs);break;
3562     case SHIFTIMM:
3563       shiftimm_assemble(i,i_regs);break;
3564     case LOAD:
3565       load_assemble(i,i_regs);break;
3566     case LOADLR:
3567       loadlr_assemble(i,i_regs);break;
3568     case STORE:
3569       store_assemble(i,i_regs);break;
3570     case STORELR:
3571       storelr_assemble(i,i_regs);break;
3572     case COP0:
3573       cop0_assemble(i,i_regs);break;
3574     case COP1:
3575       cop1_assemble(i,i_regs);break;
3576     case C1LS:
3577       c1ls_assemble(i,i_regs);break;
3578     case FCONV:
3579       fconv_assemble(i,i_regs);break;
3580     case FLOAT:
3581       float_assemble(i,i_regs);break;
3582     case FCOMP:
3583       fcomp_assemble(i,i_regs);break;
3584     case MULTDIV:
3585       multdiv_assemble(i,i_regs);break;
3586     case MOV:
3587       mov_assemble(i,i_regs);break;
3588     case SYSCALL:
3589     case SPAN:
3590     case UJUMP:
3591     case RJUMP:
3592     case CJUMP:
3593     case SJUMP:
3594     case FJUMP:
3595       printf("Jump in the delay slot.  This is probably a bug.\n");
3596   }
3597   is_delayslot=0;
3598 }
3599
3600 // Is the branch target a valid internal jump?
3601 int internal_branch(uint64_t i_is32,int addr)
3602 {
3603   if(addr&1) return 0; // Indirect (register) jump
3604   if(addr>=start && addr<start+slen*4-4)
3605   {
3606     int t=(addr-start)>>2;
3607     // Delay slots are not valid branch targets
3608     //if(t>0&&(itype[t-1]==RJUMP||itype[t-1]==UJUMP||itype[t-1]==CJUMP||itype[t-1]==SJUMP||itype[t-1]==FJUMP)) return 0;
3609     // 64 -> 32 bit transition requires a recompile
3610     /*if(is32[t]&~unneeded_reg_upper[t]&~i_is32)
3611     {
3612       if(requires_32bit[t]&~i_is32) printf("optimizable: no\n");
3613       else printf("optimizable: yes\n");
3614     }*/
3615     //if(is32[t]&~unneeded_reg_upper[t]&~i_is32) return 0;
3616     if(requires_32bit[t]&~i_is32) return 0;
3617     else return 1;
3618   }
3619   return 0;
3620 }
3621
3622 #ifndef wb_invalidate
3623 void wb_invalidate(signed char pre[],signed char entry[],uint64_t dirty,uint64_t is32,
3624   uint64_t u,uint64_t uu)
3625 {
3626   int hr;
3627   for(hr=0;hr<HOST_REGS;hr++) {
3628     if(hr!=EXCLUDE_REG) {
3629       if(pre[hr]!=entry[hr]) {
3630         if(pre[hr]>=0) {
3631           if((dirty>>hr)&1) {
3632             if(get_reg(entry,pre[hr])<0) {
3633               if(pre[hr]<64) {
3634                 if(!((u>>pre[hr])&1)) {
3635                   emit_storereg(pre[hr],hr);
3636                   if( ((is32>>pre[hr])&1) && !((uu>>pre[hr])&1) ) {
3637                     emit_sarimm(hr,31,hr);
3638                     emit_storereg(pre[hr]|64,hr);
3639                   }
3640                 }
3641               }else{
3642                 if(!((uu>>(pre[hr]&63))&1) && !((is32>>(pre[hr]&63))&1)) {
3643                   emit_storereg(pre[hr],hr);
3644                 }
3645               }
3646             }
3647           }
3648         }
3649       }
3650     }
3651   }
3652   // Move from one register to another (no writeback)
3653   for(hr=0;hr<HOST_REGS;hr++) {
3654     if(hr!=EXCLUDE_REG) {
3655       if(pre[hr]!=entry[hr]) {
3656         if(pre[hr]>=0&&(pre[hr]&63)<TEMPREG) {
3657           int nr;
3658           if((nr=get_reg(entry,pre[hr]))>=0) {
3659             emit_mov(hr,nr);
3660           }
3661         }
3662       }
3663     }
3664   }
3665 }
3666 #endif
3667
3668 // Load the specified registers
3669 // This only loads the registers given as arguments because
3670 // we don't want to load things that will be overwritten
3671 void load_regs(signed char entry[],signed char regmap[],int is32,int rs1,int rs2)
3672 {
3673   int hr;
3674   // Load 32-bit regs
3675   for(hr=0;hr<HOST_REGS;hr++) {
3676     if(hr!=EXCLUDE_REG&&regmap[hr]>=0) {
3677       if(entry[hr]!=regmap[hr]) {
3678         if(regmap[hr]==rs1||regmap[hr]==rs2)
3679         {
3680           if(regmap[hr]==0) {
3681             emit_zeroreg(hr);
3682           }
3683           else
3684           {
3685             emit_loadreg(regmap[hr],hr);
3686           }
3687         }
3688       }
3689     }
3690   }
3691   //Load 64-bit regs
3692   for(hr=0;hr<HOST_REGS;hr++) {
3693     if(hr!=EXCLUDE_REG&&regmap[hr]>=0) {
3694       if(entry[hr]!=regmap[hr]) {
3695         if(regmap[hr]-64==rs1||regmap[hr]-64==rs2)
3696         {
3697           assert(regmap[hr]!=64);
3698           if((is32>>(regmap[hr]&63))&1) {
3699             int lr=get_reg(regmap,regmap[hr]-64);
3700             if(lr>=0)
3701               emit_sarimm(lr,31,hr);
3702             else
3703               emit_loadreg(regmap[hr],hr);
3704           }
3705           else
3706           {
3707             emit_loadreg(regmap[hr],hr);
3708           }
3709         }
3710       }
3711     }
3712   }
3713 }
3714
3715 // Load registers prior to the start of a loop
3716 // so that they are not loaded within the loop
3717 static void loop_preload(signed char pre[],signed char entry[])
3718 {
3719   int hr;
3720   for(hr=0;hr<HOST_REGS;hr++) {
3721     if(hr!=EXCLUDE_REG) {
3722       if(pre[hr]!=entry[hr]) {
3723         if(entry[hr]>=0) {
3724           if(get_reg(pre,entry[hr])<0) {
3725             assem_debug("loop preload:\n");
3726             //printf("loop preload: %d\n",hr);
3727             if(entry[hr]==0) {
3728               emit_zeroreg(hr);
3729             }
3730             else if(entry[hr]<TEMPREG)
3731             {
3732               emit_loadreg(entry[hr],hr);
3733             }
3734             else if(entry[hr]-64<TEMPREG)
3735             {
3736               emit_loadreg(entry[hr],hr);
3737             }
3738           }
3739         }
3740       }
3741     }
3742   }
3743 }
3744
3745 // Generate address for load/store instruction
3746 void address_generation(int i,struct regstat *i_regs,signed char entry[])
3747 {
3748   if(itype[i]==LOAD||itype[i]==LOADLR||itype[i]==STORE||itype[i]==STORELR||itype[i]==C1LS) {
3749     int ra;
3750     int agr=AGEN1+(i&1);
3751     int mgr=MGEN1+(i&1);
3752     if(itype[i]==LOAD) {
3753       ra=get_reg(i_regs->regmap,rt1[i]);
3754       //if(rt1[i]) assert(ra>=0);
3755     }
3756     if(itype[i]==LOADLR) {
3757       ra=get_reg(i_regs->regmap,FTEMP);
3758     }
3759     if(itype[i]==STORE||itype[i]==STORELR) {
3760       ra=get_reg(i_regs->regmap,agr);
3761       if(ra<0) ra=get_reg(i_regs->regmap,-1);
3762     }
3763     if(itype[i]==C1LS) {
3764       if (opcode[i]==0x31||opcode[i]==0x35) // LWC1/LDC1
3765         ra=get_reg(i_regs->regmap,FTEMP);
3766       else { // SWC1/SDC1
3767         ra=get_reg(i_regs->regmap,agr);
3768         if(ra<0) ra=get_reg(i_regs->regmap,-1);
3769       }
3770     }
3771     int rs=get_reg(i_regs->regmap,rs1[i]);
3772     int rm=get_reg(i_regs->regmap,TLREG);
3773     if(ra>=0) {
3774       int offset=imm[i];
3775       int c=(i_regs->wasconst>>rs)&1;
3776       if(rs1[i]==0) {
3777         // Using r0 as a base address
3778         /*if(rm>=0) {
3779           if(!entry||entry[rm]!=mgr) {
3780             generate_map_const(offset,rm);
3781           } // else did it in the previous cycle
3782         }*/
3783         if(!entry||entry[ra]!=agr) {
3784           if (opcode[i]==0x22||opcode[i]==0x26) {
3785             emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR
3786           }else if (opcode[i]==0x1a||opcode[i]==0x1b) {
3787             emit_movimm(offset&0xFFFFFFF8,ra); // LDL/LDR
3788           }else{
3789             emit_movimm(offset,ra);
3790           }
3791         } // else did it in the previous cycle
3792       }
3793       else if(rs<0) {
3794         if(!entry||entry[ra]!=rs1[i])
3795           emit_loadreg(rs1[i],ra);
3796         //if(!entry||entry[ra]!=rs1[i])
3797         //  printf("poor load scheduling!\n");
3798       }
3799       else if(c) {
3800         if(rm>=0) {
3801           if(!entry||entry[rm]!=mgr) {
3802             if(itype[i]==STORE||itype[i]==STORELR||opcode[i]==0x39||opcode[i]==0x3D) {
3803               // Stores to memory go thru the mapper to detect self-modifying
3804               // code, loads don't.
3805               if((unsigned int)(constmap[i][rs]+offset)>=0xC0000000 ||
3806                  (unsigned int)(constmap[i][rs]+offset)<0x80800000 )
3807                 generate_map_const(constmap[i][rs]+offset,rm);
3808             }else{
3809               if((signed int)(constmap[i][rs]+offset)>=(signed int)0xC0000000)
3810                 generate_map_const(constmap[i][rs]+offset,rm);
3811             }
3812           }
3813         }
3814         if(rs1[i]!=rt1[i]||itype[i]!=LOAD) {
3815           if(!entry||entry[ra]!=agr) {
3816             if (opcode[i]==0x22||opcode[i]==0x26) {
3817               emit_movimm((constmap[i][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR
3818             }else if (opcode[i]==0x1a||opcode[i]==0x1b) {
3819               emit_movimm((constmap[i][rs]+offset)&0xFFFFFFF8,ra); // LDL/LDR
3820             }else{
3821               #ifdef HOST_IMM_ADDR32
3822               if((itype[i]!=LOAD&&opcode[i]!=0x31&&opcode[i]!=0x35) ||
3823                  (using_tlb&&((signed int)constmap[i][rs]+offset)>=(signed int)0xC0000000))
3824               #endif
3825               emit_movimm(constmap[i][rs]+offset,ra);
3826             }
3827           } // else did it in the previous cycle
3828         } // else load_consts already did it
3829       }
3830       if(offset&&!c&&rs1[i]) {
3831         if(rs>=0) {
3832           emit_addimm(rs,offset,ra);
3833         }else{
3834           emit_addimm(ra,offset,ra);
3835         }
3836       }
3837     }
3838   }
3839   // Preload constants for next instruction
3840   if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS) {
3841     int agr,ra;
3842     #ifndef HOST_IMM_ADDR32
3843     // Mapper entry
3844     agr=MGEN1+((i+1)&1);
3845     ra=get_reg(i_regs->regmap,agr);
3846     if(ra>=0) {
3847       int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
3848       int offset=imm[i+1];
3849       int c=(regs[i+1].wasconst>>rs)&1;
3850       if(c) {
3851         if(itype[i+1]==STORE||itype[i+1]==STORELR||opcode[i+1]==0x39||opcode[i+1]==0x3D) {
3852           // Stores to memory go thru the mapper to detect self-modifying
3853           // code, loads don't.
3854           if((unsigned int)(constmap[i+1][rs]+offset)>=0xC0000000 ||
3855              (unsigned int)(constmap[i+1][rs]+offset)<0x80800000 )
3856             generate_map_const(constmap[i+1][rs]+offset,ra);
3857         }else{
3858           if((signed int)(constmap[i+1][rs]+offset)>=(signed int)0xC0000000)
3859             generate_map_const(constmap[i+1][rs]+offset,ra);
3860         }
3861       }
3862       /*else if(rs1[i]==0) {
3863         generate_map_const(offset,ra);
3864       }*/
3865     }
3866     #endif
3867     // Actual address
3868     agr=AGEN1+((i+1)&1);
3869     ra=get_reg(i_regs->regmap,agr);
3870     if(ra>=0) {
3871       int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
3872       int offset=imm[i+1];
3873       int c=(regs[i+1].wasconst>>rs)&1;
3874       if(c&&(rs1[i+1]!=rt1[i+1]||itype[i+1]!=LOAD)) {
3875         if (opcode[i+1]==0x22||opcode[i+1]==0x26) {
3876           emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR
3877         }else if (opcode[i+1]==0x1a||opcode[i+1]==0x1b) {
3878           emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFF8,ra); // LDL/LDR
3879         }else{
3880           #ifdef HOST_IMM_ADDR32
3881           if((itype[i+1]!=LOAD&&opcode[i+1]!=0x31&&opcode[i+1]!=0x35) ||
3882              (using_tlb&&((signed int)constmap[i+1][rs]+offset)>=(signed int)0xC0000000))
3883           #endif
3884           emit_movimm(constmap[i+1][rs]+offset,ra);
3885         }
3886       }
3887       else if(rs1[i+1]==0) {
3888         // Using r0 as a base address
3889         if (opcode[i+1]==0x22||opcode[i+1]==0x26) {
3890           emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR
3891         }else if (opcode[i+1]==0x1a||opcode[i+1]==0x1b) {
3892           emit_movimm(offset&0xFFFFFFF8,ra); // LDL/LDR
3893         }else{
3894           emit_movimm(offset,ra);
3895         }
3896       }
3897     }
3898   }
3899 }
3900
3901 int get_final_value(int hr, int i, int *value)
3902 {
3903   int reg=regs[i].regmap[hr];
3904   while(i<slen-1) {
3905     if(regs[i+1].regmap[hr]!=reg) break;
3906     if(!((regs[i+1].isconst>>hr)&1)) break;
3907     if(bt[i+1]) break;
3908     i++;
3909   }
3910   if(i<slen-1) {
3911     if(itype[i]==UJUMP||itype[i]==RJUMP||itype[i]==CJUMP||itype[i]==SJUMP) {