try to make drc more configurable
[pcsx_rearmed.git] / libpcsxcore / new_dynarec / new_dynarec.c
1 /* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
2  *   Mupen64plus - new_dynarec.c                                           *
3  *   Copyright (C) 2009-2010 Ari64                                         *
4  *                                                                         *
5  *   This program is free software; you can redistribute it and/or modify  *
6  *   it under the terms of the GNU General Public License as published by  *
7  *   the Free Software Foundation; either version 2 of the License, or     *
8  *   (at your option) any later version.                                   *
9  *                                                                         *
10  *   This program is distributed in the hope that it will be useful,       *
11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
13  *   GNU General Public License for more details.                          *
14  *                                                                         *
15  *   You should have received a copy of the GNU General Public License     *
16  *   along with this program; if not, write to the                         *
17  *   Free Software Foundation, Inc.,                                       *
18  *   51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.          *
19  * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
20
21 #include <stdlib.h>
22 #include <stdint.h> //include for uint64_t
23 #include <assert.h>
24
25 #include "emu_if.h" //emulator interface
26
27 #include <sys/mman.h>
28
29 #ifdef __i386__
30 #include "assem_x86.h"
31 #endif
32 #ifdef __x86_64__
33 #include "assem_x64.h"
34 #endif
35 #ifdef __arm__
36 #include "assem_arm.h"
37 #endif
38
39 #define MAXBLOCK 4096
40 #define MAX_OUTPUT_BLOCK_SIZE 262144
41 #define CLOCK_DIVIDER 2
42
43 struct regstat
44 {
45   signed char regmap_entry[HOST_REGS];
46   signed char regmap[HOST_REGS];
47   uint64_t was32;
48   uint64_t is32;
49   uint64_t wasdirty;
50   uint64_t dirty;
51   uint64_t u;
52   uint64_t uu;
53   u_int wasconst;
54   u_int isconst;
55   uint64_t constmap[HOST_REGS];
56 };
57
58 struct ll_entry
59 {
60   u_int vaddr;
61   u_int reg32;
62   void *addr;
63   struct ll_entry *next;
64 };
65
66   u_int start;
67   u_int *source;
68   u_int pagelimit;
69   char insn[MAXBLOCK][10];
70   u_char itype[MAXBLOCK];
71   u_char opcode[MAXBLOCK];
72   u_char opcode2[MAXBLOCK];
73   u_char bt[MAXBLOCK];
74   u_char rs1[MAXBLOCK];
75   u_char rs2[MAXBLOCK];
76   u_char rt1[MAXBLOCK];
77   u_char rt2[MAXBLOCK];
78   u_char us1[MAXBLOCK];
79   u_char us2[MAXBLOCK];
80   u_char dep1[MAXBLOCK];
81   u_char dep2[MAXBLOCK];
82   u_char lt1[MAXBLOCK];
83   int imm[MAXBLOCK];
84   u_int ba[MAXBLOCK];
85   char likely[MAXBLOCK];
86   char is_ds[MAXBLOCK];
87   uint64_t unneeded_reg[MAXBLOCK];
88   uint64_t unneeded_reg_upper[MAXBLOCK];
89   uint64_t branch_unneeded_reg[MAXBLOCK];
90   uint64_t branch_unneeded_reg_upper[MAXBLOCK];
91   uint64_t p32[MAXBLOCK];
92   uint64_t pr32[MAXBLOCK];
93   signed char regmap_pre[MAXBLOCK][HOST_REGS];
94   signed char regmap[MAXBLOCK][HOST_REGS];
95   signed char regmap_entry[MAXBLOCK][HOST_REGS];
96   uint64_t constmap[MAXBLOCK][HOST_REGS];
97   uint64_t known_value[HOST_REGS];
98   u_int known_reg;
99   struct regstat regs[MAXBLOCK];
100   struct regstat branch_regs[MAXBLOCK];
101   u_int needed_reg[MAXBLOCK];
102   uint64_t requires_32bit[MAXBLOCK];
103   u_int wont_dirty[MAXBLOCK];
104   u_int will_dirty[MAXBLOCK];
105   int ccadj[MAXBLOCK];
106   int slen;
107   u_int instr_addr[MAXBLOCK];
108   u_int link_addr[MAXBLOCK][3];
109   int linkcount;
110   u_int stubs[MAXBLOCK*3][8];
111   int stubcount;
112   u_int literals[1024][2];
113   int literalcount;
114   int is_delayslot;
115   int cop1_usable;
116   u_char *out;
117   struct ll_entry *jump_in[4096];
118   struct ll_entry *jump_out[4096];
119   struct ll_entry *jump_dirty[4096];
120   u_int hash_table[65536][4]  __attribute__((aligned(16)));
121   char shadow[1048576]  __attribute__((aligned(16)));
122   void *copy;
123   int expirep;
124   u_int using_tlb;
125   u_int stop_after_jal;
126   extern u_char restore_candidate[512];
127   extern int cycle_count;
128
129   /* registers that may be allocated */
130   /* 1-31 gpr */
131 #define HIREG 32 // hi
132 #define LOREG 33 // lo
133 #define FSREG 34 // FPU status (FCSR)
134 #define CSREG 35 // Coprocessor status
135 #define CCREG 36 // Cycle count
136 #define INVCP 37 // Pointer to invalid_code
137 #define TEMPREG 38
138 #define FTEMP 38 // FPU temporary register
139 #define PTEMP 39 // Prefetch temporary register
140 #define TLREG 40 // TLB mapping offset
141 #define RHASH 41 // Return address hash
142 #define RHTBL 42 // Return address hash table address
143 #define RTEMP 43 // JR/JALR address register
144 #define MAXREG 43
145 #define AGEN1 44 // Address generation temporary register
146 #define AGEN2 45 // Address generation temporary register
147 #define MGEN1 46 // Maptable address generation temporary register
148 #define MGEN2 47 // Maptable address generation temporary register
149 #define BTREG 48 // Branch target temporary register
150
151   /* instruction types */
152 #define NOP 0     // No operation
153 #define LOAD 1    // Load
154 #define STORE 2   // Store
155 #define LOADLR 3  // Unaligned load
156 #define STORELR 4 // Unaligned store
157 #define MOV 5     // Move 
158 #define ALU 6     // Arithmetic/logic
159 #define MULTDIV 7 // Multiply/divide
160 #define SHIFT 8   // Shift by register
161 #define SHIFTIMM 9// Shift by immediate
162 #define IMM16 10  // 16-bit immediate
163 #define RJUMP 11  // Unconditional jump to register
164 #define UJUMP 12  // Unconditional jump
165 #define CJUMP 13  // Conditional branch (BEQ/BNE/BGTZ/BLEZ)
166 #define SJUMP 14  // Conditional branch (regimm format)
167 #define COP0 15   // Coprocessor 0
168 #define COP1 16   // Coprocessor 1
169 #define C1LS 17   // Coprocessor 1 load/store
170 #define FJUMP 18  // Conditional branch (floating point)
171 #define FLOAT 19  // Floating point unit
172 #define FCONV 20  // Convert integer to float
173 #define FCOMP 21  // Floating point compare (sets FSREG)
174 #define SYSCALL 22// SYSCALL
175 #define OTHER 23  // Other
176 #define SPAN 24   // Branch/delay slot spans 2 pages
177 #define NI 25     // Not implemented
178
179   /* stubs */
180 #define CC_STUB 1
181 #define FP_STUB 2
182 #define LOADB_STUB 3
183 #define LOADH_STUB 4
184 #define LOADW_STUB 5
185 #define LOADD_STUB 6
186 #define LOADBU_STUB 7
187 #define LOADHU_STUB 8
188 #define STOREB_STUB 9
189 #define STOREH_STUB 10
190 #define STOREW_STUB 11
191 #define STORED_STUB 12
192 #define STORELR_STUB 13
193 #define INVCODE_STUB 14
194
195   /* branch codes */
196 #define TAKEN 1
197 #define NOTTAKEN 2
198 #define NULLDS 3
199
200 // asm linkage
201 int new_recompile_block(int addr);
202 void *get_addr_ht(u_int vaddr);
203 void invalidate_block(u_int block);
204 void invalidate_addr(u_int addr);
205 void remove_hash(int vaddr);
206 void jump_vaddr();
207 void dyna_linker();
208 void dyna_linker_ds();
209 void verify_code();
210 void verify_code_vm();
211 void verify_code_ds();
212 void cc_interrupt();
213 void fp_exception();
214 void fp_exception_ds();
215 void jump_syscall();
216 void jump_eret();
217
218 // TLB
219 void TLBWI_new();
220 void TLBWR_new();
221 void read_nomem_new();
222 void read_nomemb_new();
223 void read_nomemh_new();
224 void read_nomemd_new();
225 void write_nomem_new();
226 void write_nomemb_new();
227 void write_nomemh_new();
228 void write_nomemd_new();
229 void write_rdram_new();
230 void write_rdramb_new();
231 void write_rdramh_new();
232 void write_rdramd_new();
233 extern u_int memory_map[1048576];
234
235 // Needed by assembler
236 void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32);
237 void wb_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty);
238 void wb_needed_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr);
239 void load_all_regs(signed char i_regmap[]);
240 void load_needed_regs(signed char i_regmap[],signed char next_regmap[]);
241 void load_regs_entry(int t);
242 void load_all_consts(signed char regmap[],int is32,u_int dirty,int i);
243
244 int tracedebug=0;
245
246 //#define DEBUG_CYCLE_COUNT 1
247
248 void nullf() {}
249 //#define assem_debug printf
250 //#define inv_debug printf
251 #define assem_debug nullf
252 #define inv_debug nullf
253
254 static void tlb_hacks()
255 {
256 #ifndef DISABLE_TLB
257   // Goldeneye hack
258   if (strncmp((char *) ROM_HEADER->nom, "GOLDENEYE",9) == 0)
259   {
260     u_int addr;
261     int n;
262     switch (ROM_HEADER->Country_code&0xFF) 
263     {
264       case 0x45: // U
265         addr=0x34b30;
266         break;                   
267       case 0x4A: // J 
268         addr=0x34b70;    
269         break;    
270       case 0x50: // E 
271         addr=0x329f0;
272         break;                        
273       default: 
274         // Unknown country code
275         addr=0;
276         break;
277     }
278     u_int rom_addr=(u_int)rom;
279     #ifdef ROM_COPY
280     // Since memory_map is 32-bit, on 64-bit systems the rom needs to be
281     // in the lower 4G of memory to use this hack.  Copy it if necessary.
282     if((void *)rom>(void *)0xffffffff) {
283       munmap(ROM_COPY, 67108864);
284       if(mmap(ROM_COPY, 12582912,
285               PROT_READ | PROT_WRITE,
286               MAP_FIXED | MAP_PRIVATE | MAP_ANONYMOUS,
287               -1, 0) <= 0) {printf("mmap() failed\n");}
288       memcpy(ROM_COPY,rom,12582912);
289       rom_addr=(u_int)ROM_COPY;
290     }
291     #endif
292     if(addr) {
293       for(n=0x7F000;n<0x80000;n++) {
294         memory_map[n]=(((u_int)(rom_addr+addr-0x7F000000))>>2)|0x40000000;
295       }
296     }
297   }
298 #endif
299 }
300
301 static u_int get_page(u_int vaddr)
302 {
303   u_int page=(vaddr^0x80000000)>>12;
304 #ifndef DISABLE_TLB
305   if(page>262143&&tlb_LUT_r[vaddr>>12]) page=(tlb_LUT_r[vaddr>>12]^0x80000000)>>12;
306 #endif
307   if(page>2048) page=2048+(page&2047);
308   return page;
309 }
310
311 static u_int get_vpage(u_int vaddr)
312 {
313   u_int vpage=(vaddr^0x80000000)>>12;
314 #ifndef DISABLE_TLB
315   if(vpage>262143&&tlb_LUT_r[vaddr>>12]) vpage&=2047; // jump_dirty uses a hash of the virtual address instead
316 #endif
317   if(vpage>2048) vpage=2048+(vpage&2047);
318   return vpage;
319 }
320
321 // Get address from virtual address
322 // This is called from the recompiled JR/JALR instructions
323 void *get_addr(u_int vaddr)
324 {
325   u_int page=get_page(vaddr);
326   u_int vpage=get_vpage(vaddr);
327   struct ll_entry *head;
328   //printf("TRACE: count=%d next=%d (get_addr %x,page %d)\n",Count,next_interupt,vaddr,page);
329   head=jump_in[page];
330   while(head!=NULL) {
331     if(head->vaddr==vaddr&&head->reg32==0) {
332   //printf("TRACE: count=%d next=%d (get_addr match %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
333       int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
334       ht_bin[3]=ht_bin[1];
335       ht_bin[2]=ht_bin[0];
336       ht_bin[1]=(int)head->addr;
337       ht_bin[0]=vaddr;
338       return head->addr;
339     }
340     head=head->next;
341   }
342   head=jump_dirty[vpage];
343   while(head!=NULL) {
344     if(head->vaddr==vaddr&&head->reg32==0) {
345       //printf("TRACE: count=%d next=%d (get_addr match dirty %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
346       // Don't restore blocks which are about to expire from the cache
347       if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
348       if(verify_dirty(head->addr)) {
349         //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]);
350         invalid_code[vaddr>>12]=0;
351         memory_map[vaddr>>12]|=0x40000000;
352         if(vpage<2048) {
353 #ifndef DISABLE_TLB
354           if(tlb_LUT_r[vaddr>>12]) {
355             invalid_code[tlb_LUT_r[vaddr>>12]>>12]=0;
356             memory_map[tlb_LUT_r[vaddr>>12]>>12]|=0x40000000;
357           }
358 #endif
359           restore_candidate[vpage>>3]|=1<<(vpage&7);
360         }
361         else restore_candidate[page>>3]|=1<<(page&7);
362         int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
363         if(ht_bin[0]==vaddr) {
364           ht_bin[1]=(int)head->addr; // Replace existing entry
365         }
366         else
367         {
368           ht_bin[3]=ht_bin[1];
369           ht_bin[2]=ht_bin[0];
370           ht_bin[1]=(int)head->addr;
371           ht_bin[0]=vaddr;
372         }
373         return head->addr;
374       }
375     }
376     head=head->next;
377   }
378   //printf("TRACE: count=%d next=%d (get_addr no-match %x)\n",Count,next_interupt,vaddr);
379   int r=new_recompile_block(vaddr);
380   if(r==0) return get_addr(vaddr);
381   // Execute in unmapped page, generate pagefault execption
382   Status|=2;
383   Cause=(vaddr<<31)|0x8;
384   EPC=(vaddr&1)?vaddr-5:vaddr;
385   BadVAddr=(vaddr&~1);
386   Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0);
387   EntryHi=BadVAddr&0xFFFFE000;
388   return get_addr_ht(0x80000000);
389 }
390 // Look up address in hash table first
391 void *get_addr_ht(u_int vaddr)
392 {
393   //printf("TRACE: count=%d next=%d (get_addr_ht %x)\n",Count,next_interupt,vaddr);
394   int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
395   if(ht_bin[0]==vaddr) return (void *)ht_bin[1];
396   if(ht_bin[2]==vaddr) return (void *)ht_bin[3];
397   return get_addr(vaddr);
398 }
399
400 void *get_addr_32(u_int vaddr,u_int flags)
401 {
402   //printf("TRACE: count=%d next=%d (get_addr_32 %x,flags %x)\n",Count,next_interupt,vaddr,flags);
403   int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
404   if(ht_bin[0]==vaddr) return (void *)ht_bin[1];
405   if(ht_bin[2]==vaddr) return (void *)ht_bin[3];
406   u_int page=get_page(vaddr);
407   u_int vpage=get_vpage(vaddr);
408   struct ll_entry *head;
409   head=jump_in[page];
410   while(head!=NULL) {
411     if(head->vaddr==vaddr&&(head->reg32&flags)==0) {
412       //printf("TRACE: count=%d next=%d (get_addr_32 match %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
413       if(head->reg32==0) {
414         int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
415         if(ht_bin[0]==-1) {
416           ht_bin[1]=(int)head->addr;
417           ht_bin[0]=vaddr;
418         }else if(ht_bin[2]==-1) {
419           ht_bin[3]=(int)head->addr;
420           ht_bin[2]=vaddr;
421         }
422         //ht_bin[3]=ht_bin[1];
423         //ht_bin[2]=ht_bin[0];
424         //ht_bin[1]=(int)head->addr;
425         //ht_bin[0]=vaddr;
426       }
427       return head->addr;
428     }
429     head=head->next;
430   }
431   head=jump_dirty[vpage];
432   while(head!=NULL) {
433     if(head->vaddr==vaddr&&(head->reg32&flags)==0) {
434       //printf("TRACE: count=%d next=%d (get_addr_32 match dirty %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
435       // Don't restore blocks which are about to expire from the cache
436       if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
437       if(verify_dirty(head->addr)) {
438         //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]);
439         invalid_code[vaddr>>12]=0;
440         memory_map[vaddr>>12]|=0x40000000;
441         if(vpage<2048) {
442 #ifndef DISABLE_TLB
443           if(tlb_LUT_r[vaddr>>12]) {
444             invalid_code[tlb_LUT_r[vaddr>>12]>>12]=0;
445             memory_map[tlb_LUT_r[vaddr>>12]>>12]|=0x40000000;
446           }
447 #endif
448           restore_candidate[vpage>>3]|=1<<(vpage&7);
449         }
450         else restore_candidate[page>>3]|=1<<(page&7);
451         if(head->reg32==0) {
452           int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
453           if(ht_bin[0]==-1) {
454             ht_bin[1]=(int)head->addr;
455             ht_bin[0]=vaddr;
456           }else if(ht_bin[2]==-1) {
457             ht_bin[3]=(int)head->addr;
458             ht_bin[2]=vaddr;
459           }
460           //ht_bin[3]=ht_bin[1];
461           //ht_bin[2]=ht_bin[0];
462           //ht_bin[1]=(int)head->addr;
463           //ht_bin[0]=vaddr;
464         }
465         return head->addr;
466       }
467     }
468     head=head->next;
469   }
470   //printf("TRACE: count=%d next=%d (get_addr_32 no-match %x,flags %x)\n",Count,next_interupt,vaddr,flags);
471   int r=new_recompile_block(vaddr);
472   if(r==0) return get_addr(vaddr);
473   // Execute in unmapped page, generate pagefault execption
474   Status|=2;
475   Cause=(vaddr<<31)|0x8;
476   EPC=(vaddr&1)?vaddr-5:vaddr;
477   BadVAddr=(vaddr&~1);
478   Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0);
479   EntryHi=BadVAddr&0xFFFFE000;
480   return get_addr_ht(0x80000000);
481 }
482
483 void clear_all_regs(signed char regmap[])
484 {
485   int hr;
486   for (hr=0;hr<HOST_REGS;hr++) regmap[hr]=-1;
487 }
488
489 signed char get_reg(signed char regmap[],int r)
490 {
491   int hr;
492   for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&&regmap[hr]==r) return hr;
493   return -1;
494 }
495
496 // Find a register that is available for two consecutive cycles
497 signed char get_reg2(signed char regmap1[],signed char regmap2[],int r)
498 {
499   int hr;
500   for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&&regmap1[hr]==r&&regmap2[hr]==r) return hr;
501   return -1;
502 }
503
504 int count_free_regs(signed char regmap[])
505 {
506   int count=0;
507   int hr;
508   for(hr=0;hr<HOST_REGS;hr++)
509   {
510     if(hr!=EXCLUDE_REG) {
511       if(regmap[hr]<0) count++;
512     }
513   }
514   return count;
515 }
516
517 void dirty_reg(struct regstat *cur,signed char reg)
518 {
519   int hr;
520   if(!reg) return;
521   for (hr=0;hr<HOST_REGS;hr++) {
522     if((cur->regmap[hr]&63)==reg) {
523       cur->dirty|=1<<hr;
524     }
525   }
526 }
527
528 // If we dirty the lower half of a 64 bit register which is now being
529 // sign-extended, we need to dump the upper half.
530 // Note: Do this only after completion of the instruction, because
531 // some instructions may need to read the full 64-bit value even if
532 // overwriting it (eg SLTI, DSRA32).
533 static void flush_dirty_uppers(struct regstat *cur)
534 {
535   int hr,reg;
536   for (hr=0;hr<HOST_REGS;hr++) {
537     if((cur->dirty>>hr)&1) {
538       reg=cur->regmap[hr];
539       if(reg>=64) 
540         if((cur->is32>>(reg&63))&1) cur->regmap[hr]=-1;
541     }
542   }
543 }
544
545 void set_const(struct regstat *cur,signed char reg,uint64_t value)
546 {
547   int hr;
548   if(!reg) return;
549   for (hr=0;hr<HOST_REGS;hr++) {
550     if(cur->regmap[hr]==reg) {
551       cur->isconst|=1<<hr;
552       cur->constmap[hr]=value;
553     }
554     else if((cur->regmap[hr]^64)==reg) {
555       cur->isconst|=1<<hr;
556       cur->constmap[hr]=value>>32;
557     }
558   }
559 }
560
561 void clear_const(struct regstat *cur,signed char reg)
562 {
563   int hr;
564   if(!reg) return;
565   for (hr=0;hr<HOST_REGS;hr++) {
566     if((cur->regmap[hr]&63)==reg) {
567       cur->isconst&=~(1<<hr);
568     }
569   }
570 }
571
572 int is_const(struct regstat *cur,signed char reg)
573 {
574   int hr;
575   if(!reg) return 1;
576   for (hr=0;hr<HOST_REGS;hr++) {
577     if((cur->regmap[hr]&63)==reg) {
578       return (cur->isconst>>hr)&1;
579     }
580   }
581   return 0;
582 }
583 uint64_t get_const(struct regstat *cur,signed char reg)
584 {
585   int hr;
586   if(!reg) return 0;
587   for (hr=0;hr<HOST_REGS;hr++) {
588     if(cur->regmap[hr]==reg) {
589       return cur->constmap[hr];
590     }
591   }
592   printf("Unknown constant in r%d\n",reg);
593   exit(1);
594 }
595
596 // Least soon needed registers
597 // Look at the next ten instructions and see which registers
598 // will be used.  Try not to reallocate these.
599 void lsn(u_char hsn[], int i, int *preferred_reg)
600 {
601   int j;
602   int b=-1;
603   for(j=0;j<9;j++)
604   {
605     if(i+j>=slen) {
606       j=slen-i-1;
607       break;
608     }
609     if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
610     {
611       // Don't go past an unconditonal jump
612       j++;
613       break;
614     }
615   }
616   for(;j>=0;j--)
617   {
618     if(rs1[i+j]) hsn[rs1[i+j]]=j;
619     if(rs2[i+j]) hsn[rs2[i+j]]=j;
620     if(rt1[i+j]) hsn[rt1[i+j]]=j;
621     if(rt2[i+j]) hsn[rt2[i+j]]=j;
622     if(itype[i+j]==STORE || itype[i+j]==STORELR) {
623       // Stores can allocate zero
624       hsn[rs1[i+j]]=j;
625       hsn[rs2[i+j]]=j;
626     }
627     // On some architectures stores need invc_ptr
628     #if defined(HOST_IMM8)
629     if(itype[i+j]==STORE || itype[i+j]==STORELR || (opcode[i+j]&0x3b)==0x39) {
630       hsn[INVCP]=j;
631     }
632     #endif
633     if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP))
634     {
635       hsn[CCREG]=j;
636       b=j;
637     }
638   }
639   if(b>=0)
640   {
641     if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
642     {
643       // Follow first branch
644       int t=(ba[i+b]-start)>>2;
645       j=7-b;if(t+j>=slen) j=slen-t-1;
646       for(;j>=0;j--)
647       {
648         if(rs1[t+j]) if(hsn[rs1[t+j]]>j+b+2) hsn[rs1[t+j]]=j+b+2;
649         if(rs2[t+j]) if(hsn[rs2[t+j]]>j+b+2) hsn[rs2[t+j]]=j+b+2;
650         //if(rt1[t+j]) if(hsn[rt1[t+j]]>j+b+2) hsn[rt1[t+j]]=j+b+2;
651         //if(rt2[t+j]) if(hsn[rt2[t+j]]>j+b+2) hsn[rt2[t+j]]=j+b+2;
652       }
653     }
654     // TODO: preferred register based on backward branch
655   }
656   // Delay slot should preferably not overwrite branch conditions or cycle count
657   if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)) {
658     if(rs1[i-1]) if(hsn[rs1[i-1]]>1) hsn[rs1[i-1]]=1;
659     if(rs2[i-1]) if(hsn[rs2[i-1]]>1) hsn[rs2[i-1]]=1;
660     hsn[CCREG]=1;
661     // ...or hash tables
662     hsn[RHASH]=1;
663     hsn[RHTBL]=1;
664   }
665   // Coprocessor load/store needs FTEMP, even if not declared
666   if(itype[i]==C1LS) {
667     hsn[FTEMP]=0;
668   }
669   // Load L/R also uses FTEMP as a temporary register
670   if(itype[i]==LOADLR) {
671     hsn[FTEMP]=0;
672   }
673   // Also 64-bit SDL/SDR
674   if(opcode[i]==0x2c||opcode[i]==0x2d) {
675     hsn[FTEMP]=0;
676   }
677   // Don't remove the TLB registers either
678   if(itype[i]==LOAD || itype[i]==LOADLR || itype[i]==STORE || itype[i]==STORELR || itype[i]==C1LS ) {
679     hsn[TLREG]=0;
680   }
681   // Don't remove the miniht registers
682   if(itype[i]==UJUMP||itype[i]==RJUMP)
683   {
684     hsn[RHASH]=0;
685     hsn[RHTBL]=0;
686   }
687 }
688
689 // We only want to allocate registers if we're going to use them again soon
690 int needed_again(int r, int i)
691 {
692   int j;
693   int b=-1;
694   int rn=10;
695   int hr;
696   u_char hsn[MAXREG+1];
697   int preferred_reg;
698   
699   memset(hsn,10,sizeof(hsn));
700   lsn(hsn,i,&preferred_reg);
701   
702   if(i>0&&(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000))
703   {
704     if(ba[i-1]<start || ba[i-1]>start+slen*4-4)
705       return 0; // Don't need any registers if exiting the block
706   }
707   for(j=0;j<9;j++)
708   {
709     if(i+j>=slen) {
710       j=slen-i-1;
711       break;
712     }
713     if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
714     {
715       // Don't go past an unconditonal jump
716       j++;
717       break;
718     }
719     if(itype[i+j]==SYSCALL||((source[i+j]&0xfc00003f)==0x0d))
720     {
721       break;
722     }
723   }
724   for(;j>=1;j--)
725   {
726     if(rs1[i+j]==r) rn=j;
727     if(rs2[i+j]==r) rn=j;
728     if((unneeded_reg[i+j]>>r)&1) rn=10;
729     if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP))
730     {
731       b=j;
732     }
733   }
734   /*
735   if(b>=0)
736   {
737     if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
738     {
739       // Follow first branch
740       int o=rn;
741       int t=(ba[i+b]-start)>>2;
742       j=7-b;if(t+j>=slen) j=slen-t-1;
743       for(;j>=0;j--)
744       {
745         if(!((unneeded_reg[t+j]>>r)&1)) {
746           if(rs1[t+j]==r) if(rn>j+b+2) rn=j+b+2;
747           if(rs2[t+j]==r) if(rn>j+b+2) rn=j+b+2;
748         }
749         else rn=o;
750       }
751     }
752   }*/
753   for(hr=0;hr<HOST_REGS;hr++) {
754     if(hr!=EXCLUDE_REG) {
755       if(rn<hsn[hr]) return 1;
756     }
757   }
758   return 0;
759 }
760
761 // Try to match register allocations at the end of a loop with those
762 // at the beginning
763 int loop_reg(int i, int r, int hr)
764 {
765   int j,k;
766   for(j=0;j<9;j++)
767   {
768     if(i+j>=slen) {
769       j=slen-i-1;
770       break;
771     }
772     if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
773     {
774       // Don't go past an unconditonal jump
775       j++;
776       break;
777     }
778   }
779   k=0;
780   if(i>0){
781     if(itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)
782       k--;
783   }
784   for(;k<j;k++)
785   {
786     if(r<64&&((unneeded_reg[i+k]>>r)&1)) return hr;
787     if(r>64&&((unneeded_reg_upper[i+k]>>r)&1)) return hr;
788     if(i+k>=0&&(itype[i+k]==UJUMP||itype[i+k]==CJUMP||itype[i+k]==SJUMP||itype[i+k]==FJUMP))
789     {
790       if(ba[i+k]>=start && ba[i+k]<(start+i*4))
791       {
792         int t=(ba[i+k]-start)>>2;
793         int reg=get_reg(regs[t].regmap_entry,r);
794         if(reg>=0) return reg;
795         //reg=get_reg(regs[t+1].regmap_entry,r);
796         //if(reg>=0) return reg;
797       }
798     }
799   }
800   return hr;
801 }
802
803
804 // Allocate every register, preserving source/target regs
805 void alloc_all(struct regstat *cur,int i)
806 {
807   int hr;
808   
809   for(hr=0;hr<HOST_REGS;hr++) {
810     if(hr!=EXCLUDE_REG) {
811       if(((cur->regmap[hr]&63)!=rs1[i])&&((cur->regmap[hr]&63)!=rs2[i])&&
812          ((cur->regmap[hr]&63)!=rt1[i])&&((cur->regmap[hr]&63)!=rt2[i]))
813       {
814         cur->regmap[hr]=-1;
815         cur->dirty&=~(1<<hr);
816       }
817       // Don't need zeros
818       if((cur->regmap[hr]&63)==0)
819       {
820         cur->regmap[hr]=-1;
821         cur->dirty&=~(1<<hr);
822       }
823     }
824   }
825 }
826
827
828 void div64(int64_t dividend,int64_t divisor)
829 {
830   lo=dividend/divisor;
831   hi=dividend%divisor;
832   //printf("TRACE: ddiv %8x%8x %8x%8x\n" ,(int)reg[HIREG],(int)(reg[HIREG]>>32)
833   //                                     ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
834 }
835 void divu64(uint64_t dividend,uint64_t divisor)
836 {
837   lo=dividend/divisor;
838   hi=dividend%divisor;
839   //printf("TRACE: ddivu %8x%8x %8x%8x\n",(int)reg[HIREG],(int)(reg[HIREG]>>32)
840   //                                     ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
841 }
842
843 void mult64(uint64_t m1,uint64_t m2)
844 {
845    unsigned long long int op1, op2, op3, op4;
846    unsigned long long int result1, result2, result3, result4;
847    unsigned long long int temp1, temp2, temp3, temp4;
848    int sign = 0;
849    
850    if (m1 < 0)
851      {
852     op2 = -m1;
853     sign = 1 - sign;
854      }
855    else op2 = m1;
856    if (m2 < 0)
857      {
858     op4 = -m2;
859     sign = 1 - sign;
860      }
861    else op4 = m2;
862    
863    op1 = op2 & 0xFFFFFFFF;
864    op2 = (op2 >> 32) & 0xFFFFFFFF;
865    op3 = op4 & 0xFFFFFFFF;
866    op4 = (op4 >> 32) & 0xFFFFFFFF;
867    
868    temp1 = op1 * op3;
869    temp2 = (temp1 >> 32) + op1 * op4;
870    temp3 = op2 * op3;
871    temp4 = (temp3 >> 32) + op2 * op4;
872    
873    result1 = temp1 & 0xFFFFFFFF;
874    result2 = temp2 + (temp3 & 0xFFFFFFFF);
875    result3 = (result2 >> 32) + temp4;
876    result4 = (result3 >> 32);
877    
878    lo = result1 | (result2 << 32);
879    hi = (result3 & 0xFFFFFFFF) | (result4 << 32);
880    if (sign)
881      {
882     hi = ~hi;
883     if (!lo) hi++;
884     else lo = ~lo + 1;
885      }
886 }
887
888 void multu64(uint64_t m1,uint64_t m2)
889 {
890    unsigned long long int op1, op2, op3, op4;
891    unsigned long long int result1, result2, result3, result4;
892    unsigned long long int temp1, temp2, temp3, temp4;
893    
894    op1 = m1 & 0xFFFFFFFF;
895    op2 = (m1 >> 32) & 0xFFFFFFFF;
896    op3 = m2 & 0xFFFFFFFF;
897    op4 = (m2 >> 32) & 0xFFFFFFFF;
898    
899    temp1 = op1 * op3;
900    temp2 = (temp1 >> 32) + op1 * op4;
901    temp3 = op2 * op3;
902    temp4 = (temp3 >> 32) + op2 * op4;
903    
904    result1 = temp1 & 0xFFFFFFFF;
905    result2 = temp2 + (temp3 & 0xFFFFFFFF);
906    result3 = (result2 >> 32) + temp4;
907    result4 = (result3 >> 32);
908    
909    lo = result1 | (result2 << 32);
910    hi = (result3 & 0xFFFFFFFF) | (result4 << 32);
911    
912   //printf("TRACE: dmultu %8x%8x %8x%8x\n",(int)reg[HIREG],(int)(reg[HIREG]>>32)
913   //                                      ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
914 }
915
916 uint64_t ldl_merge(uint64_t original,uint64_t loaded,u_int bits)
917 {
918   if(bits) {
919     original<<=64-bits;
920     original>>=64-bits;
921     loaded<<=bits;
922     original|=loaded;
923   }
924   else original=loaded;
925   return original;
926 }
927 uint64_t ldr_merge(uint64_t original,uint64_t loaded,u_int bits)
928 {
929   if(bits^56) {
930     original>>=64-(bits^56);
931     original<<=64-(bits^56);
932     loaded>>=bits^56;
933     original|=loaded;
934   }
935   else original=loaded;
936   return original;
937 }
938
939 #ifdef __i386__
940 #include "assem_x86.c"
941 #endif
942 #ifdef __x86_64__
943 #include "assem_x64.c"
944 #endif
945 #ifdef __arm__
946 #include "assem_arm.c"
947 #endif
948
949 // Add virtual address mapping to linked list
950 void ll_add(struct ll_entry **head,int vaddr,void *addr)
951 {
952   struct ll_entry *new_entry;
953   new_entry=malloc(sizeof(struct ll_entry));
954   assert(new_entry!=NULL);
955   new_entry->vaddr=vaddr;
956   new_entry->reg32=0;
957   new_entry->addr=addr;
958   new_entry->next=*head;
959   *head=new_entry;
960 }
961
962 // Add virtual address mapping for 32-bit compiled block
963 void ll_add_32(struct ll_entry **head,int vaddr,u_int reg32,void *addr)
964 {
965   struct ll_entry *new_entry;
966   new_entry=malloc(sizeof(struct ll_entry));
967   assert(new_entry!=NULL);
968   new_entry->vaddr=vaddr;
969   new_entry->reg32=reg32;
970   new_entry->addr=addr;
971   new_entry->next=*head;
972   *head=new_entry;
973 }
974
975 // Check if an address is already compiled
976 // but don't return addresses which are about to expire from the cache
977 void *check_addr(u_int vaddr)
978 {
979   u_int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
980   if(ht_bin[0]==vaddr) {
981     if(((ht_bin[1]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
982       if(isclean(ht_bin[1])) return (void *)ht_bin[1];
983   }
984   if(ht_bin[2]==vaddr) {
985     if(((ht_bin[3]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
986       if(isclean(ht_bin[3])) return (void *)ht_bin[3];
987   }
988   u_int page=get_page(vaddr);
989   struct ll_entry *head;
990   head=jump_in[page];
991   while(head!=NULL) {
992     if(head->vaddr==vaddr&&head->reg32==0) {
993       if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
994         // Update existing entry with current address
995         if(ht_bin[0]==vaddr) {
996           ht_bin[1]=(int)head->addr;
997           return head->addr;
998         }
999         if(ht_bin[2]==vaddr) {
1000           ht_bin[3]=(int)head->addr;
1001           return head->addr;
1002         }
1003         // Insert into hash table with low priority.
1004         // Don't evict existing entries, as they are probably
1005         // addresses that are being accessed frequently.
1006         if(ht_bin[0]==-1) {
1007           ht_bin[1]=(int)head->addr;
1008           ht_bin[0]=vaddr;
1009         }else if(ht_bin[2]==-1) {
1010           ht_bin[3]=(int)head->addr;
1011           ht_bin[2]=vaddr;
1012         }
1013         return head->addr;
1014       }
1015     }
1016     head=head->next;
1017   }
1018   return 0;
1019 }
1020
1021 void remove_hash(int vaddr)
1022 {
1023   //printf("remove hash: %x\n",vaddr);
1024   int *ht_bin=hash_table[(((vaddr)>>16)^vaddr)&0xFFFF];
1025   if(ht_bin[2]==vaddr) {
1026     ht_bin[2]=ht_bin[3]=-1;
1027   }
1028   if(ht_bin[0]==vaddr) {
1029     ht_bin[0]=ht_bin[2];
1030     ht_bin[1]=ht_bin[3];
1031     ht_bin[2]=ht_bin[3]=-1;
1032   }
1033 }
1034
1035 void ll_remove_matching_addrs(struct ll_entry **head,int addr,int shift)
1036 {
1037   struct ll_entry *next;
1038   while(*head) {
1039     if(((u_int)((*head)->addr)>>shift)==(addr>>shift) || 
1040        ((u_int)((*head)->addr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift))
1041     {
1042       inv_debug("EXP: Remove pointer to %x (%x)\n",(int)(*head)->addr,(*head)->vaddr);
1043       remove_hash((*head)->vaddr);
1044       next=(*head)->next;
1045       free(*head);
1046       *head=next;
1047     }
1048     else
1049     {
1050       head=&((*head)->next);
1051     }
1052   }
1053 }
1054
1055 // Remove all entries from linked list
1056 void ll_clear(struct ll_entry **head)
1057 {
1058   struct ll_entry *cur;
1059   struct ll_entry *next;
1060   if(cur=*head) {
1061     *head=0;
1062     while(cur) {
1063       next=cur->next;
1064       free(cur);
1065       cur=next;
1066     }
1067   }
1068 }
1069
1070 // Dereference the pointers and remove if it matches
1071 void ll_kill_pointers(struct ll_entry *head,int addr,int shift)
1072 {
1073   while(head) {
1074     int ptr=get_pointer(head->addr);
1075     inv_debug("EXP: Lookup pointer to %x at %x (%x)\n",(int)ptr,(int)head->addr,head->vaddr);
1076     if(((ptr>>shift)==(addr>>shift)) ||
1077        (((ptr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift)))
1078     {
1079       inv_debug("EXP: Kill pointer at %x (%x)\n",(int)head->addr,head->vaddr);
1080       kill_pointer(head->addr);
1081     }
1082     head=head->next;
1083   }
1084 }
1085
1086 // This is called when we write to a compiled block (see do_invstub)
1087 int invalidate_page(u_int page)
1088 {
1089   int modified=0;
1090   struct ll_entry *head;
1091   struct ll_entry *next;
1092   head=jump_in[page];
1093   jump_in[page]=0;
1094   while(head!=NULL) {
1095     inv_debug("INVALIDATE: %x\n",head->vaddr);
1096     remove_hash(head->vaddr);
1097     next=head->next;
1098     free(head);
1099     head=next;
1100   }
1101   head=jump_out[page];
1102   jump_out[page]=0;
1103   while(head!=NULL) {
1104     inv_debug("INVALIDATE: kill pointer to %x (%x)\n",head->vaddr,(int)head->addr);
1105     kill_pointer(head->addr);
1106     modified=1;
1107     next=head->next;
1108     free(head);
1109     head=next;
1110   }
1111   return modified;
1112 }
1113 void invalidate_block(u_int block)
1114 {
1115   int modified;
1116   u_int page=get_page(block<<12);
1117   u_int vpage=get_vpage(block<<12);
1118   inv_debug("INVALIDATE: %x (%d)\n",block<<12,page);
1119   //inv_debug("invalid_code[block]=%d\n",invalid_code[block]);
1120   u_int first,last;
1121   first=last=page;
1122   struct ll_entry *head;
1123   head=jump_dirty[vpage];
1124   //printf("page=%d vpage=%d\n",page,vpage);
1125   while(head!=NULL) {
1126     u_int start,end;
1127     if(vpage>2047||(head->vaddr>>12)==block) { // Ignore vaddr hash collision
1128       get_bounds((int)head->addr,&start,&end);
1129       //printf("start: %x end: %x\n",start,end);
1130       if(page<2048&&start>=0x80000000&&end<0x80800000) {
1131         if(((start-(u_int)rdram)>>12)<=page&&((end-1-(u_int)rdram)>>12)>=page) {
1132           if((((start-(u_int)rdram)>>12)&2047)<first) first=((start-(u_int)rdram)>>12)&2047;
1133           if((((end-1-(u_int)rdram)>>12)&2047)>last) last=((end-1-(u_int)rdram)>>12)&2047;
1134         }
1135       }
1136       if(page<2048&&(signed int)start>=(signed int)0xC0000000&&(signed int)end>=(signed int)0xC0000000) {
1137         if(((start+memory_map[start>>12]-(u_int)rdram)>>12)<=page&&((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)>=page) {
1138           if((((start+memory_map[start>>12]-(u_int)rdram)>>12)&2047)<first) first=((start+memory_map[start>>12]-(u_int)rdram)>>12)&2047;
1139           if((((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)&2047)>last) last=((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)&2047;
1140         }
1141       }
1142     }
1143     head=head->next;
1144   }
1145   //printf("first=%d last=%d\n",first,last);
1146   modified=invalidate_page(page);
1147   assert(first+5>page); // NB: this assumes MAXBLOCK<=4096 (4 pages)
1148   assert(last<page+5);
1149   // Invalidate the adjacent pages if a block crosses a 4K boundary
1150   while(first<page) {
1151     invalidate_page(first);
1152     first++;
1153   }
1154   for(first=page+1;first<last;first++) {
1155     invalidate_page(first);
1156   }
1157   
1158   // Don't trap writes
1159   invalid_code[block]=1;
1160 #ifndef DISABLE_TLB
1161   // If there is a valid TLB entry for this page, remove write protect
1162   if(tlb_LUT_w[block]) {
1163     assert(tlb_LUT_r[block]==tlb_LUT_w[block]);
1164     // CHECK: Is this right?
1165     memory_map[block]=((tlb_LUT_w[block]&0xFFFFF000)-(block<<12)+(unsigned int)rdram-0x80000000)>>2;
1166     u_int real_block=tlb_LUT_w[block]>>12;
1167     invalid_code[real_block]=1;
1168     if(real_block>=0x80000&&real_block<0x80800) memory_map[real_block]=((u_int)rdram-0x80000000)>>2;
1169   }
1170   else if(block>=0x80000&&block<0x80800) memory_map[block]=((u_int)rdram-0x80000000)>>2;
1171 #endif
1172   #ifdef __arm__
1173   if(modified)
1174     __clear_cache((void *)BASE_ADDR,(void *)BASE_ADDR+(1<<TARGET_SIZE_2));
1175   #endif
1176   #ifdef USE_MINI_HT
1177   memset(mini_ht,-1,sizeof(mini_ht));
1178   #endif
1179 }
1180 void invalidate_addr(u_int addr)
1181 {
1182   invalidate_block(addr>>12);
1183 }
1184 void invalidate_all_pages()
1185 {
1186   u_int page,n;
1187   for(page=0;page<4096;page++)
1188     invalidate_page(page);
1189   for(page=0;page<1048576;page++)
1190     if(!invalid_code[page]) {
1191       restore_candidate[(page&2047)>>3]|=1<<(page&7);
1192       restore_candidate[((page&2047)>>3)+256]|=1<<(page&7);
1193     }
1194   #ifdef __arm__
1195   __clear_cache((void *)BASE_ADDR,(void *)BASE_ADDR+(1<<TARGET_SIZE_2));
1196   #endif
1197   #ifdef USE_MINI_HT
1198   memset(mini_ht,-1,sizeof(mini_ht));
1199   #endif
1200   #ifndef DISABLE_TLB
1201   // TLB
1202   for(page=0;page<0x100000;page++) {
1203     if(tlb_LUT_r[page]) {
1204       memory_map[page]=((tlb_LUT_r[page]&0xFFFFF000)-(page<<12)+(unsigned int)rdram-0x80000000)>>2;
1205       if(!tlb_LUT_w[page]||!invalid_code[page])
1206         memory_map[page]|=0x40000000; // Write protect
1207     }
1208     else memory_map[page]=-1;
1209     if(page==0x80000) page=0xC0000;
1210   }
1211   tlb_hacks();
1212   #endif
1213 }
1214
1215 // Add an entry to jump_out after making a link
1216 void add_link(u_int vaddr,void *src)
1217 {
1218   u_int page=get_page(vaddr);
1219   inv_debug("add_link: %x -> %x (%d)\n",(int)src,vaddr,page);
1220   ll_add(jump_out+page,vaddr,src);
1221   //int ptr=get_pointer(src);
1222   //inv_debug("add_link: Pointer is to %x\n",(int)ptr);
1223 }
1224
1225 // If a code block was found to be unmodified (bit was set in
1226 // restore_candidate) and it remains unmodified (bit is clear
1227 // in invalid_code) then move the entries for that 4K page from
1228 // the dirty list to the clean list.
1229 void clean_blocks(u_int page)
1230 {
1231   struct ll_entry *head;
1232   inv_debug("INV: clean_blocks page=%d\n",page);
1233   head=jump_dirty[page];
1234   while(head!=NULL) {
1235     if(!invalid_code[head->vaddr>>12]) {
1236       // Don't restore blocks which are about to expire from the cache
1237       if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1238         u_int start,end;
1239         if(verify_dirty((int)head->addr)) {
1240           //printf("Possibly Restore %x (%x)\n",head->vaddr, (int)head->addr);
1241           u_int i;
1242           u_int inv=0;
1243           get_bounds((int)head->addr,&start,&end);
1244           if(start-(u_int)rdram<0x800000) {
1245             for(i=(start-(u_int)rdram+0x80000000)>>12;i<=(end-1-(u_int)rdram+0x80000000)>>12;i++) {
1246               inv|=invalid_code[i];
1247             }
1248           }
1249           if((signed int)head->vaddr>=(signed int)0xC0000000) {
1250             u_int addr = (head->vaddr+(memory_map[head->vaddr>>12]<<2));
1251             //printf("addr=%x start=%x end=%x\n",addr,start,end);
1252             if(addr<start||addr>=end) inv=1;
1253           }
1254           else if((signed int)head->vaddr>=(signed int)0x80800000) {
1255             inv=1;
1256           }
1257           if(!inv) {
1258             void * clean_addr=(void *)get_clean_addr((int)head->addr);
1259             if((((u_int)clean_addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1260               u_int ppage=page;
1261 #ifndef DISABLE_TLB
1262               if(page<2048&&tlb_LUT_r[head->vaddr>>12]) ppage=(tlb_LUT_r[head->vaddr>>12]^0x80000000)>>12;
1263 #endif
1264               inv_debug("INV: Restored %x (%x/%x)\n",head->vaddr, (int)head->addr, (int)clean_addr);
1265               //printf("page=%x, addr=%x\n",page,head->vaddr);
1266               //assert(head->vaddr>>12==(page|0x80000));
1267               ll_add_32(jump_in+ppage,head->vaddr,head->reg32,clean_addr);
1268               int *ht_bin=hash_table[((head->vaddr>>16)^head->vaddr)&0xFFFF];
1269               if(!head->reg32) {
1270                 if(ht_bin[0]==head->vaddr) {
1271                   ht_bin[1]=(int)clean_addr; // Replace existing entry
1272                 }
1273                 if(ht_bin[2]==head->vaddr) {
1274                   ht_bin[3]=(int)clean_addr; // Replace existing entry
1275                 }
1276               }
1277             }
1278           }
1279         }
1280       }
1281     }
1282     head=head->next;
1283   }
1284 }
1285
1286
1287 void mov_alloc(struct regstat *current,int i)
1288 {
1289   // Note: Don't need to actually alloc the source registers
1290   if((~current->is32>>rs1[i])&1) {
1291     //alloc_reg64(current,i,rs1[i]);
1292     alloc_reg64(current,i,rt1[i]);
1293     current->is32&=~(1LL<<rt1[i]);
1294   } else {
1295     //alloc_reg(current,i,rs1[i]);
1296     alloc_reg(current,i,rt1[i]);
1297     current->is32|=(1LL<<rt1[i]);
1298   }
1299   clear_const(current,rs1[i]);
1300   clear_const(current,rt1[i]);
1301   dirty_reg(current,rt1[i]);
1302 }
1303
1304 void shiftimm_alloc(struct regstat *current,int i)
1305 {
1306   clear_const(current,rs1[i]);
1307   clear_const(current,rt1[i]);
1308   if(opcode2[i]<=0x3) // SLL/SRL/SRA
1309   {
1310     if(rt1[i]) {
1311       if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1312       else lt1[i]=rs1[i];
1313       alloc_reg(current,i,rt1[i]);
1314       current->is32|=1LL<<rt1[i];
1315       dirty_reg(current,rt1[i]);
1316     }
1317   }
1318   if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA
1319   {
1320     if(rt1[i]) {
1321       if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1322       alloc_reg64(current,i,rt1[i]);
1323       current->is32&=~(1LL<<rt1[i]);
1324       dirty_reg(current,rt1[i]);
1325     }
1326   }
1327   if(opcode2[i]==0x3c) // DSLL32
1328   {
1329     if(rt1[i]) {
1330       if(rs1[i]) alloc_reg(current,i,rs1[i]);
1331       alloc_reg64(current,i,rt1[i]);
1332       current->is32&=~(1LL<<rt1[i]);
1333       dirty_reg(current,rt1[i]);
1334     }
1335   }
1336   if(opcode2[i]==0x3e) // DSRL32
1337   {
1338     if(rt1[i]) {
1339       alloc_reg64(current,i,rs1[i]);
1340       if(imm[i]==32) {
1341         alloc_reg64(current,i,rt1[i]);
1342         current->is32&=~(1LL<<rt1[i]);
1343       } else {
1344         alloc_reg(current,i,rt1[i]);
1345         current->is32|=1LL<<rt1[i];
1346       }
1347       dirty_reg(current,rt1[i]);
1348     }
1349   }
1350   if(opcode2[i]==0x3f) // DSRA32
1351   {
1352     if(rt1[i]) {
1353       alloc_reg64(current,i,rs1[i]);
1354       alloc_reg(current,i,rt1[i]);
1355       current->is32|=1LL<<rt1[i];
1356       dirty_reg(current,rt1[i]);
1357     }
1358   }
1359 }
1360
1361 void shift_alloc(struct regstat *current,int i)
1362 {
1363   if(rt1[i]) {
1364     if(opcode2[i]<=0x07) // SLLV/SRLV/SRAV
1365     {
1366       if(rs1[i]) alloc_reg(current,i,rs1[i]);
1367       if(rs2[i]) alloc_reg(current,i,rs2[i]);
1368       alloc_reg(current,i,rt1[i]);
1369       if(rt1[i]==rs2[i]) alloc_reg_temp(current,i,-1);
1370       current->is32|=1LL<<rt1[i];
1371     } else { // DSLLV/DSRLV/DSRAV
1372       if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1373       if(rs2[i]) alloc_reg(current,i,rs2[i]);
1374       alloc_reg64(current,i,rt1[i]);
1375       current->is32&=~(1LL<<rt1[i]);
1376       if(opcode2[i]==0x16||opcode2[i]==0x17) // DSRLV and DSRAV need a temporary register
1377         alloc_reg_temp(current,i,-1);
1378     }
1379     clear_const(current,rs1[i]);
1380     clear_const(current,rs2[i]);
1381     clear_const(current,rt1[i]);
1382     dirty_reg(current,rt1[i]);
1383   }
1384 }
1385
1386 void alu_alloc(struct regstat *current,int i)
1387 {
1388   if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
1389     if(rt1[i]) {
1390       if(rs1[i]&&rs2[i]) {
1391         alloc_reg(current,i,rs1[i]);
1392         alloc_reg(current,i,rs2[i]);
1393       }
1394       else {
1395         if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1396         if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]);
1397       }
1398       alloc_reg(current,i,rt1[i]);
1399     }
1400     current->is32|=1LL<<rt1[i];
1401   }
1402   if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU
1403     if(rt1[i]) {
1404       if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1405       {
1406         alloc_reg64(current,i,rs1[i]);
1407         alloc_reg64(current,i,rs2[i]);
1408         alloc_reg(current,i,rt1[i]);
1409       } else {
1410         alloc_reg(current,i,rs1[i]);
1411         alloc_reg(current,i,rs2[i]);
1412         alloc_reg(current,i,rt1[i]);
1413       }
1414     }
1415     current->is32|=1LL<<rt1[i];
1416   }
1417   if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR
1418     if(rt1[i]) {
1419       if(rs1[i]&&rs2[i]) {
1420         alloc_reg(current,i,rs1[i]);
1421         alloc_reg(current,i,rs2[i]);
1422       }
1423       else
1424       {
1425         if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1426         if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]);
1427       }
1428       alloc_reg(current,i,rt1[i]);
1429       if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1430       {
1431         if(!((current->uu>>rt1[i])&1)) {
1432           alloc_reg64(current,i,rt1[i]);
1433         }
1434         if(get_reg(current->regmap,rt1[i]|64)>=0) {
1435           if(rs1[i]&&rs2[i]) {
1436             alloc_reg64(current,i,rs1[i]);
1437             alloc_reg64(current,i,rs2[i]);
1438           }
1439           else
1440           {
1441             // Is is really worth it to keep 64-bit values in registers?
1442             #ifdef NATIVE_64BIT
1443             if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]);
1444             if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg64(current,i,rs2[i]);
1445             #endif
1446           }
1447         }
1448         current->is32&=~(1LL<<rt1[i]);
1449       } else {
1450         current->is32|=1LL<<rt1[i];
1451       }
1452     }
1453   }
1454   if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU
1455     if(rt1[i]) {
1456       if(rs1[i]&&rs2[i]) {
1457         if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1458           alloc_reg64(current,i,rs1[i]);
1459           alloc_reg64(current,i,rs2[i]);
1460           alloc_reg64(current,i,rt1[i]);
1461         } else {
1462           alloc_reg(current,i,rs1[i]);
1463           alloc_reg(current,i,rs2[i]);
1464           alloc_reg(current,i,rt1[i]);
1465         }
1466       }
1467       else {
1468         alloc_reg(current,i,rt1[i]);
1469         if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1470           // DADD used as move, or zeroing
1471           // If we have a 64-bit source, then make the target 64 bits too
1472           if(rs1[i]&&!((current->is32>>rs1[i])&1)) {
1473             if(get_reg(current->regmap,rs1[i])>=0) alloc_reg64(current,i,rs1[i]);
1474             alloc_reg64(current,i,rt1[i]);
1475           } else if(rs2[i]&&!((current->is32>>rs2[i])&1)) {
1476             if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]);
1477             alloc_reg64(current,i,rt1[i]);
1478           }
1479           if(opcode2[i]>=0x2e&&rs2[i]) {
1480             // DSUB used as negation - 64-bit result
1481             // If we have a 32-bit register, extend it to 64 bits
1482             if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]);
1483             alloc_reg64(current,i,rt1[i]);
1484           }
1485         }
1486       }
1487       if(rs1[i]&&rs2[i]) {
1488         current->is32&=~(1LL<<rt1[i]);
1489       } else if(rs1[i]) {
1490         current->is32&=~(1LL<<rt1[i]);
1491         if((current->is32>>rs1[i])&1)
1492           current->is32|=1LL<<rt1[i];
1493       } else if(rs2[i]) {
1494         current->is32&=~(1LL<<rt1[i]);
1495         if((current->is32>>rs2[i])&1)
1496           current->is32|=1LL<<rt1[i];
1497       } else {
1498         current->is32|=1LL<<rt1[i];
1499       }
1500     }
1501   }
1502   clear_const(current,rs1[i]);
1503   clear_const(current,rs2[i]);
1504   clear_const(current,rt1[i]);
1505   dirty_reg(current,rt1[i]);
1506 }
1507
1508 void imm16_alloc(struct regstat *current,int i)
1509 {
1510   if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1511   else lt1[i]=rs1[i];
1512   if(rt1[i]) alloc_reg(current,i,rt1[i]);
1513   if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU
1514     current->is32&=~(1LL<<rt1[i]);
1515     if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1516       // TODO: Could preserve the 32-bit flag if the immediate is zero
1517       alloc_reg64(current,i,rt1[i]);
1518       alloc_reg64(current,i,rs1[i]);
1519     }
1520     clear_const(current,rs1[i]);
1521     clear_const(current,rt1[i]);
1522   }
1523   else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU
1524     if((~current->is32>>rs1[i])&1) alloc_reg64(current,i,rs1[i]);
1525     current->is32|=1LL<<rt1[i];
1526     clear_const(current,rs1[i]);
1527     clear_const(current,rt1[i]);
1528   }
1529   else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI
1530     if(((~current->is32>>rs1[i])&1)&&opcode[i]>0x0c) {
1531       if(rs1[i]!=rt1[i]) {
1532         if(needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]);
1533         alloc_reg64(current,i,rt1[i]);
1534         current->is32&=~(1LL<<rt1[i]);
1535       }
1536     }
1537     else current->is32|=1LL<<rt1[i]; // ANDI clears upper bits
1538     if(is_const(current,rs1[i])) {
1539       int v=get_const(current,rs1[i]);
1540       if(opcode[i]==0x0c) set_const(current,rt1[i],v&imm[i]);
1541       if(opcode[i]==0x0d) set_const(current,rt1[i],v|imm[i]);
1542       if(opcode[i]==0x0e) set_const(current,rt1[i],v^imm[i]);
1543     }
1544     else clear_const(current,rt1[i]);
1545   }
1546   else if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU
1547     if(is_const(current,rs1[i])) {
1548       int v=get_const(current,rs1[i]);
1549       set_const(current,rt1[i],v+imm[i]);
1550     }
1551     else clear_const(current,rt1[i]);
1552     current->is32|=1LL<<rt1[i];
1553   }
1554   else {
1555     set_const(current,rt1[i],((long long)((short)imm[i]))<<16); // LUI
1556     current->is32|=1LL<<rt1[i];
1557   }
1558   dirty_reg(current,rt1[i]);
1559 }
1560
1561 void load_alloc(struct regstat *current,int i)
1562 {
1563   clear_const(current,rt1[i]);
1564   //if(rs1[i]!=rt1[i]&&needed_again(rs1[i],i)) clear_const(current,rs1[i]); // Does this help or hurt?
1565   if(!rs1[i]) current->u&=~1LL; // Allow allocating r0 if it's the source register
1566   if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1567   if(rt1[i]) {
1568     alloc_reg(current,i,rt1[i]);
1569     if(opcode[i]==0x27||opcode[i]==0x37) // LWU/LD
1570     {
1571       current->is32&=~(1LL<<rt1[i]);
1572       alloc_reg64(current,i,rt1[i]);
1573     }
1574     else if(opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
1575     {
1576       current->is32&=~(1LL<<rt1[i]);
1577       alloc_reg64(current,i,rt1[i]);
1578       alloc_all(current,i);
1579       alloc_reg64(current,i,FTEMP);
1580     }
1581     else current->is32|=1LL<<rt1[i];
1582     dirty_reg(current,rt1[i]);
1583     // If using TLB, need a register for pointer to the mapping table
1584     if(using_tlb) alloc_reg(current,i,TLREG);
1585     // LWL/LWR need a temporary register for the old value
1586     if(opcode[i]==0x22||opcode[i]==0x26)
1587     {
1588       alloc_reg(current,i,FTEMP);
1589       alloc_reg_temp(current,i,-1);
1590     }
1591   }
1592   else
1593   {
1594     // Load to r0 (dummy load)
1595     // but we still need a register to calculate the address
1596     alloc_reg_temp(current,i,-1);
1597   }
1598 }
1599
1600 void store_alloc(struct regstat *current,int i)
1601 {
1602   clear_const(current,rs2[i]);
1603   if(!(rs2[i])) current->u&=~1LL; // Allow allocating r0 if necessary
1604   if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1605   alloc_reg(current,i,rs2[i]);
1606   if(opcode[i]==0x2c||opcode[i]==0x2d||opcode[i]==0x3f) { // 64-bit SDL/SDR/SD
1607     alloc_reg64(current,i,rs2[i]);
1608     if(rs2[i]) alloc_reg(current,i,FTEMP);
1609   }
1610   // If using TLB, need a register for pointer to the mapping table
1611   if(using_tlb) alloc_reg(current,i,TLREG);
1612   #if defined(HOST_IMM8)
1613   // On CPUs without 32-bit immediates we need a pointer to invalid_code
1614   else alloc_reg(current,i,INVCP);
1615   #endif
1616   if(opcode[i]==0x2c||opcode[i]==0x2d) { // 64-bit SDL/SDR
1617     alloc_reg(current,i,FTEMP);
1618   }
1619   // We need a temporary register for address generation
1620   alloc_reg_temp(current,i,-1);
1621 }
1622
1623 void c1ls_alloc(struct regstat *current,int i)
1624 {
1625   //clear_const(current,rs1[i]); // FIXME
1626   clear_const(current,rt1[i]);
1627   if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1628   alloc_reg(current,i,CSREG); // Status
1629   alloc_reg(current,i,FTEMP);
1630   if(opcode[i]==0x35||opcode[i]==0x3d) { // 64-bit LDC1/SDC1
1631     alloc_reg64(current,i,FTEMP);
1632   }
1633   // If using TLB, need a register for pointer to the mapping table
1634   if(using_tlb) alloc_reg(current,i,TLREG);
1635   #if defined(HOST_IMM8)
1636   // On CPUs without 32-bit immediates we need a pointer to invalid_code
1637   else if((opcode[i]&0x3b)==0x39) // SWC1/SDC1
1638     alloc_reg(current,i,INVCP);
1639   #endif
1640   // We need a temporary register for address generation
1641   alloc_reg_temp(current,i,-1);
1642 }
1643
1644 #ifndef multdiv_alloc
1645 void multdiv_alloc(struct regstat *current,int i)
1646 {
1647   //  case 0x18: MULT
1648   //  case 0x19: MULTU
1649   //  case 0x1A: DIV
1650   //  case 0x1B: DIVU
1651   //  case 0x1C: DMULT
1652   //  case 0x1D: DMULTU
1653   //  case 0x1E: DDIV
1654   //  case 0x1F: DDIVU
1655   clear_const(current,rs1[i]);
1656   clear_const(current,rs2[i]);
1657   if(rs1[i]&&rs2[i])
1658   {
1659     if((opcode2[i]&4)==0) // 32-bit
1660     {
1661       current->u&=~(1LL<<HIREG);
1662       current->u&=~(1LL<<LOREG);
1663       alloc_reg(current,i,HIREG);
1664       alloc_reg(current,i,LOREG);
1665       alloc_reg(current,i,rs1[i]);
1666       alloc_reg(current,i,rs2[i]);
1667       current->is32|=1LL<<HIREG;
1668       current->is32|=1LL<<LOREG;
1669       dirty_reg(current,HIREG);
1670       dirty_reg(current,LOREG);
1671     }
1672     else // 64-bit
1673     {
1674       current->u&=~(1LL<<HIREG);
1675       current->u&=~(1LL<<LOREG);
1676       current->uu&=~(1LL<<HIREG);
1677       current->uu&=~(1LL<<LOREG);
1678       alloc_reg64(current,i,HIREG);
1679       //if(HOST_REGS>10) alloc_reg64(current,i,LOREG);
1680       alloc_reg64(current,i,rs1[i]);
1681       alloc_reg64(current,i,rs2[i]);
1682       alloc_all(current,i);
1683       current->is32&=~(1LL<<HIREG);
1684       current->is32&=~(1LL<<LOREG);
1685       dirty_reg(current,HIREG);
1686       dirty_reg(current,LOREG);
1687     }
1688   }
1689   else
1690   {
1691     // Multiply by zero is zero.
1692     // MIPS does not have a divide by zero exception.
1693     // The result is undefined, we return zero.
1694     alloc_reg(current,i,HIREG);
1695     alloc_reg(current,i,LOREG);
1696     current->is32|=1LL<<HIREG;
1697     current->is32|=1LL<<LOREG;
1698     dirty_reg(current,HIREG);
1699     dirty_reg(current,LOREG);
1700   }
1701 }
1702 #endif
1703
1704 void cop0_alloc(struct regstat *current,int i)
1705 {
1706   if(opcode2[i]==0) // MFC0
1707   {
1708     if(rt1[i]) {
1709       clear_const(current,rt1[i]);
1710       alloc_all(current,i);
1711       alloc_reg(current,i,rt1[i]);
1712       current->is32|=1LL<<rt1[i];
1713       dirty_reg(current,rt1[i]);
1714     }
1715   }
1716   else if(opcode2[i]==4) // MTC0
1717   {
1718     if(rs1[i]){
1719       clear_const(current,rs1[i]);
1720       alloc_reg(current,i,rs1[i]);
1721       alloc_all(current,i);
1722     }
1723     else {
1724       alloc_all(current,i); // FIXME: Keep r0
1725       current->u&=~1LL;
1726       alloc_reg(current,i,0);
1727     }
1728   }
1729   else
1730   {
1731     // TLBR/TLBWI/TLBWR/TLBP/ERET
1732     assert(opcode2[i]==0x10);
1733     alloc_all(current,i);
1734   }
1735 }
1736
1737 void cop1_alloc(struct regstat *current,int i)
1738 {
1739   alloc_reg(current,i,CSREG); // Load status
1740   if(opcode2[i]<3) // MFC1/DMFC1/CFC1
1741   {
1742     assert(rt1[i]);
1743     clear_const(current,rt1[i]);
1744     if(opcode2[i]==1) {
1745       alloc_reg64(current,i,rt1[i]); // DMFC1
1746       current->is32&=~(1LL<<rt1[i]);
1747     }else{
1748       alloc_reg(current,i,rt1[i]); // MFC1/CFC1
1749       current->is32|=1LL<<rt1[i];
1750     }
1751     dirty_reg(current,rt1[i]);
1752     alloc_reg_temp(current,i,-1);
1753   }
1754   else if(opcode2[i]>3) // MTC1/DMTC1/CTC1
1755   {
1756     if(rs1[i]){
1757       clear_const(current,rs1[i]);
1758       if(opcode2[i]==5)
1759         alloc_reg64(current,i,rs1[i]); // DMTC1
1760       else
1761         alloc_reg(current,i,rs1[i]); // MTC1/CTC1
1762       alloc_reg_temp(current,i,-1);
1763     }
1764     else {
1765       current->u&=~1LL;
1766       alloc_reg(current,i,0);
1767       alloc_reg_temp(current,i,-1);
1768     }
1769   }
1770 }
1771 void fconv_alloc(struct regstat *current,int i)
1772 {
1773   alloc_reg(current,i,CSREG); // Load status
1774   alloc_reg_temp(current,i,-1);
1775 }
1776 void float_alloc(struct regstat *current,int i)
1777 {
1778   alloc_reg(current,i,CSREG); // Load status
1779   alloc_reg_temp(current,i,-1);
1780 }
1781 void fcomp_alloc(struct regstat *current,int i)
1782 {
1783   alloc_reg(current,i,CSREG); // Load status
1784   alloc_reg(current,i,FSREG); // Load flags
1785   dirty_reg(current,FSREG); // Flag will be modified
1786   alloc_reg_temp(current,i,-1);
1787 }
1788
1789 void syscall_alloc(struct regstat *current,int i)
1790 {
1791   alloc_cc(current,i);
1792   dirty_reg(current,CCREG);
1793   alloc_all(current,i);
1794   current->isconst=0;
1795 }
1796
1797 void delayslot_alloc(struct regstat *current,int i)
1798 {
1799   switch(itype[i]) {
1800     case UJUMP:
1801     case CJUMP:
1802     case SJUMP:
1803     case RJUMP:
1804     case FJUMP:
1805     case SYSCALL:
1806     case SPAN:
1807       assem_debug("jump in the delay slot.  this shouldn't happen.\n");//exit(1);
1808       printf("Disabled speculative precompilation\n");
1809       stop_after_jal=1;
1810       break;
1811     case IMM16:
1812       imm16_alloc(current,i);
1813       break;
1814     case LOAD:
1815     case LOADLR:
1816       load_alloc(current,i);
1817       break;
1818     case STORE:
1819     case STORELR:
1820       store_alloc(current,i);
1821       break;
1822     case ALU:
1823       alu_alloc(current,i);
1824       break;
1825     case SHIFT:
1826       shift_alloc(current,i);
1827       break;
1828     case MULTDIV:
1829       multdiv_alloc(current,i);
1830       break;
1831     case SHIFTIMM:
1832       shiftimm_alloc(current,i);
1833       break;
1834     case MOV:
1835       mov_alloc(current,i);
1836       break;
1837     case COP0:
1838       cop0_alloc(current,i);
1839       break;
1840     case COP1:
1841       cop1_alloc(current,i);
1842       break;
1843     case C1LS:
1844       c1ls_alloc(current,i);
1845       break;
1846     case FCONV:
1847       fconv_alloc(current,i);
1848       break;
1849     case FLOAT:
1850       float_alloc(current,i);
1851       break;
1852     case FCOMP:
1853       fcomp_alloc(current,i);
1854       break;
1855   }
1856 }
1857
1858 // Special case where a branch and delay slot span two pages in virtual memory
1859 static void pagespan_alloc(struct regstat *current,int i)
1860 {
1861   current->isconst=0;
1862   current->wasconst=0;
1863   regs[i].wasconst=0;
1864   alloc_all(current,i);
1865   alloc_cc(current,i);
1866   dirty_reg(current,CCREG);
1867   if(opcode[i]==3) // JAL
1868   {
1869     alloc_reg(current,i,31);
1870     dirty_reg(current,31);
1871   }
1872   if(opcode[i]==0&&(opcode2[i]&0x3E)==8) // JR/JALR
1873   {
1874     alloc_reg(current,i,rs1[i]);
1875     if (rt1[i]==31) {
1876       alloc_reg(current,i,31);
1877       dirty_reg(current,31);
1878     }
1879   }
1880   if((opcode[i]&0x2E)==4) // BEQ/BNE/BEQL/BNEL
1881   {
1882     if(rs1[i]) alloc_reg(current,i,rs1[i]);
1883     if(rs2[i]) alloc_reg(current,i,rs2[i]);
1884     if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1885     {
1886       if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1887       if(rs2[i]) alloc_reg64(current,i,rs2[i]);
1888     }
1889   }
1890   else
1891   if((opcode[i]&0x2E)==6) // BLEZ/BGTZ/BLEZL/BGTZL
1892   {
1893     if(rs1[i]) alloc_reg(current,i,rs1[i]);
1894     if(!((current->is32>>rs1[i])&1))
1895     {
1896       if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1897     }
1898   }
1899   else
1900   if(opcode[i]==0x11) // BC1
1901   {
1902     alloc_reg(current,i,FSREG);
1903     alloc_reg(current,i,CSREG);
1904   }
1905   //else ...
1906 }
1907
1908 add_stub(int type,int addr,int retaddr,int a,int b,int c,int d,int e)
1909 {
1910   stubs[stubcount][0]=type;
1911   stubs[stubcount][1]=addr;
1912   stubs[stubcount][2]=retaddr;
1913   stubs[stubcount][3]=a;
1914   stubs[stubcount][4]=b;
1915   stubs[stubcount][5]=c;
1916   stubs[stubcount][6]=d;
1917   stubs[stubcount][7]=e;
1918   stubcount++;
1919 }
1920
1921 // Write out a single register
1922 void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32)
1923 {
1924   int hr;
1925   for(hr=0;hr<HOST_REGS;hr++) {
1926     if(hr!=EXCLUDE_REG) {
1927       if((regmap[hr]&63)==r) {
1928         if((dirty>>hr)&1) {
1929           if(regmap[hr]<64) {
1930             emit_storereg(r,hr);
1931             if((is32>>regmap[hr])&1) {
1932               emit_sarimm(hr,31,hr);
1933               emit_storereg(r|64,hr);
1934             }
1935           }else{
1936             emit_storereg(r|64,hr);
1937           }
1938         }
1939       }
1940     }
1941   }
1942 }
1943
1944 int mchecksum()
1945 {
1946   //if(!tracedebug) return 0;
1947   int i;
1948   int sum=0;
1949   for(i=0;i<2097152;i++) {
1950     unsigned int temp=sum;
1951     sum<<=1;
1952     sum|=(~temp)>>31;
1953     sum^=((u_int *)rdram)[i];
1954   }
1955   return sum;
1956 }
1957 int rchecksum()
1958 {
1959   int i;
1960   int sum=0;
1961   for(i=0;i<64;i++)
1962     sum^=((u_int *)reg)[i];
1963   return sum;
1964 }
1965 void rlist()
1966 {
1967   int i;
1968   printf("TRACE: ");
1969   for(i=0;i<32;i++)
1970     printf("r%d:%8x%8x ",i,((int *)(reg+i))[1],((int *)(reg+i))[0]);
1971   printf("\n");
1972 #ifndef DISABLE_COP1
1973   printf("TRACE: ");
1974   for(i=0;i<32;i++)
1975     printf("f%d:%8x%8x ",i,((int*)reg_cop1_simple[i])[1],*((int*)reg_cop1_simple[i]));
1976   printf("\n");
1977 #endif
1978 }
1979
1980 void enabletrace()
1981 {
1982   tracedebug=1;
1983 }
1984
1985 void memdebug(int i)
1986 {
1987   //printf("TRACE: count=%d next=%d (checksum %x) lo=%8x%8x\n",Count,next_interupt,mchecksum(),(int)(reg[LOREG]>>32),(int)reg[LOREG]);
1988   //printf("TRACE: count=%d next=%d (rchecksum %x)\n",Count,next_interupt,rchecksum());
1989   //rlist();
1990   //if(tracedebug) {
1991   //if(Count>=-2084597794) {
1992   if((signed int)Count>=-2084597794&&(signed int)Count<0) {
1993   //if(0) {
1994     printf("TRACE: count=%d next=%d (checksum %x)\n",Count,next_interupt,mchecksum());
1995     //printf("TRACE: count=%d next=%d (checksum %x) Status=%x\n",Count,next_interupt,mchecksum(),Status);
1996     //printf("TRACE: count=%d next=%d (checksum %x) hi=%8x%8x\n",Count,next_interupt,mchecksum(),(int)(reg[HIREG]>>32),(int)reg[HIREG]);
1997     rlist();
1998     #ifdef __i386__
1999     printf("TRACE: %x\n",(&i)[-1]);
2000     #endif
2001     #ifdef __arm__
2002     int j;
2003     printf("TRACE: %x \n",(&j)[10]);
2004     printf("TRACE: %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x\n",(&j)[1],(&j)[2],(&j)[3],(&j)[4],(&j)[5],(&j)[6],(&j)[7],(&j)[8],(&j)[9],(&j)[10],(&j)[11],(&j)[12],(&j)[13],(&j)[14],(&j)[15],(&j)[16],(&j)[17],(&j)[18],(&j)[19],(&j)[20]);
2005     #endif
2006     //fflush(stdout);
2007   }
2008   //printf("TRACE: %x\n",(&i)[-1]);
2009 }
2010
2011 void tlb_debug(u_int cause, u_int addr, u_int iaddr)
2012 {
2013   printf("TLB Exception: instruction=%x addr=%x cause=%x\n",iaddr, addr, cause);
2014 }
2015
2016 void alu_assemble(int i,struct regstat *i_regs)
2017 {
2018   if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
2019     if(rt1[i]) {
2020       signed char s1,s2,t;
2021       t=get_reg(i_regs->regmap,rt1[i]);
2022       if(t>=0) {
2023         s1=get_reg(i_regs->regmap,rs1[i]);
2024         s2=get_reg(i_regs->regmap,rs2[i]);
2025         if(rs1[i]&&rs2[i]) {
2026           assert(s1>=0);
2027           assert(s2>=0);
2028           if(opcode2[i]&2) emit_sub(s1,s2,t);
2029           else emit_add(s1,s2,t);
2030         }
2031         else if(rs1[i]) {
2032           if(s1>=0) emit_mov(s1,t);
2033           else emit_loadreg(rs1[i],t);
2034         }
2035         else if(rs2[i]) {
2036           if(s2>=0) {
2037             if(opcode2[i]&2) emit_neg(s2,t);
2038             else emit_mov(s2,t);
2039           }
2040           else {
2041             emit_loadreg(rs2[i],t);
2042             if(opcode2[i]&2) emit_neg(t,t);
2043           }
2044         }
2045         else emit_zeroreg(t);
2046       }
2047     }
2048   }
2049   if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU
2050     if(rt1[i]) {
2051       signed char s1l,s2l,s1h,s2h,tl,th;
2052       tl=get_reg(i_regs->regmap,rt1[i]);
2053       th=get_reg(i_regs->regmap,rt1[i]|64);
2054       if(tl>=0) {
2055         s1l=get_reg(i_regs->regmap,rs1[i]);
2056         s2l=get_reg(i_regs->regmap,rs2[i]);
2057         s1h=get_reg(i_regs->regmap,rs1[i]|64);
2058         s2h=get_reg(i_regs->regmap,rs2[i]|64);
2059         if(rs1[i]&&rs2[i]) {
2060           assert(s1l>=0);
2061           assert(s2l>=0);
2062           if(opcode2[i]&2) emit_subs(s1l,s2l,tl);
2063           else emit_adds(s1l,s2l,tl);
2064           if(th>=0) {
2065             #ifdef INVERTED_CARRY
2066             if(opcode2[i]&2) {if(s1h!=th) emit_mov(s1h,th);emit_sbb(th,s2h);}
2067             #else
2068             if(opcode2[i]&2) emit_sbc(s1h,s2h,th);
2069             #endif
2070             else emit_add(s1h,s2h,th);
2071           }
2072         }
2073         else if(rs1[i]) {
2074           if(s1l>=0) emit_mov(s1l,tl);
2075           else emit_loadreg(rs1[i],tl);
2076           if(th>=0) {
2077             if(s1h>=0) emit_mov(s1h,th);
2078             else emit_loadreg(rs1[i]|64,th);
2079           }
2080         }
2081         else if(rs2[i]) {
2082           if(s2l>=0) {
2083             if(opcode2[i]&2) emit_negs(s2l,tl);
2084             else emit_mov(s2l,tl);
2085           }
2086           else {
2087             emit_loadreg(rs2[i],tl);
2088             if(opcode2[i]&2) emit_negs(tl,tl);
2089           }
2090           if(th>=0) {
2091             #ifdef INVERTED_CARRY
2092             if(s2h>=0) emit_mov(s2h,th);
2093             else emit_loadreg(rs2[i]|64,th);
2094             if(opcode2[i]&2) {
2095               emit_adcimm(-1,th); // x86 has inverted carry flag
2096               emit_not(th,th);
2097             }
2098             #else
2099             if(opcode2[i]&2) {
2100               if(s2h>=0) emit_rscimm(s2h,0,th);
2101               else {
2102                 emit_loadreg(rs2[i]|64,th);
2103                 emit_rscimm(th,0,th);
2104               }
2105             }else{
2106               if(s2h>=0) emit_mov(s2h,th);
2107               else emit_loadreg(rs2[i]|64,th);
2108             }
2109             #endif
2110           }
2111         }
2112         else {
2113           emit_zeroreg(tl);
2114           if(th>=0) emit_zeroreg(th);
2115         }
2116       }
2117     }
2118   }
2119   if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU
2120     if(rt1[i]) {
2121       signed char s1l,s1h,s2l,s2h,t;
2122       if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1))
2123       {
2124         t=get_reg(i_regs->regmap,rt1[i]);
2125         //assert(t>=0);
2126         if(t>=0) {
2127           s1l=get_reg(i_regs->regmap,rs1[i]);
2128           s1h=get_reg(i_regs->regmap,rs1[i]|64);
2129           s2l=get_reg(i_regs->regmap,rs2[i]);
2130           s2h=get_reg(i_regs->regmap,rs2[i]|64);
2131           if(rs2[i]==0) // rx<r0
2132           {
2133             assert(s1h>=0);
2134             if(opcode2[i]==0x2a) // SLT
2135               emit_shrimm(s1h,31,t);
2136             else // SLTU (unsigned can not be less than zero)
2137               emit_zeroreg(t);
2138           }
2139           else if(rs1[i]==0) // r0<rx
2140           {
2141             assert(s2h>=0);
2142             if(opcode2[i]==0x2a) // SLT
2143               emit_set_gz64_32(s2h,s2l,t);
2144             else // SLTU (set if not zero)
2145               emit_set_nz64_32(s2h,s2l,t);
2146           }
2147           else {
2148             assert(s1l>=0);assert(s1h>=0);
2149             assert(s2l>=0);assert(s2h>=0);
2150             if(opcode2[i]==0x2a) // SLT
2151               emit_set_if_less64_32(s1h,s1l,s2h,s2l,t);
2152             else // SLTU
2153               emit_set_if_carry64_32(s1h,s1l,s2h,s2l,t);
2154           }
2155         }
2156       } else {
2157         t=get_reg(i_regs->regmap,rt1[i]);
2158         //assert(t>=0);
2159         if(t>=0) {
2160           s1l=get_reg(i_regs->regmap,rs1[i]);
2161           s2l=get_reg(i_regs->regmap,rs2[i]);
2162           if(rs2[i]==0) // rx<r0
2163           {
2164             assert(s1l>=0);
2165             if(opcode2[i]==0x2a) // SLT
2166               emit_shrimm(s1l,31,t);
2167             else // SLTU (unsigned can not be less than zero)
2168               emit_zeroreg(t);
2169           }
2170           else if(rs1[i]==0) // r0<rx
2171           {
2172             assert(s2l>=0);
2173             if(opcode2[i]==0x2a) // SLT
2174               emit_set_gz32(s2l,t);
2175             else // SLTU (set if not zero)
2176               emit_set_nz32(s2l,t);
2177           }
2178           else{
2179             assert(s1l>=0);assert(s2l>=0);
2180             if(opcode2[i]==0x2a) // SLT
2181               emit_set_if_less32(s1l,s2l,t);
2182             else // SLTU
2183               emit_set_if_carry32(s1l,s2l,t);
2184           }
2185         }
2186       }
2187     }
2188   }
2189   if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR
2190     if(rt1[i]) {
2191       signed char s1l,s1h,s2l,s2h,th,tl;
2192       tl=get_reg(i_regs->regmap,rt1[i]);
2193       th=get_reg(i_regs->regmap,rt1[i]|64);
2194       if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1)&&th>=0)
2195       {
2196         assert(tl>=0);
2197         if(tl>=0) {
2198           s1l=get_reg(i_regs->regmap,rs1[i]);
2199           s1h=get_reg(i_regs->regmap,rs1[i]|64);
2200           s2l=get_reg(i_regs->regmap,rs2[i]);
2201           s2h=get_reg(i_regs->regmap,rs2[i]|64);
2202           if(rs1[i]&&rs2[i]) {
2203             assert(s1l>=0);assert(s1h>=0);
2204             assert(s2l>=0);assert(s2h>=0);
2205             if(opcode2[i]==0x24) { // AND
2206               emit_and(s1l,s2l,tl);
2207               emit_and(s1h,s2h,th);
2208             } else
2209             if(opcode2[i]==0x25) { // OR
2210               emit_or(s1l,s2l,tl);
2211               emit_or(s1h,s2h,th);
2212             } else
2213             if(opcode2[i]==0x26) { // XOR
2214               emit_xor(s1l,s2l,tl);
2215               emit_xor(s1h,s2h,th);
2216             } else
2217             if(opcode2[i]==0x27) { // NOR
2218               emit_or(s1l,s2l,tl);
2219               emit_or(s1h,s2h,th);
2220               emit_not(tl,tl);
2221               emit_not(th,th);
2222             }
2223           }
2224           else
2225           {
2226             if(opcode2[i]==0x24) { // AND
2227               emit_zeroreg(tl);
2228               emit_zeroreg(th);
2229             } else
2230             if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR
2231               if(rs1[i]){
2232                 if(s1l>=0) emit_mov(s1l,tl);
2233                 else emit_loadreg(rs1[i],tl);
2234                 if(s1h>=0) emit_mov(s1h,th);
2235                 else emit_loadreg(rs1[i]|64,th);
2236               }
2237               else
2238               if(rs2[i]){
2239                 if(s2l>=0) emit_mov(s2l,tl);
2240                 else emit_loadreg(rs2[i],tl);
2241                 if(s2h>=0) emit_mov(s2h,th);
2242                 else emit_loadreg(rs2[i]|64,th);
2243               }
2244               else{
2245                 emit_zeroreg(tl);
2246                 emit_zeroreg(th);
2247               }
2248             } else
2249             if(opcode2[i]==0x27) { // NOR
2250               if(rs1[i]){
2251                 if(s1l>=0) emit_not(s1l,tl);
2252                 else{
2253                   emit_loadreg(rs1[i],tl);
2254                   emit_not(tl,tl);
2255                 }
2256                 if(s1h>=0) emit_not(s1h,th);
2257                 else{
2258                   emit_loadreg(rs1[i]|64,th);
2259                   emit_not(th,th);
2260                 }
2261               }
2262               else
2263               if(rs2[i]){
2264                 if(s2l>=0) emit_not(s2l,tl);
2265                 else{
2266                   emit_loadreg(rs2[i],tl);
2267                   emit_not(tl,tl);
2268                 }
2269                 if(s2h>=0) emit_not(s2h,th);
2270                 else{
2271                   emit_loadreg(rs2[i]|64,th);
2272                   emit_not(th,th);
2273                 }
2274               }
2275               else {
2276                 emit_movimm(-1,tl);
2277                 emit_movimm(-1,th);
2278               }
2279             }
2280           }
2281         }
2282       }
2283       else
2284       {
2285         // 32 bit
2286         if(tl>=0) {
2287           s1l=get_reg(i_regs->regmap,rs1[i]);
2288           s2l=get_reg(i_regs->regmap,rs2[i]);
2289           if(rs1[i]&&rs2[i]) {
2290             assert(s1l>=0);
2291             assert(s2l>=0);
2292             if(opcode2[i]==0x24) { // AND
2293               emit_and(s1l,s2l,tl);
2294             } else
2295             if(opcode2[i]==0x25) { // OR
2296               emit_or(s1l,s2l,tl);
2297             } else
2298             if(opcode2[i]==0x26) { // XOR
2299               emit_xor(s1l,s2l,tl);
2300             } else
2301             if(opcode2[i]==0x27) { // NOR
2302               emit_or(s1l,s2l,tl);
2303               emit_not(tl,tl);
2304             }
2305           }
2306           else
2307           {
2308             if(opcode2[i]==0x24) { // AND
2309               emit_zeroreg(tl);
2310             } else
2311             if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR
2312               if(rs1[i]){
2313                 if(s1l>=0) emit_mov(s1l,tl);
2314                 else emit_loadreg(rs1[i],tl); // CHECK: regmap_entry?
2315               }
2316               else
2317               if(rs2[i]){
2318                 if(s2l>=0) emit_mov(s2l,tl);
2319                 else emit_loadreg(rs2[i],tl); // CHECK: regmap_entry?
2320               }
2321               else emit_zeroreg(tl);
2322             } else
2323             if(opcode2[i]==0x27) { // NOR
2324               if(rs1[i]){
2325                 if(s1l>=0) emit_not(s1l,tl);
2326                 else {
2327                   emit_loadreg(rs1[i],tl);
2328                   emit_not(tl,tl);
2329                 }
2330               }
2331               else
2332               if(rs2[i]){
2333                 if(s2l>=0) emit_not(s2l,tl);
2334                 else {
2335                   emit_loadreg(rs2[i],tl);
2336                   emit_not(tl,tl);
2337                 }
2338               }
2339               else emit_movimm(-1,tl);
2340             }
2341           }
2342         }
2343       }
2344     }
2345   }
2346 }
2347
2348 void imm16_assemble(int i,struct regstat *i_regs)
2349 {
2350   if (opcode[i]==0x0f) { // LUI
2351     if(rt1[i]) {
2352       signed char t;
2353       t=get_reg(i_regs->regmap,rt1[i]);
2354       //assert(t>=0);
2355       if(t>=0) {
2356         if(!((i_regs->isconst>>t)&1))
2357           emit_movimm(imm[i]<<16,t);
2358       }
2359     }
2360   }
2361   if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU
2362     if(rt1[i]) {
2363       signed char s,t;
2364       t=get_reg(i_regs->regmap,rt1[i]);
2365       s=get_reg(i_regs->regmap,rs1[i]);
2366       if(rs1[i]) {
2367         //assert(t>=0);
2368         //assert(s>=0);
2369         if(t>=0) {
2370           if(!((i_regs->isconst>>t)&1)) {
2371             if(s<0) {
2372               if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2373               emit_addimm(t,imm[i],t);
2374             }else{
2375               if(!((i_regs->wasconst>>s)&1))
2376                 emit_addimm(s,imm[i],t);
2377               else
2378                 emit_movimm(constmap[i][s]+imm[i],t);
2379             }
2380           }
2381         }
2382       } else {
2383         if(t>=0) {
2384           if(!((i_regs->isconst>>t)&1))
2385             emit_movimm(imm[i],t);
2386         }
2387       }
2388     }
2389   }
2390   if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU
2391     if(rt1[i]) {
2392       signed char sh,sl,th,tl;
2393       th=get_reg(i_regs->regmap,rt1[i]|64);
2394       tl=get_reg(i_regs->regmap,rt1[i]);
2395       sh=get_reg(i_regs->regmap,rs1[i]|64);
2396       sl=get_reg(i_regs->regmap,rs1[i]);
2397       if(tl>=0) {
2398         if(rs1[i]) {
2399           assert(sh>=0);
2400           assert(sl>=0);
2401           if(th>=0) {
2402             emit_addimm64_32(sh,sl,imm[i],th,tl);
2403           }
2404           else {
2405             emit_addimm(sl,imm[i],tl);
2406           }
2407         } else {
2408           emit_movimm(imm[i],tl);
2409           if(th>=0) emit_movimm(((signed int)imm[i])>>31,th);
2410         }
2411       }
2412     }
2413   }
2414   else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU
2415     if(rt1[i]) {
2416       //assert(rs1[i]!=0); // r0 might be valid, but it's probably a bug
2417       signed char sh,sl,t;
2418       t=get_reg(i_regs->regmap,rt1[i]);
2419       sh=get_reg(i_regs->regmap,rs1[i]|64);
2420       sl=get_reg(i_regs->regmap,rs1[i]);
2421       //assert(t>=0);
2422       if(t>=0) {
2423         if(rs1[i]>0) {
2424           if(sh<0) assert((i_regs->was32>>rs1[i])&1);
2425           if(sh<0||((i_regs->was32>>rs1[i])&1)) {
2426             if(opcode[i]==0x0a) { // SLTI
2427               if(sl<0) {
2428                 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2429                 emit_slti32(t,imm[i],t);
2430               }else{
2431                 emit_slti32(sl,imm[i],t);
2432               }
2433             }
2434             else { // SLTIU
2435               if(sl<0) {
2436                 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2437                 emit_sltiu32(t,imm[i],t);
2438               }else{
2439                 emit_sltiu32(sl,imm[i],t);
2440               }
2441             }
2442           }else{ // 64-bit
2443             assert(sl>=0);
2444             if(opcode[i]==0x0a) // SLTI
2445               emit_slti64_32(sh,sl,imm[i],t);
2446             else // SLTIU
2447               emit_sltiu64_32(sh,sl,imm[i],t);
2448           }
2449         }else{
2450           // SLTI(U) with r0 is just stupid,
2451           // nonetheless examples can be found
2452           if(opcode[i]==0x0a) // SLTI
2453             if(0<imm[i]) emit_movimm(1,t);
2454             else emit_zeroreg(t);
2455           else // SLTIU
2456           {
2457             if(imm[i]) emit_movimm(1,t);
2458             else emit_zeroreg(t);
2459           }
2460         }
2461       }
2462     }
2463   }
2464   else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI
2465     if(rt1[i]) {
2466       signed char sh,sl,th,tl;
2467       th=get_reg(i_regs->regmap,rt1[i]|64);
2468       tl=get_reg(i_regs->regmap,rt1[i]);
2469       sh=get_reg(i_regs->regmap,rs1[i]|64);
2470       sl=get_reg(i_regs->regmap,rs1[i]);
2471       if(tl>=0 && !((i_regs->isconst>>tl)&1)) {
2472         if(opcode[i]==0x0c) //ANDI
2473         {
2474           if(rs1[i]) {
2475             if(sl<0) {
2476               if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl);
2477               emit_andimm(tl,imm[i],tl);
2478             }else{
2479               if(!((i_regs->wasconst>>sl)&1))
2480                 emit_andimm(sl,imm[i],tl);
2481               else
2482                 emit_movimm(constmap[i][sl]&imm[i],tl);
2483             }
2484           }
2485           else
2486             emit_zeroreg(tl);
2487           if(th>=0) emit_zeroreg(th);
2488         }
2489         else
2490         {
2491           if(rs1[i]) {
2492             if(sl<0) {
2493               if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl);
2494             }
2495             if(th>=0) {
2496               if(sh<0) {
2497                 emit_loadreg(rs1[i]|64,th);
2498               }else{
2499                 emit_mov(sh,th);
2500               }
2501             }
2502             if(opcode[i]==0x0d) //ORI
2503             if(sl<0) {
2504               emit_orimm(tl,imm[i],tl);
2505             }else{
2506               if(!((i_regs->wasconst>>sl)&1))
2507                 emit_orimm(sl,imm[i],tl);
2508               else
2509                 emit_movimm(constmap[i][sl]|imm[i],tl);
2510             }
2511             if(opcode[i]==0x0e) //XORI
2512             if(sl<0) {
2513               emit_xorimm(tl,imm[i],tl);
2514             }else{
2515               if(!((i_regs->wasconst>>sl)&1))
2516                 emit_xorimm(sl,imm[i],tl);
2517               else
2518                 emit_movimm(constmap[i][sl]^imm[i],tl);
2519             }
2520           }
2521           else {
2522             emit_movimm(imm[i],tl);
2523             if(th>=0) emit_zeroreg(th);
2524           }
2525         }
2526       }
2527     }
2528   }
2529 }
2530
2531 void shiftimm_assemble(int i,struct regstat *i_regs)
2532 {
2533   if(opcode2[i]<=0x3) // SLL/SRL/SRA
2534   {
2535     if(rt1[i]) {
2536       signed char s,t;
2537       t=get_reg(i_regs->regmap,rt1[i]);
2538       s=get_reg(i_regs->regmap,rs1[i]);
2539       //assert(t>=0);
2540       if(t>=0){
2541         if(rs1[i]==0)
2542         {
2543           emit_zeroreg(t);
2544         }
2545         else
2546         {
2547           if(s<0&&i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2548           if(imm[i]) {
2549             if(opcode2[i]==0) // SLL
2550             {
2551               emit_shlimm(s<0?t:s,imm[i],t);
2552             }
2553             if(opcode2[i]==2) // SRL
2554             {
2555               emit_shrimm(s<0?t:s,imm[i],t);
2556             }
2557             if(opcode2[i]==3) // SRA
2558             {
2559               emit_sarimm(s<0?t:s,imm[i],t);
2560             }
2561           }else{
2562             // Shift by zero
2563             if(s>=0 && s!=t) emit_mov(s,t);
2564           }
2565         }
2566       }
2567       //emit_storereg(rt1[i],t); //DEBUG
2568     }
2569   }
2570   if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA
2571   {
2572     if(rt1[i]) {
2573       signed char sh,sl,th,tl;
2574       th=get_reg(i_regs->regmap,rt1[i]|64);
2575       tl=get_reg(i_regs->regmap,rt1[i]);
2576       sh=get_reg(i_regs->regmap,rs1[i]|64);
2577       sl=get_reg(i_regs->regmap,rs1[i]);
2578       if(tl>=0) {
2579         if(rs1[i]==0)
2580         {
2581           emit_zeroreg(tl);
2582           if(th>=0) emit_zeroreg(th);
2583         }
2584         else
2585         {
2586           assert(sl>=0);
2587           assert(sh>=0);
2588           if(imm[i]) {
2589             if(opcode2[i]==0x38) // DSLL
2590             {
2591               if(th>=0) emit_shldimm(sh,sl,imm[i],th);
2592               emit_shlimm(sl,imm[i],tl);
2593             }
2594             if(opcode2[i]==0x3a) // DSRL
2595             {
2596               emit_shrdimm(sl,sh,imm[i],tl);
2597               if(th>=0) emit_shrimm(sh,imm[i],th);
2598             }
2599             if(opcode2[i]==0x3b) // DSRA
2600             {
2601               emit_shrdimm(sl,sh,imm[i],tl);
2602               if(th>=0) emit_sarimm(sh,imm[i],th);
2603             }
2604           }else{
2605             // Shift by zero
2606             if(sl!=tl) emit_mov(sl,tl);
2607             if(th>=0&&sh!=th) emit_mov(sh,th);
2608           }
2609         }
2610       }
2611     }
2612   }
2613   if(opcode2[i]==0x3c) // DSLL32
2614   {
2615     if(rt1[i]) {
2616       signed char sl,tl,th;
2617       tl=get_reg(i_regs->regmap,rt1[i]);
2618       th=get_reg(i_regs->regmap,rt1[i]|64);
2619       sl=get_reg(i_regs->regmap,rs1[i]);
2620       if(th>=0||tl>=0){
2621         assert(tl>=0);
2622         assert(th>=0);
2623         assert(sl>=0);
2624         emit_mov(sl,th);
2625         emit_zeroreg(tl);
2626         if(imm[i]>32)
2627         {
2628           emit_shlimm(th,imm[i]&31,th);
2629         }
2630       }
2631     }
2632   }
2633   if(opcode2[i]==0x3e) // DSRL32
2634   {
2635     if(rt1[i]) {
2636       signed char sh,tl,th;
2637       tl=get_reg(i_regs->regmap,rt1[i]);
2638       th=get_reg(i_regs->regmap,rt1[i]|64);
2639       sh=get_reg(i_regs->regmap,rs1[i]|64);
2640       if(tl>=0){
2641         assert(sh>=0);
2642         emit_mov(sh,tl);
2643         if(th>=0) emit_zeroreg(th);
2644         if(imm[i]>32)
2645         {
2646           emit_shrimm(tl,imm[i]&31,tl);
2647         }
2648       }
2649     }
2650   }
2651   if(opcode2[i]==0x3f) // DSRA32
2652   {
2653     if(rt1[i]) {
2654       signed char sh,tl;
2655       tl=get_reg(i_regs->regmap,rt1[i]);
2656       sh=get_reg(i_regs->regmap,rs1[i]|64);
2657       if(tl>=0){
2658         assert(sh>=0);
2659         emit_mov(sh,tl);
2660         if(imm[i]>32)
2661         {
2662           emit_sarimm(tl,imm[i]&31,tl);
2663         }
2664       }
2665     }
2666   }
2667 }
2668
2669 #ifndef shift_assemble
2670 void shift_assemble(int i,struct regstat *i_regs)
2671 {
2672   printf("Need shift_assemble for this architecture.\n");
2673   exit(1);
2674 }
2675 #endif
2676
2677 void load_assemble(int i,struct regstat *i_regs)
2678 {
2679   int s,th,tl,addr,map=-1;
2680   int offset;
2681   int jaddr=0;
2682   int memtarget,c=0;
2683   u_int hr,reglist=0;
2684   th=get_reg(i_regs->regmap,rt1[i]|64);
2685   tl=get_reg(i_regs->regmap,rt1[i]);
2686   s=get_reg(i_regs->regmap,rs1[i]);
2687   offset=imm[i];
2688   for(hr=0;hr<HOST_REGS;hr++) {
2689     if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
2690   }
2691   if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
2692   if(s>=0) {
2693     c=(i_regs->wasconst>>s)&1;
2694     memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80800000;
2695     if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
2696   }
2697   if(offset||s<0||c) addr=tl;
2698   else addr=s;
2699   //printf("load_assemble: c=%d\n",c);
2700   //if(c) printf("load_assemble: const=%x\n",(int)constmap[i][s]+offset);
2701   // FIXME: Even if the load is a NOP, we should check for pagefaults...
2702   if(tl>=0) {
2703     //assert(tl>=0);
2704     //assert(rt1[i]);
2705     reglist&=~(1<<tl);
2706     if(th>=0) reglist&=~(1<<th);
2707     if(!using_tlb) {
2708       if(!c) {
2709 //#define R29_HACK 1
2710         #ifdef R29_HACK
2711         // Strmnnrmn's speed hack
2712         if(rs1[i]!=29||start<0x80001000||start>=0x80800000)
2713         #endif
2714         {
2715           emit_cmpimm(addr,0x800000);
2716           jaddr=(int)out;
2717           #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
2718           // Hint to branch predictor that the branch is unlikely to be taken
2719           if(rs1[i]>=28)
2720             emit_jno_unlikely(0);
2721           else
2722           #endif
2723           emit_jno(0);
2724         }
2725       }
2726     }else{ // using tlb
2727       int x=0;
2728       if (opcode[i]==0x20||opcode[i]==0x24) x=3; // LB/LBU
2729       if (opcode[i]==0x21||opcode[i]==0x25) x=2; // LH/LHU
2730       map=get_reg(i_regs->regmap,TLREG);
2731       assert(map>=0);
2732       map=do_tlb_r(addr,tl,map,x,-1,-1,c,constmap[i][s]+offset);
2733       do_tlb_r_branch(map,c,constmap[i][s]+offset,&jaddr);
2734     }
2735     if (opcode[i]==0x20) { // LB
2736       if(!c||memtarget) {
2737         #ifdef HOST_IMM_ADDR32
2738         if(c)
2739           emit_movsbl_tlb((constmap[i][s]+offset)^3,map,tl);
2740         else
2741         #endif
2742         {
2743           //emit_xorimm(addr,3,tl);
2744           //gen_tlb_addr_r(tl,map);
2745           //emit_movsbl_indexed((int)rdram-0x80000000,tl,tl);
2746           int x=0;
2747           if(!c) emit_xorimm(addr,3,tl);
2748           else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2749           emit_movsbl_indexed_tlb(x,tl,map,tl);
2750         }
2751         if(jaddr)
2752           add_stub(LOADB_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2753       }
2754       else
2755         inline_readstub(LOADB_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2756     }
2757     if (opcode[i]==0x21) { // LH
2758       if(!c||memtarget) {
2759         #ifdef HOST_IMM_ADDR32
2760         if(c)
2761           emit_movswl_tlb((constmap[i][s]+offset)^2,map,tl);
2762         else
2763         #endif
2764         {
2765           int x=0;
2766           if(!c) emit_xorimm(addr,2,tl);
2767           else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
2768           //#ifdef
2769           //emit_movswl_indexed_tlb(x,tl,map,tl);
2770           //else
2771           if(map>=0) {
2772             gen_tlb_addr_r(tl,map);
2773             emit_movswl_indexed(x,tl,tl);
2774           }else
2775             emit_movswl_indexed((int)rdram-0x80000000+x,tl,tl);
2776         }
2777         if(jaddr)
2778           add_stub(LOADH_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2779       }
2780       else
2781         inline_readstub(LOADH_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2782     }
2783     if (opcode[i]==0x23) { // LW
2784       if(!c||memtarget) {
2785         //emit_readword_indexed((int)rdram-0x80000000,addr,tl);
2786         #ifdef HOST_IMM_ADDR32
2787         if(c)
2788           emit_readword_tlb(constmap[i][s]+offset,map,tl);
2789         else
2790         #endif
2791         emit_readword_indexed_tlb(0,addr,map,tl);
2792         if(jaddr)
2793           add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2794       }
2795       else
2796         inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2797     }
2798     if (opcode[i]==0x24) { // LBU
2799       if(!c||memtarget) {
2800         #ifdef HOST_IMM_ADDR32
2801         if(c)
2802           emit_movzbl_tlb((constmap[i][s]+offset)^3,map,tl);
2803         else
2804         #endif
2805         {
2806           //emit_xorimm(addr,3,tl);
2807           //gen_tlb_addr_r(tl,map);
2808           //emit_movzbl_indexed((int)rdram-0x80000000,tl,tl);
2809           int x=0;
2810           if(!c) emit_xorimm(addr,3,tl);
2811           else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2812           emit_movzbl_indexed_tlb(x,tl,map,tl);
2813         }
2814         if(jaddr)
2815           add_stub(LOADBU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2816       }
2817       else
2818         inline_readstub(LOADBU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2819     }
2820     if (opcode[i]==0x25) { // LHU
2821       if(!c||memtarget) {
2822         #ifdef HOST_IMM_ADDR32
2823         if(c)
2824           emit_movzwl_tlb((constmap[i][s]+offset)^2,map,tl);
2825         else
2826         #endif
2827         {
2828           int x=0;
2829           if(!c) emit_xorimm(addr,2,tl);
2830           else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
2831           //#ifdef
2832           //emit_movzwl_indexed_tlb(x,tl,map,tl);
2833           //#else
2834           if(map>=0) {
2835             gen_tlb_addr_r(tl,map);
2836             emit_movzwl_indexed(x,tl,tl);
2837           }else
2838             emit_movzwl_indexed((int)rdram-0x80000000+x,tl,tl);
2839           if(jaddr)
2840             add_stub(LOADHU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2841         }
2842       }
2843       else
2844         inline_readstub(LOADHU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2845     }
2846     if (opcode[i]==0x27) { // LWU
2847       assert(th>=0);
2848       if(!c||memtarget) {
2849         //emit_readword_indexed((int)rdram-0x80000000,addr,tl);
2850         #ifdef HOST_IMM_ADDR32
2851         if(c)
2852           emit_readword_tlb(constmap[i][s]+offset,map,tl);
2853         else
2854         #endif
2855         emit_readword_indexed_tlb(0,addr,map,tl);
2856         if(jaddr)
2857           add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2858       }
2859       else {
2860         inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2861       }
2862       emit_zeroreg(th);
2863     }
2864     if (opcode[i]==0x37) { // LD
2865       if(!c||memtarget) {
2866         //gen_tlb_addr_r(tl,map);
2867         //if(th>=0) emit_readword_indexed((int)rdram-0x80000000,addr,th);
2868         //emit_readword_indexed((int)rdram-0x7FFFFFFC,addr,tl);
2869         #ifdef HOST_IMM_ADDR32
2870         if(c)
2871           emit_readdword_tlb(constmap[i][s]+offset,map,th,tl);
2872         else
2873         #endif
2874         emit_readdword_indexed_tlb(0,addr,map,th,tl);
2875         if(jaddr)
2876           add_stub(LOADD_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2877       }
2878       else
2879         inline_readstub(LOADD_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2880     }
2881     //emit_storereg(rt1[i],tl); // DEBUG
2882   }
2883   //if(opcode[i]==0x23)
2884   //if(opcode[i]==0x24)
2885   //if(opcode[i]==0x23||opcode[i]==0x24)
2886   /*if(opcode[i]==0x21||opcode[i]==0x23||opcode[i]==0x24)
2887   {
2888     //emit_pusha();
2889     save_regs(0x100f);
2890         emit_readword((int)&last_count,ECX);
2891         #ifdef __i386__
2892         if(get_reg(i_regs->regmap,CCREG)<0)
2893           emit_loadreg(CCREG,HOST_CCREG);
2894         emit_add(HOST_CCREG,ECX,HOST_CCREG);
2895         emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
2896         emit_writeword(HOST_CCREG,(int)&Count);
2897         #endif
2898         #ifdef __arm__
2899         if(get_reg(i_regs->regmap,CCREG)<0)
2900           emit_loadreg(CCREG,0);
2901         else
2902           emit_mov(HOST_CCREG,0);
2903         emit_add(0,ECX,0);
2904         emit_addimm(0,2*ccadj[i],0);
2905         emit_writeword(0,(int)&Count);
2906         #endif
2907     emit_call((int)memdebug);
2908     //emit_popa();
2909     restore_regs(0x100f);
2910   }/**/
2911 }
2912
2913 #ifndef loadlr_assemble
2914 void loadlr_assemble(int i,struct regstat *i_regs)
2915 {
2916   printf("Need loadlr_assemble for this architecture.\n");
2917   exit(1);
2918 }
2919 #endif
2920
2921 void store_assemble(int i,struct regstat *i_regs)
2922 {
2923   int s,th,tl,map=-1;
2924   int addr,temp;
2925   int offset;
2926   int jaddr=0,jaddr2,type;
2927   int memtarget,c=0;
2928   int agr=AGEN1+(i&1);
2929   u_int hr,reglist=0;
2930   th=get_reg(i_regs->regmap,rs2[i]|64);
2931   tl=get_reg(i_regs->regmap,rs2[i]);
2932   s=get_reg(i_regs->regmap,rs1[i]);
2933   temp=get_reg(i_regs->regmap,agr);
2934   if(temp<0) temp=get_reg(i_regs->regmap,-1);
2935   offset=imm[i];
2936   if(s>=0) {
2937     c=(i_regs->wasconst>>s)&1;
2938     memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80800000;
2939     if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
2940   }
2941   assert(tl>=0);
2942   assert(temp>=0);
2943   for(hr=0;hr<HOST_REGS;hr++) {
2944     if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
2945   }
2946   if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
2947   if(offset||s<0||c) addr=temp;
2948   else addr=s;
2949   if(!using_tlb) {
2950     if(!c) {
2951       #ifdef R29_HACK
2952       // Strmnnrmn's speed hack
2953       memtarget=1;
2954       if(rs1[i]!=29||start<0x80001000||start>=0x80800000)
2955       #endif
2956       emit_cmpimm(addr,0x800000);
2957       #ifdef DESTRUCTIVE_SHIFT
2958       if(s==addr) emit_mov(s,temp);
2959       #endif
2960       #ifdef R29_HACK
2961       if(rs1[i]!=29||start<0x80001000||start>=0x80800000)
2962       #endif
2963       {
2964         jaddr=(int)out;
2965         #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
2966         // Hint to branch predictor that the branch is unlikely to be taken
2967         if(rs1[i]>=28)
2968           emit_jno_unlikely(0);
2969         else
2970         #endif
2971         emit_jno(0);
2972       }
2973     }
2974   }else{ // using tlb
2975     int x=0;
2976     if (opcode[i]==0x28) x=3; // SB
2977     if (opcode[i]==0x29) x=2; // SH
2978     map=get_reg(i_regs->regmap,TLREG);
2979     assert(map>=0);
2980     map=do_tlb_w(addr,temp,map,x,c,constmap[i][s]+offset);
2981     do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr);
2982   }
2983
2984   if (opcode[i]==0x28) { // SB
2985     if(!c||memtarget) {
2986       int x=0;
2987       if(!c) emit_xorimm(addr,3,temp);
2988       else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2989       //gen_tlb_addr_w(temp,map);
2990       //emit_writebyte_indexed(tl,(int)rdram-0x80000000,temp);
2991       emit_writebyte_indexed_tlb(tl,x,temp,map,temp);
2992     }
2993     type=STOREB_STUB;
2994   }
2995   if (opcode[i]==0x29) { // SH
2996     if(!c||memtarget) {
2997       int x=0;
2998       if(!c) emit_xorimm(addr,2,temp);
2999       else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
3000       //#ifdef
3001       //emit_writehword_indexed_tlb(tl,x,temp,map,temp);
3002       //#else
3003       if(map>=0) {
3004         gen_tlb_addr_w(temp,map);
3005         emit_writehword_indexed(tl,x,temp);
3006       }else
3007         emit_writehword_indexed(tl,(int)rdram-0x80000000+x,temp);
3008     }
3009     type=STOREH_STUB;
3010   }
3011   if (opcode[i]==0x2B) { // SW
3012     if(!c||memtarget)
3013       //emit_writeword_indexed(tl,(int)rdram-0x80000000,addr);
3014       emit_writeword_indexed_tlb(tl,0,addr,map,temp);
3015     type=STOREW_STUB;
3016   }
3017   if (opcode[i]==0x3F) { // SD
3018     if(!c||memtarget) {
3019       if(rs2[i]) {
3020         assert(th>=0);
3021         //emit_writeword_indexed(th,(int)rdram-0x80000000,addr);
3022         //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,addr);
3023         emit_writedword_indexed_tlb(th,tl,0,addr,map,temp);
3024       }else{
3025         // Store zero
3026         //emit_writeword_indexed(tl,(int)rdram-0x80000000,temp);
3027         //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,temp);
3028         emit_writedword_indexed_tlb(tl,tl,0,addr,map,temp);
3029       }
3030     }
3031     type=STORED_STUB;
3032   }
3033   if(jaddr) {
3034     add_stub(type,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3035   } else if(!memtarget) {
3036     inline_writestub(type,i,constmap[i][s]+offset,i_regs->regmap,rs2[i],ccadj[i],reglist);
3037   }
3038   if(!using_tlb) {
3039     if(!c||memtarget) {
3040       #ifdef DESTRUCTIVE_SHIFT
3041       // The x86 shift operation is 'destructive'; it overwrites the
3042       // source register, so we need to make a copy first and use that.
3043       addr=temp;
3044       #endif
3045       #if defined(HOST_IMM8)
3046       int ir=get_reg(i_regs->regmap,INVCP);
3047       assert(ir>=0);
3048       emit_cmpmem_indexedsr12_reg(ir,addr,1);
3049       #else
3050       emit_cmpmem_indexedsr12_imm((int)invalid_code,addr,1);
3051       #endif
3052       jaddr2=(int)out;
3053       emit_jne(0);
3054       add_stub(INVCODE_STUB,jaddr2,(int)out,reglist|(1<<HOST_CCREG),addr,0,0,0);
3055     }
3056   }
3057   //if(opcode[i]==0x2B || opcode[i]==0x3F)
3058   //if(opcode[i]==0x2B || opcode[i]==0x28)
3059   //if(opcode[i]==0x2B || opcode[i]==0x29)
3060   //if(opcode[i]==0x2B)
3061   /*if(opcode[i]==0x2B || opcode[i]==0x28 || opcode[i]==0x29 || opcode[i]==0x3F)
3062   {
3063     //emit_pusha();
3064     save_regs(0x100f);
3065         emit_readword((int)&last_count,ECX);
3066         #ifdef __i386__
3067         if(get_reg(i_regs->regmap,CCREG)<0)
3068           emit_loadreg(CCREG,HOST_CCREG);
3069         emit_add(HOST_CCREG,ECX,HOST_CCREG);
3070         emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3071         emit_writeword(HOST_CCREG,(int)&Count);
3072         #endif
3073         #ifdef __arm__
3074         if(get_reg(i_regs->regmap,CCREG)<0)
3075           emit_loadreg(CCREG,0);
3076         else
3077           emit_mov(HOST_CCREG,0);
3078         emit_add(0,ECX,0);
3079         emit_addimm(0,2*ccadj[i],0);
3080         emit_writeword(0,(int)&Count);
3081         #endif
3082     emit_call((int)memdebug);
3083     //emit_popa();
3084     restore_regs(0x100f);
3085   }/**/
3086 }
3087
3088 void storelr_assemble(int i,struct regstat *i_regs)
3089 {
3090   int s,th,tl;
3091   int temp;
3092   int temp2;
3093   int offset;
3094   int jaddr=0,jaddr2;
3095   int case1,case2,case3;
3096   int done0,done1,done2;
3097   int memtarget,c=0;
3098   u_int hr,reglist=0;
3099   th=get_reg(i_regs->regmap,rs2[i]|64);
3100   tl=get_reg(i_regs->regmap,rs2[i]);
3101   s=get_reg(i_regs->regmap,rs1[i]);
3102   temp=get_reg(i_regs->regmap,-1);
3103   offset=imm[i];
3104   if(s>=0) {
3105     c=(i_regs->isconst>>s)&1;
3106     memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80800000;
3107     if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
3108   }
3109   assert(tl>=0);
3110   for(hr=0;hr<HOST_REGS;hr++) {
3111     if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3112   }
3113   if(tl>=0) {
3114     assert(temp>=0);
3115     if(!using_tlb) {
3116       if(!c) {
3117         emit_cmpimm(s<0||offset?temp:s,0x800000);
3118         if(!offset&&s!=temp) emit_mov(s,temp);
3119         jaddr=(int)out;
3120         emit_jno(0);
3121       }
3122       else
3123       {
3124         if(!memtarget||!rs1[i]) {
3125           jaddr=(int)out;
3126           emit_jmp(0);
3127         }
3128       }
3129       if((u_int)rdram!=0x80000000) 
3130         emit_addimm_no_flags((u_int)rdram-(u_int)0x80000000,temp);
3131     }else{ // using tlb
3132       int map=get_reg(i_regs->regmap,TLREG);
3133       assert(map>=0);
3134       map=do_tlb_w(c||s<0||offset?temp:s,temp,map,0,c,constmap[i][s]+offset);
3135       if(!c&&!offset&&s>=0) emit_mov(s,temp);
3136       do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr);
3137       if(!jaddr&&!memtarget) {
3138         jaddr=(int)out;
3139         emit_jmp(0);
3140       }
3141       gen_tlb_addr_w(temp,map);
3142     }
3143
3144     if (opcode[i]==0x2C||opcode[i]==0x2D) { // SDL/SDR
3145       temp2=get_reg(i_regs->regmap,FTEMP);
3146       if(!rs2[i]) temp2=th=tl;
3147     }
3148
3149     emit_testimm(temp,2);
3150     case2=(int)out;
3151     emit_jne(0);
3152     emit_testimm(temp,1);
3153     case1=(int)out;
3154     emit_jne(0);
3155     // 0
3156     if (opcode[i]==0x2A) { // SWL
3157       emit_writeword_indexed(tl,0,temp);
3158     }
3159     if (opcode[i]==0x2E) { // SWR
3160       emit_writebyte_indexed(tl,3,temp);
3161     }
3162     if (opcode[i]==0x2C) { // SDL
3163       emit_writeword_indexed(th,0,temp);
3164       if(rs2[i]) emit_mov(tl,temp2);
3165     }
3166     if (opcode[i]==0x2D) { // SDR
3167       emit_writebyte_indexed(tl,3,temp);
3168       if(rs2[i]) emit_shldimm(th,tl,24,temp2);
3169     }
3170     done0=(int)out;
3171     emit_jmp(0);
3172     // 1
3173     set_jump_target(case1,(int)out);
3174     if (opcode[i]==0x2A) { // SWL
3175       // Write 3 msb into three least significant bytes
3176       if(rs2[i]) emit_rorimm(tl,8,tl);
3177       emit_writehword_indexed(tl,-1,temp);
3178       if(rs2[i]) emit_rorimm(tl,16,tl);
3179       emit_writebyte_indexed(tl,1,temp);
3180       if(rs2[i]) emit_rorimm(tl,8,tl);
3181     }
3182     if (opcode[i]==0x2E) { // SWR
3183       // Write two lsb into two most significant bytes
3184       emit_writehword_indexed(tl,1,temp);
3185     }
3186     if (opcode[i]==0x2C) { // SDL
3187       if(rs2[i]) emit_shrdimm(tl,th,8,temp2);
3188       // Write 3 msb into three least significant bytes
3189       if(rs2[i]) emit_rorimm(th,8,th);
3190       emit_writehword_indexed(th,-1,temp);
3191       if(rs2[i]) emit_rorimm(th,16,th);
3192       emit_writebyte_indexed(th,1,temp);
3193       if(rs2[i]) emit_rorimm(th,8,th);
3194     }
3195     if (opcode[i]==0x2D) { // SDR
3196       if(rs2[i]) emit_shldimm(th,tl,16,temp2);
3197       // Write two lsb into two most significant bytes
3198       emit_writehword_indexed(tl,1,temp);
3199     }
3200     done1=(int)out;
3201     emit_jmp(0);
3202     // 2
3203     set_jump_target(case2,(int)out);
3204     emit_testimm(temp,1);
3205     case3=(int)out;
3206     emit_jne(0);
3207     if (opcode[i]==0x2A) { // SWL
3208       // Write two msb into two least significant bytes
3209       if(rs2[i]) emit_rorimm(tl,16,tl);
3210       emit_writehword_indexed(tl,-2,temp);
3211       if(rs2[i]) emit_rorimm(tl,16,tl);
3212     }
3213     if (opcode[i]==0x2E) { // SWR
3214       // Write 3 lsb into three most significant bytes
3215       emit_writebyte_indexed(tl,-1,temp);
3216       if(rs2[i]) emit_rorimm(tl,8,tl);
3217       emit_writehword_indexed(tl,0,temp);
3218       if(rs2[i]) emit_rorimm(tl,24,tl);
3219     }
3220     if (opcode[i]==0x2C) { // SDL
3221       if(rs2[i]) emit_shrdimm(tl,th,16,temp2);
3222       // Write two msb into two least significant bytes
3223       if(rs2[i]) emit_rorimm(th,16,th);
3224       emit_writehword_indexed(th,-2,temp);
3225       if(rs2[i]) emit_rorimm(th,16,th);
3226     }
3227     if (opcode[i]==0x2D) { // SDR
3228       if(rs2[i]) emit_shldimm(th,tl,8,temp2);
3229       // Write 3 lsb into three most significant bytes
3230       emit_writebyte_indexed(tl,-1,temp);
3231       if(rs2[i]) emit_rorimm(tl,8,tl);
3232       emit_writehword_indexed(tl,0,temp);
3233       if(rs2[i]) emit_rorimm(tl,24,tl);
3234     }
3235     done2=(int)out;
3236     emit_jmp(0);
3237     // 3
3238     set_jump_target(case3,(int)out);
3239     if (opcode[i]==0x2A) { // SWL
3240       // Write msb into least significant byte
3241       if(rs2[i]) emit_rorimm(tl,24,tl);
3242       emit_writebyte_indexed(tl,-3,temp);
3243       if(rs2[i]) emit_rorimm(tl,8,tl);
3244     }
3245     if (opcode[i]==0x2E) { // SWR
3246       // Write entire word
3247       emit_writeword_indexed(tl,-3,temp);
3248     }
3249     if (opcode[i]==0x2C) { // SDL
3250       if(rs2[i]) emit_shrdimm(tl,th,24,temp2);
3251       // Write msb into least significant byte
3252       if(rs2[i]) emit_rorimm(th,24,th);
3253       emit_writebyte_indexed(th,-3,temp);
3254       if(rs2[i]) emit_rorimm(th,8,th);
3255     }
3256     if (opcode[i]==0x2D) { // SDR
3257       if(rs2[i]) emit_mov(th,temp2);
3258       // Write entire word
3259       emit_writeword_indexed(tl,-3,temp);
3260     }
3261     set_jump_target(done0,(int)out);
3262     set_jump_target(done1,(int)out);
3263     set_jump_target(done2,(int)out);
3264     if (opcode[i]==0x2C) { // SDL
3265       emit_testimm(temp,4);
3266       done0=(int)out;
3267       emit_jne(0);
3268       emit_andimm(temp,~3,temp);
3269       emit_writeword_indexed(temp2,4,temp);
3270       set_jump_target(done0,(int)out);
3271     }
3272     if (opcode[i]==0x2D) { // SDR
3273       emit_testimm(temp,4);
3274       done0=(int)out;
3275       emit_jeq(0);
3276       emit_andimm(temp,~3,temp);
3277       emit_writeword_indexed(temp2,-4,temp);
3278       set_jump_target(done0,(int)out);
3279     }
3280     if(!c||!memtarget)
3281       add_stub(STORELR_STUB,jaddr,(int)out,0,(int)i_regs,rs2[i],ccadj[i],reglist);
3282   }
3283   if(!using_tlb) {
3284     emit_addimm_no_flags((u_int)0x80000000-(u_int)rdram,temp);
3285     #if defined(HOST_IMM8)
3286     int ir=get_reg(i_regs->regmap,INVCP);
3287     assert(ir>=0);
3288     emit_cmpmem_indexedsr12_reg(ir,temp,1);
3289     #else
3290     emit_cmpmem_indexedsr12_imm((int)invalid_code,temp,1);
3291     #endif
3292     jaddr2=(int)out;
3293     emit_jne(0);
3294     add_stub(INVCODE_STUB,jaddr2,(int)out,reglist|(1<<HOST_CCREG),temp,0,0,0);
3295   }
3296   /*
3297     emit_pusha();
3298     //save_regs(0x100f);
3299         emit_readword((int)&last_count,ECX);
3300         if(get_reg(i_regs->regmap,CCREG)<0)
3301           emit_loadreg(CCREG,HOST_CCREG);
3302         emit_add(HOST_CCREG,ECX,HOST_CCREG);
3303         emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3304         emit_writeword(HOST_CCREG,(int)&Count);
3305     emit_call((int)memdebug);
3306     emit_popa();
3307     //restore_regs(0x100f);
3308   /**/
3309 }
3310
3311 void c1ls_assemble(int i,struct regstat *i_regs)
3312 {
3313 #ifndef DISABLE_COP1
3314   int s,th,tl;
3315   int temp,ar;
3316   int map=-1;
3317   int offset;
3318   int c=0;
3319   int jaddr,jaddr2=0,jaddr3,type;
3320   int agr=AGEN1+(i&1);
3321   u_int hr,reglist=0;
3322   th=get_reg(i_regs->regmap,FTEMP|64);
3323   tl=get_reg(i_regs->regmap,FTEMP);
3324   s=get_reg(i_regs->regmap,rs1[i]);
3325   temp=get_reg(i_regs->regmap,agr);
3326   if(temp<0) temp=get_reg(i_regs->regmap,-1);
3327   offset=imm[i];
3328   assert(tl>=0);
3329   assert(rs1[i]>0);
3330   assert(temp>=0);
3331   for(hr=0;hr<HOST_REGS;hr++) {
3332     if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3333   }
3334   if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
3335   if (opcode[i]==0x31||opcode[i]==0x35) // LWC1/LDC1
3336   {
3337     // Loads use a temporary register which we need to save
3338     reglist|=1<<temp;
3339   }
3340   if (opcode[i]==0x39||opcode[i]==0x3D) // SWC1/SDC1
3341     ar=temp;
3342   else // LWC1/LDC1
3343     ar=tl;
3344   //if(s<0) emit_loadreg(rs1[i],ar); //address_generation does this now
3345   //else c=(i_regs->wasconst>>s)&1;
3346   if(s>=0) c=(i_regs->wasconst>>s)&1;
3347   // Check cop1 unusable
3348   if(!cop1_usable) {
3349     signed char rs=get_reg(i_regs->regmap,CSREG);
3350     assert(rs>=0);
3351     emit_testimm(rs,0x20000000);
3352     jaddr=(int)out;
3353     emit_jeq(0);
3354     add_stub(FP_STUB,jaddr,(int)out,i,rs,(int)i_regs,is_delayslot,0);
3355     cop1_usable=1;
3356   }
3357   if (opcode[i]==0x39) { // SWC1 (get float address)
3358     emit_readword((int)&reg_cop1_simple[(source[i]>>16)&0x1f],tl);
3359   }
3360   if (opcode[i]==0x3D) { // SDC1 (get double address)
3361     emit_readword((int)&reg_cop1_double[(source[i]>>16)&0x1f],tl);
3362   }
3363   // Generate address + offset
3364   if(!using_tlb) {
3365     if(!c)
3366       emit_cmpimm(offset||c||s<0?ar:s,0x800000);
3367   }
3368   else
3369   {
3370     map=get_reg(i_regs->regmap,TLREG);
3371     assert(map>=0);
3372     if (opcode[i]==0x31||opcode[i]==0x35) { // LWC1/LDC1
3373       map=do_tlb_r(offset||c||s<0?ar:s,ar,map,0,-1,-1,c,constmap[i][s]+offset);
3374     }
3375     if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3376       map=do_tlb_w(offset||c||s<0?ar:s,ar,map,0,c,constmap[i][s]+offset);
3377     }
3378   }
3379   if (opcode[i]==0x39) { // SWC1 (read float)
3380     emit_readword_indexed(0,tl,tl);
3381   }
3382   if (opcode[i]==0x3D) { // SDC1 (read double)
3383     emit_readword_indexed(4,tl,th);
3384     emit_readword_indexed(0,tl,tl);
3385   }
3386   if (opcode[i]==0x31) { // LWC1 (get target address)
3387     emit_readword((int)&reg_cop1_simple[(source[i]>>16)&0x1f],temp);
3388   }
3389   if (opcode[i]==0x35) { // LDC1 (get target address)
3390     emit_readword((int)&reg_cop1_double[(source[i]>>16)&0x1f],temp);
3391   }
3392   if(!using_tlb) {
3393     if(!c) {
3394       jaddr2=(int)out;
3395       emit_jno(0);
3396     }
3397     else if(((signed int)(constmap[i][s]+offset))>=(signed int)0x80800000) {
3398       jaddr2=(int)out;
3399       emit_jmp(0); // inline_readstub/inline_writestub?  Very rare case
3400     }
3401     #ifdef DESTRUCTIVE_SHIFT
3402     if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3403       if(!offset&&!c&&s>=0) emit_mov(s,ar);
3404     }
3405     #endif
3406   }else{
3407     if (opcode[i]==0x31||opcode[i]==0x35) { // LWC1/LDC1
3408       do_tlb_r_branch(map,c,constmap[i][s]+offset,&jaddr2);
3409     }
3410     if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3411       do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr2);
3412     }
3413   }
3414   if (opcode[i]==0x31) { // LWC1
3415     //if(s>=0&&!c&&!offset) emit_mov(s,tl);
3416     //gen_tlb_addr_r(ar,map);
3417     //emit_readword_indexed((int)rdram-0x80000000,tl,tl);
3418     #ifdef HOST_IMM_ADDR32
3419     if(c) emit_readword_tlb(constmap[i][s]+offset,map,tl);
3420     else
3421     #endif
3422     emit_readword_indexed_tlb(0,offset||c||s<0?tl:s,map,tl);
3423     type=LOADW_STUB;
3424   }
3425   if (opcode[i]==0x35) { // LDC1
3426     assert(th>=0);
3427     //if(s>=0&&!c&&!offset) emit_mov(s,tl);
3428     //gen_tlb_addr_r(ar,map);
3429     //emit_readword_indexed((int)rdram-0x80000000,tl,th);
3430     //emit_readword_indexed((int)rdram-0x7FFFFFFC,tl,tl);
3431     #ifdef HOST_IMM_ADDR32
3432     if(c) emit_readdword_tlb(constmap[i][s]+offset,map,th,tl);
3433     else
3434     #endif
3435     emit_readdword_indexed_tlb(0,offset||c||s<0?tl:s,map,th,tl);
3436     type=LOADD_STUB;
3437   }
3438   if (opcode[i]==0x39) { // SWC1
3439     //emit_writeword_indexed(tl,(int)rdram-0x80000000,temp);
3440     emit_writeword_indexed_tlb(tl,0,offset||c||s<0?temp:s,map,temp);
3441     type=STOREW_STUB;
3442   }
3443   if (opcode[i]==0x3D) { // SDC1
3444     assert(th>=0);
3445     //emit_writeword_indexed(th,(int)rdram-0x80000000,temp);
3446     //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,temp);
3447     emit_writedword_indexed_tlb(th,tl,0,offset||c||s<0?temp:s,map,temp);
3448     type=STORED_STUB;
3449   }
3450   if(!using_tlb) {
3451     if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3452       #ifndef DESTRUCTIVE_SHIFT
3453       temp=offset||c||s<0?ar:s;
3454       #endif
3455       #if defined(HOST_IMM8)
3456       int ir=get_reg(i_regs->regmap,INVCP);
3457       assert(ir>=0);
3458       emit_cmpmem_indexedsr12_reg(ir,temp,1);
3459       #else
3460       emit_cmpmem_indexedsr12_imm((int)invalid_code,temp,1);
3461       #endif
3462       jaddr3=(int)out;
3463       emit_jne(0);
3464       add_stub(INVCODE_STUB,jaddr3,(int)out,reglist|(1<<HOST_CCREG),temp,0,0,0);
3465     }
3466   }
3467   if(jaddr2) add_stub(type,jaddr2,(int)out,i,offset||c||s<0?ar:s,(int)i_regs,ccadj[i],reglist);
3468   if (opcode[i]==0x31) { // LWC1 (write float)
3469     emit_writeword_indexed(tl,0,temp);
3470   }
3471   if (opcode[i]==0x35) { // LDC1 (write double)
3472     emit_writeword_indexed(th,4,temp);
3473     emit_writeword_indexed(tl,0,temp);
3474   }
3475   //if(opcode[i]==0x39)
3476   /*if(opcode[i]==0x39||opcode[i]==0x31)
3477   {
3478     emit_pusha();
3479         emit_readword((int)&last_count,ECX);
3480         if(get_reg(i_regs->regmap,CCREG)<0)
3481           emit_loadreg(CCREG,HOST_CCREG);
3482         emit_add(HOST_CCREG,ECX,HOST_CCREG);
3483         emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3484         emit_writeword(HOST_CCREG,(int)&Count);
3485     emit_call((int)memdebug);
3486     emit_popa();
3487   }/**/
3488 #else
3489   cop1_unusable(i, i_regs);
3490 #endif
3491 }
3492
3493 #ifndef multdiv_assemble
3494 void multdiv_assemble(int i,struct regstat *i_regs)
3495 {
3496   printf("Need multdiv_assemble for this architecture.\n");
3497   exit(1);
3498 }
3499 #endif
3500
3501 void mov_assemble(int i,struct regstat *i_regs)
3502 {
3503   //if(opcode2[i]==0x10||opcode2[i]==0x12) { // MFHI/MFLO
3504   //if(opcode2[i]==0x11||opcode2[i]==0x13) { // MTHI/MTLO
3505   assert(rt1[i]>0);
3506   if(rt1[i]) {
3507     signed char sh,sl,th,tl;
3508     th=get_reg(i_regs->regmap,rt1[i]|64);
3509     tl=get_reg(i_regs->regmap,rt1[i]);
3510     //assert(tl>=0);
3511     if(tl>=0) {
3512       sh=get_reg(i_regs->regmap,rs1[i]|64);
3513       sl=get_reg(i_regs->regmap,rs1[i]);
3514       if(sl>=0) emit_mov(sl,tl);
3515       else emit_loadreg(rs1[i],tl);
3516       if(th>=0) {
3517         if(sh>=0) emit_mov(sh,th);
3518         else emit_loadreg(rs1[i]|64,th);
3519       }
3520     }
3521   }
3522 }
3523
3524 #ifndef fconv_assemble
3525 void fconv_assemble(int i,struct regstat *i_regs)
3526 {
3527   printf("Need fconv_assemble for this architecture.\n");
3528   exit(1);
3529 }
3530 #endif
3531
3532 #if 0
3533 void float_assemble(int i,struct regstat *i_regs)
3534 {
3535   printf("Need float_assemble for this architecture.\n");
3536   exit(1);
3537 }
3538 #endif
3539
3540 void syscall_assemble(int i,struct regstat *i_regs)
3541 {
3542   signed char ccreg=get_reg(i_regs->regmap,CCREG);
3543   assert(ccreg==HOST_CCREG);
3544   assert(!is_delayslot);
3545   emit_movimm(start+i*4,EAX); // Get PC
3546   emit_addimm(HOST_CCREG,CLOCK_DIVIDER*ccadj[i],HOST_CCREG); // CHECK: is this right?  There should probably be an extra cycle...
3547   emit_jmp((int)jump_syscall);
3548 }
3549
3550 void ds_assemble(int i,struct regstat *i_regs)
3551 {
3552   is_delayslot=1;
3553   switch(itype[i]) {
3554     case ALU:
3555       alu_assemble(i,i_regs);break;
3556     case IMM16:
3557       imm16_assemble(i,i_regs);break;
3558     case SHIFT:
3559       shift_assemble(i,i_regs);break;
3560     case SHIFTIMM:
3561       shiftimm_assemble(i,i_regs);break;
3562     case LOAD:
3563       load_assemble(i,i_regs);break;
3564     case LOADLR:
3565       loadlr_assemble(i,i_regs);break;
3566     case STORE:
3567       store_assemble(i,i_regs);break;
3568     case STORELR:
3569       storelr_assemble(i,i_regs);break;
3570     case COP0:
3571       cop0_assemble(i,i_regs);break;
3572     case COP1:
3573       cop1_assemble(i,i_regs);break;
3574     case C1LS:
3575       c1ls_assemble(i,i_regs);break;
3576     case FCONV:
3577       fconv_assemble(i,i_regs);break;
3578     case FLOAT:
3579       float_assemble(i,i_regs);break;
3580     case FCOMP:
3581       fcomp_assemble(i,i_regs);break;
3582     case MULTDIV:
3583       multdiv_assemble(i,i_regs);break;
3584     case MOV:
3585       mov_assemble(i,i_regs);break;
3586     case SYSCALL:
3587     case SPAN:
3588     case UJUMP:
3589     case RJUMP:
3590     case CJUMP:
3591     case SJUMP:
3592     case FJUMP:
3593       printf("Jump in the delay slot.  This is probably a bug.\n");
3594   }
3595   is_delayslot=0;
3596 }
3597
3598 // Is the branch target a valid internal jump?
3599 int internal_branch(uint64_t i_is32,int addr)
3600 {
3601   if(addr&1) return 0; // Indirect (register) jump
3602   if(addr>=start && addr<start+slen*4-4)
3603   {
3604     int t=(addr-start)>>2;
3605     // Delay slots are not valid branch targets
3606     //if(t>0&&(itype[t-1]==RJUMP||itype[t-1]==UJUMP||itype[t-1]==CJUMP||itype[t-1]==SJUMP||itype[t-1]==FJUMP)) return 0;
3607     // 64 -> 32 bit transition requires a recompile
3608     /*if(is32[t]&~unneeded_reg_upper[t]&~i_is32)
3609     {
3610       if(requires_32bit[t]&~i_is32) printf("optimizable: no\n");
3611       else printf("optimizable: yes\n");
3612     }*/
3613     //if(is32[t]&~unneeded_reg_upper[t]&~i_is32) return 0;
3614     if(requires_32bit[t]&~i_is32) return 0;
3615     else return 1;
3616   }
3617   return 0;
3618 }
3619
3620 #ifndef wb_invalidate
3621 void wb_invalidate(signed char pre[],signed char entry[],uint64_t dirty,uint64_t is32,
3622   uint64_t u,uint64_t uu)
3623 {
3624   int hr;
3625   for(hr=0;hr<HOST_REGS;hr++) {
3626     if(hr!=EXCLUDE_REG) {
3627       if(pre[hr]!=entry[hr]) {
3628         if(pre[hr]>=0) {
3629           if((dirty>>hr)&1) {
3630             if(get_reg(entry,pre[hr])<0) {
3631               if(pre[hr]<64) {
3632                 if(!((u>>pre[hr])&1)) {
3633                   emit_storereg(pre[hr],hr);
3634                   if( ((is32>>pre[hr])&1) && !((uu>>pre[hr])&1) ) {
3635                     emit_sarimm(hr,31,hr);
3636                     emit_storereg(pre[hr]|64,hr);
3637                   }
3638                 }
3639               }else{
3640                 if(!((uu>>(pre[hr]&63))&1) && !((is32>>(pre[hr]&63))&1)) {
3641                   emit_storereg(pre[hr],hr);
3642                 }
3643               }
3644             }
3645           }
3646         }
3647       }
3648     }
3649   }
3650   // Move from one register to another (no writeback)
3651   for(hr=0;hr<HOST_REGS;hr++) {
3652     if(hr!=EXCLUDE_REG) {
3653       if(pre[hr]!=entry[hr]) {
3654         if(pre[hr]>=0&&(pre[hr]&63)<TEMPREG) {
3655           int nr;
3656           if((nr=get_reg(entry,pre[hr]))>=0) {
3657             emit_mov(hr,nr);
3658           }
3659         }
3660       }
3661     }
3662   }
3663 }
3664 #endif
3665
3666 // Load the specified registers
3667 // This only loads the registers given as arguments because
3668 // we don't want to load things that will be overwritten
3669 void load_regs(signed char entry[],signed char regmap[],int is32,int rs1,int rs2)
3670 {
3671   int hr;
3672   // Load 32-bit regs
3673   for(hr=0;hr<HOST_REGS;hr++) {
3674     if(hr!=EXCLUDE_REG&&regmap[hr]>=0) {
3675       if(entry[hr]!=regmap[hr]) {
3676         if(regmap[hr]==rs1||regmap[hr]==rs2)
3677         {
3678           if(regmap[hr]==0) {
3679             emit_zeroreg(hr);
3680           }
3681           else
3682           {
3683             emit_loadreg(regmap[hr],hr);
3684           }
3685         }
3686       }
3687     }
3688   }
3689   //Load 64-bit regs
3690   for(hr=0;hr<HOST_REGS;hr++) {
3691     if(hr!=EXCLUDE_REG&&regmap[hr]>=0) {
3692       if(entry[hr]!=regmap[hr]) {
3693         if(regmap[hr]-64==rs1||regmap[hr]-64==rs2)
3694         {
3695           assert(regmap[hr]!=64);
3696           if((is32>>(regmap[hr]&63))&1) {
3697             int lr=get_reg(regmap,regmap[hr]-64);
3698             if(lr>=0)
3699               emit_sarimm(lr,31,hr);
3700             else
3701               emit_loadreg(regmap[hr],hr);
3702           }
3703           else
3704           {
3705             emit_loadreg(regmap[hr],hr);
3706           }
3707         }
3708       }
3709     }
3710   }
3711 }
3712
3713 // Load registers prior to the start of a loop
3714 // so that they are not loaded within the loop
3715 static void loop_preload(signed char pre[],signed char entry[])
3716 {
3717   int hr;
3718   for(hr=0;hr<HOST_REGS;hr++) {
3719     if(hr!=EXCLUDE_REG) {
3720       if(pre[hr]!=entry[hr]) {
3721         if(entry[hr]>=0) {
3722           if(get_reg(pre,entry[hr])<0) {
3723             assem_debug("loop preload:\n");
3724             //printf("loop preload: %d\n",hr);
3725             if(entry[hr]==0) {
3726               emit_zeroreg(hr);
3727             }
3728             else if(entry[hr]<TEMPREG)
3729             {
3730               emit_loadreg(entry[hr],hr);
3731             }
3732             else if(entry[hr]-64<TEMPREG)
3733             {
3734               emit_loadreg(entry[hr],hr);
3735             }
3736           }
3737         }
3738       }
3739     }
3740   }
3741 }
3742
3743 // Generate address for load/store instruction
3744 void address_generation(int i,struct regstat *i_regs,signed char entry[])
3745 {
3746   if(itype[i]==LOAD||itype[i]==LOADLR||itype[i]==STORE||itype[i]==STORELR||itype[i]==C1LS) {
3747     int ra;
3748     int agr=AGEN1+(i&1);
3749     int mgr=MGEN1+(i&1);
3750     if(itype[i]==LOAD) {
3751       ra=get_reg(i_regs->regmap,rt1[i]);
3752       //if(rt1[i]) assert(ra>=0);
3753     }
3754     if(itype[i]==LOADLR) {
3755       ra=get_reg(i_regs->regmap,FTEMP);
3756     }
3757     if(itype[i]==STORE||itype[i]==STORELR) {
3758       ra=get_reg(i_regs->regmap,agr);
3759       if(ra<0) ra=get_reg(i_regs->regmap,-1);
3760     }
3761     if(itype[i]==C1LS) {
3762       if (opcode[i]==0x31||opcode[i]==0x35) // LWC1/LDC1
3763         ra=get_reg(i_regs->regmap,FTEMP);
3764       else { // SWC1/SDC1
3765         ra=get_reg(i_regs->regmap,agr);
3766         if(ra<0) ra=get_reg(i_regs->regmap,-1);
3767       }
3768     }
3769     int rs=get_reg(i_regs->regmap,rs1[i]);
3770     int rm=get_reg(i_regs->regmap,TLREG);
3771     if(ra>=0) {
3772       int offset=imm[i];
3773       int c=(i_regs->wasconst>>rs)&1;
3774       if(rs1[i]==0) {
3775         // Using r0 as a base address
3776         /*if(rm>=0) {
3777           if(!entry||entry[rm]!=mgr) {
3778             generate_map_const(offset,rm);
3779           } // else did it in the previous cycle
3780         }*/
3781         if(!entry||entry[ra]!=agr) {
3782           if (opcode[i]==0x22||opcode[i]==0x26) {
3783             emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR
3784           }else if (opcode[i]==0x1a||opcode[i]==0x1b) {
3785             emit_movimm(offset&0xFFFFFFF8,ra); // LDL/LDR
3786           }else{
3787             emit_movimm(offset,ra);
3788           }
3789         } // else did it in the previous cycle
3790       }
3791       else if(rs<0) {
3792         if(!entry||entry[ra]!=rs1[i])
3793           emit_loadreg(rs1[i],ra);
3794         //if(!entry||entry[ra]!=rs1[i])
3795         //  printf("poor load scheduling!\n");
3796       }
3797       else if(c) {
3798         if(rm>=0) {
3799           if(!entry||entry[rm]!=mgr) {
3800             if(itype[i]==STORE||itype[i]==STORELR||opcode[i]==0x39||opcode[i]==0x3D) {
3801               // Stores to memory go thru the mapper to detect self-modifying
3802               // code, loads don't.
3803               if((unsigned int)(constmap[i][rs]+offset)>=0xC0000000 ||
3804                  (unsigned int)(constmap[i][rs]+offset)<0x80800000 )
3805                 generate_map_const(constmap[i][rs]+offset,rm);
3806             }else{
3807               if((signed int)(constmap[i][rs]+offset)>=(signed int)0xC0000000)
3808                 generate_map_const(constmap[i][rs]+offset,rm);
3809             }
3810           }
3811         }
3812         if(rs1[i]!=rt1[i]||itype[i]!=LOAD) {
3813           if(!entry||entry[ra]!=agr) {
3814             if (opcode[i]==0x22||opcode[i]==0x26) {
3815               emit_movimm((constmap[i][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR
3816             }else if (opcode[i]==0x1a||opcode[i]==0x1b) {
3817               emit_movimm((constmap[i][rs]+offset)&0xFFFFFFF8,ra); // LDL/LDR
3818             }else{
3819               #ifdef HOST_IMM_ADDR32
3820               if((itype[i]!=LOAD&&opcode[i]!=0x31&&opcode[i]!=0x35) ||
3821                  (using_tlb&&((signed int)constmap[i][rs]+offset)>=(signed int)0xC0000000))
3822               #endif
3823               emit_movimm(constmap[i][rs]+offset,ra);
3824             }
3825           } // else did it in the previous cycle
3826         } // else load_consts already did it
3827       }
3828       if(offset&&!c&&rs1[i]) {
3829         if(rs>=0) {
3830           emit_addimm(rs,offset,ra);
3831         }else{
3832           emit_addimm(ra,offset,ra);
3833         }
3834       }
3835     }
3836   }
3837   // Preload constants for next instruction
3838   if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS) {
3839     int agr,ra;
3840     #ifndef HOST_IMM_ADDR32
3841     // Mapper entry
3842     agr=MGEN1+((i+1)&1);
3843     ra=get_reg(i_regs->regmap,agr);
3844     if(ra>=0) {
3845       int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
3846       int offset=imm[i+1];
3847       int c=(regs[i+1].wasconst>>rs)&1;
3848       if(c) {
3849         if(itype[i+1]==STORE||itype[i+1]==STORELR||opcode[i+1]==0x39||opcode[i+1]==0x3D) {
3850           // Stores to memory go thru the mapper to detect self-modifying
3851           // code, loads don't.
3852           if((unsigned int)(constmap[i+1][rs]+offset)>=0xC0000000 ||
3853              (unsigned int)(constmap[i+1][rs]+offset)<0x80800000 )
3854             generate_map_const(constmap[i+1][rs]+offset,ra);
3855         }else{
3856           if((signed int)(constmap[i+1][rs]+offset)>=(signed int)0xC0000000)
3857             generate_map_const(constmap[i+1][rs]+offset,ra);
3858         }
3859       }
3860       /*else if(rs1[i]==0) {
3861         generate_map_const(offset,ra);
3862       }*/
3863     }
3864     #endif
3865     // Actual address
3866     agr=AGEN1+((i+1)&1);
3867     ra=get_reg(i_regs->regmap,agr);
3868     if(ra>=0) {
3869       int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
3870       int offset=imm[i+1];
3871       int c=(regs[i+1].wasconst>>rs)&1;
3872       if(c&&(rs1[i+1]!=rt1[i+1]||itype[i+1]!=LOAD)) {
3873         if (opcode[i+1]==0x22||opcode[i+1]==0x26) {
3874           emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR
3875         }else if (opcode[i+1]==0x1a||opcode[i+1]==0x1b) {
3876           emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFF8,ra); // LDL/LDR
3877         }else{
3878           #ifdef HOST_IMM_ADDR32
3879           if((itype[i+1]!=LOAD&&opcode[i+1]!=0x31&&opcode[i+1]!=0x35) ||
3880              (using_tlb&&((signed int)constmap[i+1][rs]+offset)>=(signed int)0xC0000000))
3881           #endif
3882           emit_movimm(constmap[i+1][rs]+offset,ra);
3883         }
3884       }
3885       else if(rs1[i+1]==0) {
3886         // Using r0 as a base address
3887         if (opcode[i+1]==0x22||opcode[i+1]==0x26) {
3888           emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR
3889         }else if (opcode[i+1]==0x1a||opcode[i+1]==0x1b) {
3890           emit_movimm(offset&0xFFFFFFF8,ra); // LDL/LDR
3891         }else{
3892           emit_movimm(offset,ra);
3893         }
3894       }
3895     }
3896   }
3897 }
3898
3899 int get_final_value(int hr, int i, int *value)
3900 {
3901   int reg=regs[i].regmap[hr];
3902   while(i<slen-1) {
3903     if(regs[i+1].regmap[hr]!=reg) break;
3904     if(!((regs[i+1].isconst>>hr)&1)) break;
3905     if(bt[i+1]) break;
3906     i++;
3907   }
3908   if(i<slen-1) {
3909     if(itype[i]==UJUMP||itype[i]==RJUMP||itype[i]==CJUMP||itype[i]==SJUMP) {
3910       *value=constmap[i][hr];
3911       return 1;