libpcsxcore/new_dynarec/new_dynarec.c

   1 /* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
   2  *   Mupen64plus - new_dynarec.c                                           *
   3  *   Copyright (C) 2009-2010 Ari64                                         *
   4  *                                                                         *
   5  *   This program is free software; you can redistribute it and/or modify  *
   6  *   it under the terms of the GNU General Public License as published by  *
   7  *   the Free Software Foundation; either version 2 of the License, or     *
   8  *   (at your option) any later version.                                   *
   9  *                                                                         *
  10  *   This program is distributed in the hope that it will be useful,       *
  11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  13  *   GNU General Public License for more details.                          *
  14  *                                                                         *
  15  *   You should have received a copy of the GNU General Public License     *
  16  *   along with this program; if not, write to the                         *
  17  *   Free Software Foundation, Inc.,                                       *
  18  *   51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.          *
  19  * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
  20
  21 #include <stdlib.h>
  22 #include <stdint.h> //include for uint64_t
  23 #include <assert.h>
  24
  25 #include "emu_if.h" //emulator interface
  26
  27 #include <sys/mman.h>
  28
  29 #ifdef __i386__
  30 #include "assem_x86.h"
  31 #endif
  32 #ifdef __x86_64__
  33 #include "assem_x64.h"
  34 #endif
  35 #ifdef __arm__
  36 #include "assem_arm.h"
  37 #endif
  38
  39 #define MAXBLOCK 4096
  40 #define MAX_OUTPUT_BLOCK_SIZE 262144
  41 #define CLOCK_DIVIDER 2
  42
  43 struct regstat
  44 {
  45   signed char regmap_entry[HOST_REGS];
  46   signed char regmap[HOST_REGS];
  47   uint64_t was32;
  48   uint64_t is32;
  49   uint64_t wasdirty;
  50   uint64_t dirty;
  51   uint64_t u;
  52   uint64_t uu;
  53   u_int wasconst;
  54   u_int isconst;
  55   uint64_t constmap[HOST_REGS];
  56 };
  57
  58 struct ll_entry
  59 {
  60   u_int vaddr;
  61   u_int reg32;
  62   void *addr;
  63   struct ll_entry *next;
  64 };
  65
  66   u_int start;
  67   u_int *source;
  68   u_int pagelimit;
  69   char insn[MAXBLOCK][10];
  70   u_char itype[MAXBLOCK];
  71   u_char opcode[MAXBLOCK];
  72   u_char opcode2[MAXBLOCK];
  73   u_char bt[MAXBLOCK];
  74   u_char rs1[MAXBLOCK];
  75   u_char rs2[MAXBLOCK];
  76   u_char rt1[MAXBLOCK];
  77   u_char rt2[MAXBLOCK];
  78   u_char us1[MAXBLOCK];
  79   u_char us2[MAXBLOCK];
  80   u_char dep1[MAXBLOCK];
  81   u_char dep2[MAXBLOCK];
  82   u_char lt1[MAXBLOCK];
  83   int imm[MAXBLOCK];
  84   u_int ba[MAXBLOCK];
  85   char likely[MAXBLOCK];
  86   char is_ds[MAXBLOCK];
  87   uint64_t unneeded_reg[MAXBLOCK];
  88   uint64_t unneeded_reg_upper[MAXBLOCK];
  89   uint64_t branch_unneeded_reg[MAXBLOCK];
  90   uint64_t branch_unneeded_reg_upper[MAXBLOCK];
  91   uint64_t p32[MAXBLOCK];
  92   uint64_t pr32[MAXBLOCK];
  93   signed char regmap_pre[MAXBLOCK][HOST_REGS];
  94   signed char regmap[MAXBLOCK][HOST_REGS];
  95   signed char regmap_entry[MAXBLOCK][HOST_REGS];
  96   uint64_t constmap[MAXBLOCK][HOST_REGS];
  97   uint64_t known_value[HOST_REGS];
  98   u_int known_reg;
  99   struct regstat regs[MAXBLOCK];
 100   struct regstat branch_regs[MAXBLOCK];
 101   u_int needed_reg[MAXBLOCK];
 102   uint64_t requires_32bit[MAXBLOCK];
 103   u_int wont_dirty[MAXBLOCK];
 104   u_int will_dirty[MAXBLOCK];
 105   int ccadj[MAXBLOCK];
 106   int slen;
 107   u_int instr_addr[MAXBLOCK];
 108   u_int link_addr[MAXBLOCK][3];
 109   int linkcount;
 110   u_int stubs[MAXBLOCK*3][8];
 111   int stubcount;
 112   u_int literals[1024][2];
 113   int literalcount;
 114   int is_delayslot;
 115   int cop1_usable;
 116   u_char *out;
 117   struct ll_entry *jump_in[4096];
 118   struct ll_entry *jump_out[4096];
 119   struct ll_entry *jump_dirty[4096];
 120   u_int hash_table[65536][4]  __attribute__((aligned(16)));
 121   char shadow[1048576]  __attribute__((aligned(16)));
 122   void *copy;
 123   int expirep;
 124   u_int using_tlb;
 125   u_int stop_after_jal;
 126   extern u_char restore_candidate[512];
 127   extern int cycle_count;
 128
 129   /* registers that may be allocated */
 130   /* 1-31 gpr */
 131 #define HIREG 32 // hi
 132 #define LOREG 33 // lo
 133 #define FSREG 34 // FPU status (FCSR)
 134 #define CSREG 35 // Coprocessor status
 135 #define CCREG 36 // Cycle count
 136 #define INVCP 37 // Pointer to invalid_code
 137 #define TEMPREG 38
 138 #define FTEMP 38 // FPU temporary register
 139 #define PTEMP 39 // Prefetch temporary register
 140 #define TLREG 40 // TLB mapping offset
 141 #define RHASH 41 // Return address hash
 142 #define RHTBL 42 // Return address hash table address
 143 #define RTEMP 43 // JR/JALR address register
 144 #define MAXREG 43
 145 #define AGEN1 44 // Address generation temporary register
 146 #define AGEN2 45 // Address generation temporary register
 147 #define MGEN1 46 // Maptable address generation temporary register
 148 #define MGEN2 47 // Maptable address generation temporary register
 149 #define BTREG 48 // Branch target temporary register
 150
 151   /* instruction types */
 152 #define NOP 0     // No operation
 153 #define LOAD 1    // Load
 154 #define STORE 2   // Store
 155 #define LOADLR 3  // Unaligned load
 156 #define STORELR 4 // Unaligned store
 157 #define MOV 5     // Move
 158 #define ALU 6     // Arithmetic/logic
 159 #define MULTDIV 7 // Multiply/divide
 160 #define SHIFT 8   // Shift by register
 161 #define SHIFTIMM 9// Shift by immediate
 162 #define IMM16 10  // 16-bit immediate
 163 #define RJUMP 11  // Unconditional jump to register
 164 #define UJUMP 12  // Unconditional jump
 165 #define CJUMP 13  // Conditional branch (BEQ/BNE/BGTZ/BLEZ)
 166 #define SJUMP 14  // Conditional branch (regimm format)
 167 #define COP0 15   // Coprocessor 0
 168 #define COP1 16   // Coprocessor 1
 169 #define C1LS 17   // Coprocessor 1 load/store
 170 #define FJUMP 18  // Conditional branch (floating point)
 171 #define FLOAT 19  // Floating point unit
 172 #define FCONV 20  // Convert integer to float
 173 #define FCOMP 21  // Floating point compare (sets FSREG)
 174 #define SYSCALL 22// SYSCALL
 175 #define OTHER 23  // Other
 176 #define SPAN 24   // Branch/delay slot spans 2 pages
 177 #define NI 25     // Not implemented
 178
 179   /* stubs */
 180 #define CC_STUB 1
 181 #define FP_STUB 2
 182 #define LOADB_STUB 3
 183 #define LOADH_STUB 4
 184 #define LOADW_STUB 5
 185 #define LOADD_STUB 6
 186 #define LOADBU_STUB 7
 187 #define LOADHU_STUB 8
 188 #define STOREB_STUB 9
 189 #define STOREH_STUB 10
 190 #define STOREW_STUB 11
 191 #define STORED_STUB 12
 192 #define STORELR_STUB 13
 193 #define INVCODE_STUB 14
 194
 195   /* branch codes */
 196 #define TAKEN 1
 197 #define NOTTAKEN 2
 198 #define NULLDS 3
 199
 200 // asm linkage
 201 int new_recompile_block(int addr);
 202 void *get_addr_ht(u_int vaddr);
 203 void invalidate_block(u_int block);
 204 void invalidate_addr(u_int addr);
 205 void remove_hash(int vaddr);
 206 void jump_vaddr();
 207 void dyna_linker();
 208 void dyna_linker_ds();
 209 void verify_code();
 210 void verify_code_vm();
 211 void verify_code_ds();
 212 void cc_interrupt();
 213 void fp_exception();
 214 void fp_exception_ds();
 215 void jump_syscall();
 216 void jump_eret();
 217
 218 // TLB
 219 void TLBWI_new();
 220 void TLBWR_new();
 221 void read_nomem_new();
 222 void read_nomemb_new();
 223 void read_nomemh_new();
 224 void read_nomemd_new();
 225 void write_nomem_new();
 226 void write_nomemb_new();
 227 void write_nomemh_new();
 228 void write_nomemd_new();
 229 void write_rdram_new();
 230 void write_rdramb_new();
 231 void write_rdramh_new();
 232 void write_rdramd_new();
 233 extern u_int memory_map[1048576];
 234
 235 // Needed by assembler
 236 void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32);
 237 void wb_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty);
 238 void wb_needed_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr);
 239 void load_all_regs(signed char i_regmap[]);
 240 void load_needed_regs(signed char i_regmap[],signed char next_regmap[]);
 241 void load_regs_entry(int t);
 242 void load_all_consts(signed char regmap[],int is32,u_int dirty,int i);
 243
 244 int tracedebug=0;
 245
 246 //#define DEBUG_CYCLE_COUNT 1
 247
 248 void nullf() {}
 249 //#define assem_debug printf
 250 //#define inv_debug printf
 251 #define assem_debug nullf
 252 #define inv_debug nullf
 253
 254 static void tlb_hacks()
 255 {
 256 #ifndef DISABLE_TLB
 257   // Goldeneye hack
 258   if (strncmp((char *) ROM_HEADER->nom, "GOLDENEYE",9) == 0)
 259   {
 260     u_int addr;
 261     int n;
 262     switch (ROM_HEADER->Country_code&0xFF)
 263     {
 264       case 0x45: // U
 265         addr=0x34b30;
 266         break;
 267       case 0x4A: // J
 268         addr=0x34b70;
 269         break;
 270       case 0x50: // E
 271         addr=0x329f0;
 272         break;
 273       default:
 274         // Unknown country code
 275         addr=0;
 276         break;
 277     }
 278     u_int rom_addr=(u_int)rom;
 279     #ifdef ROM_COPY
 280     // Since memory_map is 32-bit, on 64-bit systems the rom needs to be
 281     // in the lower 4G of memory to use this hack.  Copy it if necessary.
 282     if((void *)rom>(void *)0xffffffff) {
 283       munmap(ROM_COPY, 67108864);
 284       if(mmap(ROM_COPY, 12582912,
 285               PROT_READ | PROT_WRITE,
 286               MAP_FIXED | MAP_PRIVATE | MAP_ANONYMOUS,
 287               -1, 0) <= 0) {printf("mmap() failed\n");}
 288       memcpy(ROM_COPY,rom,12582912);
 289       rom_addr=(u_int)ROM_COPY;
 290     }
 291     #endif
 292     if(addr) {
 293       for(n=0x7F000;n<0x80000;n++) {
 294         memory_map[n]=(((u_int)(rom_addr+addr-0x7F000000))>>2)|0x40000000;
 295       }
 296     }
 297   }
 298 #endif
 299 }
 300
 301 static u_int get_page(u_int vaddr)
 302 {
 303   u_int page=(vaddr^0x80000000)>>12;
 304 #ifndef DISABLE_TLB
 305   if(page>262143&&tlb_LUT_r[vaddr>>12]) page=(tlb_LUT_r[vaddr>>12]^0x80000000)>>12;
 306 #endif
 307   if(page>2048) page=2048+(page&2047);
 308   return page;
 309 }
 310
 311 static u_int get_vpage(u_int vaddr)
 312 {
 313   u_int vpage=(vaddr^0x80000000)>>12;
 314 #ifndef DISABLE_TLB
 315   if(vpage>262143&&tlb_LUT_r[vaddr>>12]) vpage&=2047; // jump_dirty uses a hash of the virtual address instead
 316 #endif
 317   if(vpage>2048) vpage=2048+(vpage&2047);
 318   return vpage;
 319 }
 320
 321 // Get address from virtual address
 322 // This is called from the recompiled JR/JALR instructions
 323 void *get_addr(u_int vaddr)
 324 {
 325   u_int page=get_page(vaddr);
 326   u_int vpage=get_vpage(vaddr);
 327   struct ll_entry *head;
 328   //printf("TRACE: count=%d next=%d (get_addr %x,page %d)\n",Count,next_interupt,vaddr,page);
 329   head=jump_in[page];
 330   while(head!=NULL) {
 331     if(head->vaddr==vaddr&&head->reg32==0) {
 332   //printf("TRACE: count=%d next=%d (get_addr match %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
 333       int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
 334       ht_bin[3]=ht_bin[1];
 335       ht_bin[2]=ht_bin[0];
 336       ht_bin[1]=(int)head->addr;
 337       ht_bin[0]=vaddr;
 338       return head->addr;
 339     }
 340     head=head->next;
 341   }
 342   head=jump_dirty[vpage];
 343   while(head!=NULL) {
 344     if(head->vaddr==vaddr&&head->reg32==0) {
 345       //printf("TRACE: count=%d next=%d (get_addr match dirty %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
 346       // Don't restore blocks which are about to expire from the cache
 347       if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
 348       if(verify_dirty(head->addr)) {
 349         //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]);
 350         invalid_code[vaddr>>12]=0;
 351         memory_map[vaddr>>12]|=0x40000000;
 352         if(vpage<2048) {
 353 #ifndef DISABLE_TLB
 354           if(tlb_LUT_r[vaddr>>12]) {
 355             invalid_code[tlb_LUT_r[vaddr>>12]>>12]=0;
 356             memory_map[tlb_LUT_r[vaddr>>12]>>12]|=0x40000000;
 357           }
 358 #endif
 359           restore_candidate[vpage>>3]|=1<<(vpage&7);
 360         }
 361         else restore_candidate[page>>3]|=1<<(page&7);
 362         int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
 363         if(ht_bin[0]==vaddr) {
 364           ht_bin[1]=(int)head->addr; // Replace existing entry
 365         }
 366         else
 367         {
 368           ht_bin[3]=ht_bin[1];
 369           ht_bin[2]=ht_bin[0];
 370           ht_bin[1]=(int)head->addr;
 371           ht_bin[0]=vaddr;
 372         }
 373         return head->addr;
 374       }
 375     }
 376     head=head->next;
 377   }
 378   //printf("TRACE: count=%d next=%d (get_addr no-match %x)\n",Count,next_interupt,vaddr);
 379   int r=new_recompile_block(vaddr);
 380   if(r==0) return get_addr(vaddr);
 381   // Execute in unmapped page, generate pagefault execption
 382   Status|=2;
 383   Cause=(vaddr<<31)|0x8;
 384   EPC=(vaddr&1)?vaddr-5:vaddr;
 385   BadVAddr=(vaddr&~1);
 386   Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0);
 387   EntryHi=BadVAddr&0xFFFFE000;
 388   return get_addr_ht(0x80000000);
 389 }
 390 // Look up address in hash table first
 391 void *get_addr_ht(u_int vaddr)
 392 {
 393   //printf("TRACE: count=%d next=%d (get_addr_ht %x)\n",Count,next_interupt,vaddr);
 394   int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
 395   if(ht_bin[0]==vaddr) return (void *)ht_bin[1];
 396   if(ht_bin[2]==vaddr) return (void *)ht_bin[3];
 397   return get_addr(vaddr);
 398 }
 399
 400 void *get_addr_32(u_int vaddr,u_int flags)
 401 {
 402   //printf("TRACE: count=%d next=%d (get_addr_32 %x,flags %x)\n",Count,next_interupt,vaddr,flags);
 403   int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
 404   if(ht_bin[0]==vaddr) return (void *)ht_bin[1];
 405   if(ht_bin[2]==vaddr) return (void *)ht_bin[3];
 406   u_int page=get_page(vaddr);
 407   u_int vpage=get_vpage(vaddr);
 408   struct ll_entry *head;
 409   head=jump_in[page];
 410   while(head!=NULL) {
 411     if(head->vaddr==vaddr&&(head->reg32&flags)==0) {
 412       //printf("TRACE: count=%d next=%d (get_addr_32 match %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
 413       if(head->reg32==0) {
 414         int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
 415         if(ht_bin[0]==-1) {
 416           ht_bin[1]=(int)head->addr;
 417           ht_bin[0]=vaddr;
 418         }else if(ht_bin[2]==-1) {
 419           ht_bin[3]=(int)head->addr;
 420           ht_bin[2]=vaddr;
 421         }
 422         //ht_bin[3]=ht_bin[1];
 423         //ht_bin[2]=ht_bin[0];
 424         //ht_bin[1]=(int)head->addr;
 425         //ht_bin[0]=vaddr;
 426       }
 427       return head->addr;
 428     }
 429     head=head->next;
 430   }
 431   head=jump_dirty[vpage];
 432   while(head!=NULL) {
 433     if(head->vaddr==vaddr&&(head->reg32&flags)==0) {
 434       //printf("TRACE: count=%d next=%d (get_addr_32 match dirty %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
 435       // Don't restore blocks which are about to expire from the cache
 436       if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
 437       if(verify_dirty(head->addr)) {
 438         //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]);
 439         invalid_code[vaddr>>12]=0;
 440         memory_map[vaddr>>12]|=0x40000000;
 441         if(vpage<2048) {
 442 #ifndef DISABLE_TLB
 443           if(tlb_LUT_r[vaddr>>12]) {
 444             invalid_code[tlb_LUT_r[vaddr>>12]>>12]=0;
 445             memory_map[tlb_LUT_r[vaddr>>12]>>12]|=0x40000000;
 446           }
 447 #endif
 448           restore_candidate[vpage>>3]|=1<<(vpage&7);
 449         }
 450         else restore_candidate[page>>3]|=1<<(page&7);
 451         if(head->reg32==0) {
 452           int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
 453           if(ht_bin[0]==-1) {
 454             ht_bin[1]=(int)head->addr;
 455             ht_bin[0]=vaddr;
 456           }else if(ht_bin[2]==-1) {
 457             ht_bin[3]=(int)head->addr;
 458             ht_bin[2]=vaddr;
 459           }
 460           //ht_bin[3]=ht_bin[1];
 461           //ht_bin[2]=ht_bin[0];
 462           //ht_bin[1]=(int)head->addr;
 463           //ht_bin[0]=vaddr;
 464         }
 465         return head->addr;
 466       }
 467     }
 468     head=head->next;
 469   }
 470   //printf("TRACE: count=%d next=%d (get_addr_32 no-match %x,flags %x)\n",Count,next_interupt,vaddr,flags);
 471   int r=new_recompile_block(vaddr);
 472   if(r==0) return get_addr(vaddr);
 473   // Execute in unmapped page, generate pagefault execption
 474   Status|=2;
 475   Cause=(vaddr<<31)|0x8;
 476   EPC=(vaddr&1)?vaddr-5:vaddr;
 477   BadVAddr=(vaddr&~1);
 478   Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0);
 479   EntryHi=BadVAddr&0xFFFFE000;
 480   return get_addr_ht(0x80000000);
 481 }
 482
 483 void clear_all_regs(signed char regmap[])
 484 {
 485   int hr;
 486   for (hr=0;hr<HOST_REGS;hr++) regmap[hr]=-1;
 487 }
 488
 489 signed char get_reg(signed char regmap[],int r)
 490 {
 491   int hr;
 492   for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&&regmap[hr]==r) return hr;
 493   return -1;
 494 }
 495
 496 // Find a register that is available for two consecutive cycles
 497 signed char get_reg2(signed char regmap1[],signed char regmap2[],int r)
 498 {
 499   int hr;
 500   for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&&regmap1[hr]==r&&regmap2[hr]==r) return hr;
 501   return -1;
 502 }
 503
 504 int count_free_regs(signed char regmap[])
 505 {
 506   int count=0;
 507   int hr;
 508   for(hr=0;hr<HOST_REGS;hr++)
 509   {
 510     if(hr!=EXCLUDE_REG) {
 511       if(regmap[hr]<0) count++;
 512     }
 513   }
 514   return count;
 515 }
 516
 517 void dirty_reg(struct regstat *cur,signed char reg)
 518 {
 519   int hr;
 520   if(!reg) return;
 521   for (hr=0;hr<HOST_REGS;hr++) {
 522     if((cur->regmap[hr]&63)==reg) {
 523       cur->dirty|=1<<hr;
 524     }
 525   }
 526 }
 527
 528 // If we dirty the lower half of a 64 bit register which is now being
 529 // sign-extended, we need to dump the upper half.
 530 // Note: Do this only after completion of the instruction, because
 531 // some instructions may need to read the full 64-bit value even if
 532 // overwriting it (eg SLTI, DSRA32).
 533 static void flush_dirty_uppers(struct regstat *cur)
 534 {
 535   int hr,reg;
 536   for (hr=0;hr<HOST_REGS;hr++) {
 537     if((cur->dirty>>hr)&1) {
 538       reg=cur->regmap[hr];
 539       if(reg>=64)
 540         if((cur->is32>>(reg&63))&1) cur->regmap[hr]=-1;
 541     }
 542   }
 543 }
 544
 545 void set_const(struct regstat *cur,signed char reg,uint64_t value)
 546 {
 547   int hr;
 548   if(!reg) return;
 549   for (hr=0;hr<HOST_REGS;hr++) {
 550     if(cur->regmap[hr]==reg) {
 551       cur->isconst|=1<<hr;
 552       cur->constmap[hr]=value;
 553     }
 554     else if((cur->regmap[hr]^64)==reg) {
 555       cur->isconst|=1<<hr;
 556       cur->constmap[hr]=value>>32;
 557     }
 558   }
 559 }
 560
 561 void clear_const(struct regstat *cur,signed char reg)
 562 {
 563   int hr;
 564   if(!reg) return;
 565   for (hr=0;hr<HOST_REGS;hr++) {
 566     if((cur->regmap[hr]&63)==reg) {
 567       cur->isconst&=~(1<<hr);
 568     }
 569   }
 570 }
 571
 572 int is_const(struct regstat *cur,signed char reg)
 573 {
 574   int hr;
 575   if(!reg) return 1;
 576   for (hr=0;hr<HOST_REGS;hr++) {
 577     if((cur->regmap[hr]&63)==reg) {
 578       return (cur->isconst>>hr)&1;
 579     }
 580   }
 581   return 0;
 582 }
 583 uint64_t get_const(struct regstat *cur,signed char reg)
 584 {
 585   int hr;
 586   if(!reg) return 0;
 587   for (hr=0;hr<HOST_REGS;hr++) {
 588     if(cur->regmap[hr]==reg) {
 589       return cur->constmap[hr];
 590     }
 591   }
 592   printf("Unknown constant in r%d\n",reg);
 593   exit(1);
 594 }
 595
 596 // Least soon needed registers
 597 // Look at the next ten instructions and see which registers
 598 // will be used.  Try not to reallocate these.
 599 void lsn(u_char hsn[], int i, int *preferred_reg)
 600 {
 601   int j;
 602   int b=-1;
 603   for(j=0;j<9;j++)
 604   {
 605     if(i+j>=slen) {
 606       j=slen-i-1;
 607       break;
 608     }
 609     if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
 610     {
 611       // Don't go past an unconditonal jump
 612       j++;
 613       break;
 614     }
 615   }
 616   for(;j>=0;j--)
 617   {
 618     if(rs1[i+j]) hsn[rs1[i+j]]=j;
 619     if(rs2[i+j]) hsn[rs2[i+j]]=j;
 620     if(rt1[i+j]) hsn[rt1[i+j]]=j;
 621     if(rt2[i+j]) hsn[rt2[i+j]]=j;
 622     if(itype[i+j]==STORE || itype[i+j]==STORELR) {
 623       // Stores can allocate zero
 624       hsn[rs1[i+j]]=j;
 625       hsn[rs2[i+j]]=j;
 626     }
 627     // On some architectures stores need invc_ptr
 628     #if defined(HOST_IMM8)
 629     if(itype[i+j]==STORE || itype[i+j]==STORELR || (opcode[i+j]&0x3b)==0x39) {
 630       hsn[INVCP]=j;
 631     }
 632     #endif
 633     if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP))
 634     {
 635       hsn[CCREG]=j;
 636       b=j;
 637     }
 638   }
 639   if(b>=0)
 640   {
 641     if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
 642     {
 643       // Follow first branch
 644       int t=(ba[i+b]-start)>>2;
 645       j=7-b;if(t+j>=slen) j=slen-t-1;
 646       for(;j>=0;j--)
 647       {
 648         if(rs1[t+j]) if(hsn[rs1[t+j]]>j+b+2) hsn[rs1[t+j]]=j+b+2;
 649         if(rs2[t+j]) if(hsn[rs2[t+j]]>j+b+2) hsn[rs2[t+j]]=j+b+2;
 650         //if(rt1[t+j]) if(hsn[rt1[t+j]]>j+b+2) hsn[rt1[t+j]]=j+b+2;
 651         //if(rt2[t+j]) if(hsn[rt2[t+j]]>j+b+2) hsn[rt2[t+j]]=j+b+2;
 652       }
 653     }
 654     // TODO: preferred register based on backward branch
 655   }
 656   // Delay slot should preferably not overwrite branch conditions or cycle count
 657   if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)) {
 658     if(rs1[i-1]) if(hsn[rs1[i-1]]>1) hsn[rs1[i-1]]=1;
 659     if(rs2[i-1]) if(hsn[rs2[i-1]]>1) hsn[rs2[i-1]]=1;
 660     hsn[CCREG]=1;
 661     // ...or hash tables
 662     hsn[RHASH]=1;
 663     hsn[RHTBL]=1;
 664   }
 665   // Coprocessor load/store needs FTEMP, even if not declared
 666   if(itype[i]==C1LS) {
 667     hsn[FTEMP]=0;
 668   }
 669   // Load L/R also uses FTEMP as a temporary register
 670   if(itype[i]==LOADLR) {
 671     hsn[FTEMP]=0;
 672   }
 673   // Also 64-bit SDL/SDR
 674   if(opcode[i]==0x2c||opcode[i]==0x2d) {
 675     hsn[FTEMP]=0;
 676   }
 677   // Don't remove the TLB registers either
 678   if(itype[i]==LOAD || itype[i]==LOADLR || itype[i]==STORE || itype[i]==STORELR || itype[i]==C1LS ) {
 679     hsn[TLREG]=0;
 680   }
 681   // Don't remove the miniht registers
 682   if(itype[i]==UJUMP||itype[i]==RJUMP)
 683   {
 684     hsn[RHASH]=0;
 685     hsn[RHTBL]=0;
 686   }
 687 }
 688
 689 // We only want to allocate registers if we're going to use them again soon
 690 int needed_again(int r, int i)
 691 {
 692   int j;
 693   int b=-1;
 694   int rn=10;
 695   int hr;
 696   u_char hsn[MAXREG+1];
 697   int preferred_reg;
 698
 699   memset(hsn,10,sizeof(hsn));
 700   lsn(hsn,i,&preferred_reg);
 701
 702   if(i>0&&(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000))
 703   {
 704     if(ba[i-1]<start || ba[i-1]>start+slen*4-4)
 705       return 0; // Don't need any registers if exiting the block
 706   }
 707   for(j=0;j<9;j++)
 708   {
 709     if(i+j>=slen) {
 710       j=slen-i-1;
 711       break;
 712     }
 713     if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
 714     {
 715       // Don't go past an unconditonal jump
 716       j++;
 717       break;
 718     }
 719     if(itype[i+j]==SYSCALL||((source[i+j]&0xfc00003f)==0x0d))
 720     {
 721       break;
 722     }
 723   }
 724   for(;j>=1;j--)
 725   {
 726     if(rs1[i+j]==r) rn=j;
 727     if(rs2[i+j]==r) rn=j;
 728     if((unneeded_reg[i+j]>>r)&1) rn=10;
 729     if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP))
 730     {
 731       b=j;
 732     }
 733   }
 734   /*
 735   if(b>=0)
 736   {
 737     if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
 738     {
 739       // Follow first branch
 740       int o=rn;
 741       int t=(ba[i+b]-start)>>2;
 742       j=7-b;if(t+j>=slen) j=slen-t-1;
 743       for(;j>=0;j--)
 744       {
 745         if(!((unneeded_reg[t+j]>>r)&1)) {
 746           if(rs1[t+j]==r) if(rn>j+b+2) rn=j+b+2;
 747           if(rs2[t+j]==r) if(rn>j+b+2) rn=j+b+2;
 748         }
 749         else rn=o;
 750       }
 751     }
 752   }*/
 753   for(hr=0;hr<HOST_REGS;hr++) {
 754     if(hr!=EXCLUDE_REG) {
 755       if(rn<hsn[hr]) return 1;
 756     }
 757   }
 758   return 0;
 759 }
 760
 761 // Try to match register allocations at the end of a loop with those
 762 // at the beginning
 763 int loop_reg(int i, int r, int hr)
 764 {
 765   int j,k;
 766   for(j=0;j<9;j++)
 767   {
 768     if(i+j>=slen) {
 769       j=slen-i-1;
 770       break;
 771     }
 772     if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
 773     {
 774       // Don't go past an unconditonal jump
 775       j++;
 776       break;
 777     }
 778   }
 779   k=0;
 780   if(i>0){
 781     if(itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)
 782       k--;
 783   }
 784   for(;k<j;k++)
 785   {
 786     if(r<64&&((unneeded_reg[i+k]>>r)&1)) return hr;
 787     if(r>64&&((unneeded_reg_upper[i+k]>>r)&1)) return hr;
 788     if(i+k>=0&&(itype[i+k]==UJUMP||itype[i+k]==CJUMP||itype[i+k]==SJUMP||itype[i+k]==FJUMP))
 789     {
 790       if(ba[i+k]>=start && ba[i+k]<(start+i*4))
 791       {
 792         int t=(ba[i+k]-start)>>2;
 793         int reg=get_reg(regs[t].regmap_entry,r);
 794         if(reg>=0) return reg;
 795         //reg=get_reg(regs[t+1].regmap_entry,r);
 796         //if(reg>=0) return reg;
 797       }
 798     }
 799   }
 800   return hr;
 801 }
 802
 803
 804 // Allocate every register, preserving source/target regs
 805 void alloc_all(struct regstat *cur,int i)
 806 {
 807   int hr;
 808
 809   for(hr=0;hr<HOST_REGS;hr++) {
 810     if(hr!=EXCLUDE_REG) {
 811       if(((cur->regmap[hr]&63)!=rs1[i])&&((cur->regmap[hr]&63)!=rs2[i])&&
 812          ((cur->regmap[hr]&63)!=rt1[i])&&((cur->regmap[hr]&63)!=rt2[i]))
 813       {
 814         cur->regmap[hr]=-1;
 815         cur->dirty&=~(1<<hr);
 816       }
 817       // Don't need zeros
 818       if((cur->regmap[hr]&63)==0)
 819       {
 820         cur->regmap[hr]=-1;
 821         cur->dirty&=~(1<<hr);
 822       }
 823     }
 824   }
 825 }
 826
 827
 828 void div64(int64_t dividend,int64_t divisor)
 829 {
 830   lo=dividend/divisor;
 831   hi=dividend%divisor;
 832   //printf("TRACE: ddiv %8x%8x %8x%8x\n" ,(int)reg[HIREG],(int)(reg[HIREG]>>32)
 833   //                                     ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
 834 }
 835 void divu64(uint64_t dividend,uint64_t divisor)
 836 {
 837   lo=dividend/divisor;
 838   hi=dividend%divisor;
 839   //printf("TRACE: ddivu %8x%8x %8x%8x\n",(int)reg[HIREG],(int)(reg[HIREG]>>32)
 840   //                                     ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
 841 }
 842
 843 void mult64(uint64_t m1,uint64_t m2)
 844 {
 845    unsigned long long int op1, op2, op3, op4;
 846    unsigned long long int result1, result2, result3, result4;
 847    unsigned long long int temp1, temp2, temp3, temp4;
 848    int sign = 0;
 849
 850    if (m1 < 0)
 851      {
 852     op2 = -m1;
 853     sign = 1 - sign;
 854      }
 855    else op2 = m1;
 856    if (m2 < 0)
 857      {
 858     op4 = -m2;
 859     sign = 1 - sign;
 860      }
 861    else op4 = m2;
 862
 863    op1 = op2 & 0xFFFFFFFF;
 864    op2 = (op2 >> 32) & 0xFFFFFFFF;
 865    op3 = op4 & 0xFFFFFFFF;
 866    op4 = (op4 >> 32) & 0xFFFFFFFF;
 867
 868    temp1 = op1 * op3;
 869    temp2 = (temp1 >> 32) + op1 * op4;
 870    temp3 = op2 * op3;
 871    temp4 = (temp3 >> 32) + op2 * op4;
 872
 873    result1 = temp1 & 0xFFFFFFFF;
 874    result2 = temp2 + (temp3 & 0xFFFFFFFF);
 875    result3 = (result2 >> 32) + temp4;
 876    result4 = (result3 >> 32);
 877
 878    lo = result1 | (result2 << 32);
 879    hi = (result3 & 0xFFFFFFFF) | (result4 << 32);
 880    if (sign)
 881      {
 882     hi = ~hi;
 883     if (!lo) hi++;
 884     else lo = ~lo + 1;
 885      }
 886 }
 887
 888 void multu64(uint64_t m1,uint64_t m2)
 889 {
 890    unsigned long long int op1, op2, op3, op4;
 891    unsigned long long int result1, result2, result3, result4;
 892    unsigned long long int temp1, temp2, temp3, temp4;
 893
 894    op1 = m1 & 0xFFFFFFFF;
 895    op2 = (m1 >> 32) & 0xFFFFFFFF;
 896    op3 = m2 & 0xFFFFFFFF;
 897    op4 = (m2 >> 32) & 0xFFFFFFFF;
 898
 899    temp1 = op1 * op3;
 900    temp2 = (temp1 >> 32) + op1 * op4;
 901    temp3 = op2 * op3;
 902    temp4 = (temp3 >> 32) + op2 * op4;
 903
 904    result1 = temp1 & 0xFFFFFFFF;
 905    result2 = temp2 + (temp3 & 0xFFFFFFFF);
 906    result3 = (result2 >> 32) + temp4;
 907    result4 = (result3 >> 32);
 908
 909    lo = result1 | (result2 << 32);
 910    hi = (result3 & 0xFFFFFFFF) | (result4 << 32);
 911
 912   //printf("TRACE: dmultu %8x%8x %8x%8x\n",(int)reg[HIREG],(int)(reg[HIREG]>>32)
 913   //                                      ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
 914 }
 915
 916 uint64_t ldl_merge(uint64_t original,uint64_t loaded,u_int bits)
 917 {
 918   if(bits) {
 919     original<<=64-bits;
 920     original>>=64-bits;
 921     loaded<<=bits;
 922     original|=loaded;
 923   }
 924   else original=loaded;
 925   return original;
 926 }
 927 uint64_t ldr_merge(uint64_t original,uint64_t loaded,u_int bits)
 928 {
 929   if(bits^56) {
 930     original>>=64-(bits^56);
 931     original<<=64-(bits^56);
 932     loaded>>=bits^56;
 933     original|=loaded;
 934   }
 935   else original=loaded;
 936   return original;
 937 }
 938
 939 #ifdef __i386__
 940 #include "assem_x86.c"
 941 #endif
 942 #ifdef __x86_64__
 943 #include "assem_x64.c"
 944 #endif
 945 #ifdef __arm__
 946 #include "assem_arm.c"
 947 #endif
 948
 949 // Add virtual address mapping to linked list
 950 void ll_add(struct ll_entry **head,int vaddr,void *addr)
 951 {
 952   struct ll_entry *new_entry;
 953   new_entry=malloc(sizeof(struct ll_entry));
 954   assert(new_entry!=NULL);
 955   new_entry->vaddr=vaddr;
 956   new_entry->reg32=0;
 957   new_entry->addr=addr;
 958   new_entry->next=*head;
 959   *head=new_entry;
 960 }
 961
 962 // Add virtual address mapping for 32-bit compiled block
 963 void ll_add_32(struct ll_entry **head,int vaddr,u_int reg32,void *addr)
 964 {
 965   struct ll_entry *new_entry;
 966   new_entry=malloc(sizeof(struct ll_entry));
 967   assert(new_entry!=NULL);
 968   new_entry->vaddr=vaddr;
 969   new_entry->reg32=reg32;
 970   new_entry->addr=addr;
 971   new_entry->next=*head;
 972   *head=new_entry;
 973 }
 974
 975 // Check if an address is already compiled
 976 // but don't return addresses which are about to expire from the cache
 977 void *check_addr(u_int vaddr)
 978 {
 979   u_int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
 980   if(ht_bin[0]==vaddr) {
 981     if(((ht_bin[1]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
 982       if(isclean(ht_bin[1])) return (void *)ht_bin[1];
 983   }
 984   if(ht_bin[2]==vaddr) {
 985     if(((ht_bin[3]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
 986       if(isclean(ht_bin[3])) return (void *)ht_bin[3];
 987   }
 988   u_int page=get_page(vaddr);
 989   struct ll_entry *head;
 990   head=jump_in[page];
 991   while(head!=NULL) {
 992     if(head->vaddr==vaddr&&head->reg32==0) {
 993       if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
 994         // Update existing entry with current address
 995         if(ht_bin[0]==vaddr) {
 996           ht_bin[1]=(int)head->addr;
 997           return head->addr;
 998         }
 999         if(ht_bin[2]==vaddr) {
1000           ht_bin[3]=(int)head->addr;
1001           return head->addr;
1002         }
1003         // Insert into hash table with low priority.
1004         // Don't evict existing entries, as they are probably
1005         // addresses that are being accessed frequently.
1006         if(ht_bin[0]==-1) {
1007           ht_bin[1]=(int)head->addr;
1008           ht_bin[0]=vaddr;
1009         }else if(ht_bin[2]==-1) {
1010           ht_bin[3]=(int)head->addr;
1011           ht_bin[2]=vaddr;
1012         }
1013         return head->addr;
1014       }
1015     }
1016     head=head->next;
1017   }
1018   return 0;
1019 }
1020
1021 void remove_hash(int vaddr)
1022 {
1023   //printf("remove hash: %x\n",vaddr);
1024   int *ht_bin=hash_table[(((vaddr)>>16)^vaddr)&0xFFFF];
1025   if(ht_bin[2]==vaddr) {
1026     ht_bin[2]=ht_bin[3]=-1;
1027   }
1028   if(ht_bin[0]==vaddr) {
1029     ht_bin[0]=ht_bin[2];
1030     ht_bin[1]=ht_bin[3];
1031     ht_bin[2]=ht_bin[3]=-1;
1032   }
1033 }
1034
1035 void ll_remove_matching_addrs(struct ll_entry **head,int addr,int shift)
1036 {
1037   struct ll_entry *next;
1038   while(*head) {
1039     if(((u_int)((*head)->addr)>>shift)==(addr>>shift) ||
1040        ((u_int)((*head)->addr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift))
1041     {
1042       inv_debug("EXP: Remove pointer to %x (%x)\n",(int)(*head)->addr,(*head)->vaddr);
1043       remove_hash((*head)->vaddr);
1044       next=(*head)->next;
1045       free(*head);
1046       *head=next;
1047     }
1048     else
1049     {
1050       head=&((*head)->next);
1051     }
1052   }
1053 }
1054
1055 // Remove all entries from linked list
1056 void ll_clear(struct ll_entry **head)
1057 {
1058   struct ll_entry *cur;
1059   struct ll_entry *next;
1060   if(cur=*head) {
1061     *head=0;
1062     while(cur) {
1063       next=cur->next;
1064       free(cur);
1065       cur=next;
1066     }
1067   }
1068 }
1069
1070 // Dereference the pointers and remove if it matches
1071 void ll_kill_pointers(struct ll_entry *head,int addr,int shift)
1072 {
1073   while(head) {
1074     int ptr=get_pointer(head->addr);
1075     inv_debug("EXP: Lookup pointer to %x at %x (%x)\n",(int)ptr,(int)head->addr,head->vaddr);
1076     if(((ptr>>shift)==(addr>>shift)) ||
1077        (((ptr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift)))
1078     {
1079       inv_debug("EXP: Kill pointer at %x (%x)\n",(int)head->addr,head->vaddr);
1080       kill_pointer(head->addr);
1081     }
1082     head=head->next;
1083   }
1084 }
1085
1086 // This is called when we write to a compiled block (see do_invstub)
1087 int invalidate_page(u_int page)
1088 {
1089   int modified=0;
1090   struct ll_entry *head;
1091   struct ll_entry *next;
1092   head=jump_in[page];
1093   jump_in[page]=0;
1094   while(head!=NULL) {
1095     inv_debug("INVALIDATE: %x\n",head->vaddr);
1096     remove_hash(head->vaddr);
1097     next=head->next;
1098     free(head);
1099     head=next;
1100   }
1101   head=jump_out[page];
1102   jump_out[page]=0;
1103   while(head!=NULL) {
1104     inv_debug("INVALIDATE: kill pointer to %x (%x)\n",head->vaddr,(int)head->addr);
1105     kill_pointer(head->addr);
1106     modified=1;
1107     next=head->next;
1108     free(head);
1109     head=next;
1110   }
1111   return modified;
1112 }
1113 void invalidate_block(u_int block)
1114 {
1115   int modified;
1116   u_int page=get_page(block<<12);
1117   u_int vpage=get_vpage(block<<12);
1118   inv_debug("INVALIDATE: %x (%d)\n",block<<12,page);
1119   //inv_debug("invalid_code[block]=%d\n",invalid_code[block]);
1120   u_int first,last;
1121   first=last=page;
1122   struct ll_entry *head;
1123   head=jump_dirty[vpage];
1124   //printf("page=%d vpage=%d\n",page,vpage);
1125   while(head!=NULL) {
1126     u_int start,end;
1127     if(vpage>2047||(head->vaddr>>12)==block) { // Ignore vaddr hash collision
1128       get_bounds((int)head->addr,&start,&end);
1129       //printf("start: %x end: %x\n",start,end);
1130       if(page<2048&&start>=0x80000000&&end<0x80800000) {
1131         if(((start-(u_int)rdram)>>12)<=page&&((end-1-(u_int)rdram)>>12)>=page) {
1132           if((((start-(u_int)rdram)>>12)&2047)<first) first=((start-(u_int)rdram)>>12)&2047;
1133           if((((end-1-(u_int)rdram)>>12)&2047)>last) last=((end-1-(u_int)rdram)>>12)&2047;
1134         }
1135       }
1136       if(page<2048&&(signed int)start>=(signed int)0xC0000000&&(signed int)end>=(signed int)0xC0000000) {
1137         if(((start+memory_map[start>>12]-(u_int)rdram)>>12)<=page&&((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)>=page) {
1138           if((((start+memory_map[start>>12]-(u_int)rdram)>>12)&2047)<first) first=((start+memory_map[start>>12]-(u_int)rdram)>>12)&2047;
1139           if((((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)&2047)>last) last=((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)&2047;
1140         }
1141       }
1142     }
1143     head=head->next;
1144   }
1145   //printf("first=%d last=%d\n",first,last);
1146   modified=invalidate_page(page);
1147   assert(first+5>page); // NB: this assumes MAXBLOCK<=4096 (4 pages)
1148   assert(last<page+5);
1149   // Invalidate the adjacent pages if a block crosses a 4K boundary
1150   while(first<page) {
1151     invalidate_page(first);
1152     first++;
1153   }
1154   for(first=page+1;first<last;first++) {
1155     invalidate_page(first);
1156   }
1157
1158   // Don't trap writes
1159   invalid_code[block]=1;
1160 #ifndef DISABLE_TLB
1161   // If there is a valid TLB entry for this page, remove write protect
1162   if(tlb_LUT_w[block]) {
1163     assert(tlb_LUT_r[block]==tlb_LUT_w[block]);
1164     // CHECK: Is this right?
1165     memory_map[block]=((tlb_LUT_w[block]&0xFFFFF000)-(block<<12)+(unsigned int)rdram-0x80000000)>>2;
1166     u_int real_block=tlb_LUT_w[block]>>12;
1167     invalid_code[real_block]=1;
1168     if(real_block>=0x80000&&real_block<0x80800) memory_map[real_block]=((u_int)rdram-0x80000000)>>2;
1169   }
1170   else if(block>=0x80000&&block<0x80800) memory_map[block]=((u_int)rdram-0x80000000)>>2;
1171 #endif
1172   #ifdef __arm__
1173   if(modified)
1174     __clear_cache((void *)BASE_ADDR,(void *)BASE_ADDR+(1<<TARGET_SIZE_2));
1175   #endif
1176   #ifdef USE_MINI_HT
1177   memset(mini_ht,-1,sizeof(mini_ht));
1178   #endif
1179 }
1180 void invalidate_addr(u_int addr)
1181 {
1182   invalidate_block(addr>>12);
1183 }
1184 void invalidate_all_pages()
1185 {
1186   u_int page,n;
1187   for(page=0;page<4096;page++)
1188     invalidate_page(page);
1189   for(page=0;page<1048576;page++)
1190     if(!invalid_code[page]) {
1191       restore_candidate[(page&2047)>>3]|=1<<(page&7);
1192       restore_candidate[((page&2047)>>3)+256]|=1<<(page&7);
1193     }
1194   #ifdef __arm__
1195   __clear_cache((void *)BASE_ADDR,(void *)BASE_ADDR+(1<<TARGET_SIZE_2));
1196   #endif
1197   #ifdef USE_MINI_HT
1198   memset(mini_ht,-1,sizeof(mini_ht));
1199   #endif
1200   #ifndef DISABLE_TLB
1201   // TLB
1202   for(page=0;page<0x100000;page++) {
1203     if(tlb_LUT_r[page]) {
1204       memory_map[page]=((tlb_LUT_r[page]&0xFFFFF000)-(page<<12)+(unsigned int)rdram-0x80000000)>>2;
1205       if(!tlb_LUT_w[page]||!invalid_code[page])
1206         memory_map[page]|=0x40000000; // Write protect
1207     }
1208     else memory_map[page]=-1;
1209     if(page==0x80000) page=0xC0000;
1210   }
1211   tlb_hacks();
1212   #endif
1213 }
1214
1215 // Add an entry to jump_out after making a link
1216 void add_link(u_int vaddr,void *src)
1217 {
1218   u_int page=get_page(vaddr);
1219   inv_debug("add_link: %x -> %x (%d)\n",(int)src,vaddr,page);
1220   ll_add(jump_out+page,vaddr,src);
1221   //int ptr=get_pointer(src);
1222   //inv_debug("add_link: Pointer is to %x\n",(int)ptr);
1223 }
1224
1225 // If a code block was found to be unmodified (bit was set in
1226 // restore_candidate) and it remains unmodified (bit is clear
1227 // in invalid_code) then move the entries for that 4K page from
1228 // the dirty list to the clean list.
1229 void clean_blocks(u_int page)
1230 {
1231   struct ll_entry *head;
1232   inv_debug("INV: clean_blocks page=%d\n",page);
1233   head=jump_dirty[page];
1234   while(head!=NULL) {
1235     if(!invalid_code[head->vaddr>>12]) {
1236       // Don't restore blocks which are about to expire from the cache
1237       if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1238         u_int start,end;
1239         if(verify_dirty((int)head->addr)) {
1240           //printf("Possibly Restore %x (%x)\n",head->vaddr, (int)head->addr);
1241           u_int i;
1242           u_int inv=0;
1243           get_bounds((int)head->addr,&start,&end);
1244           if(start-(u_int)rdram<0x800000) {
1245             for(i=(start-(u_int)rdram+0x80000000)>>12;i<=(end-1-(u_int)rdram+0x80000000)>>12;i++) {
1246               inv|=invalid_code[i];
1247             }
1248           }
1249           if((signed int)head->vaddr>=(signed int)0xC0000000) {
1250             u_int addr = (head->vaddr+(memory_map[head->vaddr>>12]<<2));
1251             //printf("addr=%x start=%x end=%x\n",addr,start,end);
1252             if(addr<start||addr>=end) inv=1;
1253           }
1254           else if((signed int)head->vaddr>=(signed int)0x80800000) {
1255             inv=1;
1256           }
1257           if(!inv) {
1258             void * clean_addr=(void *)get_clean_addr((int)head->addr);
1259             if((((u_int)clean_addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1260               u_int ppage=page;
1261 #ifndef DISABLE_TLB
1262               if(page<2048&&tlb_LUT_r[head->vaddr>>12]) ppage=(tlb_LUT_r[head->vaddr>>12]^0x80000000)>>12;
1263 #endif
1264               inv_debug("INV: Restored %x (%x/%x)\n",head->vaddr, (int)head->addr, (int)clean_addr);
1265               //printf("page=%x, addr=%x\n",page,head->vaddr);
1266               //assert(head->vaddr>>12==(page|0x80000));
1267               ll_add_32(jump_in+ppage,head->vaddr,head->reg32,clean_addr);
1268               int *ht_bin=hash_table[((head->vaddr>>16)^head->vaddr)&0xFFFF];
1269               if(!head->reg32) {
1270                 if(ht_bin[0]==head->vaddr) {
1271                   ht_bin[1]=(int)clean_addr; // Replace existing entry
1272                 }
1273                 if(ht_bin[2]==head->vaddr) {
1274                   ht_bin[3]=(int)clean_addr; // Replace existing entry
1275                 }
1276               }
1277             }
1278           }
1279         }
1280       }
1281     }
1282     head=head->next;
1283   }
1284 }
1285
1286
1287 void mov_alloc(struct regstat *current,int i)
1288 {
1289   // Note: Don't need to actually alloc the source registers
1290   if((~current->is32>>rs1[i])&1) {
1291     //alloc_reg64(current,i,rs1[i]);
1292     alloc_reg64(current,i,rt1[i]);
1293     current->is32&=~(1LL<<rt1[i]);
1294   } else {
1295     //alloc_reg(current,i,rs1[i]);
1296     alloc_reg(current,i,rt1[i]);
1297     current->is32|=(1LL<<rt1[i]);
1298   }
1299   clear_const(current,rs1[i]);
1300   clear_const(current,rt1[i]);
1301   dirty_reg(current,rt1[i]);
1302 }
1303
1304 void shiftimm_alloc(struct regstat *current,int i)
1305 {
1306   clear_const(current,rs1[i]);
1307   clear_const(current,rt1[i]);
1308   if(opcode2[i]<=0x3) // SLL/SRL/SRA
1309   {
1310     if(rt1[i]) {
1311       if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1312       else lt1[i]=rs1[i];
1313       alloc_reg(current,i,rt1[i]);
1314       current->is32|=1LL<<rt1[i];
1315       dirty_reg(current,rt1[i]);
1316     }
1317   }
1318   if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA
1319   {
1320     if(rt1[i]) {
1321       if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1322       alloc_reg64(current,i,rt1[i]);
1323       current->is32&=~(1LL<<rt1[i]);
1324       dirty_reg(current,rt1[i]);
1325     }
1326   }
1327   if(opcode2[i]==0x3c) // DSLL32
1328   {
1329     if(rt1[i]) {
1330       if(rs1[i]) alloc_reg(current,i,rs1[i]);
1331       alloc_reg64(current,i,rt1[i]);
1332       current->is32&=~(1LL<<rt1[i]);
1333       dirty_reg(current,rt1[i]);
1334     }
1335   }
1336   if(opcode2[i]==0x3e) // DSRL32
1337   {
1338     if(rt1[i]) {
1339       alloc_reg64(current,i,rs1[i]);
1340       if(imm[i]==32) {
1341         alloc_reg64(current,i,rt1[i]);
1342         current->is32&=~(1LL<<rt1[i]);
1343       } else {
1344         alloc_reg(current,i,rt1[i]);
1345         current->is32|=1LL<<rt1[i];
1346       }
1347       dirty_reg(current,rt1[i]);
1348     }
1349   }
1350   if(opcode2[i]==0x3f) // DSRA32
1351   {
1352     if(rt1[i]) {
1353       alloc_reg64(current,i,rs1[i]);
1354       alloc_reg(current,i,rt1[i]);
1355       current->is32|=1LL<<rt1[i];
1356       dirty_reg(current,rt1[i]);
1357     }
1358   }
1359 }
1360
1361 void shift_alloc(struct regstat *current,int i)
1362 {
1363   if(rt1[i]) {
1364     if(opcode2[i]<=0x07) // SLLV/SRLV/SRAV
1365     {
1366       if(rs1[i]) alloc_reg(current,i,rs1[i]);
1367       if(rs2[i]) alloc_reg(current,i,rs2[i]);
1368       alloc_reg(current,i,rt1[i]);
1369       if(rt1[i]==rs2[i]) alloc_reg_temp(current,i,-1);
1370       current->is32|=1LL<<rt1[i];
1371     } else { // DSLLV/DSRLV/DSRAV
1372       if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1373       if(rs2[i]) alloc_reg(current,i,rs2[i]);
1374       alloc_reg64(current,i,rt1[i]);
1375       current->is32&=~(1LL<<rt1[i]);
1376       if(opcode2[i]==0x16||opcode2[i]==0x17) // DSRLV and DSRAV need a temporary register
1377         alloc_reg_temp(current,i,-1);
1378     }
1379     clear_const(current,rs1[i]);
1380     clear_const(current,rs2[i]);
1381     clear_const(current,rt1[i]);
1382     dirty_reg(current,rt1[i]);
1383   }
1384 }
1385
1386 void alu_alloc(struct regstat *current,int i)
1387 {
1388   if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
1389     if(rt1[i]) {
1390       if(rs1[i]&&rs2[i]) {
1391         alloc_reg(current,i,rs1[i]);
1392         alloc_reg(current,i,rs2[i]);
1393       }
1394       else {
1395         if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1396         if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]);
1397       }
1398       alloc_reg(current,i,rt1[i]);
1399     }
1400     current->is32|=1LL<<rt1[i];
1401   }
1402   if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU
1403     if(rt1[i]) {
1404       if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1405       {
1406         alloc_reg64(current,i,rs1[i]);
1407         alloc_reg64(current,i,rs2[i]);
1408         alloc_reg(current,i,rt1[i]);
1409       } else {
1410         alloc_reg(current,i,rs1[i]);
1411         alloc_reg(current,i,rs2[i]);
1412         alloc_reg(current,i,rt1[i]);
1413       }
1414     }
1415     current->is32|=1LL<<rt1[i];
1416   }
1417   if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR
1418     if(rt1[i]) {
1419       if(rs1[i]&&rs2[i]) {
1420         alloc_reg(current,i,rs1[i]);
1421         alloc_reg(current,i,rs2[i]);
1422       }
1423       else
1424       {
1425         if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1426         if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]);
1427       }
1428       alloc_reg(current,i,rt1[i]);
1429       if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1430       {
1431         if(!((current->uu>>rt1[i])&1)) {
1432           alloc_reg64(current,i,rt1[i]);
1433         }
1434         if(get_reg(current->regmap,rt1[i]|64)>=0) {
1435           if(rs1[i]&&rs2[i]) {
1436             alloc_reg64(current,i,rs1[i]);
1437             alloc_reg64(current,i,rs2[i]);
1438           }
1439           else
1440           {
1441             // Is is really worth it to keep 64-bit values in registers?
1442             #ifdef NATIVE_64BIT
1443             if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]);
1444             if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg64(current,i,rs2[i]);
1445             #endif
1446           }
1447         }
1448         current->is32&=~(1LL<<rt1[i]);
1449       } else {
1450         current->is32|=1LL<<rt1[i];
1451       }
1452     }
1453   }
1454   if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU
1455     if(rt1[i]) {
1456       if(rs1[i]&&rs2[i]) {
1457         if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1458           alloc_reg64(current,i,rs1[i]);
1459           alloc_reg64(current,i,rs2[i]);
1460           alloc_reg64(current,i,rt1[i]);
1461         } else {
1462           alloc_reg(current,i,rs1[i]);
1463           alloc_reg(current,i,rs2[i]);
1464           alloc_reg(current,i,rt1[i]);
1465         }
1466       }
1467       else {
1468         alloc_reg(current,i,rt1[i]);
1469         if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1470           // DADD used as move, or zeroing
1471           // If we have a 64-bit source, then make the target 64 bits too
1472           if(rs1[i]&&!((current->is32>>rs1[i])&1)) {
1473             if(get_reg(current->regmap,rs1[i])>=0) alloc_reg64(current,i,rs1[i]);
1474             alloc_reg64(current,i,rt1[i]);
1475           } else if(rs2[i]&&!((current->is32>>rs2[i])&1)) {
1476             if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]);
1477             alloc_reg64(current,i,rt1[i]);
1478           }
1479           if(opcode2[i]>=0x2e&&rs2[i]) {
1480             // DSUB used as negation - 64-bit result
1481             // If we have a 32-bit register, extend it to 64 bits
1482             if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]);
1483             alloc_reg64(current,i,rt1[i]);
1484           }
1485         }
1486       }
1487       if(rs1[i]&&rs2[i]) {
1488         current->is32&=~(1LL<<rt1[i]);
1489       } else if(rs1[i]) {
1490         current->is32&=~(1LL<<rt1[i]);
1491         if((current->is32>>rs1[i])&1)
1492           current->is32|=1LL<<rt1[i];
1493       } else if(rs2[i]) {
1494         current->is32&=~(1LL<<rt1[i]);
1495         if((current->is32>>rs2[i])&1)
1496           current->is32|=1LL<<rt1[i];
1497       } else {
1498         current->is32|=1LL<<rt1[i];
1499       }
1500     }
1501   }
1502   clear_const(current,rs1[i]);
1503   clear_const(current,rs2[i]);
1504   clear_const(current,rt1[i]);
1505   dirty_reg(current,rt1[i]);
1506 }
1507
1508 void imm16_alloc(struct regstat *current,int i)
1509 {
1510   if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1511   else lt1[i]=rs1[i];
1512   if(rt1[i]) alloc_reg(current,i,rt1[i]);
1513   if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU
1514     current->is32&=~(1LL<<rt1[i]);
1515     if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1516       // TODO: Could preserve the 32-bit flag if the immediate is zero
1517       alloc_reg64(current,i,rt1[i]);
1518       alloc_reg64(current,i,rs1[i]);
1519     }
1520     clear_const(current,rs1[i]);
1521     clear_const(current,rt1[i]);
1522   }
1523   else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU
1524     if((~current->is32>>rs1[i])&1) alloc_reg64(current,i,rs1[i]);
1525     current->is32|=1LL<<rt1[i];
1526     clear_const(current,rs1[i]);
1527     clear_const(current,rt1[i]);
1528   }
1529   else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI
1530     if(((~current->is32>>rs1[i])&1)&&opcode[i]>0x0c) {
1531       if(rs1[i]!=rt1[i]) {
1532         if(needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]);
1533         alloc_reg64(current,i,rt1[i]);
1534         current->is32&=~(1LL<<rt1[i]);
1535       }
1536     }
1537     else current->is32|=1LL<<rt1[i]; // ANDI clears upper bits
1538     if(is_const(current,rs1[i])) {
1539       int v=get_const(current,rs1[i]);
1540       if(opcode[i]==0x0c) set_const(current,rt1[i],v&imm[i]);
1541       if(opcode[i]==0x0d) set_const(current,rt1[i],v|imm[i]);
1542       if(opcode[i]==0x0e) set_const(current,rt1[i],v^imm[i]);
1543     }
1544     else clear_const(current,rt1[i]);
1545   }
1546   else if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU
1547     if(is_const(current,rs1[i])) {
1548       int v=get_const(current,rs1[i]);
1549       set_const(current,rt1[i],v+imm[i]);
1550     }
1551     else clear_const(current,rt1[i]);
1552     current->is32|=1LL<<rt1[i];
1553   }
1554   else {
1555     set_const(current,rt1[i],((long long)((short)imm[i]))<<16); // LUI
1556     current->is32|=1LL<<rt1[i];
1557   }
1558   dirty_reg(current,rt1[i]);
1559 }
1560
1561 void load_alloc(struct regstat *current,int i)
1562 {
1563   clear_const(current,rt1[i]);
1564   //if(rs1[i]!=rt1[i]&&needed_again(rs1[i],i)) clear_const(current,rs1[i]); // Does this help or hurt?
1565   if(!rs1[i]) current->u&=~1LL; // Allow allocating r0 if it's the source register
1566   if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1567   if(rt1[i]) {
1568     alloc_reg(current,i,rt1[i]);
1569     if(opcode[i]==0x27||opcode[i]==0x37) // LWU/LD
1570     {
1571       current->is32&=~(1LL<<rt1[i]);
1572       alloc_reg64(current,i,rt1[i]);
1573     }
1574     else if(opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
1575     {
1576       current->is32&=~(1LL<<rt1[i]);
1577       alloc_reg64(current,i,rt1[i]);
1578       alloc_all(current,i);
1579       alloc_reg64(current,i,FTEMP);
1580     }
1581     else current->is32|=1LL<<rt1[i];
1582     dirty_reg(current,rt1[i]);
1583     // If using TLB, need a register for pointer to the mapping table
1584     if(using_tlb) alloc_reg(current,i,TLREG);
1585     // LWL/LWR need a temporary register for the old value
1586     if(opcode[i]==0x22||opcode[i]==0x26)
1587     {
1588       alloc_reg(current,i,FTEMP);
1589       alloc_reg_temp(current,i,-1);
1590     }
1591   }
1592   else
1593   {
1594     // Load to r0 (dummy load)
1595     // but we still need a register to calculate the address
1596     alloc_reg_temp(current,i,-1);
1597   }
1598 }
1599
1600 void store_alloc(struct regstat *current,int i)
1601 {
1602   clear_const(current,rs2[i]);
1603   if(!(rs2[i])) current->u&=~1LL; // Allow allocating r0 if necessary
1604   if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1605   alloc_reg(current,i,rs2[i]);
1606   if(opcode[i]==0x2c||opcode[i]==0x2d||opcode[i]==0x3f) { // 64-bit SDL/SDR/SD
1607     alloc_reg64(current,i,rs2[i]);
1608     if(rs2[i]) alloc_reg(current,i,FTEMP);
1609   }
1610   // If using TLB, need a register for pointer to the mapping table
1611   if(using_tlb) alloc_reg(current,i,TLREG);
1612   #if defined(HOST_IMM8)
1613   // On CPUs without 32-bit immediates we need a pointer to invalid_code
1614   else alloc_reg(current,i,INVCP);
1615   #endif
1616   if(opcode[i]==0x2c||opcode[i]==0x2d) { // 64-bit SDL/SDR
1617     alloc_reg(current,i,FTEMP);
1618   }
1619   // We need a temporary register for address generation
1620   alloc_reg_temp(current,i,-1);
1621 }
1622
1623 void c1ls_alloc(struct regstat *current,int i)
1624 {
1625   //clear_const(current,rs1[i]); // FIXME
1626   clear_const(current,rt1[i]);
1627   if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1628   alloc_reg(current,i,CSREG); // Status
1629   alloc_reg(current,i,FTEMP);
1630   if(opcode[i]==0x35||opcode[i]==0x3d) { // 64-bit LDC1/SDC1
1631     alloc_reg64(current,i,FTEMP);
1632   }
1633   // If using TLB, need a register for pointer to the mapping table
1634   if(using_tlb) alloc_reg(current,i,TLREG);
1635   #if defined(HOST_IMM8)
1636   // On CPUs without 32-bit immediates we need a pointer to invalid_code
1637   else if((opcode[i]&0x3b)==0x39) // SWC1/SDC1
1638     alloc_reg(current,i,INVCP);
1639   #endif
1640   // We need a temporary register for address generation
1641   alloc_reg_temp(current,i,-1);
1642 }
1643
1644 #ifndef multdiv_alloc
1645 void multdiv_alloc(struct regstat *current,int i)
1646 {
1647   //  case 0x18: MULT
1648   //  case 0x19: MULTU
1649   //  case 0x1A: DIV
1650   //  case 0x1B: DIVU
1651   //  case 0x1C: DMULT
1652   //  case 0x1D: DMULTU
1653   //  case 0x1E: DDIV
1654   //  case 0x1F: DDIVU
1655   clear_const(current,rs1[i]);
1656   clear_const(current,rs2[i]);
1657   if(rs1[i]&&rs2[i])
1658   {
1659     if((opcode2[i]&4)==0) // 32-bit
1660     {
1661       current->u&=~(1LL<<HIREG);
1662       current->u&=~(1LL<<LOREG);
1663       alloc_reg(current,i,HIREG);
1664       alloc_reg(current,i,LOREG);
1665       alloc_reg(current,i,rs1[i]);
1666       alloc_reg(current,i,rs2[i]);
1667       current->is32|=1LL<<HIREG;
1668       current->is32|=1LL<<LOREG;
1669       dirty_reg(current,HIREG);
1670       dirty_reg(current,LOREG);
1671     }
1672     else // 64-bit
1673     {
1674       current->u&=~(1LL<<HIREG);
1675       current->u&=~(1LL<<LOREG);
1676       current->uu&=~(1LL<<HIREG);
1677       current->uu&=~(1LL<<LOREG);
1678       alloc_reg64(current,i,HIREG);
1679       //if(HOST_REGS>10) alloc_reg64(current,i,LOREG);
1680       alloc_reg64(current,i,rs1[i]);
1681       alloc_reg64(current,i,rs2[i]);
1682       alloc_all(current,i);
1683       current->is32&=~(1LL<<HIREG);
1684       current->is32&=~(1LL<<LOREG);
1685       dirty_reg(current,HIREG);
1686       dirty_reg(current,LOREG);
1687     }
1688   }
1689   else
1690   {
1691     // Multiply by zero is zero.
1692     // MIPS does not have a divide by zero exception.
1693     // The result is undefined, we return zero.
1694     alloc_reg(current,i,HIREG);
1695     alloc_reg(current,i,LOREG);
1696     current->is32|=1LL<<HIREG;
1697     current->is32|=1LL<<LOREG;
1698     dirty_reg(current,HIREG);
1699     dirty_reg(current,LOREG);
1700   }
1701 }
1702 #endif
1703
1704 void cop0_alloc(struct regstat *current,int i)
1705 {
1706   if(opcode2[i]==0) // MFC0
1707   {
1708     if(rt1[i]) {
1709       clear_const(current,rt1[i]);
1710       alloc_all(current,i);
1711       alloc_reg(current,i,rt1[i]);
1712       current->is32|=1LL<<rt1[i];
1713       dirty_reg(current,rt1[i]);
1714     }
1715   }
1716   else if(opcode2[i]==4) // MTC0
1717   {
1718     if(rs1[i]){
1719       clear_const(current,rs1[i]);
1720       alloc_reg(current,i,rs1[i]);
1721       alloc_all(current,i);
1722     }
1723     else {
1724       alloc_all(current,i); // FIXME: Keep r0
1725       current->u&=~1LL;
1726       alloc_reg(current,i,0);
1727     }
1728   }
1729   else
1730   {
1731     // TLBR/TLBWI/TLBWR/TLBP/ERET
1732     assert(opcode2[i]==0x10);
1733     alloc_all(current,i);
1734   }
1735 }
1736
1737 void cop1_alloc(struct regstat *current,int i)
1738 {
1739   alloc_reg(current,i,CSREG); // Load status
1740   if(opcode2[i]<3) // MFC1/DMFC1/CFC1
1741   {
1742     assert(rt1[i]);
1743     clear_const(current,rt1[i]);
1744     if(opcode2[i]==1) {
1745       alloc_reg64(current,i,rt1[i]); // DMFC1
1746       current->is32&=~(1LL<<rt1[i]);
1747     }else{
1748       alloc_reg(current,i,rt1[i]); // MFC1/CFC1
1749       current->is32|=1LL<<rt1[i];
1750     }
1751     dirty_reg(current,rt1[i]);
1752     alloc_reg_temp(current,i,-1);
1753   }
1754   else if(opcode2[i]>3) // MTC1/DMTC1/CTC1
1755   {
1756     if(rs1[i]){
1757       clear_const(current,rs1[i]);
1758       if(opcode2[i]==5)
1759         alloc_reg64(current,i,rs1[i]); // DMTC1
1760       else
1761         alloc_reg(current,i,rs1[i]); // MTC1/CTC1
1762       alloc_reg_temp(current,i,-1);
1763     }
1764     else {
1765       current->u&=~1LL;
1766       alloc_reg(current,i,0);
1767       alloc_reg_temp(current,i,-1);
1768     }
1769   }
1770 }
1771 void fconv_alloc(struct regstat *current,int i)
1772 {
1773   alloc_reg(current,i,CSREG); // Load status
1774   alloc_reg_temp(current,i,-1);
1775 }
1776 void float_alloc(struct regstat *current,int i)
1777 {
1778   alloc_reg(current,i,CSREG); // Load status
1779   alloc_reg_temp(current,i,-1);
1780 }
1781 void fcomp_alloc(struct regstat *current,int i)
1782 {
1783   alloc_reg(current,i,CSREG); // Load status
1784   alloc_reg(current,i,FSREG); // Load flags
1785   dirty_reg(current,FSREG); // Flag will be modified
1786   alloc_reg_temp(current,i,-1);
1787 }
1788
1789 void syscall_alloc(struct regstat *current,int i)
1790 {
1791   alloc_cc(current,i);
1792   dirty_reg(current,CCREG);
1793   alloc_all(current,i);
1794   current->isconst=0;
1795 }
1796
1797 void delayslot_alloc(struct regstat *current,int i)
1798 {
1799   switch(itype[i]) {
1800     case UJUMP:
1801     case CJUMP:
1802     case SJUMP:
1803     case RJUMP:
1804     case FJUMP:
1805     case SYSCALL:
1806     case SPAN:
1807       assem_debug("jump in the delay slot.  this shouldn't happen.\n");//exit(1);
1808       printf("Disabled speculative precompilation\n");
1809       stop_after_jal=1;
1810       break;
1811     case IMM16:
1812       imm16_alloc(current,i);
1813       break;
1814     case LOAD:
1815     case LOADLR:
1816       load_alloc(current,i);
1817       break;
1818     case STORE:
1819     case STORELR:
1820       store_alloc(current,i);
1821       break;
1822     case ALU:
1823       alu_alloc(current,i);
1824       break;
1825     case SHIFT:
1826       shift_alloc(current,i);
1827       break;
1828     case MULTDIV:
1829       multdiv_alloc(current,i);
1830       break;
1831     case SHIFTIMM:
1832       shiftimm_alloc(current,i);
1833       break;
1834     case MOV:
1835       mov_alloc(current,i);
1836       break;
1837     case COP0:
1838       cop0_alloc(current,i);
1839       break;
1840     case COP1:
1841       cop1_alloc(current,i);
1842       break;
1843     case C1LS:
1844       c1ls_alloc(current,i);
1845       break;
1846     case FCONV:
1847       fconv_alloc(current,i);
1848       break;
1849     case FLOAT:
1850       float_alloc(current,i);
1851       break;
1852     case FCOMP:
1853       fcomp_alloc(current,i);
1854       break;
1855   }
1856 }
1857
1858 // Special case where a branch and delay slot span two pages in virtual memory
1859 static void pagespan_alloc(struct regstat *current,int i)
1860 {
1861   current->isconst=0;
1862   current->wasconst=0;
1863   regs[i].wasconst=0;
1864   alloc_all(current,i);
1865   alloc_cc(current,i);
1866   dirty_reg(current,CCREG);
1867   if(opcode[i]==3) // JAL
1868   {
1869     alloc_reg(current,i,31);
1870     dirty_reg(current,31);
1871   }
1872   if(opcode[i]==0&&(opcode2[i]&0x3E)==8) // JR/JALR
1873   {
1874     alloc_reg(current,i,rs1[i]);
1875     if (rt1[i]==31) {
1876       alloc_reg(current,i,31);
1877       dirty_reg(current,31);
1878     }
1879   }
1880   if((opcode[i]&0x2E)==4) // BEQ/BNE/BEQL/BNEL
1881   {
1882     if(rs1[i]) alloc_reg(current,i,rs1[i]);
1883     if(rs2[i]) alloc_reg(current,i,rs2[i]);
1884     if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1885     {
1886       if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1887       if(rs2[i]) alloc_reg64(current,i,rs2[i]);
1888     }
1889   }
1890   else
1891   if((opcode[i]&0x2E)==6) // BLEZ/BGTZ/BLEZL/BGTZL
1892   {
1893     if(rs1[i]) alloc_reg(current,i,rs1[i]);
1894     if(!((current->is32>>rs1[i])&1))
1895     {
1896       if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1897     }
1898   }
1899   else
1900   if(opcode[i]==0x11) // BC1
1901   {
1902     alloc_reg(current,i,FSREG);
1903     alloc_reg(current,i,CSREG);
1904   }
1905   //else ...
1906 }
1907
1908 add_stub(int type,int addr,int retaddr,int a,int b,int c,int d,int e)
1909 {
1910   stubs[stubcount][0]=type;
1911   stubs[stubcount][1]=addr;
1912   stubs[stubcount][2]=retaddr;
1913   stubs[stubcount][3]=a;
1914   stubs[stubcount][4]=b;
1915   stubs[stubcount][5]=c;
1916   stubs[stubcount][6]=d;
1917   stubs[stubcount][7]=e;
1918   stubcount++;
1919 }
1920
1921 // Write out a single register
1922 void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32)
1923 {
1924   int hr;
1925   for(hr=0;hr<HOST_REGS;hr++) {
1926     if(hr!=EXCLUDE_REG) {
1927       if((regmap[hr]&63)==r) {
1928         if((dirty>>hr)&1) {
1929           if(regmap[hr]<64) {
1930             emit_storereg(r,hr);
1931             if((is32>>regmap[hr])&1) {
1932               emit_sarimm(hr,31,hr);
1933               emit_storereg(r|64,hr);
1934             }
1935           }else{
1936             emit_storereg(r|64,hr);
1937           }
1938         }
1939       }
1940     }
1941   }
1942 }
1943
1944 int mchecksum()
1945 {
1946   //if(!tracedebug) return 0;
1947   int i;
1948   int sum=0;
1949   for(i=0;i<2097152;i++) {
1950     unsigned int temp=sum;
1951     sum<<=1;
1952     sum|=(~temp)>>31;
1953     sum^=((u_int *)rdram)[i];
1954   }
1955   return sum;
1956 }
1957 int rchecksum()
1958 {
1959   int i;
1960   int sum=0;
1961   for(i=0;i<64;i++)
1962     sum^=((u_int *)reg)[i];
1963   return sum;
1964 }
1965 void rlist()
1966 {
1967   int i;
1968   printf("TRACE: ");
1969   for(i=0;i<32;i++)
1970     printf("r%d:%8x%8x ",i,((int *)(reg+i))[1],((int *)(reg+i))[0]);
1971   printf("\n");
1972 #ifndef DISABLE_COP1
1973   printf("TRACE: ");
1974   for(i=0;i<32;i++)
1975     printf("f%d:%8x%8x ",i,((int*)reg_cop1_simple[i])[1],*((int*)reg_cop1_simple[i]));
1976   printf("\n");
1977 #endif
1978 }
1979
1980 void enabletrace()
1981 {
1982   tracedebug=1;
1983 }
1984
1985 void memdebug(int i)
1986 {
1987   //printf("TRACE: count=%d next=%d (checksum %x) lo=%8x%8x\n",Count,next_interupt,mchecksum(),(int)(reg[LOREG]>>32),(int)reg[LOREG]);
1988   //printf("TRACE: count=%d next=%d (rchecksum %x)\n",Count,next_interupt,rchecksum());
1989   //rlist();
1990   //if(tracedebug) {
1991   //if(Count>=-2084597794) {
1992   if((signed int)Count>=-2084597794&&(signed int)Count<0) {
1993   //if(0) {
1994     printf("TRACE: count=%d next=%d (checksum %x)\n",Count,next_interupt,mchecksum());
1995     //printf("TRACE: count=%d next=%d (checksum %x) Status=%x\n",Count,next_interupt,mchecksum(),Status);
1996     //printf("TRACE: count=%d next=%d (checksum %x) hi=%8x%8x\n",Count,next_interupt,mchecksum(),(int)(reg[HIREG]>>32),(int)reg[HIREG]);
1997     rlist();
1998     #ifdef __i386__
1999     printf("TRACE: %x\n",(&i)[-1]);
2000     #endif
2001     #ifdef __arm__
2002     int j;
2003     printf("TRACE: %x \n",(&j)[10]);
2004     printf("TRACE: %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x\n",(&j)[1],(&j)[2],(&j)[3],(&j)[4],(&j)[5],(&j)[6],(&j)[7],(&j)[8],(&j)[9],(&j)[10],(&j)[11],(&j)[12],(&j)[13],(&j)[14],(&j)[15],(&j)[16],(&j)[17],(&j)[18],(&j)[19],(&j)[20]);
2005     #endif
2006     //fflush(stdout);
2007   }
2008   //printf("TRACE: %x\n",(&i)[-1]);
2009 }
2010
2011 void tlb_debug(u_int cause, u_int addr, u_int iaddr)
2012 {
2013   printf("TLB Exception: instruction=%x addr=%x cause=%x\n",iaddr, addr, cause);
2014 }
2015
2016 void alu_assemble(int i,struct regstat *i_regs)
2017 {
2018   if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
2019     if(rt1[i]) {
2020       signed char s1,s2,t;
2021       t=get_reg(i_regs->regmap,rt1[i]);
2022       if(t>=0) {
2023         s1=get_reg(i_regs->regmap,rs1[i]);
2024         s2=get_reg(i_regs->regmap,rs2[i]);
2025         if(rs1[i]&&rs2[i]) {
2026           assert(s1>=0);
2027           assert(s2>=0);
2028           if(opcode2[i]&2) emit_sub(s1,s2,t);
2029           else emit_add(s1,s2,t);
2030         }
2031         else if(rs1[i]) {
2032           if(s1>=0) emit_mov(s1,t);
2033           else emit_loadreg(rs1[i],t);
2034         }
2035         else if(rs2[i]) {
2036           if(s2>=0) {
2037             if(opcode2[i]&2) emit_neg(s2,t);
2038             else emit_mov(s2,t);
2039           }
2040           else {
2041             emit_loadreg(rs2[i],t);
2042             if(opcode2[i]&2) emit_neg(t,t);
2043           }
2044         }
2045         else emit_zeroreg(t);
2046       }
2047     }
2048   }
2049   if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU
2050     if(rt1[i]) {
2051       signed char s1l,s2l,s1h,s2h,tl,th;
2052       tl=get_reg(i_regs->regmap,rt1[i]);
2053       th=get_reg(i_regs->regmap,rt1[i]|64);
2054       if(tl>=0) {
2055         s1l=get_reg(i_regs->regmap,rs1[i]);
2056         s2l=get_reg(i_regs->regmap,rs2[i]);
2057         s1h=get_reg(i_regs->regmap,rs1[i]|64);
2058         s2h=get_reg(i_regs->regmap,rs2[i]|64);
2059         if(rs1[i]&&rs2[i]) {
2060           assert(s1l>=0);
2061           assert(s2l>=0);
2062           if(opcode2[i]&2) emit_subs(s1l,s2l,tl);
2063           else emit_adds(s1l,s2l,tl);
2064           if(th>=0) {
2065             #ifdef INVERTED_CARRY
2066             if(opcode2[i]&2) {if(s1h!=th) emit_mov(s1h,th);emit_sbb(th,s2h);}
2067             #else
2068             if(opcode2[i]&2) emit_sbc(s1h,s2h,th);
2069             #endif
2070             else emit_add(s1h,s2h,th);
2071           }
2072         }
2073         else if(rs1[i]) {
2074           if(s1l>=0) emit_mov(s1l,tl);
2075           else emit_loadreg(rs1[i],tl);
2076           if(th>=0) {
2077             if(s1h>=0) emit_mov(s1h,th);
2078             else emit_loadreg(rs1[i]|64,th);
2079           }
2080         }
2081         else if(rs2[i]) {
2082           if(s2l>=0) {
2083             if(opcode2[i]&2) emit_negs(s2l,tl);
2084             else emit_mov(s2l,tl);
2085           }
2086           else {
2087             emit_loadreg(rs2[i],tl);
2088             if(opcode2[i]&2) emit_negs(tl,tl);
2089           }
2090           if(th>=0) {
2091             #ifdef INVERTED_CARRY
2092             if(s2h>=0) emit_mov(s2h,th);
2093             else emit_loadreg(rs2[i]|64,th);
2094             if(opcode2[i]&2) {
2095               emit_adcimm(-1,th); // x86 has inverted carry flag
2096               emit_not(th,th);
2097             }
2098             #else
2099             if(opcode2[i]&2) {
2100               if(s2h>=0) emit_rscimm(s2h,0,th);
2101               else {
2102                 emit_loadreg(rs2[i]|64,th);
2103                 emit_rscimm(th,0,th);
2104               }
2105             }else{
2106               if(s2h>=0) emit_mov(s2h,th);
2107               else emit_loadreg(rs2[i]|64,th);
2108             }
2109             #endif
2110           }
2111         }
2112         else {
2113           emit_zeroreg(tl);
2114           if(th>=0) emit_zeroreg(th);
2115         }
2116       }
2117     }
2118   }
2119   if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU
2120     if(rt1[i]) {
2121       signed char s1l,s1h,s2l,s2h,t;
2122       if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1))
2123       {
2124         t=get_reg(i_regs->regmap,rt1[i]);
2125         //assert(t>=0);
2126         if(t>=0) {
2127           s1l=get_reg(i_regs->regmap,rs1[i]);
2128           s1h=get_reg(i_regs->regmap,rs1[i]|64);
2129           s2l=get_reg(i_regs->regmap,rs2[i]);
2130           s2h=get_reg(i_regs->regmap,rs2[i]|64);
2131           if(rs2[i]==0) // rx<r0
2132           {
2133             assert(s1h>=0);
2134             if(opcode2[i]==0x2a) // SLT
2135               emit_shrimm(s1h,31,t);
2136             else // SLTU (unsigned can not be less than zero)
2137               emit_zeroreg(t);
2138           }
2139           else if(rs1[i]==0) // r0<rx
2140           {
2141             assert(s2h>=0);
2142             if(opcode2[i]==0x2a) // SLT
2143               emit_set_gz64_32(s2h,s2l,t);
2144             else // SLTU (set if not zero)
2145               emit_set_nz64_32(s2h,s2l,t);
2146           }
2147           else {
2148             assert(s1l>=0);assert(s1h>=0);
2149             assert(s2l>=0);assert(s2h>=0);
2150             if(opcode2[i]==0x2a) // SLT
2151               emit_set_if_less64_32(s1h,s1l,s2h,s2l,t);
2152             else // SLTU
2153               emit_set_if_carry64_32(s1h,s1l,s2h,s2l,t);
2154           }
2155         }
2156       } else {
2157         t=get_reg(i_regs->regmap,rt1[i]);
2158         //assert(t>=0);
2159         if(t>=0) {
2160           s1l=get_reg(i_regs->regmap,rs1[i]);
2161           s2l=get_reg(i_regs->regmap,rs2[i]);
2162           if(rs2[i]==0) // rx<r0
2163           {
2164             assert(s1l>=0);
2165             if(opcode2[i]==0x2a) // SLT
2166               emit_shrimm(s1l,31,t);
2167             else // SLTU (unsigned can not be less than zero)
2168               emit_zeroreg(t);
2169           }
2170           else if(rs1[i]==0) // r0<rx
2171           {
2172             assert(s2l>=0);
2173             if(opcode2[i]==0x2a) // SLT
2174               emit_set_gz32(s2l,t);
2175             else // SLTU (set if not zero)
2176               emit_set_nz32(s2l,t);
2177           }
2178           else{
2179             assert(s1l>=0);assert(s2l>=0);
2180             if(opcode2[i]==0x2a) // SLT
2181               emit_set_if_less32(s1l,s2l,t);
2182             else // SLTU
2183               emit_set_if_carry32(s1l,s2l,t);
2184           }
2185         }
2186       }
2187     }
2188   }
2189   if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR
2190     if(rt1[i]) {
2191       signed char s1l,s1h,s2l,s2h,th,tl;
2192       tl=get_reg(i_regs->regmap,rt1[i]);
2193       th=get_reg(i_regs->regmap,rt1[i]|64);
2194       if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1)&&th>=0)
2195       {
2196         assert(tl>=0);
2197         if(tl>=0) {
2198           s1l=get_reg(i_regs->regmap,rs1[i]);
2199           s1h=get_reg(i_regs->regmap,rs1[i]|64);
2200           s2l=get_reg(i_regs->regmap,rs2[i]);
2201           s2h=get_reg(i_regs->regmap,rs2[i]|64);
2202           if(rs1[i]&&rs2[i]) {
2203             assert(s1l>=0);assert(s1h>=0);
2204             assert(s2l>=0);assert(s2h>=0);
2205             if(opcode2[i]==0x24) { // AND
2206               emit_and(s1l,s2l,tl);
2207               emit_and(s1h,s2h,th);
2208             } else
2209             if(opcode2[i]==0x25) { // OR
2210               emit_or(s1l,s2l,tl);
2211               emit_or(s1h,s2h,th);
2212             } else
2213             if(opcode2[i]==0x26) { // XOR
2214               emit_xor(s1l,s2l,tl);
2215               emit_xor(s1h,s2h,th);
2216             } else
2217             if(opcode2[i]==0x27) { // NOR
2218               emit_or(s1l,s2l,tl);
2219               emit_or(s1h,s2h,th);
2220               emit_not(tl,tl);
2221               emit_not(th,th);
2222             }
2223           }
2224           else
2225           {
2226             if(opcode2[i]==0x24) { // AND
2227               emit_zeroreg(tl);
2228               emit_zeroreg(th);
2229             } else
2230             if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR
2231               if(rs1[i]){
2232                 if(s1l>=0) emit_mov(s1l,tl);
2233                 else emit_loadreg(rs1[i],tl);
2234                 if(s1h>=0) emit_mov(s1h,th);
2235                 else emit_loadreg(rs1[i]|64,th);
2236               }
2237               else
2238               if(rs2[i]){
2239                 if(s2l>=0) emit_mov(s2l,tl);
2240                 else emit_loadreg(rs2[i],tl);
2241                 if(s2h>=0) emit_mov(s2h,th);
2242                 else emit_loadreg(rs2[i]|64,th);
2243               }
2244               else{
2245                 emit_zeroreg(tl);
2246                 emit_zeroreg(th);
2247               }
2248             } else
2249             if(opcode2[i]==0x27) { // NOR
2250               if(rs1[i]){
2251                 if(s1l>=0) emit_not(s1l,tl);
2252                 else{
2253                   emit_loadreg(rs1[i],tl);
2254                   emit_not(tl,tl);
2255                 }
2256                 if(s1h>=0) emit_not(s1h,th);
2257                 else{
2258                   emit_loadreg(rs1[i]|64,th);
2259                   emit_not(th,th);
2260                 }
2261               }
2262               else
2263               if(rs2[i]){
2264                 if(s2l>=0) emit_not(s2l,tl);
2265                 else{
2266                   emit_loadreg(rs2[i],tl);
2267                   emit_not(tl,tl);
2268                 }
2269                 if(s2h>=0) emit_not(s2h,th);
2270                 else{
2271                   emit_loadreg(rs2[i]|64,th);
2272                   emit_not(th,th);
2273                 }
2274               }
2275               else {
2276                 emit_movimm(-1,tl);
2277                 emit_movimm(-1,th);
2278               }
2279             }
2280           }
2281         }
2282       }
2283       else
2284       {
2285         // 32 bit
2286         if(tl>=0) {
2287           s1l=get_reg(i_regs->regmap,rs1[i]);
2288           s2l=get_reg(i_regs->regmap,rs2[i]);
2289           if(rs1[i]&&rs2[i]) {
2290             assert(s1l>=0);
2291             assert(s2l>=0);
2292             if(opcode2[i]==0x24) { // AND
2293               emit_and(s1l,s2l,tl);
2294             } else
2295             if(opcode2[i]==0x25) { // OR
2296               emit_or(s1l,s2l,tl);
2297             } else
2298             if(opcode2[i]==0x26) { // XOR
2299               emit_xor(s1l,s2l,tl);
2300             } else
2301             if(opcode2[i]==0x27) { // NOR
2302               emit_or(s1l,s2l,tl);
2303               emit_not(tl,tl);
2304             }
2305           }
2306           else
2307           {
2308             if(opcode2[i]==0x24) { // AND
2309               emit_zeroreg(tl);
2310             } else
2311             if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR
2312               if(rs1[i]){
2313                 if(s1l>=0) emit_mov(s1l,tl);
2314                 else emit_loadreg(rs1[i],tl); // CHECK: regmap_entry?
2315               }
2316               else
2317               if(rs2[i]){
2318                 if(s2l>=0) emit_mov(s2l,tl);
2319                 else emit_loadreg(rs2[i],tl); // CHECK: regmap_entry?
2320               }
2321               else emit_zeroreg(tl);
2322             } else
2323             if(opcode2[i]==0x27) { // NOR
2324               if(rs1[i]){
2325                 if(s1l>=0) emit_not(s1l,tl);
2326                 else {
2327                   emit_loadreg(rs1[i],tl);
2328                   emit_not(tl,tl);
2329                 }
2330               }
2331               else
2332               if(rs2[i]){
2333                 if(s2l>=0) emit_not(s2l,tl);
2334                 else {
2335                   emit_loadreg(rs2[i],tl);
2336                   emit_not(tl,tl);
2337                 }
2338               }
2339               else emit_movimm(-1,tl);
2340             }
2341           }
2342         }
2343       }
2344     }
2345   }
2346 }
2347
2348 void imm16_assemble(int i,struct regstat *i_regs)
2349 {
2350   if (opcode[i]==0x0f) { // LUI
2351     if(rt1[i]) {
2352       signed char t;
2353       t=get_reg(i_regs->regmap,rt1[i]);
2354       //assert(t>=0);
2355       if(t>=0) {
2356         if(!((i_regs->isconst>>t)&1))
2357           emit_movimm(imm[i]<<16,t);
2358       }
2359     }
2360   }
2361   if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU
2362     if(rt1[i]) {
2363       signed char s,t;
2364       t=get_reg(i_regs->regmap,rt1[i]);
2365       s=get_reg(i_regs->regmap,rs1[i]);
2366       if(rs1[i]) {
2367         //assert(t>=0);
2368         //assert(s>=0);
2369         if(t>=0) {
2370           if(!((i_regs->isconst>>t)&1)) {
2371             if(s<0) {
2372               if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2373               emit_addimm(t,imm[i],t);
2374             }else{
2375               if(!((i_regs->wasconst>>s)&1))
2376                 emit_addimm(s,imm[i],t);
2377               else
2378                 emit_movimm(constmap[i][s]+imm[i],t);
2379             }
2380           }
2381         }
2382       } else {
2383         if(t>=0) {
2384           if(!((i_regs->isconst>>t)&1))
2385             emit_movimm(imm[i],t);
2386         }
2387       }
2388     }
2389   }
2390   if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU
2391     if(rt1[i]) {
2392       signed char sh,sl,th,tl;
2393       th=get_reg(i_regs->regmap,rt1[i]|64);
2394       tl=get_reg(i_regs->regmap,rt1[i]);
2395       sh=get_reg(i_regs->regmap,rs1[i]|64);
2396       sl=get_reg(i_regs->regmap,rs1[i]);
2397       if(tl>=0) {
2398         if(rs1[i]) {
2399           assert(sh>=0);
2400           assert(sl>=0);
2401           if(th>=0) {
2402             emit_addimm64_32(sh,sl,imm[i],th,tl);
2403           }
2404           else {
2405             emit_addimm(sl,imm[i],tl);
2406           }
2407         } else {
2408           emit_movimm(imm[i],tl);
2409           if(th>=0) emit_movimm(((signed int)imm[i])>>31,th);
2410         }
2411       }
2412     }
2413   }
2414   else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU
2415     if(rt1[i]) {
2416       //assert(rs1[i]!=0); // r0 might be valid, but it's probably a bug
2417       signed char sh,sl,t;
2418       t=get_reg(i_regs->regmap,rt1[i]);
2419       sh=get_reg(i_regs->regmap,rs1[i]|64);
2420       sl=get_reg(i_regs->regmap,rs1[i]);
2421       //assert(t>=0);
2422       if(t>=0) {
2423         if(rs1[i]>0) {
2424           if(sh<0) assert((i_regs->was32>>rs1[i])&1);
2425           if(sh<0||((i_regs->was32>>rs1[i])&1)) {
2426             if(opcode[i]==0x0a) { // SLTI
2427               if(sl<0) {
2428                 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2429                 emit_slti32(t,imm[i],t);
2430               }else{
2431                 emit_slti32(sl,imm[i],t);
2432               }
2433             }
2434             else { // SLTIU
2435               if(sl<0) {
2436                 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2437                 emit_sltiu32(t,imm[i],t);
2438               }else{
2439                 emit_sltiu32(sl,imm[i],t);
2440               }
2441             }
2442           }else{ // 64-bit
2443             assert(sl>=0);
2444             if(opcode[i]==0x0a) // SLTI
2445               emit_slti64_32(sh,sl,imm[i],t);
2446             else // SLTIU
2447               emit_sltiu64_32(sh,sl,imm[i],t);
2448           }
2449         }else{
2450           // SLTI(U) with r0 is just stupid,
2451           // nonetheless examples can be found
2452           if(opcode[i]==0x0a) // SLTI
2453             if(0<imm[i]) emit_movimm(1,t);
2454             else emit_zeroreg(t);
2455           else // SLTIU
2456           {
2457             if(imm[i]) emit_movimm(1,t);
2458             else emit_zeroreg(t);
2459           }
2460         }
2461       }
2462     }
2463   }
2464   else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI
2465     if(rt1[i]) {
2466       signed char sh,sl,th,tl;
2467       th=get_reg(i_regs->regmap,rt1[i]|64);
2468       tl=get_reg(i_regs->regmap,rt1[i]);
2469       sh=get_reg(i_regs->regmap,rs1[i]|64);
2470       sl=get_reg(i_regs->regmap,rs1[i]);
2471       if(tl>=0 && !((i_regs->isconst>>tl)&1)) {
2472         if(opcode[i]==0x0c) //ANDI
2473         {
2474           if(rs1[i]) {
2475             if(sl<0) {
2476               if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl);
2477               emit_andimm(tl,imm[i],tl);
2478             }else{
2479               if(!((i_regs->wasconst>>sl)&1))
2480                 emit_andimm(sl,imm[i],tl);
2481               else
2482                 emit_movimm(constmap[i][sl]&imm[i],tl);
2483             }
2484           }
2485           else
2486             emit_zeroreg(tl);
2487           if(th>=0) emit_zeroreg(th);
2488         }
2489         else
2490         {
2491           if(rs1[i]) {
2492             if(sl<0) {
2493               if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl);
2494             }
2495             if(th>=0) {
2496               if(sh<0) {
2497                 emit_loadreg(rs1[i]|64,th);
2498               }else{
2499                 emit_mov(sh,th);
2500               }
2501             }
2502             if(opcode[i]==0x0d) //ORI
2503             if(sl<0) {
2504               emit_orimm(tl,imm[i],tl);
2505             }else{
2506               if(!((i_regs->wasconst>>sl)&1))
2507                 emit_orimm(sl,imm[i],tl);
2508               else
2509                 emit_movimm(constmap[i][sl]|imm[i],tl);
2510             }
2511             if(opcode[i]==0x0e) //XORI
2512             if(sl<0) {
2513               emit_xorimm(tl,imm[i],tl);
2514             }else{
2515               if(!((i_regs->wasconst>>sl)&1))
2516                 emit_xorimm(sl,imm[i],tl);
2517               else
2518                 emit_movimm(constmap[i][sl]^imm[i],tl);
2519             }
2520           }
2521           else {
2522             emit_movimm(imm[i],tl);
2523             if(th>=0) emit_zeroreg(th);
2524           }
2525         }
2526       }
2527     }
2528   }
2529 }
2530
2531 void shiftimm_assemble(int i,struct regstat *i_regs)
2532 {
2533   if(opcode2[i]<=0x3) // SLL/SRL/SRA
2534   {
2535     if(rt1[i]) {
2536       signed char s,t;
2537       t=get_reg(i_regs->regmap,rt1[i]);
2538       s=get_reg(i_regs->regmap,rs1[i]);
2539       //assert(t>=0);
2540       if(t>=0){
2541         if(rs1[i]==0)
2542         {
2543           emit_zeroreg(t);
2544         }
2545         else
2546         {
2547           if(s<0&&i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2548           if(imm[i]) {
2549             if(opcode2[i]==0) // SLL
2550             {
2551               emit_shlimm(s<0?t:s,imm[i],t);
2552             }
2553             if(opcode2[i]==2) // SRL
2554             {
2555               emit_shrimm(s<0?t:s,imm[i],t);
2556             }
2557             if(opcode2[i]==3) // SRA
2558             {
2559               emit_sarimm(s<0?t:s,imm[i],t);
2560             }
2561           }else{
2562             // Shift by zero
2563             if(s>=0 && s!=t) emit_mov(s,t);
2564           }
2565         }
2566       }
2567       //emit_storereg(rt1[i],t); //DEBUG
2568     }
2569   }
2570   if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA
2571   {
2572     if(rt1[i]) {
2573       signed char sh,sl,th,tl;
2574       th=get_reg(i_regs->regmap,rt1[i]|64);
2575       tl=get_reg(i_regs->regmap,rt1[i]);
2576       sh=get_reg(i_regs->regmap,rs1[i]|64);
2577       sl=get_reg(i_regs->regmap,rs1[i]);
2578       if(tl>=0) {
2579         if(rs1[i]==0)
2580         {
2581           emit_zeroreg(tl);
2582           if(th>=0) emit_zeroreg(th);
2583         }
2584         else
2585         {
2586           assert(sl>=0);
2587           assert(sh>=0);
2588           if(imm[i]) {
2589             if(opcode2[i]==0x38) // DSLL
2590             {
2591               if(th>=0) emit_shldimm(sh,sl,imm[i],th);
2592               emit_shlimm(sl,imm[i],tl);
2593             }
2594             if(opcode2[i]==0x3a) // DSRL
2595             {
2596               emit_shrdimm(sl,sh,imm[i],tl);
2597               if(th>=0) emit_shrimm(sh,imm[i],th);
2598             }
2599             if(opcode2[i]==0x3b) // DSRA
2600             {
2601               emit_shrdimm(sl,sh,imm[i],tl);
2602               if(th>=0) emit_sarimm(sh,imm[i],th);
2603             }
2604           }else{
2605             // Shift by zero
2606             if(sl!=tl) emit_mov(sl,tl);
2607             if(th>=0&&sh!=th) emit_mov(sh,th);
2608           }
2609         }
2610       }
2611     }
2612   }
2613   if(opcode2[i]==0x3c) // DSLL32
2614   {
2615     if(rt1[i]) {
2616       signed char sl,tl,th;
2617       tl=get_reg(i_regs->regmap,rt1[i]);
2618       th=get_reg(i_regs->regmap,rt1[i]|64);
2619       sl=get_reg(i_regs->regmap,rs1[i]);
2620       if(th>=0||tl>=0){
2621         assert(tl>=0);
2622         assert(th>=0);
2623         assert(sl>=0);
2624         emit_mov(sl,th);
2625         emit_zeroreg(tl);
2626         if(imm[i]>32)
2627         {
2628           emit_shlimm(th,imm[i]&31,th);
2629         }
2630       }
2631     }
2632   }
2633   if(opcode2[i]==0x3e) // DSRL32
2634   {
2635     if(rt1[i]) {
2636       signed char sh,tl,th;
2637       tl=get_reg(i_regs->regmap,rt1[i]);
2638       th=get_reg(i_regs->regmap,rt1[i]|64);
2639       sh=get_reg(i_regs->regmap,rs1[i]|64);
2640       if(tl>=0){
2641         assert(sh>=0);
2642         emit_mov(sh,tl);
2643         if(th>=0) emit_zeroreg(th);
2644         if(imm[i]>32)
2645         {
2646           emit_shrimm(tl,imm[i]&31,tl);
2647         }
2648       }
2649     }
2650   }
2651   if(opcode2[i]==0x3f) // DSRA32
2652   {
2653     if(rt1[i]) {
2654       signed char sh,tl;
2655       tl=get_reg(i_regs->regmap,rt1[i]);
2656       sh=get_reg(i_regs->regmap,rs1[i]|64);
2657       if(tl>=0){
2658         assert(sh>=0);
2659         emit_mov(sh,tl);
2660         if(imm[i]>32)
2661         {
2662           emit_sarimm(tl,imm[i]&31,tl);
2663         }
2664       }
2665     }
2666   }
2667 }
2668
2669 #ifndef shift_assemble
2670 void shift_assemble(int i,struct regstat *i_regs)
2671 {
2672   printf("Need shift_assemble for this architecture.\n");
2673   exit(1);
2674 }
2675 #endif
2676
2677 void load_assemble(int i,struct regstat *i_regs)
2678 {
2679   int s,th,tl,addr,map=-1;
2680   int offset;
2681   int jaddr=0;
2682   int memtarget,c=0;
2683   u_int hr,reglist=0;
2684   th=get_reg(i_regs->regmap,rt1[i]|64);
2685   tl=get_reg(i_regs->regmap,rt1[i]);
2686   s=get_reg(i_regs->regmap,rs1[i]);
2687   offset=imm[i];
2688   for(hr=0;hr<HOST_REGS;hr++) {
2689     if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
2690   }
2691   if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
2692   if(s>=0) {
2693     c=(i_regs->wasconst>>s)&1;
2694     memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80800000;
2695     if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
2696   }
2697   if(offset||s<0||c) addr=tl;
2698   else addr=s;
2699   //printf("load_assemble: c=%d\n",c);
2700   //if(c) printf("load_assemble: const=%x\n",(int)constmap[i][s]+offset);
2701   // FIXME: Even if the load is a NOP, we should check for pagefaults...
2702   if(tl>=0) {
2703     //assert(tl>=0);
2704     //assert(rt1[i]);
2705     reglist&=~(1<<tl);
2706     if(th>=0) reglist&=~(1<<th);
2707     if(!using_tlb) {
2708       if(!c) {
2709 //#define R29_HACK 1
2710         #ifdef R29_HACK
2711         // Strmnnrmn's speed hack
2712         if(rs1[i]!=29||start<0x80001000||start>=0x80800000)
2713         #endif
2714         {
2715           emit_cmpimm(addr,0x800000);
2716           jaddr=(int)out;
2717           #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
2718           // Hint to branch predictor that the branch is unlikely to be taken
2719           if(rs1[i]>=28)
2720             emit_jno_unlikely(0);
2721           else
2722           #endif
2723           emit_jno(0);
2724         }
2725       }
2726     }else{ // using tlb
2727       int x=0;
2728       if (opcode[i]==0x20||opcode[i]==0x24) x=3; // LB/LBU
2729       if (opcode[i]==0x21||opcode[i]==0x25) x=2; // LH/LHU
2730       map=get_reg(i_regs->regmap,TLREG);
2731       assert(map>=0);
2732       map=do_tlb_r(addr,tl,map,x,-1,-1,c,constmap[i][s]+offset);
2733       do_tlb_r_branch(map,c,constmap[i][s]+offset,&jaddr);
2734     }
2735     if (opcode[i]==0x20) { // LB
2736       if(!c||memtarget) {
2737         #ifdef HOST_IMM_ADDR32
2738         if(c)
2739           emit_movsbl_tlb((constmap[i][s]+offset)^3,map,tl);
2740         else
2741         #endif
2742         {
2743           //emit_xorimm(addr,3,tl);
2744           //gen_tlb_addr_r(tl,map);
2745           //emit_movsbl_indexed((int)rdram-0x80000000,tl,tl);
2746           int x=0;
2747           if(!c) emit_xorimm(addr,3,tl);
2748           else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2749           emit_movsbl_indexed_tlb(x,tl,map,tl);
2750         }
2751         if(jaddr)
2752           add_stub(LOADB_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2753       }
2754       else
2755         inline_readstub(LOADB_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2756     }
2757     if (opcode[i]==0x21) { // LH
2758       if(!c||memtarget) {
2759         #ifdef HOST_IMM_ADDR32
2760         if(c)
2761           emit_movswl_tlb((constmap[i][s]+offset)^2,map,tl);
2762         else
2763         #endif
2764         {
2765           int x=0;
2766           if(!c) emit_xorimm(addr,2,tl);
2767           else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
2768           //#ifdef
2769           //emit_movswl_indexed_tlb(x,tl,map,tl);
2770           //else
2771           if(map>=0) {
2772             gen_tlb_addr_r(tl,map);
2773             emit_movswl_indexed(x,tl,tl);
2774           }else
2775             emit_movswl_indexed((int)rdram-0x80000000+x,tl,tl);
2776         }
2777         if(jaddr)
2778           add_stub(LOADH_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2779       }
2780       else
2781         inline_readstub(LOADH_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2782     }
2783     if (opcode[i]==0x23) { // LW
2784       if(!c||memtarget) {
2785         //emit_readword_indexed((int)rdram-0x80000000,addr,tl);
2786         #ifdef HOST_IMM_ADDR32
2787         if(c)
2788           emit_readword_tlb(constmap[i][s]+offset,map,tl);
2789         else
2790         #endif
2791         emit_readword_indexed_tlb(0,addr,map,tl);
2792         if(jaddr)
2793           add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2794       }
2795       else
2796         inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2797     }
2798     if (opcode[i]==0x24) { // LBU
2799       if(!c||memtarget) {
2800         #ifdef HOST_IMM_ADDR32
2801         if(c)
2802           emit_movzbl_tlb((constmap[i][s]+offset)^3,map,tl);
2803         else
2804         #endif
2805         {
2806           //emit_xorimm(addr,3,tl);
2807           //gen_tlb_addr_r(tl,map);
2808           //emit_movzbl_indexed((int)rdram-0x80000000,tl,tl);
2809           int x=0;
2810           if(!c) emit_xorimm(addr,3,tl);
2811           else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2812           emit_movzbl_indexed_tlb(x,tl,map,tl);
2813         }
2814         if(jaddr)
2815           add_stub(LOADBU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2816       }
2817       else
2818         inline_readstub(LOADBU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2819     }
2820     if (opcode[i]==0x25) { // LHU
2821       if(!c||memtarget) {
2822         #ifdef HOST_IMM_ADDR32
2823         if(c)
2824           emit_movzwl_tlb((constmap[i][s]+offset)^2,map,tl);
2825         else
2826         #endif
2827         {
2828           int x=0;
2829           if(!c) emit_xorimm(addr,2,tl);
2830           else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
2831           //#ifdef
2832           //emit_movzwl_indexed_tlb(x,tl,map,tl);
2833           //#else
2834           if(map>=0) {
2835             gen_tlb_addr_r(tl,map);
2836             emit_movzwl_indexed(x,tl,tl);
2837           }else
2838             emit_movzwl_indexed((int)rdram-0x80000000+x,tl,tl);
2839           if(jaddr)
2840             add_stub(LOADHU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2841         }
2842       }
2843       else
2844         inline_readstub(LOADHU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2845     }
2846     if (opcode[i]==0x27) { // LWU
2847       assert(th>=0);
2848       if(!c||memtarget) {
2849         //emit_readword_indexed((int)rdram-0x80000000,addr,tl);
2850         #ifdef HOST_IMM_ADDR32
2851         if(c)
2852           emit_readword_tlb(constmap[i][s]+offset,map,tl);
2853         else
2854         #endif
2855         emit_readword_indexed_tlb(0,addr,map,tl);
2856         if(jaddr)
2857           add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2858       }
2859       else {
2860         inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2861       }
2862       emit_zeroreg(th);
2863     }
2864     if (opcode[i]==0x37) { // LD
2865       if(!c||memtarget) {
2866         //gen_tlb_addr_r(tl,map);
2867         //if(th>=0) emit_readword_indexed((int)rdram-0x80000000,addr,th);
2868         //emit_readword_indexed((int)rdram-0x7FFFFFFC,addr,tl);
2869         #ifdef HOST_IMM_ADDR32
2870         if(c)
2871           emit_readdword_tlb(constmap[i][s]+offset,map,th,tl);
2872         else
2873         #endif
2874         emit_readdword_indexed_tlb(0,addr,map,th,tl);
2875         if(jaddr)
2876           add_stub(LOADD_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2877       }
2878       else
2879         inline_readstub(LOADD_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2880     }
2881     //emit_storereg(rt1[i],tl); // DEBUG
2882   }
2883   //if(opcode[i]==0x23)
2884   //if(opcode[i]==0x24)
2885   //if(opcode[i]==0x23||opcode[i]==0x24)
2886   /*if(opcode[i]==0x21||opcode[i]==0x23||opcode[i]==0x24)
2887   {
2888     //emit_pusha();
2889     save_regs(0x100f);
2890         emit_readword((int)&last_count,ECX);
2891         #ifdef __i386__
2892         if(get_reg(i_regs->regmap,CCREG)<0)
2893           emit_loadreg(CCREG,HOST_CCREG);
2894         emit_add(HOST_CCREG,ECX,HOST_CCREG);
2895         emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
2896         emit_writeword(HOST_CCREG,(int)&Count);
2897         #endif
2898         #ifdef __arm__
2899         if(get_reg(i_regs->regmap,CCREG)<0)
2900           emit_loadreg(CCREG,0);
2901         else
2902           emit_mov(HOST_CCREG,0);
2903         emit_add(0,ECX,0);
2904         emit_addimm(0,2*ccadj[i],0);
2905         emit_writeword(0,(int)&Count);
2906         #endif
2907     emit_call((int)memdebug);
2908     //emit_popa();
2909     restore_regs(0x100f);
2910   }/**/
2911 }
2912
2913 #ifndef loadlr_assemble
2914 void loadlr_assemble(int i,struct regstat *i_regs)
2915 {
2916   printf("Need loadlr_assemble for this architecture.\n");
2917   exit(1);
2918 }
2919 #endif
2920
2921 void store_assemble(int i,struct regstat *i_regs)
2922 {
2923   int s,th,tl,map=-1;
2924   int addr,temp;
2925   int offset;
2926   int jaddr=0,jaddr2,type;
2927   int memtarget,c=0;
2928   int agr=AGEN1+(i&1);
2929   u_int hr,reglist=0;
2930   th=get_reg(i_regs->regmap,rs2[i]|64);
2931   tl=get_reg(i_regs->regmap,rs2[i]);
2932   s=get_reg(i_regs->regmap,rs1[i]);
2933   temp=get_reg(i_regs->regmap,agr);
2934   if(temp<0) temp=get_reg(i_regs->regmap,-1);
2935   offset=imm[i];
2936   if(s>=0) {
2937     c=(i_regs->wasconst>>s)&1;
2938     memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80800000;
2939     if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
2940   }
2941   assert(tl>=0);
2942   assert(temp>=0);
2943   for(hr=0;hr<HOST_REGS;hr++) {
2944     if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
2945   }
2946   if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
2947   if(offset||s<0||c) addr=temp;
2948   else addr=s;
2949   if(!using_tlb) {
2950     if(!c) {
2951       #ifdef R29_HACK
2952       // Strmnnrmn's speed hack
2953       memtarget=1;
2954       if(rs1[i]!=29||start<0x80001000||start>=0x80800000)
2955       #endif
2956       emit_cmpimm(addr,0x800000);
2957       #ifdef DESTRUCTIVE_SHIFT
2958       if(s==addr) emit_mov(s,temp);
2959       #endif
2960       #ifdef R29_HACK
2961       if(rs1[i]!=29||start<0x80001000||start>=0x80800000)
2962       #endif
2963       {
2964         jaddr=(int)out;
2965         #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
2966         // Hint to branch predictor that the branch is unlikely to be taken
2967         if(rs1[i]>=28)
2968           emit_jno_unlikely(0);
2969         else
2970         #endif
2971         emit_jno(0);
2972       }
2973     }
2974   }else{ // using tlb
2975     int x=0;
2976     if (opcode[i]==0x28) x=3; // SB
2977     if (opcode[i]==0x29) x=2; // SH
2978     map=get_reg(i_regs->regmap,TLREG);
2979     assert(map>=0);
2980     map=do_tlb_w(addr,temp,map,x,c,constmap[i][s]+offset);
2981     do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr);
2982   }
2983
2984   if (opcode[i]==0x28) { // SB
2985     if(!c||memtarget) {
2986       int x=0;
2987       if(!c) emit_xorimm(addr,3,temp);
2988       else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2989       //gen_tlb_addr_w(temp,map);
2990       //emit_writebyte_indexed(tl,(int)rdram-0x80000000,temp);
2991       emit_writebyte_indexed_tlb(tl,x,temp,map,temp);
2992     }
2993     type=STOREB_STUB;
2994   }
2995   if (opcode[i]==0x29) { // SH
2996     if(!c||memtarget) {
2997       int x=0;
2998       if(!c) emit_xorimm(addr,2,temp);
2999       else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
3000       //#ifdef
3001       //emit_writehword_indexed_tlb(tl,x,temp,map,temp);
3002       //#else
3003       if(map>=0) {
3004         gen_tlb_addr_w(temp,map);
3005         emit_writehword_indexed(tl,x,temp);
3006       }else
3007         emit_writehword_indexed(tl,(int)rdram-0x80000000+x,temp);
3008     }
3009     type=STOREH_STUB;
3010   }
3011   if (opcode[i]==0x2B) { // SW
3012     if(!c||memtarget)
3013       //emit_writeword_indexed(tl,(int)rdram-0x80000000,addr);
3014       emit_writeword_indexed_tlb(tl,0,addr,map,temp);
3015     type=STOREW_STUB;
3016   }
3017   if (opcode[i]==0x3F) { // SD
3018     if(!c||memtarget) {
3019       if(rs2[i]) {
3020         assert(th>=0);
3021         //emit_writeword_indexed(th,(int)rdram-0x80000000,addr);
3022         //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,addr);
3023         emit_writedword_indexed_tlb(th,tl,0,addr,map,temp);
3024       }else{
3025         // Store zero
3026         //emit_writeword_indexed(tl,(int)rdram-0x80000000,temp);
3027         //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,temp);
3028         emit_writedword_indexed_tlb(tl,tl,0,addr,map,temp);
3029       }
3030     }
3031     type=STORED_STUB;
3032   }
3033   if(jaddr) {
3034     add_stub(type,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3035   } else if(!memtarget) {
3036     inline_writestub(type,i,constmap[i][s]+offset,i_regs->regmap,rs2[i],ccadj[i],reglist);
3037   }
3038   if(!using_tlb) {
3039     if(!c||memtarget) {
3040       #ifdef DESTRUCTIVE_SHIFT
3041       // The x86 shift operation is 'destructive'; it overwrites the
3042       // source register, so we need to make a copy first and use that.
3043       addr=temp;
3044       #endif
3045       #if defined(HOST_IMM8)
3046       int ir=get_reg(i_regs->regmap,INVCP);
3047       assert(ir>=0);
3048       emit_cmpmem_indexedsr12_reg(ir,addr,1);
3049       #else
3050       emit_cmpmem_indexedsr12_imm((int)invalid_code,addr,1);
3051       #endif
3052       jaddr2=(int)out;
3053       emit_jne(0);
3054       add_stub(INVCODE_STUB,jaddr2,(int)out,reglist|(1<<HOST_CCREG),addr,0,0,0);
3055     }
3056   }
3057   //if(opcode[i]==0x2B || opcode[i]==0x3F)
3058   //if(opcode[i]==0x2B || opcode[i]==0x28)
3059   //if(opcode[i]==0x2B || opcode[i]==0x29)
3060   //if(opcode[i]==0x2B)
3061   /*if(opcode[i]==0x2B || opcode[i]==0x28 || opcode[i]==0x29 || opcode[i]==0x3F)
3062   {
3063     //emit_pusha();
3064     save_regs(0x100f);
3065         emit_readword((int)&last_count,ECX);
3066         #ifdef __i386__
3067         if(get_reg(i_regs->regmap,CCREG)<0)
3068           emit_loadreg(CCREG,HOST_CCREG);
3069         emit_add(HOST_CCREG,ECX,HOST_CCREG);
3070         emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3071         emit_writeword(HOST_CCREG,(int)&Count);
3072         #endif
3073         #ifdef __arm__
3074         if(get_reg(i_regs->regmap,CCREG)<0)
3075           emit_loadreg(CCREG,0);
3076         else
3077           emit_mov(HOST_CCREG,0);
3078         emit_add(0,ECX,0);
3079         emit_addimm(0,2*ccadj[i],0);
3080         emit_writeword(0,(int)&Count);
3081         #endif
3082     emit_call((int)memdebug);
3083     //emit_popa();
3084     restore_regs(0x100f);
3085   }/**/
3086 }
3087
3088 void storelr_assemble(int i,struct regstat *i_regs)
3089 {
3090   int s,th,tl;
3091   int temp;
3092   int temp2;
3093   int offset;
3094   int jaddr=0,jaddr2;
3095   int case1,case2,case3;
3096   int done0,done1,done2;
3097   int memtarget,c=0;
3098   u_int hr,reglist=0;
3099   th=get_reg(i_regs->regmap,rs2[i]|64);
3100   tl=get_reg(i_regs->regmap,rs2[i]);
3101   s=get_reg(i_regs->regmap,rs1[i]);
3102   temp=get_reg(i_regs->regmap,-1);
3103   offset=imm[i];
3104   if(s>=0) {
3105     c=(i_regs->isconst>>s)&1;
3106     memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80800000;
3107     if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
3108   }
3109   assert(tl>=0);
3110   for(hr=0;hr<HOST_REGS;hr++) {
3111     if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3112   }
3113   if(tl>=0) {
3114     assert(temp>=0);
3115     if(!using_tlb) {
3116       if(!c) {
3117         emit_cmpimm(s<0||offset?temp:s,0x800000);
3118         if(!offset&&s!=temp) emit_mov(s,temp);
3119         jaddr=(int)out;
3120         emit_jno(0);
3121       }
3122       else
3123       {
3124         if(!memtarget||!rs1[i]) {
3125           jaddr=(int)out;
3126           emit_jmp(0);
3127         }
3128       }
3129       if((u_int)rdram!=0x80000000)
3130         emit_addimm_no_flags((u_int)rdram-(u_int)0x80000000,temp);
3131     }else{ // using tlb
3132       int map=get_reg(i_regs->regmap,TLREG);
3133       assert(map>=0);
3134       map=do_tlb_w(c||s<0||offset?temp:s,temp,map,0,c,constmap[i][s]+offset);
3135       if(!c&&!offset&&s>=0) emit_mov(s,temp);
3136       do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr);
3137       if(!jaddr&&!memtarget) {
3138         jaddr=(int)out;
3139         emit_jmp(0);
3140       }
3141       gen_tlb_addr_w(temp,map);
3142     }
3143
3144     if (opcode[i]==0x2C||opcode[i]==0x2D) { // SDL/SDR
3145       temp2=get_reg(i_regs->regmap,FTEMP);
3146       if(!rs2[i]) temp2=th=tl;
3147     }
3148
3149     emit_testimm(temp,2);
3150     case2=(int)out;
3151     emit_jne(0);
3152     emit_testimm(temp,1);
3153     case1=(int)out;
3154     emit_jne(0);
3155     // 0
3156     if (opcode[i]==0x2A) { // SWL
3157       emit_writeword_indexed(tl,0,temp);
3158     }
3159     if (opcode[i]==0x2E) { // SWR
3160       emit_writebyte_indexed(tl,3,temp);
3161     }
3162     if (opcode[i]==0x2C) { // SDL
3163       emit_writeword_indexed(th,0,temp);
3164       if(rs2[i]) emit_mov(tl,temp2);
3165     }
3166     if (opcode[i]==0x2D) { // SDR
3167       emit_writebyte_indexed(tl,3,temp);
3168       if(rs2[i]) emit_shldimm(th,tl,24,temp2);
3169     }
3170     done0=(int)out;
3171     emit_jmp(0);
3172     // 1
3173     set_jump_target(case1,(int)out);
3174     if (opcode[i]==0x2A) { // SWL
3175       // Write 3 msb into three least significant bytes
3176       if(rs2[i]) emit_rorimm(tl,8,tl);
3177       emit_writehword_indexed(tl,-1,temp);
3178       if(rs2[i]) emit_rorimm(tl,16,tl);
3179       emit_writebyte_indexed(tl,1,temp);
3180       if(rs2[i]) emit_rorimm(tl,8,tl);
3181     }
3182     if (opcode[i]==0x2E) { // SWR
3183       // Write two lsb into two most significant bytes
3184       emit_writehword_indexed(tl,1,temp);
3185     }
3186     if (opcode[i]==0x2C) { // SDL
3187       if(rs2[i]) emit_shrdimm(tl,th,8,temp2);
3188       // Write 3 msb into three least significant bytes
3189       if(rs2[i]) emit_rorimm(th,8,th);
3190       emit_writehword_indexed(th,-1,temp);
3191       if(rs2[i]) emit_rorimm(th,16,th);
3192       emit_writebyte_indexed(th,1,temp);
3193       if(rs2[i]) emit_rorimm(th,8,th);
3194     }
3195     if (opcode[i]==0x2D) { // SDR
3196       if(rs2[i]) emit_shldimm(th,tl,16,temp2);
3197       // Write two lsb into two most significant bytes
3198       emit_writehword_indexed(tl,1,temp);
3199     }
3200     done1=(int)out;
3201     emit_jmp(0);
3202     // 2
3203     set_jump_target(case2,(int)out);
3204     emit_testimm(temp,1);
3205     case3=(int)out;
3206     emit_jne(0);
3207     if (opcode[i]==0x2A) { // SWL
3208       // Write two msb into two least significant bytes
3209       if(rs2[i]) emit_rorimm(tl,16,tl);
3210       emit_writehword_indexed(tl,-2,temp);
3211       if(rs2[i]) emit_rorimm(tl,16,tl);
3212     }
3213     if (opcode[i]==0x2E) { // SWR
3214       // Write 3 lsb into three most significant bytes
3215       emit_writebyte_indexed(tl,-1,temp);
3216       if(rs2[i]) emit_rorimm(tl,8,tl);
3217       emit_writehword_indexed(tl,0,temp);
3218       if(rs2[i]) emit_rorimm(tl,24,tl);
3219     }
3220     if (opcode[i]==0x2C) { // SDL
3221       if(rs2[i]) emit_shrdimm(tl,th,16,temp2);
3222       // Write two msb into two least significant bytes
3223       if(rs2[i]) emit_rorimm(th,16,th);
3224       emit_writehword_indexed(th,-2,temp);
3225       if(rs2[i]) emit_rorimm(th,16,th);
3226     }
3227     if (opcode[i]==0x2D) { // SDR
3228       if(rs2[i]) emit_shldimm(th,tl,8,temp2);
3229       // Write 3 lsb into three most significant bytes
3230       emit_writebyte_indexed(tl,-1,temp);
3231       if(rs2[i]) emit_rorimm(tl,8,tl);
3232       emit_writehword_indexed(tl,0,temp);
3233       if(rs2[i]) emit_rorimm(tl,24,tl);
3234     }
3235     done2=(int)out;
3236     emit_jmp(0);
3237     // 3
3238     set_jump_target(case3,(int)out);
3239     if (opcode[i]==0x2A) { // SWL
3240       // Write msb into least significant byte
3241       if(rs2[i]) emit_rorimm(tl,24,tl);
3242       emit_writebyte_indexed(tl,-3,temp);
3243       if(rs2[i]) emit_rorimm(tl,8,tl);
3244     }
3245     if (opcode[i]==0x2E) { // SWR
3246       // Write entire word
3247       emit_writeword_indexed(tl,-3,temp);
3248     }
3249     if (opcode[i]==0x2C) { // SDL
3250       if(rs2[i]) emit_shrdimm(tl,th,24,temp2);
3251       // Write msb into least significant byte
3252       if(rs2[i]) emit_rorimm(th,24,th);
3253       emit_writebyte_indexed(th,-3,temp);
3254       if(rs2[i]) emit_rorimm(th,8,th);
3255     }
3256     if (opcode[i]==0x2D) { // SDR
3257       if(rs2[i]) emit_mov(th,temp2);
3258       // Write entire word
3259       emit_writeword_indexed(tl,-3,temp);
3260     }
3261     set_jump_target(done0,(int)out);
3262     set_jump_target(done1,(int)out);
3263     set_jump_target(done2,(int)out);
3264     if (opcode[i]==0x2C) { // SDL
3265       emit_testimm(temp,4);
3266       done0=(int)out;
3267       emit_jne(0);
3268       emit_andimm(temp,~3,temp);
3269       emit_writeword_indexed(temp2,4,temp);
3270       set_jump_target(done0,(int)out);
3271     }
3272     if (opcode[i]==0x2D) { // SDR
3273       emit_testimm(temp,4);
3274       done0=(int)out;
3275       emit_jeq(0);
3276       emit_andimm(temp,~3,temp);
3277       emit_writeword_indexed(temp2,-4,temp);
3278       set_jump_target(done0,(int)out);
3279     }
3280     if(!c||!memtarget)
3281       add_stub(STORELR_STUB,jaddr,(int)out,0,(int)i_regs,rs2[i],ccadj[i],reglist);
3282   }
3283   if(!using_tlb) {
3284     emit_addimm_no_flags((u_int)0x80000000-(u_int)rdram,temp);
3285     #if defined(HOST_IMM8)
3286     int ir=get_reg(i_regs->regmap,INVCP);
3287     assert(ir>=0);
3288     emit_cmpmem_indexedsr12_reg(ir,temp,1);
3289     #else
3290     emit_cmpmem_indexedsr12_imm((int)invalid_code,temp,1);
3291     #endif
3292     jaddr2=(int)out;
3293     emit_jne(0);
3294     add_stub(INVCODE_STUB,jaddr2,(int)out,reglist|(1<<HOST_CCREG),temp,0,0,0);
3295   }
3296   /*
3297     emit_pusha();
3298     //save_regs(0x100f);
3299         emit_readword((int)&last_count,ECX);
3300         if(get_reg(i_regs->regmap,CCREG)<0)
3301           emit_loadreg(CCREG,HOST_CCREG);
3302         emit_add(HOST_CCREG,ECX,HOST_CCREG);
3303         emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3304         emit_writeword(HOST_CCREG,(int)&Count);
3305     emit_call((int)memdebug);
3306     emit_popa();
3307     //restore_regs(0x100f);
3308   /**/
3309 }
3310
3311 void c1ls_assemble(int i,struct regstat *i_regs)
3312 {
3313 #ifndef DISABLE_COP1
3314   int s,th,tl;
3315   int temp,ar;
3316   int map=-1;
3317   int offset;
3318   int c=0;
3319   int jaddr,jaddr2=0,jaddr3,type;
3320   int agr=AGEN1+(i&1);
3321   u_int hr,reglist=0;
3322   th=get_reg(i_regs->regmap,FTEMP|64);
3323   tl=get_reg(i_regs->regmap,FTEMP);
3324   s=get_reg(i_regs->regmap,rs1[i]);
3325   temp=get_reg(i_regs->regmap,agr);
3326   if(temp<0) temp=get_reg(i_regs->regmap,-1);
3327   offset=imm[i];
3328   assert(tl>=0);
3329   assert(rs1[i]>0);
3330   assert(temp>=0);
3331   for(hr=0;hr<HOST_REGS;hr++) {
3332     if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3333   }
3334   if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
3335   if (opcode[i]==0x31||opcode[i]==0x35) // LWC1/LDC1
3336   {
3337     // Loads use a temporary register which we need to save
3338     reglist|=1<<temp;
3339   }
3340   if (opcode[i]==0x39||opcode[i]==0x3D) // SWC1/SDC1
3341     ar=temp;
3342   else // LWC1/LDC1
3343     ar=tl;
3344   //if(s<0) emit_loadreg(rs1[i],ar); //address_generation does this now
3345   //else c=(i_regs->wasconst>>s)&1;
3346   if(s>=0) c=(i_regs->wasconst>>s)&1;
3347   // Check cop1 unusable
3348   if(!cop1_usable) {
3349     signed char rs=get_reg(i_regs->regmap,CSREG);
3350     assert(rs>=0);
3351     emit_testimm(rs,0x20000000);
3352     jaddr=(int)out;
3353     emit_jeq(0);
3354     add_stub(FP_STUB,jaddr,(int)out,i,rs,(int)i_regs,is_delayslot,0);
3355     cop1_usable=1;
3356   }
3357   if (opcode[i]==0x39) { // SWC1 (get float address)
3358     emit_readword((int)&reg_cop1_simple[(source[i]>>16)&0x1f],tl);
3359   }
3360   if (opcode[i]==0x3D) { // SDC1 (get double address)
3361     emit_readword((int)&reg_cop1_double[(source[i]>>16)&0x1f],tl);
3362   }
3363   // Generate address + offset
3364   if(!using_tlb) {
3365     if(!c)
3366       emit_cmpimm(offset||c||s<0?ar:s,0x800000);
3367   }
3368   else
3369   {
3370     map=get_reg(i_regs->regmap,TLREG);
3371     assert(map>=0);
3372     if (opcode[i]==0x31||opcode[i]==0x35) { // LWC1/LDC1
3373       map=do_tlb_r(offset||c||s<0?ar:s,ar,map,0,-1,-1,c,constmap[i][s]+offset);
3374     }
3375     if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3376       map=do_tlb_w(offset||c||s<0?ar:s,ar,map,0,c,constmap[i][s]+offset);
3377     }
3378   }
3379   if (opcode[i]==0x39) { // SWC1 (read float)
3380     emit_readword_indexed(0,tl,tl);
3381   }
3382   if (opcode[i]==0x3D) { // SDC1 (read double)
3383     emit_readword_indexed(4,tl,th);
3384     emit_readword_indexed(0,tl,tl);
3385   }
3386   if (opcode[i]==0x31) { // LWC1 (get target address)
3387     emit_readword((int)&reg_cop1_simple[(source[i]>>16)&0x1f],temp);
3388   }
3389   if (opcode[i]==0x35) { // LDC1 (get target address)
3390     emit_readword((int)&reg_cop1_double[(source[i]>>16)&0x1f],temp);
3391   }
3392   if(!using_tlb) {
3393     if(!c) {
3394       jaddr2=(int)out;
3395       emit_jno(0);
3396     }
3397     else if(((signed int)(constmap[i][s]+offset))>=(signed int)0x80800000) {
3398       jaddr2=(int)out;
3399       emit_jmp(0); // inline_readstub/inline_writestub?  Very rare case
3400     }
3401     #ifdef DESTRUCTIVE_SHIFT
3402     if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3403       if(!offset&&!c&&s>=0) emit_mov(s,ar);
3404     }
3405     #endif
3406   }else{
3407     if (opcode[i]==0x31||opcode[i]==0x35) { // LWC1/LDC1
3408       do_tlb_r_branch(map,c,constmap[i][s]+offset,&jaddr2);
3409     }
3410     if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3411       do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr2);
3412     }
3413   }
3414   if (opcode[i]==0x31) { // LWC1
3415     //if(s>=0&&!c&&!offset) emit_mov(s,tl);
3416     //gen_tlb_addr_r(ar,map);
3417     //emit_readword_indexed((int)rdram-0x80000000,tl,tl);
3418     #ifdef HOST_IMM_ADDR32
3419     if(c) emit_readword_tlb(constmap[i][s]+offset,map,tl);
3420     else
3421     #endif
3422     emit_readword_indexed_tlb(0,offset||c||s<0?tl:s,map,tl);
3423     type=LOADW_STUB;
3424   }
3425   if (opcode[i]==0x35) { // LDC1
3426     assert(th>=0);
3427     //if(s>=0&&!c&&!offset) emit_mov(s,tl);
3428     //gen_tlb_addr_r(ar,map);
3429     //emit_readword_indexed((int)rdram-0x80000000,tl,th);
3430     //emit_readword_indexed((int)rdram-0x7FFFFFFC,tl,tl);
3431     #ifdef HOST_IMM_ADDR32
3432     if(c) emit_readdword_tlb(constmap[i][s]+offset,map,th,tl);
3433     else
3434     #endif
3435     emit_readdword_indexed_tlb(0,offset||c||s<0?tl:s,map,th,tl);
3436     type=LOADD_STUB;
3437   }
3438   if (opcode[i]==0x39) { // SWC1
3439     //emit_writeword_indexed(tl,(int)rdram-0x80000000,temp);
3440     emit_writeword_indexed_tlb(tl,0,offset||c||s<0?temp:s,map,temp);
3441     type=STOREW_STUB;
3442   }
3443   if (opcode[i]==0x3D) { // SDC1
3444     assert(th>=0);
3445     //emit_writeword_indexed(th,(int)rdram-0x80000000,temp);
3446     //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,temp);
3447     emit_writedword_indexed_tlb(th,tl,0,offset||c||s<0?temp:s,map,temp);
3448     type=STORED_STUB;
3449   }
3450   if(!using_tlb) {
3451     if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3452       #ifndef DESTRUCTIVE_SHIFT
3453       temp=offset||c||s<0?ar:s;
3454       #endif
3455       #if defined(HOST_IMM8)
3456       int ir=get_reg(i_regs->regmap,INVCP);
3457       assert(ir>=0);
3458       emit_cmpmem_indexedsr12_reg(ir,temp,1);
3459       #else
3460       emit_cmpmem_indexedsr12_imm((int)invalid_code,temp,1);
3461       #endif
3462       jaddr3=(int)out;
3463       emit_jne(0);
3464       add_stub(INVCODE_STUB,jaddr3,(int)out,reglist|(1<<HOST_CCREG),temp,0,0,0);
3465     }
3466   }
3467   if(jaddr2) add_stub(type,jaddr2,(int)out,i,offset||c||s<0?ar:s,(int)i_regs,ccadj[i],reglist);
3468   if (opcode[i]==0x31) { // LWC1 (write float)
3469     emit_writeword_indexed(tl,0,temp);
3470   }
3471   if (opcode[i]==0x35) { // LDC1 (write double)
3472     emit_writeword_indexed(th,4,temp);
3473     emit_writeword_indexed(tl,0,temp);
3474   }
3475   //if(opcode[i]==0x39)
3476   /*if(opcode[i]==0x39||opcode[i]==0x31)
3477   {
3478     emit_pusha();
3479         emit_readword((int)&last_count,ECX);
3480         if(get_reg(i_regs->regmap,CCREG)<0)
3481           emit_loadreg(CCREG,HOST_CCREG);
3482         emit_add(HOST_CCREG,ECX,HOST_CCREG);
3483         emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3484         emit_writeword(HOST_CCREG,(int)&Count);
3485     emit_call((int)memdebug);
3486     emit_popa();
3487   }/**/
3488 #else
3489   cop1_unusable(i, i_regs);
3490 #endif
3491 }
3492
3493 #ifndef multdiv_assemble
3494 void multdiv_assemble(int i,struct regstat *i_regs)
3495 {
3496   printf("Need multdiv_assemble for this architecture.\n");
3497   exit(1);
3498 }
3499 #endif
3500
3501 void mov_assemble(int i,struct regstat *i_regs)
3502 {
3503   //if(opcode2[i]==0x10||opcode2[i]==0x12) { // MFHI/MFLO
3504   //if(opcode2[i]==0x11||opcode2[i]==0x13) { // MTHI/MTLO
3505   assert(rt1[i]>0);
3506   if(rt1[i]) {
3507     signed char sh,sl,th,tl;
3508     th=get_reg(i_regs->regmap,rt1[i]|64);
3509     tl=get_reg(i_regs->regmap,rt1[i]);
3510     //assert(tl>=0);
3511     if(tl>=0) {
3512       sh=get_reg(i_regs->regmap,rs1[i]|64);
3513       sl=get_reg(i_regs->regmap,rs1[i]);
3514       if(sl>=0) emit_mov(sl,tl);
3515       else emit_loadreg(rs1[i],tl);
3516       if(th>=0) {
3517         if(sh>=0) emit_mov(sh,th);
3518         else emit_loadreg(rs1[i]|64,th);
3519       }
3520     }
3521   }
3522 }
3523
3524 #ifndef fconv_assemble
3525 void fconv_assemble(int i,struct regstat *i_regs)
3526 {
3527   printf("Need fconv_assemble for this architecture.\n");
3528   exit(1);
3529 }
3530 #endif
3531
3532 #if 0
3533 void float_assemble(int i,struct regstat *i_regs)
3534 {
3535   printf("Need float_assemble for this architecture.\n");
3536   exit(1);
3537 }
3538 #endif
3539
3540 void syscall_assemble(int i,struct regstat *i_regs)
3541 {
3542   signed char ccreg=get_reg(i_regs->regmap,CCREG);
3543   assert(ccreg==HOST_CCREG);
3544   assert(!is_delayslot);
3545   emit_movimm(start+i*4,EAX); // Get PC
3546   emit_addimm(HOST_CCREG,CLOCK_DIVIDER*ccadj[i],HOST_CCREG); // CHECK: is this right?  There should probably be an extra cycle...
3547   emit_jmp((int)jump_syscall);
3548 }
3549
3550 void ds_assemble(int i,struct regstat *i_regs)
3551 {
3552   is_delayslot=1;
3553   switch(itype[i]) {
3554     case ALU:
3555       alu_assemble(i,i_regs);break;
3556     case IMM16:
3557       imm16_assemble(i,i_regs);break;
3558     case SHIFT:
3559       shift_assemble(i,i_regs);break;
3560     case SHIFTIMM:
3561       shiftimm_assemble(i,i_regs);break;
3562     case LOAD:
3563       load_assemble(i,i_regs);break;
3564     case LOADLR:
3565       loadlr_assemble(i,i_regs);break;
3566     case STORE:
3567       store_assemble(i,i_regs);break;
3568     case STORELR:
3569       storelr_assemble(i,i_regs);break;
3570     case COP0:
3571       cop0_assemble(i,i_regs);break;
3572     case COP1:
3573       cop1_assemble(i,i_regs);break;
3574     case C1LS:
3575       c1ls_assemble(i,i_regs);break;
3576     case FCONV:
3577       fconv_assemble(i,i_regs);break;
3578     case FLOAT:
3579       float_assemble(i,i_regs);break;
3580     case FCOMP:
3581       fcomp_assemble(i,i_regs);break;
3582     case MULTDIV:
3583       multdiv_assemble(i,i_regs);break;
3584     case MOV:
3585       mov_assemble(i,i_regs);break;
3586     case SYSCALL:
3587     case SPAN:
3588     case UJUMP:
3589     case RJUMP:
3590     case CJUMP:
3591     case SJUMP:
3592     case FJUMP:
3593       printf("Jump in the delay slot.  This is probably a bug.\n");
3594   }
3595   is_delayslot=0;
3596 }
3597
3598 // Is the branch target a valid internal jump?
3599 int internal_branch(uint64_t i_is32,int addr)
3600 {
3601   if(addr&1) return 0; // Indirect (register) jump
3602   if(addr>=start && addr<start+slen*4-4)
3603   {
3604     int t=(addr-start)>>2;
3605     // Delay slots are not valid branch targets
3606     //if(t>0&&(itype[t-1]==RJUMP||itype[t-1]==UJUMP||itype[t-1]==CJUMP||itype[t-1]==SJUMP||itype[t-1]==FJUMP)) return 0;
3607     // 64 -> 32 bit transition requires a recompile
3608     /*if(is32[t]&~unneeded_reg_upper[t]&~i_is32)
3609     {
3610       if(requires_32bit[t]&~i_is32) printf("optimizable: no\n");
3611       else printf("optimizable: yes\n");
3612     }*/
3613     //if(is32[t]&~unneeded_reg_upper[t]&~i_is32) return 0;
3614     if(requires_32bit[t]&~i_is32) return 0;
3615     else return 1;
3616   }
3617   return 0;
3618 }
3619
3620 #ifndef wb_invalidate
3621 void wb_invalidate(signed char pre[],signed char entry[],uint64_t dirty,uint64_t is32,
3622   uint64_t u,uint64_t uu)
3623 {
3624   int hr;
3625   for(hr=0;hr<HOST_REGS;hr++) {
3626     if(hr!=EXCLUDE_REG) {
3627       if(pre[hr]!=entry[hr]) {
3628         if(pre[hr]>=0) {
3629           if((dirty>>hr)&1) {
3630             if(get_reg(entry,pre[hr])<0) {
3631               if(pre[hr]<64) {
3632                 if(!((u>>pre[hr])&1)) {
3633                   emit_storereg(pre[hr],hr);
3634                   if( ((is32>>pre[hr])&1) && !((uu>>pre[hr])&1) ) {
3635                     emit_sarimm(hr,31,hr);
3636                     emit_storereg(pre[hr]|64,hr);
3637                   }
3638                 }
3639               }else{
3640                 if(!((uu>>(pre[hr]&63))&1) && !((is32>>(pre[hr]&63))&1)) {
3641                   emit_storereg(pre[hr],hr);
3642                 }
3643               }
3644             }
3645           }
3646         }
3647       }
3648     }
3649   }
3650   // Move from one register to another (no writeback)
3651   for(hr=0;hr<HOST_REGS;hr++) {
3652     if(hr!=EXCLUDE_REG) {
3653       if(pre[hr]!=entry[hr]) {
3654         if(pre[hr]>=0&&(pre[hr]&63)<TEMPREG) {
3655           int nr;
3656           if((nr=get_reg(entry,pre[hr]))>=0) {
3657             emit_mov(hr,nr);
3658           }
3659         }
3660       }
3661     }
3662   }
3663 }
3664 #endif
3665
3666 // Load the specified registers
3667 // This only loads the registers given as arguments because
3668 // we don't want to load things that will be overwritten
3669 void load_regs(signed char entry[],signed char regmap[],int is32,int rs1,int rs2)
3670 {
3671   int hr;
3672   // Load 32-bit regs
3673   for(hr=0;hr<HOST_REGS;hr++) {
3674     if(hr!=EXCLUDE_REG&&regmap[hr]>=0) {
3675       if(entry[hr]!=regmap[hr]) {
3676         if(regmap[hr]==rs1||regmap[hr]==rs2)
3677         {
3678           if(regmap[hr]==0) {
3679             emit_zeroreg(hr);
3680           }
3681           else
3682           {
3683             emit_loadreg(regmap[hr],hr);
3684           }
3685         }
3686       }
3687     }
3688   }
3689   //Load 64-bit regs
3690   for(hr=0;hr<HOST_REGS;hr++) {
3691     if(hr!=EXCLUDE_REG&&regmap[hr]>=0) {
3692       if(entry[hr]!=regmap[hr]) {
3693         if(regmap[hr]-64==rs1||regmap[hr]-64==rs2)
3694         {
3695           assert(regmap[hr]!=64);
3696           if((is32>>(regmap[hr]&63))&1) {
3697             int lr=get_reg(regmap,regmap[hr]-64);
3698             if(lr>=0)
3699               emit_sarimm(lr,31,hr);
3700             else
3701               emit_loadreg(regmap[hr],hr);
3702           }
3703           else
3704           {
3705             emit_loadreg(regmap[hr],hr);
3706           }
3707         }
3708       }
3709     }
3710   }
3711 }
3712
3713 // Load registers prior to the start of a loop
3714 // so that they are not loaded within the loop
3715 static void loop_preload(signed char pre[],signed char entry[])
3716 {
3717   int hr;
3718   for(hr=0;hr<HOST_REGS;hr++) {
3719     if(hr!=EXCLUDE_REG) {
3720       if(pre[hr]!=entry[hr]) {
3721         if(entry[hr]>=0) {
3722           if(get_reg(pre,entry[hr])<0) {
3723             assem_debug("loop preload:\n");
3724             //printf("loop preload: %d\n",hr);
3725             if(entry[hr]==0) {
3726               emit_zeroreg(hr);
3727             }
3728             else if(entry[hr]<TEMPREG)
3729             {
3730               emit_loadreg(entry[hr],hr);
3731             }
3732             else if(entry[hr]-64<TEMPREG)
3733             {
3734               emit_loadreg(entry[hr],hr);
3735             }
3736           }
3737         }
3738       }
3739     }
3740   }
3741 }
3742
3743 // Generate address for load/store instruction
3744 void address_generation(int i,struct regstat *i_regs,signed char entry[])
3745 {
3746   if(itype[i]==LOAD||itype[i]==LOADLR||itype[i]==STORE||itype[i]==STORELR||itype[i]==C1LS) {
3747     int ra;
3748     int agr=AGEN1+(i&1);
3749     int mgr=MGEN1+(i&1);
3750     if(itype[i]==LOAD) {
3751       ra=get_reg(i_regs->regmap,rt1[i]);
3752       //if(rt1[i]) assert(ra>=0);
3753     }
3754     if(itype[i]==LOADLR) {
3755       ra=get_reg(i_regs->regmap,FTEMP);
3756     }
3757     if(itype[i]==STORE||itype[i]==STORELR) {
3758       ra=get_reg(i_regs->regmap,agr);
3759       if(ra<0) ra=get_reg(i_regs->regmap,-1);
3760     }
3761     if(itype[i]==C1LS) {
3762       if (opcode[i]==0x31||opcode[i]==0x35) // LWC1/LDC1
3763         ra=get_reg(i_regs->regmap,FTEMP);
3764       else { // SWC1/SDC1
3765         ra=get_reg(i_regs->regmap,agr);
3766         if(ra<0) ra=get_reg(i_regs->regmap,-1);
3767       }
3768     }
3769     int rs=get_reg(i_regs->regmap,rs1[i]);
3770     int rm=get_reg(i_regs->regmap,TLREG);
3771     if(ra>=0) {
3772       int offset=imm[i];
3773       int c=(i_regs->wasconst>>rs)&1;
3774       if(rs1[i]==0) {
3775         // Using r0 as a base address
3776         /*if(rm>=0) {
3777           if(!entry||entry[rm]!=mgr) {
3778             generate_map_const(offset,rm);
3779           } // else did it in the previous cycle
3780         }*/
3781         if(!entry||entry[ra]!=agr) {
3782           if (opcode[i]==0x22||opcode[i]==0x26) {
3783             emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR
3784           }else if (opcode[i]==0x1a||opcode[i]==0x1b) {
3785             emit_movimm(offset&0xFFFFFFF8,ra); // LDL/LDR
3786           }else{
3787             emit_movimm(offset,ra);
3788           }
3789         } // else did it in the previous cycle
3790       }
3791       else if(rs<0) {
3792         if(!entry||entry[ra]!=rs1[i])
3793           emit_loadreg(rs1[i],ra);
3794         //if(!entry||entry[ra]!=rs1[i])
3795         //  printf("poor load scheduling!\n");
3796       }
3797       else if(c) {
3798         if(rm>=0) {
3799           if(!entry||entry[rm]!=mgr) {
3800             if(itype[i]==STORE||itype[i]==STORELR||opcode[i]==0x39||opcode[i]==0x3D) {
3801               // Stores to memory go thru the mapper to detect self-modifying
3802               // code, loads don't.
3803               if((unsigned int)(constmap[i][rs]+offset)>=0xC0000000 ||
3804                  (unsigned int)(constmap[i][rs]+offset)<0x80800000 )
3805                 generate_map_const(constmap[i][rs]+offset,rm);
3806             }else{
3807               if((signed int)(constmap[i][rs]+offset)>=(signed int)0xC0000000)
3808                 generate_map_const(constmap[i][rs]+offset,rm);
3809             }
3810           }
3811         }
3812         if(rs1[i]!=rt1[i]||itype[i]!=LOAD) {
3813           if(!entry||entry[ra]!=agr) {
3814             if (opcode[i]==0x22||opcode[i]==0x26) {
3815               emit_movimm((constmap[i][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR
3816             }else if (opcode[i]==0x1a||opcode[i]==0x1b) {
3817               emit_movimm((constmap[i][rs]+offset)&0xFFFFFFF8,ra); // LDL/LDR
3818             }else{
3819               #ifdef HOST_IMM_ADDR32
3820               if((itype[i]!=LOAD&&opcode[i]!=0x31&&opcode[i]!=0x35) ||
3821                  (using_tlb&&((signed int)constmap[i][rs]+offset)>=(signed int)0xC0000000))
3822               #endif
3823               emit_movimm(constmap[i][rs]+offset,ra);
3824             }
3825           } // else did it in the previous cycle
3826         } // else load_consts already did it
3827       }
3828       if(offset&&!c&&rs1[i]) {
3829         if(rs>=0) {
3830           emit_addimm(rs,offset,ra);
3831         }else{
3832           emit_addimm(ra,offset,ra);
3833         }
3834       }
3835     }
3836   }
3837   // Preload constants for next instruction
3838   if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS) {
3839     int agr,ra;
3840     #ifndef HOST_IMM_ADDR32
3841     // Mapper entry
3842     agr=MGEN1+((i+1)&1);
3843     ra=get_reg(i_regs->regmap,agr);
3844     if(ra>=0) {
3845       int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
3846       int offset=imm[i+1];
3847       int c=(regs[i+1].wasconst>>rs)&1;
3848       if(c) {
3849         if(itype[i+1]==STORE||itype[i+1]==STORELR||opcode[i+1]==0x39||opcode[i+1]==0x3D) {
3850           // Stores to memory go thru the mapper to detect self-modifying
3851           // code, loads don't.
3852           if((unsigned int)(constmap[i+1][rs]+offset)>=0xC0000000 ||
3853              (unsigned int)(constmap[i+1][rs]+offset)<0x80800000 )
3854             generate_map_const(constmap[i+1][rs]+offset,ra);
3855         }else{
3856           if((signed int)(constmap[i+1][rs]+offset)>=(signed int)0xC0000000)
3857             generate_map_const(constmap[i+1][rs]+offset,ra);
3858         }
3859       }
3860       /*else if(rs1[i]==0) {
3861         generate_map_const(offset,ra);
3862       }*/
3863     }
3864     #endif
3865     // Actual address
3866     agr=AGEN1+((i+1)&1);
3867     ra=get_reg(i_regs->regmap,agr);
3868     if(ra>=0) {
3869       int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
3870       int offset=imm[i+1];
3871       int c=(regs[i+1].wasconst>>rs)&1;
3872       if(c&&(rs1[i+1]!=rt1[i+1]||itype[i+1]!=LOAD)) {
3873         if (opcode[i+1]==0x22||opcode[i+1]==0x26) {
3874           emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR
3875         }else if (opcode[i+1]==0x1a||opcode[i+1]==0x1b) {
3876           emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFF8,ra); // LDL/LDR
3877         }else{
3878           #ifdef HOST_IMM_ADDR32
3879           if((itype[i+1]!=LOAD&&opcode[i+1]!=0x31&&opcode[i+1]!=0x35) ||
3880              (using_tlb&&((signed int)constmap[i+1][rs]+offset)>=(signed int)0xC0000000))
3881           #endif
3882           emit_movimm(constmap[i+1][rs]+offset,ra);
3883         }
3884       }
3885       else if(rs1[i+1]==0) {
3886         // Using r0 as a base address
3887         if (opcode[i+1]==0x22||opcode[i+1]==0x26) {
3888           emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR
3889         }else if (opcode[i+1]==0x1a||opcode[i+1]==0x1b) {
3890           emit_movimm(offset&0xFFFFFFF8,ra); // LDL/LDR
3891         }else{
3892           emit_movimm(offset,ra);
3893         }
3894       }
3895     }
3896   }
3897 }
3898
3899 int get_final_value(int hr, int i, int *value)
3900 {
3901   int reg=regs[i].regmap[hr];
3902   while(i<slen-1) {
3903     if(regs[i+1].regmap[hr]!=reg) break;
3904     if(!((regs[i+1].isconst>>hr)&1)) break;
3905     if(bt[i+1]) break;
3906     i++;
3907   }
3908   if(i<slen-1) {
3909     if(itype[i]==UJUMP||itype[i]==RJUMP||itype[i]==CJUMP||itype[i]==SJUMP) {
3910       *value=constmap[i][hr];
3911       return 1;
3912     }
3913     if(!bt[i+1]) {
3914       if(itype[i+1]==UJUMP||itype[i+1]==RJUMP||itype[i+1]==CJUMP||itype[i+1]==SJUMP) {
3915         // Load in delay slot, out-of-order execution
3916         if(itype[i+2]==LOAD&&rs1[i+2]==reg&&rt1[i+2]==reg&&((regs[i+1].wasconst>>hr)&1))
3917         {
3918           #ifdef HOST_IMM_ADDR32
3919           if(!using_tlb||((signed int)constmap[i][hr]+imm[i+2])<(signed int)0xC0000000) return 0;
3920           #endif
3921           // Precompute load address
3922           *value=constmap[i][hr]+imm[i+2];
3923           return 1;
3924         }
3925       }
3926       if(itype[i+1]==LOAD&&rs1[i+1]==reg&&rt1[i+1]==reg)
3927       {
3928         #ifdef HOST_IMM_ADDR32
3929         if(!using_tlb||((signed int)constmap[i][hr]+imm[i+1])<(signed int)0xC0000000) return 0;
3930         #endif
3931         // Precompute load address
3932         *value=constmap[i][hr]+imm[i+1];
3933         //printf("c=%x imm=%x\n",(int)constmap[i][hr],imm[i+1]);
3934         return 1;
3935       }
3936     }
3937   }
3938   *value=constmap[i][hr];
3939   //printf("c=%x\n",(int)constmap[i][hr]);
3940   if(i==slen-1) return 1;
3941   if(reg<64) {
3942     return !((unneeded_reg[i+1]>>reg)&1);
3943   }else{
3944     return !((unneeded_reg_upper[i+1]>>reg)&1);
3945   }
3946 }
3947
3948 // Load registers with known constants
3949 void load_consts(signed char pre[],signed char regmap[],int is32,int i)
3950 {
3951   int hr;
3952   // Load 32-bit regs
3953   for(hr=0;hr<HOST_REGS;hr++) {
3954     if(hr!=EXCLUDE_REG&&regmap[hr]>=0) {
3955       //if(entry[hr]!=regmap[hr]) {
3956       if(i==0||!((regs[i-1].isconst>>hr)&1)||pre[hr]!=regmap[hr]||bt[i]) {
3957         if(((regs[i].isconst>>hr)&1)&&regmap[hr]<64&&regmap[hr]>0) {
3958           int value;
3959           if(get_final_value(hr,i,&value)) {
3960             if(value==0) {
3961               emit_zeroreg(hr);
3962             }
3963             else {
3964               emit_movimm(value,hr);
3965             }
3966           }
3967         }
3968       }
3969     }
3970   }
3971   // Load 64-bit regs
3972   for(hr=0;hr<HOST_REGS;hr++) {
3973     if(hr!=EXCLUDE_REG&&regmap[hr]>=0) {
3974       //if(entry[hr]!=regmap[hr]) {
3975       if(i==0||!((regs[i-1].isconst>>hr)&1)||pre[hr]!=regmap[hr]||bt[i]) {
3976         if(((regs[i].isconst>>hr)&1)&&regmap[hr]>64) {
3977           if((is32>>(regmap[hr]&63))&1) {
3978             int lr=get_reg(regmap,regmap[hr]-64);
3979             assert(lr>=0);
3980             emit_sarimm(lr,31,hr);
3981           }
3982           else
3983           {
3984             int value;
3985             if(get_final_value(hr,i,&value)) {
3986               if(value==0) {
3987                 emit_zeroreg(hr);
3988               }
3989               else {
3990                 emit_movimm(value,hr);
3991               }
3992             }
3993           }
3994         }
3995       }
3996     }
3997   }
3998 }
3999 void load_all_consts(signed char regmap[],int is32,u_int dirty,int i)
4000 {
4001   int hr;
4002   // Load 32-bit regs
4003   for(hr=0;hr<HOST_REGS;hr++) {
4004     if(hr!=EXCLUDE_REG&&regmap[hr]>=0&&((dirty>>hr)&1)) {
4005       if(((regs[i].isconst>>hr)&1)&&regmap[hr]<64&&regmap[hr]>0) {
4006         int value=constmap[i][hr];
4007         if(value==0) {
4008           emit_zeroreg(hr);
4009         }
4010         else {
4011           emit_movimm(value,hr);
4012         }
4013       }
4014     }
4015   }
4016   // Load 64-bit regs
4017   for(hr=0;hr<HOST_REGS;hr++) {
4018     if(hr!=EXCLUDE_REG&&regmap[hr]>=0&&((dirty>>hr)&1)) {
4019       if(((regs[i].isconst>>hr)&1)&&regmap[hr]>64) {
4020         if((is32>>(regmap[hr]&63))&1) {
4021           int lr=get_reg(regmap,regmap[hr]-64);
4022           assert(lr>=0);
4023           emit_sarimm(lr,31,hr);
4024         }
4025         else
4026         {
4027           int value=constmap[i][hr];
4028           if(value==0) {
4029             emit_zeroreg(hr);
4030           }
4031           else {
4032             emit_movimm(value,hr);
4033           }
4034         }
4035       }
4036     }
4037   }
4038 }
4039
4040 // Write out all dirty registers (except cycle count)
4041 void wb_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty)
4042 {
4043   int hr;
4044   for(hr=0;hr<HOST_REGS;hr++) {
4045     if(hr!=EXCLUDE_REG) {
4046       if(i_regmap[hr]>0) {
4047         if(i_regmap[hr]!=CCREG) {
4048           if((i_dirty>>hr)&1) {
4049             if(i_regmap[hr]<64) {
4050               emit_storereg(i_regmap[hr],hr);
4051               if( ((i_is32>>i_regmap[hr])&1) ) {
4052                 #ifdef DESTRUCTIVE_WRITEBACK
4053                 emit_sarimm(hr,31,hr);
4054                 emit_storereg(i_regmap[hr]|64,hr);
4055                 #else
4056                 emit_sarimm(hr,31,HOST_TEMPREG);
4057                 emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
4058                 #endif
4059               }
4060             }else{
4061               if( !((i_is32>>(i_regmap[hr]&63))&1) ) {
4062                 emit_storereg(i_regmap[hr],hr);
4063               }
4064             }
4065           }
4066         }
4067       }
4068     }
4069   }
4070 }
4071 // Write out dirty registers that we need to reload (pair with load_needed_regs)
4072 // This writes the registers not written by store_regs_bt
4073 void wb_needed_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4074 {
4075   int hr;
4076   int t=(addr-start)>>2;
4077   for(hr=0;hr<HOST_REGS;hr++) {
4078     if(hr!=EXCLUDE_REG) {
4079       if(i_regmap[hr]>0) {
4080         if(i_regmap[hr]!=CCREG) {
4081           if(i_regmap[hr]==regs[t].regmap_entry[hr] && ((regs[t].dirty>>hr)&1) && !(((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) {
4082             if((i_dirty>>hr)&1) {
4083               if(i_regmap[hr]<64) {
4084                 emit_storereg(i_regmap[hr],hr);
4085                 if( ((i_is32>>i_regmap[hr])&1) ) {
4086                   #ifdef DESTRUCTIVE_WRITEBACK
4087                   emit_sarimm(hr,31,hr);
4088                   emit_storereg(i_regmap[hr]|64,hr);
4089                   #else
4090                   emit_sarimm(hr,31,HOST_TEMPREG);
4091                   emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
4092                   #endif
4093                 }
4094               }else{
4095                 if( !((i_is32>>(i_regmap[hr]&63))&1) ) {
4096                   emit_storereg(i_regmap[hr],hr);
4097                 }
4098               }
4099             }
4100           }
4101         }
4102       }
4103     }
4104   }
4105 }
4106
4107 // Load all registers (except cycle count)
4108 void load_all_regs(signed char i_regmap[])
4109 {
4110   int hr;
4111   for(hr=0;hr<HOST_REGS;hr++) {
4112     if(hr!=EXCLUDE_REG) {
4113       if(i_regmap[hr]==0) {
4114         emit_zeroreg(hr);
4115       }
4116       else
4117       if(i_regmap[hr]>0 && i_regmap[hr]!=CCREG)
4118       {
4119         emit_loadreg(i_regmap[hr],hr);
4120       }
4121     }
4122   }
4123 }
4124
4125 // Load all current registers also needed by next instruction
4126 void load_needed_regs(signed char i_regmap[],signed char next_regmap[])
4127 {
4128   int hr;
4129   for(hr=0;hr<HOST_REGS;hr++) {
4130     if(hr!=EXCLUDE_REG) {
4131       if(get_reg(next_regmap,i_regmap[hr])>=0) {
4132         if(i_regmap[hr]==0) {
4133           emit_zeroreg(hr);
4134         }
4135         else
4136         if(i_regmap[hr]>0 && i_regmap[hr]!=CCREG)
4137         {
4138           emit_loadreg(i_regmap[hr],hr);
4139         }
4140       }
4141     }
4142   }
4143 }
4144
4145 // Load all regs, storing cycle count if necessary
4146 void load_regs_entry(int t)
4147 {
4148   int hr;
4149   if(is_ds[t]) emit_addimm(HOST_CCREG,CLOCK_DIVIDER,HOST_CCREG);
4150   else if(ccadj[t]) emit_addimm(HOST_CCREG,-ccadj[t]*CLOCK_DIVIDER,HOST_CCREG);
4151   if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) {
4152     emit_storereg(CCREG,HOST_CCREG);
4153   }
4154   // Load 32-bit regs
4155   for(hr=0;hr<HOST_REGS;hr++) {
4156     if(regs[t].regmap_entry[hr]>=0&&regs[t].regmap_entry[hr]<64) {
4157       if(regs[t].regmap_entry[hr]==0) {
4158         emit_zeroreg(hr);
4159       }
4160       else if(regs[t].regmap_entry[hr]!=CCREG)
4161       {
4162         emit_loadreg(regs[t].regmap_entry[hr],hr);
4163       }
4164     }
4165   }
4166   // Load 64-bit regs
4167   for(hr=0;hr<HOST_REGS;hr++) {
4168     if(regs[t].regmap_entry[hr]>=64) {
4169       assert(regs[t].regmap_entry[hr]!=64);
4170       if((regs[t].was32>>(regs[t].regmap_entry[hr]&63))&1) {
4171         int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64);
4172         if(lr<0) {
4173           emit_loadreg(regs[t].regmap_entry[hr],hr);
4174         }
4175         else
4176         {
4177           emit_sarimm(lr,31,hr);
4178         }
4179       }
4180       else
4181       {
4182         emit_loadreg(regs[t].regmap_entry[hr],hr);
4183       }
4184     }
4185   }
4186 }
4187
4188 // Store dirty registers prior to branch
4189 void store_regs_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4190 {
4191   if(internal_branch(i_is32,addr))
4192   {
4193     int t=(addr-start)>>2;
4194     int hr;
4195     for(hr=0;hr<HOST_REGS;hr++) {
4196       if(hr!=EXCLUDE_REG) {
4197         if(i_regmap[hr]>0 && i_regmap[hr]!=CCREG) {
4198           if(i_regmap[hr]!=regs[t].regmap_entry[hr] || !((regs[t].dirty>>hr)&1) || (((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) {
4199             if((i_dirty>>hr)&1) {
4200               if(i_regmap[hr]<64) {
4201                 if(!((unneeded_reg[t]>>i_regmap[hr])&1)) {
4202                   emit_storereg(i_regmap[hr],hr);
4203                   if( ((i_is32>>i_regmap[hr])&1) && !((unneeded_reg_upper[t]>>i_regmap[hr])&1) ) {
4204                     #ifdef DESTRUCTIVE_WRITEBACK
4205                     emit_sarimm(hr,31,hr);
4206                     emit_storereg(i_regmap[hr]|64,hr);
4207                     #else
4208                     emit_sarimm(hr,31,HOST_TEMPREG);
4209                     emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
4210                     #endif
4211                   }
4212                 }
4213               }else{
4214                 if( !((i_is32>>(i_regmap[hr]&63))&1) && !((unneeded_reg_upper[t]>>(i_regmap[hr]&63))&1) ) {
4215                   emit_storereg(i_regmap[hr],hr);
4216                 }
4217               }
4218             }
4219           }
4220         }
4221       }
4222     }
4223   }
4224   else
4225   {
4226     // Branch out of this block, write out all dirty regs
4227     wb_dirtys(i_regmap,i_is32,i_dirty);
4228   }
4229 }
4230
4231 // Load all needed registers for branch target
4232 void load_regs_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4233 {
4234   //if(addr>=start && addr<(start+slen*4))
4235   if(internal_branch(i_is32,addr))
4236   {
4237     int t=(addr-start)>>2;
4238     int hr;
4239     // Store the cycle count before loading something else
4240     if(i_regmap[HOST_CCREG]!=CCREG) {
4241       assert(i_regmap[HOST_CCREG]==-1);
4242     }
4243     if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) {
4244       emit_storereg(CCREG,HOST_CCREG);
4245     }
4246     // Load 32-bit regs
4247     for(hr=0;hr<HOST_REGS;hr++) {
4248       if(hr!=EXCLUDE_REG&&regs[t].regmap_entry[hr]>=0&&regs[t].regmap_entry[hr]<64) {
4249         #ifdef DESTRUCTIVE_WRITEBACK
4250         if(i_regmap[hr]!=regs[t].regmap_entry[hr] || ( !((regs[t].dirty>>hr)&1) && ((i_dirty>>hr)&1) && (((i_is32&~unneeded_reg_upper[t])>>i_regmap[hr])&1) ) || (((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) {
4251         #else
4252         if(i_regmap[hr]!=regs[t].regmap_entry[hr] ) {
4253         #endif
4254           if(regs[t].regmap_entry[hr]==0) {
4255             emit_zeroreg(hr);
4256           }
4257           else if(regs[t].regmap_entry[hr]!=CCREG)
4258           {
4259             emit_loadreg(regs[t].regmap_entry[hr],hr);
4260           }
4261         }
4262       }
4263     }
4264     //Load 64-bit regs
4265     for(hr=0;hr<HOST_REGS;hr++) {
4266       if(hr!=EXCLUDE_REG&&regs[t].regmap_entry[hr]>=64) {
4267         if(i_regmap[hr]!=regs[t].regmap_entry[hr]) {
4268           assert(regs[t].regmap_entry[hr]!=64);
4269           if((i_is32>>(regs[t].regmap_entry[hr]&63))&1) {
4270             int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64);
4271             if(lr<0) {
4272               emit_loadreg(regs[t].regmap_entry[hr],hr);
4273             }
4274             else
4275             {
4276               emit_sarimm(lr,31,hr);
4277             }
4278           }
4279           else
4280           {
4281             emit_loadreg(regs[t].regmap_entry[hr],hr);
4282           }
4283         }
4284         else if((i_is32>>(regs[t].regmap_entry[hr]&63))&1) {
4285           int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64);
4286           assert(lr>=0);
4287           emit_sarimm(lr,31,hr);
4288         }
4289       }
4290     }
4291   }
4292 }
4293
4294 int match_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4295 {
4296   if(addr>=start && addr<start+slen*4-4)
4297   {
4298     int t=(addr-start)>>2;
4299     int hr;
4300     if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) return 0;
4301     for(hr=0;hr<HOST_REGS;hr++)
4302     {
4303       if(hr!=EXCLUDE_REG)
4304       {
4305         if(i_regmap[hr]!=regs[t].regmap_entry[hr])
4306         {
4307           if(regs[t].regmap_entry[hr]!=-1)
4308           {
4309             return 0;
4310           }
4311           else
4312           if((i_dirty>>hr)&1)
4313           {
4314             if(i_regmap[hr]<64)
4315             {
4316               if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4317                 return 0;
4318             }
4319             else
4320             {
4321               if(!((unneeded_reg_upper[t]>>(i_regmap[hr]&63))&1))
4322                 return 0;
4323             }
4324           }
4325         }
4326         else // Same register but is it 32-bit or dirty?
4327         if(i_regmap[hr]>=0)
4328         {
4329           if(!((regs[t].dirty>>hr)&1))
4330           {
4331             if((i_dirty>>hr)&1)
4332             {
4333               if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4334               {
4335                 //printf("%x: dirty no match\n",addr);
4336                 return 0;
4337               }
4338             }
4339           }
4340           if((((regs[t].was32^i_is32)&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)
4341           {
4342             //printf("%x: is32 no match\n",addr);
4343             return 0;
4344           }
4345         }
4346       }
4347     }
4348     //if(is32[t]&~unneeded_reg_upper[t]&~i_is32) return 0;
4349     if(requires_32bit[t]&~i_is32) return 0;
4350     // Delay slots are not valid branch targets
4351     //if(t>0&&(itype[t-1]==RJUMP||itype[t-1]==UJUMP||itype[t-1]==CJUMP||itype[t-1]==SJUMP||itype[t-1]==FJUMP)) return 0;
4352     // Delay slots require additional processing, so do not match
4353     if(is_ds[t]) return 0;
4354   }
4355   else
4356   {
4357     int hr;
4358     for(hr=0;hr<HOST_REGS;hr++)
4359     {
4360       if(hr!=EXCLUDE_REG)
4361       {
4362         if(i_regmap[hr]>=0)
4363         {
4364           if(hr!=HOST_CCREG||i_regmap[hr]!=CCREG)
4365           {
4366             if((i_dirty>>hr)&1)
4367             {
4368               return 0;
4369             }
4370           }
4371         }
4372       }
4373     }
4374   }
4375   return 1;
4376 }
4377
4378 // Used when a branch jumps into the delay slot of another branch
4379 void ds_assemble_entry(int i)
4380 {
4381   int t=(ba[i]-start)>>2;
4382   if(!instr_addr[t]) instr_addr[t]=(u_int)out;
4383   assem_debug("Assemble delay slot at %x\n",ba[i]);
4384   assem_debug("<->\n");
4385   if(regs[t].regmap_entry[HOST_CCREG]==CCREG&&regs[t].regmap[HOST_CCREG]!=CCREG)
4386     wb_register(CCREG,regs[t].regmap_entry,regs[t].wasdirty,regs[t].was32);
4387   load_regs(regs[t].regmap_entry,regs[t].regmap,regs[t].was32,rs1[t],rs2[t]);
4388   address_generation(t,&regs[t],regs[t].regmap_entry);
4389   if(itype[t]==STORE||itype[t]==STORELR||(opcode[t]&0x3b)==0x39)
4390     load_regs(regs[t].regmap_entry,regs[t].regmap,regs[t].was32,INVCP,INVCP);
4391   cop1_usable=0;
4392   is_delayslot=0;
4393   switch(itype[t]) {
4394     case ALU:
4395       alu_assemble(t,&regs[t]);break;
4396     case IMM16:
4397       imm16_assemble(t,&regs[t]);break;
4398     case SHIFT:
4399       shift_assemble(t,&regs[t]);break;
4400     case SHIFTIMM:
4401       shiftimm_assemble(t,&regs[t]);break;
4402     case LOAD:
4403       load_assemble(t,&regs[t]);break;
4404     case LOADLR:
4405       loadlr_assemble(t,&regs[t]);break;
4406     case STORE:
4407       store_assemble(t,&regs[t]);break;
4408     case STORELR:
4409       storelr_assemble(t,&regs[t]);break;
4410     case COP0:
4411       cop0_assemble(t,&regs[t]);break;
4412     case COP1:
4413       cop1_assemble(t,&regs[t]);break;
4414     case C1LS:
4415       c1ls_assemble(t,&regs[t]);break;
4416     case FCONV:
4417       fconv_assemble(t,&regs[t]);break;
4418     case FLOAT:
4419       float_assemble(t,&regs[t]);break;
4420     case FCOMP:
4421       fcomp_assemble(t,&regs[t]);break;
4422     case MULTDIV:
4423       multdiv_assemble(t,&regs[t]);break;
4424     case MOV:
4425       mov_assemble(t,&regs[t]);break;
4426     case SYSCALL:
4427     case SPAN:
4428     case UJUMP:
4429     case RJUMP:
4430     case CJUMP:
4431     case SJUMP:
4432     case FJUMP:
4433       printf("Jump in the delay slot.  This is probably a bug.\n");
4434   }
4435   store_regs_bt(regs[t].regmap,regs[t].is32,regs[t].dirty,ba[i]+4);
4436   load_regs_bt(regs[t].regmap,regs[t].is32,regs[t].dirty,ba[i]+4);
4437   if(internal_branch(regs[t].is32,ba[i]+4))
4438     assem_debug("branch: internal\n");
4439   else
4440     assem_debug("branch: external\n");
4441   assert(internal_branch(regs[t].is32,ba[i]+4));
4442   add_to_linker((int)out,ba[i]+4,internal_branch(regs[t].is32,ba[i]+4));
4443   emit_jmp(0);
4444 }
4445
4446 void do_cc(int i,signed char i_regmap[],int *adj,int addr,int taken,int invert)
4447 {
4448   int count;
4449   int jaddr;
4450   int idle=0;
4451   if(itype[i]==RJUMP)
4452   {
4453     *adj=0;
4454   }
4455   //if(ba[i]>=start && ba[i]<(start+slen*4))
4456   if(internal_branch(branch_regs[i].is32,ba[i]))
4457   {
4458     int t=(ba[i]-start)>>2;
4459     if(is_ds[t]) *adj=-1; // Branch into delay slot adds an extra cycle
4460     else *adj=ccadj[t];
4461   }
4462   else
4463   {
4464     *adj=0;
4465   }
4466   count=ccadj[i];
4467   if(taken==TAKEN && i==(ba[i]-start)>>2 && source[i+1]==0) {
4468     // Idle loop
4469     if(count&1) emit_addimm_and_set_flags(2*(count+2),HOST_CCREG);
4470     idle=(int)out;
4471     //emit_subfrommem(&idlecount,HOST_CCREG); // Count idle cycles
4472     emit_andimm(HOST_CCREG,3,HOST_CCREG);
4473     jaddr=(int)out;
4474     emit_jmp(0);
4475   }
4476   else if(*adj==0||invert) {
4477     emit_addimm_and_set_flags(CLOCK_DIVIDER*(count+2),HOST_CCREG);
4478     jaddr=(int)out;
4479     emit_jns(0);
4480   }
4481   else
4482   {
4483     emit_cmpimm(HOST_CCREG,-2*(count+2));
4484     jaddr=(int)out;
4485     emit_jns(0);
4486   }
4487   add_stub(CC_STUB,jaddr,idle?idle:(int)out,(*adj==0||invert||idle)?0:(count+2),i,addr,taken,0);
4488 }
4489
4490 void do_ccstub(int n)
4491 {
4492   literal_pool(256);
4493   assem_debug("do_ccstub %x\n",start+stubs[n][4]*4);
4494   set_jump_target(stubs[n][1],(int)out);
4495   int i=stubs[n][4];
4496   if(stubs[n][6]==NULLDS) {
4497     // Delay slot instruction is nullified ("likely" branch)
4498     wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty);
4499   }
4500   else if(stubs[n][6]!=TAKEN) {
4501     wb_dirtys(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty);
4502   }
4503   else {
4504     if(internal_branch(branch_regs[i].is32,ba[i]))
4505       wb_needed_dirtys(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
4506   }
4507   if(stubs[n][5]!=-1)
4508   {
4509     // Save PC as return address
4510     emit_movimm(stubs[n][5],EAX);
4511     emit_writeword(EAX,(int)&pcaddr);
4512   }
4513   else
4514   {
4515     // Return address depends on which way the branch goes
4516     if(itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
4517     {
4518       int s1l=get_reg(branch_regs[i].regmap,rs1[i]);
4519       int s1h=get_reg(branch_regs[i].regmap,rs1[i]|64);
4520       int s2l=get_reg(branch_regs[i].regmap,rs2[i]);
4521       int s2h=get_reg(branch_regs[i].regmap,rs2[i]|64);
4522       if(rs1[i]==0)
4523       {
4524         s1l=s2l;s1h=s2h;
4525         s2l=s2h=-1;
4526       }
4527       else if(rs2[i]==0)
4528       {
4529         s2l=s2h=-1;
4530       }
4531       if((branch_regs[i].is32>>rs1[i])&(branch_regs[i].is32>>rs2[i])&1) {
4532         s1h=s2h=-1;
4533       }
4534       assert(s1l>=0);
4535       #ifdef DESTRUCTIVE_WRITEBACK
4536       if(rs1[i]) {
4537         if((branch_regs[i].dirty>>s1l)&(branch_regs[i].is32>>rs1[i])&1)
4538           emit_loadreg(rs1[i],s1l);
4539       }
4540       else {
4541         if((branch_regs[i].dirty>>s1l)&(branch_regs[i].is32>>rs2[i])&1)
4542           emit_loadreg(rs2[i],s1l);
4543       }
4544       if(s2l>=0)
4545         if((branch_regs[i].dirty>>s2l)&(branch_regs[i].is32>>rs2[i])&1)
4546           emit_loadreg(rs2[i],s2l);
4547       #endif
4548       int hr=0;
4549       int addr,alt,ntaddr;
4550       while(hr<HOST_REGS)
4551       {
4552         if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
4553            (branch_regs[i].regmap[hr]&63)!=rs1[i] &&
4554            (branch_regs[i].regmap[hr]&63)!=rs2[i] )
4555         {
4556           addr=hr++;break;
4557         }
4558         hr++;
4559       }
4560       while(hr<HOST_REGS)
4561       {
4562         if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
4563            (branch_regs[i].regmap[hr]&63)!=rs1[i] &&
4564            (branch_regs[i].regmap[hr]&63)!=rs2[i] )
4565         {
4566           alt=hr++;break;
4567         }
4568         hr++;
4569       }
4570       if((opcode[i]&0x2E)==6) // BLEZ/BGTZ needs another register
4571       {
4572         while(hr<HOST_REGS)
4573         {
4574           if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
4575              (branch_regs[i].regmap[hr]&63)!=rs1[i] &&
4576              (branch_regs[i].regmap[hr]&63)!=rs2[i] )
4577           {
4578             ntaddr=hr;break;
4579           }
4580           hr++;
4581         }
4582         assert(hr<HOST_REGS);
4583       }
4584       if((opcode[i]&0x2f)==4) // BEQ
4585       {
4586         #ifdef HAVE_CMOV_IMM
4587         if(s1h<0) {
4588           if(s2l>=0) emit_cmp(s1l,s2l);
4589           else emit_test(s1l,s1l);
4590           emit_cmov2imm_e_ne_compact(ba[i],start+i*4+8,addr);
4591         }
4592         else
4593         #endif
4594         {
4595           emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
4596           if(s1h>=0) {
4597             if(s2h>=0) emit_cmp(s1h,s2h);
4598             else emit_test(s1h,s1h);
4599             emit_cmovne_reg(alt,addr);
4600           }
4601           if(s2l>=0) emit_cmp(s1l,s2l);
4602           else emit_test(s1l,s1l);
4603           emit_cmovne_reg(alt,addr);
4604         }
4605       }
4606       if((opcode[i]&0x2f)==5) // BNE
4607       {
4608         #ifdef HAVE_CMOV_IMM
4609         if(s1h<0) {
4610           if(s2l>=0) emit_cmp(s1l,s2l);
4611           else emit_test(s1l,s1l);
4612           emit_cmov2imm_e_ne_compact(start+i*4+8,ba[i],addr);
4613         }
4614         else
4615         #endif
4616         {
4617           emit_mov2imm_compact(start+i*4+8,addr,ba[i],alt);
4618           if(s1h>=0) {
4619             if(s2h>=0) emit_cmp(s1h,s2h);
4620             else emit_test(s1h,s1h);
4621             emit_cmovne_reg(alt,addr);
4622           }
4623           if(s2l>=0) emit_cmp(s1l,s2l);
4624           else emit_test(s1l,s1l);
4625           emit_cmovne_reg(alt,addr);
4626         }
4627       }
4628       if((opcode[i]&0x2f)==6) // BLEZ
4629       {
4630         //emit_movimm(ba[i],alt);
4631         //emit_movimm(start+i*4+8,addr);
4632         emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
4633         emit_cmpimm(s1l,1);
4634         if(s1h>=0) emit_mov(addr,ntaddr);
4635         emit_cmovl_reg(alt,addr);
4636         if(s1h>=0) {
4637           emit_test(s1h,s1h);
4638           emit_cmovne_reg(ntaddr,addr);
4639           emit_cmovs_reg(alt,addr);
4640         }
4641       }
4642       if((opcode[i]&0x2f)==7) // BGTZ
4643       {
4644         //emit_movimm(ba[i],addr);
4645         //emit_movimm(start+i*4+8,ntaddr);
4646         emit_mov2imm_compact(ba[i],addr,start+i*4+8,ntaddr);
4647         emit_cmpimm(s1l,1);
4648         if(s1h>=0) emit_mov(addr,alt);
4649         emit_cmovl_reg(ntaddr,addr);
4650         if(s1h>=0) {
4651           emit_test(s1h,s1h);
4652           emit_cmovne_reg(alt,addr);
4653           emit_cmovs_reg(ntaddr,addr);
4654         }
4655       }
4656       if((opcode[i]==1)&&(opcode2[i]&0x2D)==0) // BLTZ
4657       {
4658         //emit_movimm(ba[i],alt);
4659         //emit_movimm(start+i*4+8,addr);
4660         emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
4661         if(s1h>=0) emit_test(s1h,s1h);
4662         else emit_test(s1l,s1l);
4663         emit_cmovs_reg(alt,addr);
4664       }
4665       if((opcode[i]==1)&&(opcode2[i]&0x2D)==1) // BGEZ
4666       {
4667         //emit_movimm(ba[i],addr);
4668         //emit_movimm(start+i*4+8,alt);
4669         emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
4670         if(s1h>=0) emit_test(s1h,s1h);
4671         else emit_test(s1l,s1l);
4672         emit_cmovs_reg(alt,addr);
4673       }
4674       if(opcode[i]==0x11 && opcode2[i]==0x08 ) {
4675         if(source[i]&0x10000) // BC1T
4676         {
4677           //emit_movimm(ba[i],alt);
4678           //emit_movimm(start+i*4+8,addr);
4679           emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
4680           emit_testimm(s1l,0x800000);
4681           emit_cmovne_reg(alt,addr);
4682         }
4683         else // BC1F
4684         {
4685           //emit_movimm(ba[i],addr);
4686           //emit_movimm(start+i*4+8,alt);
4687           emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
4688           emit_testimm(s1l,0x800000);
4689           emit_cmovne_reg(alt,addr);
4690         }
4691       }
4692       emit_writeword(addr,(int)&pcaddr);
4693     }
4694     else
4695     if(itype[i]==RJUMP)
4696     {
4697       int r=get_reg(branch_regs[i].regmap,rs1[i]);
4698       if(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]) {
4699         r=get_reg(branch_regs[i].regmap,RTEMP);
4700       }
4701       emit_writeword(r,(int)&pcaddr);
4702     }
4703     else {printf("Unknown branch type in do_ccstub\n");exit(1);}
4704   }
4705   // Update cycle count
4706   assert(branch_regs[i].regmap[HOST_CCREG]==CCREG||branch_regs[i].regmap[HOST_CCREG]==-1);
4707   if(stubs[n][3]) emit_addimm(HOST_CCREG,CLOCK_DIVIDER*stubs[n][3],HOST_CCREG);
4708   emit_call((int)cc_interrupt);
4709   if(stubs[n][3]) emit_addimm(HOST_CCREG,-CLOCK_DIVIDER*stubs[n][3],HOST_CCREG);
4710   if(stubs[n][6]==TAKEN) {
4711     if(internal_branch(branch_regs[i].is32,ba[i]))
4712       load_needed_regs(branch_regs[i].regmap,regs[(ba[i]-start)>>2].regmap_entry);
4713     else if(itype[i]==RJUMP) {
4714       if(get_reg(branch_regs[i].regmap,RTEMP)>=0)
4715         emit_readword((int)&pcaddr,get_reg(branch_regs[i].regmap,RTEMP));
4716       else
4717         emit_loadreg(rs1[i],get_reg(branch_regs[i].regmap,rs1[i]));
4718     }
4719   }else if(stubs[n][6]==NOTTAKEN) {
4720     if(i<slen-2) load_needed_regs(branch_regs[i].regmap,regmap_pre[i+2]);
4721     else load_all_regs(branch_regs[i].regmap);
4722   }else if(stubs[n][6]==NULLDS) {
4723     // Delay slot instruction is nullified ("likely" branch)
4724     if(i<slen-2) load_needed_regs(regs[i].regmap,regmap_pre[i+2]);
4725     else load_all_regs(regs[i].regmap);
4726   }else{
4727     load_all_regs(branch_regs[i].regmap);
4728   }
4729   emit_jmp(stubs[n][2]); // return address
4730
4731   /* This works but uses a lot of memory...
4732   emit_readword((int)&last_count,ECX);
4733   emit_add(HOST_CCREG,ECX,EAX);
4734   emit_writeword(EAX,(int)&Count);
4735   emit_call((int)gen_interupt);
4736   emit_readword((int)&Count,HOST_CCREG);
4737   emit_readword((int)&next_interupt,EAX);
4738   emit_readword((int)&pending_exception,EBX);
4739   emit_writeword(EAX,(int)&last_count);
4740   emit_sub(HOST_CCREG,EAX,HOST_CCREG);
4741   emit_test(EBX,EBX);
4742   int jne_instr=(int)out;
4743   emit_jne(0);
4744   if(stubs[n][3]) emit_addimm(HOST_CCREG,-2*stubs[n][3],HOST_CCREG);
4745   load_all_regs(branch_regs[i].regmap);
4746   emit_jmp(stubs[n][2]); // return address
4747   set_jump_target(jne_instr,(int)out);
4748   emit_readword((int)&pcaddr,EAX);
4749   // Call get_addr_ht instead of doing the hash table here.
4750   // This code is executed infrequently and takes up a lot of space
4751   // so smaller is better.
4752   emit_storereg(CCREG,HOST_CCREG);
4753   emit_pushreg(EAX);
4754   emit_call((int)get_addr_ht);
4755   emit_loadreg(CCREG,HOST_CCREG);
4756   emit_addimm(ESP,4,ESP);
4757   emit_jmpreg(EAX);*/
4758 }
4759
4760 add_to_linker(int addr,int target,int ext)
4761 {
4762   link_addr[linkcount][0]=addr;
4763   link_addr[linkcount][1]=target;
4764   link_addr[linkcount][2]=ext;
4765   linkcount++;
4766 }
4767
4768 void ujump_assemble(int i,struct regstat *i_regs)
4769 {
4770   signed char *i_regmap=i_regs->regmap;
4771   if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
4772   address_generation(i+1,i_regs,regs[i].regmap_entry);
4773   #ifdef REG_PREFETCH
4774   int temp=get_reg(branch_regs[i].regmap,PTEMP);
4775   if(rt1[i]==31&&temp>=0)
4776   {
4777     int return_address=start+i*4+8;
4778     if(get_reg(branch_regs[i].regmap,31)>0)
4779     if(i_regmap[temp]==PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
4780   }
4781   #endif
4782   ds_assemble(i+1,i_regs);
4783   uint64_t bc_unneeded=branch_regs[i].u;
4784   uint64_t bc_unneeded_upper=branch_regs[i].uu;
4785   bc_unneeded|=1|(1LL<<rt1[i]);
4786   bc_unneeded_upper|=1|(1LL<<rt1[i]);
4787   wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
4788                 bc_unneeded,bc_unneeded_upper);
4789   load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
4790   if(rt1[i]==31) {
4791     int rt;
4792     unsigned int return_address;
4793     assert(rt1[i+1]!=31);
4794     assert(rt2[i+1]!=31);
4795     rt=get_reg(branch_regs[i].regmap,31);
4796     assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
4797     //assert(rt>=0);
4798     return_address=start+i*4+8;
4799     if(rt>=0) {
4800       #ifdef USE_MINI_HT
4801       if(internal_branch(branch_regs[i].is32,return_address)) {
4802         int temp=rt+1;
4803         if(temp==EXCLUDE_REG||temp>=HOST_REGS||
4804            branch_regs[i].regmap[temp]>=0)
4805         {
4806           temp=get_reg(branch_regs[i].regmap,-1);
4807         }
4808         #ifdef HOST_TEMPREG
4809         if(temp<0) temp=HOST_TEMPREG;
4810         #endif
4811         if(temp>=0) do_miniht_insert(return_address,rt,temp);
4812         else emit_movimm(return_address,rt);
4813       }
4814       else
4815       #endif
4816       {
4817         #ifdef REG_PREFETCH
4818         if(temp>=0)
4819         {
4820           if(i_regmap[temp]!=PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
4821         }
4822         #endif
4823         emit_movimm(return_address,rt); // PC into link register
4824         #ifdef IMM_PREFETCH
4825         emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
4826         #endif
4827       }
4828     }
4829   }
4830   int cc,adj;
4831   cc=get_reg(branch_regs[i].regmap,CCREG);
4832   assert(cc==HOST_CCREG);
4833   store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
4834   #ifdef REG_PREFETCH
4835   if(rt1[i]==31&&temp>=0) emit_prefetchreg(temp);
4836   #endif
4837   do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
4838   if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
4839   load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
4840   if(internal_branch(branch_regs[i].is32,ba[i]))
4841     assem_debug("branch: internal\n");
4842   else
4843     assem_debug("branch: external\n");
4844   if(internal_branch(branch_regs[i].is32,ba[i])&&is_ds[(ba[i]-start)>>2]) {
4845     ds_assemble_entry(i);
4846   }
4847   else {
4848     add_to_linker((int)out,ba[i],internal_branch(branch_regs[i].is32,ba[i]));
4849     emit_jmp(0);
4850   }
4851 }
4852
4853 void rjump_assemble(int i,struct regstat *i_regs)
4854 {
4855   signed char *i_regmap=i_regs->regmap;
4856   int temp;
4857   int rs,cc,adj;
4858   rs=get_reg(branch_regs[i].regmap,rs1[i]);
4859   assert(rs>=0);
4860   if(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]) {
4861     // Delay slot abuse, make a copy of the branch address register
4862     temp=get_reg(branch_regs[i].regmap,RTEMP);
4863     assert(temp>=0);
4864     assert(regs[i].regmap[temp]==RTEMP);
4865     emit_mov(rs,temp);
4866     rs=temp;
4867   }
4868   address_generation(i+1,i_regs,regs[i].regmap_entry);
4869   #ifdef REG_PREFETCH
4870   if(rt1[i]==31)
4871   {
4872     if((temp=get_reg(branch_regs[i].regmap,PTEMP))>=0) {
4873       int return_address=start+i*4+8;
4874       if(i_regmap[temp]==PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
4875     }
4876   }
4877   #endif
4878   #ifdef USE_MINI_HT
4879   if(rs1[i]==31) {
4880     int rh=get_reg(regs[i].regmap,RHASH);
4881     if(rh>=0) do_preload_rhash(rh);
4882   }
4883   #endif
4884   ds_assemble(i+1,i_regs);
4885   uint64_t bc_unneeded=branch_regs[i].u;
4886   uint64_t bc_unneeded_upper=branch_regs[i].uu;
4887   bc_unneeded|=1|(1LL<<rt1[i]);
4888   bc_unneeded_upper|=1|(1LL<<rt1[i]);
4889   bc_unneeded&=~(1LL<<rs1[i]);
4890   wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
4891                 bc_unneeded,bc_unneeded_upper);
4892   load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],CCREG);
4893   if(rt1[i]==31) {
4894     int rt,return_address;
4895     assert(rt1[i+1]!=31);
4896     assert(rt2[i+1]!=31);
4897     rt=get_reg(branch_regs[i].regmap,31);
4898     assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
4899     assert(rt>=0);
4900     return_address=start+i*4+8;
4901     #ifdef REG_PREFETCH
4902     if(temp>=0)
4903     {
4904       if(i_regmap[temp]!=PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
4905     }
4906     #endif
4907     emit_movimm(return_address,rt); // PC into link register
4908     #ifdef IMM_PREFETCH
4909     emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
4910     #endif
4911   }
4912   cc=get_reg(branch_regs[i].regmap,CCREG);
4913   assert(cc==HOST_CCREG);
4914   #ifdef USE_MINI_HT
4915   int rh=get_reg(branch_regs[i].regmap,RHASH);
4916   int ht=get_reg(branch_regs[i].regmap,RHTBL);
4917   if(rs1[i]==31) {
4918     if(regs[i].regmap[rh]!=RHASH) do_preload_rhash(rh);
4919     do_preload_rhtbl(ht);
4920     do_rhash(rs,rh);
4921   }
4922   #endif
4923   store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,-1);
4924   #ifdef DESTRUCTIVE_WRITEBACK
4925   if((branch_regs[i].dirty>>rs)&(branch_regs[i].is32>>rs1[i])&1) {
4926     if(rs1[i]!=rt1[i+1]&&rs1[i]!=rt2[i+1]) {
4927       emit_loadreg(rs1[i],rs);
4928     }
4929   }
4930   #endif
4931   #ifdef REG_PREFETCH
4932   if(rt1[i]==31&&temp>=0) emit_prefetchreg(temp);
4933   #endif
4934   #ifdef USE_MINI_HT
4935   if(rs1[i]==31) {
4936     do_miniht_load(ht,rh);
4937   }
4938   #endif
4939   //do_cc(i,branch_regs[i].regmap,&adj,-1,TAKEN);
4940   //if(adj) emit_addimm(cc,2*(ccadj[i]+2-adj),cc); // ??? - Shouldn't happen
4941   //assert(adj==0);
4942   emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG);
4943   add_stub(CC_STUB,(int)out,jump_vaddr_reg[rs],0,i,-1,TAKEN,0);
4944   emit_jns(0);
4945   //load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,-1);
4946   #ifdef USE_MINI_HT
4947   if(rs1[i]==31) {
4948     do_miniht_jump(rs,rh,ht);
4949   }
4950   else
4951   #endif
4952   {
4953     //if(rs!=EAX) emit_mov(rs,EAX);
4954     //emit_jmp((int)jump_vaddr_eax);
4955     emit_jmp(jump_vaddr_reg[rs]);
4956   }
4957   /* Check hash table
4958   temp=!rs;
4959   emit_mov(rs,temp);
4960   emit_shrimm(rs,16,rs);
4961   emit_xor(temp,rs,rs);
4962   emit_movzwl_reg(rs,rs);
4963   emit_shlimm(rs,4,rs);
4964   emit_cmpmem_indexed((int)hash_table,rs,temp);
4965   emit_jne((int)out+14);
4966   emit_readword_indexed((int)hash_table+4,rs,rs);
4967   emit_jmpreg(rs);
4968   emit_cmpmem_indexed((int)hash_table+8,rs,temp);
4969   emit_addimm_no_flags(8,rs);
4970   emit_jeq((int)out-17);
4971   // No hit on hash table, call compiler
4972   emit_pushreg(temp);
4973 //DEBUG >
4974 #ifdef DEBUG_CYCLE_COUNT
4975   emit_readword((int)&last_count,ECX);
4976   emit_add(HOST_CCREG,ECX,HOST_CCREG);
4977   emit_readword((int)&next_interupt,ECX);
4978   emit_writeword(HOST_CCREG,(int)&Count);
4979   emit_sub(HOST_CCREG,ECX,HOST_CCREG);
4980   emit_writeword(ECX,(int)&last_count);
4981 #endif
4982 //DEBUG <
4983   emit_storereg(CCREG,HOST_CCREG);
4984   emit_call((int)get_addr);
4985   emit_loadreg(CCREG,HOST_CCREG);
4986   emit_addimm(ESP,4,ESP);
4987   emit_jmpreg(EAX);*/
4988   #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
4989   if(rt1[i]!=31&&i<slen-2&&(((u_int)out)&7)) emit_mov(13,13);
4990   #endif
4991 }
4992
4993 void cjump_assemble(int i,struct regstat *i_regs)
4994 {
4995   signed char *i_regmap=i_regs->regmap;
4996   int cc;
4997   int match;
4998   match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
4999   assem_debug("match=%d\n",match);
5000   int s1h,s1l,s2h,s2l;
5001   int prev_cop1_usable=cop1_usable;
5002   int unconditional=0,nop=0;
5003   int only32=0;
5004   int ooo=1;
5005   int invert=0;
5006   int internal=internal_branch(branch_regs[i].is32,ba[i]);
5007   if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
5008   if(likely[i]) ooo=0;
5009   if(!match) invert=1;
5010   #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5011   if(i>(ba[i]-start)>>2) invert=1;
5012   #endif
5013
5014   if(ooo)
5015     if((rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]))||
5016        (rs2[i]&&(rs2[i]==rt1[i+1]||rs2[i]==rt2[i+1])))
5017   {
5018     // Write-after-read dependency prevents out of order execution
5019     // First test branch condition, then execute delay slot, then branch
5020     ooo=0;
5021   }
5022
5023   if(ooo) {
5024     s1l=get_reg(branch_regs[i].regmap,rs1[i]);
5025     s1h=get_reg(branch_regs[i].regmap,rs1[i]|64);
5026     s2l=get_reg(branch_regs[i].regmap,rs2[i]);
5027     s2h=get_reg(branch_regs[i].regmap,rs2[i]|64);
5028   }
5029   else {
5030     s1l=get_reg(i_regmap,rs1[i]);
5031     s1h=get_reg(i_regmap,rs1[i]|64);
5032     s2l=get_reg(i_regmap,rs2[i]);
5033     s2h=get_reg(i_regmap,rs2[i]|64);
5034   }
5035   if(rs1[i]==0&&rs2[i]==0)
5036   {
5037     if(opcode[i]&1) nop=1;
5038     else unconditional=1;
5039     //assert(opcode[i]!=5);
5040     //assert(opcode[i]!=7);
5041     //assert(opcode[i]!=0x15);
5042     //assert(opcode[i]!=0x17);
5043   }
5044   else if(rs1[i]==0)
5045   {
5046     s1l=s2l;s1h=s2h;
5047     s2l=s2h=-1;
5048     only32=(regs[i].was32>>rs2[i])&1;
5049   }
5050   else if(rs2[i]==0)
5051   {
5052     s2l=s2h=-1;
5053     only32=(regs[i].was32>>rs1[i])&1;
5054   }
5055   else {
5056     only32=(regs[i].was32>>rs1[i])&(regs[i].was32>>rs2[i])&1;
5057   }
5058
5059   if(ooo) {
5060     // Out of order execution (delay slot first)
5061     //printf("OOOE\n");
5062     address_generation(i+1,i_regs,regs[i].regmap_entry);
5063     ds_assemble(i+1,i_regs);
5064     int adj;
5065     uint64_t bc_unneeded=branch_regs[i].u;
5066     uint64_t bc_unneeded_upper=branch_regs[i].uu;
5067     bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
5068     bc_unneeded_upper&=~((1LL<<us1[i])|(1LL<<us2[i]));
5069     bc_unneeded|=1;
5070     bc_unneeded_upper|=1;
5071     wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5072                   bc_unneeded,bc_unneeded_upper);
5073     load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],rs2[i]);
5074     load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5075     cc=get_reg(branch_regs[i].regmap,CCREG);
5076     assert(cc==HOST_CCREG);
5077     if(unconditional)
5078       store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5079     //do_cc(i,branch_regs[i].regmap,&adj,unconditional?ba[i]:-1,unconditional);
5080     //assem_debug("cycle count (adj)\n");
5081     if(unconditional) {
5082       do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5083       if(i!=(ba[i]-start)>>2 || source[i+1]!=0) {
5084         if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5085         load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5086         if(internal)
5087           assem_debug("branch: internal\n");
5088         else
5089           assem_debug("branch: external\n");
5090         if(internal&&is_ds[(ba[i]-start)>>2]) {
5091           ds_assemble_entry(i);
5092         }
5093         else {
5094           add_to_linker((int)out,ba[i],internal);
5095           emit_jmp(0);
5096         }
5097         #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5098         if(((u_int)out)&7) emit_addnop(0);
5099         #endif
5100       }
5101     }
5102     else if(nop) {
5103       emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc);
5104       int jaddr=(int)out;
5105       emit_jns(0);
5106       add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
5107     }
5108     else {
5109       int taken=0,nottaken=0,nottaken1=0;
5110       do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
5111       if(adj&&!invert) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5112       if(!only32)
5113       {
5114         assert(s1h>=0);
5115         if(opcode[i]==4) // BEQ
5116         {
5117           if(s2h>=0) emit_cmp(s1h,s2h);
5118           else emit_test(s1h,s1h);
5119           nottaken1=(int)out;
5120           emit_jne(1);
5121         }
5122         if(opcode[i]==5) // BNE
5123         {
5124           if(s2h>=0) emit_cmp(s1h,s2h);
5125           else emit_test(s1h,s1h);
5126           if(invert) taken=(int)out;
5127           else add_to_linker((int)out,ba[i],internal);
5128           emit_jne(0);
5129         }
5130         if(opcode[i]==6) // BLEZ
5131         {
5132           emit_test(s1h,s1h);
5133           if(invert) taken=(int)out;
5134           else add_to_linker((int)out,ba[i],internal);
5135           emit_js(0);
5136           nottaken1=(int)out;
5137           emit_jne(1);
5138         }
5139         if(opcode[i]==7) // BGTZ
5140         {
5141           emit_test(s1h,s1h);
5142           nottaken1=(int)out;
5143           emit_js(1);
5144           if(invert) taken=(int)out;
5145           else add_to_linker((int)out,ba[i],internal);
5146           emit_jne(0);
5147         }
5148       } // if(!only32)
5149
5150       //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5151       assert(s1l>=0);
5152       if(opcode[i]==4) // BEQ
5153       {
5154         if(s2l>=0) emit_cmp(s1l,s2l);
5155         else emit_test(s1l,s1l);
5156         if(invert){
5157           nottaken=(int)out;
5158           emit_jne(1);
5159         }else{
5160           add_to_linker((int)out,ba[i],internal);
5161           emit_jeq(0);
5162         }
5163       }
5164       if(opcode[i]==5) // BNE
5165       {
5166         if(s2l>=0) emit_cmp(s1l,s2l);
5167         else emit_test(s1l,s1l);
5168         if(invert){
5169           nottaken=(int)out;
5170           emit_jeq(1);
5171         }else{
5172           add_to_linker((int)out,ba[i],internal);
5173           emit_jne(0);
5174         }
5175       }
5176       if(opcode[i]==6) // BLEZ
5177       {
5178         emit_cmpimm(s1l,1);
5179         if(invert){
5180           nottaken=(int)out;
5181           emit_jge(1);
5182         }else{
5183           add_to_linker((int)out,ba[i],internal);
5184           emit_jl(0);
5185         }
5186       }
5187       if(opcode[i]==7) // BGTZ
5188       {
5189         emit_cmpimm(s1l,1);
5190         if(invert){
5191           nottaken=(int)out;
5192           emit_jl(1);
5193         }else{
5194           add_to_linker((int)out,ba[i],internal);
5195           emit_jge(0);
5196         }
5197       }
5198       if(invert) {
5199         if(taken) set_jump_target(taken,(int)out);
5200         #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5201         if(match&&(!internal||!is_ds[(ba[i]-start)>>2])) {
5202           if(adj) {
5203             emit_addimm(cc,-CLOCK_DIVIDER*adj,cc);
5204             add_to_linker((int)out,ba[i],internal);
5205           }else{
5206             emit_addnop(13);
5207             add_to_linker((int)out,ba[i],internal*2);
5208           }
5209           emit_jmp(0);
5210         }else
5211         #endif
5212         {
5213           if(adj) emit_addimm(cc,-CLOCK_DIVIDER*adj,cc);
5214           store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5215           load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5216           if(internal)
5217             assem_debug("branch: internal\n");
5218           else
5219             assem_debug("branch: external\n");
5220           if(internal&&is_ds[(ba[i]-start)>>2]) {
5221             ds_assemble_entry(i);
5222           }
5223           else {
5224             add_to_linker((int)out,ba[i],internal);
5225             emit_jmp(0);
5226           }
5227         }
5228         set_jump_target(nottaken,(int)out);
5229       }
5230
5231       if(nottaken1) set_jump_target(nottaken1,(int)out);
5232       if(adj) {
5233         if(!invert) emit_addimm(cc,CLOCK_DIVIDER*adj,cc);
5234       }
5235     } // (!unconditional)
5236   } // if(ooo)
5237   else
5238   {
5239     // In-order execution (branch first)
5240     //if(likely[i]) printf("IOL\n");
5241     //else
5242     //printf("IOE\n");
5243     int taken=0,nottaken=0,nottaken1=0;
5244     if(!unconditional&&!nop) {
5245       if(!only32)
5246       {
5247         assert(s1h>=0);
5248         if((opcode[i]&0x2f)==4) // BEQ
5249         {
5250           if(s2h>=0) emit_cmp(s1h,s2h);
5251           else emit_test(s1h,s1h);
5252           nottaken1=(int)out;
5253           emit_jne(2);
5254         }
5255         if((opcode[i]&0x2f)==5) // BNE
5256         {
5257           if(s2h>=0) emit_cmp(s1h,s2h);
5258           else emit_test(s1h,s1h);
5259           taken=(int)out;
5260           emit_jne(1);
5261         }
5262         if((opcode[i]&0x2f)==6) // BLEZ
5263         {
5264           emit_test(s1h,s1h);
5265           taken=(int)out;
5266           emit_js(1);
5267           nottaken1=(int)out;
5268           emit_jne(2);
5269         }
5270         if((opcode[i]&0x2f)==7) // BGTZ
5271         {
5272           emit_test(s1h,s1h);
5273           nottaken1=(int)out;
5274           emit_js(2);
5275           taken=(int)out;
5276           emit_jne(1);
5277         }
5278       } // if(!only32)
5279
5280       //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5281       assert(s1l>=0);
5282       if((opcode[i]&0x2f)==4) // BEQ
5283       {
5284         if(s2l>=0) emit_cmp(s1l,s2l);
5285         else emit_test(s1l,s1l);
5286         nottaken=(int)out;
5287         emit_jne(2);
5288       }
5289       if((opcode[i]&0x2f)==5) // BNE
5290       {
5291         if(s2l>=0) emit_cmp(s1l,s2l);
5292         else emit_test(s1l,s1l);
5293         nottaken=(int)out;
5294         emit_jeq(2);
5295       }
5296       if((opcode[i]&0x2f)==6) // BLEZ
5297       {
5298         emit_cmpimm(s1l,1);
5299         nottaken=(int)out;
5300         emit_jge(2);
5301       }
5302       if((opcode[i]&0x2f)==7) // BGTZ
5303       {
5304         emit_cmpimm(s1l,1);
5305         nottaken=(int)out;
5306         emit_jl(2);
5307       }
5308     } // if(!unconditional)
5309     int adj;
5310     uint64_t ds_unneeded=branch_regs[i].u;
5311     uint64_t ds_unneeded_upper=branch_regs[i].uu;
5312     ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
5313     ds_unneeded_upper&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
5314     if((~ds_unneeded_upper>>rt1[i+1])&1) ds_unneeded_upper&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
5315     ds_unneeded|=1;
5316     ds_unneeded_upper|=1;
5317     // branch taken
5318     if(!nop) {
5319       if(taken) set_jump_target(taken,(int)out);
5320       assem_debug("1:\n");
5321       wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5322                     ds_unneeded,ds_unneeded_upper);
5323       // load regs
5324       load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
5325       address_generation(i+1,&branch_regs[i],0);
5326       load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,INVCP);
5327       ds_assemble(i+1,&branch_regs[i]);
5328       cc=get_reg(branch_regs[i].regmap,CCREG);
5329       if(cc==-1) {
5330         emit_loadreg(CCREG,cc=HOST_CCREG);
5331         // CHECK: Is the following instruction (fall thru) allocated ok?
5332       }
5333       assert(cc==HOST_CCREG);
5334       store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5335       do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
5336       assem_debug("cycle count (adj)\n");
5337       if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5338       load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5339       if(internal)
5340         assem_debug("branch: internal\n");
5341       else
5342         assem_debug("branch: external\n");
5343       if(internal&&is_ds[(ba[i]-start)>>2]) {
5344         ds_assemble_entry(i);
5345       }
5346       else {
5347         add_to_linker((int)out,ba[i],internal);
5348         emit_jmp(0);
5349       }
5350     }
5351     // branch not taken
5352     cop1_usable=prev_cop1_usable;
5353     if(!unconditional) {
5354       if(nottaken1) set_jump_target(nottaken1,(int)out);
5355       set_jump_target(nottaken,(int)out);
5356       assem_debug("2:\n");
5357       if(!likely[i]) {
5358         wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5359                       ds_unneeded,ds_unneeded_upper);
5360         load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
5361         address_generation(i+1,&branch_regs[i],0);
5362         load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5363         ds_assemble(i+1,&branch_regs[i]);
5364       }
5365       cc=get_reg(branch_regs[i].regmap,CCREG);
5366       if(cc==-1&&!likely[i]) {
5367         // Cycle count isn't in a register, temporarily load it then write it out
5368         emit_loadreg(CCREG,HOST_CCREG);
5369         emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG);
5370         int jaddr=(int)out;
5371         emit_jns(0);
5372         add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
5373         emit_storereg(CCREG,HOST_CCREG);
5374       }
5375       else{
5376         cc=get_reg(i_regmap,CCREG);
5377         assert(cc==HOST_CCREG);
5378         emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc);
5379         int jaddr=(int)out;
5380         emit_jns(0);
5381         add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
5382       }
5383     }
5384   }
5385 }
5386
5387 void sjump_assemble(int i,struct regstat *i_regs)
5388 {
5389   signed char *i_regmap=i_regs->regmap;
5390   int cc;
5391   int match;
5392   match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5393   assem_debug("smatch=%d\n",match);
5394   int s1h,s1l;
5395   int prev_cop1_usable=cop1_usable;
5396   int unconditional=0,nevertaken=0;
5397   int only32=0;
5398   int ooo=1;
5399   int invert=0;
5400   int internal=internal_branch(branch_regs[i].is32,ba[i]);
5401   if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
5402   if(likely[i]) ooo=0;
5403   if(!match) invert=1;
5404   #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5405   if(i>(ba[i]-start)>>2) invert=1;
5406   #endif
5407
5408   //if(opcode2[i]>=0x10) return; // FIXME (BxxZAL)
5409   assert(opcode2[i]<0x10||rs1[i]==0); // FIXME (BxxZAL)
5410
5411   if(ooo)
5412     if(rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]))
5413   {
5414     // Write-after-read dependency prevents out of order execution
5415     // First test branch condition, then execute delay slot, then branch
5416     ooo=0;
5417   }
5418   // TODO: Conditional branches w/link must execute in-order so that
5419   // condition test and write to r31 occur before cycle count test
5420
5421   if(ooo) {
5422     s1l=get_reg(branch_regs[i].regmap,rs1[i]);
5423     s1h=get_reg(branch_regs[i].regmap,rs1[i]|64);
5424   }
5425   else {
5426     s1l=get_reg(i_regmap,rs1[i]);
5427     s1h=get_reg(i_regmap,rs1[i]|64);
5428   }
5429   if(rs1[i]==0)
5430   {
5431     if(opcode2[i]&1) unconditional=1;
5432     else nevertaken=1;
5433     // These are never taken (r0 is never less than zero)
5434     //assert(opcode2[i]!=0);
5435     //assert(opcode2[i]!=2);
5436     //assert(opcode2[i]!=0x10);
5437     //assert(opcode2[i]!=0x12);
5438   }
5439   else {
5440     only32=(regs[i].was32>>rs1[i])&1;
5441   }
5442
5443   if(ooo) {
5444     // Out of order execution (delay slot first)
5445     //printf("OOOE\n");
5446     address_generation(i+1,i_regs,regs[i].regmap_entry);
5447     ds_assemble(i+1,i_regs);
5448     int adj;
5449     uint64_t bc_unneeded=branch_regs[i].u;
5450     uint64_t bc_unneeded_upper=branch_regs[i].uu;
5451     bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
5452     bc_unneeded_upper&=~((1LL<<us1[i])|(1LL<<us2[i]));
5453     bc_unneeded|=1;
5454     bc_unneeded_upper|=1;
5455     wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5456                   bc_unneeded,bc_unneeded_upper);
5457     load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],rs1[i]);
5458     load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5459     if(rt1[i]==31) {
5460       int rt,return_address;
5461       assert(rt1[i+1]!=31);
5462       assert(rt2[i+1]!=31);
5463       rt=get_reg(branch_regs[i].regmap,31);
5464       assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5465       if(rt>=0) {
5466         // Save the PC even if the branch is not taken
5467         return_address=start+i*4+8;
5468         emit_movimm(return_address,rt); // PC into link register
5469         #ifdef IMM_PREFETCH
5470         if(!nevertaken) emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
5471         #endif
5472       }
5473     }
5474     cc=get_reg(branch_regs[i].regmap,CCREG);
5475     assert(cc==HOST_CCREG);
5476     if(unconditional)
5477       store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5478     //do_cc(i,branch_regs[i].regmap,&adj,unconditional?ba[i]:-1,unconditional);
5479     assem_debug("cycle count (adj)\n");
5480     if(unconditional) {
5481       do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5482       if(i!=(ba[i]-start)>>2 || source[i+1]!=0) {
5483         if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5484         load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5485         if(internal)
5486           assem_debug("branch: internal\n");
5487         else
5488           assem_debug("branch: external\n");
5489         if(internal&&is_ds[(ba[i]-start)>>2]) {
5490           ds_assemble_entry(i);
5491         }
5492         else {
5493           add_to_linker((int)out,ba[i],internal);
5494           emit_jmp(0);
5495         }
5496         #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5497         if(((u_int)out)&7) emit_addnop(0);
5498         #endif
5499       }
5500     }
5501     else if(nevertaken) {
5502       emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc);
5503       int jaddr=(int)out;
5504       emit_jns(0);
5505       add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
5506     }
5507     else {
5508       int nottaken=0;
5509       do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
5510       if(adj&&!invert) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5511       if(!only32)
5512       {
5513         assert(s1h>=0);
5514         if(opcode2[i]==0) // BLTZ
5515         {
5516           emit_test(s1h,s1h);
5517           if(invert){
5518             nottaken=(int)out;
5519             emit_jns(1);
5520           }else{
5521             add_to_linker((int)out,ba[i],internal);
5522             emit_js(0);
5523           }
5524         }
5525         if(opcode2[i]==1) // BGEZ
5526         {
5527           emit_test(s1h,s1h);
5528           if(invert){
5529             nottaken=(int)out;
5530             emit_js(1);
5531           }else{
5532             add_to_linker((int)out,ba[i],internal);
5533             emit_jns(0);
5534           }
5535         }
5536       } // if(!only32)
5537       else
5538       {
5539         assert(s1l>=0);
5540         if(opcode2[i]==0) // BLTZ
5541         {
5542           emit_test(s1l,s1l);
5543           if(invert){
5544             nottaken=(int)out;
5545             emit_jns(1);
5546           }else{
5547             add_to_linker((int)out,ba[i],internal);
5548             emit_js(0);
5549           }
5550         }
5551         if(opcode2[i]==1) // BGEZ
5552         {
5553           emit_test(s1l,s1l);
5554           if(invert){
5555             nottaken=(int)out;
5556             emit_js(1);
5557           }else{
5558             add_to_linker((int)out,ba[i],internal);
5559             emit_jns(0);
5560           }
5561         }
5562       } // if(!only32)
5563
5564       if(invert) {
5565         #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5566         if(match&&(!internal||!is_ds[(ba[i]-start)>>2])) {
5567           if(adj) {
5568             emit_addimm(cc,-CLOCK_DIVIDER*adj,cc);
5569             add_to_linker((int)out,ba[i],internal);
5570           }else{
5571             emit_addnop(13);
5572             add_to_linker((int)out,ba[i],internal*2);
5573           }
5574           emit_jmp(0);
5575         }else
5576         #endif
5577         {
5578           if(adj) emit_addimm(cc,-CLOCK_DIVIDER*adj,cc);
5579           store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5580           load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5581           if(internal)
5582             assem_debug("branch: internal\n");
5583           else
5584             assem_debug("branch: external\n");
5585           if(internal&&is_ds[(ba[i]-start)>>2]) {
5586             ds_assemble_entry(i);
5587           }
5588           else {
5589             add_to_linker((int)out,ba[i],internal);
5590             emit_jmp(0);
5591           }
5592         }
5593         set_jump_target(nottaken,(int)out);
5594       }
5595
5596       if(adj) {
5597         if(!invert) emit_addimm(cc,CLOCK_DIVIDER*adj,cc);
5598       }
5599     } // (!unconditional)
5600   } // if(ooo)
5601   else
5602   {
5603     // In-order execution (branch first)
5604     //printf("IOE\n");
5605     int nottaken=0;
5606     if(!unconditional) {
5607       //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5608       if(!only32)
5609       {
5610         assert(s1h>=0);
5611         if((opcode2[i]&0x1d)==0) // BLTZ/BLTZL
5612         {
5613           emit_test(s1h,s1h);
5614           nottaken=(int)out;
5615           emit_jns(1);
5616         }
5617         if((opcode2[i]&0x1d)==1) // BGEZ/BGEZL
5618         {
5619           emit_test(s1h,s1h);
5620           nottaken=(int)out;
5621           emit_js(1);
5622         }
5623       } // if(!only32)
5624       else
5625       {
5626         assert(s1l>=0);
5627         if((opcode2[i]&0x1d)==0) // BLTZ/BLTZL
5628         {
5629           emit_test(s1l,s1l);
5630           nottaken=(int)out;
5631           emit_jns(1);
5632         }
5633         if((opcode2[i]&0x1d)==1) // BGEZ/BGEZL
5634         {
5635           emit_test(s1l,s1l);
5636           nottaken=(int)out;
5637           emit_js(1);
5638         }
5639       }
5640     } // if(!unconditional)
5641     int adj;
5642     uint64_t ds_unneeded=branch_regs[i].u;
5643     uint64_t ds_unneeded_upper=branch_regs[i].uu;
5644     ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
5645     ds_unneeded_upper&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
5646     if((~ds_unneeded_upper>>rt1[i+1])&1) ds_unneeded_upper&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
5647     ds_unneeded|=1;
5648     ds_unneeded_upper|=1;
5649     // branch taken
5650     if(!nevertaken) {
5651       //assem_debug("1:\n");
5652       wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5653                     ds_unneeded,ds_unneeded_upper);
5654       // load regs
5655       load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
5656       address_generation(i+1,&branch_regs[i],0);
5657       load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,INVCP);
5658       ds_assemble(i+1,&branch_regs[i]);
5659       cc=get_reg(branch_regs[i].regmap,CCREG);
5660       if(cc==-1) {
5661         emit_loadreg(CCREG,cc=HOST_CCREG);
5662         // CHECK: Is the following instruction (fall thru) allocated ok?
5663       }
5664       assert(cc==HOST_CCREG);
5665       store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5666       do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
5667       assem_debug("cycle count (adj)\n");
5668       if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5669       load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5670       if(internal)
5671         assem_debug("branch: internal\n");
5672       else
5673         assem_debug("branch: external\n");
5674       if(internal&&is_ds[(ba[i]-start)>>2]) {
5675         ds_assemble_entry(i);
5676       }
5677       else {
5678         add_to_linker((int)out,ba[i],internal);
5679         emit_jmp(0);
5680       }
5681     }
5682     // branch not taken
5683     cop1_usable=prev_cop1_usable;
5684     if(!unconditional) {
5685       set_jump_target(nottaken,(int)out);
5686       assem_debug("1:\n");
5687       if(!likely[i]) {
5688         wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5689                       ds_unneeded,ds_unneeded_upper);
5690         load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
5691         address_generation(i+1,&branch_regs[i],0);
5692         load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5693         ds_assemble(i+1,&branch_regs[i]);
5694       }
5695       cc=get_reg(branch_regs[i].regmap,CCREG);
5696       if(cc==-1&&!likely[i]) {
5697         // Cycle count isn't in a register, temporarily load it then write it out
5698         emit_loadreg(CCREG,HOST_CCREG);
5699         emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG);
5700         int jaddr=(int)out;
5701         emit_jns(0);
5702         add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
5703         emit_storereg(CCREG,HOST_CCREG);
5704       }
5705       else{
5706         cc=get_reg(i_regmap,CCREG);
5707         assert(cc==HOST_CCREG);
5708         emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc);
5709         int jaddr=(int)out;
5710         emit_jns(0);
5711         add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
5712       }
5713     }
5714   }
5715 }
5716
5717 void fjump_assemble(int i,struct regstat *i_regs)
5718 {
5719   signed char *i_regmap=i_regs->regmap;
5720   int cc;
5721   int match;
5722   match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5723   assem_debug("fmatch=%d\n",match);
5724   int fs,cs;
5725   int eaddr;
5726   int ooo=1;
5727   int invert=0;
5728   int internal=internal_branch(branch_regs[i].is32,ba[i]);
5729   if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
5730   if(likely[i]) ooo=0;
5731   if(!match) invert=1;
5732   #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5733   if(i>(ba[i]-start)>>2) invert=1;
5734   #endif
5735
5736   if(ooo)
5737     if(itype[i+1]==FCOMP)
5738   {
5739     // Write-after-read dependency prevents out of order execution
5740     // First test branch condition, then execute delay slot, then branch
5741     ooo=0;
5742   }
5743
5744   if(ooo) {
5745     fs=get_reg(branch_regs[i].regmap,FSREG);
5746     address_generation(i+1,i_regs,regs[i].regmap_entry); // Is this okay?
5747   }
5748   else {
5749     fs=get_reg(i_regmap,FSREG);
5750   }
5751
5752   // Check cop1 unusable
5753   if(!cop1_usable) {
5754     cs=get_reg(i_regmap,CSREG);
5755     assert(cs>=0);
5756     emit_testimm(cs,0x20000000);
5757     eaddr=(int)out;
5758     emit_jeq(0);
5759     add_stub(FP_STUB,eaddr,(int)out,i,cs,(int)i_regs,0,0);
5760     cop1_usable=1;
5761   }
5762
5763   if(ooo) {
5764     // Out of order execution (delay slot first)
5765     //printf("OOOE\n");
5766     ds_assemble(i+1,i_regs);
5767     int adj;
5768     uint64_t bc_unneeded=branch_regs[i].u;
5769     uint64_t bc_unneeded_upper=branch_regs[i].uu;
5770     bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
5771     bc_unneeded_upper&=~((1LL<<us1[i])|(1LL<<us2[i]));
5772     bc_unneeded|=1;
5773     bc_unneeded_upper|=1;
5774     wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5775                   bc_unneeded,bc_unneeded_upper);
5776     load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],rs1[i]);
5777     load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5778     cc=get_reg(branch_regs[i].regmap,CCREG);
5779     assert(cc==HOST_CCREG);
5780     do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
5781     assem_debug("cycle count (adj)\n");
5782     if(1) {
5783       int nottaken=0;
5784       if(adj&&!invert) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5785       if(1) {
5786         assert(fs>=0);
5787         emit_testimm(fs,0x800000);
5788         if(source[i]&0x10000) // BC1T
5789         {
5790           if(invert){
5791             nottaken=(int)out;
5792             emit_jeq(1);
5793           }else{
5794             add_to_linker((int)out,ba[i],internal);
5795             emit_jne(0);
5796           }
5797         }
5798         else // BC1F
5799           if(invert){
5800             nottaken=(int)out;
5801             emit_jne(1);
5802           }else{
5803             add_to_linker((int)out,ba[i],internal);
5804             emit_jeq(0);
5805           }
5806         {
5807         }
5808       } // if(!only32)
5809
5810       if(invert) {
5811         if(adj) emit_addimm(cc,-CLOCK_DIVIDER*adj,cc);
5812         #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5813         else if(match) emit_addnop(13);
5814         #endif
5815         store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5816         load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5817         if(internal)
5818           assem_debug("branch: internal\n");
5819         else
5820           assem_debug("branch: external\n");
5821         if(internal&&is_ds[(ba[i]-start)>>2]) {
5822           ds_assemble_entry(i);
5823         }
5824         else {
5825           add_to_linker((int)out,ba[i],internal);
5826           emit_jmp(0);
5827         }
5828         set_jump_target(nottaken,(int)out);
5829       }
5830
5831       if(adj) {
5832         if(!invert) emit_addimm(cc,CLOCK_DIVIDER*adj,cc);
5833       }
5834     } // (!unconditional)
5835   } // if(ooo)
5836   else
5837   {
5838     // In-order execution (branch first)
5839     //printf("IOE\n");
5840     int nottaken=0;
5841     if(1) {
5842       //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5843       if(1) {
5844         assert(fs>=0);
5845         emit_testimm(fs,0x800000);
5846         if(source[i]&0x10000) // BC1T
5847         {
5848           nottaken=(int)out;
5849           emit_jeq(1);
5850         }
5851         else // BC1F
5852         {
5853           nottaken=(int)out;
5854           emit_jne(1);
5855         }
5856       }
5857     } // if(!unconditional)
5858     int adj;
5859     uint64_t ds_unneeded=branch_regs[i].u;
5860     uint64_t ds_unneeded_upper=branch_regs[i].uu;
5861     ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
5862     ds_unneeded_upper&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
5863     if((~ds_unneeded_upper>>rt1[i+1])&1) ds_unneeded_upper&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
5864     ds_unneeded|=1;
5865     ds_unneeded_upper|=1;
5866     // branch taken
5867     //assem_debug("1:\n");
5868     wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5869                   ds_unneeded,ds_unneeded_upper);
5870     // load regs
5871     load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
5872     address_generation(i+1,&branch_regs[i],0);
5873     load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,INVCP);
5874     ds_assemble(i+1,&branch_regs[i]);
5875     cc=get_reg(branch_regs[i].regmap,CCREG);
5876     if(cc==-1) {
5877       emit_loadreg(CCREG,cc=HOST_CCREG);
5878       // CHECK: Is the following instruction (fall thru) allocated ok?
5879     }
5880     assert(cc==HOST_CCREG);
5881     store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5882     do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
5883     assem_debug("cycle count (adj)\n");
5884     if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5885     load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5886     if(internal)
5887       assem_debug("branch: internal\n");
5888     else
5889       assem_debug("branch: external\n");
5890     if(internal&&is_ds[(ba[i]-start)>>2]) {
5891       ds_assemble_entry(i);
5892     }
5893     else {
5894       add_to_linker((int)out,ba[i],internal);
5895       emit_jmp(0);
5896     }
5897
5898     // branch not taken
5899     if(1) { // <- FIXME (don't need this)
5900       set_jump_target(nottaken,(int)out);
5901       assem_debug("1:\n");
5902       if(!likely[i]) {
5903         wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5904                       ds_unneeded,ds_unneeded_upper);
5905         load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
5906         address_generation(i+1,&branch_regs[i],0);
5907         load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5908         ds_assemble(i+1,&branch_regs[i]);
5909       }
5910       cc=get_reg(branch_regs[i].regmap,CCREG);
5911       if(cc==-1&&!likely[i]) {
5912         // Cycle count isn't in a register, temporarily load it then write it out
5913         emit_loadreg(CCREG,HOST_CCREG);
5914         emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG);
5915         int jaddr=(int)out;
5916         emit_jns(0);
5917         add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
5918         emit_storereg(CCREG,HOST_CCREG);
5919       }
5920       else{
5921         cc=get_reg(i_regmap,CCREG);
5922         assert(cc==HOST_CCREG);
5923         emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc);
5924         int jaddr=(int)out;
5925         emit_jns(0);
5926         add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
5927       }
5928     }
5929   }
5930 }
5931
5932 static void pagespan_assemble(int i,struct regstat *i_regs)
5933 {
5934   int s1l=get_reg(i_regs->regmap,rs1[i]);
5935   int s1h=get_reg(i_regs->regmap,rs1[i]|64);
5936   int s2l=get_reg(i_regs->regmap,rs2[i]);
5937   int s2h=get_reg(i_regs->regmap,rs2[i]|64);
5938   void *nt_branch=NULL;
5939   int taken=0;
5940   int nottaken=0;
5941   int unconditional=0;
5942   if(rs1[i]==0)
5943   {
5944     s1l=s2l;s1h=s2h;
5945     s2l=s2h=-1;
5946   }
5947   else if(rs2[i]==0)
5948   {
5949     s2l=s2h=-1;
5950   }
5951   if((i_regs->is32>>rs1[i])&(i_regs->is32>>rs2[i])&1) {
5952     s1h=s2h=-1;
5953   }
5954   int hr=0;
5955   int addr,alt,ntaddr;
5956   if(i_regs->regmap[HOST_BTREG]<0) {addr=HOST_BTREG;}
5957   else {
5958     while(hr<HOST_REGS)
5959     {
5960       if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
5961          (i_regs->regmap[hr]&63)!=rs1[i] &&
5962          (i_regs->regmap[hr]&63)!=rs2[i] )
5963       {
5964         addr=hr++;break;
5965       }
5966       hr++;
5967     }
5968   }
5969   while(hr<HOST_REGS)
5970   {
5971     if(hr!=EXCLUDE_REG && hr!=HOST_CCREG && hr!=HOST_BTREG &&
5972        (i_regs->regmap[hr]&63)!=rs1[i] &&
5973        (i_regs->regmap[hr]&63)!=rs2[i] )
5974     {
5975       alt=hr++;break;
5976     }
5977     hr++;
5978   }
5979   if((opcode[i]&0x2E)==6) // BLEZ/BGTZ needs another register
5980   {
5981     while(hr<HOST_REGS)
5982     {
5983       if(hr!=EXCLUDE_REG && hr!=HOST_CCREG && hr!=HOST_BTREG &&
5984          (i_regs->regmap[hr]&63)!=rs1[i] &&
5985          (i_regs->regmap[hr]&63)!=rs2[i] )
5986       {
5987         ntaddr=hr;break;
5988       }
5989       hr++;
5990     }
5991   }
5992   assert(hr<HOST_REGS);
5993   if((opcode[i]&0x2e)==4||opcode[i]==0x11) { // BEQ/BNE/BEQL/BNEL/BC1
5994     load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,CCREG,CCREG);
5995   }
5996   emit_addimm(HOST_CCREG,CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG);
5997   if(opcode[i]==2) // J
5998   {
5999     unconditional=1;
6000   }
6001   if(opcode[i]==3) // JAL
6002   {
6003     // TODO: mini_ht
6004     int rt=get_reg(i_regs->regmap,31);
6005     emit_movimm(start+i*4+8,rt);
6006     unconditional=1;
6007   }
6008   if(opcode[i]==0&&(opcode2[i]&0x3E)==8) // JR/JALR
6009   {
6010     emit_mov(s1l,addr);
6011     if(opcode2[i]==9) // JALR
6012     {
6013       int rt=get_reg(i_regs->regmap,31);
6014       emit_movimm(start+i*4+8,rt);
6015     }
6016   }
6017   if((opcode[i]&0x3f)==4) // BEQ
6018   {
6019     if(rs1[i]==rs2[i])
6020     {
6021       unconditional=1;
6022     }
6023     else
6024     #ifdef HAVE_CMOV_IMM
6025     if(s1h<0) {
6026       if(s2l>=0) emit_cmp(s1l,s2l);
6027       else emit_test(s1l,s1l);
6028       emit_cmov2imm_e_ne_compact(ba[i],start+i*4+8,addr);
6029     }
6030     else
6031     #endif
6032     {
6033       assert(s1l>=0);
6034       emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
6035       if(s1h>=0) {
6036         if(s2h>=0) emit_cmp(s1h,s2h);
6037         else emit_test(s1h,s1h);
6038         emit_cmovne_reg(alt,addr);
6039       }
6040       if(s2l>=0) emit_cmp(s1l,s2l);
6041       else emit_test(s1l,s1l);
6042       emit_cmovne_reg(alt,addr);
6043     }
6044   }
6045   if((opcode[i]&0x3f)==5) // BNE
6046   {
6047     #ifdef HAVE_CMOV_IMM
6048     if(s1h<0) {
6049       if(s2l>=0) emit_cmp(s1l,s2l);
6050       else emit_test(s1l,s1l);
6051       emit_cmov2imm_e_ne_compact(start+i*4+8,ba[i],addr);
6052     }
6053     else
6054     #endif
6055     {
6056       assert(s1l>=0);
6057       emit_mov2imm_compact(start+i*4+8,addr,ba[i],alt);
6058       if(s1h>=0) {
6059         if(s2h>=0) emit_cmp(s1h,s2h);
6060         else emit_test(s1h,s1h);
6061         emit_cmovne_reg(alt,addr);
6062       }
6063       if(s2l>=0) emit_cmp(s1l,s2l);
6064       else emit_test(s1l,s1l);
6065       emit_cmovne_reg(alt,addr);
6066     }
6067   }
6068   if((opcode[i]&0x3f)==0x14) // BEQL
6069   {
6070     if(s1h>=0) {
6071       if(s2h>=0) emit_cmp(s1h,s2h);
6072       else emit_test(s1h,s1h);
6073       nottaken=(int)out;
6074       emit_jne(0);
6075     }
6076     if(s2l>=0) emit_cmp(s1l,s2l);
6077     else emit_test(s1l,s1l);
6078     if(nottaken) set_jump_target(nottaken,(int)out);
6079     nottaken=(int)out;
6080     emit_jne(0);
6081   }
6082   if((opcode[i]&0x3f)==0x15) // BNEL
6083   {
6084     if(s1h>=0) {
6085       if(s2h>=0) emit_cmp(s1h,s2h);
6086       else emit_test(s1h,s1h);
6087       taken=(int)out;
6088       emit_jne(0);
6089     }
6090     if(s2l>=0) emit_cmp(s1l,s2l);
6091     else emit_test(s1l,s1l);
6092     nottaken=(int)out;
6093     emit_jeq(0);
6094     if(taken) set_jump_target(taken,(int)out);
6095   }
6096   if((opcode[i]&0x3f)==6) // BLEZ
6097   {
6098     emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
6099     emit_cmpimm(s1l,1);
6100     if(s1h>=0) emit_mov(addr,ntaddr);
6101     emit_cmovl_reg(alt,addr);
6102     if(s1h>=0) {
6103       emit_test(s1h,s1h);
6104       emit_cmovne_reg(ntaddr,addr);
6105       emit_cmovs_reg(alt,addr);
6106     }
6107   }
6108   if((opcode[i]&0x3f)==7) // BGTZ
6109   {
6110     emit_mov2imm_compact(ba[i],addr,start+i*4+8,ntaddr);
6111     emit_cmpimm(s1l,1);
6112     if(s1h>=0) emit_mov(addr,alt);
6113     emit_cmovl_reg(ntaddr,addr);
6114     if(s1h>=0) {
6115       emit_test(s1h,s1h);
6116       emit_cmovne_reg(alt,addr);
6117       emit_cmovs_reg(ntaddr,addr);
6118     }
6119   }
6120   if((opcode[i]&0x3f)==0x16) // BLEZL
6121   {
6122     assert((opcode[i]&0x3f)!=0x16);
6123   }
6124   if((opcode[i]&0x3f)==0x17) // BGTZL
6125   {
6126     assert((opcode[i]&0x3f)!=0x17);
6127   }
6128   assert(opcode[i]!=1); // BLTZ/BGEZ
6129
6130   //FIXME: Check CSREG
6131   if(opcode[i]==0x11 && opcode2[i]==0x08 ) {
6132     if((source[i]&0x30000)==0) // BC1F
6133     {
6134       emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
6135       emit_testimm(s1l,0x800000);
6136       emit_cmovne_reg(alt,addr);
6137     }
6138     if((source[i]&0x30000)==0x10000) // BC1T
6139     {
6140       emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
6141       emit_testimm(s1l,0x800000);
6142       emit_cmovne_reg(alt,addr);
6143     }
6144     if((source[i]&0x30000)==0x20000) // BC1FL
6145     {
6146       emit_testimm(s1l,0x800000);
6147       nottaken=(int)out;
6148       emit_jne(0);
6149     }
6150     if((source[i]&0x30000)==0x30000) // BC1TL
6151     {
6152       emit_testimm(s1l,0x800000);
6153       nottaken=(int)out;
6154       emit_jeq(0);
6155     }
6156   }
6157
6158   assert(i_regs->regmap[HOST_CCREG]==CCREG);
6159   wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty);
6160   if(likely[i]||unconditional)
6161   {
6162     emit_movimm(ba[i],HOST_BTREG);
6163   }
6164   else if(addr!=HOST_BTREG)
6165   {
6166     emit_mov(addr,HOST_BTREG);
6167   }
6168   void *branch_addr=out;
6169   emit_jmp(0);
6170   int target_addr=start+i*4+5;
6171   void *stub=out;
6172   void *compiled_target_addr=check_addr(target_addr);
6173   emit_extjump_ds((int)branch_addr,target_addr);
6174   if(compiled_target_addr) {
6175     set_jump_target((int)branch_addr,(int)compiled_target_addr);
6176     add_link(target_addr,stub);
6177   }
6178   else set_jump_target((int)branch_addr,(int)stub);
6179   if(likely[i]) {
6180     // Not-taken path
6181     set_jump_target((int)nottaken,(int)out);
6182     wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty);
6183     void *branch_addr=out;
6184     emit_jmp(0);
6185     int target_addr=start+i*4+8;
6186     void *stub=out;
6187     void *compiled_target_addr=check_addr(target_addr);
6188     emit_extjump_ds((int)branch_addr,target_addr);
6189     if(compiled_target_addr) {
6190       set_jump_target((int)branch_addr,(int)compiled_target_addr);
6191       add_link(target_addr,stub);
6192     }
6193     else set_jump_target((int)branch_addr,(int)stub);
6194   }
6195 }
6196
6197 // Assemble the delay slot for the above
6198 static void pagespan_ds()
6199 {
6200   assem_debug("initial delay slot:\n");
6201   u_int vaddr=start+1;
6202   u_int page=get_page(vaddr);
6203   u_int vpage=get_vpage(vaddr);
6204   ll_add(jump_dirty+vpage,vaddr,(void *)out);
6205   do_dirty_stub_ds();
6206   ll_add(jump_in+page,vaddr,(void *)out);
6207   assert(regs[0].regmap_entry[HOST_CCREG]==CCREG);
6208   if(regs[0].regmap[HOST_CCREG]!=CCREG)
6209     wb_register(CCREG,regs[0].regmap_entry,regs[0].wasdirty,regs[0].was32);
6210   if(regs[0].regmap[HOST_BTREG]!=BTREG)
6211     emit_writeword(HOST_BTREG,(int)&branch_target);
6212   load_regs(regs[0].regmap_entry,regs[0].regmap,regs[0].was32,rs1[0],rs2[0]);
6213   address_generation(0,&regs[0],regs[0].regmap_entry);
6214   if(itype[0]==STORE||itype[0]==STORELR||(opcode[0]&0x3b)==0x39)
6215     load_regs(regs[0].regmap_entry,regs[0].regmap,regs[0].was32,INVCP,INVCP);
6216   cop1_usable=0;
6217   is_delayslot=0;
6218   switch(itype[0]) {
6219     case ALU:
6220       alu_assemble(0,&regs[0]);break;
6221     case IMM16:
6222       imm16_assemble(0,&regs[0]);break;
6223     case SHIFT:
6224       shift_assemble(0,&regs[0]);break;
6225     case SHIFTIMM:
6226       shiftimm_assemble(0,&regs[0]);break;
6227     case LOAD:
6228       load_assemble(0,&regs[0]);break;
6229     case LOADLR:
6230       loadlr_assemble(0,&regs[0]);break;
6231     case STORE:
6232       store_assemble(0,&regs[0]);break;
6233     case STORELR:
6234       storelr_assemble(0,&regs[0]);break;
6235     case COP0:
6236       cop0_assemble(0,&regs[0]);break;
6237     case COP1:
6238       cop1_assemble(0,&regs[0]);break;
6239     case C1LS:
6240       c1ls_assemble(0,&regs[0]);break;
6241     case FCONV:
6242       fconv_assemble(0,&regs[0]);break;
6243     case FLOAT:
6244       float_assemble(0,&regs[0]);break;
6245     case FCOMP:
6246       fcomp_assemble(0,&regs[0]);break;
6247     case MULTDIV:
6248       multdiv_assemble(0,&regs[0]);break;
6249     case MOV:
6250       mov_assemble(0,&regs[0]);break;
6251     case SYSCALL:
6252     case SPAN:
6253     case UJUMP:
6254     case RJUMP:
6255     case CJUMP:
6256     case SJUMP:
6257     case FJUMP:
6258       printf("Jump in the delay slot.  This is probably a bug.\n");
6259   }
6260   int btaddr=get_reg(regs[0].regmap,BTREG);
6261   if(btaddr<0) {
6262     btaddr=get_reg(regs[0].regmap,-1);
6263     emit_readword((int)&branch_target,btaddr);
6264   }
6265   assert(btaddr!=HOST_CCREG);
6266   if(regs[0].regmap[HOST_CCREG]!=CCREG) emit_loadreg(CCREG,HOST_CCREG);
6267 #ifdef HOST_IMM8
6268   emit_movimm(start+4,HOST_TEMPREG);
6269   emit_cmp(btaddr,HOST_TEMPREG);
6270 #else
6271   emit_cmpimm(btaddr,start+4);
6272 #endif
6273   int branch=(int)out;
6274   emit_jeq(0);
6275   store_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,-1);
6276   emit_jmp(jump_vaddr_reg[btaddr]);
6277   set_jump_target(branch,(int)out);
6278   store_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,start+4);
6279   load_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,start+4);
6280 }
6281
6282 // Basic liveness analysis for MIPS registers
6283 void unneeded_registers(int istart,int iend,int r)
6284 {
6285   int i;
6286   uint64_t u,uu,b,bu;
6287   uint64_t temp_u,temp_uu;
6288   uint64_t tdep;
6289   if(iend==slen-1) {
6290     u=1;uu=1;
6291   }else{
6292     u=unneeded_reg[iend+1];
6293     uu=unneeded_reg_upper[iend+1];
6294     u=1;uu=1;
6295   }
6296   for (i=iend;i>=istart;i--)
6297   {
6298     //printf("unneeded registers i=%d (%d,%d) r=%d\n",i,istart,iend,r);
6299     if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
6300     {
6301       // If subroutine call, flag return address as a possible branch target
6302       if(rt1[i]==31 && i<slen-2) bt[i+2]=1;
6303
6304       if(ba[i]<start || ba[i]>=(start+slen*4))
6305       {
6306         // Branch out of this block, flush all regs
6307         u=1;
6308         uu=1;
6309         /* Hexagon hack
6310         if(itype[i]==UJUMP&&rt1[i]==31)
6311         {
6312           uu=u=0x300C00F; // Discard at, v0-v1, t6-t9
6313         }
6314         if(itype[i]==RJUMP&&rs1[i]==31)
6315         {
6316           uu=u=0x300C0F3; // Discard at, a0-a3, t6-t9
6317         }
6318         if(start>0x80000400&&start<0x80800000) {
6319           if(itype[i]==UJUMP&&rt1[i]==31)
6320           {
6321             //uu=u=0x30300FF0FLL; // Discard at, v0-v1, t0-t9, lo, hi
6322             uu=u=0x300FF0F; // Discard at, v0-v1, t0-t9
6323           }
6324           if(itype[i]==RJUMP&&rs1[i]==31)
6325           {
6326             //uu=u=0x30300FFF3LL; // Discard at, a0-a3, t0-t9, lo, hi
6327             uu=u=0x300FFF3; // Discard at, a0-a3, t0-t9
6328           }
6329         }*/
6330         branch_unneeded_reg[i]=u;
6331         branch_unneeded_reg_upper[i]=uu;
6332         // Merge in delay slot
6333         tdep=(~uu>>rt1[i+1])&1;
6334         u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6335         uu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6336         u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6337         uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6338         uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6339         u|=1;uu|=1;
6340         // If branch is "likely" (and conditional)
6341         // then we skip the delay slot on the fall-thru path
6342         if(likely[i]) {
6343           if(i<slen-1) {
6344             u&=unneeded_reg[i+2];
6345             uu&=unneeded_reg_upper[i+2];
6346           }
6347           else
6348           {
6349             u=1;
6350             uu=1;
6351           }
6352         }
6353       }
6354       else
6355       {
6356         // Internal branch, flag target
6357         bt[(ba[i]-start)>>2]=1;
6358         if(ba[i]<=start+i*4) {
6359           // Backward branch
6360           if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
6361           {
6362             // Unconditional branch
6363             temp_u=1;temp_uu=1;
6364           } else {
6365             // Conditional branch (not taken case)
6366             temp_u=unneeded_reg[i+2];
6367             temp_uu=unneeded_reg_upper[i+2];
6368           }
6369           // Merge in delay slot
6370           tdep=(~temp_uu>>rt1[i+1])&1;
6371           temp_u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6372           temp_uu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6373           temp_u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6374           temp_uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6375           temp_uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6376           temp_u|=1;temp_uu|=1;
6377           // If branch is "likely" (and conditional)
6378           // then we skip the delay slot on the fall-thru path
6379           if(likely[i]) {
6380             if(i<slen-1) {
6381               temp_u&=unneeded_reg[i+2];
6382               temp_uu&=unneeded_reg_upper[i+2];
6383             }
6384             else
6385             {
6386               temp_u=1;
6387               temp_uu=1;
6388             }
6389           }
6390           tdep=(~temp_uu>>rt1[i])&1;
6391           temp_u|=(1LL<<rt1[i])|(1LL<<rt2[i]);
6392           temp_uu|=(1LL<<rt1[i])|(1LL<<rt2[i]);
6393           temp_u&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
6394           temp_uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
6395           temp_uu&=~((tdep<<dep1[i])|(tdep<<dep2[i]));
6396           temp_u|=1;temp_uu|=1;
6397           unneeded_reg[i]=temp_u;
6398           unneeded_reg_upper[i]=temp_uu;
6399           // Only go three levels deep.  This recursion can take an
6400           // excessive amount of time if there are a lot of nested loops.
6401           if(r<2) {
6402             unneeded_registers((ba[i]-start)>>2,i-1,r+1);
6403           }else{
6404             unneeded_reg[(ba[i]-start)>>2]=1;
6405             unneeded_reg_upper[(ba[i]-start)>>2]=1;
6406           }
6407         } /*else*/ if(1) {
6408           if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
6409           {
6410             // Unconditional branch
6411             u=unneeded_reg[(ba[i]-start)>>2];
6412             uu=unneeded_reg_upper[(ba[i]-start)>>2];
6413             branch_unneeded_reg[i]=u;
6414             branch_unneeded_reg_upper[i]=uu;
6415         //u=1;
6416         //uu=1;
6417         //branch_unneeded_reg[i]=u;
6418         //branch_unneeded_reg_upper[i]=uu;
6419             // Merge in delay slot
6420             tdep=(~uu>>rt1[i+1])&1;
6421             u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6422             uu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6423             u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6424             uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6425             uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6426             u|=1;uu|=1;
6427           } else {
6428             // Conditional branch
6429             b=unneeded_reg[(ba[i]-start)>>2];
6430             bu=unneeded_reg_upper[(ba[i]-start)>>2];
6431             branch_unneeded_reg[i]=b;
6432             branch_unneeded_reg_upper[i]=bu;
6433         //b=1;
6434         //bu=1;
6435         //branch_unneeded_reg[i]=b;
6436         //branch_unneeded_reg_upper[i]=bu;
6437             // Branch delay slot
6438             tdep=(~uu>>rt1[i+1])&1;
6439             b|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6440             bu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6441             b&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6442             bu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6443             bu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6444             b|=1;bu|=1;
6445             // If branch is "likely" then we skip the
6446             // delay slot on the fall-thru path
6447             if(likely[i]) {
6448               u=b;
6449               uu=bu;
6450               if(i<slen-1) {
6451                 u&=unneeded_reg[i+2];
6452                 uu&=unneeded_reg_upper[i+2];
6453         //u=1;
6454         //uu=1;
6455               }
6456             } else {
6457               u&=b;
6458               uu&=bu;
6459         //u=1;
6460         //uu=1;
6461             }
6462             if(i<slen-1) {
6463               branch_unneeded_reg[i]&=unneeded_reg[i+2];
6464               branch_unneeded_reg_upper[i]&=unneeded_reg_upper[i+2];
6465         //branch_unneeded_reg[i]=1;
6466         //branch_unneeded_reg_upper[i]=1;
6467             } else {
6468               branch_unneeded_reg[i]=1;
6469               branch_unneeded_reg_upper[i]=1;
6470             }
6471           }
6472         }
6473       }
6474     }
6475     else if(itype[i]==SYSCALL)
6476     {
6477       // SYSCALL instruction (software interrupt)
6478       u=1;
6479       uu=1;
6480     }
6481     else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
6482     {
6483       // ERET instruction (return from interrupt)
6484       u=1;
6485       uu=1;
6486     }
6487     //u=uu=1; // DEBUG
6488     tdep=(~uu>>rt1[i])&1;
6489     // Written registers are unneeded
6490     u|=1LL<<rt1[i];
6491     u|=1LL<<rt2[i];
6492     uu|=1LL<<rt1[i];
6493     uu|=1LL<<rt2[i];
6494     // Accessed registers are needed
6495     u&=~(1LL<<rs1[i]);
6496     u&=~(1LL<<rs2[i]);
6497     uu&=~(1LL<<us1[i]);
6498     uu&=~(1LL<<us2[i]);
6499     // Source-target dependencies
6500     uu&=~(tdep<<dep1[i]);
6501     uu&=~(tdep<<dep2[i]);
6502     // R0 is always unneeded
6503     u|=1;uu|=1;
6504     // Save it
6505     unneeded_reg[i]=u;
6506     unneeded_reg_upper[i]=uu;
6507     /*
6508     printf("ur (%d,%d) %x: ",istart,iend,start+i*4);
6509     printf("U:");
6510     int r;
6511     for(r=1;r<=CCREG;r++) {
6512       if((unneeded_reg[i]>>r)&1) {
6513         if(r==HIREG) printf(" HI");
6514         else if(r==LOREG) printf(" LO");
6515         else printf(" r%d",r);
6516       }
6517     }
6518     printf(" UU:");
6519     for(r=1;r<=CCREG;r++) {
6520       if(((unneeded_reg_upper[i]&~unneeded_reg[i])>>r)&1) {
6521         if(r==HIREG) printf(" HI");
6522         else if(r==LOREG) printf(" LO");
6523         else printf(" r%d",r);
6524       }
6525     }
6526     printf("\n");*/
6527   }
6528 }
6529
6530 // Identify registers which are likely to contain 32-bit values
6531 // This is used to predict whether any branches will jump to a
6532 // location with 64-bit values in registers.
6533 static void provisional_32bit()
6534 {
6535   int i,j;
6536   uint64_t is32=1;
6537   uint64_t lastbranch=1;
6538
6539   for(i=0;i<slen;i++)
6540   {
6541     if(i>0) {
6542       if(itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP) {
6543         if(i>1) is32=lastbranch;
6544         else is32=1;
6545       }
6546     }
6547     if(i>1)
6548     {
6549       if(itype[i-2]==CJUMP||itype[i-2]==SJUMP||itype[i-2]==FJUMP) {
6550         if(likely[i-2]) {
6551           if(i>2) is32=lastbranch;
6552           else is32=1;
6553         }
6554       }
6555       if((opcode[i-2]&0x2f)==0x05) // BNE/BNEL
6556       {
6557         if(rs1[i-2]==0||rs2[i-2]==0)
6558         {
6559           if(rs1[i-2]) {
6560             is32|=1LL<<rs1[i-2];
6561           }
6562           if(rs2[i-2]) {
6563             is32|=1LL<<rs2[i-2];
6564           }
6565         }
6566       }
6567     }
6568     // If something jumps here with 64-bit values
6569     // then promote those registers to 64 bits
6570     if(bt[i])
6571     {
6572       uint64_t temp_is32=is32;
6573       for(j=i-1;j>=0;j--)
6574       {
6575         if(ba[j]==start+i*4)
6576           //temp_is32&=branch_regs[j].is32;
6577           temp_is32&=p32[j];
6578       }
6579       for(j=i;j<slen;j++)
6580       {
6581         if(ba[j]==start+i*4)
6582           temp_is32=1;
6583       }
6584       is32=temp_is32;
6585     }
6586     int type=itype[i];
6587     int op=opcode[i];
6588     int op2=opcode2[i];
6589     int rt=rt1[i];
6590     int s1=rs1[i];
6591     int s2=rs2[i];
6592     if(type==UJUMP||type==RJUMP||type==CJUMP||type==SJUMP||type==FJUMP) {
6593       // Branches don't write registers, consider the delay slot instead.
6594       type=itype[i+1];
6595       op=opcode[i+1];
6596       op2=opcode2[i+1];
6597       rt=rt1[i+1];
6598       s1=rs1[i+1];
6599       s2=rs2[i+1];
6600       lastbranch=is32;
6601     }
6602     switch(type) {
6603       case LOAD:
6604         if(opcode[i]==0x27||opcode[i]==0x37|| // LWU/LD
6605            opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
6606           is32&=~(1LL<<rt);
6607         else
6608           is32|=1LL<<rt;
6609         break;
6610       case STORE:
6611       case STORELR:
6612         break;
6613       case LOADLR:
6614         if(op==0x1a||op==0x1b) is32&=~(1LL<<rt); // LDR/LDL
6615         if(op==0x22) is32|=1LL<<rt; // LWL
6616         break;
6617       case IMM16:
6618         if (op==0x08||op==0x09|| // ADDI/ADDIU
6619             op==0x0a||op==0x0b|| // SLTI/SLTIU
6620             op==0x0c|| // ANDI
6621             op==0x0f)  // LUI
6622         {
6623           is32|=1LL<<rt;
6624         }
6625         if(op==0x18||op==0x19) { // DADDI/DADDIU
6626           is32&=~(1LL<<rt);
6627           //if(imm[i]==0)
6628           //  is32|=((is32>>s1)&1LL)<<rt;
6629         }
6630         if(op==0x0d||op==0x0e) { // ORI/XORI
6631           uint64_t sr=((is32>>s1)&1LL);
6632           is32&=~(1LL<<rt);
6633           is32|=sr<<rt;
6634         }
6635         break;
6636       case UJUMP:
6637         break;
6638       case RJUMP:
6639         break;
6640       case CJUMP:
6641         break;
6642       case SJUMP:
6643         break;
6644       case FJUMP:
6645         break;
6646       case ALU:
6647         if(op2>=0x20&&op2<=0x23) { // ADD/ADDU/SUB/SUBU
6648           is32|=1LL<<rt;
6649         }
6650         if(op2==0x2a||op2==0x2b) { // SLT/SLTU
6651           is32|=1LL<<rt;
6652         }
6653         else if(op2>=0x24&&op2<=0x27) { // AND/OR/XOR/NOR
6654           uint64_t sr=((is32>>s1)&(is32>>s2)&1LL);
6655           is32&=~(1LL<<rt);
6656           is32|=sr<<rt;
6657         }
6658         else if(op2>=0x2c&&op2<=0x2d) { // DADD/DADDU
6659           if(s1==0&&s2==0) {
6660             is32|=1LL<<rt;
6661           }
6662           else if(s2==0) {
6663             uint64_t sr=((is32>>s1)&1LL);
6664             is32&=~(1LL<<rt);
6665             is32|=sr<<rt;
6666           }
6667           else if(s1==0) {
6668             uint64_t sr=((is32>>s2)&1LL);
6669             is32&=~(1LL<<rt);
6670             is32|=sr<<rt;
6671           }
6672           else {
6673             is32&=~(1LL<<rt);
6674           }
6675         }
6676         else if(op2>=0x2e&&op2<=0x2f) { // DSUB/DSUBU
6677           if(s1==0&&s2==0) {
6678             is32|=1LL<<rt;
6679           }
6680           else if(s2==0) {
6681             uint64_t sr=((is32>>s1)&1LL);
6682             is32&=~(1LL<<rt);
6683             is32|=sr<<rt;
6684           }
6685           else {
6686             is32&=~(1LL<<rt);
6687           }
6688         }
6689         break;
6690       case MULTDIV:
6691         if (op2>=0x1c&&op2<=0x1f) { // DMULT/DMULTU/DDIV/DDIVU
6692           is32&=~((1LL<<HIREG)|(1LL<<LOREG));
6693         }
6694         else {
6695           is32|=(1LL<<HIREG)|(1LL<<LOREG);
6696         }
6697         break;
6698       case MOV:
6699         {
6700           uint64_t sr=((is32>>s1)&1LL);
6701           is32&=~(1LL<<rt);
6702           is32|=sr<<rt;
6703         }
6704         break;
6705       case SHIFT:
6706         if(op2>=0x14&&op2<=0x17) is32&=~(1LL<<rt); // DSLLV/DSRLV/DSRAV
6707         else is32|=1LL<<rt; // SLLV/SRLV/SRAV
6708         break;
6709       case SHIFTIMM:
6710         is32|=1LL<<rt;
6711         // DSLL/DSRL/DSRA/DSLL32/DSRL32 but not DSRA32 have 64-bit result
6712         if(op2>=0x38&&op2<0x3f) is32&=~(1LL<<rt);
6713         break;
6714       case COP0:
6715         if(op2==0) is32|=1LL<<rt; // MFC0
6716         break;
6717       case COP1:
6718         if(op2==0) is32|=1LL<<rt; // MFC1
6719         if(op2==1) is32&=~(1LL<<rt); // DMFC1
6720         if(op2==2) is32|=1LL<<rt; // CFC1
6721         break;
6722       case C1LS:
6723         break;
6724       case FLOAT:
6725       case FCONV:
6726         break;
6727       case FCOMP:
6728         break;
6729       case SYSCALL:
6730         break;
6731       default:
6732         break;
6733     }
6734     is32|=1;
6735     p32[i]=is32;
6736
6737     if(i>0)
6738     {
6739       if(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)
6740       {
6741         if(rt1[i-1]==31) // JAL/JALR
6742         {
6743           // Subroutine call will return here, don't alloc any registers
6744           is32=1;
6745         }
6746         else if(i+1<slen)
6747         {
6748           // Internal branch will jump here, match registers to caller
6749           is32=0x3FFFFFFFFLL;
6750         }
6751       }
6752     }
6753   }
6754 }
6755
6756 // Identify registers which may be assumed to contain 32-bit values
6757 // and where optimizations will rely on this.
6758 // This is used to determine whether backward branches can safely
6759 // jump to a location with 64-bit values in registers.
6760 static void provisional_r32()
6761 {
6762   u_int r32=0;
6763   int i;
6764
6765   for (i=slen-1;i>=0;i--)
6766   {
6767     int hr;
6768     if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
6769     {
6770       if(ba[i]<start || ba[i]>=(start+slen*4))
6771       {
6772         // Branch out of this block, don't need anything
6773         r32=0;
6774       }
6775       else
6776       {
6777         // Internal branch
6778         // Need whatever matches the target
6779         // (and doesn't get overwritten by the delay slot instruction)
6780         r32=0;
6781         int t=(ba[i]-start)>>2;
6782         if(ba[i]>start+i*4) {
6783           // Forward branch
6784           //if(!(requires_32bit[t]&~regs[i].was32))
6785           //  r32|=requires_32bit[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
6786           if(!(pr32[t]&~regs[i].was32))
6787             r32|=pr32[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
6788         }else{
6789           // Backward branch
6790           if(!(regs[t].was32&~unneeded_reg_upper[t]&~regs[i].was32))
6791             r32|=regs[t].was32&~unneeded_reg_upper[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
6792         }
6793       }
6794       // Conditional branch may need registers for following instructions
6795       if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
6796       {
6797         if(i<slen-2) {
6798           //r32|=requires_32bit[i+2];
6799           r32|=pr32[i+2];
6800           r32&=regs[i].was32;
6801           // Mark this address as a branch target since it may be called
6802           // upon return from interrupt
6803           //bt[i+2]=1;
6804         }
6805       }
6806       // Merge in delay slot
6807       if(!likely[i]) {
6808         // These are overwritten unless the branch is "likely"
6809         // and the delay slot is nullified if not taken
6810         r32&=~(1LL<<rt1[i+1]);
6811         r32&=~(1LL<<rt2[i+1]);
6812       }
6813       // Assume these are needed (delay slot)
6814       if(us1[i+1]>0)
6815       {
6816         if((regs[i].was32>>us1[i+1])&1) r32|=1LL<<us1[i+1];
6817       }
6818       if(us2[i+1]>0)
6819       {
6820         if((regs[i].was32>>us2[i+1])&1) r32|=1LL<<us2[i+1];
6821       }
6822       if(dep1[i+1]&&!((unneeded_reg_upper[i]>>dep1[i+1])&1))
6823       {
6824         if((regs[i].was32>>dep1[i+1])&1) r32|=1LL<<dep1[i+1];
6825       }
6826       if(dep2[i+1]&&!((unneeded_reg_upper[i]>>dep2[i+1])&1))
6827       {
6828         if((regs[i].was32>>dep2[i+1])&1) r32|=1LL<<dep2[i+1];
6829       }
6830     }
6831     else if(itype[i]==SYSCALL)
6832     {
6833       // SYSCALL instruction (software interrupt)
6834       r32=0;
6835     }
6836     else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
6837     {
6838       // ERET instruction (return from interrupt)
6839       r32=0;
6840     }
6841     // Check 32 bits
6842     r32&=~(1LL<<rt1[i]);
6843     r32&=~(1LL<<rt2[i]);
6844     if(us1[i]>0)
6845     {
6846       if((regs[i].was32>>us1[i])&1) r32|=1LL<<us1[i];
6847     }
6848     if(us2[i]>0)
6849     {
6850       if((regs[i].was32>>us2[i])&1) r32|=1LL<<us2[i];
6851     }
6852     if(dep1[i]&&!((unneeded_reg_upper[i]>>dep1[i])&1))
6853     {
6854       if((regs[i].was32>>dep1[i])&1) r32|=1LL<<dep1[i];
6855     }
6856     if(dep2[i]&&!((unneeded_reg_upper[i]>>dep2[i])&1))
6857     {
6858       if((regs[i].was32>>dep2[i])&1) r32|=1LL<<dep2[i];
6859     }
6860     //requires_32bit[i]=r32;
6861     pr32[i]=r32;
6862
6863     // Dirty registers which are 32-bit, require 32-bit input
6864     // as they will be written as 32-bit values
6865     for(hr=0;hr<HOST_REGS;hr++)
6866     {
6867       if(regs[i].regmap_entry[hr]>0&&regs[i].regmap_entry[hr]<64) {
6868         if((regs[i].was32>>regs[i].regmap_entry[hr])&(regs[i].wasdirty>>hr)&1) {
6869           if(!((unneeded_reg_upper[i]>>regs[i].regmap_entry[hr])&1))
6870           pr32[i]|=1LL<<regs[i].regmap_entry[hr];
6871           //requires_32bit[i]|=1LL<<regs[i].regmap_entry[hr];
6872         }
6873       }
6874     }
6875   }
6876 }
6877
6878 // Write back dirty registers as soon as we will no longer modify them,
6879 // so that we don't end up with lots of writes at the branches.
6880 void clean_registers(int istart,int iend,int wr)
6881 {
6882   int i;
6883   int r;
6884   u_int will_dirty_i,will_dirty_next,temp_will_dirty;
6885   u_int wont_dirty_i,wont_dirty_next,temp_wont_dirty;
6886   if(iend==slen-1) {
6887     will_dirty_i=will_dirty_next=0;
6888     wont_dirty_i=wont_dirty_next=0;
6889   }else{
6890     will_dirty_i=will_dirty_next=will_dirty[iend+1];
6891     wont_dirty_i=wont_dirty_next=wont_dirty[iend+1];
6892   }
6893   for (i=iend;i>=istart;i--)
6894   {
6895     if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
6896     {
6897       if(ba[i]<start || ba[i]>=(start+slen*4))
6898       {
6899         // Branch out of this block, flush all regs
6900         if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
6901         {
6902           // Unconditional branch
6903           will_dirty_i=0;
6904           wont_dirty_i=0;
6905           // Merge in delay slot (will dirty)
6906           for(r=0;r<HOST_REGS;r++) {
6907             if(r!=EXCLUDE_REG) {
6908               if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
6909               if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
6910               if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
6911               if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
6912               if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
6913               if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
6914               if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
6915               if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
6916               if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
6917               if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
6918               if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
6919               if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
6920               if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
6921               if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
6922             }
6923           }
6924         }
6925         else
6926         {
6927           // Conditional branch
6928           will_dirty_i=0;
6929           wont_dirty_i=wont_dirty_next;
6930           // Merge in delay slot (will dirty)
6931           for(r=0;r<HOST_REGS;r++) {
6932             if(r!=EXCLUDE_REG) {
6933               if(!likely[i]) {
6934                 // Might not dirty if likely branch is not taken
6935                 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
6936                 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
6937                 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
6938                 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
6939                 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
6940                 if(branch_regs[i].regmap[r]==0) will_dirty_i&=~(1<<r);
6941                 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
6942                 //if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
6943                 //if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
6944                 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
6945                 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
6946                 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
6947                 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
6948                 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
6949               }
6950             }
6951           }
6952         }
6953         // Merge in delay slot (wont dirty)
6954         for(r=0;r<HOST_REGS;r++) {
6955           if(r!=EXCLUDE_REG) {
6956             if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
6957             if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
6958             if((regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
6959             if((regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
6960             if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
6961             if((branch_regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
6962             if((branch_regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
6963             if((branch_regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
6964             if((branch_regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
6965             if(branch_regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
6966           }
6967         }
6968         if(wr) {
6969           #ifndef DESTRUCTIVE_WRITEBACK
6970           branch_regs[i].dirty&=wont_dirty_i;
6971           #endif
6972           branch_regs[i].dirty|=will_dirty_i;
6973         }
6974       }
6975       else
6976       {
6977         // Internal branch
6978         if(ba[i]<=start+i*4) {
6979           // Backward branch
6980           if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
6981           {
6982             // Unconditional branch
6983             temp_will_dirty=0;
6984             temp_wont_dirty=0;
6985             // Merge in delay slot (will dirty)
6986             for(r=0;r<HOST_REGS;r++) {
6987               if(r!=EXCLUDE_REG) {
6988                 if((branch_regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
6989                 if((branch_regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
6990                 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
6991                 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
6992                 if((branch_regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
6993                 if(branch_regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
6994                 if(branch_regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
6995                 if((regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
6996                 if((regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
6997                 if((regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
6998                 if((regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
6999                 if((regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7000                 if(regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
7001                 if(regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7002               }
7003             }
7004           } else {
7005             // Conditional branch (not taken case)
7006             temp_will_dirty=will_dirty_next;
7007             temp_wont_dirty=wont_dirty_next;
7008             // Merge in delay slot (will dirty)
7009             for(r=0;r<HOST_REGS;r++) {
7010               if(r!=EXCLUDE_REG) {
7011                 if(!likely[i]) {
7012                   // Will not dirty if likely branch is not taken
7013                   if((branch_regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7014                   if((branch_regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7015                   if((branch_regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7016                   if((branch_regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7017                   if((branch_regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7018                   if(branch_regs[i].regmap[r]==0) temp_will_dirty&=~(1<<r);
7019                   if(branch_regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7020                   //if((regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7021                   //if((regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7022                   if((regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7023                   if((regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7024                   if((regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7025                   if(regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
7026                   if(regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7027                 }
7028               }
7029             }
7030           }
7031           // Merge in delay slot (wont dirty)
7032           for(r=0;r<HOST_REGS;r++) {
7033             if(r!=EXCLUDE_REG) {
7034               if((regs[i].regmap[r]&63)==rt1[i]) temp_wont_dirty|=1<<r;
7035               if((regs[i].regmap[r]&63)==rt2[i]) temp_wont_dirty|=1<<r;
7036               if((regs[i].regmap[r]&63)==rt1[i+1]) temp_wont_dirty|=1<<r;
7037               if((regs[i].regmap[r]&63)==rt2[i+1]) temp_wont_dirty|=1<<r;
7038               if(regs[i].regmap[r]==CCREG) temp_wont_dirty|=1<<r;
7039               if((branch_regs[i].regmap[r]&63)==rt1[i]) temp_wont_dirty|=1<<r;
7040               if((branch_regs[i].regmap[r]&63)==rt2[i]) temp_wont_dirty|=1<<r;
7041               if((branch_regs[i].regmap[r]&63)==rt1[i+1]) temp_wont_dirty|=1<<r;
7042               if((branch_regs[i].regmap[r]&63)==rt2[i+1]) temp_wont_dirty|=1<<r;
7043               if(branch_regs[i].regmap[r]==CCREG) temp_wont_dirty|=1<<r;
7044             }
7045           }
7046           // Deal with changed mappings
7047           if(i<iend) {
7048             for(r=0;r<HOST_REGS;r++) {
7049               if(r!=EXCLUDE_REG) {
7050                 if(regs[i].regmap[r]!=regmap_pre[i][r]) {
7051                   temp_will_dirty&=~(1<<r);
7052                   temp_wont_dirty&=~(1<<r);
7053                   if((regmap_pre[i][r]&63)>0 && (regmap_pre[i][r]&63)<34) {
7054                     temp_will_dirty|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7055                     temp_wont_dirty|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7056                   } else {
7057                     temp_will_dirty|=1<<r;
7058                     temp_wont_dirty|=1<<r;
7059                   }
7060                 }
7061               }
7062             }
7063           }
7064           if(wr) {
7065             will_dirty[i]=temp_will_dirty;
7066             wont_dirty[i]=temp_wont_dirty;
7067             clean_registers((ba[i]-start)>>2,i-1,0);
7068           }else{
7069             // Limit recursion.  It can take an excessive amount
7070             // of time if there are a lot of nested loops.
7071             will_dirty[(ba[i]-start)>>2]=0;
7072             wont_dirty[(ba[i]-start)>>2]=-1;
7073           }
7074         }
7075         /*else*/ if(1)
7076         {
7077           if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
7078           {
7079             // Unconditional branch
7080             will_dirty_i=0;
7081             wont_dirty_i=0;
7082           //if(ba[i]>start+i*4) { // Disable recursion (for debugging)
7083             for(r=0;r<HOST_REGS;r++) {
7084               if(r!=EXCLUDE_REG) {
7085                 if(branch_regs[i].regmap[r]==regs[(ba[i]-start)>>2].regmap_entry[r]) {
7086                   will_dirty_i|=will_dirty[(ba[i]-start)>>2]&(1<<r);
7087                   wont_dirty_i|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
7088                 }
7089               }
7090             }
7091           //}
7092             // Merge in delay slot
7093             for(r=0;r<HOST_REGS;r++) {
7094               if(r!=EXCLUDE_REG) {
7095                 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7096                 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7097                 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7098                 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7099                 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7100                 if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7101                 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7102                 if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7103                 if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7104                 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7105                 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7106                 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7107                 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7108                 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7109               }
7110             }
7111           } else {
7112             // Conditional branch
7113             will_dirty_i=will_dirty_next;
7114             wont_dirty_i=wont_dirty_next;
7115           //if(ba[i]>start+i*4) { // Disable recursion (for debugging)
7116             for(r=0;r<HOST_REGS;r++) {
7117               if(r!=EXCLUDE_REG) {
7118                 if(branch_regs[i].regmap[r]==regs[(ba[i]-start)>>2].regmap_entry[r]) {
7119                   will_dirty_i&=will_dirty[(ba[i]-start)>>2]&(1<<r);
7120                   wont_dirty_i|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
7121                 }
7122                 else
7123                 {
7124                   will_dirty_i&=~(1<<r);
7125                 }
7126                 // Treat delay slot as part of branch too
7127                 /*if(regs[i+1].regmap[r]==regs[(ba[i]-start)>>2].regmap_entry[r]) {
7128                   will_dirty[i+1]&=will_dirty[(ba[i]-start)>>2]&(1<<r);
7129                   wont_dirty[i+1]|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
7130                 }
7131                 else
7132                 {
7133                   will_dirty[i+1]&=~(1<<r);
7134                 }*/
7135               }
7136             }
7137           //}
7138             // Merge in delay slot
7139             for(r=0;r<HOST_REGS;r++) {
7140               if(r!=EXCLUDE_REG) {
7141                 if(!likely[i]) {
7142                   // Might not dirty if likely branch is not taken
7143                   if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7144                   if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7145                   if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7146                   if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7147                   if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7148                   if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7149                   if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7150                   //if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7151                   //if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7152                   if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7153                   if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7154                   if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7155                   if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7156                   if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7157                 }
7158               }
7159             }
7160           }
7161           // Merge in delay slot
7162           for(r=0;r<HOST_REGS;r++) {
7163             if(r!=EXCLUDE_REG) {
7164               if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7165               if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7166               if((regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7167               if((regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7168               if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7169               if((branch_regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7170               if((branch_regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7171               if((branch_regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7172               if((branch_regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7173               if(branch_regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7174             }
7175           }
7176           if(wr) {
7177             #ifndef DESTRUCTIVE_WRITEBACK
7178             branch_regs[i].dirty&=wont_dirty_i;
7179             #endif
7180             branch_regs[i].dirty|=will_dirty_i;
7181           }
7182         }
7183       }
7184     }
7185     else if(itype[i]==SYSCALL)
7186     {
7187       // SYSCALL instruction (software interrupt)
7188       will_dirty_i=0;
7189       wont_dirty_i=0;
7190     }
7191     else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
7192     {
7193       // ERET instruction (return from interrupt)
7194       will_dirty_i=0;
7195       wont_dirty_i=0;
7196     }
7197     will_dirty_next=will_dirty_i;
7198     wont_dirty_next=wont_dirty_i;
7199     for(r=0;r<HOST_REGS;r++) {
7200       if(r!=EXCLUDE_REG) {
7201         if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7202         if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7203         if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7204         if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7205         if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7206         if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7207         if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7208         if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7209         if(i>istart) {
7210           if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=FJUMP)
7211           {
7212             // Don't store a register immediately after writing it,
7213             // may prevent dual-issue.
7214             if((regs[i].regmap[r]&63)==rt1[i-1]) wont_dirty_i|=1<<r;
7215             if((regs[i].regmap[r]&63)==rt2[i-1]) wont_dirty_i|=1<<r;
7216           }
7217         }
7218       }
7219     }
7220     // Save it
7221     will_dirty[i]=will_dirty_i;
7222     wont_dirty[i]=wont_dirty_i;
7223     // Mark registers that won't be dirtied as not dirty
7224     if(wr) {
7225       /*printf("wr (%d,%d) %x will:",istart,iend,start+i*4);
7226       for(r=0;r<HOST_REGS;r++) {
7227         if((will_dirty_i>>r)&1) {
7228           printf(" r%d",r);
7229         }
7230       }
7231       printf("\n");*/
7232
7233       //if(i==istart||(itype[i-1]!=RJUMP&&itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=FJUMP)) {
7234         regs[i].dirty|=will_dirty_i;
7235         #ifndef DESTRUCTIVE_WRITEBACK
7236         regs[i].dirty&=wont_dirty_i;
7237         if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
7238         {
7239           if(i<iend-1&&itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000) {
7240             for(r=0;r<HOST_REGS;r++) {
7241               if(r!=EXCLUDE_REG) {
7242                 if(regs[i].regmap[r]==regmap_pre[i+2][r]) {
7243                   regs[i+2].wasdirty&=wont_dirty_i|~(1<<r);
7244                 }else {/*printf("i: %x (%d) mismatch(+2): %d\n",start+i*4,i,r);/*assert(!((wont_dirty_i>>r)&1));*/}
7245               }
7246             }
7247           }
7248         }
7249         else
7250         {
7251           if(i<iend) {
7252             for(r=0;r<HOST_REGS;r++) {
7253               if(r!=EXCLUDE_REG) {
7254                 if(regs[i].regmap[r]==regmap_pre[i+1][r]) {
7255                   regs[i+1].wasdirty&=wont_dirty_i|~(1<<r);
7256                 }else {/*printf("i: %x (%d) mismatch(+1): %d\n",start+i*4,i,r);/*assert(!((wont_dirty_i>>r)&1));*/}
7257               }
7258             }
7259           }
7260         }
7261         #endif
7262       //}
7263     }
7264     // Deal with changed mappings
7265     temp_will_dirty=will_dirty_i;
7266     temp_wont_dirty=wont_dirty_i;
7267     for(r=0;r<HOST_REGS;r++) {
7268       if(r!=EXCLUDE_REG) {
7269         int nr;
7270         if(regs[i].regmap[r]==regmap_pre[i][r]) {
7271           if(wr) {
7272             #ifndef DESTRUCTIVE_WRITEBACK
7273             regs[i].wasdirty&=wont_dirty_i|~(1<<r);
7274             #endif
7275             regs[i].wasdirty|=will_dirty_i&(1<<r);
7276           }
7277         }
7278         else if((nr=get_reg(regs[i].regmap,regmap_pre[i][r]))>=0) {
7279           // Register moved to a different register
7280           will_dirty_i&=~(1<<r);
7281           wont_dirty_i&=~(1<<r);
7282           will_dirty_i|=((temp_will_dirty>>nr)&1)<<r;
7283           wont_dirty_i|=((temp_wont_dirty>>nr)&1)<<r;
7284           if(wr) {
7285             #ifndef DESTRUCTIVE_WRITEBACK
7286             regs[i].wasdirty&=wont_dirty_i|~(1<<r);
7287             #endif
7288             regs[i].wasdirty|=will_dirty_i&(1<<r);
7289           }
7290         }
7291         else {
7292           will_dirty_i&=~(1<<r);
7293           wont_dirty_i&=~(1<<r);
7294           if((regmap_pre[i][r]&63)>0 && (regmap_pre[i][r]&63)<34) {
7295             will_dirty_i|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7296             wont_dirty_i|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7297           } else {
7298             wont_dirty_i|=1<<r;
7299             /*printf("i: %x (%d) mismatch: %d\n",start+i*4,i,r);/*assert(!((will_dirty>>r)&1));*/
7300           }
7301         }
7302       }
7303     }
7304   }
7305 }
7306
7307   /* disassembly */
7308 void disassemble_inst(int i)
7309 {
7310     if (bt[i]) printf("*"); else printf(" ");
7311     switch(itype[i]) {
7312       case UJUMP:
7313         printf (" %x: %s %8x\n",start+i*4,insn[i],ba[i]);break;
7314       case CJUMP:
7315         printf (" %x: %s r%d,r%d,%8x\n",start+i*4,insn[i],rs1[i],rs2[i],i?start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14):*ba);break;
7316       case SJUMP:
7317         printf (" %x: %s r%d,%8x\n",start+i*4,insn[i],rs1[i],start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14));break;
7318       case FJUMP:
7319         printf (" %x: %s %8x\n",start+i*4,insn[i],ba[i]);break;
7320       case RJUMP:
7321         printf (" %x: %s r%d\n",start+i*4,insn[i],rs1[i]);break;
7322       case SPAN:
7323         printf (" %x: %s (pagespan) r%d,r%d,%8x\n",start+i*4,insn[i],rs1[i],rs2[i],ba[i]);break;
7324       case IMM16:
7325         if(opcode[i]==0xf) //LUI
7326           printf (" %x: %s r%d,%4x0000\n",start+i*4,insn[i],rt1[i],imm[i]&0xffff);
7327         else
7328           printf (" %x: %s r%d,r%d,%d\n",start+i*4,insn[i],rt1[i],rs1[i],imm[i]);
7329         break;
7330       case LOAD:
7331       case LOADLR:
7332         printf (" %x: %s r%d,r%d+%x\n",start+i*4,insn[i],rt1[i],rs1[i],imm[i]);
7333         break;
7334       case STORE:
7335       case STORELR:
7336         printf (" %x: %s r%d,r%d+%x\n",start+i*4,insn[i],rs2[i],rs1[i],imm[i]);
7337         break;
7338       case ALU:
7339       case SHIFT:
7340         printf (" %x: %s r%d,r%d,r%d\n",start+i*4,insn[i],rt1[i],rs1[i],rs2[i]);
7341         break;
7342       case MULTDIV:
7343         printf (" %x: %s r%d,r%d\n",start+i*4,insn[i],rs1[i],rs2[i]);
7344         break;
7345       case SHIFTIMM:
7346         printf (" %x: %s r%d,r%d,%d\n",start+i*4,insn[i],rt1[i],rs1[i],imm[i]);
7347         break;
7348       case MOV:
7349         if((opcode2[i]&0x1d)==0x10)
7350           printf (" %x: %s r%d\n",start+i*4,insn[i],rt1[i]);
7351         else if((opcode2[i]&0x1d)==0x11)
7352           printf (" %x: %s r%d\n",start+i*4,insn[i],rs1[i]);
7353         else
7354           printf (" %x: %s\n",start+i*4,insn[i]);
7355         break;
7356       case COP0:
7357         if(opcode2[i]==0)
7358           printf (" %x: %s r%d,cpr0[%d]\n",start+i*4,insn[i],rt1[i],(source[i]>>11)&0x1f); // MFC0
7359         else if(opcode2[i]==4)
7360           printf (" %x: %s r%d,cpr0[%d]\n",start+i*4,insn[i],rs1[i],(source[i]>>11)&0x1f); // MTC0
7361         else printf (" %x: %s\n",start+i*4,insn[i]);
7362         break;
7363       case COP1:
7364         if(opcode2[i]<3)
7365           printf (" %x: %s r%d,cpr1[%d]\n",start+i*4,insn[i],rt1[i],(source[i]>>11)&0x1f); // MFC1
7366         else if(opcode2[i]>3)
7367           printf (" %x: %s r%d,cpr1[%d]\n",start+i*4,insn[i],rs1[i],(source[i]>>11)&0x1f); // MTC1
7368         else printf (" %x: %s\n",start+i*4,insn[i]);
7369         break;
7370       case C1LS:
7371         printf (" %x: %s cpr1[%d],r%d+%x\n",start+i*4,insn[i],(source[i]>>16)&0x1f,rs1[i],imm[i]);
7372         break;
7373       default:
7374         //printf (" %s %8x\n",insn[i],source[i]);
7375         printf (" %x: %s\n",start+i*4,insn[i]);
7376     }
7377 }
7378
7379 void new_dynarec_init()
7380 {
7381   printf("Init new dynarec\n");
7382   out=(u_char *)BASE_ADDR;
7383   if (mmap (out, 1<<TARGET_SIZE_2,
7384             PROT_READ | PROT_WRITE | PROT_EXEC,
7385             MAP_FIXED | MAP_PRIVATE | MAP_ANONYMOUS,
7386             -1, 0) <= 0) {printf("mmap() failed\n");}
7387 #ifdef MUPEN64
7388   rdword=&readmem_dword;
7389   fake_pc.f.r.rs=&readmem_dword;
7390   fake_pc.f.r.rt=&readmem_dword;
7391   fake_pc.f.r.rd=&readmem_dword;
7392 #endif
7393   int n;
7394   for(n=0x80000;n<0x80800;n++)
7395     invalid_code[n]=1;
7396   for(n=0;n<65536;n++)
7397     hash_table[n][0]=hash_table[n][2]=-1;
7398   memset(mini_ht,-1,sizeof(mini_ht));
7399   memset(restore_candidate,0,sizeof(restore_candidate));
7400   copy=shadow;
7401   expirep=16384; // Expiry pointer, +2 blocks
7402   pending_exception=0;
7403   literalcount=0;
7404 #ifdef HOST_IMM8
7405   // Copy this into local area so we don't have to put it in every literal pool
7406   invc_ptr=invalid_code;
7407 #endif
7408   stop_after_jal=0;
7409   // TLB
7410   using_tlb=0;
7411   for(n=0;n<524288;n++) // 0 .. 0x7FFFFFFF
7412     memory_map[n]=-1;
7413   for(n=524288;n<526336;n++) // 0x80000000 .. 0x807FFFFF
7414     memory_map[n]=((u_int)rdram-0x80000000)>>2;
7415   for(n=526336;n<1048576;n++) // 0x80800000 .. 0xFFFFFFFF
7416     memory_map[n]=-1;
7417   for(n=0;n<0x8000;n++) { // 0 .. 0x7FFFFFFF
7418     writemem[n] = write_nomem_new;
7419     writememb[n] = write_nomemb_new;
7420     writememh[n] = write_nomemh_new;
7421     writememd[n] = write_nomemd_new;
7422     readmem[n] = read_nomem_new;
7423     readmemb[n] = read_nomemb_new;
7424     readmemh[n] = read_nomemh_new;
7425     readmemd[n] = read_nomemd_new;
7426   }
7427   for(n=0x8000;n<0x8080;n++) { // 0x80000000 .. 0x807FFFFF
7428     writemem[n] = write_rdram_new;
7429     writememb[n] = write_rdramb_new;
7430     writememh[n] = write_rdramh_new;
7431     writememd[n] = write_rdramd_new;
7432   }
7433   for(n=0xC000;n<0x10000;n++) { // 0xC0000000 .. 0xFFFFFFFF
7434     writemem[n] = write_nomem_new;
7435     writememb[n] = write_nomemb_new;
7436     writememh[n] = write_nomemh_new;
7437     writememd[n] = write_nomemd_new;
7438     readmem[n] = read_nomem_new;
7439     readmemb[n] = read_nomemb_new;
7440     readmemh[n] = read_nomemh_new;
7441     readmemd[n] = read_nomemd_new;
7442   }
7443   tlb_hacks();
7444   arch_init();
7445 }
7446
7447 void new_dynarec_cleanup()
7448 {
7449   int n;
7450   if (munmap ((void *)BASE_ADDR, 1<<TARGET_SIZE_2) < 0) {printf("munmap() failed\n");}
7451   for(n=0;n<4096;n++) ll_clear(jump_in+n);
7452   for(n=0;n<4096;n++) ll_clear(jump_out+n);
7453   for(n=0;n<4096;n++) ll_clear(jump_dirty+n);
7454   #ifdef ROM_COPY
7455   if (munmap (ROM_COPY, 67108864) < 0) {printf("munmap() failed\n");}
7456   #endif
7457 }
7458
7459 int new_recompile_block(int addr)
7460 {
7461 /*
7462   if(addr==0x800cd050) {
7463     int block;
7464     for(block=0x80000;block<0x80800;block++) invalidate_block(block);
7465     int n;
7466     for(n=0;n<=2048;n++) ll_clear(jump_dirty+n);
7467   }
7468 */
7469   //if(Count==365117028) tracedebug=1;
7470   assem_debug("NOTCOMPILED: addr = %x -> %x\n", (int)addr, (int)out);
7471   //printf("NOTCOMPILED: addr = %x -> %x\n", (int)addr, (int)out);
7472   //printf("TRACE: count=%d next=%d (compile %x)\n",Count,next_interupt,addr);
7473   //if(debug)
7474   //printf("TRACE: count=%d next=%d (checksum %x)\n",Count,next_interupt,mchecksum());
7475   //printf("fpu mapping=%x enabled=%x\n",(Status & 0x04000000)>>26,(Status & 0x20000000)>>29);
7476   /*if(Count>=312978186) {
7477     rlist();
7478   }*/
7479   //rlist();
7480   start = (u_int)addr&~3;
7481   //assert(((u_int)addr&1)==0);
7482 #ifdef MUPEN64
7483   if ((int)addr >= 0xa4000000 && (int)addr < 0xa4001000) {
7484     source = (u_int *)((u_int)SP_DMEM+start-0xa4000000);
7485     pagelimit = 0xa4001000;
7486   }
7487   else
7488 #endif
7489   if ((int)addr >= 0x80000000 && (int)addr < 0x80800000) {
7490     source = (u_int *)((u_int)rdram+start-0x80000000);
7491     pagelimit = 0x80800000;
7492   }
7493   else if ((signed int)addr >= (signed int)0xC0000000) {
7494     //printf("addr=%x mm=%x\n",(u_int)addr,(memory_map[start>>12]<<2));
7495     //if(tlb_LUT_r[start>>12])
7496       //source = (u_int *)(((int)rdram)+(tlb_LUT_r[start>>12]&0xFFFFF000)+(((int)addr)&0xFFF)-0x80000000);
7497     if((signed int)memory_map[start>>12]>=0) {
7498       source = (u_int *)((u_int)(start+(memory_map[start>>12]<<2)));
7499       pagelimit=(start+4096)&0xFFFFF000;
7500       int map=memory_map[start>>12];
7501       int i;
7502       for(i=0;i<5;i++) {
7503         //printf("start: %x next: %x\n",map,memory_map[pagelimit>>12]);
7504         if((map&0xBFFFFFFF)==(memory_map[pagelimit>>12]&0xBFFFFFFF)) pagelimit+=4096;
7505       }
7506       assem_debug("pagelimit=%x\n",pagelimit);
7507       assem_debug("mapping=%x (%x)\n",memory_map[start>>12],(memory_map[start>>12]<<2)+start);
7508     }
7509     else {
7510       assem_debug("Compile at unmapped memory address: %x \n", (int)addr);
7511       //assem_debug("start: %x next: %x\n",memory_map[start>>12],memory_map[(start+4096)>>12]);
7512       return 1; // Caller will invoke exception handler
7513     }
7514     //printf("source= %x\n",(int)source);
7515   }
7516   else {
7517     printf("Compile at bogus memory address: %x \n", (int)addr);
7518     exit(1);
7519   }
7520
7521   /* Pass 1: disassemble */
7522   /* Pass 2: register dependencies, branch targets */
7523   /* Pass 3: register allocation */
7524   /* Pass 4: branch dependencies */
7525   /* Pass 5: pre-alloc */
7526   /* Pass 6: optimize clean/dirty state */
7527   /* Pass 7: flag 32-bit registers */
7528   /* Pass 8: assembly */
7529   /* Pass 9: linker */
7530   /* Pass 10: garbage collection / free memory */
7531
7532   int i,j;
7533   int done=0;
7534   unsigned int type,op,op2;
7535
7536   //printf("addr = %x source = %x %x\n", addr,source,source[0]);
7537
7538   /* Pass 1 disassembly */
7539
7540   for(i=0;!done;i++) {
7541     bt[i]=0;likely[i]=0;op2=0;
7542     opcode[i]=op=source[i]>>26;
7543     switch(op)
7544     {
7545       case 0x00: strcpy(insn[i],"special"); type=NI;
7546         op2=source[i]&0x3f;
7547         switch(op2)
7548         {
7549           case 0x00: strcpy(insn[i],"SLL"); type=SHIFTIMM; break;
7550           case 0x02: strcpy(insn[i],"SRL"); type=SHIFTIMM; break;
7551           case 0x03: strcpy(insn[i],"SRA"); type=SHIFTIMM; break;
7552           case 0x04: strcpy(insn[i],"SLLV"); type=SHIFT; break;
7553           case 0x06: strcpy(insn[i],"SRLV"); type=SHIFT; break;
7554           case 0x07: strcpy(insn[i],"SRAV"); type=SHIFT; break;
7555           case 0x08: strcpy(insn[i],"JR"); type=RJUMP; break;
7556           case 0x09: strcpy(insn[i],"JALR"); type=RJUMP; break;
7557           case 0x0C: strcpy(insn[i],"SYSCALL"); type=SYSCALL; break;
7558           case 0x0D: strcpy(insn[i],"BREAK"); type=OTHER; break;
7559           case 0x0F: strcpy(insn[i],"SYNC"); type=OTHER; break;
7560           case 0x10: strcpy(insn[i],"MFHI"); type=MOV; break;
7561           case 0x11: strcpy(insn[i],"MTHI"); type=MOV; break;
7562           case 0x12: strcpy(insn[i],"MFLO"); type=MOV; break;
7563           case 0x13: strcpy(insn[i],"MTLO"); type=MOV; break;
7564           case 0x14: strcpy(insn[i],"DSLLV"); type=SHIFT; break;
7565           case 0x16: strcpy(insn[i],"DSRLV"); type=SHIFT; break;
7566           case 0x17: strcpy(insn[i],"DSRAV"); type=SHIFT; break;
7567           case 0x18: strcpy(insn[i],"MULT"); type=MULTDIV; break;
7568           case 0x19: strcpy(insn[i],"MULTU"); type=MULTDIV; break;
7569           case 0x1A: strcpy(insn[i],"DIV"); type=MULTDIV; break;
7570           case 0x1B: strcpy(insn[i],"DIVU"); type=MULTDIV; break;
7571           case 0x1C: strcpy(insn[i],"DMULT"); type=MULTDIV; break;
7572           case 0x1D: strcpy(insn[i],"DMULTU"); type=MULTDIV; break;
7573           case 0x1E: strcpy(insn[i],"DDIV"); type=MULTDIV; break;
7574           case 0x1F: strcpy(insn[i],"DDIVU"); type=MULTDIV; break;
7575           case 0x20: strcpy(insn[i],"ADD"); type=ALU; break;
7576           case 0x21: strcpy(insn[i],"ADDU"); type=ALU; break;
7577           case 0x22: strcpy(insn[i],"SUB"); type=ALU; break;
7578           case 0x23: strcpy(insn[i],"SUBU"); type=ALU; break;
7579           case 0x24: strcpy(insn[i],"AND"); type=ALU; break;
7580           case 0x25: strcpy(insn[i],"OR"); type=ALU; break;
7581           case 0x26: strcpy(insn[i],"XOR"); type=ALU; break;
7582           case 0x27: strcpy(insn[i],"NOR"); type=ALU; break;
7583           case 0x2A: strcpy(insn[i],"SLT"); type=ALU; break;
7584           case 0x2B: strcpy(insn[i],"SLTU"); type=ALU; break;
7585           case 0x2C: strcpy(insn[i],"DADD"); type=ALU; break;
7586           case 0x2D: strcpy(insn[i],"DADDU"); type=ALU; break;
7587           case 0x2E: strcpy(insn[i],"DSUB"); type=ALU; break;
7588           case 0x2F: strcpy(insn[i],"DSUBU"); type=ALU; break;
7589           case 0x30: strcpy(insn[i],"TGE"); type=NI; break;
7590           case 0x31: strcpy(insn[i],"TGEU"); type=NI; break;
7591           case 0x32: strcpy(insn[i],"TLT"); type=NI; break;
7592           case 0x33: strcpy(insn[i],"TLTU"); type=NI; break;
7593           case 0x34: strcpy(insn[i],"TEQ"); type=NI; break;
7594           case 0x36: strcpy(insn[i],"TNE"); type=NI; break;
7595           case 0x38: strcpy(insn[i],"DSLL"); type=SHIFTIMM; break;
7596           case 0x3A: strcpy(insn[i],"DSRL"); type=SHIFTIMM; break;
7597           case 0x3B: strcpy(insn[i],"DSRA"); type=SHIFTIMM; break;
7598           case 0x3C: strcpy(insn[i],"DSLL32"); type=SHIFTIMM; break;
7599           case 0x3E: strcpy(insn[i],"DSRL32"); type=SHIFTIMM; break;
7600           case 0x3F: strcpy(insn[i],"DSRA32"); type=SHIFTIMM; break;
7601         }
7602         break;
7603       case 0x01: strcpy(insn[i],"regimm"); type=NI;
7604         op2=(source[i]>>16)&0x1f;
7605         switch(op2)
7606         {
7607           case 0x00: strcpy(insn[i],"BLTZ"); type=SJUMP; break;
7608           case 0x01: strcpy(insn[i],"BGEZ"); type=SJUMP; break;
7609           case 0x02: strcpy(insn[i],"BLTZL"); type=SJUMP; break;
7610           case 0x03: strcpy(insn[i],"BGEZL"); type=SJUMP; break;
7611           case 0x08: strcpy(insn[i],"TGEI"); type=NI; break;
7612           case 0x09: strcpy(insn[i],"TGEIU"); type=NI; break;
7613           case 0x0A: strcpy(insn[i],"TLTI"); type=NI; break;
7614           case 0x0B: strcpy(insn[i],"TLTIU"); type=NI; break;
7615           case 0x0C: strcpy(insn[i],"TEQI"); type=NI; break;
7616           case 0x0E: strcpy(insn[i],"TNEI"); type=NI; break;
7617           case 0x10: strcpy(insn[i],"BLTZAL"); type=SJUMP; break;
7618           case 0x11: strcpy(insn[i],"BGEZAL"); type=SJUMP; break;
7619           case 0x12: strcpy(insn[i],"BLTZALL"); type=SJUMP; break;
7620           case 0x13: strcpy(insn[i],"BGEZALL"); type=SJUMP; break;
7621         }
7622         break;
7623       case 0x02: strcpy(insn[i],"J"); type=UJUMP; break;
7624       case 0x03: strcpy(insn[i],"JAL"); type=UJUMP; break;
7625       case 0x04: strcpy(insn[i],"BEQ"); type=CJUMP; break;
7626       case 0x05: strcpy(insn[i],"BNE"); type=CJUMP; break;
7627       case 0x06: strcpy(insn[i],"BLEZ"); type=CJUMP; break;
7628       case 0x07: strcpy(insn[i],"BGTZ"); type=CJUMP; break;
7629       case 0x08: strcpy(insn[i],"ADDI"); type=IMM16; break;
7630       case 0x09: strcpy(insn[i],"ADDIU"); type=IMM16; break;
7631       case 0x0A: strcpy(insn[i],"SLTI"); type=IMM16; break;
7632       case 0x0B: strcpy(insn[i],"SLTIU"); type=IMM16; break;
7633       case 0x0C: strcpy(insn[i],"ANDI"); type=IMM16; break;
7634       case 0x0D: strcpy(insn[i],"ORI"); type=IMM16; break;
7635       case 0x0E: strcpy(insn[i],"XORI"); type=IMM16; break;
7636       case 0x0F: strcpy(insn[i],"LUI"); type=IMM16; break;
7637       case 0x10: strcpy(insn[i],"cop0"); type=NI;
7638         op2=(source[i]>>21)&0x1f;
7639         switch(op2)
7640         {
7641           case 0x00: strcpy(insn[i],"MFC0"); type=COP0; break;
7642           case 0x04: strcpy(insn[i],"MTC0"); type=COP0; break;
7643           case 0x10: strcpy(insn[i],"tlb"); type=NI;
7644           switch(source[i]&0x3f)
7645           {
7646             case 0x01: strcpy(insn[i],"TLBR"); type=COP0; break;
7647             case 0x02: strcpy(insn[i],"TLBWI"); type=COP0; break;
7648             case 0x06: strcpy(insn[i],"TLBWR"); type=COP0; break;
7649             case 0x08: strcpy(insn[i],"TLBP"); type=COP0; break;
7650             case 0x18: strcpy(insn[i],"ERET"); type=COP0; break;
7651           }
7652         }
7653         break;
7654       case 0x11: strcpy(insn[i],"cop1"); type=NI;
7655         op2=(source[i]>>21)&0x1f;
7656         switch(op2)
7657         {
7658           case 0x00: strcpy(insn[i],"MFC1"); type=COP1; break;
7659           case 0x01: strcpy(insn[i],"DMFC1"); type=COP1; break;
7660           case 0x02: strcpy(insn[i],"CFC1"); type=COP1; break;
7661           case 0x04: strcpy(insn[i],"MTC1"); type=COP1; break;
7662           case 0x05: strcpy(insn[i],"DMTC1"); type=COP1; break;
7663           case 0x06: strcpy(insn[i],"CTC1"); type=COP1; break;
7664           case 0x08: strcpy(insn[i],"BC1"); type=FJUMP;
7665           switch((source[i]>>16)&0x3)
7666           {
7667             case 0x00: strcpy(insn[i],"BC1F"); break;
7668             case 0x01: strcpy(insn[i],"BC1T"); break;
7669             case 0x02: strcpy(insn[i],"BC1FL"); break;
7670             case 0x03: strcpy(insn[i],"BC1TL"); break;
7671           }
7672           break;
7673           case 0x10: strcpy(insn[i],"C1.S"); type=NI;
7674           switch(source[i]&0x3f)
7675           {
7676             case 0x00: strcpy(insn[i],"ADD.S"); type=FLOAT; break;
7677             case 0x01: strcpy(insn[i],"SUB.S"); type=FLOAT; break;
7678             case 0x02: strcpy(insn[i],"MUL.S"); type=FLOAT; break;
7679             case 0x03: strcpy(insn[i],"DIV.S"); type=FLOAT; break;
7680             case 0x04: strcpy(insn[i],"SQRT.S"); type=FLOAT; break;
7681             case 0x05: strcpy(insn[i],"ABS.S"); type=FLOAT; break;
7682             case 0x06: strcpy(insn[i],"MOV.S"); type=FLOAT; break;
7683             case 0x07: strcpy(insn[i],"NEG.S"); type=FLOAT; break;
7684             case 0x08: strcpy(insn[i],"ROUND.L.S"); type=FCONV; break;
7685             case 0x09: strcpy(insn[i],"TRUNC.L.S"); type=FCONV; break;
7686             case 0x0A: strcpy(insn[i],"CEIL.L.S"); type=FCONV; break;
7687             case 0x0B: strcpy(insn[i],"FLOOR.L.S"); type=FCONV; break;
7688             case 0x0C: strcpy(insn[i],"ROUND.W.S"); type=FCONV; break;
7689             case 0x0D: strcpy(insn[i],"TRUNC.W.S"); type=FCONV; break;
7690             case 0x0E: strcpy(insn[i],"CEIL.W.S"); type=FCONV; break;
7691             case 0x0F: strcpy(insn[i],"FLOOR.W.S"); type=FCONV; break;
7692             case 0x21: strcpy(insn[i],"CVT.D.S"); type=FCONV; break;
7693             case 0x24: strcpy(insn[i],"CVT.W.S"); type=FCONV; break;
7694             case 0x25: strcpy(insn[i],"CVT.L.S"); type=FCONV; break;
7695             case 0x30: strcpy(insn[i],"C.F.S"); type=FCOMP; break;
7696             case 0x31: strcpy(insn[i],"C.UN.S"); type=FCOMP; break;
7697             case 0x32: strcpy(insn[i],"C.EQ.S"); type=FCOMP; break;
7698             case 0x33: strcpy(insn[i],"C.UEQ.S"); type=FCOMP; break;
7699             case 0x34: strcpy(insn[i],"C.OLT.S"); type=FCOMP; break;
7700             case 0x35: strcpy(insn[i],"C.ULT.S"); type=FCOMP; break;
7701             case 0x36: strcpy(insn[i],"C.OLE.S"); type=FCOMP; break;
7702             case 0x37: strcpy(insn[i],"C.ULE.S"); type=FCOMP; break;
7703             case 0x38: strcpy(insn[i],"C.SF.S"); type=FCOMP; break;
7704             case 0x39: strcpy(insn[i],"C.NGLE.S"); type=FCOMP; break;
7705             case 0x3A: strcpy(insn[i],"C.SEQ.S"); type=FCOMP; break;
7706             case 0x3B: strcpy(insn[i],"C.NGL.S"); type=FCOMP; break;
7707             case 0x3C: strcpy(insn[i],"C.LT.S"); type=FCOMP; break;
7708             case 0x3D: strcpy(insn[i],"C.NGE.S"); type=FCOMP; break;
7709             case 0x3E: strcpy(insn[i],"C.LE.S"); type=FCOMP; break;
7710             case 0x3F: strcpy(insn[i],"C.NGT.S"); type=FCOMP; break;
7711           }
7712           break;
7713           case 0x11: strcpy(insn[i],"C1.D"); type=NI;
7714           switch(source[i]&0x3f)
7715           {
7716             case 0x00: strcpy(insn[i],"ADD.D"); type=FLOAT; break;
7717             case 0x01: strcpy(insn[i],"SUB.D"); type=FLOAT; break;
7718             case 0x02: strcpy(insn[i],"MUL.D"); type=FLOAT; break;
7719             case 0x03: strcpy(insn[i],"DIV.D"); type=FLOAT; break;
7720             case 0x04: strcpy(insn[i],"SQRT.D"); type=FLOAT; break;
7721             case 0x05: strcpy(insn[i],"ABS.D"); type=FLOAT; break;
7722             case 0x06: strcpy(insn[i],"MOV.D"); type=FLOAT; break;
7723             case 0x07: strcpy(insn[i],"NEG.D"); type=FLOAT; break;
7724             case 0x08: strcpy(insn[i],"ROUND.L.D"); type=FCONV; break;
7725             case 0x09: strcpy(insn[i],"TRUNC.L.D"); type=FCONV; break;
7726             case 0x0A: strcpy(insn[i],"CEIL.L.D"); type=FCONV; break;
7727             case 0x0B: strcpy(insn[i],"FLOOR.L.D"); type=FCONV; break;
7728             case 0x0C: strcpy(insn[i],"ROUND.W.D"); type=FCONV; break;
7729             case 0x0D: strcpy(insn[i],"TRUNC.W.D"); type=FCONV; break;
7730             case 0x0E: strcpy(insn[i],"CEIL.W.D"); type=FCONV; break;
7731             case 0x0F: strcpy(insn[i],"FLOOR.W.D"); type=FCONV; break;
7732             case 0x20: strcpy(insn[i],"CVT.S.D"); type=FCONV; break;
7733             case 0x24: strcpy(insn[i],"CVT.W.D"); type=FCONV; break;
7734             case 0x25: strcpy(insn[i],"CVT.L.D"); type=FCONV; break;
7735             case 0x30: strcpy(insn[i],"C.F.D"); type=FCOMP; break;
7736             case 0x31: strcpy(insn[i],"C.UN.D"); type=FCOMP; break;
7737             case 0x32: strcpy(insn[i],"C.EQ.D"); type=FCOMP; break;
7738             case 0x33: strcpy(insn[i],"C.UEQ.D"); type=FCOMP; break;
7739             case 0x34: strcpy(insn[i],"C.OLT.D"); type=FCOMP; break;
7740             case 0x35: strcpy(insn[i],"C.ULT.D"); type=FCOMP; break;
7741             case 0x36: strcpy(insn[i],"C.OLE.D"); type=FCOMP; break;
7742             case 0x37: strcpy(insn[i],"C.ULE.D"); type=FCOMP; break;
7743             case 0x38: strcpy(insn[i],"C.SF.D"); type=FCOMP; break;
7744             case 0x39: strcpy(insn[i],"C.NGLE.D"); type=FCOMP; break;
7745             case 0x3A: strcpy(insn[i],"C.SEQ.D"); type=FCOMP; break;
7746             case 0x3B: strcpy(insn[i],"C.NGL.D"); type=FCOMP; break;
7747             case 0x3C: strcpy(insn[i],"C.LT.D"); type=FCOMP; break;
7748             case 0x3D: strcpy(insn[i],"C.NGE.D"); type=FCOMP; break;
7749             case 0x3E: strcpy(insn[i],"C.LE.D"); type=FCOMP; break;
7750             case 0x3F: strcpy(insn[i],"C.NGT.D"); type=FCOMP; break;
7751           }
7752           break;
7753           case 0x14: strcpy(insn[i],"C1.W"); type=NI;
7754           switch(source[i]&0x3f)
7755           {
7756             case 0x20: strcpy(insn[i],"CVT.S.W"); type=FCONV; break;
7757             case 0x21: strcpy(insn[i],"CVT.D.W"); type=FCONV; break;
7758           }
7759           break;
7760           case 0x15: strcpy(insn[i],"C1.L"); type=NI;
7761           switch(source[i]&0x3f)
7762           {
7763             case 0x20: strcpy(insn[i],"CVT.S.L"); type=FCONV; break;
7764             case 0x21: strcpy(insn[i],"CVT.D.L"); type=FCONV; break;
7765           }
7766           break;
7767         }
7768         break;
7769       case 0x14: strcpy(insn[i],"BEQL"); type=CJUMP; break;
7770       case 0x15: strcpy(insn[i],"BNEL"); type=CJUMP; break;
7771       case 0x16: strcpy(insn[i],"BLEZL"); type=CJUMP; break;
7772       case 0x17: strcpy(insn[i],"BGTZL"); type=CJUMP; break;
7773       case 0x18: strcpy(insn[i],"DADDI"); type=IMM16; break;
7774       case 0x19: strcpy(insn[i],"DADDIU"); type=IMM16; break;
7775       case 0x1A: strcpy(insn[i],"LDL"); type=LOADLR; break;
7776       case 0x1B: strcpy(insn[i],"LDR"); type=LOADLR; break;
7777       case 0x20: strcpy(insn[i],"LB"); type=LOAD; break;
7778       case 0x21: strcpy(insn[i],"LH"); type=LOAD; break;
7779       case 0x22: strcpy(insn[i],"LWL"); type=LOADLR; break;
7780       case 0x23: strcpy(insn[i],"LW"); type=LOAD; break;
7781       case 0x24: strcpy(insn[i],"LBU"); type=LOAD; break;
7782       case 0x25: strcpy(insn[i],"LHU"); type=LOAD; break;
7783       case 0x26: strcpy(insn[i],"LWR"); type=LOADLR; break;
7784       case 0x27: strcpy(insn[i],"LWU"); type=LOAD; break;
7785       case 0x28: strcpy(insn[i],"SB"); type=STORE; break;
7786       case 0x29: strcpy(insn[i],"SH"); type=STORE; break;
7787       case 0x2A: strcpy(insn[i],"SWL"); type=STORELR; break;
7788       case 0x2B: strcpy(insn[i],"SW"); type=STORE; break;
7789       case 0x2C: strcpy(insn[i],"SDL"); type=STORELR; break;
7790       case 0x2D: strcpy(insn[i],"SDR"); type=STORELR; break;
7791       case 0x2E: strcpy(insn[i],"SWR"); type=STORELR; break;
7792       case 0x2F: strcpy(insn[i],"CACHE"); type=NOP; break;
7793       case 0x30: strcpy(insn[i],"LL"); type=NI; break;
7794       case 0x31: strcpy(insn[i],"LWC1"); type=C1LS; break;
7795       case 0x34: strcpy(insn[i],"LLD"); type=NI; break;
7796       case 0x35: strcpy(insn[i],"LDC1"); type=C1LS; break;
7797       case 0x37: strcpy(insn[i],"LD"); type=LOAD; break;
7798       case 0x38: strcpy(insn[i],"SC"); type=NI; break;
7799       case 0x39: strcpy(insn[i],"SWC1"); type=C1LS; break;
7800       case 0x3C: strcpy(insn[i],"SCD"); type=NI; break;
7801       case 0x3D: strcpy(insn[i],"SDC1"); type=C1LS; break;
7802       case 0x3F: strcpy(insn[i],"SD"); type=STORE; break;
7803       default: strcpy(insn[i],"???"); type=NI; break;
7804     }
7805     itype[i]=type;
7806     opcode2[i]=op2;
7807     /* Get registers/immediates */
7808     lt1[i]=0;
7809     us1[i]=0;
7810     us2[i]=0;
7811     dep1[i]=0;
7812     dep2[i]=0;
7813     switch(type) {
7814       case LOAD:
7815         rs1[i]=(source[i]>>21)&0x1f;
7816         rs2[i]=0;
7817         rt1[i]=(source[i]>>16)&0x1f;
7818         rt2[i]=0;
7819         imm[i]=(short)source[i];
7820         break;
7821       case STORE:
7822       case STORELR:
7823         rs1[i]=(source[i]>>21)&0x1f;
7824         rs2[i]=(source[i]>>16)&0x1f;
7825         rt1[i]=0;
7826         rt2[i]=0;
7827         imm[i]=(short)source[i];
7828         if(op==0x2c||op==0x2d||op==0x3f) us1[i]=rs2[i]; // 64-bit SDL/SDR/SD
7829         break;
7830       case LOADLR:
7831         // LWL/LWR only load part of the register,
7832         // therefore the target register must be treated as a source too
7833         rs1[i]=(source[i]>>21)&0x1f;
7834         rs2[i]=(source[i]>>16)&0x1f;
7835         rt1[i]=(source[i]>>16)&0x1f;
7836         rt2[i]=0;
7837         imm[i]=(short)source[i];
7838         if(op==0x1a||op==0x1b) us1[i]=rs2[i]; // LDR/LDL
7839         if(op==0x26) dep1[i]=rt1[i]; // LWR
7840         break;
7841       case IMM16:
7842         if (op==0x0f) rs1[i]=0; // LUI instruction has no source register
7843         else rs1[i]=(source[i]>>21)&0x1f;
7844         rs2[i]=0;
7845         rt1[i]=(source[i]>>16)&0x1f;
7846         rt2[i]=0;
7847         if(op>=0x0c&&op<=0x0e) { // ANDI/ORI/XORI
7848           imm[i]=(unsigned short)source[i];
7849         }else{
7850           imm[i]=(short)source[i];
7851         }
7852         if(op==0x18||op==0x19) us1[i]=rs1[i]; // DADDI/DADDIU
7853         if(op==0x0a||op==0x0b) us1[i]=rs1[i]; // SLTI/SLTIU
7854         if(op==0x0d||op==0x0e) dep1[i]=rs1[i]; // ORI/XORI
7855         break;
7856       case UJUMP:
7857         rs1[i]=0;
7858         rs2[i]=0;
7859         rt1[i]=0;
7860         rt2[i]=0;
7861         // The JAL instruction writes to r31.
7862         if (op&1) {
7863           rt1[i]=31;
7864         }
7865         rs2[i]=CCREG;
7866         break;
7867       case RJUMP:
7868         rs1[i]=(source[i]>>21)&0x1f;
7869         rs2[i]=0;
7870         rt1[i]=0;
7871         rt2[i]=0;
7872         // The JALR instruction writes to r31.
7873         if (op2&1) {
7874           rt1[i]=31;
7875         }
7876         rs2[i]=CCREG;
7877         break;
7878       case CJUMP:
7879         rs1[i]=(source[i]>>21)&0x1f;
7880         rs2[i]=(source[i]>>16)&0x1f;
7881         rt1[i]=0;
7882         rt2[i]=0;
7883         if(op&2) { // BGTZ/BLEZ
7884           rs2[i]=0;
7885         }
7886         us1[i]=rs1[i];
7887         us2[i]=rs2[i];
7888         likely[i]=op>>4;
7889         break;
7890       case SJUMP:
7891         rs1[i]=(source[i]>>21)&0x1f;
7892         rs2[i]=CCREG;
7893         rt1[i]=0;
7894         rt2[i]=0;
7895         us1[i]=rs1[i];
7896         if(op2&0x10) { // BxxAL
7897           rt1[i]=31;
7898           // NOTE: If the branch is not taken, r31 is still overwritten
7899         }
7900         likely[i]=(op2&2)>>1;
7901         break;
7902       case FJUMP:
7903         rs1[i]=FSREG;
7904         rs2[i]=CSREG;
7905         rt1[i]=0;
7906         rt2[i]=0;
7907         likely[i]=((source[i])>>17)&1;
7908         break;
7909       case ALU:
7910         rs1[i]=(source[i]>>21)&0x1f; // source
7911         rs2[i]=(source[i]>>16)&0x1f; // subtract amount
7912         rt1[i]=(source[i]>>11)&0x1f; // destination
7913         rt2[i]=0;
7914         if(op2==0x2a||op2==0x2b) { // SLT/SLTU
7915           us1[i]=rs1[i];us2[i]=rs2[i];
7916         }
7917         else if(op2>=0x24&&op2<=0x27) { // AND/OR/XOR/NOR
7918           dep1[i]=rs1[i];dep2[i]=rs2[i];
7919         }
7920         else if(op2>=0x2c&&op2<=0x2f) { // DADD/DSUB
7921           dep1[i]=rs1[i];dep2[i]=rs2[i];
7922         }
7923         break;
7924       case MULTDIV:
7925         rs1[i]=(source[i]>>21)&0x1f; // source
7926         rs2[i]=(source[i]>>16)&0x1f; // divisor
7927         rt1[i]=HIREG;
7928         rt2[i]=LOREG;
7929         if (op2>=0x1c&&op2<=0x1f) { // DMULT/DMULTU/DDIV/DDIVU
7930           us1[i]=rs1[i];us2[i]=rs2[i];
7931         }
7932         break;
7933       case MOV:
7934         rs1[i]=0;
7935         rs2[i]=0;
7936         rt1[i]=0;
7937         rt2[i]=0;
7938         if(op2==0x10) rs1[i]=HIREG; // MFHI
7939         if(op2==0x11) rt1[i]=HIREG; // MTHI
7940         if(op2==0x12) rs1[i]=LOREG; // MFLO
7941         if(op2==0x13) rt1[i]=LOREG; // MTLO
7942         if((op2&0x1d)==0x10) rt1[i]=(source[i]>>11)&0x1f; // MFxx
7943         if((op2&0x1d)==0x11) rs1[i]=(source[i]>>21)&0x1f; // MTxx
7944         dep1[i]=rs1[i];
7945         break;
7946       case SHIFT:
7947         rs1[i]=(source[i]>>16)&0x1f; // target of shift
7948         rs2[i]=(source[i]>>21)&0x1f; // shift amount
7949         rt1[i]=(source[i]>>11)&0x1f; // destination
7950         rt2[i]=0;
7951         // DSLLV/DSRLV/DSRAV are 64-bit
7952         if(op2>=0x14&&op2<=0x17) us1[i]=rs1[i];
7953         break;
7954       case SHIFTIMM:
7955         rs1[i]=(source[i]>>16)&0x1f;
7956         rs2[i]=0;
7957         rt1[i]=(source[i]>>11)&0x1f;
7958         rt2[i]=0;
7959         imm[i]=(source[i]>>6)&0x1f;
7960         // DSxx32 instructions
7961         if(op2>=0x3c) imm[i]|=0x20;
7962         // DSLL/DSRL/DSRA/DSRA32/DSRL32 but not DSLL32 require 64-bit source
7963         if(op2>=0x38&&op2!=0x3c) us1[i]=rs1[i];
7964         break;
7965       case COP0:
7966         rs1[i]=0;
7967         rs2[i]=0;
7968         rt1[i]=0;
7969         rt2[i]=0;
7970         if(op2==0) rt1[i]=(source[i]>>16)&0x1F; // MFC0
7971         if(op2==4) rs1[i]=(source[i]>>16)&0x1F; // MTC0
7972         if(op2==4&&((source[i]>>11)&0x1f)==12) rt2[i]=CSREG; // Status
7973         if(op2==16) if((source[i]&0x3f)==0x18) rs2[i]=CCREG; // ERET
7974         break;
7975       case COP1:
7976         rs1[i]=0;
7977         rs2[i]=0;
7978         rt1[i]=0;
7979         rt2[i]=0;
7980         if(op2<3) rt1[i]=(source[i]>>16)&0x1F; // MFC1/DMFC1/CFC1
7981         if(op2>3) rs1[i]=(source[i]>>16)&0x1F; // MTC1/DMTC1/CTC1
7982         if(op2==5) us1[i]=rs1[i]; // DMTC1
7983         rs2[i]=CSREG;
7984         break;
7985       case C1LS:
7986         rs1[i]=(source[i]>>21)&0x1F;
7987         rs2[i]=CSREG;
7988         rt1[i]=0;
7989         rt2[i]=0;
7990         imm[i]=(short)source[i];
7991         break;
7992       case FLOAT:
7993       case FCONV:
7994         rs1[i]=0;
7995         rs2[i]=CSREG;
7996         rt1[i]=0;
7997         rt2[i]=0;
7998         break;
7999       case FCOMP:
8000         rs1[i]=FSREG;
8001         rs2[i]=CSREG;
8002         rt1[i]=FSREG;
8003         rt2[i]=0;
8004         break;
8005       case SYSCALL:
8006         rs1[i]=CCREG;
8007         rs2[i]=0;
8008         rt1[i]=0;
8009         rt2[i]=0;
8010         break;
8011       default:
8012         rs1[i]=0;
8013         rs2[i]=0;
8014         rt1[i]=0;
8015         rt2[i]=0;
8016     }
8017     /* Calculate branch target addresses */
8018     if(type==UJUMP)
8019       ba[i]=((start+i*4+4)&0xF0000000)|(((unsigned int)source[i]<<6)>>4);
8020     else if(type==CJUMP&&rs1[i]==rs2[i]&&(op&1))
8021       ba[i]=start+i*4+8; // Ignore never taken branch
8022     else if(type==SJUMP&&rs1[i]==0&&!(op2&1))
8023       ba[i]=start+i*4+8; // Ignore never taken branch
8024     else if(type==CJUMP||type==SJUMP||type==FJUMP)
8025       ba[i]=start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14);
8026     else ba[i]=-1;
8027     /* Is this the end of the block? */
8028     if(i>0&&(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)) {
8029       if(rt1[i-1]!=31) { // Continue past subroutine call (JAL)
8030         done=1;
8031         // Does the block continue due to a branch?
8032         for(j=i-1;j>=0;j--)
8033         {
8034           if(ba[j]==start+i*4+4) done=j=0;
8035           if(ba[j]==start+i*4+8) done=j=0;
8036         }
8037       }
8038       else {
8039         if(stop_after_jal) done=1;
8040         // Stop on BREAK
8041         if((source[i+1]&0xfc00003f)==0x0d) done=1;
8042       }
8043       // Don't recompile stuff that's already compiled
8044       if(check_addr(start+i*4+4)) done=1;
8045       // Don't get too close to the limit
8046       if(i>MAXBLOCK/2) done=1;
8047     }
8048     if(i>0&&itype[i-1]==SYSCALL&&stop_after_jal) done=1;
8049     assert(i<MAXBLOCK-1);
8050     if(start+i*4==pagelimit-4) done=1;
8051     assert(start+i*4<pagelimit);
8052     if (i==MAXBLOCK-1) done=1;
8053     // Stop if we're compiling junk
8054     if(itype[i]==NI&&opcode[i]==0x11) {
8055       done=stop_after_jal=1;
8056       printf("Disabled speculative precompilation\n");
8057     }
8058   }
8059   slen=i;
8060   if(itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==RJUMP||itype[i-1]==FJUMP) {
8061     if(start+i*4==pagelimit) {
8062       itype[i-1]=SPAN;
8063     }
8064   }
8065   assert(slen>0);
8066
8067   /* Pass 2 - Register dependencies and branch targets */
8068
8069   unneeded_registers(0,slen-1,0);
8070
8071   /* Pass 3 - Register allocation */
8072
8073   struct regstat current; // Current register allocations/status
8074   current.is32=1;
8075   current.dirty=0;
8076   current.u=unneeded_reg[0];
8077   current.uu=unneeded_reg_upper[0];
8078   clear_all_regs(current.regmap);
8079   alloc_reg(&current,0,CCREG);
8080   dirty_reg(&current,CCREG);
8081   current.isconst=0;
8082   current.wasconst=0;
8083   int ds=0;
8084   int cc=0;
8085   int hr;
8086
8087   provisional_32bit();
8088
8089   if((u_int)addr&1) {
8090     // First instruction is delay slot
8091     cc=-1;
8092     bt[1]=1;
8093     ds=1;
8094     unneeded_reg[0]=1;
8095     unneeded_reg_upper[0]=1;
8096     current.regmap[HOST_BTREG]=BTREG;
8097   }
8098
8099   for(i=0;i<slen;i++)
8100   {
8101     if(bt[i])
8102     {
8103       int hr;
8104       for(hr=0;hr<HOST_REGS;hr++)
8105       {
8106         // Is this really necessary?
8107         if(current.regmap[hr]==0) current.regmap[hr]=-1;
8108       }
8109       current.isconst=0;
8110     }
8111     if(i>1)
8112     {
8113       if((opcode[i-2]&0x2f)==0x05) // BNE/BNEL
8114       {
8115         if(rs1[i-2]==0||rs2[i-2]==0)
8116         {
8117           if(rs1[i-2]) {
8118             current.is32|=1LL<<rs1[i-2];
8119             int hr=get_reg(current.regmap,rs1[i-2]|64);
8120             if(hr>=0) current.regmap[hr]=-1;
8121           }
8122           if(rs2[i-2]) {
8123             current.is32|=1LL<<rs2[i-2];
8124             int hr=get_reg(current.regmap,rs2[i-2]|64);
8125             if(hr>=0) current.regmap[hr]=-1;
8126           }
8127         }
8128       }
8129     }
8130     // If something jumps here with 64-bit values
8131     // then promote those registers to 64 bits
8132     if(bt[i])
8133     {
8134       uint64_t temp_is32=current.is32;
8135       for(j=i-1;j>=0;j--)
8136       {
8137         if(ba[j]==start+i*4)
8138           temp_is32&=branch_regs[j].is32;
8139       }
8140       for(j=i;j<slen;j++)
8141       {
8142         if(ba[j]==start+i*4)
8143           //temp_is32=1;
8144           temp_is32&=p32[j];
8145       }
8146       if(temp_is32!=current.is32) {
8147         //printf("dumping 32-bit regs (%x)\n",start+i*4);
8148         #ifdef DESTRUCTIVE_WRITEBACK
8149         for(hr=0;hr<HOST_REGS;hr++)
8150         {
8151           int r=current.regmap[hr];
8152           if(r>0&&r<64)
8153           {
8154             if((current.dirty>>hr)&((current.is32&~temp_is32)>>r)&1) {
8155               temp_is32|=1LL<<r;
8156               //printf("restore %d\n",r);
8157             }
8158           }
8159         }
8160         #endif
8161         current.is32=temp_is32;
8162       }
8163     }
8164     memcpy(regmap_pre[i],current.regmap,sizeof(current.regmap));
8165     regs[i].wasconst=current.isconst;
8166     regs[i].was32=current.is32;
8167     regs[i].wasdirty=current.dirty;
8168     #ifdef DESTRUCTIVE_WRITEBACK
8169     // To change a dirty register from 32 to 64 bits, we must write
8170     // it out during the previous cycle (for branches, 2 cycles)
8171     if(i<slen-1&&bt[i+1]&&itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP)
8172     {
8173       uint64_t temp_is32=current.is32;
8174       for(j=i-1;j>=0;j--)
8175       {
8176         if(ba[j]==start+i*4+4)
8177           temp_is32&=branch_regs[j].is32;
8178       }
8179       for(j=i;j<slen;j++)
8180       {
8181         if(ba[j]==start+i*4+4)
8182           //temp_is32=1;
8183           temp_is32&=p32[j];
8184       }
8185       if(temp_is32!=current.is32) {
8186         //printf("pre-dumping 32-bit regs (%x)\n",start+i*4);
8187         for(hr=0;hr<HOST_REGS;hr++)
8188         {
8189           int r=current.regmap[hr];
8190           if(r>0)
8191           {
8192             if((current.dirty>>hr)&((current.is32&~temp_is32)>>(r&63))&1) {
8193               if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP)
8194               {
8195                 if(rs1[i]!=(r&63)&&rs2[i]!=(r&63))
8196                 {
8197                   //printf("dump %d/r%d\n",hr,r);
8198                   current.regmap[hr]=-1;
8199                   if(get_reg(current.regmap,r|64)>=0)
8200                     current.regmap[get_reg(current.regmap,r|64)]=-1;
8201                 }
8202               }
8203             }
8204           }
8205         }
8206       }
8207     }
8208     else if(i<slen-2&&bt[i+2]&&(source[i-1]>>16)!=0x1000&&(itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP))
8209     {
8210       uint64_t temp_is32=current.is32;
8211       for(j=i-1;j>=0;j--)
8212       {
8213         if(ba[j]==start+i*4+8)
8214           temp_is32&=branch_regs[j].is32;
8215       }
8216       for(j=i;j<slen;j++)
8217       {
8218         if(ba[j]==start+i*4+8)
8219           //temp_is32=1;
8220           temp_is32&=p32[j];
8221       }
8222       if(temp_is32!=current.is32) {
8223         //printf("pre-dumping 32-bit regs (%x)\n",start+i*4);
8224         for(hr=0;hr<HOST_REGS;hr++)
8225         {
8226           int r=current.regmap[hr];
8227           if(r>0)
8228           {
8229             if((current.dirty>>hr)&((current.is32&~temp_is32)>>(r&63))&1) {
8230               if(rs1[i]!=(r&63)&&rs2[i]!=(r&63)&&rs1[i+1]!=(r&63)&&rs2[i+1]!=(r&63))
8231               {
8232                 //printf("dump %d/r%d\n",hr,r);
8233                 current.regmap[hr]=-1;
8234                 if(get_reg(current.regmap,r|64)>=0)
8235                   current.regmap[get_reg(current.regmap,r|64)]=-1;
8236               }
8237             }
8238           }
8239         }
8240       }
8241     }
8242     #endif
8243     if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP) {
8244       if(i+1<slen) {
8245         current.u=unneeded_reg[i+1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
8246         current.uu=unneeded_reg_upper[i+1]&~((1LL<<us1[i])|(1LL<<us2[i]));
8247         if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
8248         current.u|=1;
8249         current.uu|=1;
8250       } else {
8251         current.u=1;
8252         current.uu=1;
8253       }
8254     } else {
8255       if(i+1<slen) {
8256         current.u=branch_unneeded_reg[i]&~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
8257         current.uu=branch_unneeded_reg_upper[i]&~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
8258         if((~current.uu>>rt1[i+1])&1) current.uu&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
8259         current.u&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
8260         current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
8261         current.u|=1;
8262         current.uu|=1;
8263       } else { printf("oops, branch at end of block with no delay slot\n");exit(1); }
8264     }
8265     is_ds[i]=ds;
8266     if(ds) {
8267       ds=0; // Skip delay slot, already allocated as part of branch
8268       // ...but we need to alloc it in case something jumps here
8269       if(i+1<slen) {
8270         current.u=branch_unneeded_reg[i-1]&unneeded_reg[i+1];
8271         current.uu=branch_unneeded_reg_upper[i-1]&unneeded_reg_upper[i+1];
8272       }else{
8273         current.u=branch_unneeded_reg[i-1];
8274         current.uu=branch_unneeded_reg_upper[i-1];
8275       }
8276       current.u&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
8277       current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
8278       if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
8279       current.u|=1;
8280       current.uu|=1;
8281       struct regstat temp;
8282       memcpy(&temp,&current,sizeof(current));
8283       temp.wasdirty=temp.dirty;
8284       temp.was32=temp.is32;
8285       // TODO: Take into account unconditional branches, as below
8286       delayslot_alloc(&temp,i);
8287       memcpy(regs[i].regmap,temp.regmap,sizeof(temp.regmap));
8288       regs[i].wasdirty=temp.wasdirty;
8289       regs[i].was32=temp.was32;
8290       regs[i].dirty=temp.dirty;
8291       regs[i].is32=temp.is32;
8292       regs[i].isconst=0;
8293       regs[i].wasconst=0;
8294       current.isconst=0;
8295       // Create entry (branch target) regmap
8296       for(hr=0;hr<HOST_REGS;hr++)
8297       {
8298         int r=temp.regmap[hr];
8299         if(r>=0) {
8300           if(r!=regmap_pre[i][hr]) {
8301             regs[i].regmap_entry[hr]=-1;
8302           }
8303           else
8304           {
8305             if(r<64){
8306               if((current.u>>r)&1) {
8307                 regs[i].regmap_entry[hr]=-1;
8308                 regs[i].regmap[hr]=-1;
8309                 //Don't clear regs in the delay slot as the branch might need them
8310                 //current.regmap[hr]=-1;
8311               }else
8312                 regs[i].regmap_entry[hr]=r;
8313             }
8314             else {
8315               if((current.uu>>(r&63))&1) {
8316                 regs[i].regmap_entry[hr]=-1;
8317                 regs[i].regmap[hr]=-1;
8318                 //Don't clear regs in the delay slot as the branch might need them
8319                 //current.regmap[hr]=-1;
8320               }else
8321                 regs[i].regmap_entry[hr]=r;
8322             }
8323           }
8324         } else {
8325           // First instruction expects CCREG to be allocated
8326           if(i==0&&hr==HOST_CCREG)
8327             regs[i].regmap_entry[hr]=CCREG;
8328           else
8329             regs[i].regmap_entry[hr]=-1;
8330         }
8331       }
8332     }
8333     else { // Not delay slot
8334       switch(itype[i]) {
8335         case UJUMP:
8336           //current.isconst=0; // DEBUG
8337           //current.wasconst=0; // DEBUG
8338           //regs[i].wasconst=0; // DEBUG
8339           clear_const(&current,rt1[i]);
8340           alloc_cc(&current,i);
8341           dirty_reg(&current,CCREG);
8342           if (rt1[i]==31) {
8343             alloc_reg(&current,i,31);
8344             dirty_reg(&current,31);
8345             assert(rs1[i+1]!=31&&rs2[i+1]!=31);
8346             #ifdef REG_PREFETCH
8347             alloc_reg(&current,i,PTEMP);
8348             #endif
8349             //current.is32|=1LL<<rt1[i];
8350           }
8351           delayslot_alloc(&current,i+1);
8352           //current.isconst=0; // DEBUG
8353           ds=1;
8354           //printf("i=%d, isconst=%x\n",i,current.isconst);
8355           break;
8356         case RJUMP:
8357           //current.isconst=0;
8358           //current.wasconst=0;
8359           //regs[i].wasconst=0;
8360           clear_const(&current,rs1[i]);
8361           clear_const(&current,rt1[i]);
8362           alloc_cc(&current,i);
8363           dirty_reg(&current,CCREG);
8364           if(rs1[i]!=rt1[i+1]&&rs1[i]!=rt2[i+1]) {
8365             alloc_reg(&current,i,rs1[i]);
8366             if (rt1[i]==31) {
8367               alloc_reg(&current,i,31);
8368               dirty_reg(&current,31);
8369               assert(rs1[i+1]!=31&&rs2[i+1]!=31);
8370               #ifdef REG_PREFETCH
8371               alloc_reg(&current,i,PTEMP);
8372               #endif
8373             }
8374             #ifdef USE_MINI_HT
8375             if(rs1[i]==31) { // JALR
8376               alloc_reg(&current,i,RHASH);
8377               #ifndef HOST_IMM_ADDR32
8378               alloc_reg(&current,i,RHTBL);
8379               #endif
8380             }
8381             #endif
8382             delayslot_alloc(&current,i+1);
8383           } else {
8384             // The delay slot overwrites our source register,
8385             // allocate a temporary register to hold the old value.
8386             current.isconst=0;
8387             current.wasconst=0;
8388             regs[i].wasconst=0;
8389             delayslot_alloc(&current,i+1);
8390             current.isconst=0;
8391             alloc_reg(&current,i,RTEMP);
8392           }
8393           //current.isconst=0; // DEBUG
8394           ds=1;
8395           break;
8396         case CJUMP:
8397           //current.isconst=0;
8398           //current.wasconst=0;
8399           //regs[i].wasconst=0;
8400           clear_const(&current,rs1[i]);
8401           clear_const(&current,rs2[i]);
8402           if((opcode[i]&0x3E)==4) // BEQ/BNE
8403           {
8404             alloc_cc(&current,i);
8405             dirty_reg(&current,CCREG);
8406             if(rs1[i]) alloc_reg(&current,i,rs1[i]);
8407             if(rs2[i]) alloc_reg(&current,i,rs2[i]);
8408             if(!((current.is32>>rs1[i])&(current.is32>>rs2[i])&1))
8409             {
8410               if(rs1[i]) alloc_reg64(&current,i,rs1[i]);
8411               if(rs2[i]) alloc_reg64(&current,i,rs2[i]);
8412             }
8413             if((rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]))||
8414                (rs2[i]&&(rs2[i]==rt1[i+1]||rs2[i]==rt2[i+1]))) {
8415               // The delay slot overwrites one of our conditions.
8416               // Allocate the branch condition registers instead.
8417               // Note that such a sequence of instructions could
8418               // be considered a bug since the branch can not be
8419               // re-executed if an exception occurs.
8420               current.isconst=0;
8421               current.wasconst=0;
8422               regs[i].wasconst=0;
8423               if(rs1[i]) alloc_reg(&current,i,rs1[i]);
8424               if(rs2[i]) alloc_reg(&current,i,rs2[i]);
8425               if(!((current.is32>>rs1[i])&(current.is32>>rs2[i])&1))
8426               {
8427                 if(rs1[i]) alloc_reg64(&current,i,rs1[i]);
8428                 if(rs2[i]) alloc_reg64(&current,i,rs2[i]);
8429               }
8430             }
8431             else delayslot_alloc(&current,i+1);
8432           }
8433           else
8434           if((opcode[i]&0x3E)==6) // BLEZ/BGTZ
8435           {
8436             alloc_cc(&current,i);
8437             dirty_reg(&current,CCREG);
8438             alloc_reg(&current,i,rs1[i]);
8439             if(!(current.is32>>rs1[i]&1))
8440             {
8441               alloc_reg64(&current,i,rs1[i]);
8442             }
8443             if(rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1])) {
8444               // The delay slot overwrites one of our conditions.
8445               // Allocate the branch condition registers instead.
8446               // Note that such a sequence of instructions could
8447               // be considered a bug since the branch can not be
8448               // re-executed if an exception occurs.
8449               current.isconst=0;
8450               current.wasconst=0;
8451               regs[i].wasconst=0;
8452               if(rs1[i]) alloc_reg(&current,i,rs1[i]);
8453               if(!((current.is32>>rs1[i])&1))
8454               {
8455                 if(rs1[i]) alloc_reg64(&current,i,rs1[i]);
8456               }
8457             }
8458             else delayslot_alloc(&current,i+1);
8459           }
8460           else
8461           // Don't alloc the delay slot yet because we might not execute it
8462           if((opcode[i]&0x3E)==0x14) // BEQL/BNEL
8463           {
8464             current.isconst=0;
8465             current.wasconst=0;
8466             regs[i].wasconst=0;
8467             alloc_cc(&current,i);
8468             dirty_reg(&current,CCREG);
8469             alloc_reg(&current,i,rs1[i]);
8470             alloc_reg(&current,i,rs2[i]);
8471             if(!((current.is32>>rs1[i])&(current.is32>>rs2[i])&1))
8472             {
8473               alloc_reg64(&current,i,rs1[i]);
8474               alloc_reg64(&current,i,rs2[i]);
8475             }
8476           }
8477           else
8478           if((opcode[i]&0x3E)==0x16) // BLEZL/BGTZL
8479           {
8480             current.isconst=0;
8481             current.wasconst=0;
8482             regs[i].wasconst=0;
8483             alloc_cc(&current,i);
8484             dirty_reg(&current,CCREG);
8485             alloc_reg(&current,i,rs1[i]);
8486             if(!(current.is32>>rs1[i]&1))
8487             {
8488               alloc_reg64(&current,i,rs1[i]);
8489             }
8490           }
8491           ds=1;
8492           //current.isconst=0;
8493           break;
8494         case SJUMP:
8495           //current.isconst=0;
8496           //current.wasconst=0;
8497           //regs[i].wasconst=0;
8498           clear_const(&current,rs1[i]);
8499           clear_const(&current,rt1[i]);
8500           //if((opcode2[i]&0x1E)==0x0) // BLTZ/BGEZ
8501           if((opcode2[i]&0x0E)==0x0) // BLTZ/BGEZ
8502           {
8503             alloc_cc(&current,i);
8504             dirty_reg(&current,CCREG);
8505             alloc_reg(&current,i,rs1[i]);
8506             if(!(current.is32>>rs1[i]&1))
8507             {
8508               alloc_reg64(&current,i,rs1[i]);
8509             }
8510             if (rt1[i]==31) { // BLTZAL/BGEZAL
8511               alloc_reg(&current,i,31);
8512               dirty_reg(&current,31);
8513               assert(rs1[i+1]!=31&&rs2[i+1]!=31);
8514               //#ifdef REG_PREFETCH
8515               //alloc_reg(&current,i,PTEMP);
8516               //#endif
8517               //current.is32|=1LL<<rt1[i];
8518             }
8519             if(rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1])) {
8520               // The delay slot overwrites the branch condition.
8521               // Allocate the branch condition registers instead.
8522               // Note that such a sequence of instructions could
8523               // be considered a bug since the branch can not be
8524               // re-executed if an exception occurs.
8525               current.isconst=0;
8526               current.wasconst=0;
8527               regs[i].wasconst=0;
8528               if(rs1[i]) alloc_reg(&current,i,rs1[i]);
8529               if(!((current.is32>>rs1[i])&1))
8530               {
8531                 if(rs1[i]) alloc_reg64(&current,i,rs1[i]);
8532               }
8533             }
8534             else delayslot_alloc(&current,i+1);
8535           }
8536           else
8537           // Don't alloc the delay slot yet because we might not execute it
8538           if((opcode2[i]&0x1E)==0x2) // BLTZL/BGEZL
8539           {
8540             current.isconst=0;
8541             current.wasconst=0;
8542             regs[i].wasconst=0;
8543             alloc_cc(&current,i);
8544             dirty_reg(&current,CCREG);
8545             alloc_reg(&current,i,rs1[i]);
8546             if(!(current.is32>>rs1[i]&1))
8547             {
8548               alloc_reg64(&current,i,rs1[i]);
8549             }
8550           }
8551           ds=1;
8552           //current.isconst=0;
8553           break;
8554         case FJUMP:
8555           current.isconst=0;
8556           current.wasconst=0;
8557           regs[i].wasconst=0;
8558           if(likely[i]==0) // BC1F/BC1T
8559           {
8560             // TODO: Theoretically we can run out of registers here on x86.
8561             // The delay slot can allocate up to six, and we need to check
8562             // CSREG before executing the delay slot.  Possibly we can drop
8563             // the cycle count and then reload it after checking that the
8564             // FPU is in a usable state, or don't do out-of-order execution.
8565             alloc_cc(&current,i);
8566             dirty_reg(&current,CCREG);
8567             alloc_reg(&current,i,FSREG);
8568             alloc_reg(&current,i,CSREG);
8569             if(itype[i+1]==FCOMP) {
8570               // The delay slot overwrites the branch condition.
8571               // Allocate the branch condition registers instead.
8572               // Note that such a sequence of instructions could
8573               // be considered a bug since the branch can not be
8574               // re-executed if an exception occurs.
8575               alloc_cc(&current,i);
8576               dirty_reg(&current,CCREG);
8577               alloc_reg(&current,i,CSREG);
8578               alloc_reg(&current,i,FSREG);
8579             }
8580             else {
8581               delayslot_alloc(&current,i+1);
8582               alloc_reg(&current,i+1,CSREG);
8583             }
8584           }
8585           else
8586           // Don't alloc the delay slot yet because we might not execute it
8587           if(likely[i]) // BC1FL/BC1TL
8588           {
8589             alloc_cc(&current,i);
8590             dirty_reg(&current,CCREG);
8591             alloc_reg(&current,i,CSREG);
8592             alloc_reg(&current,i,FSREG);
8593           }
8594           ds=1;
8595           current.isconst=0;
8596           break;
8597         case IMM16:
8598           imm16_alloc(&current,i);
8599           break;
8600         case LOAD:
8601         case LOADLR:
8602           load_alloc(&current,i);
8603           break;
8604         case STORE:
8605         case STORELR:
8606           store_alloc(&current,i);
8607           break;
8608         case ALU:
8609           alu_alloc(&current,i);
8610           break;
8611         case SHIFT:
8612           shift_alloc(&current,i);
8613           break;
8614         case MULTDIV:
8615           multdiv_alloc(&current,i);
8616           break;
8617         case SHIFTIMM:
8618           shiftimm_alloc(&current,i);
8619           break;
8620         case MOV:
8621           mov_alloc(&current,i);
8622           break;
8623         case COP0:
8624           cop0_alloc(&current,i);
8625           break;
8626         case COP1:
8627           cop1_alloc(&current,i);
8628           break;
8629         case C1LS:
8630           c1ls_alloc(&current,i);
8631           break;
8632         case FCONV:
8633           fconv_alloc(&current,i);
8634           break;
8635         case FLOAT:
8636           float_alloc(&current,i);
8637           break;
8638         case FCOMP:
8639           fcomp_alloc(&current,i);
8640           break;
8641         case SYSCALL:
8642           syscall_alloc(&current,i);
8643           break;
8644         case SPAN:
8645           pagespan_alloc(&current,i);
8646           break;
8647       }
8648
8649       // Drop the upper half of registers that have become 32-bit
8650       current.uu|=current.is32&((1LL<<rt1[i])|(1LL<<rt2[i]));
8651       if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP) {
8652         current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
8653         if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
8654         current.uu|=1;
8655       } else {
8656         current.uu|=current.is32&((1LL<<rt1[i+1])|(1LL<<rt2[i+1]));
8657         current.uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
8658         if((~current.uu>>rt1[i+1])&1) current.uu&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
8659         current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
8660         current.uu|=1;
8661       }
8662
8663       // Create entry (branch target) regmap
8664       for(hr=0;hr<HOST_REGS;hr++)
8665       {
8666         int r,or,er;
8667         r=current.regmap[hr];
8668         if(r>=0) {
8669           if(r!=regmap_pre[i][hr]) {
8670             // TODO: delay slot (?)
8671             or=get_reg(regmap_pre[i],r); // Get old mapping for this register
8672             if(or<0||(r&63)>=TEMPREG){
8673               regs[i].regmap_entry[hr]=-1;
8674             }
8675             else
8676             {
8677               // Just move it to a different register
8678               regs[i].regmap_entry[hr]=r;
8679               // If it was dirty before, it's still dirty
8680               if((regs[i].wasdirty>>or)&1) dirty_reg(&current,r&63);
8681             }
8682           }
8683           else
8684           {
8685             // Unneeded
8686             if(r==0){
8687               regs[i].regmap_entry[hr]=0;
8688             }
8689             else
8690             if(r<64){
8691               if((current.u>>r)&1) {
8692                 regs[i].regmap_entry[hr]=-1;
8693                 //regs[i].regmap[hr]=-1;
8694                 current.regmap[hr]=-1;
8695               }else
8696                 regs[i].regmap_entry[hr]=r;
8697             }
8698             else {
8699               if((current.uu>>(r&63))&1) {
8700                 regs[i].regmap_entry[hr]=-1;
8701                 //regs[i].regmap[hr]=-1;
8702                 current.regmap[hr]=-1;
8703               }else
8704                 regs[i].regmap_entry[hr]=r;
8705             }
8706           }
8707         } else {
8708           // Branches expect CCREG to be allocated at the target
8709           if(regmap_pre[i][hr]==CCREG)
8710             regs[i].regmap_entry[hr]=CCREG;
8711           else
8712             regs[i].regmap_entry[hr]=-1;
8713         }
8714       }
8715       memcpy(regs[i].regmap,current.regmap,sizeof(current.regmap));
8716     }
8717     /* Branch post-alloc */
8718     if(i>0)
8719     {
8720       current.was32=current.is32;
8721       current.wasdirty=current.dirty;
8722       switch(itype[i-1]) {
8723         case UJUMP:
8724           memcpy(&branch_regs[i-1],&current,sizeof(current));
8725           branch_regs[i-1].isconst=0;
8726           branch_regs[i-1].wasconst=0;
8727           branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1]));
8728           branch_regs[i-1].uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i-1])|(1LL<<us2[i-1]));
8729           alloc_cc(&branch_regs[i-1],i-1);
8730           dirty_reg(&branch_regs[i-1],CCREG);
8731           if(rt1[i-1]==31) { // JAL
8732             alloc_reg(&branch_regs[i-1],i-1,31);
8733             dirty_reg(&branch_regs[i-1],31);
8734             branch_regs[i-1].is32|=1LL<<31;
8735           }
8736           memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
8737           memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
8738           break;
8739         case RJUMP:
8740           memcpy(&branch_regs[i-1],&current,sizeof(current));
8741           branch_regs[i-1].isconst=0;
8742           branch_regs[i-1].wasconst=0;
8743           branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1]));
8744           branch_regs[i-1].uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i-1])|(1LL<<us2[i-1]));
8745           alloc_cc(&branch_regs[i-1],i-1);
8746           dirty_reg(&branch_regs[i-1],CCREG);
8747           alloc_reg(&branch_regs[i-1],i-1,rs1[i-1]);
8748           if(rt1[i-1]==31) { // JALR
8749             alloc_reg(&branch_regs[i-1],i-1,31);
8750             dirty_reg(&branch_regs[i-1],31);
8751             branch_regs[i-1].is32|=1LL<<31;
8752           }
8753           #ifdef USE_MINI_HT
8754           if(rs1[i-1]==31) { // JALR
8755             alloc_reg(&branch_regs[i-1],i-1,RHASH);
8756             #ifndef HOST_IMM_ADDR32
8757             alloc_reg(&branch_regs[i-1],i-1,RHTBL);
8758             #endif
8759           }
8760           #endif
8761           memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
8762           memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
8763           break;
8764         case CJUMP:
8765           if((opcode[i-1]&0x3E)==4) // BEQ/BNE
8766           {
8767             alloc_cc(&current,i-1);
8768             dirty_reg(&current,CCREG);
8769             if((rs1[i-1]&&(rs1[i-1]==rt1[i]||rs1[i-1]==rt2[i]))||
8770                (rs2[i-1]&&(rs2[i-1]==rt1[i]||rs2[i-1]==rt2[i]))) {
8771               // The delay slot overwrote one of our conditions
8772               // Delay slot goes after the test (in order)
8773               current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
8774               current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i]));
8775               if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
8776               current.u|=1;
8777               current.uu|=1;
8778               delayslot_alloc(&current,i);
8779               current.isconst=0;
8780             }
8781             else
8782             {
8783               current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1]));
8784               current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i-1])|(1LL<<us2[i-1]));
8785               // Alloc the branch condition registers
8786               if(rs1[i-1]) alloc_reg(&current,i-1,rs1[i-1]);
8787               if(rs2[i-1]) alloc_reg(&current,i-1,rs2[i-1]);
8788               if(!((current.is32>>rs1[i-1])&(current.is32>>rs2[i-1])&1))
8789               {
8790                 if(rs1[i-1]) alloc_reg64(&current,i-1,rs1[i-1]);
8791                 if(rs2[i-1]) alloc_reg64(&current,i-1,rs2[i-1]);
8792               }
8793             }
8794             memcpy(&branch_regs[i-1],&current,sizeof(current));
8795             branch_regs[i-1].isconst=0;
8796             branch_regs[i-1].wasconst=0;
8797             memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
8798             memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
8799           }
8800           else
8801           if((opcode[i-1]&0x3E)==6) // BLEZ/BGTZ
8802           {
8803             alloc_cc(&current,i-1);
8804             dirty_reg(&current,CCREG);
8805             if(rs1[i-1]==rt1[i]||rs1[i-1]==rt2[i]) {
8806               // The delay slot overwrote the branch condition
8807               // Delay slot goes after the test (in order)
8808               current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
8809               current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i]));
8810               if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
8811               current.u|=1;
8812               current.uu|=1;
8813               delayslot_alloc(&current,i);
8814               current.isconst=0;
8815             }
8816             else
8817             {
8818               current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]);
8819               current.uu=branch_unneeded_reg_upper[i-1]&~(1LL<<us1[i-1]);
8820               // Alloc the branch condition register
8821               alloc_reg(&current,i-1,rs1[i-1]);
8822               if(!(current.is32>>rs1[i-1]&1))
8823               {
8824                 alloc_reg64(&current,i-1,rs1[i-1]);
8825               }
8826             }
8827             memcpy(&branch_regs[i-1],&current,sizeof(current));
8828             branch_regs[i-1].isconst=0;
8829             branch_regs[i-1].wasconst=0;
8830             memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
8831             memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
8832           }
8833           else
8834           // Alloc the delay slot in case the branch is taken
8835           if((opcode[i-1]&0x3E)==0x14) // BEQL/BNEL
8836           {
8837             memcpy(&branch_regs[i-1],&current,sizeof(current));
8838             branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
8839             branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
8840             if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
8841             alloc_cc(&branch_regs[i-1],i);
8842             dirty_reg(&branch_regs[i-1],CCREG);
8843             delayslot_alloc(&branch_regs[i-1],i);
8844             branch_regs[i-1].isconst=0;
8845             alloc_reg(&current,i,CCREG); // Not taken path
8846             dirty_reg(&current,CCREG);
8847             memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
8848           }
8849           else
8850           if((opcode[i-1]&0x3E)==0x16) // BLEZL/BGTZL
8851           {
8852             memcpy(&branch_regs[i-1],&current,sizeof(current));
8853             branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
8854             branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
8855             if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
8856             alloc_cc(&branch_regs[i-1],i);
8857             dirty_reg(&branch_regs[i-1],CCREG);
8858             delayslot_alloc(&branch_regs[i-1],i);
8859             branch_regs[i-1].isconst=0;
8860             alloc_reg(&current,i,CCREG); // Not taken path
8861             dirty_reg(&current,CCREG);
8862             memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
8863           }
8864           break;
8865         case SJUMP:
8866           //if((opcode2[i-1]&0x1E)==0) // BLTZ/BGEZ
8867           if((opcode2[i-1]&0x0E)==0) // BLTZ/BGEZ
8868           {
8869             alloc_cc(&current,i-1);
8870             dirty_reg(&current,CCREG);
8871             if(rs1[i-1]==rt1[i]||rs1[i-1]==rt2[i]) {
8872               // The delay slot overwrote the branch condition
8873               // Delay slot goes after the test (in order)
8874               current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
8875               current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i]));
8876               if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
8877               current.u|=1;
8878               current.uu|=1;
8879               delayslot_alloc(&current,i);
8880               current.isconst=0;
8881             }
8882             else
8883             {
8884               current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]);
8885               current.uu=branch_unneeded_reg_upper[i-1]&~(1LL<<us1[i-1]);
8886               // Alloc the branch condition register
8887               alloc_reg(&current,i-1,rs1[i-1]);
8888               if(!(current.is32>>rs1[i-1]&1))
8889               {
8890                 alloc_reg64(&current,i-1,rs1[i-1]);
8891               }
8892             }
8893             memcpy(&branch_regs[i-1],&current,sizeof(current));
8894             branch_regs[i-1].isconst=0;
8895             branch_regs[i-1].wasconst=0;
8896             memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
8897             memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
8898           }
8899           else
8900           // Alloc the delay slot in case the branch is taken
8901           if((opcode2[i-1]&0x1E)==2) // BLTZL/BGEZL
8902           {
8903             memcpy(&branch_regs[i-1],&current,sizeof(current));
8904             branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
8905             branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
8906             if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
8907             alloc_cc(&branch_regs[i-1],i);
8908             dirty_reg(&branch_regs[i-1],CCREG);
8909             delayslot_alloc(&branch_regs[i-1],i);
8910             branch_regs[i-1].isconst=0;
8911             alloc_reg(&current,i,CCREG); // Not taken path
8912             dirty_reg(&current,CCREG);
8913             memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
8914           }
8915           // FIXME: BLTZAL/BGEZAL
8916           if(opcode2[i-1]&0x10) { // BxxZAL
8917             alloc_reg(&branch_regs[i-1],i-1,31);
8918             dirty_reg(&branch_regs[i-1],31);
8919             branch_regs[i-1].is32|=1LL<<31;
8920           }
8921           break;
8922         case FJUMP:
8923           if(likely[i-1]==0) // BC1F/BC1T
8924           {
8925             alloc_cc(&current,i-1);
8926             dirty_reg(&current,CCREG);
8927             if(itype[i]==FCOMP) {
8928               // The delay slot overwrote the branch condition
8929               // Delay slot goes after the test (in order)
8930               delayslot_alloc(&current,i);
8931               current.isconst=0;
8932             }
8933             else
8934             {
8935               current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]);
8936               current.uu=branch_unneeded_reg_upper[i-1]&~(1LL<<us1[i-1]);
8937               // Alloc the branch condition register
8938               alloc_reg(&current,i-1,FSREG);
8939             }
8940             memcpy(&branch_regs[i-1],&current,sizeof(current));
8941             memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
8942           }
8943           else // BC1FL/BC1TL
8944           {
8945             // Alloc the delay slot in case the branch is taken
8946             memcpy(&branch_regs[i-1],&current,sizeof(current));
8947             branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
8948             branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
8949             if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
8950             alloc_cc(&branch_regs[i-1],i);
8951             dirty_reg(&branch_regs[i-1],CCREG);
8952             delayslot_alloc(&branch_regs[i-1],i);
8953             branch_regs[i-1].isconst=0;
8954             alloc_reg(&current,i,CCREG); // Not taken path
8955             dirty_reg(&current,CCREG);
8956             memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
8957           }
8958           break;
8959       }
8960
8961       if(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)
8962       {
8963         if(rt1[i-1]==31) // JAL/JALR
8964         {
8965           // Subroutine call will return here, don't alloc any registers
8966           current.is32=1;
8967           current.dirty=0;
8968           clear_all_regs(current.regmap);
8969           alloc_reg(&current,i,CCREG);
8970           dirty_reg(&current,CCREG);
8971         }
8972         else if(i+1<slen)
8973         {
8974           // Internal branch will jump here, match registers to caller
8975           current.is32=0x3FFFFFFFFLL;
8976           current.dirty=0;
8977           clear_all_regs(current.regmap);
8978           alloc_reg(&current,i,CCREG);
8979           dirty_reg(&current,CCREG);
8980           for(j=i-1;j>=0;j--)
8981           {
8982             if(ba[j]==start+i*4+4) {
8983               memcpy(current.regmap,branch_regs[j].regmap,sizeof(current.regmap));
8984               current.is32=branch_regs[j].is32;
8985               current.dirty=branch_regs[j].dirty;
8986               break;
8987             }
8988           }
8989           while(j>=0) {
8990             if(ba[j]==start+i*4+4) {
8991               for(hr=0;hr<HOST_REGS;hr++) {
8992                 if(current.regmap[hr]!=branch_regs[j].regmap[hr]) {
8993                   current.regmap[hr]=-1;
8994                 }
8995                 current.is32&=branch_regs[j].is32;
8996                 current.dirty&=branch_regs[j].dirty;
8997               }
8998             }
8999             j--;
9000           }
9001         }
9002       }
9003     }
9004
9005     // Count cycles in between branches
9006     ccadj[i]=cc;
9007     if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP||itype[i]==SYSCALL))
9008     {
9009       cc=0;
9010     }
9011     else
9012     {
9013       cc++;
9014     }
9015
9016     flush_dirty_uppers(&current);
9017     if(!is_ds[i]) {
9018       regs[i].is32=current.is32;
9019       regs[i].dirty=current.dirty;
9020       regs[i].isconst=current.isconst;
9021       memcpy(constmap[i],current.constmap,sizeof(current.constmap));
9022     }
9023     for(hr=0;hr<HOST_REGS;hr++) {
9024       if(hr!=EXCLUDE_REG&&regs[i].regmap[hr]>=0) {
9025         if(regmap_pre[i][hr]!=regs[i].regmap[hr]) {
9026           regs[i].wasconst&=~(1<<hr);
9027         }
9028       }
9029     }
9030     if(current.regmap[HOST_BTREG]==BTREG) current.regmap[HOST_BTREG]=-1;
9031   }
9032
9033   /* Pass 4 - Cull unused host registers */
9034
9035   uint64_t nr=0;
9036
9037   for (i=slen-1;i>=0;i--)
9038   {
9039     int hr;
9040     if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
9041     {
9042       if(ba[i]<start || ba[i]>=(start+slen*4))
9043       {
9044         // Branch out of this block, don't need anything
9045         nr=0;
9046       }
9047       else
9048       {
9049         // Internal branch
9050         // Need whatever matches the target
9051         nr=0;
9052         int t=(ba[i]-start)>>2;
9053         for(hr=0;hr<HOST_REGS;hr++)
9054         {
9055           if(regs[i].regmap_entry[hr]>=0) {
9056             if(regs[i].regmap_entry[hr]==regs[t].regmap_entry[hr]) nr|=1<<hr;
9057           }
9058         }
9059       }
9060       // Conditional branch may need registers for following instructions
9061       if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
9062       {
9063         if(i<slen-2) {
9064           nr|=needed_reg[i+2];
9065           for(hr=0;hr<HOST_REGS;hr++)
9066           {
9067             if(regmap_pre[i+2][hr]>=0&&get_reg(regs[i+2].regmap_entry,regmap_pre[i+2][hr])<0) nr&=~(1<<hr);
9068             //if((regmap_entry[i+2][hr])>=0) if(!((nr>>hr)&1)) printf("%x-bogus(%d=%d)\n",start+i*4,hr,regmap_entry[i+2][hr]);
9069           }
9070         }
9071       }
9072       // Don't need stuff which is overwritten
9073       if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr);
9074       if(regs[i].regmap[hr]<0) nr&=~(1<<hr);
9075       // Merge in delay slot
9076       for(hr=0;hr<HOST_REGS;hr++)
9077       {
9078         if(!likely[i]) {
9079           // These are overwritten unless the branch is "likely"
9080           // and the delay slot is nullified if not taken
9081           if(rt1[i+1]&&rt1[i+1]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9082           if(rt2[i+1]&&rt2[i+1]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9083         }
9084         if(us1[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9085         if(us2[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9086         if(rs1[i+1]==regmap_pre[i][hr]) nr|=1<<hr;
9087         if(rs2[i+1]==regmap_pre[i][hr]) nr|=1<<hr;
9088         if(us1[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9089         if(us2[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9090         if(rs1[i+1]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9091         if(rs2[i+1]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9092         if(dep1[i+1]&&!((unneeded_reg_upper[i]>>dep1[i+1])&1)) {
9093           if(dep1[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9094           if(dep2[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9095         }
9096         if(dep2[i+1]&&!((unneeded_reg_upper[i]>>dep2[i+1])&1)) {
9097           if(dep1[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9098           if(dep2[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9099         }
9100         if(itype[i+1]==STORE || itype[i+1]==STORELR || (opcode[i+1]&0x3b)==0x39) {
9101           if(regmap_pre[i][hr]==INVCP) nr|=1<<hr;
9102           if(regs[i].regmap_entry[hr]==INVCP) nr|=1<<hr;
9103         }
9104       }
9105     }
9106     else if(itype[i]==SYSCALL)
9107     {
9108       // SYSCALL instruction (software interrupt)
9109       nr=0;
9110     }
9111     else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
9112     {
9113       // ERET instruction (return from interrupt)
9114       nr=0;
9115     }
9116     else // Non-branch
9117     {
9118       if(i<slen-1) {
9119         for(hr=0;hr<HOST_REGS;hr++) {
9120           if(regmap_pre[i+1][hr]>=0&&get_reg(regs[i+1].regmap_entry,regmap_pre[i+1][hr])<0) nr&=~(1<<hr);
9121           if(regs[i].regmap[hr]!=regmap_pre[i+1][hr]) nr&=~(1<<hr);
9122           if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr);
9123           if(regs[i].regmap[hr]<0) nr&=~(1<<hr);
9124         }
9125       }
9126     }
9127     for(hr=0;hr<HOST_REGS;hr++)
9128     {
9129       // Overwritten registers are not needed
9130       if(rt1[i]&&rt1[i]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9131       if(rt2[i]&&rt2[i]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9132       if(FTEMP==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9133       // Source registers are needed
9134       if(us1[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9135       if(us2[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9136       if(rs1[i]==regmap_pre[i][hr]) nr|=1<<hr;
9137       if(rs2[i]==regmap_pre[i][hr]) nr|=1<<hr;
9138       if(us1[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9139       if(us2[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9140       if(rs1[i]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9141       if(rs2[i]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9142       if(dep1[i]&&!((unneeded_reg_upper[i]>>dep1[i])&1)) {
9143         if(dep1[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9144         if(dep1[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9145       }
9146       if(dep2[i]&&!((unneeded_reg_upper[i]>>dep2[i])&1)) {
9147         if(dep2[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9148         if(dep2[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9149       }
9150       if(itype[i]==STORE || itype[i]==STORELR || (opcode[i]&0x3b)==0x39) {
9151         if(regmap_pre[i][hr]==INVCP) nr|=1<<hr;
9152         if(regs[i].regmap_entry[hr]==INVCP) nr|=1<<hr;
9153       }
9154       // Don't store a register immediately after writing it,
9155       // may prevent dual-issue.
9156       // But do so if this is a branch target, otherwise we
9157       // might have to load the register before the branch.
9158       if(i>0&&!bt[i]&&((regs[i].wasdirty>>hr)&1)) {
9159         if((regmap_pre[i][hr]>0&&regmap_pre[i][hr]<64&&!((unneeded_reg[i]>>regmap_pre[i][hr])&1)) ||
9160            (regmap_pre[i][hr]>64&&!((unneeded_reg_upper[i]>>(regmap_pre[i][hr]&63))&1)) ) {
9161           if(rt1[i-1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9162           if(rt2[i-1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9163         }
9164         if((regs[i].regmap_entry[hr]>0&&regs[i].regmap_entry[hr]<64&&!((unneeded_reg[i]>>regs[i].regmap_entry[hr])&1)) ||
9165            (regs[i].regmap_entry[hr]>64&&!((unneeded_reg_upper[i]>>(regs[i].regmap_entry[hr]&63))&1)) ) {
9166           if(rt1[i-1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9167           if(rt2[i-1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9168         }
9169       }
9170     }
9171     // Cycle count is needed at branches.  Assume it is needed at the target too.
9172     if(i==0||bt[i]||itype[i]==CJUMP||itype[i]==FJUMP||itype[i]==SPAN) {
9173       if(regmap_pre[i][HOST_CCREG]==CCREG) nr|=1<<HOST_CCREG;
9174       if(regs[i].regmap_entry[HOST_CCREG]==CCREG) nr|=1<<HOST_CCREG;
9175     }
9176     // Save it
9177     needed_reg[i]=nr;
9178
9179     // Deallocate unneeded registers
9180     for(hr=0;hr<HOST_REGS;hr++)
9181     {
9182       if(!((nr>>hr)&1)) {
9183         if(regs[i].regmap_entry[hr]!=CCREG) regs[i].regmap_entry[hr]=-1;
9184         if((regs[i].regmap[hr]&63)!=rs1[i] && (regs[i].regmap[hr]&63)!=rs2[i] &&
9185            (regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] &&
9186            (regs[i].regmap[hr]&63)!=PTEMP && (regs[i].regmap[hr]&63)!=CCREG)
9187         {
9188           if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
9189           {
9190             if(likely[i]) {
9191               regs[i].regmap[hr]=-1;
9192               regs[i].isconst&=~(1<<hr);
9193               if(i<slen-2) regmap_pre[i+2][hr]=-1;
9194             }
9195           }
9196         }
9197         if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
9198         {
9199           int d1=0,d2=0,map=0,temp=0;
9200           if(get_reg(regs[i].regmap,rt1[i+1]|64)>=0||get_reg(branch_regs[i].regmap,rt1[i+1]|64)>=0)
9201           {
9202             d1=dep1[i+1];
9203             d2=dep2[i+1];
9204           }
9205           if(using_tlb) {
9206             if(itype[i+1]==LOAD || itype[i+1]==LOADLR ||
9207                itype[i+1]==STORE || itype[i+1]==STORELR ||
9208                itype[i+1]==C1LS )
9209             map=TLREG;
9210           } else
9211           if(itype[i+1]==STORE || itype[i+1]==STORELR || (opcode[i+1]&0x3b)==0x39) {
9212             map=INVCP;
9213           }
9214           if(itype[i+1]==LOADLR || itype[i+1]==STORELR ||
9215              itype[i+1]==C1LS )
9216             temp=FTEMP;
9217           if((regs[i].regmap[hr]&63)!=rs1[i] && (regs[i].regmap[hr]&63)!=rs2[i] &&
9218              (regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] &&
9219              (regs[i].regmap[hr]&63)!=rt1[i+1] && (regs[i].regmap[hr]&63)!=rt2[i+1] &&
9220              (regs[i].regmap[hr]^64)!=us1[i+1] && (regs[i].regmap[hr]^64)!=us2[i+1] &&
9221              (regs[i].regmap[hr]^64)!=d1 && (regs[i].regmap[hr]^64)!=d2 &&
9222              regs[i].regmap[hr]!=rs1[i+1] && regs[i].regmap[hr]!=rs2[i+1] &&
9223              (regs[i].regmap[hr]&63)!=temp && regs[i].regmap[hr]!=PTEMP &&
9224              regs[i].regmap[hr]!=RHASH && regs[i].regmap[hr]!=RHTBL &&
9225              regs[i].regmap[hr]!=RTEMP && regs[i].regmap[hr]!=CCREG &&
9226              regs[i].regmap[hr]!=map )
9227           {
9228             regs[i].regmap[hr]=-1;
9229             regs[i].isconst&=~(1<<hr);
9230             if((branch_regs[i].regmap[hr]&63)!=rs1[i] && (branch_regs[i].regmap[hr]&63)!=rs2[i] &&
9231                (branch_regs[i].regmap[hr]&63)!=rt1[i] && (branch_regs[i].regmap[hr]&63)!=rt2[i] &&
9232                (branch_regs[i].regmap[hr]&63)!=rt1[i+1] && (branch_regs[i].regmap[hr]&63)!=rt2[i+1] &&
9233                (branch_regs[i].regmap[hr]^64)!=us1[i+1] && (branch_regs[i].regmap[hr]^64)!=us2[i+1] &&
9234                (branch_regs[i].regmap[hr]^64)!=d1 && (branch_regs[i].regmap[hr]^64)!=d2 &&
9235                branch_regs[i].regmap[hr]!=rs1[i+1] && branch_regs[i].regmap[hr]!=rs2[i+1] &&
9236                (branch_regs[i].regmap[hr]&63)!=temp && branch_regs[i].regmap[hr]!=PTEMP &&
9237                branch_regs[i].regmap[hr]!=RHASH && branch_regs[i].regmap[hr]!=RHTBL &&
9238                branch_regs[i].regmap[hr]!=RTEMP && branch_regs[i].regmap[hr]!=CCREG &&
9239                branch_regs[i].regmap[hr]!=map)
9240             {
9241               branch_regs[i].regmap[hr]=-1;
9242               branch_regs[i].regmap_entry[hr]=-1;
9243               if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
9244               {
9245                 if(!likely[i]&&i<slen-2) {
9246                   regmap_pre[i+2][hr]=-1;
9247                 }
9248               }
9249             }
9250           }
9251         }
9252         else
9253         {
9254           // Non-branch
9255           if(i>0)
9256           {
9257             int d1=0,d2=0,map=-1,temp=-1;
9258             if(get_reg(regs[i].regmap,rt1[i]|64)>=0)
9259             {
9260               d1=dep1[i];
9261               d2=dep2[i];
9262             }
9263             if(using_tlb) {
9264               if(itype[i]==LOAD || itype[i]==LOADLR ||
9265                  itype[i]==STORE || itype[i]==STORELR ||
9266                  itype[i]==C1LS )
9267               map=TLREG;
9268             } else if(itype[i]==STORE || itype[i]==STORELR || (opcode[i]&0x3b)==0x39) {
9269               map=INVCP;
9270             }
9271             if(itype[i]==LOADLR || itype[i]==STORELR ||
9272                itype[i]==C1LS )
9273               temp=FTEMP;
9274             if((regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] &&
9275                (regs[i].regmap[hr]^64)!=us1[i] && (regs[i].regmap[hr]^64)!=us2[i] &&
9276                (regs[i].regmap[hr]^64)!=d1 && (regs[i].regmap[hr]^64)!=d2 &&
9277                regs[i].regmap[hr]!=rs1[i] && regs[i].regmap[hr]!=rs2[i] &&
9278                (regs[i].regmap[hr]&63)!=temp && regs[i].regmap[hr]!=map &&
9279                (itype[i]!=SPAN||regs[i].regmap[hr]!=CCREG))
9280             {
9281               if(i<slen-1&&!is_ds[i]) {
9282                 if(regmap_pre[i+1][hr]!=-1 || regs[i].regmap[hr]!=-1)
9283                 if(regmap_pre[i+1][hr]!=regs[i].regmap[hr])
9284                 if(regs[i].regmap[hr]<64||!((regs[i].was32>>(regs[i].regmap[hr]&63))&1))
9285                 {
9286                   printf("fail: %x (%d %d!=%d)\n",start+i*4,hr,regmap_pre[i+1][hr],regs[i].regmap[hr]);
9287                   assert(regmap_pre[i+1][hr]==regs[i].regmap[hr]);
9288                 }
9289                 regmap_pre[i+1][hr]=-1;
9290                 if(regs[i+1].regmap_entry[hr]==CCREG) regs[i+1].regmap_entry[hr]=-1;
9291               }
9292               regs[i].regmap[hr]=-1;
9293               regs[i].isconst&=~(1<<hr);
9294             }
9295           }
9296         }
9297       }
9298     }
9299   }
9300
9301   /* Pass 5 - Pre-allocate registers */
9302
9303   // If a register is allocated during a loop, try to allocate it for the
9304   // entire loop, if possible.  This avoids loading/storing registers
9305   // inside of the loop.
9306
9307   signed char f_regmap[HOST_REGS];
9308   clear_all_regs(f_regmap);
9309   for(i=0;i<slen-1;i++)
9310   {
9311     if(itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
9312     {
9313       if(ba[i]>=start && ba[i]<(start+i*4))
9314       if(itype[i+1]==NOP||itype[i+1]==MOV||itype[i+1]==ALU
9315       ||itype[i+1]==SHIFTIMM||itype[i+1]==IMM16||itype[i+1]==LOAD
9316       ||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS
9317       ||itype[i+1]==SHIFT||itype[i+1]==COP1||itype[i+1]==FLOAT
9318       ||itype[i+1]==FCOMP||itype[i+1]==FCONV)
9319       {
9320         int t=(ba[i]-start)>>2;
9321         if(t>0&&(itype[t-1]!=UJUMP&&itype[t-1]!=RJUMP&&itype[t-1]!=CJUMP&&itype[t-1]!=SJUMP&&itype[t-1]!=FJUMP)) // loop_preload can't handle jumps into delay slots
9322         if(t<2||(itype[t-2]!=UJUMP)) // call/ret assumes no registers allocated
9323         for(hr=0;hr<HOST_REGS;hr++)
9324         {
9325           if(regs[i].regmap[hr]>64) {
9326             if(!((regs[i].dirty>>hr)&1))
9327               f_regmap[hr]=regs[i].regmap[hr];
9328             else f_regmap[hr]=-1;
9329           }
9330           else if(regs[i].regmap[hr]>=0) f_regmap[hr]=regs[i].regmap[hr];
9331           if(branch_regs[i].regmap[hr]>64) {
9332             if(!((branch_regs[i].dirty>>hr)&1))
9333               f_regmap[hr]=branch_regs[i].regmap[hr];
9334             else f_regmap[hr]=-1;
9335           }
9336           else if(branch_regs[i].regmap[hr]>=0) f_regmap[hr]=branch_regs[i].regmap[hr];
9337           if(itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS
9338           ||itype[i+1]==SHIFT||itype[i+1]==COP1||itype[i+1]==FLOAT
9339           ||itype[i+1]==FCOMP||itype[i+1]==FCONV)
9340           {
9341             // Test both in case the delay slot is ooo,
9342             // could be done better...
9343             if(count_free_regs(branch_regs[i].regmap)<2
9344              ||count_free_regs(regs[i].regmap)<2)
9345               f_regmap[hr]=branch_regs[i].regmap[hr];
9346           }
9347           // Avoid dirty->clean transition
9348           // #ifdef DESTRUCTIVE_WRITEBACK here?
9349           if(t>0) if(get_reg(regmap_pre[t],f_regmap[hr])>=0) if((regs[t].wasdirty>>get_reg(regmap_pre[t],f_regmap[hr]))&1) f_regmap[hr]=-1;
9350           if(f_regmap[hr]>0) {
9351             if(regs[t].regmap_entry[hr]<0) {
9352               int r=f_regmap[hr];
9353               for(j=t;j<=i;j++)
9354               {
9355                 //printf("Test %x -> %x, %x %d/%d\n",start+i*4,ba[i],start+j*4,hr,r);
9356                 if(r<34&&((unneeded_reg[j]>>r)&1)) break;
9357                 if(r>63&&((unneeded_reg_upper[j]>>(r&63))&1)) break;
9358                 if(r>63) {
9359                   // NB This can exclude the case where the upper-half
9360                   // register is lower numbered than the lower-half
9361                   // register.  Not sure if it's worth fixing...
9362                   if(get_reg(regs[j].regmap,r&63)<0) break;
9363                   if(regs[j].is32&(1LL<<(r&63))) break;
9364                 }
9365                 if(regs[j].regmap[hr]==f_regmap[hr]&&(f_regmap[hr]&63)<TEMPREG) {
9366                   //printf("Hit %x -> %x, %x %d/%d\n",start+i*4,ba[i],start+j*4,hr,r);
9367                   int k;
9368                   if(regs[i].regmap[hr]==-1&&branch_regs[i].regmap[hr]==-1) {
9369                     if(get_reg(regs[i+2].regmap,f_regmap[hr])>=0) break;
9370                     if(r>63) {
9371                       if(get_reg(regs[i].regmap,r&63)<0) break;
9372                       if(get_reg(branch_regs[i].regmap,r&63)<0) break;
9373                     }
9374                     k=i;
9375                     while(k>1&&regs[k-1].regmap[hr]==-1) {
9376                       if(itype[k-1]==STORE||itype[k-1]==STORELR
9377                       ||itype[k-1]==C1LS||itype[k-1]==SHIFT||itype[k-1]==COP1
9378                       ||itype[k-1]==FLOAT||itype[k-1]==FCONV
9379                       ||itype[k-1]==FCOMP) {
9380                         if(count_free_regs(regs[k-1].regmap)<2) {
9381                           //printf("no free regs for store %x\n",start+(k-1)*4);
9382                           break;
9383                         }
9384                       }
9385                       else
9386                       if(itype[k-1]!=NOP&&itype[k-1]!=MOV&&itype[k-1]!=ALU&&itype[k-1]!=SHIFTIMM&&itype[k-1]!=IMM16&&itype[k-1]!=LOAD) break;
9387                       if(get_reg(regs[k-1].regmap,f_regmap[hr])>=0) {
9388                         //printf("no-match due to different register\n");
9389                         break;
9390                       }
9391                       if(itype[k-2]==UJUMP||itype[k-2]==RJUMP||itype[k-2]==CJUMP||itype[k-2]==SJUMP||itype[k-2]==FJUMP) {
9392                         //printf("no-match due to branch\n");
9393                         break;
9394                       }
9395                       // call/ret fast path assumes no registers allocated
9396                       if(k>2&&(itype[k-3]==UJUMP||itype[k-3]==RJUMP)) {
9397                         break;
9398                       }
9399                       if(r>63) {
9400                         // NB This can exclude the case where the upper-half
9401                         // register is lower numbered than the lower-half
9402                         // register.  Not sure if it's worth fixing...
9403                         if(get_reg(regs[k-1].regmap,r&63)<0) break;
9404                         if(regs[k-1].is32&(1LL<<(r&63))) break;
9405                       }
9406                       k--;
9407                     }
9408                     if(i<slen-1) {
9409                       if((regs[k].is32&(1LL<<f_regmap[hr]))!=
9410                         (regs[i+2].was32&(1LL<<f_regmap[hr]))) {
9411                         //printf("bad match after branch\n");
9412                         break;
9413                       }
9414                     }
9415                     if(regs[k-1].regmap[hr]==f_regmap[hr]&&regmap_pre[k][hr]==f_regmap[hr]) {
9416                       //printf("Extend r%d, %x ->\n",hr,start+k*4);
9417                       while(k<i) {
9418                         regs[k].regmap_entry[hr]=f_regmap[hr];
9419                         regs[k].regmap[hr]=f_regmap[hr];
9420                         regmap_pre[k+1][hr]=f_regmap[hr];
9421                         regs[k].wasdirty&=~(1<<hr);
9422                         regs[k].dirty&=~(1<<hr);
9423                         regs[k].wasdirty|=(1<<hr)&regs[k-1].dirty;
9424                         regs[k].dirty|=(1<<hr)&regs[k].wasdirty;
9425                         regs[k].wasconst&=~(1<<hr);
9426                         regs[k].isconst&=~(1<<hr);
9427                         k++;
9428                       }
9429                     }
9430                     else {
9431                       //printf("Fail Extend r%d, %x ->\n",hr,start+k*4);
9432                       break;
9433                     }
9434                     assert(regs[i-1].regmap[hr]==f_regmap[hr]);
9435                     if(regs[i-1].regmap[hr]==f_regmap[hr]&&regmap_pre[i][hr]==f_regmap[hr]) {
9436                       //printf("OK fill %x (r%d)\n",start+i*4,hr);
9437                       regs[i].regmap_entry[hr]=f_regmap[hr];
9438                       regs[i].regmap[hr]=f_regmap[hr];
9439                       regs[i].wasdirty&=~(1<<hr);
9440                       regs[i].dirty&=~(1<<hr);
9441                       regs[i].wasdirty|=(1<<hr)&regs[i-1].dirty;
9442                       regs[i].dirty|=(1<<hr)&regs[i-1].dirty;
9443                       regs[i].wasconst&=~(1<<hr);
9444                       regs[i].isconst&=~(1<<hr);
9445                       branch_regs[i].regmap_entry[hr]=f_regmap[hr];
9446                       branch_regs[i].wasdirty&=~(1<<hr);
9447                       branch_regs[i].wasdirty|=(1<<hr)&regs[i].dirty;
9448                       branch_regs[i].regmap[hr]=f_regmap[hr];
9449                       branch_regs[i].dirty&=~(1<<hr);
9450                       branch_regs[i].dirty|=(1<<hr)&regs[i].dirty;
9451                       branch_regs[i].wasconst&=~(1<<hr);
9452                       branch_regs[i].isconst&=~(1<<hr);
9453                       if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000) {
9454                         regmap_pre[i+2][hr]=f_regmap[hr];
9455                         regs[i+2].wasdirty&=~(1<<hr);
9456                         regs[i+2].wasdirty|=(1<<hr)&regs[i].dirty;
9457                         assert((branch_regs[i].is32&(1LL<<f_regmap[hr]))==
9458                           (regs[i+2].was32&(1LL<<f_regmap[hr])));
9459                       }
9460                     }
9461                   }
9462                   for(k=t;k<j;k++) {
9463                     regs[k].regmap_entry[hr]=f_regmap[hr];
9464                     regs[k].regmap[hr]=f_regmap[hr];
9465                     regmap_pre[k+1][hr]=f_regmap[hr];
9466                     regs[k+1].wasdirty&=~(1<<hr);
9467                     regs[k].dirty&=~(1<<hr);
9468                     regs[k].wasconst&=~(1<<hr);
9469                     regs[k].isconst&=~(1<<hr);
9470                   }
9471                   if(regs[j].regmap[hr]==f_regmap[hr])
9472                     regs[j].regmap_entry[hr]=f_regmap[hr];
9473                   break;
9474                 }
9475                 if(j==i) break;
9476                 if(regs[j].regmap[hr]>=0)
9477                   break;
9478                 if(get_reg(regs[j].regmap,f_regmap[hr])>=0) {
9479                   //printf("no-match due to different register\n");
9480                   break;
9481                 }
9482                 if((regs[j+1].is32&(1LL<<f_regmap[hr]))!=(regs[j].is32&(1LL<<f_regmap[hr]))) {
9483                   //printf("32/64 mismatch %x %d\n",start+j*4,hr);
9484                   break;
9485                 }
9486                 if(itype[j]==STORE||itype[j]==STORELR||itype[j]==C1LS
9487                 ||itype[j]==SHIFT||itype[j]==COP1||itype[j]==FLOAT
9488                 ||itype[j]==FCOMP||itype[j]==FCONV) {
9489                   if(count_free_regs(regs[j].regmap)<2) {
9490                     //printf("No free regs for store %x\n",start+j*4);
9491                     break;
9492                   }
9493                 }
9494                 else if(itype[j]!=NOP&&itype[j]!=MOV&&itype[j]!=ALU&&itype[j]!=SHIFTIMM&&itype[j]!=IMM16&&itype[j]!=LOAD) break;
9495                 if(f_regmap[hr]>=64) {
9496                   if(regs[j].is32&(1LL<<(f_regmap[hr]&63))) {
9497                     break;
9498                   }
9499                   else
9500                   {
9501                     if(get_reg(regs[j].regmap,f_regmap[hr]&63)<0) {
9502                       break;
9503                     }
9504                   }
9505                 }
9506               }
9507             }
9508           }
9509         }
9510       }
9511     }else{
9512       int count=0;
9513       for(hr=0;hr<HOST_REGS;hr++)
9514       {
9515         if(hr!=EXCLUDE_REG) {
9516           if(regs[i].regmap[hr]>64) {
9517             if(!((regs[i].dirty>>hr)&1))
9518               f_regmap[hr]=regs[i].regmap[hr];
9519           }
9520           else if(regs[i].regmap[hr]>=0) f_regmap[hr]=regs[i].regmap[hr];
9521           else if(regs[i].regmap[hr]<0) count++;
9522         }
9523       }
9524       // Try to restore cycle count at branch targets
9525       if(bt[i]) {
9526         for(j=i;j<slen-1;j++) {
9527           if(regs[j].regmap[HOST_CCREG]!=-1) break;
9528           if(itype[j]==STORE||itype[j]==STORELR||itype[j]==C1LS
9529           ||itype[j]==SHIFT||itype[j]==COP1||itype[j]==FLOAT
9530           ||itype[j]==FCOMP||itype[j]==FCONV) {
9531             if(count_free_regs(regs[j].regmap)<2) {
9532               //printf("no free regs for store %x\n",start+j*4);
9533               break;
9534             }
9535           }
9536           else
9537           if(itype[j]!=NOP&&itype[j]!=MOV&&itype[j]!=ALU&&itype[j]!=SHIFTIMM&&itype[j]!=IMM16&&itype[j]!=LOAD) break;
9538         }
9539         if(regs[j].regmap[HOST_CCREG]==CCREG) {
9540           int k=i;
9541           //printf("Extend CC, %x -> %x\n",start+k*4,start+j*4);
9542           while(k<j) {
9543             regs[k].regmap_entry[HOST_CCREG]=CCREG;
9544             regs[k].regmap[HOST_CCREG]=CCREG;
9545             regmap_pre[k+1][HOST_CCREG]=CCREG;
9546             regs[k+1].wasdirty|=1<<HOST_CCREG;
9547             regs[k].dirty|=1<<HOST_CCREG;
9548             regs[k].wasconst&=~(1<<HOST_CCREG);
9549             regs[k].isconst&=~(1<<HOST_CCREG);
9550             k++;
9551           }
9552           regs[j].regmap_entry[HOST_CCREG]=CCREG;
9553         }
9554         // Work backwards from the branch target
9555         if(j>i&&f_regmap[HOST_CCREG]==CCREG)
9556         {
9557           //printf("Extend backwards\n");
9558           int k;
9559           k=i;
9560           while(regs[k-1].regmap[HOST_CCREG]==-1) {
9561             if(itype[k-1]==STORE||itype[k-1]==STORELR||itype[k-1]==C1LS
9562             ||itype[k-1]==SHIFT||itype[k-1]==COP1||itype[k-1]==FLOAT
9563             ||itype[k-1]==FCONV||itype[k-1]==FCOMP) {
9564               if(count_free_regs(regs[k-1].regmap)<2) {
9565                 //printf("no free regs for store %x\n",start+(k-1)*4);
9566                 break;
9567               }
9568             }
9569             else
9570             if(itype[k-1]!=NOP&&itype[k-1]!=MOV&&itype[k-1]!=ALU&&itype[k-1]!=SHIFTIMM&&itype[k-1]!=IMM16&&itype[k-1]!=LOAD) break;
9571             k--;
9572           }
9573           if(regs[k-1].regmap[HOST_CCREG]==CCREG) {
9574             //printf("Extend CC, %x ->\n",start+k*4);
9575             while(k<=i) {
9576               regs[k].regmap_entry[HOST_CCREG]=CCREG;
9577               regs[k].regmap[HOST_CCREG]=CCREG;
9578               regmap_pre[k+1][HOST_CCREG]=CCREG;
9579               regs[k+1].wasdirty|=1<<HOST_CCREG;
9580               regs[k].dirty|=1<<HOST_CCREG;
9581               regs[k].wasconst&=~(1<<HOST_CCREG);
9582               regs[k].isconst&=~(1<<HOST_CCREG);
9583               k++;
9584             }
9585           }
9586           else {
9587             //printf("Fail Extend CC, %x ->\n",start+k*4);
9588           }
9589         }
9590       }
9591       if(itype[i]!=STORE&&itype[i]!=STORELR&&itype[i]!=C1LS&&itype[i]!=SHIFT&&
9592          itype[i]!=NOP&&itype[i]!=MOV&&itype[i]!=ALU&&itype[i]!=SHIFTIMM&&
9593          itype[i]!=IMM16&&itype[i]!=LOAD&&itype[i]!=COP1&&itype[i]!=FLOAT&&
9594          itype[i]!=FCONV&&itype[i]!=FCOMP)
9595       {
9596         memcpy(f_regmap,regs[i].regmap,sizeof(f_regmap));
9597       }
9598     }
9599   }
9600
9601   // This allocates registers (if possible) one instruction prior
9602   // to use, which can avoid a load-use penalty on certain CPUs.
9603   for(i=0;i<slen-1;i++)
9604   {
9605     if(!i||(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP))
9606     {
9607       if(!bt[i+1])
9608       {
9609         if(itype[i]==ALU||itype[i]==MOV||itype[i]==LOAD||itype[i]==SHIFTIMM||itype[i]==IMM16||(itype[i]==COP1&&opcode2[i]<3))
9610         {
9611           if(rs1[i+1]) {
9612             if((hr=get_reg(regs[i+1].regmap,rs1[i+1]))>=0)
9613             {
9614               if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
9615               {
9616                 regs[i].regmap[hr]=regs[i+1].regmap[hr];
9617                 regmap_pre[i+1][hr]=regs[i+1].regmap[hr];
9618                 regs[i+1].regmap_entry[hr]=regs[i+1].regmap[hr];
9619                 regs[i].isconst&=~(1<<hr);
9620                 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
9621                 constmap[i][hr]=constmap[i+1][hr];
9622                 regs[i+1].wasdirty&=~(1<<hr);
9623                 regs[i].dirty&=~(1<<hr);
9624               }
9625             }
9626           }
9627           if(rs2[i+1]) {
9628             if((hr=get_reg(regs[i+1].regmap,rs2[i+1]))>=0)
9629             {
9630               if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
9631               {
9632                 regs[i].regmap[hr]=regs[i+1].regmap[hr];
9633                 regmap_pre[i+1][hr]=regs[i+1].regmap[hr];
9634                 regs[i+1].regmap_entry[hr]=regs[i+1].regmap[hr];
9635                 regs[i].isconst&=~(1<<hr);
9636                 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
9637                 constmap[i][hr]=constmap[i+1][hr];
9638                 regs[i+1].wasdirty&=~(1<<hr);
9639                 regs[i].dirty&=~(1<<hr);
9640               }
9641             }
9642           }
9643           if(itype[i+1]==LOAD&&rs1[i+1]&&get_reg(regs[i+1].regmap,rs1[i+1])<0) {
9644             if((hr=get_reg(regs[i+1].regmap,rt1[i+1]))>=0)
9645             {
9646               if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
9647               {
9648                 regs[i].regmap[hr]=rs1[i+1];
9649                 regmap_pre[i+1][hr]=rs1[i+1];
9650                 regs[i+1].regmap_entry[hr]=rs1[i+1];
9651                 regs[i].isconst&=~(1<<hr);
9652                 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
9653                 constmap[i][hr]=constmap[i+1][hr];
9654                 regs[i+1].wasdirty&=~(1<<hr);
9655                 regs[i].dirty&=~(1<<hr);
9656               }
9657             }
9658           }
9659           if(lt1[i+1]&&get_reg(regs[i+1].regmap,rs1[i+1])<0) {
9660             if((hr=get_reg(regs[i+1].regmap,rt1[i+1]))>=0)
9661             {
9662               if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
9663               {
9664                 regs[i].regmap[hr]=rs1[i+1];
9665                 regmap_pre[i+1][hr]=rs1[i+1];
9666                 regs[i+1].regmap_entry[hr]=rs1[i+1];
9667                 regs[i].isconst&=~(1<<hr);
9668                 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
9669                 constmap[i][hr]=constmap[i+1][hr];
9670                 regs[i+1].wasdirty&=~(1<<hr);
9671                 regs[i].dirty&=~(1<<hr);
9672               }
9673             }
9674           }
9675           #ifndef HOST_IMM_ADDR32
9676           if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS) {
9677             hr=get_reg(regs[i+1].regmap,TLREG);
9678             if(hr>=0) {
9679               int sr=get_reg(regs[i+1].regmap,rs1[i+1]);
9680               if(sr>=0&&((regs[i+1].wasconst>>sr)&1)) {
9681                 int nr;
9682                 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
9683                 {
9684                   regs[i].regmap[hr]=MGEN1+((i+1)&1);
9685                   regmap_pre[i+1][hr]=MGEN1+((i+1)&1);
9686                   regs[i+1].regmap_entry[hr]=MGEN1+((i+1)&1);
9687                   regs[i].isconst&=~(1<<hr);
9688                   regs[i].isconst|=regs[i+1].isconst&(1<<hr);
9689                   constmap[i][hr]=constmap[i+1][hr];
9690                   regs[i+1].wasdirty&=~(1<<hr);
9691                   regs[i].dirty&=~(1<<hr);
9692                 }
9693                 else if((nr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1))>=0)
9694                 {
9695                   // move it to another register
9696                   regs[i+1].regmap[hr]=-1;
9697                   regmap_pre[i+2][hr]=-1;
9698                   regs[i+1].regmap[nr]=TLREG;
9699                   regmap_pre[i+2][nr]=TLREG;
9700                   regs[i].regmap[nr]=MGEN1+((i+1)&1);
9701                   regmap_pre[i+1][nr]=MGEN1+((i+1)&1);
9702                   regs[i+1].regmap_entry[nr]=MGEN1+((i+1)&1);
9703                   regs[i].isconst&=~(1<<nr);
9704                   regs[i+1].isconst&=~(1<<nr);
9705                   regs[i].dirty&=~(1<<nr);
9706                   regs[i+1].wasdirty&=~(1<<nr);
9707                   regs[i+1].dirty&=~(1<<nr);
9708                   regs[i+2].wasdirty&=~(1<<nr);
9709                 }
9710               }
9711             }
9712           }
9713           #endif
9714           if(itype[i+1]==STORE||itype[i+1]==STORELR||opcode[i+1]==0x39||opcode[i+1]==0x3D) { // SB/SH/SW/SD/SWC1/SDC1
9715             if(get_reg(regs[i+1].regmap,rs1[i+1])<0) {
9716               hr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1);
9717               if(hr<0) hr=get_reg(regs[i+1].regmap,-1);
9718               else {regs[i+1].regmap[hr]=AGEN1+((i+1)&1);regs[i+1].isconst&=~(1<<hr);}
9719               assert(hr>=0);
9720               if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
9721               {
9722                 regs[i].regmap[hr]=rs1[i+1];
9723                 regmap_pre[i+1][hr]=rs1[i+1];
9724                 regs[i+1].regmap_entry[hr]=rs1[i+1];
9725                 regs[i].isconst&=~(1<<hr);
9726                 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
9727                 constmap[i][hr]=constmap[i+1][hr];
9728                 regs[i+1].wasdirty&=~(1<<hr);
9729                 regs[i].dirty&=~(1<<hr);
9730               }
9731             }
9732           }
9733           if(itype[i+1]==LOADLR||opcode[i+1]==0x31||opcode[i+1]==0x35) { // LWC1/LDC1
9734             if(get_reg(regs[i+1].regmap,rs1[i+1])<0) {
9735               int nr;
9736               hr=get_reg(regs[i+1].regmap,FTEMP);
9737               assert(hr>=0);
9738               if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
9739               {
9740                 regs[i].regmap[hr]=rs1[i+1];
9741                 regmap_pre[i+1][hr]=rs1[i+1];
9742                 regs[i+1].regmap_entry[hr]=rs1[i+1];
9743                 regs[i].isconst&=~(1<<hr);
9744                 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
9745                 constmap[i][hr]=constmap[i+1][hr];
9746                 regs[i+1].wasdirty&=~(1<<hr);
9747                 regs[i].dirty&=~(1<<hr);
9748               }
9749               else if((nr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1))>=0)
9750               {
9751                 // move it to another register
9752                 regs[i+1].regmap[hr]=-1;
9753                 regmap_pre[i+2][hr]=-1;
9754                 regs[i+1].regmap[nr]=FTEMP;
9755                 regmap_pre[i+2][nr]=FTEMP;
9756                 regs[i].regmap[nr]=rs1[i+1];
9757                 regmap_pre[i+1][nr]=rs1[i+1];
9758                 regs[i+1].regmap_entry[nr]=rs1[i+1];
9759                 regs[i].isconst&=~(1<<nr);
9760                 regs[i+1].isconst&=~(1<<nr);
9761                 regs[i].dirty&=~(1<<nr);
9762                 regs[i+1].wasdirty&=~(1<<nr);
9763                 regs[i+1].dirty&=~(1<<nr);
9764                 regs[i+2].wasdirty&=~(1<<nr);
9765               }
9766             }
9767           }
9768           if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR/*||itype[i+1]==C1LS*/) {
9769             if(itype[i+1]==LOAD)
9770               hr=get_reg(regs[i+1].regmap,rt1[i+1]);
9771             if(itype[i+1]==LOADLR||opcode[i+1]==0x31||opcode[i+1]==0x35) // LWC1/LDC1
9772               hr=get_reg(regs[i+1].regmap,FTEMP);
9773             if(itype[i+1]==STORE||itype[i+1]==STORELR||opcode[i+1]==0x39||opcode[i+1]==0x3D) { // SWC1/SDC1
9774               hr=get_reg(regs[i+1].regmap,AGEN1+((i+1)&1));
9775               if(hr<0) hr=get_reg(regs[i+1].regmap,-1);
9776             }
9777             if(hr>=0&&regs[i].regmap[hr]<0) {
9778               int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
9779               if(rs>=0&&((regs[i+1].wasconst>>rs)&1)) {
9780                 regs[i].regmap[hr]=AGEN1+((i+1)&1);
9781                 regmap_pre[i+1][hr]=AGEN1+((i+1)&1);
9782                 regs[i+1].regmap_entry[hr]=AGEN1+((i+1)&1);
9783                 regs[i].isconst&=~(1<<hr);
9784                 regs[i+1].wasdirty&=~(1<<hr);
9785                 regs[i].dirty&=~(1<<hr);
9786               }
9787             }
9788           }
9789         }
9790       }
9791     }
9792   }
9793
9794   /* Pass 6 - Optimize clean/dirty state */
9795   clean_registers(0,slen-1,1);
9796
9797   /* Pass 7 - Identify 32-bit registers */
9798
9799   provisional_r32();
9800
9801   u_int r32=0;
9802
9803   for (i=slen-1;i>=0;i--)
9804   {
9805     int hr;
9806     if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
9807     {
9808       if(ba[i]<start || ba[i]>=(start+slen*4))
9809       {
9810         // Branch out of this block, don't need anything
9811         r32=0;
9812       }
9813       else
9814       {
9815         // Internal branch
9816         // Need whatever matches the target
9817         // (and doesn't get overwritten by the delay slot instruction)
9818         r32=0;
9819         int t=(ba[i]-start)>>2;
9820         if(ba[i]>start+i*4) {
9821           // Forward branch
9822           if(!(requires_32bit[t]&~regs[i].was32))
9823             r32|=requires_32bit[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
9824         }else{
9825           // Backward branch
9826           //if(!(regs[t].was32&~unneeded_reg_upper[t]&~regs[i].was32))
9827           //  r32|=regs[t].was32&~unneeded_reg_upper[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
9828           if(!(pr32[t]&~regs[i].was32))
9829             r32|=pr32[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
9830         }
9831       }
9832       // Conditional branch may need registers for following instructions
9833       if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
9834       {
9835         if(i<slen-2) {
9836           r32|=requires_32bit[i+2];
9837           r32&=regs[i].was32;
9838           // Mark this address as a branch target since it may be called
9839           // upon return from interrupt
9840           bt[i+2]=1;
9841         }
9842       }
9843       // Merge in delay slot
9844       if(!likely[i]) {
9845         // These are overwritten unless the branch is "likely"
9846         // and the delay slot is nullified if not taken
9847         r32&=~(1LL<<rt1[i+1]);
9848         r32&=~(1LL<<rt2[i+1]);
9849       }
9850       // Assume these are needed (delay slot)
9851       if(us1[i+1]>0)
9852       {
9853         if((regs[i].was32>>us1[i+1])&1) r32|=1LL<<us1[i+1];
9854       }
9855       if(us2[i+1]>0)
9856       {
9857         if((regs[i].was32>>us2[i+1])&1) r32|=1LL<<us2[i+1];
9858       }
9859       if(dep1[i+1]&&!((unneeded_reg_upper[i]>>dep1[i+1])&1))
9860       {
9861         if((regs[i].was32>>dep1[i+1])&1) r32|=1LL<<dep1[i+1];
9862       }
9863       if(dep2[i+1]&&!((unneeded_reg_upper[i]>>dep2[i+1])&1))
9864       {
9865         if((regs[i].was32>>dep2[i+1])&1) r32|=1LL<<dep2[i+1];
9866       }
9867     }
9868     else if(itype[i]==SYSCALL)
9869     {
9870       // SYSCALL instruction (software interrupt)
9871       r32=0;
9872     }
9873     else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
9874     {
9875       // ERET instruction (return from interrupt)
9876       r32=0;
9877     }
9878     // Check 32 bits
9879     r32&=~(1LL<<rt1[i]);
9880     r32&=~(1LL<<rt2[i]);
9881     if(us1[i]>0)
9882     {
9883       if((regs[i].was32>>us1[i])&1) r32|=1LL<<us1[i];
9884     }
9885     if(us2[i]>0)
9886     {
9887       if((regs[i].was32>>us2[i])&1) r32|=1LL<<us2[i];
9888     }
9889     if(dep1[i]&&!((unneeded_reg_upper[i]>>dep1[i])&1))
9890     {
9891       if((regs[i].was32>>dep1[i])&1) r32|=1LL<<dep1[i];
9892     }
9893     if(dep2[i]&&!((unneeded_reg_upper[i]>>dep2[i])&1))
9894     {
9895       if((regs[i].was32>>dep2[i])&1) r32|=1LL<<dep2[i];
9896     }
9897     requires_32bit[i]=r32;
9898
9899     // Dirty registers which are 32-bit, require 32-bit input
9900     // as they will be written as 32-bit values
9901     for(hr=0;hr<HOST_REGS;hr++)
9902     {
9903       if(regs[i].regmap_entry[hr]>0&&regs[i].regmap_entry[hr]<64) {
9904         if((regs[i].was32>>regs[i].regmap_entry[hr])&(regs[i].wasdirty>>hr)&1) {
9905           if(!((unneeded_reg_upper[i]>>regs[i].regmap_entry[hr])&1))
9906           requires_32bit[i]|=1LL<<regs[i].regmap_entry[hr];
9907         }
9908       }
9909     }
9910     //requires_32bit[i]=is32[i]&~unneeded_reg_upper[i]; // DEBUG
9911   }
9912
9913   if(itype[slen-1]==SPAN) {
9914     bt[slen-1]=1; // Mark as a branch target so instruction can restart after exception
9915   }
9916
9917   /* Debug/disassembly */
9918   if((void*)assem_debug==(void*)printf)
9919   for(i=0;i<slen;i++)
9920   {
9921     printf("U:");
9922     int r;
9923     for(r=1;r<=CCREG;r++) {
9924       if((unneeded_reg[i]>>r)&1) {
9925         if(r==HIREG) printf(" HI");
9926         else if(r==LOREG) printf(" LO");
9927         else printf(" r%d",r);
9928       }
9929     }
9930     printf(" UU:");
9931     for(r=1;r<=CCREG;r++) {
9932       if(((unneeded_reg_upper[i]&~unneeded_reg[i])>>r)&1) {
9933         if(r==HIREG) printf(" HI");
9934         else if(r==LOREG) printf(" LO");
9935         else printf(" r%d",r);
9936       }
9937     }
9938     printf(" 32:");
9939     for(r=0;r<=CCREG;r++) {
9940       //if(((is32[i]>>r)&(~unneeded_reg[i]>>r))&1) {
9941       if((regs[i].was32>>r)&1) {
9942         if(r==CCREG) printf(" CC");
9943         else if(r==HIREG) printf(" HI");
9944         else if(r==LOREG) printf(" LO");
9945         else printf(" r%d",r);
9946       }
9947     }
9948     printf("\n");
9949     #if defined(__i386__) || defined(__x86_64__)
9950     printf("pre: eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",regmap_pre[i][0],regmap_pre[i][1],regmap_pre[i][2],regmap_pre[i][3],regmap_pre[i][5],regmap_pre[i][6],regmap_pre[i][7]);
9951     #endif
9952     #ifdef __arm__
9953     printf("pre: r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d\n",regmap_pre[i][0],regmap_pre[i][1],regmap_pre[i][2],regmap_pre[i][3],regmap_pre[i][4],regmap_pre[i][5],regmap_pre[i][6],regmap_pre[i][7],regmap_pre[i][8],regmap_pre[i][9],regmap_pre[i][10],regmap_pre[i][12]);
9954     #endif
9955     printf("needs: ");
9956     if(needed_reg[i]&1) printf("eax ");
9957     if((needed_reg[i]>>1)&1) printf("ecx ");
9958     if((needed_reg[i]>>2)&1) printf("edx ");
9959     if((needed_reg[i]>>3)&1) printf("ebx ");
9960     if((needed_reg[i]>>5)&1) printf("ebp ");
9961     if((needed_reg[i]>>6)&1) printf("esi ");
9962     if((needed_reg[i]>>7)&1) printf("edi ");
9963     printf("r:");
9964     for(r=0;r<=CCREG;r++) {
9965       //if(((requires_32bit[i]>>r)&(~unneeded_reg[i]>>r))&1) {
9966       if((requires_32bit[i]>>r)&1) {
9967         if(r==CCREG) printf(" CC");
9968         else if(r==HIREG) printf(" HI");
9969         else if(r==LOREG) printf(" LO");
9970         else printf(" r%d",r);
9971       }
9972     }
9973     printf("\n");
9974     /*printf("pr:");
9975     for(r=0;r<=CCREG;r++) {
9976       //if(((requires_32bit[i]>>r)&(~unneeded_reg[i]>>r))&1) {
9977       if((pr32[i]>>r)&1) {
9978         if(r==CCREG) printf(" CC");
9979         else if(r==HIREG) printf(" HI");
9980         else if(r==LOREG) printf(" LO");
9981         else printf(" r%d",r);
9982       }
9983     }
9984     if(pr32[i]!=requires_32bit[i]) printf(" OOPS");
9985     printf("\n");*/
9986     #if defined(__i386__) || defined(__x86_64__)
9987     printf("entry: eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",regs[i].regmap_entry[0],regs[i].regmap_entry[1],regs[i].regmap_entry[2],regs[i].regmap_entry[3],regs[i].regmap_entry[5],regs[i].regmap_entry[6],regs[i].regmap_entry[7]);
9988     printf("dirty: ");
9989     if(regs[i].wasdirty&1) printf("eax ");
9990     if((regs[i].wasdirty>>1)&1) printf("ecx ");
9991     if((regs[i].wasdirty>>2)&1) printf("edx ");
9992     if((regs[i].wasdirty>>3)&1) printf("ebx ");
9993     if((regs[i].wasdirty>>5)&1) printf("ebp ");
9994     if((regs[i].wasdirty>>6)&1) printf("esi ");
9995     if((regs[i].wasdirty>>7)&1) printf("edi ");
9996     #endif
9997     #ifdef __arm__
9998     printf("entry: r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d\n",regs[i].regmap_entry[0],regs[i].regmap_entry[1],regs[i].regmap_entry[2],regs[i].regmap_entry[3],regs[i].regmap_entry[4],regs[i].regmap_entry[5],regs[i].regmap_entry[6],regs[i].regmap_entry[7],regs[i].regmap_entry[8],regs[i].regmap_entry[9],regs[i].regmap_entry[10],regs[i].regmap_entry[12]);
9999     printf("dirty: ");
10000     if(regs[i].wasdirty&1) printf("r0 ");
10001     if((regs[i].wasdirty>>1)&1) printf("r1 ");
10002     if((regs[i].wasdirty>>2)&1) printf("r2 ");
10003     if((regs[i].wasdirty>>3)&1) printf("r3 ");
10004     if((regs[i].wasdirty>>4)&1) printf("r4 ");
10005     if((regs[i].wasdirty>>5)&1) printf("r5 ");
10006     if((regs[i].wasdirty>>6)&1) printf("r6 ");
10007     if((regs[i].wasdirty>>7)&1) printf("r7 ");
10008     if((regs[i].wasdirty>>8)&1) printf("r8 ");
10009     if((regs[i].wasdirty>>9)&1) printf("r9 ");
10010     if((regs[i].wasdirty>>10)&1) printf("r10 ");
10011     if((regs[i].wasdirty>>12)&1) printf("r12 ");
10012     #endif
10013     printf("\n");
10014     disassemble_inst(i);
10015     //printf ("ccadj[%d] = %d\n",i,ccadj[i]);
10016     #if defined(__i386__) || defined(__x86_64__)
10017     printf("eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d dirty: ",regs[i].regmap[0],regs[i].regmap[1],regs[i].regmap[2],regs[i].regmap[3],regs[i].regmap[5],regs[i].regmap[6],regs[i].regmap[7]);
10018     if(regs[i].dirty&1) printf("eax ");
10019     if((regs[i].dirty>>1)&1) printf("ecx ");
10020     if((regs[i].dirty>>2)&1) printf("edx ");
10021     if((regs[i].dirty>>3)&1) printf("ebx ");
10022     if((regs[i].dirty>>5)&1) printf("ebp ");
10023     if((regs[i].dirty>>6)&1) printf("esi ");
10024     if((regs[i].dirty>>7)&1) printf("edi ");
10025     #endif
10026     #ifdef __arm__
10027     printf("r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d dirty: ",regs[i].regmap[0],regs[i].regmap[1],regs[i].regmap[2],regs[i].regmap[3],regs[i].regmap[4],regs[i].regmap[5],regs[i].regmap[6],regs[i].regmap[7],regs[i].regmap[8],regs[i].regmap[9],regs[i].regmap[10],regs[i].regmap[12]);
10028     if(regs[i].dirty&1) printf("r0 ");
10029     if((regs[i].dirty>>1)&1) printf("r1 ");
10030     if((regs[i].dirty>>2)&1) printf("r2 ");
10031     if((regs[i].dirty>>3)&1) printf("r3 ");
10032     if((regs[i].dirty>>4)&1) printf("r4 ");
10033     if((regs[i].dirty>>5)&1) printf("r5 ");
10034     if((regs[i].dirty>>6)&1) printf("r6 ");
10035     if((regs[i].dirty>>7)&1) printf("r7 ");
10036     if((regs[i].dirty>>8)&1) printf("r8 ");
10037     if((regs[i].dirty>>9)&1) printf("r9 ");
10038     if((regs[i].dirty>>10)&1) printf("r10 ");
10039     if((regs[i].dirty>>12)&1) printf("r12 ");
10040     #endif
10041     printf("\n");
10042     if(regs[i].isconst) {
10043       printf("constants: ");
10044       #if defined(__i386__) || defined(__x86_64__)
10045       if(regs[i].isconst&1) printf("eax=%x ",(int)constmap[i][0]);
10046       if((regs[i].isconst>>1)&1) printf("ecx=%x ",(int)constmap[i][1]);
10047       if((regs[i].isconst>>2)&1) printf("edx=%x ",(int)constmap[i][2]);
10048       if((regs[i].isconst>>3)&1) printf("ebx=%x ",(int)constmap[i][3]);
10049       if((regs[i].isconst>>5)&1) printf("ebp=%x ",(int)constmap[i][5]);
10050       if((regs[i].isconst>>6)&1) printf("esi=%x ",(int)constmap[i][6]);
10051       if((regs[i].isconst>>7)&1) printf("edi=%x ",(int)constmap[i][7]);
10052       #endif
10053       #ifdef __arm__
10054       if(regs[i].isconst&1) printf("r0=%x ",(int)constmap[i][0]);
10055       if((regs[i].isconst>>1)&1) printf("r1=%x ",(int)constmap[i][1]);
10056       if((regs[i].isconst>>2)&1) printf("r2=%x ",(int)constmap[i][2]);
10057       if((regs[i].isconst>>3)&1) printf("r3=%x ",(int)constmap[i][3]);
10058       if((regs[i].isconst>>4)&1) printf("r4=%x ",(int)constmap[i][4]);
10059       if((regs[i].isconst>>5)&1) printf("r5=%x ",(int)constmap[i][5]);
10060       if((regs[i].isconst>>6)&1) printf("r6=%x ",(int)constmap[i][6]);
10061       if((regs[i].isconst>>7)&1) printf("r7=%x ",(int)constmap[i][7]);
10062       if((regs[i].isconst>>8)&1) printf("r8=%x ",(int)constmap[i][8]);
10063       if((regs[i].isconst>>9)&1) printf("r9=%x ",(int)constmap[i][9]);
10064       if((regs[i].isconst>>10)&1) printf("r10=%x ",(int)constmap[i][10]);
10065       if((regs[i].isconst>>12)&1) printf("r12=%x ",(int)constmap[i][12]);
10066       #endif
10067       printf("\n");
10068     }
10069     printf(" 32:");
10070     for(r=0;r<=CCREG;r++) {
10071       if((regs[i].is32>>r)&1) {
10072         if(r==CCREG) printf(" CC");
10073         else if(r==HIREG) printf(" HI");
10074         else if(r==LOREG) printf(" LO");
10075         else printf(" r%d",r);
10076       }
10077     }
10078     printf("\n");
10079     /*printf(" p32:");
10080     for(r=0;r<=CCREG;r++) {
10081       if((p32[i]>>r)&1) {
10082         if(r==CCREG) printf(" CC");
10083         else if(r==HIREG) printf(" HI");
10084         else if(r==LOREG) printf(" LO");
10085         else printf(" r%d",r);
10086       }
10087     }
10088     if(p32[i]!=regs[i].is32) printf(" NO MATCH\n");
10089     else printf("\n");*/
10090     if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP) {
10091       #if defined(__i386__) || defined(__x86_64__)
10092       printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d dirty: ",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
10093       if(branch_regs[i].dirty&1) printf("eax ");
10094       if((branch_regs[i].dirty>>1)&1) printf("ecx ");
10095       if((branch_regs[i].dirty>>2)&1) printf("edx ");
10096       if((branch_regs[i].dirty>>3)&1) printf("ebx ");
10097       if((branch_regs[i].dirty>>5)&1) printf("ebp ");
10098       if((branch_regs[i].dirty>>6)&1) printf("esi ");
10099       if((branch_regs[i].dirty>>7)&1) printf("edi ");
10100       #endif
10101       #ifdef __arm__
10102       printf("branch(%d): r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d dirty: ",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[4],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7],branch_regs[i].regmap[8],branch_regs[i].regmap[9],branch_regs[i].regmap[10],branch_regs[i].regmap[12]);
10103       if(branch_regs[i].dirty&1) printf("r0 ");
10104       if((branch_regs[i].dirty>>1)&1) printf("r1 ");
10105       if((branch_regs[i].dirty>>2)&1) printf("r2 ");
10106       if((branch_regs[i].dirty>>3)&1) printf("r3 ");
10107       if((branch_regs[i].dirty>>4)&1) printf("r4 ");
10108       if((branch_regs[i].dirty>>5)&1) printf("r5 ");
10109       if((branch_regs[i].dirty>>6)&1) printf("r6 ");
10110       if((branch_regs[i].dirty>>7)&1) printf("r7 ");
10111       if((branch_regs[i].dirty>>8)&1) printf("r8 ");
10112       if((branch_regs[i].dirty>>9)&1) printf("r9 ");
10113       if((branch_regs[i].dirty>>10)&1) printf("r10 ");
10114       if((branch_regs[i].dirty>>12)&1) printf("r12 ");
10115       #endif
10116       printf(" 32:");
10117       for(r=0;r<=CCREG;r++) {
10118         if((branch_regs[i].is32>>r)&1) {
10119           if(r==CCREG) printf(" CC");
10120           else if(r==HIREG) printf(" HI");
10121           else if(r==LOREG) printf(" LO");
10122           else printf(" r%d",r);
10123         }
10124       }
10125       printf("\n");
10126     }
10127   }
10128
10129   /* Pass 8 - Assembly */
10130   linkcount=0;stubcount=0;
10131   ds=0;is_delayslot=0;
10132   cop1_usable=0;
10133   uint64_t is32_pre=0;
10134   u_int dirty_pre=0;
10135   u_int beginning=(u_int)out;
10136   if((u_int)addr&1) {
10137     ds=1;
10138     pagespan_ds();
10139   }
10140   for(i=0;i<slen;i++)
10141   {
10142     //if(ds) printf("ds: ");
10143     if((void*)assem_debug==(void*)printf) disassemble_inst(i);
10144     if(ds) {
10145       ds=0; // Skip delay slot
10146       if(bt[i]) assem_debug("OOPS - branch into delay slot\n");
10147       instr_addr[i]=0;
10148     } else {
10149       #ifndef DESTRUCTIVE_WRITEBACK
10150       if(i<2||(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000))
10151       {
10152         wb_sx(regmap_pre[i],regs[i].regmap_entry,regs[i].wasdirty,is32_pre,regs[i].was32,
10153               unneeded_reg[i],unneeded_reg_upper[i]);
10154         wb_valid(regmap_pre[i],regs[i].regmap_entry,dirty_pre,regs[i].wasdirty,is32_pre,
10155               unneeded_reg[i],unneeded_reg_upper[i]);
10156       }
10157       is32_pre=regs[i].is32;
10158       dirty_pre=regs[i].dirty;
10159       #endif
10160       // write back
10161       if(i<2||(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000))
10162       {
10163         wb_invalidate(regmap_pre[i],regs[i].regmap_entry,regs[i].wasdirty,regs[i].was32,
10164                       unneeded_reg[i],unneeded_reg_upper[i]);
10165         loop_preload(regmap_pre[i],regs[i].regmap_entry);
10166       }
10167       // branch target entry point
10168       instr_addr[i]=(u_int)out;
10169       assem_debug("<->\n");
10170       // load regs
10171       if(regs[i].regmap_entry[HOST_CCREG]==CCREG&&regs[i].regmap[HOST_CCREG]!=CCREG)
10172         wb_register(CCREG,regs[i].regmap_entry,regs[i].wasdirty,regs[i].was32);
10173       load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs1[i],rs2[i]);
10174       address_generation(i,&regs[i],regs[i].regmap_entry);
10175       load_consts(regmap_pre[i],regs[i].regmap,regs[i].was32,i);
10176       if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
10177       {
10178         // Load the delay slot registers if necessary
10179         if(rs1[i+1]!=rs1[i]&&rs1[i+1]!=rs2[i])
10180           load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs1[i+1],rs1[i+1]);
10181         if(rs2[i+1]!=rs1[i+1]&&rs2[i+1]!=rs1[i]&&rs2[i+1]!=rs2[i])
10182           load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs2[i+1],rs2[i+1]);
10183         if(itype[i+1]==STORE||itype[i+1]==STORELR||(opcode[i+1]&0x3b)==0x39)
10184           load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,INVCP,INVCP);
10185       }
10186       else if(i+1<slen)
10187       {
10188         // Preload registers for following instruction
10189         if(rs1[i+1]!=rs1[i]&&rs1[i+1]!=rs2[i])
10190           if(rs1[i+1]!=rt1[i]&&rs1[i+1]!=rt2[i])
10191             load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs1[i+1],rs1[i+1]);
10192         if(rs2[i+1]!=rs1[i+1]&&rs2[i+1]!=rs1[i]&&rs2[i+1]!=rs2[i])
10193           if(rs2[i+1]!=rt1[i]&&rs2[i+1]!=rt2[i])
10194             load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs2[i+1],rs2[i+1]);
10195       }
10196       // TODO: if(is_ooo(i)) address_generation(i+1);
10197       if(itype[i]==CJUMP||itype[i]==FJUMP)
10198         load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,CCREG,CCREG);
10199       if(itype[i]==STORE||itype[i]==STORELR||(opcode[i]&0x3b)==0x39)
10200         load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,INVCP,INVCP);
10201       if(bt[i]) cop1_usable=0;
10202       // assemble
10203       switch(itype[i]) {
10204         case ALU:
10205           alu_assemble(i,&regs[i]);break;
10206         case IMM16:
10207           imm16_assemble(i,&regs[i]);break;
10208         case SHIFT:
10209           shift_assemble(i,&regs[i]);break;
10210         case SHIFTIMM:
10211           shiftimm_assemble(i,&regs[i]);break;
10212         case LOAD:
10213           load_assemble(i,&regs[i]);break;
10214         case LOADLR:
10215           loadlr_assemble(i,&regs[i]);break;
10216         case STORE:
10217           store_assemble(i,&regs[i]);break;
10218         case STORELR:
10219           storelr_assemble(i,&regs[i]);break;
10220         case COP0:
10221           cop0_assemble(i,&regs[i]);break;
10222         case COP1:
10223           cop1_assemble(i,&regs[i]);break;
10224         case C1LS:
10225           c1ls_assemble(i,&regs[i]);break;
10226         case FCONV:
10227           fconv_assemble(i,&regs[i]);break;
10228         case FLOAT:
10229           float_assemble(i,&regs[i]);break;
10230         case FCOMP:
10231           fcomp_assemble(i,&regs[i]);break;
10232         case MULTDIV:
10233           multdiv_assemble(i,&regs[i]);break;
10234         case MOV:
10235           mov_assemble(i,&regs[i]);break;
10236         case SYSCALL:
10237           syscall_assemble(i,&regs[i]);break;
10238         case UJUMP:
10239           ujump_assemble(i,&regs[i]);ds=1;break;
10240         case RJUMP:
10241           rjump_assemble(i,&regs[i]);ds=1;break;
10242         case CJUMP:
10243           cjump_assemble(i,&regs[i]);ds=1;break;
10244         case SJUMP:
10245           sjump_assemble(i,&regs[i]);ds=1;break;
10246         case FJUMP:
10247           fjump_assemble(i,&regs[i]);ds=1;break;
10248         case SPAN:
10249           pagespan_assemble(i,&regs[i]);break;
10250       }
10251       if(itype[i]==UJUMP||itype[i]==RJUMP||(source[i]>>16)==0x1000)
10252         literal_pool(1024);
10253       else
10254         literal_pool_jumpover(256);
10255     }
10256   }
10257   //assert(itype[i-2]==UJUMP||itype[i-2]==RJUMP||(source[i-2]>>16)==0x1000);
10258   // If the block did not end with an unconditional branch,
10259   // add a jump to the next instruction.
10260   if(i>1) {
10261     if(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000&&itype[i-1]!=SPAN) {
10262       assert(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP);
10263       assert(i==slen);
10264       if(itype[i-2]!=CJUMP&&itype[i-2]!=SJUMP&&itype[i-2]!=FJUMP) {
10265         store_regs_bt(regs[i-1].regmap,regs[i-1].is32,regs[i-1].dirty,start+i*4);
10266         if(regs[i-1].regmap[HOST_CCREG]!=CCREG)
10267           emit_loadreg(CCREG,HOST_CCREG);
10268         emit_addimm(HOST_CCREG,CLOCK_DIVIDER*(ccadj[i-1]+1),HOST_CCREG);
10269       }
10270       else if(!likely[i-2])
10271       {
10272         store_regs_bt(branch_regs[i-2].regmap,branch_regs[i-2].is32,branch_regs[i-2].dirty,start+i*4);
10273         assert(branch_regs[i-2].regmap[HOST_CCREG]==CCREG);
10274       }
10275       else
10276       {
10277         store_regs_bt(regs[i-2].regmap,regs[i-2].is32,regs[i-2].dirty,start+i*4);
10278         assert(regs[i-2].regmap[HOST_CCREG]==CCREG);
10279       }
10280       add_to_linker((int)out,start+i*4,0);
10281       emit_jmp(0);
10282     }
10283   }
10284   else
10285   {
10286     assert(i>0);
10287     assert(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP);
10288     store_regs_bt(regs[i-1].regmap,regs[i-1].is32,regs[i-1].dirty,start+i*4);
10289     if(regs[i-1].regmap[HOST_CCREG]!=CCREG)
10290       emit_loadreg(CCREG,HOST_CCREG);
10291     emit_addimm(HOST_CCREG,CLOCK_DIVIDER*(ccadj[i-1]+1),HOST_CCREG);
10292     add_to_linker((int)out,start+i*4,0);
10293     emit_jmp(0);
10294   }
10295
10296   // TODO: delay slot stubs?
10297   // Stubs
10298   for(i=0;i<stubcount;i++)
10299   {
10300     switch(stubs[i][0])
10301     {
10302       case LOADB_STUB:
10303       case LOADH_STUB:
10304       case LOADW_STUB:
10305       case LOADD_STUB:
10306       case LOADBU_STUB:
10307       case LOADHU_STUB:
10308         do_readstub(i);break;
10309       case STOREB_STUB:
10310       case STOREH_STUB:
10311       case STOREW_STUB:
10312       case STORED_STUB:
10313         do_writestub(i);break;
10314       case CC_STUB:
10315         do_ccstub(i);break;
10316       case INVCODE_STUB:
10317         do_invstub(i);break;
10318       case FP_STUB:
10319         do_cop1stub(i);break;
10320       case STORELR_STUB:
10321         do_unalignedwritestub(i);break;
10322     }
10323   }
10324
10325   /* Pass 9 - Linker */
10326   for(i=0;i<linkcount;i++)
10327   {
10328     assem_debug("%8x -> %8x\n",link_addr[i][0],link_addr[i][1]);
10329     literal_pool(64);
10330     if(!link_addr[i][2])
10331     {
10332       void *stub=out;
10333       void *addr=check_addr(link_addr[i][1]);
10334       emit_extjump(link_addr[i][0],link_addr[i][1]);
10335       if(addr) {
10336         set_jump_target(link_addr[i][0],(int)addr);
10337         add_link(link_addr[i][1],stub);
10338       }
10339       else set_jump_target(link_addr[i][0],(int)stub);
10340     }
10341     else
10342     {
10343       // Internal branch
10344       int target=(link_addr[i][1]-start)>>2;
10345       assert(target>=0&&target<slen);
10346       assert(instr_addr[target]);
10347       //#ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
10348       //set_jump_target_fillslot(link_addr[i][0],instr_addr[target],link_addr[i][2]>>1);
10349       //#else
10350       set_jump_target(link_addr[i][0],instr_addr[target]);
10351       //#endif
10352     }
10353   }
10354   // External Branch Targets (jump_in)
10355   if(copy+slen*4>(void *)shadow+sizeof(shadow)) copy=shadow;
10356   for(i=0;i<slen;i++)
10357   {
10358     if(bt[i]||i==0)
10359     {
10360       if(instr_addr[i]) // TODO - delay slots (=null)
10361       {
10362         u_int vaddr=start+i*4;
10363         u_int page=get_page(vaddr);
10364         u_int vpage=get_vpage(vaddr);
10365         literal_pool(256);
10366         //if(!(is32[i]&(~unneeded_reg_upper[i])&~(1LL<<CCREG)))
10367         if(!requires_32bit[i])
10368         {
10369           assem_debug("%8x (%d) <- %8x\n",instr_addr[i],i,start+i*4);
10370           assem_debug("jump_in: %x\n",start+i*4);
10371           ll_add(jump_dirty+vpage,vaddr,(void *)out);
10372           int entry_point=do_dirty_stub(i);
10373           ll_add(jump_in+page,vaddr,(void *)entry_point);
10374           // If there was an existing entry in the hash table,
10375           // replace it with the new address.
10376           // Don't add new entries.  We'll insert the
10377           // ones that actually get used in check_addr().
10378           int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
10379           if(ht_bin[0]==vaddr) {
10380             ht_bin[1]=entry_point;
10381           }
10382           if(ht_bin[2]==vaddr) {
10383             ht_bin[3]=entry_point;
10384           }
10385         }
10386         else
10387         {
10388           u_int r=requires_32bit[i]|!!(requires_32bit[i]>>32);
10389           assem_debug("%8x (%d) <- %8x\n",instr_addr[i],i,start+i*4);
10390           assem_debug("jump_in: %x (restricted - %x)\n",start+i*4,r);
10391           //int entry_point=(int)out;
10392           ////assem_debug("entry_point: %x\n",entry_point);
10393           //load_regs_entry(i);
10394           //if(entry_point==(int)out)
10395           //  entry_point=instr_addr[i];
10396           //else
10397           //  emit_jmp(instr_addr[i]);
10398           //ll_add_32(jump_in+page,vaddr,r,(void *)entry_point);
10399           ll_add_32(jump_dirty+vpage,vaddr,r,(void *)out);
10400           int entry_point=do_dirty_stub(i);
10401           ll_add_32(jump_in+page,vaddr,r,(void *)entry_point);
10402         }
10403       }
10404     }
10405   }
10406   // Write out the literal pool if necessary
10407   literal_pool(0);
10408   #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
10409   // Align code
10410   if(((u_int)out)&7) emit_addnop(13);
10411   #endif
10412   assert((u_int)out-beginning<MAX_OUTPUT_BLOCK_SIZE);
10413   //printf("shadow buffer: %x-%x\n",(int)copy,(int)copy+slen*4);
10414   memcpy(copy,source,slen*4);
10415   copy+=slen*4;
10416
10417   #ifdef __arm__
10418   __clear_cache((void *)beginning,out);
10419   #endif
10420
10421   // If we're within 256K of the end of the buffer,
10422   // start over from the beginning. (Is 256K enough?)
10423   if((int)out>BASE_ADDR+(1<<TARGET_SIZE_2)-MAX_OUTPUT_BLOCK_SIZE) out=(u_char *)BASE_ADDR;
10424
10425   // Trap writes to any of the pages we compiled
10426   for(i=start>>12;i<=(start+slen*4)>>12;i++) {
10427     invalid_code[i]=0;
10428     memory_map[i]|=0x40000000;
10429     if((signed int)start>=(signed int)0xC0000000) {
10430       assert(using_tlb);
10431       j=(((u_int)i<<12)+(memory_map[i]<<2)-(u_int)rdram+(u_int)0x80000000)>>12;
10432       invalid_code[j]=0;
10433       memory_map[j]|=0x40000000;
10434       //printf("write protect physical page: %x (virtual %x)\n",j<<12,start);
10435     }
10436   }
10437
10438   /* Pass 10 - Free memory by expiring oldest blocks */
10439
10440   int end=((((int)out-BASE_ADDR)>>(TARGET_SIZE_2-16))+16384)&65535;
10441   while(expirep!=end)
10442   {
10443     int shift=TARGET_SIZE_2-3; // Divide into 8 blocks
10444     int base=BASE_ADDR+((expirep>>13)<<shift); // Base address of this block
10445     inv_debug("EXP: Phase %d\n",expirep);
10446     switch((expirep>>11)&3)
10447     {
10448       case 0:
10449         // Clear jump_in and jump_dirty
10450         ll_remove_matching_addrs(jump_in+(expirep&2047),base,shift);
10451         ll_remove_matching_addrs(jump_dirty+(expirep&2047),base,shift);
10452         ll_remove_matching_addrs(jump_in+2048+(expirep&2047),base,shift);
10453         ll_remove_matching_addrs(jump_dirty+2048+(expirep&2047),base,shift);
10454         break;
10455       case 1:
10456         // Clear pointers
10457         ll_kill_pointers(jump_out[expirep&2047],base,shift);
10458         ll_kill_pointers(jump_out[(expirep&2047)+2048],base,shift);
10459         break;
10460       case 2:
10461         // Clear hash table
10462         for(i=0;i<32;i++) {
10463           int *ht_bin=hash_table[((expirep&2047)<<5)+i];
10464           if((ht_bin[3]>>shift)==(base>>shift) ||
10465              ((ht_bin[3]-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(base>>shift)) {
10466             inv_debug("EXP: Remove hash %x -> %x\n",ht_bin[2],ht_bin[3]);
10467             ht_bin[2]=ht_bin[3]=-1;
10468           }
10469           if((ht_bin[1]>>shift)==(base>>shift) ||
10470              ((ht_bin[1]-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(base>>shift)) {
10471             inv_debug("EXP: Remove hash %x -> %x\n",ht_bin[0],ht_bin[1]);
10472             ht_bin[0]=ht_bin[2];
10473             ht_bin[1]=ht_bin[3];
10474             ht_bin[2]=ht_bin[3]=-1;
10475           }
10476         }
10477         break;
10478       case 3:
10479         // Clear jump_out
10480         #ifdef __arm__
10481         if((expirep&2047)==0)
10482           __clear_cache((void *)BASE_ADDR,(void *)BASE_ADDR+(1<<TARGET_SIZE_2));
10483         #endif
10484         ll_remove_matching_addrs(jump_out+(expirep&2047),base,shift);
10485         ll_remove_matching_addrs(jump_out+2048+(expirep&2047),base,shift);
10486         break;
10487     }
10488     expirep=(expirep+1)&65535;
10489   }
10490   return 0;
10491 }