libpcsxcore/new_dynarec/new_dynarec.c

   1 /* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
   2  *   Mupen64plus - new_dynarec.c                                           *
   3  *   Copyright (C) 2009-2011 Ari64                                         *
   4  *                                                                         *
   5  *   This program is free software; you can redistribute it and/or modify  *
   6  *   it under the terms of the GNU General Public License as published by  *
   7  *   the Free Software Foundation; either version 2 of the License, or     *
   8  *   (at your option) any later version.                                   *
   9  *                                                                         *
  10  *   This program is distributed in the hope that it will be useful,       *
  11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  13  *   GNU General Public License for more details.                          *
  14  *                                                                         *
  15  *   You should have received a copy of the GNU General Public License     *
  16  *   along with this program; if not, write to the                         *
  17  *   Free Software Foundation, Inc.,                                       *
  18  *   51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.          *
  19  * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
  20
  21 #include <stdlib.h>
  22 #include <stdint.h> //include for uint64_t
  23 #include <assert.h>
  24 #include <sys/mman.h>
  25
  26 #include "emu_if.h" //emulator interface
  27
  28 //#define DISASM
  29 //#define assem_debug printf
  30 //#define inv_debug printf
  31 #define assem_debug(...)
  32 #define inv_debug(...)
  33
  34 #ifdef __i386__
  35 #include "assem_x86.h"
  36 #endif
  37 #ifdef __x86_64__
  38 #include "assem_x64.h"
  39 #endif
  40 #ifdef __arm__
  41 #include "assem_arm.h"
  42 #endif
  43
  44 #define MAXBLOCK 4096
  45 #define MAX_OUTPUT_BLOCK_SIZE 262144
  46
  47 struct regstat
  48 {
  49   signed char regmap_entry[HOST_REGS];
  50   signed char regmap[HOST_REGS];
  51   uint64_t was32;
  52   uint64_t is32;
  53   uint64_t wasdirty;
  54   uint64_t dirty;
  55   uint64_t u;
  56   uint64_t uu;
  57   u_int wasconst;
  58   u_int isconst;
  59   u_int loadedconst;             // host regs that have constants loaded
  60   u_int waswritten;              // MIPS regs that were used as store base before
  61   uint64_t constmap[HOST_REGS];
  62 };
  63
  64 struct ll_entry
  65 {
  66   u_int vaddr;
  67   u_int reg32;
  68   void *addr;
  69   struct ll_entry *next;
  70 };
  71
  72   u_int start;
  73   u_int *source;
  74   u_int pagelimit;
  75   char insn[MAXBLOCK][10];
  76   u_char itype[MAXBLOCK];
  77   u_char opcode[MAXBLOCK];
  78   u_char opcode2[MAXBLOCK];
  79   u_char bt[MAXBLOCK];
  80   u_char rs1[MAXBLOCK];
  81   u_char rs2[MAXBLOCK];
  82   u_char rt1[MAXBLOCK];
  83   u_char rt2[MAXBLOCK];
  84   u_char us1[MAXBLOCK];
  85   u_char us2[MAXBLOCK];
  86   u_char dep1[MAXBLOCK];
  87   u_char dep2[MAXBLOCK];
  88   u_char lt1[MAXBLOCK];
  89   static uint64_t gte_rs[MAXBLOCK]; // gte: 32 data and 32 ctl regs
  90   static uint64_t gte_rt[MAXBLOCK];
  91   static uint64_t gte_unneeded[MAXBLOCK];
  92   static u_int smrv[32]; // speculated MIPS register values
  93   static u_int smrv_strong; // mask or regs that are likely to have correct values
  94   static u_int smrv_weak; // same, but somewhat less likely
  95   static u_int smrv_strong_next; // same, but after current insn executes
  96   static u_int smrv_weak_next;
  97   int imm[MAXBLOCK];
  98   u_int ba[MAXBLOCK];
  99   char likely[MAXBLOCK];
 100   char is_ds[MAXBLOCK];
 101   char ooo[MAXBLOCK];
 102   uint64_t unneeded_reg[MAXBLOCK];
 103   uint64_t unneeded_reg_upper[MAXBLOCK];
 104   uint64_t branch_unneeded_reg[MAXBLOCK];
 105   uint64_t branch_unneeded_reg_upper[MAXBLOCK];
 106   uint64_t p32[MAXBLOCK];
 107   uint64_t pr32[MAXBLOCK];
 108   signed char regmap_pre[MAXBLOCK][HOST_REGS];
 109   signed char regmap[MAXBLOCK][HOST_REGS];
 110   signed char regmap_entry[MAXBLOCK][HOST_REGS];
 111   uint64_t constmap[MAXBLOCK][HOST_REGS];
 112   struct regstat regs[MAXBLOCK];
 113   struct regstat branch_regs[MAXBLOCK];
 114   signed char minimum_free_regs[MAXBLOCK];
 115   u_int needed_reg[MAXBLOCK];
 116   uint64_t requires_32bit[MAXBLOCK];
 117   u_int wont_dirty[MAXBLOCK];
 118   u_int will_dirty[MAXBLOCK];
 119   int ccadj[MAXBLOCK];
 120   int slen;
 121   u_int instr_addr[MAXBLOCK];
 122   u_int link_addr[MAXBLOCK][3];
 123   int linkcount;
 124   u_int stubs[MAXBLOCK*3][8];
 125   int stubcount;
 126   u_int literals[1024][2];
 127   int literalcount;
 128   int is_delayslot;
 129   int cop1_usable;
 130   u_char *out;
 131   struct ll_entry *jump_in[4096];
 132   struct ll_entry *jump_out[4096];
 133   struct ll_entry *jump_dirty[4096];
 134   u_int hash_table[65536][4]  __attribute__((aligned(16)));
 135   char shadow[1048576]  __attribute__((aligned(16)));
 136   void *copy;
 137   int expirep;
 138 #ifndef PCSX
 139   u_int using_tlb;
 140 #else
 141   static const u_int using_tlb=0;
 142 #endif
 143   int new_dynarec_did_compile;
 144   int new_dynarec_hacks;
 145   u_int stop_after_jal;
 146   extern u_char restore_candidate[512];
 147   extern int cycle_count;
 148
 149   /* registers that may be allocated */
 150   /* 1-31 gpr */
 151 #define HIREG 32 // hi
 152 #define LOREG 33 // lo
 153 #define FSREG 34 // FPU status (FCSR)
 154 #define CSREG 35 // Coprocessor status
 155 #define CCREG 36 // Cycle count
 156 #define INVCP 37 // Pointer to invalid_code
 157 #define MMREG 38 // Pointer to memory_map
 158 #define ROREG 39 // ram offset (if rdram!=0x80000000)
 159 #define TEMPREG 40
 160 #define FTEMP 40 // FPU temporary register
 161 #define PTEMP 41 // Prefetch temporary register
 162 #define TLREG 42 // TLB mapping offset
 163 #define RHASH 43 // Return address hash
 164 #define RHTBL 44 // Return address hash table address
 165 #define RTEMP 45 // JR/JALR address register
 166 #define MAXREG 45
 167 #define AGEN1 46 // Address generation temporary register
 168 #define AGEN2 47 // Address generation temporary register
 169 #define MGEN1 48 // Maptable address generation temporary register
 170 #define MGEN2 49 // Maptable address generation temporary register
 171 #define BTREG 50 // Branch target temporary register
 172
 173   /* instruction types */
 174 #define NOP 0     // No operation
 175 #define LOAD 1    // Load
 176 #define STORE 2   // Store
 177 #define LOADLR 3  // Unaligned load
 178 #define STORELR 4 // Unaligned store
 179 #define MOV 5     // Move
 180 #define ALU 6     // Arithmetic/logic
 181 #define MULTDIV 7 // Multiply/divide
 182 #define SHIFT 8   // Shift by register
 183 #define SHIFTIMM 9// Shift by immediate
 184 #define IMM16 10  // 16-bit immediate
 185 #define RJUMP 11  // Unconditional jump to register
 186 #define UJUMP 12  // Unconditional jump
 187 #define CJUMP 13  // Conditional branch (BEQ/BNE/BGTZ/BLEZ)
 188 #define SJUMP 14  // Conditional branch (regimm format)
 189 #define COP0 15   // Coprocessor 0
 190 #define COP1 16   // Coprocessor 1
 191 #define C1LS 17   // Coprocessor 1 load/store
 192 #define FJUMP 18  // Conditional branch (floating point)
 193 #define FLOAT 19  // Floating point unit
 194 #define FCONV 20  // Convert integer to float
 195 #define FCOMP 21  // Floating point compare (sets FSREG)
 196 #define SYSCALL 22// SYSCALL
 197 #define OTHER 23  // Other
 198 #define SPAN 24   // Branch/delay slot spans 2 pages
 199 #define NI 25     // Not implemented
 200 #define HLECALL 26// PCSX fake opcodes for HLE
 201 #define COP2 27   // Coprocessor 2 move
 202 #define C2LS 28   // Coprocessor 2 load/store
 203 #define C2OP 29   // Coprocessor 2 operation
 204 #define INTCALL 30// Call interpreter to handle rare corner cases
 205
 206   /* stubs */
 207 #define CC_STUB 1
 208 #define FP_STUB 2
 209 #define LOADB_STUB 3
 210 #define LOADH_STUB 4
 211 #define LOADW_STUB 5
 212 #define LOADD_STUB 6
 213 #define LOADBU_STUB 7
 214 #define LOADHU_STUB 8
 215 #define STOREB_STUB 9
 216 #define STOREH_STUB 10
 217 #define STOREW_STUB 11
 218 #define STORED_STUB 12
 219 #define STORELR_STUB 13
 220 #define INVCODE_STUB 14
 221
 222   /* branch codes */
 223 #define TAKEN 1
 224 #define NOTTAKEN 2
 225 #define NULLDS 3
 226
 227 // asm linkage
 228 int new_recompile_block(int addr);
 229 void *get_addr_ht(u_int vaddr);
 230 void invalidate_block(u_int block);
 231 void invalidate_addr(u_int addr);
 232 void remove_hash(int vaddr);
 233 void jump_vaddr();
 234 void dyna_linker();
 235 void dyna_linker_ds();
 236 void verify_code();
 237 void verify_code_vm();
 238 void verify_code_ds();
 239 void cc_interrupt();
 240 void fp_exception();
 241 void fp_exception_ds();
 242 void jump_syscall();
 243 void jump_syscall_hle();
 244 void jump_eret();
 245 void jump_hlecall();
 246 void jump_intcall();
 247 void new_dyna_leave();
 248
 249 // TLB
 250 void TLBWI_new();
 251 void TLBWR_new();
 252 void read_nomem_new();
 253 void read_nomemb_new();
 254 void read_nomemh_new();
 255 void read_nomemd_new();
 256 void write_nomem_new();
 257 void write_nomemb_new();
 258 void write_nomemh_new();
 259 void write_nomemd_new();
 260 void write_rdram_new();
 261 void write_rdramb_new();
 262 void write_rdramh_new();
 263 void write_rdramd_new();
 264 extern u_int memory_map[1048576];
 265
 266 // Needed by assembler
 267 void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32);
 268 void wb_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty);
 269 void wb_needed_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr);
 270 void load_all_regs(signed char i_regmap[]);
 271 void load_needed_regs(signed char i_regmap[],signed char next_regmap[]);
 272 void load_regs_entry(int t);
 273 void load_all_consts(signed char regmap[],int is32,u_int dirty,int i);
 274
 275 int tracedebug=0;
 276
 277 //#define DEBUG_CYCLE_COUNT 1
 278
 279 int cycle_multiplier; // 100 for 1.0
 280
 281 static int CLOCK_ADJUST(int x)
 282 {
 283   int s=(x>>31)|1;
 284   return (x * cycle_multiplier + s * 50) / 100;
 285 }
 286
 287 static void tlb_hacks()
 288 {
 289 #ifndef DISABLE_TLB
 290   // Goldeneye hack
 291   if (strncmp((char *) ROM_HEADER->nom, "GOLDENEYE",9) == 0)
 292   {
 293     u_int addr;
 294     int n;
 295     switch (ROM_HEADER->Country_code&0xFF)
 296     {
 297       case 0x45: // U
 298         addr=0x34b30;
 299         break;
 300       case 0x4A: // J
 301         addr=0x34b70;
 302         break;
 303       case 0x50: // E
 304         addr=0x329f0;
 305         break;
 306       default:
 307         // Unknown country code
 308         addr=0;
 309         break;
 310     }
 311     u_int rom_addr=(u_int)rom;
 312     #ifdef ROM_COPY
 313     // Since memory_map is 32-bit, on 64-bit systems the rom needs to be
 314     // in the lower 4G of memory to use this hack.  Copy it if necessary.
 315     if((void *)rom>(void *)0xffffffff) {
 316       munmap(ROM_COPY, 67108864);
 317       if(mmap(ROM_COPY, 12582912,
 318               PROT_READ | PROT_WRITE,
 319               MAP_FIXED | MAP_PRIVATE | MAP_ANONYMOUS,
 320               -1, 0) <= 0) {printf("mmap() failed\n");}
 321       memcpy(ROM_COPY,rom,12582912);
 322       rom_addr=(u_int)ROM_COPY;
 323     }
 324     #endif
 325     if(addr) {
 326       for(n=0x7F000;n<0x80000;n++) {
 327         memory_map[n]=(((u_int)(rom_addr+addr-0x7F000000))>>2)|0x40000000;
 328       }
 329     }
 330   }
 331 #endif
 332 }
 333
 334 static u_int get_page(u_int vaddr)
 335 {
 336 #ifndef PCSX
 337   u_int page=(vaddr^0x80000000)>>12;
 338 #else
 339   u_int page=vaddr&~0xe0000000;
 340   if (page < 0x1000000)
 341     page &= ~0x0e00000; // RAM mirrors
 342   page>>=12;
 343 #endif
 344 #ifndef DISABLE_TLB
 345   if(page>262143&&tlb_LUT_r[vaddr>>12]) page=(tlb_LUT_r[vaddr>>12]^0x80000000)>>12;
 346 #endif
 347   if(page>2048) page=2048+(page&2047);
 348   return page;
 349 }
 350
 351 #ifndef PCSX
 352 static u_int get_vpage(u_int vaddr)
 353 {
 354   u_int vpage=(vaddr^0x80000000)>>12;
 355 #ifndef DISABLE_TLB
 356   if(vpage>262143&&tlb_LUT_r[vaddr>>12]) vpage&=2047; // jump_dirty uses a hash of the virtual address instead
 357 #endif
 358   if(vpage>2048) vpage=2048+(vpage&2047);
 359   return vpage;
 360 }
 361 #else
 362 // no virtual mem in PCSX
 363 static u_int get_vpage(u_int vaddr)
 364 {
 365   return get_page(vaddr);
 366 }
 367 #endif
 368
 369 // Get address from virtual address
 370 // This is called from the recompiled JR/JALR instructions
 371 void *get_addr(u_int vaddr)
 372 {
 373   u_int page=get_page(vaddr);
 374   u_int vpage=get_vpage(vaddr);
 375   struct ll_entry *head;
 376   //printf("TRACE: count=%d next=%d (get_addr %x,page %d)\n",Count,next_interupt,vaddr,page);
 377   head=jump_in[page];
 378   while(head!=NULL) {
 379     if(head->vaddr==vaddr&&head->reg32==0) {
 380   //printf("TRACE: count=%d next=%d (get_addr match %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
 381       int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
 382       ht_bin[3]=ht_bin[1];
 383       ht_bin[2]=ht_bin[0];
 384       ht_bin[1]=(int)head->addr;
 385       ht_bin[0]=vaddr;
 386       return head->addr;
 387     }
 388     head=head->next;
 389   }
 390   head=jump_dirty[vpage];
 391   while(head!=NULL) {
 392     if(head->vaddr==vaddr&&head->reg32==0) {
 393       //printf("TRACE: count=%d next=%d (get_addr match dirty %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
 394       // Don't restore blocks which are about to expire from the cache
 395       if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
 396       if(verify_dirty(head->addr)) {
 397         //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]);
 398         invalid_code[vaddr>>12]=0;
 399         inv_code_start=inv_code_end=~0;
 400 #ifndef DISABLE_TLB
 401         memory_map[vaddr>>12]|=0x40000000;
 402 #endif
 403         if(vpage<2048) {
 404 #ifndef DISABLE_TLB
 405           if(tlb_LUT_r[vaddr>>12]) {
 406             invalid_code[tlb_LUT_r[vaddr>>12]>>12]=0;
 407             memory_map[tlb_LUT_r[vaddr>>12]>>12]|=0x40000000;
 408           }
 409 #endif
 410           restore_candidate[vpage>>3]|=1<<(vpage&7);
 411         }
 412         else restore_candidate[page>>3]|=1<<(page&7);
 413         int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
 414         if(ht_bin[0]==vaddr) {
 415           ht_bin[1]=(int)head->addr; // Replace existing entry
 416         }
 417         else
 418         {
 419           ht_bin[3]=ht_bin[1];
 420           ht_bin[2]=ht_bin[0];
 421           ht_bin[1]=(int)head->addr;
 422           ht_bin[0]=vaddr;
 423         }
 424         return head->addr;
 425       }
 426     }
 427     head=head->next;
 428   }
 429   //printf("TRACE: count=%d next=%d (get_addr no-match %x)\n",Count,next_interupt,vaddr);
 430   int r=new_recompile_block(vaddr);
 431   if(r==0) return get_addr(vaddr);
 432   // Execute in unmapped page, generate pagefault execption
 433   Status|=2;
 434   Cause=(vaddr<<31)|0x8;
 435   EPC=(vaddr&1)?vaddr-5:vaddr;
 436   BadVAddr=(vaddr&~1);
 437   Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0);
 438   EntryHi=BadVAddr&0xFFFFE000;
 439   return get_addr_ht(0x80000000);
 440 }
 441 // Look up address in hash table first
 442 void *get_addr_ht(u_int vaddr)
 443 {
 444   //printf("TRACE: count=%d next=%d (get_addr_ht %x)\n",Count,next_interupt,vaddr);
 445   int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
 446   if(ht_bin[0]==vaddr) return (void *)ht_bin[1];
 447   if(ht_bin[2]==vaddr) return (void *)ht_bin[3];
 448   return get_addr(vaddr);
 449 }
 450
 451 void *get_addr_32(u_int vaddr,u_int flags)
 452 {
 453 #ifdef FORCE32
 454   return get_addr(vaddr);
 455 #else
 456   //printf("TRACE: count=%d next=%d (get_addr_32 %x,flags %x)\n",Count,next_interupt,vaddr,flags);
 457   int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
 458   if(ht_bin[0]==vaddr) return (void *)ht_bin[1];
 459   if(ht_bin[2]==vaddr) return (void *)ht_bin[3];
 460   u_int page=get_page(vaddr);
 461   u_int vpage=get_vpage(vaddr);
 462   struct ll_entry *head;
 463   head=jump_in[page];
 464   while(head!=NULL) {
 465     if(head->vaddr==vaddr&&(head->reg32&flags)==0) {
 466       //printf("TRACE: count=%d next=%d (get_addr_32 match %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
 467       if(head->reg32==0) {
 468         int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
 469         if(ht_bin[0]==-1) {
 470           ht_bin[1]=(int)head->addr;
 471           ht_bin[0]=vaddr;
 472         }else if(ht_bin[2]==-1) {
 473           ht_bin[3]=(int)head->addr;
 474           ht_bin[2]=vaddr;
 475         }
 476         //ht_bin[3]=ht_bin[1];
 477         //ht_bin[2]=ht_bin[0];
 478         //ht_bin[1]=(int)head->addr;
 479         //ht_bin[0]=vaddr;
 480       }
 481       return head->addr;
 482     }
 483     head=head->next;
 484   }
 485   head=jump_dirty[vpage];
 486   while(head!=NULL) {
 487     if(head->vaddr==vaddr&&(head->reg32&flags)==0) {
 488       //printf("TRACE: count=%d next=%d (get_addr_32 match dirty %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
 489       // Don't restore blocks which are about to expire from the cache
 490       if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
 491       if(verify_dirty(head->addr)) {
 492         //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]);
 493         invalid_code[vaddr>>12]=0;
 494         inv_code_start=inv_code_end=~0;
 495         memory_map[vaddr>>12]|=0x40000000;
 496         if(vpage<2048) {
 497 #ifndef DISABLE_TLB
 498           if(tlb_LUT_r[vaddr>>12]) {
 499             invalid_code[tlb_LUT_r[vaddr>>12]>>12]=0;
 500             memory_map[tlb_LUT_r[vaddr>>12]>>12]|=0x40000000;
 501           }
 502 #endif
 503           restore_candidate[vpage>>3]|=1<<(vpage&7);
 504         }
 505         else restore_candidate[page>>3]|=1<<(page&7);
 506         if(head->reg32==0) {
 507           int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
 508           if(ht_bin[0]==-1) {
 509             ht_bin[1]=(int)head->addr;
 510             ht_bin[0]=vaddr;
 511           }else if(ht_bin[2]==-1) {
 512             ht_bin[3]=(int)head->addr;
 513             ht_bin[2]=vaddr;
 514           }
 515           //ht_bin[3]=ht_bin[1];
 516           //ht_bin[2]=ht_bin[0];
 517           //ht_bin[1]=(int)head->addr;
 518           //ht_bin[0]=vaddr;
 519         }
 520         return head->addr;
 521       }
 522     }
 523     head=head->next;
 524   }
 525   //printf("TRACE: count=%d next=%d (get_addr_32 no-match %x,flags %x)\n",Count,next_interupt,vaddr,flags);
 526   int r=new_recompile_block(vaddr);
 527   if(r==0) return get_addr(vaddr);
 528   // Execute in unmapped page, generate pagefault execption
 529   Status|=2;
 530   Cause=(vaddr<<31)|0x8;
 531   EPC=(vaddr&1)?vaddr-5:vaddr;
 532   BadVAddr=(vaddr&~1);
 533   Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0);
 534   EntryHi=BadVAddr&0xFFFFE000;
 535   return get_addr_ht(0x80000000);
 536 #endif
 537 }
 538
 539 void clear_all_regs(signed char regmap[])
 540 {
 541   int hr;
 542   for (hr=0;hr<HOST_REGS;hr++) regmap[hr]=-1;
 543 }
 544
 545 signed char get_reg(signed char regmap[],int r)
 546 {
 547   int hr;
 548   for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&&regmap[hr]==r) return hr;
 549   return -1;
 550 }
 551
 552 // Find a register that is available for two consecutive cycles
 553 signed char get_reg2(signed char regmap1[],signed char regmap2[],int r)
 554 {
 555   int hr;
 556   for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&&regmap1[hr]==r&&regmap2[hr]==r) return hr;
 557   return -1;
 558 }
 559
 560 int count_free_regs(signed char regmap[])
 561 {
 562   int count=0;
 563   int hr;
 564   for(hr=0;hr<HOST_REGS;hr++)
 565   {
 566     if(hr!=EXCLUDE_REG) {
 567       if(regmap[hr]<0) count++;
 568     }
 569   }
 570   return count;
 571 }
 572
 573 void dirty_reg(struct regstat *cur,signed char reg)
 574 {
 575   int hr;
 576   if(!reg) return;
 577   for (hr=0;hr<HOST_REGS;hr++) {
 578     if((cur->regmap[hr]&63)==reg) {
 579       cur->dirty|=1<<hr;
 580     }
 581   }
 582 }
 583
 584 // If we dirty the lower half of a 64 bit register which is now being
 585 // sign-extended, we need to dump the upper half.
 586 // Note: Do this only after completion of the instruction, because
 587 // some instructions may need to read the full 64-bit value even if
 588 // overwriting it (eg SLTI, DSRA32).
 589 static void flush_dirty_uppers(struct regstat *cur)
 590 {
 591   int hr,reg;
 592   for (hr=0;hr<HOST_REGS;hr++) {
 593     if((cur->dirty>>hr)&1) {
 594       reg=cur->regmap[hr];
 595       if(reg>=64)
 596         if((cur->is32>>(reg&63))&1) cur->regmap[hr]=-1;
 597     }
 598   }
 599 }
 600
 601 void set_const(struct regstat *cur,signed char reg,uint64_t value)
 602 {
 603   int hr;
 604   if(!reg) return;
 605   for (hr=0;hr<HOST_REGS;hr++) {
 606     if(cur->regmap[hr]==reg) {
 607       cur->isconst|=1<<hr;
 608       cur->constmap[hr]=value;
 609     }
 610     else if((cur->regmap[hr]^64)==reg) {
 611       cur->isconst|=1<<hr;
 612       cur->constmap[hr]=value>>32;
 613     }
 614   }
 615 }
 616
 617 void clear_const(struct regstat *cur,signed char reg)
 618 {
 619   int hr;
 620   if(!reg) return;
 621   for (hr=0;hr<HOST_REGS;hr++) {
 622     if((cur->regmap[hr]&63)==reg) {
 623       cur->isconst&=~(1<<hr);
 624     }
 625   }
 626 }
 627
 628 int is_const(struct regstat *cur,signed char reg)
 629 {
 630   int hr;
 631   if(reg<0) return 0;
 632   if(!reg) return 1;
 633   for (hr=0;hr<HOST_REGS;hr++) {
 634     if((cur->regmap[hr]&63)==reg) {
 635       return (cur->isconst>>hr)&1;
 636     }
 637   }
 638   return 0;
 639 }
 640 uint64_t get_const(struct regstat *cur,signed char reg)
 641 {
 642   int hr;
 643   if(!reg) return 0;
 644   for (hr=0;hr<HOST_REGS;hr++) {
 645     if(cur->regmap[hr]==reg) {
 646       return cur->constmap[hr];
 647     }
 648   }
 649   printf("Unknown constant in r%d\n",reg);
 650   exit(1);
 651 }
 652
 653 // Least soon needed registers
 654 // Look at the next ten instructions and see which registers
 655 // will be used.  Try not to reallocate these.
 656 void lsn(u_char hsn[], int i, int *preferred_reg)
 657 {
 658   int j;
 659   int b=-1;
 660   for(j=0;j<9;j++)
 661   {
 662     if(i+j>=slen) {
 663       j=slen-i-1;
 664       break;
 665     }
 666     if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
 667     {
 668       // Don't go past an unconditonal jump
 669       j++;
 670       break;
 671     }
 672   }
 673   for(;j>=0;j--)
 674   {
 675     if(rs1[i+j]) hsn[rs1[i+j]]=j;
 676     if(rs2[i+j]) hsn[rs2[i+j]]=j;
 677     if(rt1[i+j]) hsn[rt1[i+j]]=j;
 678     if(rt2[i+j]) hsn[rt2[i+j]]=j;
 679     if(itype[i+j]==STORE || itype[i+j]==STORELR) {
 680       // Stores can allocate zero
 681       hsn[rs1[i+j]]=j;
 682       hsn[rs2[i+j]]=j;
 683     }
 684     // On some architectures stores need invc_ptr
 685     #if defined(HOST_IMM8)
 686     if(itype[i+j]==STORE || itype[i+j]==STORELR || (opcode[i+j]&0x3b)==0x39 || (opcode[i+j]&0x3b)==0x3a) {
 687       hsn[INVCP]=j;
 688     }
 689     #endif
 690     if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP))
 691     {
 692       hsn[CCREG]=j;
 693       b=j;
 694     }
 695   }
 696   if(b>=0)
 697   {
 698     if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
 699     {
 700       // Follow first branch
 701       int t=(ba[i+b]-start)>>2;
 702       j=7-b;if(t+j>=slen) j=slen-t-1;
 703       for(;j>=0;j--)
 704       {
 705         if(rs1[t+j]) if(hsn[rs1[t+j]]>j+b+2) hsn[rs1[t+j]]=j+b+2;
 706         if(rs2[t+j]) if(hsn[rs2[t+j]]>j+b+2) hsn[rs2[t+j]]=j+b+2;
 707         //if(rt1[t+j]) if(hsn[rt1[t+j]]>j+b+2) hsn[rt1[t+j]]=j+b+2;
 708         //if(rt2[t+j]) if(hsn[rt2[t+j]]>j+b+2) hsn[rt2[t+j]]=j+b+2;
 709       }
 710     }
 711     // TODO: preferred register based on backward branch
 712   }
 713   // Delay slot should preferably not overwrite branch conditions or cycle count
 714   if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)) {
 715     if(rs1[i-1]) if(hsn[rs1[i-1]]>1) hsn[rs1[i-1]]=1;
 716     if(rs2[i-1]) if(hsn[rs2[i-1]]>1) hsn[rs2[i-1]]=1;
 717     hsn[CCREG]=1;
 718     // ...or hash tables
 719     hsn[RHASH]=1;
 720     hsn[RHTBL]=1;
 721   }
 722   // Coprocessor load/store needs FTEMP, even if not declared
 723   if(itype[i]==C1LS||itype[i]==C2LS) {
 724     hsn[FTEMP]=0;
 725   }
 726   // Load L/R also uses FTEMP as a temporary register
 727   if(itype[i]==LOADLR) {
 728     hsn[FTEMP]=0;
 729   }
 730   // Also SWL/SWR/SDL/SDR
 731   if(opcode[i]==0x2a||opcode[i]==0x2e||opcode[i]==0x2c||opcode[i]==0x2d) {
 732     hsn[FTEMP]=0;
 733   }
 734   // Don't remove the TLB registers either
 735   if(itype[i]==LOAD || itype[i]==LOADLR || itype[i]==STORE || itype[i]==STORELR || itype[i]==C1LS || itype[i]==C2LS) {
 736     hsn[TLREG]=0;
 737   }
 738   // Don't remove the miniht registers
 739   if(itype[i]==UJUMP||itype[i]==RJUMP)
 740   {
 741     hsn[RHASH]=0;
 742     hsn[RHTBL]=0;
 743   }
 744 }
 745
 746 // We only want to allocate registers if we're going to use them again soon
 747 int needed_again(int r, int i)
 748 {
 749   int j;
 750   int b=-1;
 751   int rn=10;
 752
 753   if(i>0&&(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000))
 754   {
 755     if(ba[i-1]<start || ba[i-1]>start+slen*4-4)
 756       return 0; // Don't need any registers if exiting the block
 757   }
 758   for(j=0;j<9;j++)
 759   {
 760     if(i+j>=slen) {
 761       j=slen-i-1;
 762       break;
 763     }
 764     if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
 765     {
 766       // Don't go past an unconditonal jump
 767       j++;
 768       break;
 769     }
 770     if(itype[i+j]==SYSCALL||itype[i+j]==HLECALL||itype[i+j]==INTCALL||((source[i+j]&0xfc00003f)==0x0d))
 771     {
 772       break;
 773     }
 774   }
 775   for(;j>=1;j--)
 776   {
 777     if(rs1[i+j]==r) rn=j;
 778     if(rs2[i+j]==r) rn=j;
 779     if((unneeded_reg[i+j]>>r)&1) rn=10;
 780     if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP))
 781     {
 782       b=j;
 783     }
 784   }
 785   /*
 786   if(b>=0)
 787   {
 788     if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
 789     {
 790       // Follow first branch
 791       int o=rn;
 792       int t=(ba[i+b]-start)>>2;
 793       j=7-b;if(t+j>=slen) j=slen-t-1;
 794       for(;j>=0;j--)
 795       {
 796         if(!((unneeded_reg[t+j]>>r)&1)) {
 797           if(rs1[t+j]==r) if(rn>j+b+2) rn=j+b+2;
 798           if(rs2[t+j]==r) if(rn>j+b+2) rn=j+b+2;
 799         }
 800         else rn=o;
 801       }
 802     }
 803   }*/
 804   if(rn<10) return 1;
 805   return 0;
 806 }
 807
 808 // Try to match register allocations at the end of a loop with those
 809 // at the beginning
 810 int loop_reg(int i, int r, int hr)
 811 {
 812   int j,k;
 813   for(j=0;j<9;j++)
 814   {
 815     if(i+j>=slen) {
 816       j=slen-i-1;
 817       break;
 818     }
 819     if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
 820     {
 821       // Don't go past an unconditonal jump
 822       j++;
 823       break;
 824     }
 825   }
 826   k=0;
 827   if(i>0){
 828     if(itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)
 829       k--;
 830   }
 831   for(;k<j;k++)
 832   {
 833     if(r<64&&((unneeded_reg[i+k]>>r)&1)) return hr;
 834     if(r>64&&((unneeded_reg_upper[i+k]>>r)&1)) return hr;
 835     if(i+k>=0&&(itype[i+k]==UJUMP||itype[i+k]==CJUMP||itype[i+k]==SJUMP||itype[i+k]==FJUMP))
 836     {
 837       if(ba[i+k]>=start && ba[i+k]<(start+i*4))
 838       {
 839         int t=(ba[i+k]-start)>>2;
 840         int reg=get_reg(regs[t].regmap_entry,r);
 841         if(reg>=0) return reg;
 842         //reg=get_reg(regs[t+1].regmap_entry,r);
 843         //if(reg>=0) return reg;
 844       }
 845     }
 846   }
 847   return hr;
 848 }
 849
 850
 851 // Allocate every register, preserving source/target regs
 852 void alloc_all(struct regstat *cur,int i)
 853 {
 854   int hr;
 855
 856   for(hr=0;hr<HOST_REGS;hr++) {
 857     if(hr!=EXCLUDE_REG) {
 858       if(((cur->regmap[hr]&63)!=rs1[i])&&((cur->regmap[hr]&63)!=rs2[i])&&
 859          ((cur->regmap[hr]&63)!=rt1[i])&&((cur->regmap[hr]&63)!=rt2[i]))
 860       {
 861         cur->regmap[hr]=-1;
 862         cur->dirty&=~(1<<hr);
 863       }
 864       // Don't need zeros
 865       if((cur->regmap[hr]&63)==0)
 866       {
 867         cur->regmap[hr]=-1;
 868         cur->dirty&=~(1<<hr);
 869       }
 870     }
 871   }
 872 }
 873
 874 #ifndef FORCE32
 875 void div64(int64_t dividend,int64_t divisor)
 876 {
 877   lo=dividend/divisor;
 878   hi=dividend%divisor;
 879   //printf("TRACE: ddiv %8x%8x %8x%8x\n" ,(int)reg[HIREG],(int)(reg[HIREG]>>32)
 880   //                                     ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
 881 }
 882 void divu64(uint64_t dividend,uint64_t divisor)
 883 {
 884   lo=dividend/divisor;
 885   hi=dividend%divisor;
 886   //printf("TRACE: ddivu %8x%8x %8x%8x\n",(int)reg[HIREG],(int)(reg[HIREG]>>32)
 887   //                                     ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
 888 }
 889
 890 void mult64(uint64_t m1,uint64_t m2)
 891 {
 892    unsigned long long int op1, op2, op3, op4;
 893    unsigned long long int result1, result2, result3, result4;
 894    unsigned long long int temp1, temp2, temp3, temp4;
 895    int sign = 0;
 896
 897    if (m1 < 0)
 898      {
 899     op2 = -m1;
 900     sign = 1 - sign;
 901      }
 902    else op2 = m1;
 903    if (m2 < 0)
 904      {
 905     op4 = -m2;
 906     sign = 1 - sign;
 907      }
 908    else op4 = m2;
 909
 910    op1 = op2 & 0xFFFFFFFF;
 911    op2 = (op2 >> 32) & 0xFFFFFFFF;
 912    op3 = op4 & 0xFFFFFFFF;
 913    op4 = (op4 >> 32) & 0xFFFFFFFF;
 914
 915    temp1 = op1 * op3;
 916    temp2 = (temp1 >> 32) + op1 * op4;
 917    temp3 = op2 * op3;
 918    temp4 = (temp3 >> 32) + op2 * op4;
 919
 920    result1 = temp1 & 0xFFFFFFFF;
 921    result2 = temp2 + (temp3 & 0xFFFFFFFF);
 922    result3 = (result2 >> 32) + temp4;
 923    result4 = (result3 >> 32);
 924
 925    lo = result1 | (result2 << 32);
 926    hi = (result3 & 0xFFFFFFFF) | (result4 << 32);
 927    if (sign)
 928      {
 929     hi = ~hi;
 930     if (!lo) hi++;
 931     else lo = ~lo + 1;
 932      }
 933 }
 934
 935 void multu64(uint64_t m1,uint64_t m2)
 936 {
 937    unsigned long long int op1, op2, op3, op4;
 938    unsigned long long int result1, result2, result3, result4;
 939    unsigned long long int temp1, temp2, temp3, temp4;
 940
 941    op1 = m1 & 0xFFFFFFFF;
 942    op2 = (m1 >> 32) & 0xFFFFFFFF;
 943    op3 = m2 & 0xFFFFFFFF;
 944    op4 = (m2 >> 32) & 0xFFFFFFFF;
 945
 946    temp1 = op1 * op3;
 947    temp2 = (temp1 >> 32) + op1 * op4;
 948    temp3 = op2 * op3;
 949    temp4 = (temp3 >> 32) + op2 * op4;
 950
 951    result1 = temp1 & 0xFFFFFFFF;
 952    result2 = temp2 + (temp3 & 0xFFFFFFFF);
 953    result3 = (result2 >> 32) + temp4;
 954    result4 = (result3 >> 32);
 955
 956    lo = result1 | (result2 << 32);
 957    hi = (result3 & 0xFFFFFFFF) | (result4 << 32);
 958
 959   //printf("TRACE: dmultu %8x%8x %8x%8x\n",(int)reg[HIREG],(int)(reg[HIREG]>>32)
 960   //                                      ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
 961 }
 962
 963 uint64_t ldl_merge(uint64_t original,uint64_t loaded,u_int bits)
 964 {
 965   if(bits) {
 966     original<<=64-bits;
 967     original>>=64-bits;
 968     loaded<<=bits;
 969     original|=loaded;
 970   }
 971   else original=loaded;
 972   return original;
 973 }
 974 uint64_t ldr_merge(uint64_t original,uint64_t loaded,u_int bits)
 975 {
 976   if(bits^56) {
 977     original>>=64-(bits^56);
 978     original<<=64-(bits^56);
 979     loaded>>=bits^56;
 980     original|=loaded;
 981   }
 982   else original=loaded;
 983   return original;
 984 }
 985 #endif
 986
 987 #ifdef __i386__
 988 #include "assem_x86.c"
 989 #endif
 990 #ifdef __x86_64__
 991 #include "assem_x64.c"
 992 #endif
 993 #ifdef __arm__
 994 #include "assem_arm.c"
 995 #endif
 996
 997 // Add virtual address mapping to linked list
 998 void ll_add(struct ll_entry **head,int vaddr,void *addr)
 999 {
1000   struct ll_entry *new_entry;
1001   new_entry=malloc(sizeof(struct ll_entry));
1002   assert(new_entry!=NULL);
1003   new_entry->vaddr=vaddr;
1004   new_entry->reg32=0;
1005   new_entry->addr=addr;
1006   new_entry->next=*head;
1007   *head=new_entry;
1008 }
1009
1010 // Add virtual address mapping for 32-bit compiled block
1011 void ll_add_32(struct ll_entry **head,int vaddr,u_int reg32,void *addr)
1012 {
1013   ll_add(head,vaddr,addr);
1014 #ifndef FORCE32
1015   (*head)->reg32=reg32;
1016 #endif
1017 }
1018
1019 // Check if an address is already compiled
1020 // but don't return addresses which are about to expire from the cache
1021 void *check_addr(u_int vaddr)
1022 {
1023   u_int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
1024   if(ht_bin[0]==vaddr) {
1025     if(((ht_bin[1]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
1026       if(isclean(ht_bin[1])) return (void *)ht_bin[1];
1027   }
1028   if(ht_bin[2]==vaddr) {
1029     if(((ht_bin[3]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
1030       if(isclean(ht_bin[3])) return (void *)ht_bin[3];
1031   }
1032   u_int page=get_page(vaddr);
1033   struct ll_entry *head;
1034   head=jump_in[page];
1035   while(head!=NULL) {
1036     if(head->vaddr==vaddr&&head->reg32==0) {
1037       if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1038         // Update existing entry with current address
1039         if(ht_bin[0]==vaddr) {
1040           ht_bin[1]=(int)head->addr;
1041           return head->addr;
1042         }
1043         if(ht_bin[2]==vaddr) {
1044           ht_bin[3]=(int)head->addr;
1045           return head->addr;
1046         }
1047         // Insert into hash table with low priority.
1048         // Don't evict existing entries, as they are probably
1049         // addresses that are being accessed frequently.
1050         if(ht_bin[0]==-1) {
1051           ht_bin[1]=(int)head->addr;
1052           ht_bin[0]=vaddr;
1053         }else if(ht_bin[2]==-1) {
1054           ht_bin[3]=(int)head->addr;
1055           ht_bin[2]=vaddr;
1056         }
1057         return head->addr;
1058       }
1059     }
1060     head=head->next;
1061   }
1062   return 0;
1063 }
1064
1065 void remove_hash(int vaddr)
1066 {
1067   //printf("remove hash: %x\n",vaddr);
1068   int *ht_bin=hash_table[(((vaddr)>>16)^vaddr)&0xFFFF];
1069   if(ht_bin[2]==vaddr) {
1070     ht_bin[2]=ht_bin[3]=-1;
1071   }
1072   if(ht_bin[0]==vaddr) {
1073     ht_bin[0]=ht_bin[2];
1074     ht_bin[1]=ht_bin[3];
1075     ht_bin[2]=ht_bin[3]=-1;
1076   }
1077 }
1078
1079 void ll_remove_matching_addrs(struct ll_entry **head,int addr,int shift)
1080 {
1081   struct ll_entry *next;
1082   while(*head) {
1083     if(((u_int)((*head)->addr)>>shift)==(addr>>shift) ||
1084        ((u_int)((*head)->addr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift))
1085     {
1086       inv_debug("EXP: Remove pointer to %x (%x)\n",(int)(*head)->addr,(*head)->vaddr);
1087       remove_hash((*head)->vaddr);
1088       next=(*head)->next;
1089       free(*head);
1090       *head=next;
1091     }
1092     else
1093     {
1094       head=&((*head)->next);
1095     }
1096   }
1097 }
1098
1099 // Remove all entries from linked list
1100 void ll_clear(struct ll_entry **head)
1101 {
1102   struct ll_entry *cur;
1103   struct ll_entry *next;
1104   if(cur=*head) {
1105     *head=0;
1106     while(cur) {
1107       next=cur->next;
1108       free(cur);
1109       cur=next;
1110     }
1111   }
1112 }
1113
1114 // Dereference the pointers and remove if it matches
1115 void ll_kill_pointers(struct ll_entry *head,int addr,int shift)
1116 {
1117   while(head) {
1118     int ptr=get_pointer(head->addr);
1119     inv_debug("EXP: Lookup pointer to %x at %x (%x)\n",(int)ptr,(int)head->addr,head->vaddr);
1120     if(((ptr>>shift)==(addr>>shift)) ||
1121        (((ptr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift)))
1122     {
1123       inv_debug("EXP: Kill pointer at %x (%x)\n",(int)head->addr,head->vaddr);
1124       u_int host_addr=(u_int)kill_pointer(head->addr);
1125       #ifdef __arm__
1126         needs_clear_cache[(host_addr-(u_int)BASE_ADDR)>>17]|=1<<(((host_addr-(u_int)BASE_ADDR)>>12)&31);
1127       #endif
1128     }
1129     head=head->next;
1130   }
1131 }
1132
1133 // This is called when we write to a compiled block (see do_invstub)
1134 void invalidate_page(u_int page)
1135 {
1136   struct ll_entry *head;
1137   struct ll_entry *next;
1138   head=jump_in[page];
1139   jump_in[page]=0;
1140   while(head!=NULL) {
1141     inv_debug("INVALIDATE: %x\n",head->vaddr);
1142     remove_hash(head->vaddr);
1143     next=head->next;
1144     free(head);
1145     head=next;
1146   }
1147   head=jump_out[page];
1148   jump_out[page]=0;
1149   while(head!=NULL) {
1150     inv_debug("INVALIDATE: kill pointer to %x (%x)\n",head->vaddr,(int)head->addr);
1151     u_int host_addr=(u_int)kill_pointer(head->addr);
1152     #ifdef __arm__
1153       needs_clear_cache[(host_addr-(u_int)BASE_ADDR)>>17]|=1<<(((host_addr-(u_int)BASE_ADDR)>>12)&31);
1154     #endif
1155     next=head->next;
1156     free(head);
1157     head=next;
1158   }
1159 }
1160
1161 static void invalidate_block_range(u_int block, u_int first, u_int last)
1162 {
1163   u_int page=get_page(block<<12);
1164   //printf("first=%d last=%d\n",first,last);
1165   invalidate_page(page);
1166   assert(first+5>page); // NB: this assumes MAXBLOCK<=4096 (4 pages)
1167   assert(last<page+5);
1168   // Invalidate the adjacent pages if a block crosses a 4K boundary
1169   while(first<page) {
1170     invalidate_page(first);
1171     first++;
1172   }
1173   for(first=page+1;first<last;first++) {
1174     invalidate_page(first);
1175   }
1176   #ifdef __arm__
1177     do_clear_cache();
1178   #endif
1179
1180   // Don't trap writes
1181   invalid_code[block]=1;
1182 #ifndef DISABLE_TLB
1183   // If there is a valid TLB entry for this page, remove write protect
1184   if(tlb_LUT_w[block]) {
1185     assert(tlb_LUT_r[block]==tlb_LUT_w[block]);
1186     // CHECK: Is this right?
1187     memory_map[block]=((tlb_LUT_w[block]&0xFFFFF000)-(block<<12)+(unsigned int)rdram-0x80000000)>>2;
1188     u_int real_block=tlb_LUT_w[block]>>12;
1189     invalid_code[real_block]=1;
1190     if(real_block>=0x80000&&real_block<0x80800) memory_map[real_block]=((u_int)rdram-0x80000000)>>2;
1191   }
1192   else if(block>=0x80000&&block<0x80800) memory_map[block]=((u_int)rdram-0x80000000)>>2;
1193 #endif
1194
1195   #ifdef USE_MINI_HT
1196   memset(mini_ht,-1,sizeof(mini_ht));
1197   #endif
1198 }
1199
1200 void invalidate_block(u_int block)
1201 {
1202   u_int page=get_page(block<<12);
1203   u_int vpage=get_vpage(block<<12);
1204   inv_debug("INVALIDATE: %x (%d)\n",block<<12,page);
1205   //inv_debug("invalid_code[block]=%d\n",invalid_code[block]);
1206   u_int first,last;
1207   first=last=page;
1208   struct ll_entry *head;
1209   head=jump_dirty[vpage];
1210   //printf("page=%d vpage=%d\n",page,vpage);
1211   while(head!=NULL) {
1212     u_int start,end;
1213     if(vpage>2047||(head->vaddr>>12)==block) { // Ignore vaddr hash collision
1214       get_bounds((int)head->addr,&start,&end);
1215       //printf("start: %x end: %x\n",start,end);
1216       if(page<2048&&start>=0x80000000&&end<0x80000000+RAM_SIZE) {
1217         if(((start-(u_int)rdram)>>12)<=page&&((end-1-(u_int)rdram)>>12)>=page) {
1218           if((((start-(u_int)rdram)>>12)&2047)<first) first=((start-(u_int)rdram)>>12)&2047;
1219           if((((end-1-(u_int)rdram)>>12)&2047)>last) last=((end-1-(u_int)rdram)>>12)&2047;
1220         }
1221       }
1222 #ifndef DISABLE_TLB
1223       if(page<2048&&(signed int)start>=(signed int)0xC0000000&&(signed int)end>=(signed int)0xC0000000) {
1224         if(((start+memory_map[start>>12]-(u_int)rdram)>>12)<=page&&((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)>=page) {
1225           if((((start+memory_map[start>>12]-(u_int)rdram)>>12)&2047)<first) first=((start+memory_map[start>>12]-(u_int)rdram)>>12)&2047;
1226           if((((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)&2047)>last) last=((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)&2047;
1227         }
1228       }
1229 #endif
1230     }
1231     head=head->next;
1232   }
1233   invalidate_block_range(block,first,last);
1234 }
1235
1236 void invalidate_addr(u_int addr)
1237 {
1238 #ifdef PCSX
1239   //static int rhits;
1240   // this check is done by the caller
1241   //if (inv_code_start<=addr&&addr<=inv_code_end) { rhits++; return; }
1242   u_int page=get_vpage(addr);
1243   if(page<2048) { // RAM
1244     struct ll_entry *head;
1245     u_int addr_min=~0, addr_max=0;
1246     int mask=RAM_SIZE-1;
1247     int pg1;
1248     inv_code_start=addr&~0xfff;
1249     inv_code_end=addr|0xfff;
1250     pg1=page;
1251     if (pg1>0) {
1252       // must check previous page too because of spans..
1253       pg1--;
1254       inv_code_start-=0x1000;
1255     }
1256     for(;pg1<=page;pg1++) {
1257       for(head=jump_dirty[pg1];head!=NULL;head=head->next) {
1258         u_int start,end;
1259         get_bounds((int)head->addr,&start,&end);
1260         if((start&mask)<=(addr&mask)&&(addr&mask)<(end&mask)) {
1261           if(start<addr_min) addr_min=start;
1262           if(end>addr_max) addr_max=end;
1263         }
1264         else if(addr<start) {
1265           if(start<inv_code_end)
1266             inv_code_end=start-1;
1267         }
1268         else {
1269           if(end>inv_code_start)
1270             inv_code_start=end;
1271         }
1272       }
1273     }
1274     if (addr_min!=~0) {
1275       inv_debug("INV ADDR: %08x hit %08x-%08x\n", addr, addr_min, addr_max);
1276       inv_code_start=inv_code_end=~0;
1277       invalidate_block_range(addr>>12,(addr_min&mask)>>12,(addr_max&mask)>>12);
1278       return;
1279     }
1280     else {
1281       inv_debug("INV ADDR: %08x miss, inv %08x-%08x, sk %d\n", addr, inv_code_start, inv_code_end, 0);
1282       return;
1283     }
1284   }
1285 #endif
1286   invalidate_block(addr>>12);
1287 }
1288
1289 // This is called when loading a save state.
1290 // Anything could have changed, so invalidate everything.
1291 void invalidate_all_pages()
1292 {
1293   u_int page,n;
1294   for(page=0;page<4096;page++)
1295     invalidate_page(page);
1296   for(page=0;page<1048576;page++)
1297     if(!invalid_code[page]) {
1298       restore_candidate[(page&2047)>>3]|=1<<(page&7);
1299       restore_candidate[((page&2047)>>3)+256]|=1<<(page&7);
1300     }
1301   #ifdef __arm__
1302   __clear_cache((void *)BASE_ADDR,(void *)BASE_ADDR+(1<<TARGET_SIZE_2));
1303   #endif
1304   #ifdef USE_MINI_HT
1305   memset(mini_ht,-1,sizeof(mini_ht));
1306   #endif
1307   #ifndef DISABLE_TLB
1308   // TLB
1309   for(page=0;page<0x100000;page++) {
1310     if(tlb_LUT_r[page]) {
1311       memory_map[page]=((tlb_LUT_r[page]&0xFFFFF000)-(page<<12)+(unsigned int)rdram-0x80000000)>>2;
1312       if(!tlb_LUT_w[page]||!invalid_code[page])
1313         memory_map[page]|=0x40000000; // Write protect
1314     }
1315     else memory_map[page]=-1;
1316     if(page==0x80000) page=0xC0000;
1317   }
1318   tlb_hacks();
1319   #endif
1320 }
1321
1322 // Add an entry to jump_out after making a link
1323 void add_link(u_int vaddr,void *src)
1324 {
1325   u_int page=get_page(vaddr);
1326   inv_debug("add_link: %x -> %x (%d)\n",(int)src,vaddr,page);
1327   int *ptr=(int *)(src+4);
1328   assert((*ptr&0x0fff0000)==0x059f0000);
1329   ll_add(jump_out+page,vaddr,src);
1330   //int ptr=get_pointer(src);
1331   //inv_debug("add_link: Pointer is to %x\n",(int)ptr);
1332 }
1333
1334 // If a code block was found to be unmodified (bit was set in
1335 // restore_candidate) and it remains unmodified (bit is clear
1336 // in invalid_code) then move the entries for that 4K page from
1337 // the dirty list to the clean list.
1338 void clean_blocks(u_int page)
1339 {
1340   struct ll_entry *head;
1341   inv_debug("INV: clean_blocks page=%d\n",page);
1342   head=jump_dirty[page];
1343   while(head!=NULL) {
1344     if(!invalid_code[head->vaddr>>12]) {
1345       // Don't restore blocks which are about to expire from the cache
1346       if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1347         u_int start,end;
1348         if(verify_dirty((int)head->addr)) {
1349           //printf("Possibly Restore %x (%x)\n",head->vaddr, (int)head->addr);
1350           u_int i;
1351           u_int inv=0;
1352           get_bounds((int)head->addr,&start,&end);
1353           if(start-(u_int)rdram<RAM_SIZE) {
1354             for(i=(start-(u_int)rdram+0x80000000)>>12;i<=(end-1-(u_int)rdram+0x80000000)>>12;i++) {
1355               inv|=invalid_code[i];
1356             }
1357           }
1358 #ifndef DISABLE_TLB
1359           if((signed int)head->vaddr>=(signed int)0xC0000000) {
1360             u_int addr = (head->vaddr+(memory_map[head->vaddr>>12]<<2));
1361             //printf("addr=%x start=%x end=%x\n",addr,start,end);
1362             if(addr<start||addr>=end) inv=1;
1363           }
1364 #endif
1365           else if((signed int)head->vaddr>=(signed int)0x80000000+RAM_SIZE) {
1366             inv=1;
1367           }
1368           if(!inv) {
1369             void * clean_addr=(void *)get_clean_addr((int)head->addr);
1370             if((((u_int)clean_addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1371               u_int ppage=page;
1372 #ifndef DISABLE_TLB
1373               if(page<2048&&tlb_LUT_r[head->vaddr>>12]) ppage=(tlb_LUT_r[head->vaddr>>12]^0x80000000)>>12;
1374 #endif
1375               inv_debug("INV: Restored %x (%x/%x)\n",head->vaddr, (int)head->addr, (int)clean_addr);
1376               //printf("page=%x, addr=%x\n",page,head->vaddr);
1377               //assert(head->vaddr>>12==(page|0x80000));
1378               ll_add_32(jump_in+ppage,head->vaddr,head->reg32,clean_addr);
1379               int *ht_bin=hash_table[((head->vaddr>>16)^head->vaddr)&0xFFFF];
1380               if(!head->reg32) {
1381                 if(ht_bin[0]==head->vaddr) {
1382                   ht_bin[1]=(int)clean_addr; // Replace existing entry
1383                 }
1384                 if(ht_bin[2]==head->vaddr) {
1385                   ht_bin[3]=(int)clean_addr; // Replace existing entry
1386                 }
1387               }
1388             }
1389           }
1390         }
1391       }
1392     }
1393     head=head->next;
1394   }
1395 }
1396
1397
1398 void mov_alloc(struct regstat *current,int i)
1399 {
1400   // Note: Don't need to actually alloc the source registers
1401   if((~current->is32>>rs1[i])&1) {
1402     //alloc_reg64(current,i,rs1[i]);
1403     alloc_reg64(current,i,rt1[i]);
1404     current->is32&=~(1LL<<rt1[i]);
1405   } else {
1406     //alloc_reg(current,i,rs1[i]);
1407     alloc_reg(current,i,rt1[i]);
1408     current->is32|=(1LL<<rt1[i]);
1409   }
1410   clear_const(current,rs1[i]);
1411   clear_const(current,rt1[i]);
1412   dirty_reg(current,rt1[i]);
1413 }
1414
1415 void shiftimm_alloc(struct regstat *current,int i)
1416 {
1417   if(opcode2[i]<=0x3) // SLL/SRL/SRA
1418   {
1419     if(rt1[i]) {
1420       if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1421       else lt1[i]=rs1[i];
1422       alloc_reg(current,i,rt1[i]);
1423       current->is32|=1LL<<rt1[i];
1424       dirty_reg(current,rt1[i]);
1425       if(is_const(current,rs1[i])) {
1426         int v=get_const(current,rs1[i]);
1427         if(opcode2[i]==0x00) set_const(current,rt1[i],v<<imm[i]);
1428         if(opcode2[i]==0x02) set_const(current,rt1[i],(u_int)v>>imm[i]);
1429         if(opcode2[i]==0x03) set_const(current,rt1[i],v>>imm[i]);
1430       }
1431       else clear_const(current,rt1[i]);
1432     }
1433   }
1434   else
1435   {
1436     clear_const(current,rs1[i]);
1437     clear_const(current,rt1[i]);
1438   }
1439
1440   if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA
1441   {
1442     if(rt1[i]) {
1443       if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1444       alloc_reg64(current,i,rt1[i]);
1445       current->is32&=~(1LL<<rt1[i]);
1446       dirty_reg(current,rt1[i]);
1447     }
1448   }
1449   if(opcode2[i]==0x3c) // DSLL32
1450   {
1451     if(rt1[i]) {
1452       if(rs1[i]) alloc_reg(current,i,rs1[i]);
1453       alloc_reg64(current,i,rt1[i]);
1454       current->is32&=~(1LL<<rt1[i]);
1455       dirty_reg(current,rt1[i]);
1456     }
1457   }
1458   if(opcode2[i]==0x3e) // DSRL32
1459   {
1460     if(rt1[i]) {
1461       alloc_reg64(current,i,rs1[i]);
1462       if(imm[i]==32) {
1463         alloc_reg64(current,i,rt1[i]);
1464         current->is32&=~(1LL<<rt1[i]);
1465       } else {
1466         alloc_reg(current,i,rt1[i]);
1467         current->is32|=1LL<<rt1[i];
1468       }
1469       dirty_reg(current,rt1[i]);
1470     }
1471   }
1472   if(opcode2[i]==0x3f) // DSRA32
1473   {
1474     if(rt1[i]) {
1475       alloc_reg64(current,i,rs1[i]);
1476       alloc_reg(current,i,rt1[i]);
1477       current->is32|=1LL<<rt1[i];
1478       dirty_reg(current,rt1[i]);
1479     }
1480   }
1481 }
1482
1483 void shift_alloc(struct regstat *current,int i)
1484 {
1485   if(rt1[i]) {
1486     if(opcode2[i]<=0x07) // SLLV/SRLV/SRAV
1487     {
1488       if(rs1[i]) alloc_reg(current,i,rs1[i]);
1489       if(rs2[i]) alloc_reg(current,i,rs2[i]);
1490       alloc_reg(current,i,rt1[i]);
1491       if(rt1[i]==rs2[i]) {
1492         alloc_reg_temp(current,i,-1);
1493         minimum_free_regs[i]=1;
1494       }
1495       current->is32|=1LL<<rt1[i];
1496     } else { // DSLLV/DSRLV/DSRAV
1497       if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1498       if(rs2[i]) alloc_reg(current,i,rs2[i]);
1499       alloc_reg64(current,i,rt1[i]);
1500       current->is32&=~(1LL<<rt1[i]);
1501       if(opcode2[i]==0x16||opcode2[i]==0x17) // DSRLV and DSRAV need a temporary register
1502       {
1503         alloc_reg_temp(current,i,-1);
1504         minimum_free_regs[i]=1;
1505       }
1506     }
1507     clear_const(current,rs1[i]);
1508     clear_const(current,rs2[i]);
1509     clear_const(current,rt1[i]);
1510     dirty_reg(current,rt1[i]);
1511   }
1512 }
1513
1514 void alu_alloc(struct regstat *current,int i)
1515 {
1516   if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
1517     if(rt1[i]) {
1518       if(rs1[i]&&rs2[i]) {
1519         alloc_reg(current,i,rs1[i]);
1520         alloc_reg(current,i,rs2[i]);
1521       }
1522       else {
1523         if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1524         if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]);
1525       }
1526       alloc_reg(current,i,rt1[i]);
1527     }
1528     current->is32|=1LL<<rt1[i];
1529   }
1530   if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU
1531     if(rt1[i]) {
1532       if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1533       {
1534         alloc_reg64(current,i,rs1[i]);
1535         alloc_reg64(current,i,rs2[i]);
1536         alloc_reg(current,i,rt1[i]);
1537       } else {
1538         alloc_reg(current,i,rs1[i]);
1539         alloc_reg(current,i,rs2[i]);
1540         alloc_reg(current,i,rt1[i]);
1541       }
1542     }
1543     current->is32|=1LL<<rt1[i];
1544   }
1545   if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR
1546     if(rt1[i]) {
1547       if(rs1[i]&&rs2[i]) {
1548         alloc_reg(current,i,rs1[i]);
1549         alloc_reg(current,i,rs2[i]);
1550       }
1551       else
1552       {
1553         if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1554         if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]);
1555       }
1556       alloc_reg(current,i,rt1[i]);
1557       if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1558       {
1559         if(!((current->uu>>rt1[i])&1)) {
1560           alloc_reg64(current,i,rt1[i]);
1561         }
1562         if(get_reg(current->regmap,rt1[i]|64)>=0) {
1563           if(rs1[i]&&rs2[i]) {
1564             alloc_reg64(current,i,rs1[i]);
1565             alloc_reg64(current,i,rs2[i]);
1566           }
1567           else
1568           {
1569             // Is is really worth it to keep 64-bit values in registers?
1570             #ifdef NATIVE_64BIT
1571             if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]);
1572             if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg64(current,i,rs2[i]);
1573             #endif
1574           }
1575         }
1576         current->is32&=~(1LL<<rt1[i]);
1577       } else {
1578         current->is32|=1LL<<rt1[i];
1579       }
1580     }
1581   }
1582   if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU
1583     if(rt1[i]) {
1584       if(rs1[i]&&rs2[i]) {
1585         if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1586           alloc_reg64(current,i,rs1[i]);
1587           alloc_reg64(current,i,rs2[i]);
1588           alloc_reg64(current,i,rt1[i]);
1589         } else {
1590           alloc_reg(current,i,rs1[i]);
1591           alloc_reg(current,i,rs2[i]);
1592           alloc_reg(current,i,rt1[i]);
1593         }
1594       }
1595       else {
1596         alloc_reg(current,i,rt1[i]);
1597         if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1598           // DADD used as move, or zeroing
1599           // If we have a 64-bit source, then make the target 64 bits too
1600           if(rs1[i]&&!((current->is32>>rs1[i])&1)) {
1601             if(get_reg(current->regmap,rs1[i])>=0) alloc_reg64(current,i,rs1[i]);
1602             alloc_reg64(current,i,rt1[i]);
1603           } else if(rs2[i]&&!((current->is32>>rs2[i])&1)) {
1604             if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]);
1605             alloc_reg64(current,i,rt1[i]);
1606           }
1607           if(opcode2[i]>=0x2e&&rs2[i]) {
1608             // DSUB used as negation - 64-bit result
1609             // If we have a 32-bit register, extend it to 64 bits
1610             if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]);
1611             alloc_reg64(current,i,rt1[i]);
1612           }
1613         }
1614       }
1615       if(rs1[i]&&rs2[i]) {
1616         current->is32&=~(1LL<<rt1[i]);
1617       } else if(rs1[i]) {
1618         current->is32&=~(1LL<<rt1[i]);
1619         if((current->is32>>rs1[i])&1)
1620           current->is32|=1LL<<rt1[i];
1621       } else if(rs2[i]) {
1622         current->is32&=~(1LL<<rt1[i]);
1623         if((current->is32>>rs2[i])&1)
1624           current->is32|=1LL<<rt1[i];
1625       } else {
1626         current->is32|=1LL<<rt1[i];
1627       }
1628     }
1629   }
1630   clear_const(current,rs1[i]);
1631   clear_const(current,rs2[i]);
1632   clear_const(current,rt1[i]);
1633   dirty_reg(current,rt1[i]);
1634 }
1635
1636 void imm16_alloc(struct regstat *current,int i)
1637 {
1638   if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1639   else lt1[i]=rs1[i];
1640   if(rt1[i]) alloc_reg(current,i,rt1[i]);
1641   if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU
1642     current->is32&=~(1LL<<rt1[i]);
1643     if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1644       // TODO: Could preserve the 32-bit flag if the immediate is zero
1645       alloc_reg64(current,i,rt1[i]);
1646       alloc_reg64(current,i,rs1[i]);
1647     }
1648     clear_const(current,rs1[i]);
1649     clear_const(current,rt1[i]);
1650   }
1651   else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU
1652     if((~current->is32>>rs1[i])&1) alloc_reg64(current,i,rs1[i]);
1653     current->is32|=1LL<<rt1[i];
1654     clear_const(current,rs1[i]);
1655     clear_const(current,rt1[i]);
1656   }
1657   else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI
1658     if(((~current->is32>>rs1[i])&1)&&opcode[i]>0x0c) {
1659       if(rs1[i]!=rt1[i]) {
1660         if(needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]);
1661         alloc_reg64(current,i,rt1[i]);
1662         current->is32&=~(1LL<<rt1[i]);
1663       }
1664     }
1665     else current->is32|=1LL<<rt1[i]; // ANDI clears upper bits
1666     if(is_const(current,rs1[i])) {
1667       int v=get_const(current,rs1[i]);
1668       if(opcode[i]==0x0c) set_const(current,rt1[i],v&imm[i]);
1669       if(opcode[i]==0x0d) set_const(current,rt1[i],v|imm[i]);
1670       if(opcode[i]==0x0e) set_const(current,rt1[i],v^imm[i]);
1671     }
1672     else clear_const(current,rt1[i]);
1673   }
1674   else if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU
1675     if(is_const(current,rs1[i])) {
1676       int v=get_const(current,rs1[i]);
1677       set_const(current,rt1[i],v+imm[i]);
1678     }
1679     else clear_const(current,rt1[i]);
1680     current->is32|=1LL<<rt1[i];
1681   }
1682   else {
1683     set_const(current,rt1[i],((long long)((short)imm[i]))<<16); // LUI
1684     current->is32|=1LL<<rt1[i];
1685   }
1686   dirty_reg(current,rt1[i]);
1687 }
1688
1689 void load_alloc(struct regstat *current,int i)
1690 {
1691   clear_const(current,rt1[i]);
1692   //if(rs1[i]!=rt1[i]&&needed_again(rs1[i],i)) clear_const(current,rs1[i]); // Does this help or hurt?
1693   if(!rs1[i]) current->u&=~1LL; // Allow allocating r0 if it's the source register
1694   if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1695   if(rt1[i]&&!((current->u>>rt1[i])&1)) {
1696     alloc_reg(current,i,rt1[i]);
1697     assert(get_reg(current->regmap,rt1[i])>=0);
1698     if(opcode[i]==0x27||opcode[i]==0x37) // LWU/LD
1699     {
1700       current->is32&=~(1LL<<rt1[i]);
1701       alloc_reg64(current,i,rt1[i]);
1702     }
1703     else if(opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
1704     {
1705       current->is32&=~(1LL<<rt1[i]);
1706       alloc_reg64(current,i,rt1[i]);
1707       alloc_all(current,i);
1708       alloc_reg64(current,i,FTEMP);
1709       minimum_free_regs[i]=HOST_REGS;
1710     }
1711     else current->is32|=1LL<<rt1[i];
1712     dirty_reg(current,rt1[i]);
1713     // If using TLB, need a register for pointer to the mapping table
1714     if(using_tlb) alloc_reg(current,i,TLREG);
1715     // LWL/LWR need a temporary register for the old value
1716     if(opcode[i]==0x22||opcode[i]==0x26)
1717     {
1718       alloc_reg(current,i,FTEMP);
1719       alloc_reg_temp(current,i,-1);
1720       minimum_free_regs[i]=1;
1721     }
1722   }
1723   else
1724   {
1725     // Load to r0 or unneeded register (dummy load)
1726     // but we still need a register to calculate the address
1727     if(opcode[i]==0x22||opcode[i]==0x26)
1728     {
1729       alloc_reg(current,i,FTEMP); // LWL/LWR need another temporary
1730     }
1731     // If using TLB, need a register for pointer to the mapping table
1732     if(using_tlb) alloc_reg(current,i,TLREG);
1733     alloc_reg_temp(current,i,-1);
1734     minimum_free_regs[i]=1;
1735     if(opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
1736     {
1737       alloc_all(current,i);
1738       alloc_reg64(current,i,FTEMP);
1739       minimum_free_regs[i]=HOST_REGS;
1740     }
1741   }
1742 }
1743
1744 void store_alloc(struct regstat *current,int i)
1745 {
1746   clear_const(current,rs2[i]);
1747   if(!(rs2[i])) current->u&=~1LL; // Allow allocating r0 if necessary
1748   if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1749   alloc_reg(current,i,rs2[i]);
1750   if(opcode[i]==0x2c||opcode[i]==0x2d||opcode[i]==0x3f) { // 64-bit SDL/SDR/SD
1751     alloc_reg64(current,i,rs2[i]);
1752     if(rs2[i]) alloc_reg(current,i,FTEMP);
1753   }
1754   // If using TLB, need a register for pointer to the mapping table
1755   if(using_tlb) alloc_reg(current,i,TLREG);
1756   #if defined(HOST_IMM8)
1757   // On CPUs without 32-bit immediates we need a pointer to invalid_code
1758   else alloc_reg(current,i,INVCP);
1759   #endif
1760   if(opcode[i]==0x2a||opcode[i]==0x2e||opcode[i]==0x2c||opcode[i]==0x2d) { // SWL/SWL/SDL/SDR
1761     alloc_reg(current,i,FTEMP);
1762   }
1763   // We need a temporary register for address generation
1764   alloc_reg_temp(current,i,-1);
1765   minimum_free_regs[i]=1;
1766 }
1767
1768 void c1ls_alloc(struct regstat *current,int i)
1769 {
1770   //clear_const(current,rs1[i]); // FIXME
1771   clear_const(current,rt1[i]);
1772   if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1773   alloc_reg(current,i,CSREG); // Status
1774   alloc_reg(current,i,FTEMP);
1775   if(opcode[i]==0x35||opcode[i]==0x3d) { // 64-bit LDC1/SDC1
1776     alloc_reg64(current,i,FTEMP);
1777   }
1778   // If using TLB, need a register for pointer to the mapping table
1779   if(using_tlb) alloc_reg(current,i,TLREG);
1780   #if defined(HOST_IMM8)
1781   // On CPUs without 32-bit immediates we need a pointer to invalid_code
1782   else if((opcode[i]&0x3b)==0x39) // SWC1/SDC1
1783     alloc_reg(current,i,INVCP);
1784   #endif
1785   // We need a temporary register for address generation
1786   alloc_reg_temp(current,i,-1);
1787 }
1788
1789 void c2ls_alloc(struct regstat *current,int i)
1790 {
1791   clear_const(current,rt1[i]);
1792   if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1793   alloc_reg(current,i,FTEMP);
1794   // If using TLB, need a register for pointer to the mapping table
1795   if(using_tlb) alloc_reg(current,i,TLREG);
1796   #if defined(HOST_IMM8)
1797   // On CPUs without 32-bit immediates we need a pointer to invalid_code
1798   else if((opcode[i]&0x3b)==0x3a) // SWC2/SDC2
1799     alloc_reg(current,i,INVCP);
1800   #endif
1801   // We need a temporary register for address generation
1802   alloc_reg_temp(current,i,-1);
1803   minimum_free_regs[i]=1;
1804 }
1805
1806 #ifndef multdiv_alloc
1807 void multdiv_alloc(struct regstat *current,int i)
1808 {
1809   //  case 0x18: MULT
1810   //  case 0x19: MULTU
1811   //  case 0x1A: DIV
1812   //  case 0x1B: DIVU
1813   //  case 0x1C: DMULT
1814   //  case 0x1D: DMULTU
1815   //  case 0x1E: DDIV
1816   //  case 0x1F: DDIVU
1817   clear_const(current,rs1[i]);
1818   clear_const(current,rs2[i]);
1819   if(rs1[i]&&rs2[i])
1820   {
1821     if((opcode2[i]&4)==0) // 32-bit
1822     {
1823       current->u&=~(1LL<<HIREG);
1824       current->u&=~(1LL<<LOREG);
1825       alloc_reg(current,i,HIREG);
1826       alloc_reg(current,i,LOREG);
1827       alloc_reg(current,i,rs1[i]);
1828       alloc_reg(current,i,rs2[i]);
1829       current->is32|=1LL<<HIREG;
1830       current->is32|=1LL<<LOREG;
1831       dirty_reg(current,HIREG);
1832       dirty_reg(current,LOREG);
1833     }
1834     else // 64-bit
1835     {
1836       current->u&=~(1LL<<HIREG);
1837       current->u&=~(1LL<<LOREG);
1838       current->uu&=~(1LL<<HIREG);
1839       current->uu&=~(1LL<<LOREG);
1840       alloc_reg64(current,i,HIREG);
1841       //if(HOST_REGS>10) alloc_reg64(current,i,LOREG);
1842       alloc_reg64(current,i,rs1[i]);
1843       alloc_reg64(current,i,rs2[i]);
1844       alloc_all(current,i);
1845       current->is32&=~(1LL<<HIREG);
1846       current->is32&=~(1LL<<LOREG);
1847       dirty_reg(current,HIREG);
1848       dirty_reg(current,LOREG);
1849       minimum_free_regs[i]=HOST_REGS;
1850     }
1851   }
1852   else
1853   {
1854     // Multiply by zero is zero.
1855     // MIPS does not have a divide by zero exception.
1856     // The result is undefined, we return zero.
1857     alloc_reg(current,i,HIREG);
1858     alloc_reg(current,i,LOREG);
1859     current->is32|=1LL<<HIREG;
1860     current->is32|=1LL<<LOREG;
1861     dirty_reg(current,HIREG);
1862     dirty_reg(current,LOREG);
1863   }
1864 }
1865 #endif
1866
1867 void cop0_alloc(struct regstat *current,int i)
1868 {
1869   if(opcode2[i]==0) // MFC0
1870   {
1871     if(rt1[i]) {
1872       clear_const(current,rt1[i]);
1873       alloc_all(current,i);
1874       alloc_reg(current,i,rt1[i]);
1875       current->is32|=1LL<<rt1[i];
1876       dirty_reg(current,rt1[i]);
1877     }
1878   }
1879   else if(opcode2[i]==4) // MTC0
1880   {
1881     if(rs1[i]){
1882       clear_const(current,rs1[i]);
1883       alloc_reg(current,i,rs1[i]);
1884       alloc_all(current,i);
1885     }
1886     else {
1887       alloc_all(current,i); // FIXME: Keep r0
1888       current->u&=~1LL;
1889       alloc_reg(current,i,0);
1890     }
1891   }
1892   else
1893   {
1894     // TLBR/TLBWI/TLBWR/TLBP/ERET
1895     assert(opcode2[i]==0x10);
1896     alloc_all(current,i);
1897   }
1898   minimum_free_regs[i]=HOST_REGS;
1899 }
1900
1901 void cop1_alloc(struct regstat *current,int i)
1902 {
1903   alloc_reg(current,i,CSREG); // Load status
1904   if(opcode2[i]<3) // MFC1/DMFC1/CFC1
1905   {
1906     if(rt1[i]){
1907       clear_const(current,rt1[i]);
1908       if(opcode2[i]==1) {
1909         alloc_reg64(current,i,rt1[i]); // DMFC1
1910         current->is32&=~(1LL<<rt1[i]);
1911       }else{
1912         alloc_reg(current,i,rt1[i]); // MFC1/CFC1
1913         current->is32|=1LL<<rt1[i];
1914       }
1915       dirty_reg(current,rt1[i]);
1916     }
1917     alloc_reg_temp(current,i,-1);
1918   }
1919   else if(opcode2[i]>3) // MTC1/DMTC1/CTC1
1920   {
1921     if(rs1[i]){
1922       clear_const(current,rs1[i]);
1923       if(opcode2[i]==5)
1924         alloc_reg64(current,i,rs1[i]); // DMTC1
1925       else
1926         alloc_reg(current,i,rs1[i]); // MTC1/CTC1
1927       alloc_reg_temp(current,i,-1);
1928     }
1929     else {
1930       current->u&=~1LL;
1931       alloc_reg(current,i,0);
1932       alloc_reg_temp(current,i,-1);
1933     }
1934   }
1935   minimum_free_regs[i]=1;
1936 }
1937 void fconv_alloc(struct regstat *current,int i)
1938 {
1939   alloc_reg(current,i,CSREG); // Load status
1940   alloc_reg_temp(current,i,-1);
1941   minimum_free_regs[i]=1;
1942 }
1943 void float_alloc(struct regstat *current,int i)
1944 {
1945   alloc_reg(current,i,CSREG); // Load status
1946   alloc_reg_temp(current,i,-1);
1947   minimum_free_regs[i]=1;
1948 }
1949 void c2op_alloc(struct regstat *current,int i)
1950 {
1951   alloc_reg_temp(current,i,-1);
1952 }
1953 void fcomp_alloc(struct regstat *current,int i)
1954 {
1955   alloc_reg(current,i,CSREG); // Load status
1956   alloc_reg(current,i,FSREG); // Load flags
1957   dirty_reg(current,FSREG); // Flag will be modified
1958   alloc_reg_temp(current,i,-1);
1959   minimum_free_regs[i]=1;
1960 }
1961
1962 void syscall_alloc(struct regstat *current,int i)
1963 {
1964   alloc_cc(current,i);
1965   dirty_reg(current,CCREG);
1966   alloc_all(current,i);
1967   minimum_free_regs[i]=HOST_REGS;
1968   current->isconst=0;
1969 }
1970
1971 void delayslot_alloc(struct regstat *current,int i)
1972 {
1973   switch(itype[i]) {
1974     case UJUMP:
1975     case CJUMP:
1976     case SJUMP:
1977     case RJUMP:
1978     case FJUMP:
1979     case SYSCALL:
1980     case HLECALL:
1981     case SPAN:
1982       assem_debug("jump in the delay slot.  this shouldn't happen.\n");//exit(1);
1983       printf("Disabled speculative precompilation\n");
1984       stop_after_jal=1;
1985       break;
1986     case IMM16:
1987       imm16_alloc(current,i);
1988       break;
1989     case LOAD:
1990     case LOADLR:
1991       load_alloc(current,i);
1992       break;
1993     case STORE:
1994     case STORELR:
1995       store_alloc(current,i);
1996       break;
1997     case ALU:
1998       alu_alloc(current,i);
1999       break;
2000     case SHIFT:
2001       shift_alloc(current,i);
2002       break;
2003     case MULTDIV:
2004       multdiv_alloc(current,i);
2005       break;
2006     case SHIFTIMM:
2007       shiftimm_alloc(current,i);
2008       break;
2009     case MOV:
2010       mov_alloc(current,i);
2011       break;
2012     case COP0:
2013       cop0_alloc(current,i);
2014       break;
2015     case COP1:
2016     case COP2:
2017       cop1_alloc(current,i);
2018       break;
2019     case C1LS:
2020       c1ls_alloc(current,i);
2021       break;
2022     case C2LS:
2023       c2ls_alloc(current,i);
2024       break;
2025     case FCONV:
2026       fconv_alloc(current,i);
2027       break;
2028     case FLOAT:
2029       float_alloc(current,i);
2030       break;
2031     case FCOMP:
2032       fcomp_alloc(current,i);
2033       break;
2034     case C2OP:
2035       c2op_alloc(current,i);
2036       break;
2037   }
2038 }
2039
2040 // Special case where a branch and delay slot span two pages in virtual memory
2041 static void pagespan_alloc(struct regstat *current,int i)
2042 {
2043   current->isconst=0;
2044   current->wasconst=0;
2045   regs[i].wasconst=0;
2046   minimum_free_regs[i]=HOST_REGS;
2047   alloc_all(current,i);
2048   alloc_cc(current,i);
2049   dirty_reg(current,CCREG);
2050   if(opcode[i]==3) // JAL
2051   {
2052     alloc_reg(current,i,31);
2053     dirty_reg(current,31);
2054   }
2055   if(opcode[i]==0&&(opcode2[i]&0x3E)==8) // JR/JALR
2056   {
2057     alloc_reg(current,i,rs1[i]);
2058     if (rt1[i]!=0) {
2059       alloc_reg(current,i,rt1[i]);
2060       dirty_reg(current,rt1[i]);
2061     }
2062   }
2063   if((opcode[i]&0x2E)==4) // BEQ/BNE/BEQL/BNEL
2064   {
2065     if(rs1[i]) alloc_reg(current,i,rs1[i]);
2066     if(rs2[i]) alloc_reg(current,i,rs2[i]);
2067     if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
2068     {
2069       if(rs1[i]) alloc_reg64(current,i,rs1[i]);
2070       if(rs2[i]) alloc_reg64(current,i,rs2[i]);
2071     }
2072   }
2073   else
2074   if((opcode[i]&0x2E)==6) // BLEZ/BGTZ/BLEZL/BGTZL
2075   {
2076     if(rs1[i]) alloc_reg(current,i,rs1[i]);
2077     if(!((current->is32>>rs1[i])&1))
2078     {
2079       if(rs1[i]) alloc_reg64(current,i,rs1[i]);
2080     }
2081   }
2082   else
2083   if(opcode[i]==0x11) // BC1
2084   {
2085     alloc_reg(current,i,FSREG);
2086     alloc_reg(current,i,CSREG);
2087   }
2088   //else ...
2089 }
2090
2091 add_stub(int type,int addr,int retaddr,int a,int b,int c,int d,int e)
2092 {
2093   stubs[stubcount][0]=type;
2094   stubs[stubcount][1]=addr;
2095   stubs[stubcount][2]=retaddr;
2096   stubs[stubcount][3]=a;
2097   stubs[stubcount][4]=b;
2098   stubs[stubcount][5]=c;
2099   stubs[stubcount][6]=d;
2100   stubs[stubcount][7]=e;
2101   stubcount++;
2102 }
2103
2104 // Write out a single register
2105 void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32)
2106 {
2107   int hr;
2108   for(hr=0;hr<HOST_REGS;hr++) {
2109     if(hr!=EXCLUDE_REG) {
2110       if((regmap[hr]&63)==r) {
2111         if((dirty>>hr)&1) {
2112           if(regmap[hr]<64) {
2113             emit_storereg(r,hr);
2114 #ifndef FORCE32
2115             if((is32>>regmap[hr])&1) {
2116               emit_sarimm(hr,31,hr);
2117               emit_storereg(r|64,hr);
2118             }
2119 #endif
2120           }else{
2121             emit_storereg(r|64,hr);
2122           }
2123         }
2124       }
2125     }
2126   }
2127 }
2128
2129 int mchecksum()
2130 {
2131   //if(!tracedebug) return 0;
2132   int i;
2133   int sum=0;
2134   for(i=0;i<2097152;i++) {
2135     unsigned int temp=sum;
2136     sum<<=1;
2137     sum|=(~temp)>>31;
2138     sum^=((u_int *)rdram)[i];
2139   }
2140   return sum;
2141 }
2142 int rchecksum()
2143 {
2144   int i;
2145   int sum=0;
2146   for(i=0;i<64;i++)
2147     sum^=((u_int *)reg)[i];
2148   return sum;
2149 }
2150 void rlist()
2151 {
2152   int i;
2153   printf("TRACE: ");
2154   for(i=0;i<32;i++)
2155     printf("r%d:%8x%8x ",i,((int *)(reg+i))[1],((int *)(reg+i))[0]);
2156   printf("\n");
2157 #ifndef DISABLE_COP1
2158   printf("TRACE: ");
2159   for(i=0;i<32;i++)
2160     printf("f%d:%8x%8x ",i,((int*)reg_cop1_simple[i])[1],*((int*)reg_cop1_simple[i]));
2161   printf("\n");
2162 #endif
2163 }
2164
2165 void enabletrace()
2166 {
2167   tracedebug=1;
2168 }
2169
2170 void memdebug(int i)
2171 {
2172   //printf("TRACE: count=%d next=%d (checksum %x) lo=%8x%8x\n",Count,next_interupt,mchecksum(),(int)(reg[LOREG]>>32),(int)reg[LOREG]);
2173   //printf("TRACE: count=%d next=%d (rchecksum %x)\n",Count,next_interupt,rchecksum());
2174   //rlist();
2175   //if(tracedebug) {
2176   //if(Count>=-2084597794) {
2177   if((signed int)Count>=-2084597794&&(signed int)Count<0) {
2178   //if(0) {
2179     printf("TRACE: count=%d next=%d (checksum %x)\n",Count,next_interupt,mchecksum());
2180     //printf("TRACE: count=%d next=%d (checksum %x) Status=%x\n",Count,next_interupt,mchecksum(),Status);
2181     //printf("TRACE: count=%d next=%d (checksum %x) hi=%8x%8x\n",Count,next_interupt,mchecksum(),(int)(reg[HIREG]>>32),(int)reg[HIREG]);
2182     rlist();
2183     #ifdef __i386__
2184     printf("TRACE: %x\n",(&i)[-1]);
2185     #endif
2186     #ifdef __arm__
2187     int j;
2188     printf("TRACE: %x \n",(&j)[10]);
2189     printf("TRACE: %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x\n",(&j)[1],(&j)[2],(&j)[3],(&j)[4],(&j)[5],(&j)[6],(&j)[7],(&j)[8],(&j)[9],(&j)[10],(&j)[11],(&j)[12],(&j)[13],(&j)[14],(&j)[15],(&j)[16],(&j)[17],(&j)[18],(&j)[19],(&j)[20]);
2190     #endif
2191     //fflush(stdout);
2192   }
2193   //printf("TRACE: %x\n",(&i)[-1]);
2194 }
2195
2196 void tlb_debug(u_int cause, u_int addr, u_int iaddr)
2197 {
2198   printf("TLB Exception: instruction=%x addr=%x cause=%x\n",iaddr, addr, cause);
2199 }
2200
2201 void alu_assemble(int i,struct regstat *i_regs)
2202 {
2203   if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
2204     if(rt1[i]) {
2205       signed char s1,s2,t;
2206       t=get_reg(i_regs->regmap,rt1[i]);
2207       if(t>=0) {
2208         s1=get_reg(i_regs->regmap,rs1[i]);
2209         s2=get_reg(i_regs->regmap,rs2[i]);
2210         if(rs1[i]&&rs2[i]) {
2211           assert(s1>=0);
2212           assert(s2>=0);
2213           if(opcode2[i]&2) emit_sub(s1,s2,t);
2214           else emit_add(s1,s2,t);
2215         }
2216         else if(rs1[i]) {
2217           if(s1>=0) emit_mov(s1,t);
2218           else emit_loadreg(rs1[i],t);
2219         }
2220         else if(rs2[i]) {
2221           if(s2>=0) {
2222             if(opcode2[i]&2) emit_neg(s2,t);
2223             else emit_mov(s2,t);
2224           }
2225           else {
2226             emit_loadreg(rs2[i],t);
2227             if(opcode2[i]&2) emit_neg(t,t);
2228           }
2229         }
2230         else emit_zeroreg(t);
2231       }
2232     }
2233   }
2234   if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU
2235     if(rt1[i]) {
2236       signed char s1l,s2l,s1h,s2h,tl,th;
2237       tl=get_reg(i_regs->regmap,rt1[i]);
2238       th=get_reg(i_regs->regmap,rt1[i]|64);
2239       if(tl>=0) {
2240         s1l=get_reg(i_regs->regmap,rs1[i]);
2241         s2l=get_reg(i_regs->regmap,rs2[i]);
2242         s1h=get_reg(i_regs->regmap,rs1[i]|64);
2243         s2h=get_reg(i_regs->regmap,rs2[i]|64);
2244         if(rs1[i]&&rs2[i]) {
2245           assert(s1l>=0);
2246           assert(s2l>=0);
2247           if(opcode2[i]&2) emit_subs(s1l,s2l,tl);
2248           else emit_adds(s1l,s2l,tl);
2249           if(th>=0) {
2250             #ifdef INVERTED_CARRY
2251             if(opcode2[i]&2) {if(s1h!=th) emit_mov(s1h,th);emit_sbb(th,s2h);}
2252             #else
2253             if(opcode2[i]&2) emit_sbc(s1h,s2h,th);
2254             #endif
2255             else emit_add(s1h,s2h,th);
2256           }
2257         }
2258         else if(rs1[i]) {
2259           if(s1l>=0) emit_mov(s1l,tl);
2260           else emit_loadreg(rs1[i],tl);
2261           if(th>=0) {
2262             if(s1h>=0) emit_mov(s1h,th);
2263             else emit_loadreg(rs1[i]|64,th);
2264           }
2265         }
2266         else if(rs2[i]) {
2267           if(s2l>=0) {
2268             if(opcode2[i]&2) emit_negs(s2l,tl);
2269             else emit_mov(s2l,tl);
2270           }
2271           else {
2272             emit_loadreg(rs2[i],tl);
2273             if(opcode2[i]&2) emit_negs(tl,tl);
2274           }
2275           if(th>=0) {
2276             #ifdef INVERTED_CARRY
2277             if(s2h>=0) emit_mov(s2h,th);
2278             else emit_loadreg(rs2[i]|64,th);
2279             if(opcode2[i]&2) {
2280               emit_adcimm(-1,th); // x86 has inverted carry flag
2281               emit_not(th,th);
2282             }
2283             #else
2284             if(opcode2[i]&2) {
2285               if(s2h>=0) emit_rscimm(s2h,0,th);
2286               else {
2287                 emit_loadreg(rs2[i]|64,th);
2288                 emit_rscimm(th,0,th);
2289               }
2290             }else{
2291               if(s2h>=0) emit_mov(s2h,th);
2292               else emit_loadreg(rs2[i]|64,th);
2293             }
2294             #endif
2295           }
2296         }
2297         else {
2298           emit_zeroreg(tl);
2299           if(th>=0) emit_zeroreg(th);
2300         }
2301       }
2302     }
2303   }
2304   if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU
2305     if(rt1[i]) {
2306       signed char s1l,s1h,s2l,s2h,t;
2307       if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1))
2308       {
2309         t=get_reg(i_regs->regmap,rt1[i]);
2310         //assert(t>=0);
2311         if(t>=0) {
2312           s1l=get_reg(i_regs->regmap,rs1[i]);
2313           s1h=get_reg(i_regs->regmap,rs1[i]|64);
2314           s2l=get_reg(i_regs->regmap,rs2[i]);
2315           s2h=get_reg(i_regs->regmap,rs2[i]|64);
2316           if(rs2[i]==0) // rx<r0
2317           {
2318             assert(s1h>=0);
2319             if(opcode2[i]==0x2a) // SLT
2320               emit_shrimm(s1h,31,t);
2321             else // SLTU (unsigned can not be less than zero)
2322               emit_zeroreg(t);
2323           }
2324           else if(rs1[i]==0) // r0<rx
2325           {
2326             assert(s2h>=0);
2327             if(opcode2[i]==0x2a) // SLT
2328               emit_set_gz64_32(s2h,s2l,t);
2329             else // SLTU (set if not zero)
2330               emit_set_nz64_32(s2h,s2l,t);
2331           }
2332           else {
2333             assert(s1l>=0);assert(s1h>=0);
2334             assert(s2l>=0);assert(s2h>=0);
2335             if(opcode2[i]==0x2a) // SLT
2336               emit_set_if_less64_32(s1h,s1l,s2h,s2l,t);
2337             else // SLTU
2338               emit_set_if_carry64_32(s1h,s1l,s2h,s2l,t);
2339           }
2340         }
2341       } else {
2342         t=get_reg(i_regs->regmap,rt1[i]);
2343         //assert(t>=0);
2344         if(t>=0) {
2345           s1l=get_reg(i_regs->regmap,rs1[i]);
2346           s2l=get_reg(i_regs->regmap,rs2[i]);
2347           if(rs2[i]==0) // rx<r0
2348           {
2349             assert(s1l>=0);
2350             if(opcode2[i]==0x2a) // SLT
2351               emit_shrimm(s1l,31,t);
2352             else // SLTU (unsigned can not be less than zero)
2353               emit_zeroreg(t);
2354           }
2355           else if(rs1[i]==0) // r0<rx
2356           {
2357             assert(s2l>=0);
2358             if(opcode2[i]==0x2a) // SLT
2359               emit_set_gz32(s2l,t);
2360             else // SLTU (set if not zero)
2361               emit_set_nz32(s2l,t);
2362           }
2363           else{
2364             assert(s1l>=0);assert(s2l>=0);
2365             if(opcode2[i]==0x2a) // SLT
2366               emit_set_if_less32(s1l,s2l,t);
2367             else // SLTU
2368               emit_set_if_carry32(s1l,s2l,t);
2369           }
2370         }
2371       }
2372     }
2373   }
2374   if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR
2375     if(rt1[i]) {
2376       signed char s1l,s1h,s2l,s2h,th,tl;
2377       tl=get_reg(i_regs->regmap,rt1[i]);
2378       th=get_reg(i_regs->regmap,rt1[i]|64);
2379       if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1)&&th>=0)
2380       {
2381         assert(tl>=0);
2382         if(tl>=0) {
2383           s1l=get_reg(i_regs->regmap,rs1[i]);
2384           s1h=get_reg(i_regs->regmap,rs1[i]|64);
2385           s2l=get_reg(i_regs->regmap,rs2[i]);
2386           s2h=get_reg(i_regs->regmap,rs2[i]|64);
2387           if(rs1[i]&&rs2[i]) {
2388             assert(s1l>=0);assert(s1h>=0);
2389             assert(s2l>=0);assert(s2h>=0);
2390             if(opcode2[i]==0x24) { // AND
2391               emit_and(s1l,s2l,tl);
2392               emit_and(s1h,s2h,th);
2393             } else
2394             if(opcode2[i]==0x25) { // OR
2395               emit_or(s1l,s2l,tl);
2396               emit_or(s1h,s2h,th);
2397             } else
2398             if(opcode2[i]==0x26) { // XOR
2399               emit_xor(s1l,s2l,tl);
2400               emit_xor(s1h,s2h,th);
2401             } else
2402             if(opcode2[i]==0x27) { // NOR
2403               emit_or(s1l,s2l,tl);
2404               emit_or(s1h,s2h,th);
2405               emit_not(tl,tl);
2406               emit_not(th,th);
2407             }
2408           }
2409           else
2410           {
2411             if(opcode2[i]==0x24) { // AND
2412               emit_zeroreg(tl);
2413               emit_zeroreg(th);
2414             } else
2415             if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR
2416               if(rs1[i]){
2417                 if(s1l>=0) emit_mov(s1l,tl);
2418                 else emit_loadreg(rs1[i],tl);
2419                 if(s1h>=0) emit_mov(s1h,th);
2420                 else emit_loadreg(rs1[i]|64,th);
2421               }
2422               else
2423               if(rs2[i]){
2424                 if(s2l>=0) emit_mov(s2l,tl);
2425                 else emit_loadreg(rs2[i],tl);
2426                 if(s2h>=0) emit_mov(s2h,th);
2427                 else emit_loadreg(rs2[i]|64,th);
2428               }
2429               else{
2430                 emit_zeroreg(tl);
2431                 emit_zeroreg(th);
2432               }
2433             } else
2434             if(opcode2[i]==0x27) { // NOR
2435               if(rs1[i]){
2436                 if(s1l>=0) emit_not(s1l,tl);
2437                 else{
2438                   emit_loadreg(rs1[i],tl);
2439                   emit_not(tl,tl);
2440                 }
2441                 if(s1h>=0) emit_not(s1h,th);
2442                 else{
2443                   emit_loadreg(rs1[i]|64,th);
2444                   emit_not(th,th);
2445                 }
2446               }
2447               else
2448               if(rs2[i]){
2449                 if(s2l>=0) emit_not(s2l,tl);
2450                 else{
2451                   emit_loadreg(rs2[i],tl);
2452                   emit_not(tl,tl);
2453                 }
2454                 if(s2h>=0) emit_not(s2h,th);
2455                 else{
2456                   emit_loadreg(rs2[i]|64,th);
2457                   emit_not(th,th);
2458                 }
2459               }
2460               else {
2461                 emit_movimm(-1,tl);
2462                 emit_movimm(-1,th);
2463               }
2464             }
2465           }
2466         }
2467       }
2468       else
2469       {
2470         // 32 bit
2471         if(tl>=0) {
2472           s1l=get_reg(i_regs->regmap,rs1[i]);
2473           s2l=get_reg(i_regs->regmap,rs2[i]);
2474           if(rs1[i]&&rs2[i]) {
2475             assert(s1l>=0);
2476             assert(s2l>=0);
2477             if(opcode2[i]==0x24) { // AND
2478               emit_and(s1l,s2l,tl);
2479             } else
2480             if(opcode2[i]==0x25) { // OR
2481               emit_or(s1l,s2l,tl);
2482             } else
2483             if(opcode2[i]==0x26) { // XOR
2484               emit_xor(s1l,s2l,tl);
2485             } else
2486             if(opcode2[i]==0x27) { // NOR
2487               emit_or(s1l,s2l,tl);
2488               emit_not(tl,tl);
2489             }
2490           }
2491           else
2492           {
2493             if(opcode2[i]==0x24) { // AND
2494               emit_zeroreg(tl);
2495             } else
2496             if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR
2497               if(rs1[i]){
2498                 if(s1l>=0) emit_mov(s1l,tl);
2499                 else emit_loadreg(rs1[i],tl); // CHECK: regmap_entry?
2500               }
2501               else
2502               if(rs2[i]){
2503                 if(s2l>=0) emit_mov(s2l,tl);
2504                 else emit_loadreg(rs2[i],tl); // CHECK: regmap_entry?
2505               }
2506               else emit_zeroreg(tl);
2507             } else
2508             if(opcode2[i]==0x27) { // NOR
2509               if(rs1[i]){
2510                 if(s1l>=0) emit_not(s1l,tl);
2511                 else {
2512                   emit_loadreg(rs1[i],tl);
2513                   emit_not(tl,tl);
2514                 }
2515               }
2516               else
2517               if(rs2[i]){
2518                 if(s2l>=0) emit_not(s2l,tl);
2519                 else {
2520                   emit_loadreg(rs2[i],tl);
2521                   emit_not(tl,tl);
2522                 }
2523               }
2524               else emit_movimm(-1,tl);
2525             }
2526           }
2527         }
2528       }
2529     }
2530   }
2531 }
2532
2533 void imm16_assemble(int i,struct regstat *i_regs)
2534 {
2535   if (opcode[i]==0x0f) { // LUI
2536     if(rt1[i]) {
2537       signed char t;
2538       t=get_reg(i_regs->regmap,rt1[i]);
2539       //assert(t>=0);
2540       if(t>=0) {
2541         if(!((i_regs->isconst>>t)&1))
2542           emit_movimm(imm[i]<<16,t);
2543       }
2544     }
2545   }
2546   if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU
2547     if(rt1[i]) {
2548       signed char s,t;
2549       t=get_reg(i_regs->regmap,rt1[i]);
2550       s=get_reg(i_regs->regmap,rs1[i]);
2551       if(rs1[i]) {
2552         //assert(t>=0);
2553         //assert(s>=0);
2554         if(t>=0) {
2555           if(!((i_regs->isconst>>t)&1)) {
2556             if(s<0) {
2557               if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2558               emit_addimm(t,imm[i],t);
2559             }else{
2560               if(!((i_regs->wasconst>>s)&1))
2561                 emit_addimm(s,imm[i],t);
2562               else
2563                 emit_movimm(constmap[i][s]+imm[i],t);
2564             }
2565           }
2566         }
2567       } else {
2568         if(t>=0) {
2569           if(!((i_regs->isconst>>t)&1))
2570             emit_movimm(imm[i],t);
2571         }
2572       }
2573     }
2574   }
2575   if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU
2576     if(rt1[i]) {
2577       signed char sh,sl,th,tl;
2578       th=get_reg(i_regs->regmap,rt1[i]|64);
2579       tl=get_reg(i_regs->regmap,rt1[i]);
2580       sh=get_reg(i_regs->regmap,rs1[i]|64);
2581       sl=get_reg(i_regs->regmap,rs1[i]);
2582       if(tl>=0) {
2583         if(rs1[i]) {
2584           assert(sh>=0);
2585           assert(sl>=0);
2586           if(th>=0) {
2587             emit_addimm64_32(sh,sl,imm[i],th,tl);
2588           }
2589           else {
2590             emit_addimm(sl,imm[i],tl);
2591           }
2592         } else {
2593           emit_movimm(imm[i],tl);
2594           if(th>=0) emit_movimm(((signed int)imm[i])>>31,th);
2595         }
2596       }
2597     }
2598   }
2599   else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU
2600     if(rt1[i]) {
2601       //assert(rs1[i]!=0); // r0 might be valid, but it's probably a bug
2602       signed char sh,sl,t;
2603       t=get_reg(i_regs->regmap,rt1[i]);
2604       sh=get_reg(i_regs->regmap,rs1[i]|64);
2605       sl=get_reg(i_regs->regmap,rs1[i]);
2606       //assert(t>=0);
2607       if(t>=0) {
2608         if(rs1[i]>0) {
2609           if(sh<0) assert((i_regs->was32>>rs1[i])&1);
2610           if(sh<0||((i_regs->was32>>rs1[i])&1)) {
2611             if(opcode[i]==0x0a) { // SLTI
2612               if(sl<0) {
2613                 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2614                 emit_slti32(t,imm[i],t);
2615               }else{
2616                 emit_slti32(sl,imm[i],t);
2617               }
2618             }
2619             else { // SLTIU
2620               if(sl<0) {
2621                 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2622                 emit_sltiu32(t,imm[i],t);
2623               }else{
2624                 emit_sltiu32(sl,imm[i],t);
2625               }
2626             }
2627           }else{ // 64-bit
2628             assert(sl>=0);
2629             if(opcode[i]==0x0a) // SLTI
2630               emit_slti64_32(sh,sl,imm[i],t);
2631             else // SLTIU
2632               emit_sltiu64_32(sh,sl,imm[i],t);
2633           }
2634         }else{
2635           // SLTI(U) with r0 is just stupid,
2636           // nonetheless examples can be found
2637           if(opcode[i]==0x0a) // SLTI
2638             if(0<imm[i]) emit_movimm(1,t);
2639             else emit_zeroreg(t);
2640           else // SLTIU
2641           {
2642             if(imm[i]) emit_movimm(1,t);
2643             else emit_zeroreg(t);
2644           }
2645         }
2646       }
2647     }
2648   }
2649   else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI
2650     if(rt1[i]) {
2651       signed char sh,sl,th,tl;
2652       th=get_reg(i_regs->regmap,rt1[i]|64);
2653       tl=get_reg(i_regs->regmap,rt1[i]);
2654       sh=get_reg(i_regs->regmap,rs1[i]|64);
2655       sl=get_reg(i_regs->regmap,rs1[i]);
2656       if(tl>=0 && !((i_regs->isconst>>tl)&1)) {
2657         if(opcode[i]==0x0c) //ANDI
2658         {
2659           if(rs1[i]) {
2660             if(sl<0) {
2661               if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl);
2662               emit_andimm(tl,imm[i],tl);
2663             }else{
2664               if(!((i_regs->wasconst>>sl)&1))
2665                 emit_andimm(sl,imm[i],tl);
2666               else
2667                 emit_movimm(constmap[i][sl]&imm[i],tl);
2668             }
2669           }
2670           else
2671             emit_zeroreg(tl);
2672           if(th>=0) emit_zeroreg(th);
2673         }
2674         else
2675         {
2676           if(rs1[i]) {
2677             if(sl<0) {
2678               if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl);
2679             }
2680             if(th>=0) {
2681               if(sh<0) {
2682                 emit_loadreg(rs1[i]|64,th);
2683               }else{
2684                 emit_mov(sh,th);
2685               }
2686             }
2687             if(opcode[i]==0x0d) //ORI
2688             if(sl<0) {
2689               emit_orimm(tl,imm[i],tl);
2690             }else{
2691               if(!((i_regs->wasconst>>sl)&1))
2692                 emit_orimm(sl,imm[i],tl);
2693               else
2694                 emit_movimm(constmap[i][sl]|imm[i],tl);
2695             }
2696             if(opcode[i]==0x0e) //XORI
2697             if(sl<0) {
2698               emit_xorimm(tl,imm[i],tl);
2699             }else{
2700               if(!((i_regs->wasconst>>sl)&1))
2701                 emit_xorimm(sl,imm[i],tl);
2702               else
2703                 emit_movimm(constmap[i][sl]^imm[i],tl);
2704             }
2705           }
2706           else {
2707             emit_movimm(imm[i],tl);
2708             if(th>=0) emit_zeroreg(th);
2709           }
2710         }
2711       }
2712     }
2713   }
2714 }
2715
2716 void shiftimm_assemble(int i,struct regstat *i_regs)
2717 {
2718   if(opcode2[i]<=0x3) // SLL/SRL/SRA
2719   {
2720     if(rt1[i]) {
2721       signed char s,t;
2722       t=get_reg(i_regs->regmap,rt1[i]);
2723       s=get_reg(i_regs->regmap,rs1[i]);
2724       //assert(t>=0);
2725       if(t>=0&&!((i_regs->isconst>>t)&1)){
2726         if(rs1[i]==0)
2727         {
2728           emit_zeroreg(t);
2729         }
2730         else
2731         {
2732           if(s<0&&i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2733           if(imm[i]) {
2734             if(opcode2[i]==0) // SLL
2735             {
2736               emit_shlimm(s<0?t:s,imm[i],t);
2737             }
2738             if(opcode2[i]==2) // SRL
2739             {
2740               emit_shrimm(s<0?t:s,imm[i],t);
2741             }
2742             if(opcode2[i]==3) // SRA
2743             {
2744               emit_sarimm(s<0?t:s,imm[i],t);
2745             }
2746           }else{
2747             // Shift by zero
2748             if(s>=0 && s!=t) emit_mov(s,t);
2749           }
2750         }
2751       }
2752       //emit_storereg(rt1[i],t); //DEBUG
2753     }
2754   }
2755   if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA
2756   {
2757     if(rt1[i]) {
2758       signed char sh,sl,th,tl;
2759       th=get_reg(i_regs->regmap,rt1[i]|64);
2760       tl=get_reg(i_regs->regmap,rt1[i]);
2761       sh=get_reg(i_regs->regmap,rs1[i]|64);
2762       sl=get_reg(i_regs->regmap,rs1[i]);
2763       if(tl>=0) {
2764         if(rs1[i]==0)
2765         {
2766           emit_zeroreg(tl);
2767           if(th>=0) emit_zeroreg(th);
2768         }
2769         else
2770         {
2771           assert(sl>=0);
2772           assert(sh>=0);
2773           if(imm[i]) {
2774             if(opcode2[i]==0x38) // DSLL
2775             {
2776               if(th>=0) emit_shldimm(sh,sl,imm[i],th);
2777               emit_shlimm(sl,imm[i],tl);
2778             }
2779             if(opcode2[i]==0x3a) // DSRL
2780             {
2781               emit_shrdimm(sl,sh,imm[i],tl);
2782               if(th>=0) emit_shrimm(sh,imm[i],th);
2783             }
2784             if(opcode2[i]==0x3b) // DSRA
2785             {
2786               emit_shrdimm(sl,sh,imm[i],tl);
2787               if(th>=0) emit_sarimm(sh,imm[i],th);
2788             }
2789           }else{
2790             // Shift by zero
2791             if(sl!=tl) emit_mov(sl,tl);
2792             if(th>=0&&sh!=th) emit_mov(sh,th);
2793           }
2794         }
2795       }
2796     }
2797   }
2798   if(opcode2[i]==0x3c) // DSLL32
2799   {
2800     if(rt1[i]) {
2801       signed char sl,tl,th;
2802       tl=get_reg(i_regs->regmap,rt1[i]);
2803       th=get_reg(i_regs->regmap,rt1[i]|64);
2804       sl=get_reg(i_regs->regmap,rs1[i]);
2805       if(th>=0||tl>=0){
2806         assert(tl>=0);
2807         assert(th>=0);
2808         assert(sl>=0);
2809         emit_mov(sl,th);
2810         emit_zeroreg(tl);
2811         if(imm[i]>32)
2812         {
2813           emit_shlimm(th,imm[i]&31,th);
2814         }
2815       }
2816     }
2817   }
2818   if(opcode2[i]==0x3e) // DSRL32
2819   {
2820     if(rt1[i]) {
2821       signed char sh,tl,th;
2822       tl=get_reg(i_regs->regmap,rt1[i]);
2823       th=get_reg(i_regs->regmap,rt1[i]|64);
2824       sh=get_reg(i_regs->regmap,rs1[i]|64);
2825       if(tl>=0){
2826         assert(sh>=0);
2827         emit_mov(sh,tl);
2828         if(th>=0) emit_zeroreg(th);
2829         if(imm[i]>32)
2830         {
2831           emit_shrimm(tl,imm[i]&31,tl);
2832         }
2833       }
2834     }
2835   }
2836   if(opcode2[i]==0x3f) // DSRA32
2837   {
2838     if(rt1[i]) {
2839       signed char sh,tl;
2840       tl=get_reg(i_regs->regmap,rt1[i]);
2841       sh=get_reg(i_regs->regmap,rs1[i]|64);
2842       if(tl>=0){
2843         assert(sh>=0);
2844         emit_mov(sh,tl);
2845         if(imm[i]>32)
2846         {
2847           emit_sarimm(tl,imm[i]&31,tl);
2848         }
2849       }
2850     }
2851   }
2852 }
2853
2854 #ifndef shift_assemble
2855 void shift_assemble(int i,struct regstat *i_regs)
2856 {
2857   printf("Need shift_assemble for this architecture.\n");
2858   exit(1);
2859 }
2860 #endif
2861
2862 void load_assemble(int i,struct regstat *i_regs)
2863 {
2864   int s,th,tl,addr,map=-1;
2865   int offset;
2866   int jaddr=0;
2867   int memtarget=0,c=0;
2868   int fastload_reg_override=0;
2869   u_int hr,reglist=0;
2870   th=get_reg(i_regs->regmap,rt1[i]|64);
2871   tl=get_reg(i_regs->regmap,rt1[i]);
2872   s=get_reg(i_regs->regmap,rs1[i]);
2873   offset=imm[i];
2874   for(hr=0;hr<HOST_REGS;hr++) {
2875     if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
2876   }
2877   if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
2878   if(s>=0) {
2879     c=(i_regs->wasconst>>s)&1;
2880     if (c) {
2881       memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
2882       if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
2883     }
2884   }
2885   //printf("load_assemble: c=%d\n",c);
2886   //if(c) printf("load_assemble: const=%x\n",(int)constmap[i][s]+offset);
2887   // FIXME: Even if the load is a NOP, we should check for pagefaults...
2888 #ifdef PCSX
2889   if(tl<0&&(!c||(((u_int)constmap[i][s]+offset)>>16)==0x1f80)
2890     ||rt1[i]==0) {
2891       // could be FIFO, must perform the read
2892       // ||dummy read
2893       assem_debug("(forced read)\n");
2894       tl=get_reg(i_regs->regmap,-1);
2895       assert(tl>=0);
2896   }
2897 #endif
2898   if(offset||s<0||c) addr=tl;
2899   else addr=s;
2900   //if(tl<0) tl=get_reg(i_regs->regmap,-1);
2901  if(tl>=0) {
2902   //printf("load_assemble: c=%d\n",c);
2903   //if(c) printf("load_assemble: const=%x\n",(int)constmap[i][s]+offset);
2904   assert(tl>=0); // Even if the load is a NOP, we must check for pagefaults and I/O
2905   reglist&=~(1<<tl);
2906   if(th>=0) reglist&=~(1<<th);
2907   if(!using_tlb) {
2908     if(!c) {
2909       #ifdef RAM_OFFSET
2910       map=get_reg(i_regs->regmap,ROREG);
2911       if(map<0) emit_loadreg(ROREG,map=HOST_TEMPREG);
2912       #endif
2913 //#define R29_HACK 1
2914       #ifdef R29_HACK
2915       // Strmnnrmn's speed hack
2916       if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
2917       #endif
2918       {
2919         jaddr=emit_fastpath_cmp_jump(i,addr,&fastload_reg_override);
2920       }
2921     }
2922   }else{ // using tlb
2923     int x=0;
2924     if (opcode[i]==0x20||opcode[i]==0x24) x=3; // LB/LBU
2925     if (opcode[i]==0x21||opcode[i]==0x25) x=2; // LH/LHU
2926     map=get_reg(i_regs->regmap,TLREG);
2927     assert(map>=0);
2928     reglist&=~(1<<map);
2929     map=do_tlb_r(addr,tl,map,x,-1,-1,c,constmap[i][s]+offset);
2930     do_tlb_r_branch(map,c,constmap[i][s]+offset,&jaddr);
2931   }
2932   int dummy=(rt1[i]==0)||(tl!=get_reg(i_regs->regmap,rt1[i])); // ignore loads to r0 and unneeded reg
2933   if (opcode[i]==0x20) { // LB
2934     if(!c||memtarget) {
2935       if(!dummy) {
2936         #ifdef HOST_IMM_ADDR32
2937         if(c)
2938           emit_movsbl_tlb((constmap[i][s]+offset)^3,map,tl);
2939         else
2940         #endif
2941         {
2942           //emit_xorimm(addr,3,tl);
2943           //gen_tlb_addr_r(tl,map);
2944           //emit_movsbl_indexed((int)rdram-0x80000000,tl,tl);
2945           int x=0,a=tl;
2946 #ifdef BIG_ENDIAN_MIPS
2947           if(!c) emit_xorimm(addr,3,tl);
2948           else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2949 #else
2950           if(!c) a=addr;
2951 #endif
2952           if(fastload_reg_override) a=fastload_reg_override;
2953
2954           emit_movsbl_indexed_tlb(x,a,map,tl);
2955         }
2956       }
2957       if(jaddr)
2958         add_stub(LOADB_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2959     }
2960     else
2961       inline_readstub(LOADB_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2962   }
2963   if (opcode[i]==0x21) { // LH
2964     if(!c||memtarget) {
2965       if(!dummy) {
2966         #ifdef HOST_IMM_ADDR32
2967         if(c)
2968           emit_movswl_tlb((constmap[i][s]+offset)^2,map,tl);
2969         else
2970         #endif
2971         {
2972           int x=0,a=tl;
2973 #ifdef BIG_ENDIAN_MIPS
2974           if(!c) emit_xorimm(addr,2,tl);
2975           else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
2976 #else
2977           if(!c) a=addr;
2978 #endif
2979           if(fastload_reg_override) a=fastload_reg_override;
2980           //#ifdef
2981           //emit_movswl_indexed_tlb(x,tl,map,tl);
2982           //else
2983           if(map>=0) {
2984             gen_tlb_addr_r(a,map);
2985             emit_movswl_indexed(x,a,tl);
2986           }else{
2987             #ifdef RAM_OFFSET
2988             emit_movswl_indexed(x,a,tl);
2989             #else
2990             emit_movswl_indexed((int)rdram-0x80000000+x,a,tl);
2991             #endif
2992           }
2993         }
2994       }
2995       if(jaddr)
2996         add_stub(LOADH_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2997     }
2998     else
2999       inline_readstub(LOADH_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3000   }
3001   if (opcode[i]==0x23) { // LW
3002     if(!c||memtarget) {
3003       if(!dummy) {
3004         int a=addr;
3005         if(fastload_reg_override) a=fastload_reg_override;
3006         //emit_readword_indexed((int)rdram-0x80000000,addr,tl);
3007         #ifdef HOST_IMM_ADDR32
3008         if(c)
3009           emit_readword_tlb(constmap[i][s]+offset,map,tl);
3010         else
3011         #endif
3012         emit_readword_indexed_tlb(0,a,map,tl);
3013       }
3014       if(jaddr)
3015         add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3016     }
3017     else
3018       inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3019   }
3020   if (opcode[i]==0x24) { // LBU
3021     if(!c||memtarget) {
3022       if(!dummy) {
3023         #ifdef HOST_IMM_ADDR32
3024         if(c)
3025           emit_movzbl_tlb((constmap[i][s]+offset)^3,map,tl);
3026         else
3027         #endif
3028         {
3029           //emit_xorimm(addr,3,tl);
3030           //gen_tlb_addr_r(tl,map);
3031           //emit_movzbl_indexed((int)rdram-0x80000000,tl,tl);
3032           int x=0,a=tl;
3033 #ifdef BIG_ENDIAN_MIPS
3034           if(!c) emit_xorimm(addr,3,tl);
3035           else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
3036 #else
3037           if(!c) a=addr;
3038 #endif
3039           if(fastload_reg_override) a=fastload_reg_override;
3040
3041           emit_movzbl_indexed_tlb(x,a,map,tl);
3042         }
3043       }
3044       if(jaddr)
3045         add_stub(LOADBU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3046     }
3047     else
3048       inline_readstub(LOADBU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3049   }
3050   if (opcode[i]==0x25) { // LHU
3051     if(!c||memtarget) {
3052       if(!dummy) {
3053         #ifdef HOST_IMM_ADDR32
3054         if(c)
3055           emit_movzwl_tlb((constmap[i][s]+offset)^2,map,tl);
3056         else
3057         #endif
3058         {
3059           int x=0,a=tl;
3060 #ifdef BIG_ENDIAN_MIPS
3061           if(!c) emit_xorimm(addr,2,tl);
3062           else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
3063 #else
3064           if(!c) a=addr;
3065 #endif
3066           if(fastload_reg_override) a=fastload_reg_override;
3067           //#ifdef
3068           //emit_movzwl_indexed_tlb(x,tl,map,tl);
3069           //#else
3070           if(map>=0) {
3071             gen_tlb_addr_r(a,map);
3072             emit_movzwl_indexed(x,a,tl);
3073           }else{
3074             #ifdef RAM_OFFSET
3075             emit_movzwl_indexed(x,a,tl);
3076             #else
3077             emit_movzwl_indexed((int)rdram-0x80000000+x,a,tl);
3078             #endif
3079           }
3080         }
3081       }
3082       if(jaddr)
3083         add_stub(LOADHU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3084     }
3085     else
3086       inline_readstub(LOADHU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3087   }
3088   if (opcode[i]==0x27) { // LWU
3089     assert(th>=0);
3090     if(!c||memtarget) {
3091       if(!dummy) {
3092         int a=addr;
3093         if(fastload_reg_override) a=fastload_reg_override;
3094         //emit_readword_indexed((int)rdram-0x80000000,addr,tl);
3095         #ifdef HOST_IMM_ADDR32
3096         if(c)
3097           emit_readword_tlb(constmap[i][s]+offset,map,tl);
3098         else
3099         #endif
3100         emit_readword_indexed_tlb(0,a,map,tl);
3101       }
3102       if(jaddr)
3103         add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3104     }
3105     else {
3106       inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3107     }
3108     emit_zeroreg(th);
3109   }
3110   if (opcode[i]==0x37) { // LD
3111     if(!c||memtarget) {
3112       if(!dummy) {
3113         int a=addr;
3114         if(fastload_reg_override) a=fastload_reg_override;
3115         //gen_tlb_addr_r(tl,map);
3116         //if(th>=0) emit_readword_indexed((int)rdram-0x80000000,addr,th);
3117         //emit_readword_indexed((int)rdram-0x7FFFFFFC,addr,tl);
3118         #ifdef HOST_IMM_ADDR32
3119         if(c)
3120           emit_readdword_tlb(constmap[i][s]+offset,map,th,tl);
3121         else
3122         #endif
3123         emit_readdword_indexed_tlb(0,a,map,th,tl);
3124       }
3125       if(jaddr)
3126         add_stub(LOADD_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3127     }
3128     else
3129       inline_readstub(LOADD_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3130   }
3131  }
3132   //emit_storereg(rt1[i],tl); // DEBUG
3133   //if(opcode[i]==0x23)
3134   //if(opcode[i]==0x24)
3135   //if(opcode[i]==0x23||opcode[i]==0x24)
3136   /*if(opcode[i]==0x21||opcode[i]==0x23||opcode[i]==0x24)
3137   {
3138     //emit_pusha();
3139     save_regs(0x100f);
3140         emit_readword((int)&last_count,ECX);
3141         #ifdef __i386__
3142         if(get_reg(i_regs->regmap,CCREG)<0)
3143           emit_loadreg(CCREG,HOST_CCREG);
3144         emit_add(HOST_CCREG,ECX,HOST_CCREG);
3145         emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3146         emit_writeword(HOST_CCREG,(int)&Count);
3147         #endif
3148         #ifdef __arm__
3149         if(get_reg(i_regs->regmap,CCREG)<0)
3150           emit_loadreg(CCREG,0);
3151         else
3152           emit_mov(HOST_CCREG,0);
3153         emit_add(0,ECX,0);
3154         emit_addimm(0,2*ccadj[i],0);
3155         emit_writeword(0,(int)&Count);
3156         #endif
3157     emit_call((int)memdebug);
3158     //emit_popa();
3159     restore_regs(0x100f);
3160   }/**/
3161 }
3162
3163 #ifndef loadlr_assemble
3164 void loadlr_assemble(int i,struct regstat *i_regs)
3165 {
3166   printf("Need loadlr_assemble for this architecture.\n");
3167   exit(1);
3168 }
3169 #endif
3170
3171 void store_assemble(int i,struct regstat *i_regs)
3172 {
3173   int s,th,tl,map=-1;
3174   int addr,temp;
3175   int offset;
3176   int jaddr=0,jaddr2,type;
3177   int memtarget=0,c=0;
3178   int agr=AGEN1+(i&1);
3179   int faststore_reg_override=0;
3180   u_int hr,reglist=0;
3181   th=get_reg(i_regs->regmap,rs2[i]|64);
3182   tl=get_reg(i_regs->regmap,rs2[i]);
3183   s=get_reg(i_regs->regmap,rs1[i]);
3184   temp=get_reg(i_regs->regmap,agr);
3185   if(temp<0) temp=get_reg(i_regs->regmap,-1);
3186   offset=imm[i];
3187   if(s>=0) {
3188     c=(i_regs->wasconst>>s)&1;
3189     if(c) {
3190       memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
3191       if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
3192     }
3193   }
3194   assert(tl>=0);
3195   assert(temp>=0);
3196   for(hr=0;hr<HOST_REGS;hr++) {
3197     if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3198   }
3199   if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
3200   if(offset||s<0||c) addr=temp;
3201   else addr=s;
3202   if(!using_tlb) {
3203     if(!c) {
3204       #ifndef PCSX
3205       #ifdef R29_HACK
3206       // Strmnnrmn's speed hack
3207       if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
3208       #endif
3209       emit_cmpimm(addr,RAM_SIZE);
3210       #ifdef DESTRUCTIVE_SHIFT
3211       if(s==addr) emit_mov(s,temp);
3212       #endif
3213       #ifdef R29_HACK
3214       memtarget=1;
3215       if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
3216       #endif
3217       {
3218         jaddr=(int)out;
3219         #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
3220         // Hint to branch predictor that the branch is unlikely to be taken
3221         if(rs1[i]>=28)
3222           emit_jno_unlikely(0);
3223         else
3224         #endif
3225         emit_jno(0);
3226       }
3227       #else
3228         jaddr=emit_fastpath_cmp_jump(i,addr,&faststore_reg_override);
3229       #endif
3230     }
3231   }else{ // using tlb
3232     int x=0;
3233     if (opcode[i]==0x28) x=3; // SB
3234     if (opcode[i]==0x29) x=2; // SH
3235     map=get_reg(i_regs->regmap,TLREG);
3236     assert(map>=0);
3237     reglist&=~(1<<map);
3238     map=do_tlb_w(addr,temp,map,x,c,constmap[i][s]+offset);
3239     do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr);
3240   }
3241
3242   if (opcode[i]==0x28) { // SB
3243     if(!c||memtarget) {
3244       int x=0,a=temp;
3245 #ifdef BIG_ENDIAN_MIPS
3246       if(!c) emit_xorimm(addr,3,temp);
3247       else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
3248 #else
3249       if(!c) a=addr;
3250 #endif
3251       if(faststore_reg_override) a=faststore_reg_override;
3252       //gen_tlb_addr_w(temp,map);
3253       //emit_writebyte_indexed(tl,(int)rdram-0x80000000,temp);
3254       emit_writebyte_indexed_tlb(tl,x,a,map,a);
3255     }
3256     type=STOREB_STUB;
3257   }
3258   if (opcode[i]==0x29) { // SH
3259     if(!c||memtarget) {
3260       int x=0,a=temp;
3261 #ifdef BIG_ENDIAN_MIPS
3262       if(!c) emit_xorimm(addr,2,temp);
3263       else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
3264 #else
3265       if(!c) a=addr;
3266 #endif
3267       if(faststore_reg_override) a=faststore_reg_override;
3268       //#ifdef
3269       //emit_writehword_indexed_tlb(tl,x,temp,map,temp);
3270       //#else
3271       if(map>=0) {
3272         gen_tlb_addr_w(a,map);
3273         emit_writehword_indexed(tl,x,a);
3274       }else
3275         emit_writehword_indexed(tl,(int)rdram-0x80000000+x,a);
3276     }
3277     type=STOREH_STUB;
3278   }
3279   if (opcode[i]==0x2B) { // SW
3280     if(!c||memtarget) {
3281       int a=addr;
3282       if(faststore_reg_override) a=faststore_reg_override;
3283       //emit_writeword_indexed(tl,(int)rdram-0x80000000,addr);
3284       emit_writeword_indexed_tlb(tl,0,a,map,temp);
3285     }
3286     type=STOREW_STUB;
3287   }
3288   if (opcode[i]==0x3F) { // SD
3289     if(!c||memtarget) {
3290       int a=addr;
3291       if(faststore_reg_override) a=faststore_reg_override;
3292       if(rs2[i]) {
3293         assert(th>=0);
3294         //emit_writeword_indexed(th,(int)rdram-0x80000000,addr);
3295         //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,addr);
3296         emit_writedword_indexed_tlb(th,tl,0,a,map,temp);
3297       }else{
3298         // Store zero
3299         //emit_writeword_indexed(tl,(int)rdram-0x80000000,temp);
3300         //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,temp);
3301         emit_writedword_indexed_tlb(tl,tl,0,a,map,temp);
3302       }
3303     }
3304     type=STORED_STUB;
3305   }
3306 #ifdef PCSX
3307   if(jaddr) {
3308     // PCSX store handlers don't check invcode again
3309     reglist|=1<<addr;
3310     add_stub(type,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3311     jaddr=0;
3312   }
3313 #endif
3314   if(!using_tlb&&!(i_regs->waswritten&(1<<rs1[i]))&&!(new_dynarec_hacks&NDHACK_NO_SMC_CHECK)) {
3315     if(!c||memtarget) {
3316       #ifdef DESTRUCTIVE_SHIFT
3317       // The x86 shift operation is 'destructive'; it overwrites the
3318       // source register, so we need to make a copy first and use that.
3319       addr=temp;
3320       #endif
3321       #if defined(HOST_IMM8)
3322       int ir=get_reg(i_regs->regmap,INVCP);
3323       assert(ir>=0);
3324       emit_cmpmem_indexedsr12_reg(ir,addr,1);
3325       #else
3326       emit_cmpmem_indexedsr12_imm((int)invalid_code,addr,1);
3327       #endif
3328       #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3329       emit_callne(invalidate_addr_reg[addr]);
3330       #else
3331       jaddr2=(int)out;
3332       emit_jne(0);
3333       add_stub(INVCODE_STUB,jaddr2,(int)out,reglist|(1<<HOST_CCREG),addr,0,0,0);
3334       #endif
3335     }
3336   }
3337   if(jaddr) {
3338     add_stub(type,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3339   } else if(c&&!memtarget) {
3340     inline_writestub(type,i,constmap[i][s]+offset,i_regs->regmap,rs2[i],ccadj[i],reglist);
3341   }
3342   //if(opcode[i]==0x2B || opcode[i]==0x3F)
3343   //if(opcode[i]==0x2B || opcode[i]==0x28)
3344   //if(opcode[i]==0x2B || opcode[i]==0x29)
3345   //if(opcode[i]==0x2B)
3346   /*if(opcode[i]==0x2B || opcode[i]==0x28 || opcode[i]==0x29 || opcode[i]==0x3F)
3347   {
3348     #ifdef __i386__
3349     emit_pusha();
3350     #endif
3351     #ifdef __arm__
3352     save_regs(0x100f);
3353     #endif
3354         emit_readword((int)&last_count,ECX);
3355         #ifdef __i386__
3356         if(get_reg(i_regs->regmap,CCREG)<0)
3357           emit_loadreg(CCREG,HOST_CCREG);
3358         emit_add(HOST_CCREG,ECX,HOST_CCREG);
3359         emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3360         emit_writeword(HOST_CCREG,(int)&Count);
3361         #endif
3362         #ifdef __arm__
3363         if(get_reg(i_regs->regmap,CCREG)<0)
3364           emit_loadreg(CCREG,0);
3365         else
3366           emit_mov(HOST_CCREG,0);
3367         emit_add(0,ECX,0);
3368         emit_addimm(0,2*ccadj[i],0);
3369         emit_writeword(0,(int)&Count);
3370         #endif
3371     emit_call((int)memdebug);
3372     #ifdef __i386__
3373     emit_popa();
3374     #endif
3375     #ifdef __arm__
3376     restore_regs(0x100f);
3377     #endif
3378   }/**/
3379 }
3380
3381 void storelr_assemble(int i,struct regstat *i_regs)
3382 {
3383   int s,th,tl;
3384   int temp;
3385   int temp2;
3386   int offset;
3387   int jaddr=0,jaddr2;
3388   int case1,case2,case3;
3389   int done0,done1,done2;
3390   int memtarget=0,c=0;
3391   int agr=AGEN1+(i&1);
3392   u_int hr,reglist=0;
3393   th=get_reg(i_regs->regmap,rs2[i]|64);
3394   tl=get_reg(i_regs->regmap,rs2[i]);
3395   s=get_reg(i_regs->regmap,rs1[i]);
3396   temp=get_reg(i_regs->regmap,agr);
3397   if(temp<0) temp=get_reg(i_regs->regmap,-1);
3398   offset=imm[i];
3399   if(s>=0) {
3400     c=(i_regs->isconst>>s)&1;
3401     if(c) {
3402       memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
3403       if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
3404     }
3405   }
3406   assert(tl>=0);
3407   for(hr=0;hr<HOST_REGS;hr++) {
3408     if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3409   }
3410   assert(temp>=0);
3411   if(!using_tlb) {
3412     if(!c) {
3413       emit_cmpimm(s<0||offset?temp:s,RAM_SIZE);
3414       if(!offset&&s!=temp) emit_mov(s,temp);
3415       jaddr=(int)out;
3416       emit_jno(0);
3417     }
3418     else
3419     {
3420       if(!memtarget||!rs1[i]) {
3421         jaddr=(int)out;
3422         emit_jmp(0);
3423       }
3424     }
3425     #ifdef RAM_OFFSET
3426     int map=get_reg(i_regs->regmap,ROREG);
3427     if(map<0) emit_loadreg(ROREG,map=HOST_TEMPREG);
3428     gen_tlb_addr_w(temp,map);
3429     #else
3430     if((u_int)rdram!=0x80000000)
3431       emit_addimm_no_flags((u_int)rdram-(u_int)0x80000000,temp);
3432     #endif
3433   }else{ // using tlb
3434     int map=get_reg(i_regs->regmap,TLREG);
3435     assert(map>=0);
3436     reglist&=~(1<<map);
3437     map=do_tlb_w(c||s<0||offset?temp:s,temp,map,0,c,constmap[i][s]+offset);
3438     if(!c&&!offset&&s>=0) emit_mov(s,temp);
3439     do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr);
3440     if(!jaddr&&!memtarget) {
3441       jaddr=(int)out;
3442       emit_jmp(0);
3443     }
3444     gen_tlb_addr_w(temp,map);
3445   }
3446
3447   if (opcode[i]==0x2C||opcode[i]==0x2D) { // SDL/SDR
3448     temp2=get_reg(i_regs->regmap,FTEMP);
3449     if(!rs2[i]) temp2=th=tl;
3450   }
3451
3452 #ifndef BIG_ENDIAN_MIPS
3453     emit_xorimm(temp,3,temp);
3454 #endif
3455   emit_testimm(temp,2);
3456   case2=(int)out;
3457   emit_jne(0);
3458   emit_testimm(temp,1);
3459   case1=(int)out;
3460   emit_jne(0);
3461   // 0
3462   if (opcode[i]==0x2A) { // SWL
3463     emit_writeword_indexed(tl,0,temp);
3464   }
3465   if (opcode[i]==0x2E) { // SWR
3466     emit_writebyte_indexed(tl,3,temp);
3467   }
3468   if (opcode[i]==0x2C) { // SDL
3469     emit_writeword_indexed(th,0,temp);
3470     if(rs2[i]) emit_mov(tl,temp2);
3471   }
3472   if (opcode[i]==0x2D) { // SDR
3473     emit_writebyte_indexed(tl,3,temp);
3474     if(rs2[i]) emit_shldimm(th,tl,24,temp2);
3475   }
3476   done0=(int)out;
3477   emit_jmp(0);
3478   // 1
3479   set_jump_target(case1,(int)out);
3480   if (opcode[i]==0x2A) { // SWL
3481     // Write 3 msb into three least significant bytes
3482     if(rs2[i]) emit_rorimm(tl,8,tl);
3483     emit_writehword_indexed(tl,-1,temp);
3484     if(rs2[i]) emit_rorimm(tl,16,tl);
3485     emit_writebyte_indexed(tl,1,temp);
3486     if(rs2[i]) emit_rorimm(tl,8,tl);
3487   }
3488   if (opcode[i]==0x2E) { // SWR
3489     // Write two lsb into two most significant bytes
3490     emit_writehword_indexed(tl,1,temp);
3491   }
3492   if (opcode[i]==0x2C) { // SDL
3493     if(rs2[i]) emit_shrdimm(tl,th,8,temp2);
3494     // Write 3 msb into three least significant bytes
3495     if(rs2[i]) emit_rorimm(th,8,th);
3496     emit_writehword_indexed(th,-1,temp);
3497     if(rs2[i]) emit_rorimm(th,16,th);
3498     emit_writebyte_indexed(th,1,temp);
3499     if(rs2[i]) emit_rorimm(th,8,th);
3500   }
3501   if (opcode[i]==0x2D) { // SDR
3502     if(rs2[i]) emit_shldimm(th,tl,16,temp2);
3503     // Write two lsb into two most significant bytes
3504     emit_writehword_indexed(tl,1,temp);
3505   }
3506   done1=(int)out;
3507   emit_jmp(0);
3508   // 2
3509   set_jump_target(case2,(int)out);
3510   emit_testimm(temp,1);
3511   case3=(int)out;
3512   emit_jne(0);
3513   if (opcode[i]==0x2A) { // SWL
3514     // Write two msb into two least significant bytes
3515     if(rs2[i]) emit_rorimm(tl,16,tl);
3516     emit_writehword_indexed(tl,-2,temp);
3517     if(rs2[i]) emit_rorimm(tl,16,tl);
3518   }
3519   if (opcode[i]==0x2E) { // SWR
3520     // Write 3 lsb into three most significant bytes
3521     emit_writebyte_indexed(tl,-1,temp);
3522     if(rs2[i]) emit_rorimm(tl,8,tl);
3523     emit_writehword_indexed(tl,0,temp);
3524     if(rs2[i]) emit_rorimm(tl,24,tl);
3525   }
3526   if (opcode[i]==0x2C) { // SDL
3527     if(rs2[i]) emit_shrdimm(tl,th,16,temp2);
3528     // Write two msb into two least significant bytes
3529     if(rs2[i]) emit_rorimm(th,16,th);
3530     emit_writehword_indexed(th,-2,temp);
3531     if(rs2[i]) emit_rorimm(th,16,th);
3532   }
3533   if (opcode[i]==0x2D) { // SDR
3534     if(rs2[i]) emit_shldimm(th,tl,8,temp2);
3535     // Write 3 lsb into three most significant bytes
3536     emit_writebyte_indexed(tl,-1,temp);
3537     if(rs2[i]) emit_rorimm(tl,8,tl);
3538     emit_writehword_indexed(tl,0,temp);
3539     if(rs2[i]) emit_rorimm(tl,24,tl);
3540   }
3541   done2=(int)out;
3542   emit_jmp(0);
3543   // 3
3544   set_jump_target(case3,(int)out);
3545   if (opcode[i]==0x2A) { // SWL
3546     // Write msb into least significant byte
3547     if(rs2[i]) emit_rorimm(tl,24,tl);
3548     emit_writebyte_indexed(tl,-3,temp);
3549     if(rs2[i]) emit_rorimm(tl,8,tl);
3550   }
3551   if (opcode[i]==0x2E) { // SWR
3552     // Write entire word
3553     emit_writeword_indexed(tl,-3,temp);
3554   }
3555   if (opcode[i]==0x2C) { // SDL
3556     if(rs2[i]) emit_shrdimm(tl,th,24,temp2);
3557     // Write msb into least significant byte
3558     if(rs2[i]) emit_rorimm(th,24,th);
3559     emit_writebyte_indexed(th,-3,temp);
3560     if(rs2[i]) emit_rorimm(th,8,th);
3561   }
3562   if (opcode[i]==0x2D) { // SDR
3563     if(rs2[i]) emit_mov(th,temp2);
3564     // Write entire word
3565     emit_writeword_indexed(tl,-3,temp);
3566   }
3567   set_jump_target(done0,(int)out);
3568   set_jump_target(done1,(int)out);
3569   set_jump_target(done2,(int)out);
3570   if (opcode[i]==0x2C) { // SDL
3571     emit_testimm(temp,4);
3572     done0=(int)out;
3573     emit_jne(0);
3574     emit_andimm(temp,~3,temp);
3575     emit_writeword_indexed(temp2,4,temp);
3576     set_jump_target(done0,(int)out);
3577   }
3578   if (opcode[i]==0x2D) { // SDR
3579     emit_testimm(temp,4);
3580     done0=(int)out;
3581     emit_jeq(0);
3582     emit_andimm(temp,~3,temp);
3583     emit_writeword_indexed(temp2,-4,temp);
3584     set_jump_target(done0,(int)out);
3585   }
3586   if(!c||!memtarget)
3587     add_stub(STORELR_STUB,jaddr,(int)out,i,(int)i_regs,temp,ccadj[i],reglist);
3588   if(!using_tlb&&!(i_regs->waswritten&(1<<rs1[i]))&&!(new_dynarec_hacks&NDHACK_NO_SMC_CHECK)) {
3589     #ifdef RAM_OFFSET
3590     int map=get_reg(i_regs->regmap,ROREG);
3591     if(map<0) map=HOST_TEMPREG;
3592     gen_orig_addr_w(temp,map);
3593     #else
3594     emit_addimm_no_flags((u_int)0x80000000-(u_int)rdram,temp);
3595     #endif
3596     #if defined(HOST_IMM8)
3597     int ir=get_reg(i_regs->regmap,INVCP);
3598     assert(ir>=0);
3599     emit_cmpmem_indexedsr12_reg(ir,temp,1);
3600     #else
3601     emit_cmpmem_indexedsr12_imm((int)invalid_code,temp,1);
3602     #endif
3603     #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3604     emit_callne(invalidate_addr_reg[temp]);
3605     #else
3606     jaddr2=(int)out;
3607     emit_jne(0);
3608     add_stub(INVCODE_STUB,jaddr2,(int)out,reglist|(1<<HOST_CCREG),temp,0,0,0);
3609     #endif
3610   }
3611   /*
3612     emit_pusha();
3613     //save_regs(0x100f);
3614         emit_readword((int)&last_count,ECX);
3615         if(get_reg(i_regs->regmap,CCREG)<0)
3616           emit_loadreg(CCREG,HOST_CCREG);
3617         emit_add(HOST_CCREG,ECX,HOST_CCREG);
3618         emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3619         emit_writeword(HOST_CCREG,(int)&Count);
3620     emit_call((int)memdebug);
3621     emit_popa();
3622     //restore_regs(0x100f);
3623   /**/
3624 }
3625
3626 void c1ls_assemble(int i,struct regstat *i_regs)
3627 {
3628 #ifndef DISABLE_COP1
3629   int s,th,tl;
3630   int temp,ar;
3631   int map=-1;
3632   int offset;
3633   int c=0;
3634   int jaddr,jaddr2=0,jaddr3,type;
3635   int agr=AGEN1+(i&1);
3636   u_int hr,reglist=0;
3637   th=get_reg(i_regs->regmap,FTEMP|64);
3638   tl=get_reg(i_regs->regmap,FTEMP);
3639   s=get_reg(i_regs->regmap,rs1[i]);
3640   temp=get_reg(i_regs->regmap,agr);
3641   if(temp<0) temp=get_reg(i_regs->regmap,-1);
3642   offset=imm[i];
3643   assert(tl>=0);
3644   assert(rs1[i]>0);
3645   assert(temp>=0);
3646   for(hr=0;hr<HOST_REGS;hr++) {
3647     if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3648   }
3649   if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
3650   if (opcode[i]==0x31||opcode[i]==0x35) // LWC1/LDC1
3651   {
3652     // Loads use a temporary register which we need to save
3653     reglist|=1<<temp;
3654   }
3655   if (opcode[i]==0x39||opcode[i]==0x3D) // SWC1/SDC1
3656     ar=temp;
3657   else // LWC1/LDC1
3658     ar=tl;
3659   //if(s<0) emit_loadreg(rs1[i],ar); //address_generation does this now
3660   //else c=(i_regs->wasconst>>s)&1;
3661   if(s>=0) c=(i_regs->wasconst>>s)&1;
3662   // Check cop1 unusable
3663   if(!cop1_usable) {
3664     signed char rs=get_reg(i_regs->regmap,CSREG);
3665     assert(rs>=0);
3666     emit_testimm(rs,0x20000000);
3667     jaddr=(int)out;
3668     emit_jeq(0);
3669     add_stub(FP_STUB,jaddr,(int)out,i,rs,(int)i_regs,is_delayslot,0);
3670     cop1_usable=1;
3671   }
3672   if (opcode[i]==0x39) { // SWC1 (get float address)
3673     emit_readword((int)&reg_cop1_simple[(source[i]>>16)&0x1f],tl);
3674   }
3675   if (opcode[i]==0x3D) { // SDC1 (get double address)
3676     emit_readword((int)&reg_cop1_double[(source[i]>>16)&0x1f],tl);
3677   }
3678   // Generate address + offset
3679   if(!using_tlb) {
3680     if(!c)
3681       emit_cmpimm(offset||c||s<0?ar:s,RAM_SIZE);
3682   }
3683   else
3684   {
3685     map=get_reg(i_regs->regmap,TLREG);
3686     assert(map>=0);
3687     reglist&=~(1<<map);
3688     if (opcode[i]==0x31||opcode[i]==0x35) { // LWC1/LDC1
3689       map=do_tlb_r(offset||c||s<0?ar:s,ar,map,0,-1,-1,c,constmap[i][s]+offset);
3690     }
3691     if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3692       map=do_tlb_w(offset||c||s<0?ar:s,ar,map,0,c,constmap[i][s]+offset);
3693     }
3694   }
3695   if (opcode[i]==0x39) { // SWC1 (read float)
3696     emit_readword_indexed(0,tl,tl);
3697   }
3698   if (opcode[i]==0x3D) { // SDC1 (read double)
3699     emit_readword_indexed(4,tl,th);
3700     emit_readword_indexed(0,tl,tl);
3701   }
3702   if (opcode[i]==0x31) { // LWC1 (get target address)
3703     emit_readword((int)&reg_cop1_simple[(source[i]>>16)&0x1f],temp);
3704   }
3705   if (opcode[i]==0x35) { // LDC1 (get target address)
3706     emit_readword((int)&reg_cop1_double[(source[i]>>16)&0x1f],temp);
3707   }
3708   if(!using_tlb) {
3709     if(!c) {
3710       jaddr2=(int)out;
3711       emit_jno(0);
3712     }
3713     else if(((signed int)(constmap[i][s]+offset))>=(signed int)0x80000000+RAM_SIZE) {
3714       jaddr2=(int)out;
3715       emit_jmp(0); // inline_readstub/inline_writestub?  Very rare case
3716     }
3717     #ifdef DESTRUCTIVE_SHIFT
3718     if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3719       if(!offset&&!c&&s>=0) emit_mov(s,ar);
3720     }
3721     #endif
3722   }else{
3723     if (opcode[i]==0x31||opcode[i]==0x35) { // LWC1/LDC1
3724       do_tlb_r_branch(map,c,constmap[i][s]+offset,&jaddr2);
3725     }
3726     if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3727       do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr2);
3728     }
3729   }
3730   if (opcode[i]==0x31) { // LWC1
3731     //if(s>=0&&!c&&!offset) emit_mov(s,tl);
3732     //gen_tlb_addr_r(ar,map);
3733     //emit_readword_indexed((int)rdram-0x80000000,tl,tl);
3734     #ifdef HOST_IMM_ADDR32
3735     if(c) emit_readword_tlb(constmap[i][s]+offset,map,tl);
3736     else
3737     #endif
3738     emit_readword_indexed_tlb(0,offset||c||s<0?tl:s,map,tl);
3739     type=LOADW_STUB;
3740   }
3741   if (opcode[i]==0x35) { // LDC1
3742     assert(th>=0);
3743     //if(s>=0&&!c&&!offset) emit_mov(s,tl);
3744     //gen_tlb_addr_r(ar,map);
3745     //emit_readword_indexed((int)rdram-0x80000000,tl,th);
3746     //emit_readword_indexed((int)rdram-0x7FFFFFFC,tl,tl);
3747     #ifdef HOST_IMM_ADDR32
3748     if(c) emit_readdword_tlb(constmap[i][s]+offset,map,th,tl);
3749     else
3750     #endif
3751     emit_readdword_indexed_tlb(0,offset||c||s<0?tl:s,map,th,tl);
3752     type=LOADD_STUB;
3753   }
3754   if (opcode[i]==0x39) { // SWC1
3755     //emit_writeword_indexed(tl,(int)rdram-0x80000000,temp);
3756     emit_writeword_indexed_tlb(tl,0,offset||c||s<0?temp:s,map,temp);
3757     type=STOREW_STUB;
3758   }
3759   if (opcode[i]==0x3D) { // SDC1
3760     assert(th>=0);
3761     //emit_writeword_indexed(th,(int)rdram-0x80000000,temp);
3762     //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,temp);
3763     emit_writedword_indexed_tlb(th,tl,0,offset||c||s<0?temp:s,map,temp);
3764     type=STORED_STUB;
3765   }
3766   if(!using_tlb&&!(i_regs->waswritten&(1<<rs1[i]))&&!(new_dynarec_hacks&NDHACK_NO_SMC_CHECK)) {
3767     if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3768       #ifndef DESTRUCTIVE_SHIFT
3769       temp=offset||c||s<0?ar:s;
3770       #endif
3771       #if defined(HOST_IMM8)
3772       int ir=get_reg(i_regs->regmap,INVCP);
3773       assert(ir>=0);
3774       emit_cmpmem_indexedsr12_reg(ir,temp,1);
3775       #else
3776       emit_cmpmem_indexedsr12_imm((int)invalid_code,temp,1);
3777       #endif
3778       #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3779       emit_callne(invalidate_addr_reg[temp]);
3780       #else
3781       jaddr3=(int)out;
3782       emit_jne(0);
3783       add_stub(INVCODE_STUB,jaddr3,(int)out,reglist|(1<<HOST_CCREG),temp,0,0,0);
3784       #endif
3785     }
3786   }
3787   if(jaddr2) add_stub(type,jaddr2,(int)out,i,offset||c||s<0?ar:s,(int)i_regs,ccadj[i],reglist);
3788   if (opcode[i]==0x31) { // LWC1 (write float)
3789     emit_writeword_indexed(tl,0,temp);
3790   }
3791   if (opcode[i]==0x35) { // LDC1 (write double)
3792     emit_writeword_indexed(th,4,temp);
3793     emit_writeword_indexed(tl,0,temp);
3794   }
3795   //if(opcode[i]==0x39)
3796   /*if(opcode[i]==0x39||opcode[i]==0x31)
3797   {
3798     emit_pusha();
3799         emit_readword((int)&last_count,ECX);
3800         if(get_reg(i_regs->regmap,CCREG)<0)
3801           emit_loadreg(CCREG,HOST_CCREG);
3802         emit_add(HOST_CCREG,ECX,HOST_CCREG);
3803         emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3804         emit_writeword(HOST_CCREG,(int)&Count);
3805     emit_call((int)memdebug);
3806     emit_popa();
3807   }/**/
3808 #else
3809   cop1_unusable(i, i_regs);
3810 #endif
3811 }
3812
3813 void c2ls_assemble(int i,struct regstat *i_regs)
3814 {
3815   int s,tl;
3816   int ar;
3817   int offset;
3818   int memtarget=0,c=0;
3819   int jaddr2=0,jaddr3,type;
3820   int agr=AGEN1+(i&1);
3821   int fastio_reg_override=0;
3822   u_int hr,reglist=0;
3823   u_int copr=(source[i]>>16)&0x1f;
3824   s=get_reg(i_regs->regmap,rs1[i]);
3825   tl=get_reg(i_regs->regmap,FTEMP);
3826   offset=imm[i];
3827   assert(rs1[i]>0);
3828   assert(tl>=0);
3829   assert(!using_tlb);
3830
3831   for(hr=0;hr<HOST_REGS;hr++) {
3832     if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3833   }
3834   if(i_regs->regmap[HOST_CCREG]==CCREG)
3835     reglist&=~(1<<HOST_CCREG);
3836
3837   // get the address
3838   if (opcode[i]==0x3a) { // SWC2
3839     ar=get_reg(i_regs->regmap,agr);
3840     if(ar<0) ar=get_reg(i_regs->regmap,-1);
3841     reglist|=1<<ar;
3842   } else { // LWC2
3843     ar=tl;
3844   }
3845   if(s>=0) c=(i_regs->wasconst>>s)&1;
3846   memtarget=c&&(((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE);
3847   if (!offset&&!c&&s>=0) ar=s;
3848   assert(ar>=0);
3849
3850   if (opcode[i]==0x3a) { // SWC2
3851     cop2_get_dreg(copr,tl,HOST_TEMPREG);
3852     type=STOREW_STUB;
3853   }
3854   else
3855     type=LOADW_STUB;
3856
3857   if(c&&!memtarget) {
3858     jaddr2=(int)out;
3859     emit_jmp(0); // inline_readstub/inline_writestub?
3860   }
3861   else {
3862     if(!c) {
3863       jaddr2=emit_fastpath_cmp_jump(i,ar,&fastio_reg_override);
3864     }
3865     if (opcode[i]==0x32) { // LWC2
3866       #ifdef HOST_IMM_ADDR32
3867       if(c) emit_readword_tlb(constmap[i][s]+offset,-1,tl);
3868       else
3869       #endif
3870       int a=ar;
3871       if(fastio_reg_override) a=fastio_reg_override;
3872       emit_readword_indexed(0,a,tl);
3873     }
3874     if (opcode[i]==0x3a) { // SWC2
3875       #ifdef DESTRUCTIVE_SHIFT
3876       if(!offset&&!c&&s>=0) emit_mov(s,ar);
3877       #endif
3878       int a=ar;
3879       if(fastio_reg_override) a=fastio_reg_override;
3880       emit_writeword_indexed(tl,0,a);
3881     }
3882   }
3883   if(jaddr2)
3884     add_stub(type,jaddr2,(int)out,i,ar,(int)i_regs,ccadj[i],reglist);
3885   if(opcode[i]==0x3a) // SWC2
3886   if(!(i_regs->waswritten&(1<<rs1[i]))&&!(new_dynarec_hacks&NDHACK_NO_SMC_CHECK)) {
3887 #if defined(HOST_IMM8)
3888     int ir=get_reg(i_regs->regmap,INVCP);
3889     assert(ir>=0);
3890     emit_cmpmem_indexedsr12_reg(ir,ar,1);
3891 #else
3892     emit_cmpmem_indexedsr12_imm((int)invalid_code,ar,1);
3893 #endif
3894     #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3895     emit_callne(invalidate_addr_reg[ar]);
3896     #else
3897     jaddr3=(int)out;
3898     emit_jne(0);
3899     add_stub(INVCODE_STUB,jaddr3,(int)out,reglist|(1<<HOST_CCREG),ar,0,0,0);
3900     #endif
3901   }
3902   if (opcode[i]==0x32) { // LWC2
3903     cop2_put_dreg(copr,tl,HOST_TEMPREG);
3904   }
3905 }
3906
3907 #ifndef multdiv_assemble
3908 void multdiv_assemble(int i,struct regstat *i_regs)
3909 {
3910   printf("Need multdiv_assemble for this architecture.\n");
3911   exit(1);
3912 }
3913 #endif
3914
3915 void mov_assemble(int i,struct regstat *i_regs)
3916 {
3917   //if(opcode2[i]==0x10||opcode2[i]==0x12) { // MFHI/MFLO
3918   //if(opcode2[i]==0x11||opcode2[i]==0x13) { // MTHI/MTLO
3919   if(rt1[i]) {
3920     signed char sh,sl,th,tl;
3921     th=get_reg(i_regs->regmap,rt1[i]|64);
3922     tl=get_reg(i_regs->regmap,rt1[i]);
3923     //assert(tl>=0);
3924     if(tl>=0) {
3925       sh=get_reg(i_regs->regmap,rs1[i]|64);
3926       sl=get_reg(i_regs->regmap,rs1[i]);
3927       if(sl>=0) emit_mov(sl,tl);
3928       else emit_loadreg(rs1[i],tl);
3929       if(th>=0) {
3930         if(sh>=0) emit_mov(sh,th);
3931         else emit_loadreg(rs1[i]|64,th);
3932       }
3933     }
3934   }
3935 }
3936
3937 #ifndef fconv_assemble
3938 void fconv_assemble(int i,struct regstat *i_regs)
3939 {
3940   printf("Need fconv_assemble for this architecture.\n");
3941   exit(1);
3942 }
3943 #endif
3944
3945 #if 0
3946 void float_assemble(int i,struct regstat *i_regs)
3947 {
3948   printf("Need float_assemble for this architecture.\n");
3949   exit(1);
3950 }
3951 #endif
3952
3953 void syscall_assemble(int i,struct regstat *i_regs)
3954 {
3955   signed char ccreg=get_reg(i_regs->regmap,CCREG);
3956   assert(ccreg==HOST_CCREG);
3957   assert(!is_delayslot);
3958   emit_movimm(start+i*4,EAX); // Get PC
3959   emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i]),HOST_CCREG); // CHECK: is this right?  There should probably be an extra cycle...
3960   emit_jmp((int)jump_syscall_hle); // XXX
3961 }
3962
3963 void hlecall_assemble(int i,struct regstat *i_regs)
3964 {
3965   signed char ccreg=get_reg(i_regs->regmap,CCREG);
3966   assert(ccreg==HOST_CCREG);
3967   assert(!is_delayslot);
3968   emit_movimm(start+i*4+4,0); // Get PC
3969   emit_movimm((int)psxHLEt[source[i]&7],1);
3970   emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i]),HOST_CCREG); // XXX
3971   emit_jmp((int)jump_hlecall);
3972 }
3973
3974 void intcall_assemble(int i,struct regstat *i_regs)
3975 {
3976   signed char ccreg=get_reg(i_regs->regmap,CCREG);
3977   assert(ccreg==HOST_CCREG);
3978   assert(!is_delayslot);
3979   emit_movimm(start+i*4,0); // Get PC
3980   emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i]),HOST_CCREG);
3981   emit_jmp((int)jump_intcall);
3982 }
3983
3984 void ds_assemble(int i,struct regstat *i_regs)
3985 {
3986   speculate_register_values(i);
3987   is_delayslot=1;
3988   switch(itype[i]) {
3989     case ALU:
3990       alu_assemble(i,i_regs);break;
3991     case IMM16:
3992       imm16_assemble(i,i_regs);break;
3993     case SHIFT:
3994       shift_assemble(i,i_regs);break;
3995     case SHIFTIMM:
3996       shiftimm_assemble(i,i_regs);break;
3997     case LOAD:
3998       load_assemble(i,i_regs);break;
3999     case LOADLR:
4000       loadlr_assemble(i,i_regs);break;
4001     case STORE:
4002       store_assemble(i,i_regs);break;
4003     case STORELR:
4004       storelr_assemble(i,i_regs);break;
4005     case COP0:
4006       cop0_assemble(i,i_regs);break;
4007     case COP1:
4008       cop1_assemble(i,i_regs);break;
4009     case C1LS:
4010       c1ls_assemble(i,i_regs);break;
4011     case COP2:
4012       cop2_assemble(i,i_regs);break;
4013     case C2LS:
4014       c2ls_assemble(i,i_regs);break;
4015     case C2OP:
4016       c2op_assemble(i,i_regs);break;
4017     case FCONV:
4018       fconv_assemble(i,i_regs);break;
4019     case FLOAT:
4020       float_assemble(i,i_regs);break;
4021     case FCOMP:
4022       fcomp_assemble(i,i_regs);break;
4023     case MULTDIV:
4024       multdiv_assemble(i,i_regs);break;
4025     case MOV:
4026       mov_assemble(i,i_regs);break;
4027     case SYSCALL:
4028     case HLECALL:
4029     case INTCALL:
4030     case SPAN:
4031     case UJUMP:
4032     case RJUMP:
4033     case CJUMP:
4034     case SJUMP:
4035     case FJUMP:
4036       printf("Jump in the delay slot.  This is probably a bug.\n");
4037   }
4038   is_delayslot=0;
4039 }
4040
4041 // Is the branch target a valid internal jump?
4042 int internal_branch(uint64_t i_is32,int addr)
4043 {
4044   if(addr&1) return 0; // Indirect (register) jump
4045   if(addr>=start && addr<start+slen*4-4)
4046   {
4047     int t=(addr-start)>>2;
4048     // Delay slots are not valid branch targets
4049     //if(t>0&&(itype[t-1]==RJUMP||itype[t-1]==UJUMP||itype[t-1]==CJUMP||itype[t-1]==SJUMP||itype[t-1]==FJUMP)) return 0;
4050     // 64 -> 32 bit transition requires a recompile
4051     /*if(is32[t]&~unneeded_reg_upper[t]&~i_is32)
4052     {
4053       if(requires_32bit[t]&~i_is32) printf("optimizable: no\n");
4054       else printf("optimizable: yes\n");
4055     }*/
4056     //if(is32[t]&~unneeded_reg_upper[t]&~i_is32) return 0;
4057 #ifndef FORCE32
4058     if(requires_32bit[t]&~i_is32) return 0;
4059     else
4060 #endif
4061       return 1;
4062   }
4063   return 0;
4064 }
4065
4066 #ifndef wb_invalidate
4067 void wb_invalidate(signed char pre[],signed char entry[],uint64_t dirty,uint64_t is32,
4068   uint64_t u,uint64_t uu)
4069 {
4070   int hr;
4071   for(hr=0;hr<HOST_REGS;hr++) {
4072     if(hr!=EXCLUDE_REG) {
4073       if(pre[hr]!=entry[hr]) {
4074         if(pre[hr]>=0) {
4075           if((dirty>>hr)&1) {
4076             if(get_reg(entry,pre[hr])<0) {
4077               if(pre[hr]<64) {
4078                 if(!((u>>pre[hr])&1)) {
4079                   emit_storereg(pre[hr],hr);
4080                   if( ((is32>>pre[hr])&1) && !((uu>>pre[hr])&1) ) {
4081                     emit_sarimm(hr,31,hr);
4082                     emit_storereg(pre[hr]|64,hr);
4083                   }
4084                 }
4085               }else{
4086                 if(!((uu>>(pre[hr]&63))&1) && !((is32>>(pre[hr]&63))&1)) {
4087                   emit_storereg(pre[hr],hr);
4088                 }
4089               }
4090             }
4091           }
4092         }
4093       }
4094     }
4095   }
4096   // Move from one register to another (no writeback)
4097   for(hr=0;hr<HOST_REGS;hr++) {
4098     if(hr!=EXCLUDE_REG) {
4099       if(pre[hr]!=entry[hr]) {
4100         if(pre[hr]>=0&&(pre[hr]&63)<TEMPREG) {
4101           int nr;
4102           if((nr=get_reg(entry,pre[hr]))>=0) {
4103             emit_mov(hr,nr);
4104           }
4105         }
4106       }
4107     }
4108   }
4109 }
4110 #endif
4111
4112 // Load the specified registers
4113 // This only loads the registers given as arguments because
4114 // we don't want to load things that will be overwritten
4115 void load_regs(signed char entry[],signed char regmap[],int is32,int rs1,int rs2)
4116 {
4117   int hr;
4118   // Load 32-bit regs
4119   for(hr=0;hr<HOST_REGS;hr++) {
4120     if(hr!=EXCLUDE_REG&&regmap[hr]>=0) {
4121       if(entry[hr]!=regmap[hr]) {
4122         if(regmap[hr]==rs1||regmap[hr]==rs2)
4123         {
4124           if(regmap[hr]==0) {
4125             emit_zeroreg(hr);
4126           }
4127           else
4128           {
4129             emit_loadreg(regmap[hr],hr);
4130           }
4131         }
4132       }
4133     }
4134   }
4135   //Load 64-bit regs
4136   for(hr=0;hr<HOST_REGS;hr++) {
4137     if(hr!=EXCLUDE_REG&&regmap[hr]>=0) {
4138       if(entry[hr]!=regmap[hr]) {
4139         if(regmap[hr]-64==rs1||regmap[hr]-64==rs2)
4140         {
4141           assert(regmap[hr]!=64);
4142           if((is32>>(regmap[hr]&63))&1) {
4143             int lr=get_reg(regmap,regmap[hr]-64);
4144             if(lr>=0)
4145               emit_sarimm(lr,31,hr);
4146             else
4147               emit_loadreg(regmap[hr],hr);
4148           }
4149           else
4150           {
4151             emit_loadreg(regmap[hr],hr);
4152           }
4153         }
4154       }
4155     }
4156   }
4157 }
4158
4159 // Load registers prior to the start of a loop
4160 // so that they are not loaded within the loop
4161 static void loop_preload(signed char pre[],signed char entry[])
4162 {
4163   int hr;
4164   for(hr=0;hr<HOST_REGS;hr++) {
4165     if(hr!=EXCLUDE_REG) {
4166       if(pre[hr]!=entry[hr]) {
4167         if(entry[hr]>=0) {
4168           if(get_reg(pre,entry[hr])<0) {
4169             assem_debug("loop preload:\n");
4170             //printf("loop preload: %d\n",hr);
4171             if(entry[hr]==0) {
4172               emit_zeroreg(hr);
4173             }
4174             else if(entry[hr]<TEMPREG)
4175             {
4176               emit_loadreg(entry[hr],hr);
4177             }
4178             else if(entry[hr]-64<TEMPREG)
4179             {
4180               emit_loadreg(entry[hr],hr);
4181             }
4182           }
4183         }
4184       }
4185     }
4186   }
4187 }
4188
4189 // Generate address for load/store instruction
4190 // goes to AGEN for writes, FTEMP for LOADLR and cop1/2 loads
4191 void address_generation(int i,struct regstat *i_regs,signed char entry[])
4192 {
4193   if(itype[i]==LOAD||itype[i]==LOADLR||itype[i]==STORE||itype[i]==STORELR||itype[i]==C1LS||itype[i]==C2LS) {
4194     int ra=-1;
4195     int agr=AGEN1+(i&1);
4196     int mgr=MGEN1+(i&1);
4197     if(itype[i]==LOAD) {
4198       ra=get_reg(i_regs->regmap,rt1[i]);
4199       if(ra<0) ra=get_reg(i_regs->regmap,-1);
4200       assert(ra>=0);
4201     }
4202     if(itype[i]==LOADLR) {
4203       ra=get_reg(i_regs->regmap,FTEMP);
4204     }
4205     if(itype[i]==STORE||itype[i]==STORELR) {
4206       ra=get_reg(i_regs->regmap,agr);
4207       if(ra<0) ra=get_reg(i_regs->regmap,-1);
4208     }
4209     if(itype[i]==C1LS||itype[i]==C2LS) {
4210       if ((opcode[i]&0x3b)==0x31||(opcode[i]&0x3b)==0x32) // LWC1/LDC1/LWC2/LDC2
4211         ra=get_reg(i_regs->regmap,FTEMP);
4212       else { // SWC1/SDC1/SWC2/SDC2
4213         ra=get_reg(i_regs->regmap,agr);
4214         if(ra<0) ra=get_reg(i_regs->regmap,-1);
4215       }
4216     }
4217     int rs=get_reg(i_regs->regmap,rs1[i]);
4218     int rm=get_reg(i_regs->regmap,TLREG);
4219     if(ra>=0) {
4220       int offset=imm[i];
4221       int c=(i_regs->wasconst>>rs)&1;
4222       if(rs1[i]==0) {
4223         // Using r0 as a base address
4224         /*if(rm>=0) {
4225           if(!entry||entry[rm]!=mgr) {
4226             generate_map_const(offset,rm);
4227           } // else did it in the previous cycle
4228         }*/
4229         if(!entry||entry[ra]!=agr) {
4230           if (opcode[i]==0x22||opcode[i]==0x26) {
4231             emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR
4232           }else if (opcode[i]==0x1a||opcode[i]==0x1b) {
4233             emit_movimm(offset&0xFFFFFFF8,ra); // LDL/LDR
4234           }else{
4235             emit_movimm(offset,ra);
4236           }
4237         } // else did it in the previous cycle
4238       }
4239       else if(rs<0) {
4240         if(!entry||entry[ra]!=rs1[i])
4241           emit_loadreg(rs1[i],ra);
4242         //if(!entry||entry[ra]!=rs1[i])
4243         //  printf("poor load scheduling!\n");
4244       }
4245       else if(c) {
4246 #ifndef DISABLE_TLB
4247         if(rm>=0) {
4248           if(!entry||entry[rm]!=mgr) {
4249             if(itype[i]==STORE||itype[i]==STORELR||(opcode[i]&0x3b)==0x39||(opcode[i]&0x3b)==0x3a) {
4250               // Stores to memory go thru the mapper to detect self-modifying
4251               // code, loads don't.
4252               if((unsigned int)(constmap[i][rs]+offset)>=0xC0000000 ||
4253                  (unsigned int)(constmap[i][rs]+offset)<0x80000000+RAM_SIZE )
4254                 generate_map_const(constmap[i][rs]+offset,rm);
4255             }else{
4256               if((signed int)(constmap[i][rs]+offset)>=(signed int)0xC0000000)
4257                 generate_map_const(constmap[i][rs]+offset,rm);
4258             }
4259           }
4260         }
4261 #endif
4262         if(rs1[i]!=rt1[i]||itype[i]!=LOAD) {
4263           if(!entry||entry[ra]!=agr) {
4264             if (opcode[i]==0x22||opcode[i]==0x26) {
4265               emit_movimm((constmap[i][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR
4266             }else if (opcode[i]==0x1a||opcode[i]==0x1b) {
4267               emit_movimm((constmap[i][rs]+offset)&0xFFFFFFF8,ra); // LDL/LDR
4268             }else{
4269               #ifdef HOST_IMM_ADDR32
4270               if((itype[i]!=LOAD&&(opcode[i]&0x3b)!=0x31&&(opcode[i]&0x3b)!=0x32) || // LWC1/LDC1/LWC2/LDC2
4271                  (using_tlb&&((signed int)constmap[i][rs]+offset)>=(signed int)0xC0000000))
4272               #endif
4273               emit_movimm(constmap[i][rs]+offset,ra);
4274               regs[i].loadedconst|=1<<ra;
4275             }
4276           } // else did it in the previous cycle
4277         } // else load_consts already did it
4278       }
4279       if(offset&&!c&&rs1[i]) {
4280         if(rs>=0) {
4281           emit_addimm(rs,offset,ra);
4282         }else{
4283           emit_addimm(ra,offset,ra);
4284         }
4285       }
4286     }
4287   }
4288   // Preload constants for next instruction
4289   if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS||itype[i+1]==C2LS) {
4290     int agr,ra;
4291     #if !defined(HOST_IMM_ADDR32) && !defined(DISABLE_TLB)
4292     // Mapper entry
4293     agr=MGEN1+((i+1)&1);
4294     ra=get_reg(i_regs->regmap,agr);
4295     if(ra>=0) {
4296       int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
4297       int offset=imm[i+1];
4298       int c=(regs[i+1].wasconst>>rs)&1;
4299       if(c) {
4300         if(itype[i+1]==STORE||itype[i+1]==STORELR
4301            ||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a) { // SWC1/SDC1, SWC2/SDC2
4302           // Stores to memory go thru the mapper to detect self-modifying
4303           // code, loads don't.
4304           if((unsigned int)(constmap[i+1][rs]+offset)>=0xC0000000 ||
4305              (unsigned int)(constmap[i+1][rs]+offset)<0x80000000+RAM_SIZE )
4306             generate_map_const(constmap[i+1][rs]+offset,ra);
4307         }else{
4308           if((signed int)(constmap[i+1][rs]+offset)>=(signed int)0xC0000000)
4309             generate_map_const(constmap[i+1][rs]+offset,ra);
4310         }
4311       }
4312       /*else if(rs1[i]==0) {
4313         generate_map_const(offset,ra);
4314       }*/
4315     }
4316     #endif
4317     // Actual address
4318     agr=AGEN1+((i+1)&1);
4319     ra=get_reg(i_regs->regmap,agr);
4320     if(ra>=0) {
4321       int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
4322       int offset=imm[i+1];
4323       int c=(regs[i+1].wasconst>>rs)&1;
4324       if(c&&(rs1[i+1]!=rt1[i+1]||itype[i+1]!=LOAD)) {
4325         if (opcode[i+1]==0x22||opcode[i+1]==0x26) {
4326           emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR
4327         }else if (opcode[i+1]==0x1a||opcode[i+1]==0x1b) {
4328           emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFF8,ra); // LDL/LDR
4329         }else{
4330           #ifdef HOST_IMM_ADDR32
4331           if((itype[i+1]!=LOAD&&(opcode[i+1]&0x3b)!=0x31&&(opcode[i+1]&0x3b)!=0x32) || // LWC1/LDC1/LWC2/LDC2
4332              (using_tlb&&((signed int)constmap[i+1][rs]+offset)>=(signed int)0xC0000000))
4333           #endif
4334           emit_movimm(constmap[i+1][rs]+offset,ra);
4335           regs[i+1].loadedconst|=1<<ra;
4336         }
4337       }
4338       else if(rs1[i+1]==0) {
4339         // Using r0 as a base address
4340         if (opcode[i+1]==0x22||opcode[i+1]==0x26) {
4341           emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR
4342         }else if (opcode[i+1]==0x1a||opcode[i+1]==0x1b) {
4343           emit_movimm(offset&0xFFFFFFF8,ra); // LDL/LDR
4344         }else{
4345           emit_movimm(offset,ra);
4346         }
4347       }
4348     }
4349   }
4350 }
4351
4352 int get_final_value(int hr, int i, int *value)
4353 {
4354   int reg=regs[i].regmap[hr];
4355   while(i<slen-1) {
4356     if(regs[i+1].regmap[hr]!=reg) break;
4357     if(!((regs[i+1].isconst>>hr)&1)) break;
4358     if(bt[i+1]) break;
4359     i++;
4360   }
4361   if(i<slen-1) {
4362     if(itype[i]==UJUMP||itype[i]==RJUMP||itype[i]==CJUMP||itype[i]==SJUMP) {
4363       *value=constmap[i][hr];
4364       return 1;
4365     }
4366     if(!bt[i+1]) {
4367       if(itype[i+1]==UJUMP||itype[i+1]==RJUMP||itype[i+1]==CJUMP||itype[i+1]==SJUMP) {
4368         // Load in delay slot, out-of-order execution
4369         if(itype[i+2]==LOAD&&rs1[i+2]==reg&&rt1[i+2]==reg&&((regs[i+1].wasconst>>hr)&1))
4370         {
4371           #ifdef HOST_IMM_ADDR32
4372           if(!using_tlb||((signed int)constmap[i][hr]+imm[i+2])<(signed int)0xC0000000) return 0;
4373           #endif
4374           // Precompute load address
4375           *value=constmap[i][hr]+imm[i+2];
4376           return 1;
4377         }
4378       }
4379       if(itype[i+1]==LOAD&&rs1[i+1]==reg&&rt1[i+1]==reg)
4380       {
4381         #ifdef HOST_IMM_ADDR32
4382         if(!using_tlb||((signed int)constmap[i][hr]+imm[i+1])<(signed int)0xC0000000) return 0;
4383         #endif
4384         // Precompute load address
4385         *value=constmap[i][hr]+imm[i+1];
4386         //printf("c=%x imm=%x\n",(int)constmap[i][hr],imm[i+1]);
4387         return 1;
4388       }
4389     }
4390   }
4391   *value=constmap[i][hr];
4392   //printf("c=%x\n",(int)constmap[i][hr]);
4393   if(i==slen-1) return 1;
4394   if(reg<64) {
4395     return !((unneeded_reg[i+1]>>reg)&1);
4396   }else{
4397     return !((unneeded_reg_upper[i+1]>>reg)&1);
4398   }
4399 }
4400
4401 // Load registers with known constants
4402 void load_consts(signed char pre[],signed char regmap[],int is32,int i)
4403 {
4404   int hr,hr2;
4405   // propagate loaded constant flags
4406   if(i==0||bt[i])
4407     regs[i].loadedconst=0;
4408   else {
4409     for(hr=0;hr<HOST_REGS;hr++) {
4410       if(hr!=EXCLUDE_REG&&regmap[hr]>=0&&((regs[i-1].isconst>>hr)&1)&&pre[hr]==regmap[hr]
4411          &&regmap[hr]==regs[i-1].regmap[hr]&&((regs[i-1].loadedconst>>hr)&1))
4412       {
4413         regs[i].loadedconst|=1<<hr;
4414       }
4415     }
4416   }
4417   // Load 32-bit regs
4418   for(hr=0;hr<HOST_REGS;hr++) {
4419     if(hr!=EXCLUDE_REG&&regmap[hr]>=0) {
4420       //if(entry[hr]!=regmap[hr]) {
4421       if(!((regs[i].loadedconst>>hr)&1)) {
4422         if(((regs[i].isconst>>hr)&1)&&regmap[hr]<64&&regmap[hr]>0) {
4423           int value,similar=0;
4424           if(get_final_value(hr,i,&value)) {
4425             // see if some other register has similar value
4426             for(hr2=0;hr2<HOST_REGS;hr2++) {
4427               if(hr2!=EXCLUDE_REG&&((regs[i].loadedconst>>hr2)&1)) {
4428                 if(is_similar_value(value,constmap[i][hr2])) {
4429                   similar=1;
4430                   break;
4431                 }
4432               }
4433             }
4434             if(similar) {
4435               int value2;
4436               if(get_final_value(hr2,i,&value2)) // is this needed?
4437                 emit_movimm_from(value2,hr2,value,hr);
4438               else
4439                 emit_movimm(value,hr);
4440             }
4441             else if(value==0) {
4442               emit_zeroreg(hr);
4443             }
4444             else {
4445               emit_movimm(value,hr);
4446             }
4447           }
4448           regs[i].loadedconst|=1<<hr;
4449         }
4450       }
4451     }
4452   }
4453   // Load 64-bit regs
4454   for(hr=0;hr<HOST_REGS;hr++) {
4455     if(hr!=EXCLUDE_REG&&regmap[hr]>=0) {
4456       //if(entry[hr]!=regmap[hr]) {
4457       if(i==0||!((regs[i-1].isconst>>hr)&1)||pre[hr]!=regmap[hr]||bt[i]) {
4458         if(((regs[i].isconst>>hr)&1)&&regmap[hr]>64) {
4459           if((is32>>(regmap[hr]&63))&1) {
4460             int lr=get_reg(regmap,regmap[hr]-64);
4461             assert(lr>=0);
4462             emit_sarimm(lr,31,hr);
4463           }
4464           else
4465           {
4466             int value;
4467             if(get_final_value(hr,i,&value)) {
4468               if(value==0) {
4469                 emit_zeroreg(hr);
4470               }
4471               else {
4472                 emit_movimm(value,hr);
4473               }
4474             }
4475           }
4476         }
4477       }
4478     }
4479   }
4480 }
4481 void load_all_consts(signed char regmap[],int is32,u_int dirty,int i)
4482 {
4483   int hr;
4484   // Load 32-bit regs
4485   for(hr=0;hr<HOST_REGS;hr++) {
4486     if(hr!=EXCLUDE_REG&&regmap[hr]>=0&&((dirty>>hr)&1)) {
4487       if(((regs[i].isconst>>hr)&1)&&regmap[hr]<64&&regmap[hr]>0) {
4488         int value=constmap[i][hr];
4489         if(value==0) {
4490           emit_zeroreg(hr);
4491         }
4492         else {
4493           emit_movimm(value,hr);
4494         }
4495       }
4496     }
4497   }
4498   // Load 64-bit regs
4499   for(hr=0;hr<HOST_REGS;hr++) {
4500     if(hr!=EXCLUDE_REG&&regmap[hr]>=0&&((dirty>>hr)&1)) {
4501       if(((regs[i].isconst>>hr)&1)&&regmap[hr]>64) {
4502         if((is32>>(regmap[hr]&63))&1) {
4503           int lr=get_reg(regmap,regmap[hr]-64);
4504           assert(lr>=0);
4505           emit_sarimm(lr,31,hr);
4506         }
4507         else
4508         {
4509           int value=constmap[i][hr];
4510           if(value==0) {
4511             emit_zeroreg(hr);
4512           }
4513           else {
4514             emit_movimm(value,hr);
4515           }
4516         }
4517       }
4518     }
4519   }
4520 }
4521
4522 // Write out all dirty registers (except cycle count)
4523 void wb_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty)
4524 {
4525   int hr;
4526   for(hr=0;hr<HOST_REGS;hr++) {
4527     if(hr!=EXCLUDE_REG) {
4528       if(i_regmap[hr]>0) {
4529         if(i_regmap[hr]!=CCREG) {
4530           if((i_dirty>>hr)&1) {
4531             if(i_regmap[hr]<64) {
4532               emit_storereg(i_regmap[hr],hr);
4533 #ifndef FORCE32
4534               if( ((i_is32>>i_regmap[hr])&1) ) {
4535                 #ifdef DESTRUCTIVE_WRITEBACK
4536                 emit_sarimm(hr,31,hr);
4537                 emit_storereg(i_regmap[hr]|64,hr);
4538                 #else
4539                 emit_sarimm(hr,31,HOST_TEMPREG);
4540                 emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
4541                 #endif
4542               }
4543 #endif
4544             }else{
4545               if( !((i_is32>>(i_regmap[hr]&63))&1) ) {
4546                 emit_storereg(i_regmap[hr],hr);
4547               }
4548             }
4549           }
4550         }
4551       }
4552     }
4553   }
4554 }
4555 // Write out dirty registers that we need to reload (pair with load_needed_regs)
4556 // This writes the registers not written by store_regs_bt
4557 void wb_needed_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4558 {
4559   int hr;
4560   int t=(addr-start)>>2;
4561   for(hr=0;hr<HOST_REGS;hr++) {
4562     if(hr!=EXCLUDE_REG) {
4563       if(i_regmap[hr]>0) {
4564         if(i_regmap[hr]!=CCREG) {
4565           if(i_regmap[hr]==regs[t].regmap_entry[hr] && ((regs[t].dirty>>hr)&1) && !(((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) {
4566             if((i_dirty>>hr)&1) {
4567               if(i_regmap[hr]<64) {
4568                 emit_storereg(i_regmap[hr],hr);
4569 #ifndef FORCE32
4570                 if( ((i_is32>>i_regmap[hr])&1) ) {
4571                   #ifdef DESTRUCTIVE_WRITEBACK
4572                   emit_sarimm(hr,31,hr);
4573                   emit_storereg(i_regmap[hr]|64,hr);
4574                   #else
4575                   emit_sarimm(hr,31,HOST_TEMPREG);
4576                   emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
4577                   #endif
4578                 }
4579 #endif
4580               }else{
4581                 if( !((i_is32>>(i_regmap[hr]&63))&1) ) {
4582                   emit_storereg(i_regmap[hr],hr);
4583                 }
4584               }
4585             }
4586           }
4587         }
4588       }
4589     }
4590   }
4591 }
4592
4593 // Load all registers (except cycle count)
4594 void load_all_regs(signed char i_regmap[])
4595 {
4596   int hr;
4597   for(hr=0;hr<HOST_REGS;hr++) {
4598     if(hr!=EXCLUDE_REG) {
4599       if(i_regmap[hr]==0) {
4600         emit_zeroreg(hr);
4601       }
4602       else
4603       if(i_regmap[hr]>0 && (i_regmap[hr]&63)<TEMPREG && i_regmap[hr]!=CCREG)
4604       {
4605         emit_loadreg(i_regmap[hr],hr);
4606       }
4607     }
4608   }
4609 }
4610
4611 // Load all current registers also needed by next instruction
4612 void load_needed_regs(signed char i_regmap[],signed char next_regmap[])
4613 {
4614   int hr;
4615   for(hr=0;hr<HOST_REGS;hr++) {
4616     if(hr!=EXCLUDE_REG) {
4617       if(get_reg(next_regmap,i_regmap[hr])>=0) {
4618         if(i_regmap[hr]==0) {
4619           emit_zeroreg(hr);
4620         }
4621         else
4622         if(i_regmap[hr]>0 && (i_regmap[hr]&63)<TEMPREG && i_regmap[hr]!=CCREG)
4623         {
4624           emit_loadreg(i_regmap[hr],hr);
4625         }
4626       }
4627     }
4628   }
4629 }
4630
4631 // Load all regs, storing cycle count if necessary
4632 void load_regs_entry(int t)
4633 {
4634   int hr;
4635   if(is_ds[t]) emit_addimm(HOST_CCREG,CLOCK_ADJUST(1),HOST_CCREG);
4636   else if(ccadj[t]) emit_addimm(HOST_CCREG,-CLOCK_ADJUST(ccadj[t]),HOST_CCREG);
4637   if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) {
4638     emit_storereg(CCREG,HOST_CCREG);
4639   }
4640   // Load 32-bit regs
4641   for(hr=0;hr<HOST_REGS;hr++) {
4642     if(regs[t].regmap_entry[hr]>=0&&regs[t].regmap_entry[hr]<TEMPREG) {
4643       if(regs[t].regmap_entry[hr]==0) {
4644         emit_zeroreg(hr);
4645       }
4646       else if(regs[t].regmap_entry[hr]!=CCREG)
4647       {
4648         emit_loadreg(regs[t].regmap_entry[hr],hr);
4649       }
4650     }
4651   }
4652   // Load 64-bit regs
4653   for(hr=0;hr<HOST_REGS;hr++) {
4654     if(regs[t].regmap_entry[hr]>=64&&regs[t].regmap_entry[hr]<TEMPREG+64) {
4655       assert(regs[t].regmap_entry[hr]!=64);
4656       if((regs[t].was32>>(regs[t].regmap_entry[hr]&63))&1) {
4657         int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64);
4658         if(lr<0) {
4659           emit_loadreg(regs[t].regmap_entry[hr],hr);
4660         }
4661         else
4662         {
4663           emit_sarimm(lr,31,hr);
4664         }
4665       }
4666       else
4667       {
4668         emit_loadreg(regs[t].regmap_entry[hr],hr);
4669       }
4670     }
4671   }
4672 }
4673
4674 // Store dirty registers prior to branch
4675 void store_regs_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4676 {
4677   if(internal_branch(i_is32,addr))
4678   {
4679     int t=(addr-start)>>2;
4680     int hr;
4681     for(hr=0;hr<HOST_REGS;hr++) {
4682       if(hr!=EXCLUDE_REG) {
4683         if(i_regmap[hr]>0 && i_regmap[hr]!=CCREG) {
4684           if(i_regmap[hr]!=regs[t].regmap_entry[hr] || !((regs[t].dirty>>hr)&1) || (((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) {
4685             if((i_dirty>>hr)&1) {
4686               if(i_regmap[hr]<64) {
4687                 if(!((unneeded_reg[t]>>i_regmap[hr])&1)) {
4688                   emit_storereg(i_regmap[hr],hr);
4689                   if( ((i_is32>>i_regmap[hr])&1) && !((unneeded_reg_upper[t]>>i_regmap[hr])&1) ) {
4690                     #ifdef DESTRUCTIVE_WRITEBACK
4691                     emit_sarimm(hr,31,hr);
4692                     emit_storereg(i_regmap[hr]|64,hr);
4693                     #else
4694                     emit_sarimm(hr,31,HOST_TEMPREG);
4695                     emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
4696                     #endif
4697                   }
4698                 }
4699               }else{
4700                 if( !((i_is32>>(i_regmap[hr]&63))&1) && !((unneeded_reg_upper[t]>>(i_regmap[hr]&63))&1) ) {
4701                   emit_storereg(i_regmap[hr],hr);
4702                 }
4703               }
4704             }
4705           }
4706         }
4707       }
4708     }
4709   }
4710   else
4711   {
4712     // Branch out of this block, write out all dirty regs
4713     wb_dirtys(i_regmap,i_is32,i_dirty);
4714   }
4715 }
4716
4717 // Load all needed registers for branch target
4718 void load_regs_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4719 {
4720   //if(addr>=start && addr<(start+slen*4))
4721   if(internal_branch(i_is32,addr))
4722   {
4723     int t=(addr-start)>>2;
4724     int hr;
4725     // Store the cycle count before loading something else
4726     if(i_regmap[HOST_CCREG]!=CCREG) {
4727       assert(i_regmap[HOST_CCREG]==-1);
4728     }
4729     if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) {
4730       emit_storereg(CCREG,HOST_CCREG);
4731     }
4732     // Load 32-bit regs
4733     for(hr=0;hr<HOST_REGS;hr++) {
4734       if(hr!=EXCLUDE_REG&&regs[t].regmap_entry[hr]>=0&&regs[t].regmap_entry[hr]<TEMPREG) {
4735         #ifdef DESTRUCTIVE_WRITEBACK
4736         if(i_regmap[hr]!=regs[t].regmap_entry[hr] || ( !((regs[t].dirty>>hr)&1) && ((i_dirty>>hr)&1) && (((i_is32&~unneeded_reg_upper[t])>>i_regmap[hr])&1) ) || (((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) {
4737         #else
4738         if(i_regmap[hr]!=regs[t].regmap_entry[hr] ) {
4739         #endif
4740           if(regs[t].regmap_entry[hr]==0) {
4741             emit_zeroreg(hr);
4742           }
4743           else if(regs[t].regmap_entry[hr]!=CCREG)
4744           {
4745             emit_loadreg(regs[t].regmap_entry[hr],hr);
4746           }
4747         }
4748       }
4749     }
4750     //Load 64-bit regs
4751     for(hr=0;hr<HOST_REGS;hr++) {
4752       if(hr!=EXCLUDE_REG&&regs[t].regmap_entry[hr]>=64&&regs[t].regmap_entry[hr]<TEMPREG+64) {
4753         if(i_regmap[hr]!=regs[t].regmap_entry[hr]) {
4754           assert(regs[t].regmap_entry[hr]!=64);
4755           if((i_is32>>(regs[t].regmap_entry[hr]&63))&1) {
4756             int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64);
4757             if(lr<0) {
4758               emit_loadreg(regs[t].regmap_entry[hr],hr);
4759             }
4760             else
4761             {
4762               emit_sarimm(lr,31,hr);
4763             }
4764           }
4765           else
4766           {
4767             emit_loadreg(regs[t].regmap_entry[hr],hr);
4768           }
4769         }
4770         else if((i_is32>>(regs[t].regmap_entry[hr]&63))&1) {
4771           int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64);
4772           assert(lr>=0);
4773           emit_sarimm(lr,31,hr);
4774         }
4775       }
4776     }
4777   }
4778 }
4779
4780 int match_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4781 {
4782   if(addr>=start && addr<start+slen*4-4)
4783   {
4784     int t=(addr-start)>>2;
4785     int hr;
4786     if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) return 0;
4787     for(hr=0;hr<HOST_REGS;hr++)
4788     {
4789       if(hr!=EXCLUDE_REG)
4790       {
4791         if(i_regmap[hr]!=regs[t].regmap_entry[hr])
4792         {
4793           if(regs[t].regmap_entry[hr]>=0&&(regs[t].regmap_entry[hr]|64)<TEMPREG+64)
4794           {
4795             return 0;
4796           }
4797           else
4798           if((i_dirty>>hr)&1)
4799           {
4800             if(i_regmap[hr]<TEMPREG)
4801             {
4802               if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4803                 return 0;
4804             }
4805             else if(i_regmap[hr]>=64&&i_regmap[hr]<TEMPREG+64)
4806             {
4807               if(!((unneeded_reg_upper[t]>>(i_regmap[hr]&63))&1))
4808                 return 0;
4809             }
4810           }
4811         }
4812         else // Same register but is it 32-bit or dirty?
4813         if(i_regmap[hr]>=0)
4814         {
4815           if(!((regs[t].dirty>>hr)&1))
4816           {
4817             if((i_dirty>>hr)&1)
4818             {
4819               if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4820               {
4821                 //printf("%x: dirty no match\n",addr);
4822                 return 0;
4823               }
4824             }
4825           }
4826           if((((regs[t].was32^i_is32)&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)
4827           {
4828             //printf("%x: is32 no match\n",addr);
4829             return 0;
4830           }
4831         }
4832       }
4833     }
4834     //if(is32[t]&~unneeded_reg_upper[t]&~i_is32) return 0;
4835 #ifndef FORCE32
4836     if(requires_32bit[t]&~i_is32) return 0;
4837 #endif
4838     // Delay slots are not valid branch targets
4839     //if(t>0&&(itype[t-1]==RJUMP||itype[t-1]==UJUMP||itype[t-1]==CJUMP||itype[t-1]==SJUMP||itype[t-1]==FJUMP)) return 0;
4840     // Delay slots require additional processing, so do not match
4841     if(is_ds[t]) return 0;
4842   }
4843   else
4844   {
4845     int hr;
4846     for(hr=0;hr<HOST_REGS;hr++)
4847     {
4848       if(hr!=EXCLUDE_REG)
4849       {
4850         if(i_regmap[hr]>=0)
4851         {
4852           if(hr!=HOST_CCREG||i_regmap[hr]!=CCREG)
4853           {
4854             if((i_dirty>>hr)&1)
4855             {
4856               return 0;
4857             }
4858           }
4859         }
4860       }
4861     }
4862   }
4863   return 1;
4864 }
4865
4866 // Used when a branch jumps into the delay slot of another branch
4867 void ds_assemble_entry(int i)
4868 {
4869   int t=(ba[i]-start)>>2;
4870   if(!instr_addr[t]) instr_addr[t]=(u_int)out;
4871   assem_debug("Assemble delay slot at %x\n",ba[i]);
4872   assem_debug("<->\n");
4873   if(regs[t].regmap_entry[HOST_CCREG]==CCREG&&regs[t].regmap[HOST_CCREG]!=CCREG)
4874     wb_register(CCREG,regs[t].regmap_entry,regs[t].wasdirty,regs[t].was32);
4875   load_regs(regs[t].regmap_entry,regs[t].regmap,regs[t].was32,rs1[t],rs2[t]);
4876   address_generation(t,&regs[t],regs[t].regmap_entry);
4877   if(itype[t]==STORE||itype[t]==STORELR||(opcode[t]&0x3b)==0x39||(opcode[t]&0x3b)==0x3a)
4878     load_regs(regs[t].regmap_entry,regs[t].regmap,regs[t].was32,INVCP,INVCP);
4879   cop1_usable=0;
4880   is_delayslot=0;
4881   switch(itype[t]) {
4882     case ALU:
4883       alu_assemble(t,&regs[t]);break;
4884     case IMM16:
4885       imm16_assemble(t,&regs[t]);break;
4886     case SHIFT:
4887       shift_assemble(t,&regs[t]);break;
4888     case SHIFTIMM:
4889       shiftimm_assemble(t,&regs[t]);break;
4890     case LOAD:
4891       load_assemble(t,&regs[t]);break;
4892     case LOADLR:
4893       loadlr_assemble(t,&regs[t]);break;
4894     case STORE:
4895       store_assemble(t,&regs[t]);break;
4896     case STORELR:
4897       storelr_assemble(t,&regs[t]);break;
4898     case COP0:
4899       cop0_assemble(t,&regs[t]);break;
4900     case COP1:
4901       cop1_assemble(t,&regs[t]);break;
4902     case C1LS:
4903       c1ls_assemble(t,&regs[t]);break;
4904     case COP2:
4905       cop2_assemble(t,&regs[t]);break;
4906     case C2LS:
4907       c2ls_assemble(t,&regs[t]);break;
4908     case C2OP:
4909       c2op_assemble(t,&regs[t]);break;
4910     case FCONV:
4911       fconv_assemble(t,&regs[t]);break;
4912     case FLOAT:
4913       float_assemble(t,&regs[t]);break;
4914     case FCOMP:
4915       fcomp_assemble(t,&regs[t]);break;
4916     case MULTDIV:
4917       multdiv_assemble(t,&regs[t]);break;
4918     case MOV:
4919       mov_assemble(t,&regs[t]);break;
4920     case SYSCALL:
4921     case HLECALL:
4922     case INTCALL:
4923     case SPAN:
4924     case UJUMP:
4925     case RJUMP:
4926     case CJUMP:
4927     case SJUMP:
4928     case FJUMP:
4929       printf("Jump in the delay slot.  This is probably a bug.\n");
4930   }
4931   store_regs_bt(regs[t].regmap,regs[t].is32,regs[t].dirty,ba[i]+4);
4932   load_regs_bt(regs[t].regmap,regs[t].is32,regs[t].dirty,ba[i]+4);
4933   if(internal_branch(regs[t].is32,ba[i]+4))
4934     assem_debug("branch: internal\n");
4935   else
4936     assem_debug("branch: external\n");
4937   assert(internal_branch(regs[t].is32,ba[i]+4));
4938   add_to_linker((int)out,ba[i]+4,internal_branch(regs[t].is32,ba[i]+4));
4939   emit_jmp(0);
4940 }
4941
4942 void do_cc(int i,signed char i_regmap[],int *adj,int addr,int taken,int invert)
4943 {
4944   int count;
4945   int jaddr;
4946   int idle=0;
4947   if(itype[i]==RJUMP)
4948   {
4949     *adj=0;
4950   }
4951   //if(ba[i]>=start && ba[i]<(start+slen*4))
4952   if(internal_branch(branch_regs[i].is32,ba[i]))
4953   {
4954     int t=(ba[i]-start)>>2;
4955     if(is_ds[t]) *adj=-1; // Branch into delay slot adds an extra cycle
4956     else *adj=ccadj[t];
4957   }
4958   else
4959   {
4960     *adj=0;
4961   }
4962   count=ccadj[i];
4963   if(taken==TAKEN && i==(ba[i]-start)>>2 && source[i+1]==0) {
4964     // Idle loop
4965     if(count&1) emit_addimm_and_set_flags(2*(count+2),HOST_CCREG);
4966     idle=(int)out;
4967     //emit_subfrommem(&idlecount,HOST_CCREG); // Count idle cycles
4968     emit_andimm(HOST_CCREG,3,HOST_CCREG);
4969     jaddr=(int)out;
4970     emit_jmp(0);
4971   }
4972   else if(*adj==0||invert) {
4973     emit_addimm_and_set_flags(CLOCK_ADJUST(count+2),HOST_CCREG);
4974     jaddr=(int)out;
4975     emit_jns(0);
4976   }
4977   else
4978   {
4979     emit_cmpimm(HOST_CCREG,-CLOCK_ADJUST(count+2));
4980     jaddr=(int)out;
4981     emit_jns(0);
4982   }
4983   add_stub(CC_STUB,jaddr,idle?idle:(int)out,(*adj==0||invert||idle)?0:(count+2),i,addr,taken,0);
4984 }
4985
4986 void do_ccstub(int n)
4987 {
4988   literal_pool(256);
4989   assem_debug("do_ccstub %x\n",start+stubs[n][4]*4);
4990   set_jump_target(stubs[n][1],(int)out);
4991   int i=stubs[n][4];
4992   if(stubs[n][6]==NULLDS) {
4993     // Delay slot instruction is nullified ("likely" branch)
4994     wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty);
4995   }
4996   else if(stubs[n][6]!=TAKEN) {
4997     wb_dirtys(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty);
4998   }
4999   else {
5000     if(internal_branch(branch_regs[i].is32,ba[i]))
5001       wb_needed_dirtys(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5002   }
5003   if(stubs[n][5]!=-1)
5004   {
5005     // Save PC as return address
5006     emit_movimm(stubs[n][5],EAX);
5007     emit_writeword(EAX,(int)&pcaddr);
5008   }
5009   else
5010   {
5011     // Return address depends on which way the branch goes
5012     if(itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
5013     {
5014       int s1l=get_reg(branch_regs[i].regmap,rs1[i]);
5015       int s1h=get_reg(branch_regs[i].regmap,rs1[i]|64);
5016       int s2l=get_reg(branch_regs[i].regmap,rs2[i]);
5017       int s2h=get_reg(branch_regs[i].regmap,rs2[i]|64);
5018       if(rs1[i]==0)
5019       {
5020         s1l=s2l;s1h=s2h;
5021         s2l=s2h=-1;
5022       }
5023       else if(rs2[i]==0)
5024       {
5025         s2l=s2h=-1;
5026       }
5027       if((branch_regs[i].is32>>rs1[i])&(branch_regs[i].is32>>rs2[i])&1) {
5028         s1h=s2h=-1;
5029       }
5030       assert(s1l>=0);
5031       #ifdef DESTRUCTIVE_WRITEBACK
5032       if(rs1[i]) {
5033         if((branch_regs[i].dirty>>s1l)&(branch_regs[i].is32>>rs1[i])&1)
5034           emit_loadreg(rs1[i],s1l);
5035       }
5036       else {
5037         if((branch_regs[i].dirty>>s1l)&(branch_regs[i].is32>>rs2[i])&1)
5038           emit_loadreg(rs2[i],s1l);
5039       }
5040       if(s2l>=0)
5041         if((branch_regs[i].dirty>>s2l)&(branch_regs[i].is32>>rs2[i])&1)
5042           emit_loadreg(rs2[i],s2l);
5043       #endif
5044       int hr=0;
5045       int addr=-1,alt=-1,ntaddr=-1;
5046       while(hr<HOST_REGS)
5047       {
5048         if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
5049            (branch_regs[i].regmap[hr]&63)!=rs1[i] &&
5050            (branch_regs[i].regmap[hr]&63)!=rs2[i] )
5051         {
5052           addr=hr++;break;
5053         }
5054         hr++;
5055       }
5056       while(hr<HOST_REGS)
5057       {
5058         if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
5059            (branch_regs[i].regmap[hr]&63)!=rs1[i] &&
5060            (branch_regs[i].regmap[hr]&63)!=rs2[i] )
5061         {
5062           alt=hr++;break;
5063         }
5064         hr++;
5065       }
5066       if((opcode[i]&0x2E)==6) // BLEZ/BGTZ needs another register
5067       {
5068         while(hr<HOST_REGS)
5069         {
5070           if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
5071              (branch_regs[i].regmap[hr]&63)!=rs1[i] &&
5072              (branch_regs[i].regmap[hr]&63)!=rs2[i] )
5073           {
5074             ntaddr=hr;break;
5075           }
5076           hr++;
5077         }
5078         assert(hr<HOST_REGS);
5079       }
5080       if((opcode[i]&0x2f)==4) // BEQ
5081       {
5082         #ifdef HAVE_CMOV_IMM
5083         if(s1h<0) {
5084           if(s2l>=0) emit_cmp(s1l,s2l);
5085           else emit_test(s1l,s1l);
5086           emit_cmov2imm_e_ne_compact(ba[i],start+i*4+8,addr);
5087         }
5088         else
5089         #endif
5090         {
5091           emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
5092           if(s1h>=0) {
5093             if(s2h>=0) emit_cmp(s1h,s2h);
5094             else emit_test(s1h,s1h);
5095             emit_cmovne_reg(alt,addr);
5096           }
5097           if(s2l>=0) emit_cmp(s1l,s2l);
5098           else emit_test(s1l,s1l);
5099           emit_cmovne_reg(alt,addr);
5100         }
5101       }
5102       if((opcode[i]&0x2f)==5) // BNE
5103       {
5104         #ifdef HAVE_CMOV_IMM
5105         if(s1h<0) {
5106           if(s2l>=0) emit_cmp(s1l,s2l);
5107           else emit_test(s1l,s1l);
5108           emit_cmov2imm_e_ne_compact(start+i*4+8,ba[i],addr);
5109         }
5110         else
5111         #endif
5112         {
5113           emit_mov2imm_compact(start+i*4+8,addr,ba[i],alt);
5114           if(s1h>=0) {
5115             if(s2h>=0) emit_cmp(s1h,s2h);
5116             else emit_test(s1h,s1h);
5117             emit_cmovne_reg(alt,addr);
5118           }
5119           if(s2l>=0) emit_cmp(s1l,s2l);
5120           else emit_test(s1l,s1l);
5121           emit_cmovne_reg(alt,addr);
5122         }
5123       }
5124       if((opcode[i]&0x2f)==6) // BLEZ
5125       {
5126         //emit_movimm(ba[i],alt);
5127         //emit_movimm(start+i*4+8,addr);
5128         emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
5129         emit_cmpimm(s1l,1);
5130         if(s1h>=0) emit_mov(addr,ntaddr);
5131         emit_cmovl_reg(alt,addr);
5132         if(s1h>=0) {
5133           emit_test(s1h,s1h);
5134           emit_cmovne_reg(ntaddr,addr);
5135           emit_cmovs_reg(alt,addr);
5136         }
5137       }
5138       if((opcode[i]&0x2f)==7) // BGTZ
5139       {
5140         //emit_movimm(ba[i],addr);
5141         //emit_movimm(start+i*4+8,ntaddr);
5142         emit_mov2imm_compact(ba[i],addr,start+i*4+8,ntaddr);
5143         emit_cmpimm(s1l,1);
5144         if(s1h>=0) emit_mov(addr,alt);
5145         emit_cmovl_reg(ntaddr,addr);
5146         if(s1h>=0) {
5147           emit_test(s1h,s1h);
5148           emit_cmovne_reg(alt,addr);
5149           emit_cmovs_reg(ntaddr,addr);
5150         }
5151       }
5152       if((opcode[i]==1)&&(opcode2[i]&0x2D)==0) // BLTZ
5153       {
5154         //emit_movimm(ba[i],alt);
5155         //emit_movimm(start+i*4+8,addr);
5156         emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
5157         if(s1h>=0) emit_test(s1h,s1h);
5158         else emit_test(s1l,s1l);
5159         emit_cmovs_reg(alt,addr);
5160       }
5161       if((opcode[i]==1)&&(opcode2[i]&0x2D)==1) // BGEZ
5162       {
5163         //emit_movimm(ba[i],addr);
5164         //emit_movimm(start+i*4+8,alt);
5165         emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
5166         if(s1h>=0) emit_test(s1h,s1h);
5167         else emit_test(s1l,s1l);
5168         emit_cmovs_reg(alt,addr);
5169       }
5170       if(opcode[i]==0x11 && opcode2[i]==0x08 ) {
5171         if(source[i]&0x10000) // BC1T
5172         {
5173           //emit_movimm(ba[i],alt);
5174           //emit_movimm(start+i*4+8,addr);
5175           emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
5176           emit_testimm(s1l,0x800000);
5177           emit_cmovne_reg(alt,addr);
5178         }
5179         else // BC1F
5180         {
5181           //emit_movimm(ba[i],addr);
5182           //emit_movimm(start+i*4+8,alt);
5183           emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
5184           emit_testimm(s1l,0x800000);
5185           emit_cmovne_reg(alt,addr);
5186         }
5187       }
5188       emit_writeword(addr,(int)&pcaddr);
5189     }
5190     else
5191     if(itype[i]==RJUMP)
5192     {
5193       int r=get_reg(branch_regs[i].regmap,rs1[i]);
5194       if(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]) {
5195         r=get_reg(branch_regs[i].regmap,RTEMP);
5196       }
5197       emit_writeword(r,(int)&pcaddr);
5198     }
5199     else {printf("Unknown branch type in do_ccstub\n");exit(1);}
5200   }
5201   // Update cycle count
5202   assert(branch_regs[i].regmap[HOST_CCREG]==CCREG||branch_regs[i].regmap[HOST_CCREG]==-1);
5203   if(stubs[n][3]) emit_addimm(HOST_CCREG,CLOCK_ADJUST((int)stubs[n][3]),HOST_CCREG);
5204   emit_call((int)cc_interrupt);
5205   if(stubs[n][3]) emit_addimm(HOST_CCREG,-CLOCK_ADJUST((int)stubs[n][3]),HOST_CCREG);
5206   if(stubs[n][6]==TAKEN) {
5207     if(internal_branch(branch_regs[i].is32,ba[i]))
5208       load_needed_regs(branch_regs[i].regmap,regs[(ba[i]-start)>>2].regmap_entry);
5209     else if(itype[i]==RJUMP) {
5210       if(get_reg(branch_regs[i].regmap,RTEMP)>=0)
5211         emit_readword((int)&pcaddr,get_reg(branch_regs[i].regmap,RTEMP));
5212       else
5213         emit_loadreg(rs1[i],get_reg(branch_regs[i].regmap,rs1[i]));
5214     }
5215   }else if(stubs[n][6]==NOTTAKEN) {
5216     if(i<slen-2) load_needed_regs(branch_regs[i].regmap,regmap_pre[i+2]);
5217     else load_all_regs(branch_regs[i].regmap);
5218   }else if(stubs[n][6]==NULLDS) {
5219     // Delay slot instruction is nullified ("likely" branch)
5220     if(i<slen-2) load_needed_regs(regs[i].regmap,regmap_pre[i+2]);
5221     else load_all_regs(regs[i].regmap);
5222   }else{
5223     load_all_regs(branch_regs[i].regmap);
5224   }
5225   emit_jmp(stubs[n][2]); // return address
5226
5227   /* This works but uses a lot of memory...
5228   emit_readword((int)&last_count,ECX);
5229   emit_add(HOST_CCREG,ECX,EAX);
5230   emit_writeword(EAX,(int)&Count);
5231   emit_call((int)gen_interupt);
5232   emit_readword((int)&Count,HOST_CCREG);
5233   emit_readword((int)&next_interupt,EAX);
5234   emit_readword((int)&pending_exception,EBX);
5235   emit_writeword(EAX,(int)&last_count);
5236   emit_sub(HOST_CCREG,EAX,HOST_CCREG);
5237   emit_test(EBX,EBX);
5238   int jne_instr=(int)out;
5239   emit_jne(0);
5240   if(stubs[n][3]) emit_addimm(HOST_CCREG,-2*stubs[n][3],HOST_CCREG);
5241   load_all_regs(branch_regs[i].regmap);
5242   emit_jmp(stubs[n][2]); // return address
5243   set_jump_target(jne_instr,(int)out);
5244   emit_readword((int)&pcaddr,EAX);
5245   // Call get_addr_ht instead of doing the hash table here.
5246   // This code is executed infrequently and takes up a lot of space
5247   // so smaller is better.
5248   emit_storereg(CCREG,HOST_CCREG);
5249   emit_pushreg(EAX);
5250   emit_call((int)get_addr_ht);
5251   emit_loadreg(CCREG,HOST_CCREG);
5252   emit_addimm(ESP,4,ESP);
5253   emit_jmpreg(EAX);*/
5254 }
5255
5256 add_to_linker(int addr,int target,int ext)
5257 {
5258   link_addr[linkcount][0]=addr;
5259   link_addr[linkcount][1]=target;
5260   link_addr[linkcount][2]=ext;
5261   linkcount++;
5262 }
5263
5264 static void ujump_assemble_write_ra(int i)
5265 {
5266   int rt;
5267   unsigned int return_address;
5268   rt=get_reg(branch_regs[i].regmap,31);
5269   assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5270   //assert(rt>=0);
5271   return_address=start+i*4+8;
5272   if(rt>=0) {
5273     #ifdef USE_MINI_HT
5274     if(internal_branch(branch_regs[i].is32,return_address)&&rt1[i+1]!=31) {
5275       int temp=-1; // note: must be ds-safe
5276       #ifdef HOST_TEMPREG
5277       temp=HOST_TEMPREG;
5278       #endif
5279       if(temp>=0) do_miniht_insert(return_address,rt,temp);
5280       else emit_movimm(return_address,rt);
5281     }
5282     else
5283     #endif
5284     {
5285       #ifdef REG_PREFETCH
5286       if(temp>=0)
5287       {
5288         if(i_regmap[temp]!=PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5289       }
5290       #endif
5291       emit_movimm(return_address,rt); // PC into link register
5292       #ifdef IMM_PREFETCH
5293       emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
5294       #endif
5295     }
5296   }
5297 }
5298
5299 void ujump_assemble(int i,struct regstat *i_regs)
5300 {
5301   signed char *i_regmap=i_regs->regmap;
5302   int ra_done=0;
5303   if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
5304   address_generation(i+1,i_regs,regs[i].regmap_entry);
5305   #ifdef REG_PREFETCH
5306   int temp=get_reg(branch_regs[i].regmap,PTEMP);
5307   if(rt1[i]==31&&temp>=0)
5308   {
5309     int return_address=start+i*4+8;
5310     if(get_reg(branch_regs[i].regmap,31)>0)
5311     if(i_regmap[temp]==PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5312   }
5313   #endif
5314   if(rt1[i]==31&&(rt1[i]==rs1[i+1]||rt1[i]==rs2[i+1])) {
5315     ujump_assemble_write_ra(i); // writeback ra for DS
5316     ra_done=1;
5317   }
5318   ds_assemble(i+1,i_regs);
5319   uint64_t bc_unneeded=branch_regs[i].u;
5320   uint64_t bc_unneeded_upper=branch_regs[i].uu;
5321   bc_unneeded|=1|(1LL<<rt1[i]);
5322   bc_unneeded_upper|=1|(1LL<<rt1[i]);
5323   wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5324                 bc_unneeded,bc_unneeded_upper);
5325   load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5326   if(!ra_done&&rt1[i]==31)
5327     ujump_assemble_write_ra(i);
5328   int cc,adj;
5329   cc=get_reg(branch_regs[i].regmap,CCREG);
5330   assert(cc==HOST_CCREG);
5331   store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5332   #ifdef REG_PREFETCH
5333   if(rt1[i]==31&&temp>=0) emit_prefetchreg(temp);
5334   #endif
5335   do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5336   if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
5337   load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5338   if(internal_branch(branch_regs[i].is32,ba[i]))
5339     assem_debug("branch: internal\n");
5340   else
5341     assem_debug("branch: external\n");
5342   if(internal_branch(branch_regs[i].is32,ba[i])&&is_ds[(ba[i]-start)>>2]) {
5343     ds_assemble_entry(i);
5344   }
5345   else {
5346     add_to_linker((int)out,ba[i],internal_branch(branch_regs[i].is32,ba[i]));
5347     emit_jmp(0);
5348   }
5349 }
5350
5351 static void rjump_assemble_write_ra(int i)
5352 {
5353   int rt,return_address;
5354   assert(rt1[i+1]!=rt1[i]);
5355   assert(rt2[i+1]!=rt1[i]);
5356   rt=get_reg(branch_regs[i].regmap,rt1[i]);
5357   assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5358   assert(rt>=0);
5359   return_address=start+i*4+8;
5360   #ifdef REG_PREFETCH
5361   if(temp>=0)
5362   {
5363     if(i_regmap[temp]!=PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5364   }
5365   #endif
5366   emit_movimm(return_address,rt); // PC into link register
5367   #ifdef IMM_PREFETCH
5368   emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
5369   #endif
5370 }
5371
5372 void rjump_assemble(int i,struct regstat *i_regs)
5373 {
5374   signed char *i_regmap=i_regs->regmap;
5375   int temp;
5376   int rs,cc,adj;
5377   int ra_done=0;
5378   rs=get_reg(branch_regs[i].regmap,rs1[i]);
5379   assert(rs>=0);
5380   if(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]) {
5381     // Delay slot abuse, make a copy of the branch address register
5382     temp=get_reg(branch_regs[i].regmap,RTEMP);
5383     assert(temp>=0);
5384     assert(regs[i].regmap[temp]==RTEMP);
5385     emit_mov(rs,temp);
5386     rs=temp;
5387   }
5388   address_generation(i+1,i_regs,regs[i].regmap_entry);
5389   #ifdef REG_PREFETCH
5390   if(rt1[i]==31)
5391   {
5392     if((temp=get_reg(branch_regs[i].regmap,PTEMP))>=0) {
5393       int return_address=start+i*4+8;
5394       if(i_regmap[temp]==PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5395     }
5396   }
5397   #endif
5398   #ifdef USE_MINI_HT
5399   if(rs1[i]==31) {
5400     int rh=get_reg(regs[i].regmap,RHASH);
5401     if(rh>=0) do_preload_rhash(rh);
5402   }
5403   #endif
5404   if(rt1[i]!=0&&(rt1[i]==rs1[i+1]||rt1[i]==rs2[i+1])) {
5405     rjump_assemble_write_ra(i);
5406     ra_done=1;
5407   }
5408   ds_assemble(i+1,i_regs);
5409   uint64_t bc_unneeded=branch_regs[i].u;
5410   uint64_t bc_unneeded_upper=branch_regs[i].uu;
5411   bc_unneeded|=1|(1LL<<rt1[i]);
5412   bc_unneeded_upper|=1|(1LL<<rt1[i]);
5413   bc_unneeded&=~(1LL<<rs1[i]);
5414   wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5415                 bc_unneeded,bc_unneeded_upper);
5416   load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],CCREG);
5417   if(!ra_done&&rt1[i]!=0)
5418     rjump_assemble_write_ra(i);
5419   cc=get_reg(branch_regs[i].regmap,CCREG);
5420   assert(cc==HOST_CCREG);
5421   #ifdef USE_MINI_HT
5422   int rh=get_reg(branch_regs[i].regmap,RHASH);
5423   int ht=get_reg(branch_regs[i].regmap,RHTBL);
5424   if(rs1[i]==31) {
5425     if(regs[i].regmap[rh]!=RHASH) do_preload_rhash(rh);
5426     do_preload_rhtbl(ht);
5427     do_rhash(rs,rh);
5428   }
5429   #endif
5430   store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,-1);
5431   #ifdef DESTRUCTIVE_WRITEBACK
5432   if((branch_regs[i].dirty>>rs)&(branch_regs[i].is32>>rs1[i])&1) {
5433     if(rs1[i]!=rt1[i+1]&&rs1[i]!=rt2[i+1]) {
5434       emit_loadreg(rs1[i],rs);
5435     }
5436   }
5437   #endif
5438   #ifdef REG_PREFETCH
5439   if(rt1[i]==31&&temp>=0) emit_prefetchreg(temp);
5440   #endif
5441   #ifdef USE_MINI_HT
5442   if(rs1[i]==31) {
5443     do_miniht_load(ht,rh);
5444   }
5445   #endif
5446   //do_cc(i,branch_regs[i].regmap,&adj,-1,TAKEN);
5447   //if(adj) emit_addimm(cc,2*(ccadj[i]+2-adj),cc); // ??? - Shouldn't happen
5448   //assert(adj==0);
5449   emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),HOST_CCREG);
5450   add_stub(CC_STUB,(int)out,jump_vaddr_reg[rs],0,i,-1,TAKEN,0);
5451 #ifdef PCSX
5452   if(itype[i+1]==COP0&&(source[i+1]&0x3f)==0x10)
5453     // special case for RFE
5454     emit_jmp(0);
5455   else
5456 #endif
5457   emit_jns(0);
5458   //load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,-1);
5459   #ifdef USE_MINI_HT
5460   if(rs1[i]==31) {
5461     do_miniht_jump(rs,rh,ht);
5462   }
5463   else
5464   #endif
5465   {
5466     //if(rs!=EAX) emit_mov(rs,EAX);
5467     //emit_jmp((int)jump_vaddr_eax);
5468     emit_jmp(jump_vaddr_reg[rs]);
5469   }
5470   /* Check hash table
5471   temp=!rs;
5472   emit_mov(rs,temp);
5473   emit_shrimm(rs,16,rs);
5474   emit_xor(temp,rs,rs);
5475   emit_movzwl_reg(rs,rs);
5476   emit_shlimm(rs,4,rs);
5477   emit_cmpmem_indexed((int)hash_table,rs,temp);
5478   emit_jne((int)out+14);
5479   emit_readword_indexed((int)hash_table+4,rs,rs);
5480   emit_jmpreg(rs);
5481   emit_cmpmem_indexed((int)hash_table+8,rs,temp);
5482   emit_addimm_no_flags(8,rs);
5483   emit_jeq((int)out-17);
5484   // No hit on hash table, call compiler
5485   emit_pushreg(temp);
5486 //DEBUG >
5487 #ifdef DEBUG_CYCLE_COUNT
5488   emit_readword((int)&last_count,ECX);
5489   emit_add(HOST_CCREG,ECX,HOST_CCREG);
5490   emit_readword((int)&next_interupt,ECX);
5491   emit_writeword(HOST_CCREG,(int)&Count);
5492   emit_sub(HOST_CCREG,ECX,HOST_CCREG);
5493   emit_writeword(ECX,(int)&last_count);
5494 #endif
5495 //DEBUG <
5496   emit_storereg(CCREG,HOST_CCREG);
5497   emit_call((int)get_addr);
5498   emit_loadreg(CCREG,HOST_CCREG);
5499   emit_addimm(ESP,4,ESP);
5500   emit_jmpreg(EAX);*/
5501   #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5502   if(rt1[i]!=31&&i<slen-2&&(((u_int)out)&7)) emit_mov(13,13);
5503   #endif
5504 }
5505
5506 void cjump_assemble(int i,struct regstat *i_regs)
5507 {
5508   signed char *i_regmap=i_regs->regmap;
5509   int cc;
5510   int match;
5511   match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5512   assem_debug("match=%d\n",match);
5513   int s1h,s1l,s2h,s2l;
5514   int prev_cop1_usable=cop1_usable;
5515   int unconditional=0,nop=0;
5516   int only32=0;
5517   int invert=0;
5518   int internal=internal_branch(branch_regs[i].is32,ba[i]);
5519   if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
5520   if(!match) invert=1;
5521   #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5522   if(i>(ba[i]-start)>>2) invert=1;
5523   #endif
5524
5525   if(ooo[i]) {
5526     s1l=get_reg(branch_regs[i].regmap,rs1[i]);
5527     s1h=get_reg(branch_regs[i].regmap,rs1[i]|64);
5528     s2l=get_reg(branch_regs[i].regmap,rs2[i]);
5529     s2h=get_reg(branch_regs[i].regmap,rs2[i]|64);
5530   }
5531   else {
5532     s1l=get_reg(i_regmap,rs1[i]);
5533     s1h=get_reg(i_regmap,rs1[i]|64);
5534     s2l=get_reg(i_regmap,rs2[i]);
5535     s2h=get_reg(i_regmap,rs2[i]|64);
5536   }
5537   if(rs1[i]==0&&rs2[i]==0)
5538   {
5539     if(opcode[i]&1) nop=1;
5540     else unconditional=1;
5541     //assert(opcode[i]!=5);
5542     //assert(opcode[i]!=7);
5543     //assert(opcode[i]!=0x15);
5544     //assert(opcode[i]!=0x17);
5545   }
5546   else if(rs1[i]==0)
5547   {
5548     s1l=s2l;s1h=s2h;
5549     s2l=s2h=-1;
5550     only32=(regs[i].was32>>rs2[i])&1;
5551   }
5552   else if(rs2[i]==0)
5553   {
5554     s2l=s2h=-1;
5555     only32=(regs[i].was32>>rs1[i])&1;
5556   }
5557   else {
5558     only32=(regs[i].was32>>rs1[i])&(regs[i].was32>>rs2[i])&1;
5559   }
5560
5561   if(ooo[i]) {
5562     // Out of order execution (delay slot first)
5563     //printf("OOOE\n");
5564     address_generation(i+1,i_regs,regs[i].regmap_entry);
5565     ds_assemble(i+1,i_regs);
5566     int adj;
5567     uint64_t bc_unneeded=branch_regs[i].u;
5568     uint64_t bc_unneeded_upper=branch_regs[i].uu;
5569     bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
5570     bc_unneeded_upper&=~((1LL<<us1[i])|(1LL<<us2[i]));
5571     bc_unneeded|=1;
5572     bc_unneeded_upper|=1;
5573     wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5574                   bc_unneeded,bc_unneeded_upper);
5575     load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],rs2[i]);
5576     load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5577     cc=get_reg(branch_regs[i].regmap,CCREG);
5578     assert(cc==HOST_CCREG);
5579     if(unconditional)
5580       store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5581     //do_cc(i,branch_regs[i].regmap,&adj,unconditional?ba[i]:-1,unconditional);
5582     //assem_debug("cycle count (adj)\n");
5583     if(unconditional) {
5584       do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5585       if(i!=(ba[i]-start)>>2 || source[i+1]!=0) {
5586         if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
5587         load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5588         if(internal)
5589           assem_debug("branch: internal\n");
5590         else
5591           assem_debug("branch: external\n");
5592         if(internal&&is_ds[(ba[i]-start)>>2]) {
5593           ds_assemble_entry(i);
5594         }
5595         else {
5596           add_to_linker((int)out,ba[i],internal);
5597           emit_jmp(0);
5598         }
5599         #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5600         if(((u_int)out)&7) emit_addnop(0);
5601         #endif
5602       }
5603     }
5604     else if(nop) {
5605       emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),cc);
5606       int jaddr=(int)out;
5607       emit_jns(0);
5608       add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
5609     }
5610     else {
5611       int taken=0,nottaken=0,nottaken1=0;
5612       do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
5613       if(adj&&!invert) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
5614       if(!only32)
5615       {
5616         assert(s1h>=0);
5617         if(opcode[i]==4) // BEQ
5618         {
5619           if(s2h>=0) emit_cmp(s1h,s2h);
5620           else emit_test(s1h,s1h);
5621           nottaken1=(int)out;
5622           emit_jne(1);
5623         }
5624         if(opcode[i]==5) // BNE
5625         {
5626           if(s2h>=0) emit_cmp(s1h,s2h);
5627           else emit_test(s1h,s1h);
5628           if(invert) taken=(int)out;
5629           else add_to_linker((int)out,ba[i],internal);
5630           emit_jne(0);
5631         }
5632         if(opcode[i]==6) // BLEZ
5633         {
5634           emit_test(s1h,s1h);
5635           if(invert) taken=(int)out;
5636           else add_to_linker((int)out,ba[i],internal);
5637           emit_js(0);
5638           nottaken1=(int)out;
5639           emit_jne(1);
5640         }
5641         if(opcode[i]==7) // BGTZ
5642         {
5643           emit_test(s1h,s1h);
5644           nottaken1=(int)out;
5645           emit_js(1);
5646           if(invert) taken=(int)out;
5647           else add_to_linker((int)out,ba[i],internal);
5648           emit_jne(0);
5649         }
5650       } // if(!only32)
5651
5652       //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5653       assert(s1l>=0);
5654       if(opcode[i]==4) // BEQ
5655       {
5656         if(s2l>=0) emit_cmp(s1l,s2l);
5657         else emit_test(s1l,s1l);
5658         if(invert){
5659           nottaken=(int)out;
5660           emit_jne(1);
5661         }else{
5662           add_to_linker((int)out,ba[i],internal);
5663           emit_jeq(0);
5664         }
5665       }
5666       if(opcode[i]==5) // BNE
5667       {
5668         if(s2l>=0) emit_cmp(s1l,s2l);
5669         else emit_test(s1l,s1l);
5670         if(invert){
5671           nottaken=(int)out;
5672           emit_jeq(1);
5673         }else{
5674           add_to_linker((int)out,ba[i],internal);
5675           emit_jne(0);
5676         }
5677       }
5678       if(opcode[i]==6) // BLEZ
5679       {
5680         emit_cmpimm(s1l,1);
5681         if(invert){
5682           nottaken=(int)out;
5683           emit_jge(1);
5684         }else{
5685           add_to_linker((int)out,ba[i],internal);
5686           emit_jl(0);
5687         }
5688       }
5689       if(opcode[i]==7) // BGTZ
5690       {
5691         emit_cmpimm(s1l,1);
5692         if(invert){
5693           nottaken=(int)out;
5694           emit_jl(1);
5695         }else{
5696           add_to_linker((int)out,ba[i],internal);
5697           emit_jge(0);
5698         }
5699       }
5700       if(invert) {
5701         if(taken) set_jump_target(taken,(int)out);
5702         #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5703         if(match&&(!internal||!is_ds[(ba[i]-start)>>2])) {
5704           if(adj) {
5705             emit_addimm(cc,-CLOCK_ADJUST(adj),cc);
5706             add_to_linker((int)out,ba[i],internal);
5707           }else{
5708             emit_addnop(13);
5709             add_to_linker((int)out,ba[i],internal*2);
5710           }
5711           emit_jmp(0);
5712         }else
5713         #endif
5714         {
5715           if(adj) emit_addimm(cc,-CLOCK_ADJUST(adj),cc);
5716           store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5717           load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5718           if(internal)
5719             assem_debug("branch: internal\n");
5720           else
5721             assem_debug("branch: external\n");
5722           if(internal&&is_ds[(ba[i]-start)>>2]) {
5723             ds_assemble_entry(i);
5724           }
5725           else {
5726             add_to_linker((int)out,ba[i],internal);
5727             emit_jmp(0);
5728           }
5729         }
5730         set_jump_target(nottaken,(int)out);
5731       }
5732
5733       if(nottaken1) set_jump_target(nottaken1,(int)out);
5734       if(adj) {
5735         if(!invert) emit_addimm(cc,CLOCK_ADJUST(adj),cc);
5736       }
5737     } // (!unconditional)
5738   } // if(ooo)
5739   else
5740   {
5741     // In-order execution (branch first)
5742     //if(likely[i]) printf("IOL\n");
5743     //else
5744     //printf("IOE\n");
5745     int taken=0,nottaken=0,nottaken1=0;
5746     if(!unconditional&&!nop) {
5747       if(!only32)
5748       {
5749         assert(s1h>=0);
5750         if((opcode[i]&0x2f)==4) // BEQ
5751         {
5752           if(s2h>=0) emit_cmp(s1h,s2h);
5753           else emit_test(s1h,s1h);
5754           nottaken1=(int)out;
5755           emit_jne(2);
5756         }
5757         if((opcode[i]&0x2f)==5) // BNE
5758         {
5759           if(s2h>=0) emit_cmp(s1h,s2h);
5760           else emit_test(s1h,s1h);
5761           taken=(int)out;
5762           emit_jne(1);
5763         }
5764         if((opcode[i]&0x2f)==6) // BLEZ
5765         {
5766           emit_test(s1h,s1h);
5767           taken=(int)out;
5768           emit_js(1);
5769           nottaken1=(int)out;
5770           emit_jne(2);
5771         }
5772         if((opcode[i]&0x2f)==7) // BGTZ
5773         {
5774           emit_test(s1h,s1h);
5775           nottaken1=(int)out;
5776           emit_js(2);
5777           taken=(int)out;
5778           emit_jne(1);
5779         }
5780       } // if(!only32)
5781
5782       //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5783       assert(s1l>=0);
5784       if((opcode[i]&0x2f)==4) // BEQ
5785       {
5786         if(s2l>=0) emit_cmp(s1l,s2l);
5787         else emit_test(s1l,s1l);
5788         nottaken=(int)out;
5789         emit_jne(2);
5790       }
5791       if((opcode[i]&0x2f)==5) // BNE
5792       {
5793         if(s2l>=0) emit_cmp(s1l,s2l);
5794         else emit_test(s1l,s1l);
5795         nottaken=(int)out;
5796         emit_jeq(2);
5797       }
5798       if((opcode[i]&0x2f)==6) // BLEZ
5799       {
5800         emit_cmpimm(s1l,1);
5801         nottaken=(int)out;
5802         emit_jge(2);
5803       }
5804       if((opcode[i]&0x2f)==7) // BGTZ
5805       {
5806         emit_cmpimm(s1l,1);
5807         nottaken=(int)out;
5808         emit_jl(2);
5809       }
5810     } // if(!unconditional)
5811     int adj;
5812     uint64_t ds_unneeded=branch_regs[i].u;
5813     uint64_t ds_unneeded_upper=branch_regs[i].uu;
5814     ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
5815     ds_unneeded_upper&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
5816     if((~ds_unneeded_upper>>rt1[i+1])&1) ds_unneeded_upper&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
5817     ds_unneeded|=1;
5818     ds_unneeded_upper|=1;
5819     // branch taken
5820     if(!nop) {
5821       if(taken) set_jump_target(taken,(int)out);
5822       assem_debug("1:\n");
5823       wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5824                     ds_unneeded,ds_unneeded_upper);
5825       // load regs
5826       load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
5827       address_generation(i+1,&branch_regs[i],0);
5828       load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,INVCP);
5829       ds_assemble(i+1,&branch_regs[i]);
5830       cc=get_reg(branch_regs[i].regmap,CCREG);
5831       if(cc==-1) {
5832         emit_loadreg(CCREG,cc=HOST_CCREG);
5833         // CHECK: Is the following instruction (fall thru) allocated ok?
5834       }
5835       assert(cc==HOST_CCREG);
5836       store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5837       do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
5838       assem_debug("cycle count (adj)\n");
5839       if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
5840       load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5841       if(internal)
5842         assem_debug("branch: internal\n");
5843       else
5844         assem_debug("branch: external\n");
5845       if(internal&&is_ds[(ba[i]-start)>>2]) {
5846         ds_assemble_entry(i);
5847       }
5848       else {
5849         add_to_linker((int)out,ba[i],internal);
5850         emit_jmp(0);
5851       }
5852     }
5853     // branch not taken
5854     cop1_usable=prev_cop1_usable;
5855     if(!unconditional) {
5856       if(nottaken1) set_jump_target(nottaken1,(int)out);
5857       set_jump_target(nottaken,(int)out);
5858       assem_debug("2:\n");
5859       if(!likely[i]) {
5860         wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5861                       ds_unneeded,ds_unneeded_upper);
5862         load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
5863         address_generation(i+1,&branch_regs[i],0);
5864         load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5865         ds_assemble(i+1,&branch_regs[i]);
5866       }
5867       cc=get_reg(branch_regs[i].regmap,CCREG);
5868       if(cc==-1&&!likely[i]) {
5869         // Cycle count isn't in a register, temporarily load it then write it out
5870         emit_loadreg(CCREG,HOST_CCREG);
5871         emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),HOST_CCREG);
5872         int jaddr=(int)out;
5873         emit_jns(0);
5874         add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
5875         emit_storereg(CCREG,HOST_CCREG);
5876       }
5877       else{
5878         cc=get_reg(i_regmap,CCREG);
5879         assert(cc==HOST_CCREG);
5880         emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),cc);
5881         int jaddr=(int)out;
5882         emit_jns(0);
5883         add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
5884       }
5885     }
5886   }
5887 }
5888
5889 void sjump_assemble(int i,struct regstat *i_regs)
5890 {
5891   signed char *i_regmap=i_regs->regmap;
5892   int cc;
5893   int match;
5894   match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5895   assem_debug("smatch=%d\n",match);
5896   int s1h,s1l;
5897   int prev_cop1_usable=cop1_usable;
5898   int unconditional=0,nevertaken=0;
5899   int only32=0;
5900   int invert=0;
5901   int internal=internal_branch(branch_regs[i].is32,ba[i]);
5902   if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
5903   if(!match) invert=1;
5904   #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5905   if(i>(ba[i]-start)>>2) invert=1;
5906   #endif
5907
5908   //if(opcode2[i]>=0x10) return; // FIXME (BxxZAL)
5909   //assert(opcode2[i]<0x10||rs1[i]==0); // FIXME (BxxZAL)
5910
5911   if(ooo[i]) {
5912     s1l=get_reg(branch_regs[i].regmap,rs1[i]);
5913     s1h=get_reg(branch_regs[i].regmap,rs1[i]|64);
5914   }
5915   else {
5916     s1l=get_reg(i_regmap,rs1[i]);
5917     s1h=get_reg(i_regmap,rs1[i]|64);
5918   }
5919   if(rs1[i]==0)
5920   {
5921     if(opcode2[i]&1) unconditional=1;
5922     else nevertaken=1;
5923     // These are never taken (r0 is never less than zero)
5924     //assert(opcode2[i]!=0);
5925     //assert(opcode2[i]!=2);
5926     //assert(opcode2[i]!=0x10);
5927     //assert(opcode2[i]!=0x12);
5928   }
5929   else {
5930     only32=(regs[i].was32>>rs1[i])&1;
5931   }
5932
5933   if(ooo[i]) {
5934     // Out of order execution (delay slot first)
5935     //printf("OOOE\n");
5936     address_generation(i+1,i_regs,regs[i].regmap_entry);
5937     ds_assemble(i+1,i_regs);
5938     int adj;
5939     uint64_t bc_unneeded=branch_regs[i].u;
5940     uint64_t bc_unneeded_upper=branch_regs[i].uu;
5941     bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
5942     bc_unneeded_upper&=~((1LL<<us1[i])|(1LL<<us2[i]));
5943     bc_unneeded|=1;
5944     bc_unneeded_upper|=1;
5945     wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5946                   bc_unneeded,bc_unneeded_upper);
5947     load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],rs1[i]);
5948     load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5949     if(rt1[i]==31) {
5950       int rt,return_address;
5951       rt=get_reg(branch_regs[i].regmap,31);
5952       assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5953       if(rt>=0) {
5954         // Save the PC even if the branch is not taken
5955         return_address=start+i*4+8;
5956         emit_movimm(return_address,rt); // PC into link register
5957         #ifdef IMM_PREFETCH
5958         if(!nevertaken) emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
5959         #endif
5960       }
5961     }
5962     cc=get_reg(branch_regs[i].regmap,CCREG);
5963     assert(cc==HOST_CCREG);
5964     if(unconditional)
5965       store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5966     //do_cc(i,branch_regs[i].regmap,&adj,unconditional?ba[i]:-1,unconditional);
5967     assem_debug("cycle count (adj)\n");
5968     if(unconditional) {
5969       do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5970       if(i!=(ba[i]-start)>>2 || source[i+1]!=0) {
5971         if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
5972         load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5973         if(internal)
5974           assem_debug("branch: internal\n");
5975         else
5976           assem_debug("branch: external\n");
5977         if(internal&&is_ds[(ba[i]-start)>>2]) {
5978           ds_assemble_entry(i);
5979         }
5980         else {
5981           add_to_linker((int)out,ba[i],internal);
5982           emit_jmp(0);
5983         }
5984         #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5985         if(((u_int)out)&7) emit_addnop(0);
5986         #endif
5987       }
5988     }
5989     else if(nevertaken) {
5990       emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),cc);
5991       int jaddr=(int)out;
5992       emit_jns(0);
5993       add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
5994     }
5995     else {
5996       int nottaken=0;
5997       do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
5998       if(adj&&!invert) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
5999       if(!only32)
6000       {
6001         assert(s1h>=0);
6002         if((opcode2[i]&0xf)==0) // BLTZ/BLTZAL
6003         {
6004           emit_test(s1h,s1h);
6005           if(invert){
6006             nottaken=(int)out;
6007             emit_jns(1);
6008           }else{
6009             add_to_linker((int)out,ba[i],internal);
6010             emit_js(0);
6011           }
6012         }
6013         if((opcode2[i]&0xf)==1) // BGEZ/BLTZAL
6014         {
6015           emit_test(s1h,s1h);
6016           if(invert){
6017             nottaken=(int)out;
6018             emit_js(1);
6019           }else{
6020             add_to_linker((int)out,ba[i],internal);
6021             emit_jns(0);
6022           }
6023         }
6024       } // if(!only32)
6025       else
6026       {
6027         assert(s1l>=0);
6028         if((opcode2[i]&0xf)==0) // BLTZ/BLTZAL
6029         {
6030           emit_test(s1l,s1l);
6031           if(invert){
6032             nottaken=(int)out;
6033             emit_jns(1);
6034           }else{
6035             add_to_linker((int)out,ba[i],internal);
6036             emit_js(0);
6037           }
6038         }
6039         if((opcode2[i]&0xf)==1) // BGEZ/BLTZAL
6040         {
6041           emit_test(s1l,s1l);
6042           if(invert){
6043             nottaken=(int)out;
6044             emit_js(1);
6045           }else{
6046             add_to_linker((int)out,ba[i],internal);
6047             emit_jns(0);
6048           }
6049         }
6050       } // if(!only32)
6051
6052       if(invert) {
6053         #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
6054         if(match&&(!internal||!is_ds[(ba[i]-start)>>2])) {
6055           if(adj) {
6056             emit_addimm(cc,-CLOCK_ADJUST(adj),cc);
6057             add_to_linker((int)out,ba[i],internal);
6058           }else{
6059             emit_addnop(13);
6060             add_to_linker((int)out,ba[i],internal*2);
6061           }
6062           emit_jmp(0);
6063         }else
6064         #endif
6065         {
6066           if(adj) emit_addimm(cc,-CLOCK_ADJUST(adj),cc);
6067           store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6068           load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6069           if(internal)
6070             assem_debug("branch: internal\n");
6071           else
6072             assem_debug("branch: external\n");
6073           if(internal&&is_ds[(ba[i]-start)>>2]) {
6074             ds_assemble_entry(i);
6075           }
6076           else {
6077             add_to_linker((int)out,ba[i],internal);
6078             emit_jmp(0);
6079           }
6080         }
6081         set_jump_target(nottaken,(int)out);
6082       }
6083
6084       if(adj) {
6085         if(!invert) emit_addimm(cc,CLOCK_ADJUST(adj),cc);
6086       }
6087     } // (!unconditional)
6088   } // if(ooo)
6089   else
6090   {
6091     // In-order execution (branch first)
6092     //printf("IOE\n");
6093     int nottaken=0;
6094     if(rt1[i]==31) {
6095       int rt,return_address;
6096       rt=get_reg(branch_regs[i].regmap,31);
6097       if(rt>=0) {
6098         // Save the PC even if the branch is not taken
6099         return_address=start+i*4+8;
6100         emit_movimm(return_address,rt); // PC into link register
6101         #ifdef IMM_PREFETCH
6102         emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
6103         #endif
6104       }
6105     }
6106     if(!unconditional) {
6107       //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
6108       if(!only32)
6109       {
6110         assert(s1h>=0);
6111         if((opcode2[i]&0x0d)==0) // BLTZ/BLTZL/BLTZAL/BLTZALL
6112         {
6113           emit_test(s1h,s1h);
6114           nottaken=(int)out;
6115           emit_jns(1);
6116         }
6117         if((opcode2[i]&0x0d)==1) // BGEZ/BGEZL/BGEZAL/BGEZALL
6118         {
6119           emit_test(s1h,s1h);
6120           nottaken=(int)out;
6121           emit_js(1);
6122         }
6123       } // if(!only32)
6124       else
6125       {
6126         assert(s1l>=0);
6127         if((opcode2[i]&0x0d)==0) // BLTZ/BLTZL/BLTZAL/BLTZALL
6128         {
6129           emit_test(s1l,s1l);
6130           nottaken=(int)out;
6131           emit_jns(1);
6132         }
6133         if((opcode2[i]&0x0d)==1) // BGEZ/BGEZL/BGEZAL/BGEZALL
6134         {
6135           emit_test(s1l,s1l);
6136           nottaken=(int)out;
6137           emit_js(1);
6138         }
6139       }
6140     } // if(!unconditional)
6141     int adj;
6142     uint64_t ds_unneeded=branch_regs[i].u;
6143     uint64_t ds_unneeded_upper=branch_regs[i].uu;
6144     ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6145     ds_unneeded_upper&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6146     if((~ds_unneeded_upper>>rt1[i+1])&1) ds_unneeded_upper&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
6147     ds_unneeded|=1;
6148     ds_unneeded_upper|=1;
6149     // branch taken
6150     if(!nevertaken) {
6151       //assem_debug("1:\n");
6152       wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6153                     ds_unneeded,ds_unneeded_upper);
6154       // load regs
6155       load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
6156       address_generation(i+1,&branch_regs[i],0);
6157       load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,INVCP);
6158       ds_assemble(i+1,&branch_regs[i]);
6159       cc=get_reg(branch_regs[i].regmap,CCREG);
6160       if(cc==-1) {
6161         emit_loadreg(CCREG,cc=HOST_CCREG);
6162         // CHECK: Is the following instruction (fall thru) allocated ok?
6163       }
6164       assert(cc==HOST_CCREG);
6165       store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6166       do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
6167       assem_debug("cycle count (adj)\n");
6168       if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
6169       load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6170       if(internal)
6171         assem_debug("branch: internal\n");
6172       else
6173         assem_debug("branch: external\n");
6174       if(internal&&is_ds[(ba[i]-start)>>2]) {
6175         ds_assemble_entry(i);
6176       }
6177       else {
6178         add_to_linker((int)out,ba[i],internal);
6179         emit_jmp(0);
6180       }
6181     }
6182     // branch not taken
6183     cop1_usable=prev_cop1_usable;
6184     if(!unconditional) {
6185       set_jump_target(nottaken,(int)out);
6186       assem_debug("1:\n");
6187       if(!likely[i]) {
6188         wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6189                       ds_unneeded,ds_unneeded_upper);
6190         load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
6191         address_generation(i+1,&branch_regs[i],0);
6192         load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
6193         ds_assemble(i+1,&branch_regs[i]);
6194       }
6195       cc=get_reg(branch_regs[i].regmap,CCREG);
6196       if(cc==-1&&!likely[i]) {
6197         // Cycle count isn't in a register, temporarily load it then write it out
6198         emit_loadreg(CCREG,HOST_CCREG);
6199         emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),HOST_CCREG);
6200         int jaddr=(int)out;
6201         emit_jns(0);
6202         add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
6203         emit_storereg(CCREG,HOST_CCREG);
6204       }
6205       else{
6206         cc=get_reg(i_regmap,CCREG);
6207         assert(cc==HOST_CCREG);
6208         emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),cc);
6209         int jaddr=(int)out;
6210         emit_jns(0);
6211         add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
6212       }
6213     }
6214   }
6215 }
6216
6217 void fjump_assemble(int i,struct regstat *i_regs)
6218 {
6219   signed char *i_regmap=i_regs->regmap;
6220   int cc;
6221   int match;
6222   match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6223   assem_debug("fmatch=%d\n",match);
6224   int fs,cs;
6225   int eaddr;
6226   int invert=0;
6227   int internal=internal_branch(branch_regs[i].is32,ba[i]);
6228   if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
6229   if(!match) invert=1;
6230   #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
6231   if(i>(ba[i]-start)>>2) invert=1;
6232   #endif
6233
6234   if(ooo[i]) {
6235     fs=get_reg(branch_regs[i].regmap,FSREG);
6236     address_generation(i+1,i_regs,regs[i].regmap_entry); // Is this okay?
6237   }
6238   else {
6239     fs=get_reg(i_regmap,FSREG);
6240   }
6241
6242   // Check cop1 unusable
6243   if(!cop1_usable) {
6244     cs=get_reg(i_regmap,CSREG);
6245     assert(cs>=0);
6246     emit_testimm(cs,0x20000000);
6247     eaddr=(int)out;
6248     emit_jeq(0);
6249     add_stub(FP_STUB,eaddr,(int)out,i,cs,(int)i_regs,0,0);
6250     cop1_usable=1;
6251   }
6252
6253   if(ooo[i]) {
6254     // Out of order execution (delay slot first)
6255     //printf("OOOE\n");
6256     ds_assemble(i+1,i_regs);
6257     int adj;
6258     uint64_t bc_unneeded=branch_regs[i].u;
6259     uint64_t bc_unneeded_upper=branch_regs[i].uu;
6260     bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
6261     bc_unneeded_upper&=~((1LL<<us1[i])|(1LL<<us2[i]));
6262     bc_unneeded|=1;
6263     bc_unneeded_upper|=1;
6264     wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6265                   bc_unneeded,bc_unneeded_upper);
6266     load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],rs1[i]);
6267     load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
6268     cc=get_reg(branch_regs[i].regmap,CCREG);
6269     assert(cc==HOST_CCREG);
6270     do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
6271     assem_debug("cycle count (adj)\n");
6272     if(1) {
6273       int nottaken=0;
6274       if(adj&&!invert) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
6275       if(1) {
6276         assert(fs>=0);
6277         emit_testimm(fs,0x800000);
6278         if(source[i]&0x10000) // BC1T
6279         {
6280           if(invert){
6281             nottaken=(int)out;
6282             emit_jeq(1);
6283           }else{
6284             add_to_linker((int)out,ba[i],internal);
6285             emit_jne(0);
6286           }
6287         }
6288         else // BC1F
6289           if(invert){
6290             nottaken=(int)out;
6291             emit_jne(1);
6292           }else{
6293             add_to_linker((int)out,ba[i],internal);
6294             emit_jeq(0);
6295           }
6296         {
6297         }
6298       } // if(!only32)
6299
6300       if(invert) {
6301         if(adj) emit_addimm(cc,-CLOCK_ADJUST(adj),cc);
6302         #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
6303         else if(match) emit_addnop(13);
6304         #endif
6305         store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6306         load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6307         if(internal)
6308           assem_debug("branch: internal\n");
6309         else
6310           assem_debug("branch: external\n");
6311         if(internal&&is_ds[(ba[i]-start)>>2]) {
6312           ds_assemble_entry(i);
6313         }
6314         else {
6315           add_to_linker((int)out,ba[i],internal);
6316           emit_jmp(0);
6317         }
6318         set_jump_target(nottaken,(int)out);
6319       }
6320
6321       if(adj) {
6322         if(!invert) emit_addimm(cc,CLOCK_ADJUST(adj),cc);
6323       }
6324     } // (!unconditional)
6325   } // if(ooo)
6326   else
6327   {
6328     // In-order execution (branch first)
6329     //printf("IOE\n");
6330     int nottaken=0;
6331     if(1) {
6332       //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
6333       if(1) {
6334         assert(fs>=0);
6335         emit_testimm(fs,0x800000);
6336         if(source[i]&0x10000) // BC1T
6337         {
6338           nottaken=(int)out;
6339           emit_jeq(1);
6340         }
6341         else // BC1F
6342         {
6343           nottaken=(int)out;
6344           emit_jne(1);
6345         }
6346       }
6347     } // if(!unconditional)
6348     int adj;
6349     uint64_t ds_unneeded=branch_regs[i].u;
6350     uint64_t ds_unneeded_upper=branch_regs[i].uu;
6351     ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6352     ds_unneeded_upper&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6353     if((~ds_unneeded_upper>>rt1[i+1])&1) ds_unneeded_upper&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
6354     ds_unneeded|=1;
6355     ds_unneeded_upper|=1;
6356     // branch taken
6357     //assem_debug("1:\n");
6358     wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6359                   ds_unneeded,ds_unneeded_upper);
6360     // load regs
6361     load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
6362     address_generation(i+1,&branch_regs[i],0);
6363     load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,INVCP);
6364     ds_assemble(i+1,&branch_regs[i]);
6365     cc=get_reg(branch_regs[i].regmap,CCREG);
6366     if(cc==-1) {
6367       emit_loadreg(CCREG,cc=HOST_CCREG);
6368       // CHECK: Is the following instruction (fall thru) allocated ok?
6369     }
6370     assert(cc==HOST_CCREG);
6371     store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6372     do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
6373     assem_debug("cycle count (adj)\n");
6374     if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
6375     load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6376     if(internal)
6377       assem_debug("branch: internal\n");
6378     else
6379       assem_debug("branch: external\n");
6380     if(internal&&is_ds[(ba[i]-start)>>2]) {
6381       ds_assemble_entry(i);
6382     }
6383     else {
6384       add_to_linker((int)out,ba[i],internal);
6385       emit_jmp(0);
6386     }
6387
6388     // branch not taken
6389     if(1) { // <- FIXME (don't need this)
6390       set_jump_target(nottaken,(int)out);
6391       assem_debug("1:\n");
6392       if(!likely[i]) {
6393         wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6394                       ds_unneeded,ds_unneeded_upper);
6395         load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
6396         address_generation(i+1,&branch_regs[i],0);
6397         load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
6398         ds_assemble(i+1,&branch_regs[i]);
6399       }
6400       cc=get_reg(branch_regs[i].regmap,CCREG);
6401       if(cc==-1&&!likely[i]) {
6402         // Cycle count isn't in a register, temporarily load it then write it out
6403         emit_loadreg(CCREG,HOST_CCREG);
6404         emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),HOST_CCREG);
6405         int jaddr=(int)out;
6406         emit_jns(0);
6407         add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
6408         emit_storereg(CCREG,HOST_CCREG);
6409       }
6410       else{
6411         cc=get_reg(i_regmap,CCREG);
6412         assert(cc==HOST_CCREG);
6413         emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),cc);
6414         int jaddr=(int)out;
6415         emit_jns(0);
6416         add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
6417       }
6418     }
6419   }
6420 }
6421
6422 static void pagespan_assemble(int i,struct regstat *i_regs)
6423 {
6424   int s1l=get_reg(i_regs->regmap,rs1[i]);
6425   int s1h=get_reg(i_regs->regmap,rs1[i]|64);
6426   int s2l=get_reg(i_regs->regmap,rs2[i]);
6427   int s2h=get_reg(i_regs->regmap,rs2[i]|64);
6428   void *nt_branch=NULL;
6429   int taken=0;
6430   int nottaken=0;
6431   int unconditional=0;
6432   if(rs1[i]==0)
6433   {
6434     s1l=s2l;s1h=s2h;
6435     s2l=s2h=-1;
6436   }
6437   else if(rs2[i]==0)
6438   {
6439     s2l=s2h=-1;
6440   }
6441   if((i_regs->is32>>rs1[i])&(i_regs->is32>>rs2[i])&1) {
6442     s1h=s2h=-1;
6443   }
6444   int hr=0;
6445   int addr,alt,ntaddr;
6446   if(i_regs->regmap[HOST_BTREG]<0) {addr=HOST_BTREG;}
6447   else {
6448     while(hr<HOST_REGS)
6449     {
6450       if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
6451          (i_regs->regmap[hr]&63)!=rs1[i] &&
6452          (i_regs->regmap[hr]&63)!=rs2[i] )
6453       {
6454         addr=hr++;break;
6455       }
6456       hr++;
6457     }
6458   }
6459   while(hr<HOST_REGS)
6460   {
6461     if(hr!=EXCLUDE_REG && hr!=HOST_CCREG && hr!=HOST_BTREG &&
6462        (i_regs->regmap[hr]&63)!=rs1[i] &&
6463        (i_regs->regmap[hr]&63)!=rs2[i] )
6464     {
6465       alt=hr++;break;
6466     }
6467     hr++;
6468   }
6469   if((opcode[i]&0x2E)==6) // BLEZ/BGTZ needs another register
6470   {
6471     while(hr<HOST_REGS)
6472     {
6473       if(hr!=EXCLUDE_REG && hr!=HOST_CCREG && hr!=HOST_BTREG &&
6474          (i_regs->regmap[hr]&63)!=rs1[i] &&
6475          (i_regs->regmap[hr]&63)!=rs2[i] )
6476       {
6477         ntaddr=hr;break;
6478       }
6479       hr++;
6480     }
6481   }
6482   assert(hr<HOST_REGS);
6483   if((opcode[i]&0x2e)==4||opcode[i]==0x11) { // BEQ/BNE/BEQL/BNEL/BC1
6484     load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,CCREG,CCREG);
6485   }
6486   emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i]+2),HOST_CCREG);
6487   if(opcode[i]==2) // J
6488   {
6489     unconditional=1;
6490   }
6491   if(opcode[i]==3) // JAL
6492   {
6493     // TODO: mini_ht
6494     int rt=get_reg(i_regs->regmap,31);
6495     emit_movimm(start+i*4+8,rt);
6496     unconditional=1;
6497   }
6498   if(opcode[i]==0&&(opcode2[i]&0x3E)==8) // JR/JALR
6499   {
6500     emit_mov(s1l,addr);
6501     if(opcode2[i]==9) // JALR
6502     {
6503       int rt=get_reg(i_regs->regmap,rt1[i]);
6504       emit_movimm(start+i*4+8,rt);
6505     }
6506   }
6507   if((opcode[i]&0x3f)==4) // BEQ
6508   {
6509     if(rs1[i]==rs2[i])
6510     {
6511       unconditional=1;
6512     }
6513     else
6514     #ifdef HAVE_CMOV_IMM
6515     if(s1h<0) {
6516       if(s2l>=0) emit_cmp(s1l,s2l);
6517       else emit_test(s1l,s1l);
6518       emit_cmov2imm_e_ne_compact(ba[i],start+i*4+8,addr);
6519     }
6520     else
6521     #endif
6522     {
6523       assert(s1l>=0);
6524       emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
6525       if(s1h>=0) {
6526         if(s2h>=0) emit_cmp(s1h,s2h);
6527         else emit_test(s1h,s1h);
6528         emit_cmovne_reg(alt,addr);
6529       }
6530       if(s2l>=0) emit_cmp(s1l,s2l);
6531       else emit_test(s1l,s1l);
6532       emit_cmovne_reg(alt,addr);
6533     }
6534   }
6535   if((opcode[i]&0x3f)==5) // BNE
6536   {
6537     #ifdef HAVE_CMOV_IMM
6538     if(s1h<0) {
6539       if(s2l>=0) emit_cmp(s1l,s2l);
6540       else emit_test(s1l,s1l);
6541       emit_cmov2imm_e_ne_compact(start+i*4+8,ba[i],addr);
6542     }
6543     else
6544     #endif
6545     {
6546       assert(s1l>=0);
6547       emit_mov2imm_compact(start+i*4+8,addr,ba[i],alt);
6548       if(s1h>=0) {
6549         if(s2h>=0) emit_cmp(s1h,s2h);
6550         else emit_test(s1h,s1h);
6551         emit_cmovne_reg(alt,addr);
6552       }
6553       if(s2l>=0) emit_cmp(s1l,s2l);
6554       else emit_test(s1l,s1l);
6555       emit_cmovne_reg(alt,addr);
6556     }
6557   }
6558   if((opcode[i]&0x3f)==0x14) // BEQL
6559   {
6560     if(s1h>=0) {
6561       if(s2h>=0) emit_cmp(s1h,s2h);
6562       else emit_test(s1h,s1h);
6563       nottaken=(int)out;
6564       emit_jne(0);
6565     }
6566     if(s2l>=0) emit_cmp(s1l,s2l);
6567     else emit_test(s1l,s1l);
6568     if(nottaken) set_jump_target(nottaken,(int)out);
6569     nottaken=(int)out;
6570     emit_jne(0);
6571   }
6572   if((opcode[i]&0x3f)==0x15) // BNEL
6573   {
6574     if(s1h>=0) {
6575       if(s2h>=0) emit_cmp(s1h,s2h);
6576       else emit_test(s1h,s1h);
6577       taken=(int)out;
6578       emit_jne(0);
6579     }
6580     if(s2l>=0) emit_cmp(s1l,s2l);
6581     else emit_test(s1l,s1l);
6582     nottaken=(int)out;
6583     emit_jeq(0);
6584     if(taken) set_jump_target(taken,(int)out);
6585   }
6586   if((opcode[i]&0x3f)==6) // BLEZ
6587   {
6588     emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
6589     emit_cmpimm(s1l,1);
6590     if(s1h>=0) emit_mov(addr,ntaddr);
6591     emit_cmovl_reg(alt,addr);
6592     if(s1h>=0) {
6593       emit_test(s1h,s1h);
6594       emit_cmovne_reg(ntaddr,addr);
6595       emit_cmovs_reg(alt,addr);
6596     }
6597   }
6598   if((opcode[i]&0x3f)==7) // BGTZ
6599   {
6600     emit_mov2imm_compact(ba[i],addr,start+i*4+8,ntaddr);
6601     emit_cmpimm(s1l,1);
6602     if(s1h>=0) emit_mov(addr,alt);
6603     emit_cmovl_reg(ntaddr,addr);
6604     if(s1h>=0) {
6605       emit_test(s1h,s1h);
6606       emit_cmovne_reg(alt,addr);
6607       emit_cmovs_reg(ntaddr,addr);
6608     }
6609   }
6610   if((opcode[i]&0x3f)==0x16) // BLEZL
6611   {
6612     assert((opcode[i]&0x3f)!=0x16);
6613   }
6614   if((opcode[i]&0x3f)==0x17) // BGTZL
6615   {
6616     assert((opcode[i]&0x3f)!=0x17);
6617   }
6618   assert(opcode[i]!=1); // BLTZ/BGEZ
6619
6620   //FIXME: Check CSREG
6621   if(opcode[i]==0x11 && opcode2[i]==0x08 ) {
6622     if((source[i]&0x30000)==0) // BC1F
6623     {
6624       emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
6625       emit_testimm(s1l,0x800000);
6626       emit_cmovne_reg(alt,addr);
6627     }
6628     if((source[i]&0x30000)==0x10000) // BC1T
6629     {
6630       emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
6631       emit_testimm(s1l,0x800000);
6632       emit_cmovne_reg(alt,addr);
6633     }
6634     if((source[i]&0x30000)==0x20000) // BC1FL
6635     {
6636       emit_testimm(s1l,0x800000);
6637       nottaken=(int)out;
6638       emit_jne(0);
6639     }
6640     if((source[i]&0x30000)==0x30000) // BC1TL
6641     {
6642       emit_testimm(s1l,0x800000);
6643       nottaken=(int)out;
6644       emit_jeq(0);
6645     }
6646   }
6647
6648   assert(i_regs->regmap[HOST_CCREG]==CCREG);
6649   wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty);
6650   if(likely[i]||unconditional)
6651   {
6652     emit_movimm(ba[i],HOST_BTREG);
6653   }
6654   else if(addr!=HOST_BTREG)
6655   {
6656     emit_mov(addr,HOST_BTREG);
6657   }
6658   void *branch_addr=out;
6659   emit_jmp(0);
6660   int target_addr=start+i*4+5;
6661   void *stub=out;
6662   void *compiled_target_addr=check_addr(target_addr);
6663   emit_extjump_ds((int)branch_addr,target_addr);
6664   if(compiled_target_addr) {
6665     set_jump_target((int)branch_addr,(int)compiled_target_addr);
6666     add_link(target_addr,stub);
6667   }
6668   else set_jump_target((int)branch_addr,(int)stub);
6669   if(likely[i]) {
6670     // Not-taken path
6671     set_jump_target((int)nottaken,(int)out);
6672     wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty);
6673     void *branch_addr=out;
6674     emit_jmp(0);
6675     int target_addr=start+i*4+8;
6676     void *stub=out;
6677     void *compiled_target_addr=check_addr(target_addr);
6678     emit_extjump_ds((int)branch_addr,target_addr);
6679     if(compiled_target_addr) {
6680       set_jump_target((int)branch_addr,(int)compiled_target_addr);
6681       add_link(target_addr,stub);
6682     }
6683     else set_jump_target((int)branch_addr,(int)stub);
6684   }
6685 }
6686
6687 // Assemble the delay slot for the above
6688 static void pagespan_ds()
6689 {
6690   assem_debug("initial delay slot:\n");
6691   u_int vaddr=start+1;
6692   u_int page=get_page(vaddr);
6693   u_int vpage=get_vpage(vaddr);
6694   ll_add(jump_dirty+vpage,vaddr,(void *)out);
6695   do_dirty_stub_ds();
6696   ll_add(jump_in+page,vaddr,(void *)out);
6697   assert(regs[0].regmap_entry[HOST_CCREG]==CCREG);
6698   if(regs[0].regmap[HOST_CCREG]!=CCREG)
6699     wb_register(CCREG,regs[0].regmap_entry,regs[0].wasdirty,regs[0].was32);
6700   if(regs[0].regmap[HOST_BTREG]!=BTREG)
6701     emit_writeword(HOST_BTREG,(int)&branch_target);
6702   load_regs(regs[0].regmap_entry,regs[0].regmap,regs[0].was32,rs1[0],rs2[0]);
6703   address_generation(0,&regs[0],regs[0].regmap_entry);
6704   if(itype[0]==STORE||itype[0]==STORELR||(opcode[0]&0x3b)==0x39||(opcode[0]&0x3b)==0x3a)
6705     load_regs(regs[0].regmap_entry,regs[0].regmap,regs[0].was32,INVCP,INVCP);
6706   cop1_usable=0;
6707   is_delayslot=0;
6708   switch(itype[0]) {
6709     case ALU:
6710       alu_assemble(0,&regs[0]);break;
6711     case IMM16:
6712       imm16_assemble(0,&regs[0]);break;
6713     case SHIFT:
6714       shift_assemble(0,&regs[0]);break;
6715     case SHIFTIMM:
6716       shiftimm_assemble(0,&regs[0]);break;
6717     case LOAD:
6718       load_assemble(0,&regs[0]);break;
6719     case LOADLR:
6720       loadlr_assemble(0,&regs[0]);break;
6721     case STORE:
6722       store_assemble(0,&regs[0]);break;
6723     case STORELR:
6724       storelr_assemble(0,&regs[0]);break;
6725     case COP0:
6726       cop0_assemble(0,&regs[0]);break;
6727     case COP1:
6728       cop1_assemble(0,&regs[0]);break;
6729     case C1LS:
6730       c1ls_assemble(0,&regs[0]);break;
6731     case COP2:
6732       cop2_assemble(0,&regs[0]);break;
6733     case C2LS:
6734       c2ls_assemble(0,&regs[0]);break;
6735     case C2OP:
6736       c2op_assemble(0,&regs[0]);break;
6737     case FCONV:
6738       fconv_assemble(0,&regs[0]);break;
6739     case FLOAT:
6740       float_assemble(0,&regs[0]);break;
6741     case FCOMP:
6742       fcomp_assemble(0,&regs[0]);break;
6743     case MULTDIV:
6744       multdiv_assemble(0,&regs[0]);break;
6745     case MOV:
6746       mov_assemble(0,&regs[0]);break;
6747     case SYSCALL:
6748     case HLECALL:
6749     case INTCALL:
6750     case SPAN:
6751     case UJUMP:
6752     case RJUMP:
6753     case CJUMP:
6754     case SJUMP:
6755     case FJUMP:
6756       printf("Jump in the delay slot.  This is probably a bug.\n");
6757   }
6758   int btaddr=get_reg(regs[0].regmap,BTREG);
6759   if(btaddr<0) {
6760     btaddr=get_reg(regs[0].regmap,-1);
6761     emit_readword((int)&branch_target,btaddr);
6762   }
6763   assert(btaddr!=HOST_CCREG);
6764   if(regs[0].regmap[HOST_CCREG]!=CCREG) emit_loadreg(CCREG,HOST_CCREG);
6765 #ifdef HOST_IMM8
6766   emit_movimm(start+4,HOST_TEMPREG);
6767   emit_cmp(btaddr,HOST_TEMPREG);
6768 #else
6769   emit_cmpimm(btaddr,start+4);
6770 #endif
6771   int branch=(int)out;
6772   emit_jeq(0);
6773   store_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,-1);
6774   emit_jmp(jump_vaddr_reg[btaddr]);
6775   set_jump_target(branch,(int)out);
6776   store_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,start+4);
6777   load_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,start+4);
6778 }
6779
6780 // Basic liveness analysis for MIPS registers
6781 void unneeded_registers(int istart,int iend,int r)
6782 {
6783   int i;
6784   uint64_t u,uu,gte_u,b,bu,gte_bu;
6785   uint64_t temp_u,temp_uu,temp_gte_u=0;
6786   uint64_t tdep;
6787   uint64_t gte_u_unknown=0;
6788   if(new_dynarec_hacks&NDHACK_GTE_UNNEEDED)
6789     gte_u_unknown=~0ll;
6790   if(iend==slen-1) {
6791     u=1;uu=1;
6792     gte_u=gte_u_unknown;
6793   }else{
6794     u=unneeded_reg[iend+1];
6795     uu=unneeded_reg_upper[iend+1];
6796     u=1;uu=1;
6797     gte_u=gte_unneeded[iend+1];
6798   }
6799
6800   for (i=iend;i>=istart;i--)
6801   {
6802     //printf("unneeded registers i=%d (%d,%d) r=%d\n",i,istart,iend,r);
6803     if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
6804     {
6805       // If subroutine call, flag return address as a possible branch target
6806       if(rt1[i]==31 && i<slen-2) bt[i+2]=1;
6807
6808       if(ba[i]<start || ba[i]>=(start+slen*4))
6809       {
6810         // Branch out of this block, flush all regs
6811         u=1;
6812         uu=1;
6813         gte_u=gte_u_unknown;
6814         /* Hexagon hack
6815         if(itype[i]==UJUMP&&rt1[i]==31)
6816         {
6817           uu=u=0x300C00F; // Discard at, v0-v1, t6-t9
6818         }
6819         if(itype[i]==RJUMP&&rs1[i]==31)
6820         {
6821           uu=u=0x300C0F3; // Discard at, a0-a3, t6-t9
6822         }
6823         if(start>0x80000400&&start<0x80000000+RAM_SIZE) {
6824           if(itype[i]==UJUMP&&rt1[i]==31)
6825           {
6826             //uu=u=0x30300FF0FLL; // Discard at, v0-v1, t0-t9, lo, hi
6827             uu=u=0x300FF0F; // Discard at, v0-v1, t0-t9
6828           }
6829           if(itype[i]==RJUMP&&rs1[i]==31)
6830           {
6831             //uu=u=0x30300FFF3LL; // Discard at, a0-a3, t0-t9, lo, hi
6832             uu=u=0x300FFF3; // Discard at, a0-a3, t0-t9
6833           }
6834         }*/
6835         branch_unneeded_reg[i]=u;
6836         branch_unneeded_reg_upper[i]=uu;
6837         // Merge in delay slot
6838         tdep=(~uu>>rt1[i+1])&1;
6839         u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6840         uu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6841         u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6842         uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6843         uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6844         u|=1;uu|=1;
6845         gte_u|=gte_rt[i+1];
6846         gte_u&=~gte_rs[i+1];
6847         // If branch is "likely" (and conditional)
6848         // then we skip the delay slot on the fall-thru path
6849         if(likely[i]) {
6850           if(i<slen-1) {
6851             u&=unneeded_reg[i+2];
6852             uu&=unneeded_reg_upper[i+2];
6853             gte_u&=gte_unneeded[i+2];
6854           }
6855           else
6856           {
6857             u=1;
6858             uu=1;
6859             gte_u=gte_u_unknown;
6860           }
6861         }
6862       }
6863       else
6864       {
6865         // Internal branch, flag target
6866         bt[(ba[i]-start)>>2]=1;
6867         if(ba[i]<=start+i*4) {
6868           // Backward branch
6869           if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
6870           {
6871             // Unconditional branch
6872             temp_u=1;temp_uu=1;
6873             temp_gte_u=0;
6874           } else {
6875             // Conditional branch (not taken case)
6876             temp_u=unneeded_reg[i+2];
6877             temp_uu=unneeded_reg_upper[i+2];
6878             temp_gte_u&=gte_unneeded[i+2];
6879           }
6880           // Merge in delay slot
6881           tdep=(~temp_uu>>rt1[i+1])&1;
6882           temp_u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6883           temp_uu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6884           temp_u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6885           temp_uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6886           temp_uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6887           temp_u|=1;temp_uu|=1;
6888           temp_gte_u|=gte_rt[i+1];
6889           temp_gte_u&=~gte_rs[i+1];
6890           // If branch is "likely" (and conditional)
6891           // then we skip the delay slot on the fall-thru path
6892           if(likely[i]) {
6893             if(i<slen-1) {
6894               temp_u&=unneeded_reg[i+2];
6895               temp_uu&=unneeded_reg_upper[i+2];
6896               temp_gte_u&=gte_unneeded[i+2];
6897             }
6898             else
6899             {
6900               temp_u=1;
6901               temp_uu=1;
6902               temp_gte_u=gte_u_unknown;
6903             }
6904           }
6905           tdep=(~temp_uu>>rt1[i])&1;
6906           temp_u|=(1LL<<rt1[i])|(1LL<<rt2[i]);
6907           temp_uu|=(1LL<<rt1[i])|(1LL<<rt2[i]);
6908           temp_u&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
6909           temp_uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
6910           temp_uu&=~((tdep<<dep1[i])|(tdep<<dep2[i]));
6911           temp_u|=1;temp_uu|=1;
6912           temp_gte_u|=gte_rt[i];
6913           temp_gte_u&=~gte_rs[i];
6914           unneeded_reg[i]=temp_u;
6915           unneeded_reg_upper[i]=temp_uu;
6916           gte_unneeded[i]=temp_gte_u;
6917           // Only go three levels deep.  This recursion can take an
6918           // excessive amount of time if there are a lot of nested loops.
6919           if(r<2) {
6920             unneeded_registers((ba[i]-start)>>2,i-1,r+1);
6921           }else{
6922             unneeded_reg[(ba[i]-start)>>2]=1;
6923             unneeded_reg_upper[(ba[i]-start)>>2]=1;
6924             gte_unneeded[(ba[i]-start)>>2]=gte_u_unknown;
6925           }
6926         } /*else*/ if(1) {
6927           if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
6928           {
6929             // Unconditional branch
6930             u=unneeded_reg[(ba[i]-start)>>2];
6931             uu=unneeded_reg_upper[(ba[i]-start)>>2];
6932             gte_u=gte_unneeded[(ba[i]-start)>>2];
6933             branch_unneeded_reg[i]=u;
6934             branch_unneeded_reg_upper[i]=uu;
6935         //u=1;
6936         //uu=1;
6937         //branch_unneeded_reg[i]=u;
6938         //branch_unneeded_reg_upper[i]=uu;
6939             // Merge in delay slot
6940             tdep=(~uu>>rt1[i+1])&1;
6941             u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6942             uu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6943             u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6944             uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6945             uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6946             u|=1;uu|=1;
6947             gte_u|=gte_rt[i+1];
6948             gte_u&=~gte_rs[i+1];
6949           } else {
6950             // Conditional branch
6951             b=unneeded_reg[(ba[i]-start)>>2];
6952             bu=unneeded_reg_upper[(ba[i]-start)>>2];
6953             gte_bu=gte_unneeded[(ba[i]-start)>>2];
6954             branch_unneeded_reg[i]=b;
6955             branch_unneeded_reg_upper[i]=bu;
6956         //b=1;
6957         //bu=1;
6958         //branch_unneeded_reg[i]=b;
6959         //branch_unneeded_reg_upper[i]=bu;
6960             // Branch delay slot
6961             tdep=(~uu>>rt1[i+1])&1;
6962             b|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6963             bu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6964             b&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6965             bu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6966             bu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6967             b|=1;bu|=1;
6968             gte_bu|=gte_rt[i+1];
6969             gte_bu&=~gte_rs[i+1];
6970             // If branch is "likely" then we skip the
6971             // delay slot on the fall-thru path
6972             if(likely[i]) {
6973               u=b;
6974               uu=bu;
6975               gte_u=gte_bu;
6976               if(i<slen-1) {
6977                 u&=unneeded_reg[i+2];
6978                 uu&=unneeded_reg_upper[i+2];
6979                 gte_u&=gte_unneeded[i+2];
6980         //u=1;
6981         //uu=1;
6982               }
6983             } else {
6984               u&=b;
6985               uu&=bu;
6986               gte_u&=gte_bu;
6987         //u=1;
6988         //uu=1;
6989             }
6990             if(i<slen-1) {
6991               branch_unneeded_reg[i]&=unneeded_reg[i+2];
6992               branch_unneeded_reg_upper[i]&=unneeded_reg_upper[i+2];
6993         //branch_unneeded_reg[i]=1;
6994         //branch_unneeded_reg_upper[i]=1;
6995             } else {
6996               branch_unneeded_reg[i]=1;
6997               branch_unneeded_reg_upper[i]=1;
6998             }
6999           }
7000         }
7001       }
7002     }
7003     else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
7004     {
7005       // SYSCALL instruction (software interrupt)
7006       u=1;
7007       uu=1;
7008     }
7009     else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
7010     {
7011       // ERET instruction (return from interrupt)
7012       u=1;
7013       uu=1;
7014     }
7015     //u=uu=1; // DEBUG
7016     tdep=(~uu>>rt1[i])&1;
7017     // Written registers are unneeded
7018     u|=1LL<<rt1[i];
7019     u|=1LL<<rt2[i];
7020     uu|=1LL<<rt1[i];
7021     uu|=1LL<<rt2[i];
7022     gte_u|=gte_rt[i];
7023     // Accessed registers are needed
7024     u&=~(1LL<<rs1[i]);
7025     u&=~(1LL<<rs2[i]);
7026     uu&=~(1LL<<us1[i]);
7027     uu&=~(1LL<<us2[i]);
7028     gte_u&=~gte_rs[i];
7029     if(gte_rs[i]&&rt1[i]&&(unneeded_reg[i+1]&(1ll<<rt1[i])))
7030       gte_u|=gte_rs[i];  // MFC2/CFC2 to dead register, unneeded
7031     // Source-target dependencies
7032     uu&=~(tdep<<dep1[i]);
7033     uu&=~(tdep<<dep2[i]);
7034     // R0 is always unneeded
7035     u|=1;uu|=1;
7036     // Save it
7037     unneeded_reg[i]=u;
7038     unneeded_reg_upper[i]=uu;
7039     gte_unneeded[i]=gte_u;
7040     /*
7041     printf("ur (%d,%d) %x: ",istart,iend,start+i*4);
7042     printf("U:");
7043     int r;
7044     for(r=1;r<=CCREG;r++) {
7045       if((unneeded_reg[i]>>r)&1) {
7046         if(r==HIREG) printf(" HI");
7047         else if(r==LOREG) printf(" LO");
7048         else printf(" r%d",r);
7049       }
7050     }
7051     printf(" UU:");
7052     for(r=1;r<=CCREG;r++) {
7053       if(((unneeded_reg_upper[i]&~unneeded_reg[i])>>r)&1) {
7054         if(r==HIREG) printf(" HI");
7055         else if(r==LOREG) printf(" LO");
7056         else printf(" r%d",r);
7057       }
7058     }
7059     printf("\n");*/
7060   }
7061 #ifdef FORCE32
7062   for (i=iend;i>=istart;i--)
7063   {
7064     unneeded_reg_upper[i]=branch_unneeded_reg_upper[i]=-1LL;
7065   }
7066 #endif
7067 }
7068
7069 // Identify registers which are likely to contain 32-bit values
7070 // This is used to predict whether any branches will jump to a
7071 // location with 64-bit values in registers.
7072 static void provisional_32bit()
7073 {
7074   int i,j;
7075   uint64_t is32=1;
7076   uint64_t lastbranch=1;
7077
7078   for(i=0;i<slen;i++)
7079   {
7080     if(i>0) {
7081       if(itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP) {
7082         if(i>1) is32=lastbranch;
7083         else is32=1;
7084       }
7085     }
7086     if(i>1)
7087     {
7088       if(itype[i-2]==CJUMP||itype[i-2]==SJUMP||itype[i-2]==FJUMP) {
7089         if(likely[i-2]) {
7090           if(i>2) is32=lastbranch;
7091           else is32=1;
7092         }
7093       }
7094       if((opcode[i-2]&0x2f)==0x05) // BNE/BNEL
7095       {
7096         if(rs1[i-2]==0||rs2[i-2]==0)
7097         {
7098           if(rs1[i-2]) {
7099             is32|=1LL<<rs1[i-2];
7100           }
7101           if(rs2[i-2]) {
7102             is32|=1LL<<rs2[i-2];
7103           }
7104         }
7105       }
7106     }
7107     // If something jumps here with 64-bit values
7108     // then promote those registers to 64 bits
7109     if(bt[i])
7110     {
7111       uint64_t temp_is32=is32;
7112       for(j=i-1;j>=0;j--)
7113       {
7114         if(ba[j]==start+i*4)
7115           //temp_is32&=branch_regs[j].is32;
7116           temp_is32&=p32[j];
7117       }
7118       for(j=i;j<slen;j++)
7119       {
7120         if(ba[j]==start+i*4)
7121           temp_is32=1;
7122       }
7123       is32=temp_is32;
7124     }
7125     int type=itype[i];
7126     int op=opcode[i];
7127     int op2=opcode2[i];
7128     int rt=rt1[i];
7129     int s1=rs1[i];
7130     int s2=rs2[i];
7131     if(type==UJUMP||type==RJUMP||type==CJUMP||type==SJUMP||type==FJUMP) {
7132       // Branches don't write registers, consider the delay slot instead.
7133       type=itype[i+1];
7134       op=opcode[i+1];
7135       op2=opcode2[i+1];
7136       rt=rt1[i+1];
7137       s1=rs1[i+1];
7138       s2=rs2[i+1];
7139       lastbranch=is32;
7140     }
7141     switch(type) {
7142       case LOAD:
7143         if(opcode[i]==0x27||opcode[i]==0x37|| // LWU/LD
7144            opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
7145           is32&=~(1LL<<rt);
7146         else
7147           is32|=1LL<<rt;
7148         break;
7149       case STORE:
7150       case STORELR:
7151         break;
7152       case LOADLR:
7153         if(op==0x1a||op==0x1b) is32&=~(1LL<<rt); // LDR/LDL
7154         if(op==0x22) is32|=1LL<<rt; // LWL
7155         break;
7156       case IMM16:
7157         if (op==0x08||op==0x09|| // ADDI/ADDIU
7158             op==0x0a||op==0x0b|| // SLTI/SLTIU
7159             op==0x0c|| // ANDI
7160             op==0x0f)  // LUI
7161         {
7162           is32|=1LL<<rt;
7163         }
7164         if(op==0x18||op==0x19) { // DADDI/DADDIU
7165           is32&=~(1LL<<rt);
7166           //if(imm[i]==0)
7167           //  is32|=((is32>>s1)&1LL)<<rt;
7168         }
7169         if(op==0x0d||op==0x0e) { // ORI/XORI
7170           uint64_t sr=((is32>>s1)&1LL);
7171           is32&=~(1LL<<rt);
7172           is32|=sr<<rt;
7173         }
7174         break;
7175       case UJUMP:
7176         break;
7177       case RJUMP:
7178         break;
7179       case CJUMP:
7180         break;
7181       case SJUMP:
7182         break;
7183       case FJUMP:
7184         break;
7185       case ALU:
7186         if(op2>=0x20&&op2<=0x23) { // ADD/ADDU/SUB/SUBU
7187           is32|=1LL<<rt;
7188         }
7189         if(op2==0x2a||op2==0x2b) { // SLT/SLTU
7190           is32|=1LL<<rt;
7191         }
7192         else if(op2>=0x24&&op2<=0x27) { // AND/OR/XOR/NOR
7193           uint64_t sr=((is32>>s1)&(is32>>s2)&1LL);
7194           is32&=~(1LL<<rt);
7195           is32|=sr<<rt;
7196         }
7197         else if(op2>=0x2c&&op2<=0x2d) { // DADD/DADDU
7198           if(s1==0&&s2==0) {
7199             is32|=1LL<<rt;
7200           }
7201           else if(s2==0) {
7202             uint64_t sr=((is32>>s1)&1LL);
7203             is32&=~(1LL<<rt);
7204             is32|=sr<<rt;
7205           }
7206           else if(s1==0) {
7207             uint64_t sr=((is32>>s2)&1LL);
7208             is32&=~(1LL<<rt);
7209             is32|=sr<<rt;
7210           }
7211           else {
7212             is32&=~(1LL<<rt);
7213           }
7214         }
7215         else if(op2>=0x2e&&op2<=0x2f) { // DSUB/DSUBU
7216           if(s1==0&&s2==0) {
7217             is32|=1LL<<rt;
7218           }
7219           else if(s2==0) {
7220             uint64_t sr=((is32>>s1)&1LL);
7221             is32&=~(1LL<<rt);
7222             is32|=sr<<rt;
7223           }
7224           else {
7225             is32&=~(1LL<<rt);
7226           }
7227         }
7228         break;
7229       case MULTDIV:
7230         if (op2>=0x1c&&op2<=0x1f) { // DMULT/DMULTU/DDIV/DDIVU
7231           is32&=~((1LL<<HIREG)|(1LL<<LOREG));
7232         }
7233         else {
7234           is32|=(1LL<<HIREG)|(1LL<<LOREG);
7235         }
7236         break;
7237       case MOV:
7238         {
7239           uint64_t sr=((is32>>s1)&1LL);
7240           is32&=~(1LL<<rt);
7241           is32|=sr<<rt;
7242         }
7243         break;
7244       case SHIFT:
7245         if(op2>=0x14&&op2<=0x17) is32&=~(1LL<<rt); // DSLLV/DSRLV/DSRAV
7246         else is32|=1LL<<rt; // SLLV/SRLV/SRAV
7247         break;
7248       case SHIFTIMM:
7249         is32|=1LL<<rt;
7250         // DSLL/DSRL/DSRA/DSLL32/DSRL32 but not DSRA32 have 64-bit result
7251         if(op2>=0x38&&op2<0x3f) is32&=~(1LL<<rt);
7252         break;
7253       case COP0:
7254         if(op2==0) is32|=1LL<<rt; // MFC0
7255         break;
7256       case COP1:
7257       case COP2:
7258         if(op2==0) is32|=1LL<<rt; // MFC1
7259         if(op2==1) is32&=~(1LL<<rt); // DMFC1
7260         if(op2==2) is32|=1LL<<rt; // CFC1
7261         break;
7262       case C1LS:
7263       case C2LS:
7264         break;
7265       case FLOAT:
7266       case FCONV:
7267         break;
7268       case FCOMP:
7269         break;
7270       case C2OP:
7271       case SYSCALL:
7272       case HLECALL:
7273         break;
7274       default:
7275         break;
7276     }
7277     is32|=1;
7278     p32[i]=is32;
7279
7280     if(i>0)
7281     {
7282       if(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)
7283       {
7284         if(rt1[i-1]==31) // JAL/JALR
7285         {
7286           // Subroutine call will return here, don't alloc any registers
7287           is32=1;
7288         }
7289         else if(i+1<slen)
7290         {
7291           // Internal branch will jump here, match registers to caller
7292           is32=0x3FFFFFFFFLL;
7293         }
7294       }
7295     }
7296   }
7297 }
7298
7299 // Identify registers which may be assumed to contain 32-bit values
7300 // and where optimizations will rely on this.
7301 // This is used to determine whether backward branches can safely
7302 // jump to a location with 64-bit values in registers.
7303 static void provisional_r32()
7304 {
7305   u_int r32=0;
7306   int i;
7307
7308   for (i=slen-1;i>=0;i--)
7309   {
7310     int hr;
7311     if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
7312     {
7313       if(ba[i]<start || ba[i]>=(start+slen*4))
7314       {
7315         // Branch out of this block, don't need anything
7316         r32=0;
7317       }
7318       else
7319       {
7320         // Internal branch
7321         // Need whatever matches the target
7322         // (and doesn't get overwritten by the delay slot instruction)
7323         r32=0;
7324         int t=(ba[i]-start)>>2;
7325         if(ba[i]>start+i*4) {
7326           // Forward branch
7327           //if(!(requires_32bit[t]&~regs[i].was32))
7328           //  r32|=requires_32bit[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
7329           if(!(pr32[t]&~regs[i].was32))
7330             r32|=pr32[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
7331         }else{
7332           // Backward branch
7333           if(!(regs[t].was32&~unneeded_reg_upper[t]&~regs[i].was32))
7334             r32|=regs[t].was32&~unneeded_reg_upper[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
7335         }
7336       }
7337       // Conditional branch may need registers for following instructions
7338       if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
7339       {
7340         if(i<slen-2) {
7341           //r32|=requires_32bit[i+2];
7342           r32|=pr32[i+2];
7343           r32&=regs[i].was32;
7344           // Mark this address as a branch target since it may be called
7345           // upon return from interrupt
7346           //bt[i+2]=1;
7347         }
7348       }
7349       // Merge in delay slot
7350       if(!likely[i]) {
7351         // These are overwritten unless the branch is "likely"
7352         // and the delay slot is nullified if not taken
7353         r32&=~(1LL<<rt1[i+1]);
7354         r32&=~(1LL<<rt2[i+1]);
7355       }
7356       // Assume these are needed (delay slot)
7357       if(us1[i+1]>0)
7358       {
7359         if((regs[i].was32>>us1[i+1])&1) r32|=1LL<<us1[i+1];
7360       }
7361       if(us2[i+1]>0)
7362       {
7363         if((regs[i].was32>>us2[i+1])&1) r32|=1LL<<us2[i+1];
7364       }
7365       if(dep1[i+1]&&!((unneeded_reg_upper[i]>>dep1[i+1])&1))
7366       {
7367         if((regs[i].was32>>dep1[i+1])&1) r32|=1LL<<dep1[i+1];
7368       }
7369       if(dep2[i+1]&&!((unneeded_reg_upper[i]>>dep2[i+1])&1))
7370       {
7371         if((regs[i].was32>>dep2[i+1])&1) r32|=1LL<<dep2[i+1];
7372       }
7373     }
7374     else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
7375     {
7376       // SYSCALL instruction (software interrupt)
7377       r32=0;
7378     }
7379     else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
7380     {
7381       // ERET instruction (return from interrupt)
7382       r32=0;
7383     }
7384     // Check 32 bits
7385     r32&=~(1LL<<rt1[i]);
7386     r32&=~(1LL<<rt2[i]);
7387     if(us1[i]>0)
7388     {
7389       if((regs[i].was32>>us1[i])&1) r32|=1LL<<us1[i];
7390     }
7391     if(us2[i]>0)
7392     {
7393       if((regs[i].was32>>us2[i])&1) r32|=1LL<<us2[i];
7394     }
7395     if(dep1[i]&&!((unneeded_reg_upper[i]>>dep1[i])&1))
7396     {
7397       if((regs[i].was32>>dep1[i])&1) r32|=1LL<<dep1[i];
7398     }
7399     if(dep2[i]&&!((unneeded_reg_upper[i]>>dep2[i])&1))
7400     {
7401       if((regs[i].was32>>dep2[i])&1) r32|=1LL<<dep2[i];
7402     }
7403     //requires_32bit[i]=r32;
7404     pr32[i]=r32;
7405
7406     // Dirty registers which are 32-bit, require 32-bit input
7407     // as they will be written as 32-bit values
7408     for(hr=0;hr<HOST_REGS;hr++)
7409     {
7410       if(regs[i].regmap_entry[hr]>0&&regs[i].regmap_entry[hr]<64) {
7411         if((regs[i].was32>>regs[i].regmap_entry[hr])&(regs[i].wasdirty>>hr)&1) {
7412           if(!((unneeded_reg_upper[i]>>regs[i].regmap_entry[hr])&1))
7413           pr32[i]|=1LL<<regs[i].regmap_entry[hr];
7414           //requires_32bit[i]|=1LL<<regs[i].regmap_entry[hr];
7415         }
7416       }
7417     }
7418   }
7419 }
7420
7421 // Write back dirty registers as soon as we will no longer modify them,
7422 // so that we don't end up with lots of writes at the branches.
7423 void clean_registers(int istart,int iend,int wr)
7424 {
7425   int i;
7426   int r;
7427   u_int will_dirty_i,will_dirty_next,temp_will_dirty;
7428   u_int wont_dirty_i,wont_dirty_next,temp_wont_dirty;
7429   if(iend==slen-1) {
7430     will_dirty_i=will_dirty_next=0;
7431     wont_dirty_i=wont_dirty_next=0;
7432   }else{
7433     will_dirty_i=will_dirty_next=will_dirty[iend+1];
7434     wont_dirty_i=wont_dirty_next=wont_dirty[iend+1];
7435   }
7436   for (i=iend;i>=istart;i--)
7437   {
7438     if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
7439     {
7440       if(ba[i]<start || ba[i]>=(start+slen*4))
7441       {
7442         // Branch out of this block, flush all regs
7443         if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
7444         {
7445           // Unconditional branch
7446           will_dirty_i=0;
7447           wont_dirty_i=0;
7448           // Merge in delay slot (will dirty)
7449           for(r=0;r<HOST_REGS;r++) {
7450             if(r!=EXCLUDE_REG) {
7451               if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7452               if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7453               if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7454               if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7455               if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7456               if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7457               if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7458               if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7459               if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7460               if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7461               if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7462               if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7463               if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7464               if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7465             }
7466           }
7467         }
7468         else
7469         {
7470           // Conditional branch
7471           will_dirty_i=0;
7472           wont_dirty_i=wont_dirty_next;
7473           // Merge in delay slot (will dirty)
7474           for(r=0;r<HOST_REGS;r++) {
7475             if(r!=EXCLUDE_REG) {
7476               if(!likely[i]) {
7477                 // Might not dirty if likely branch is not taken
7478                 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7479                 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7480                 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7481                 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7482                 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7483                 if(branch_regs[i].regmap[r]==0) will_dirty_i&=~(1<<r);
7484                 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7485                 //if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7486                 //if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7487                 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7488                 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7489                 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7490                 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7491                 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7492               }
7493             }
7494           }
7495         }
7496         // Merge in delay slot (wont dirty)
7497         for(r=0;r<HOST_REGS;r++) {
7498           if(r!=EXCLUDE_REG) {
7499             if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7500             if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7501             if((regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7502             if((regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7503             if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7504             if((branch_regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7505             if((branch_regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7506             if((branch_regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7507             if((branch_regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7508             if(branch_regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7509           }
7510         }
7511         if(wr) {
7512           #ifndef DESTRUCTIVE_WRITEBACK
7513           branch_regs[i].dirty&=wont_dirty_i;
7514           #endif
7515           branch_regs[i].dirty|=will_dirty_i;
7516         }
7517       }
7518       else
7519       {
7520         // Internal branch
7521         if(ba[i]<=start+i*4) {
7522           // Backward branch
7523           if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
7524           {
7525             // Unconditional branch
7526             temp_will_dirty=0;
7527             temp_wont_dirty=0;
7528             // Merge in delay slot (will dirty)
7529             for(r=0;r<HOST_REGS;r++) {
7530               if(r!=EXCLUDE_REG) {
7531                 if((branch_regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7532                 if((branch_regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7533                 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7534                 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7535                 if((branch_regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7536                 if(branch_regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
7537                 if(branch_regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7538                 if((regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7539                 if((regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7540                 if((regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7541                 if((regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7542                 if((regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7543                 if(regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
7544                 if(regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7545               }
7546             }
7547           } else {
7548             // Conditional branch (not taken case)
7549             temp_will_dirty=will_dirty_next;
7550             temp_wont_dirty=wont_dirty_next;
7551             // Merge in delay slot (will dirty)
7552             for(r=0;r<HOST_REGS;r++) {
7553               if(r!=EXCLUDE_REG) {
7554                 if(!likely[i]) {
7555                   // Will not dirty if likely branch is not taken
7556                   if((branch_regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7557                   if((branch_regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7558                   if((branch_regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7559                   if((branch_regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7560                   if((branch_regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7561                   if(branch_regs[i].regmap[r]==0) temp_will_dirty&=~(1<<r);
7562                   if(branch_regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7563                   //if((regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7564                   //if((regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7565                   if((regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7566                   if((regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7567                   if((regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7568                   if(regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
7569                   if(regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7570                 }
7571               }
7572             }
7573           }
7574           // Merge in delay slot (wont dirty)
7575           for(r=0;r<HOST_REGS;r++) {
7576             if(r!=EXCLUDE_REG) {
7577               if((regs[i].regmap[r]&63)==rt1[i]) temp_wont_dirty|=1<<r;
7578               if((regs[i].regmap[r]&63)==rt2[i]) temp_wont_dirty|=1<<r;
7579               if((regs[i].regmap[r]&63)==rt1[i+1]) temp_wont_dirty|=1<<r;
7580               if((regs[i].regmap[r]&63)==rt2[i+1]) temp_wont_dirty|=1<<r;
7581               if(regs[i].regmap[r]==CCREG) temp_wont_dirty|=1<<r;
7582               if((branch_regs[i].regmap[r]&63)==rt1[i]) temp_wont_dirty|=1<<r;
7583               if((branch_regs[i].regmap[r]&63)==rt2[i]) temp_wont_dirty|=1<<r;
7584               if((branch_regs[i].regmap[r]&63)==rt1[i+1]) temp_wont_dirty|=1<<r;
7585               if((branch_regs[i].regmap[r]&63)==rt2[i+1]) temp_wont_dirty|=1<<r;
7586               if(branch_regs[i].regmap[r]==CCREG) temp_wont_dirty|=1<<r;
7587             }
7588           }
7589           // Deal with changed mappings
7590           if(i<iend) {
7591             for(r=0;r<HOST_REGS;r++) {
7592               if(r!=EXCLUDE_REG) {
7593                 if(regs[i].regmap[r]!=regmap_pre[i][r]) {
7594                   temp_will_dirty&=~(1<<r);
7595                   temp_wont_dirty&=~(1<<r);
7596                   if((regmap_pre[i][r]&63)>0 && (regmap_pre[i][r]&63)<34) {
7597                     temp_will_dirty|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7598                     temp_wont_dirty|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7599                   } else {
7600                     temp_will_dirty|=1<<r;
7601                     temp_wont_dirty|=1<<r;
7602                   }
7603                 }
7604               }
7605             }
7606           }
7607           if(wr) {
7608             will_dirty[i]=temp_will_dirty;
7609             wont_dirty[i]=temp_wont_dirty;
7610             clean_registers((ba[i]-start)>>2,i-1,0);
7611           }else{
7612             // Limit recursion.  It can take an excessive amount
7613             // of time if there are a lot of nested loops.
7614             will_dirty[(ba[i]-start)>>2]=0;
7615             wont_dirty[(ba[i]-start)>>2]=-1;
7616           }
7617         }
7618         /*else*/ if(1)
7619         {
7620           if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
7621           {
7622             // Unconditional branch
7623             will_dirty_i=0;
7624             wont_dirty_i=0;
7625           //if(ba[i]>start+i*4) { // Disable recursion (for debugging)
7626             for(r=0;r<HOST_REGS;r++) {
7627               if(r!=EXCLUDE_REG) {
7628                 if(branch_regs[i].regmap[r]==regs[(ba[i]-start)>>2].regmap_entry[r]) {
7629                   will_dirty_i|=will_dirty[(ba[i]-start)>>2]&(1<<r);
7630                   wont_dirty_i|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
7631                 }
7632                 if(branch_regs[i].regmap[r]>=0) {
7633                   will_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>(branch_regs[i].regmap[r]&63))&1)<<r;
7634                   wont_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>(branch_regs[i].regmap[r]&63))&1)<<r;
7635                 }
7636               }
7637             }
7638           //}
7639             // Merge in delay slot
7640             for(r=0;r<HOST_REGS;r++) {
7641               if(r!=EXCLUDE_REG) {
7642                 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7643                 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7644                 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7645                 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7646                 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7647                 if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7648                 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7649                 if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7650                 if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7651                 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7652                 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7653                 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7654                 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7655                 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7656               }
7657             }
7658           } else {
7659             // Conditional branch
7660             will_dirty_i=will_dirty_next;
7661             wont_dirty_i=wont_dirty_next;
7662           //if(ba[i]>start+i*4) { // Disable recursion (for debugging)
7663             for(r=0;r<HOST_REGS;r++) {
7664               if(r!=EXCLUDE_REG) {
7665                 signed char target_reg=branch_regs[i].regmap[r];
7666                 if(target_reg==regs[(ba[i]-start)>>2].regmap_entry[r]) {
7667                   will_dirty_i&=will_dirty[(ba[i]-start)>>2]&(1<<r);
7668                   wont_dirty_i|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
7669                 }
7670                 else if(target_reg>=0) {
7671                   will_dirty_i&=((unneeded_reg[(ba[i]-start)>>2]>>(target_reg&63))&1)<<r;
7672                   wont_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>(target_reg&63))&1)<<r;
7673                 }
7674                 // Treat delay slot as part of branch too
7675                 /*if(regs[i+1].regmap[r]==regs[(ba[i]-start)>>2].regmap_entry[r]) {
7676                   will_dirty[i+1]&=will_dirty[(ba[i]-start)>>2]&(1<<r);
7677                   wont_dirty[i+1]|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
7678                 }
7679                 else
7680                 {
7681                   will_dirty[i+1]&=~(1<<r);
7682                 }*/
7683               }
7684             }
7685           //}
7686             // Merge in delay slot
7687             for(r=0;r<HOST_REGS;r++) {
7688               if(r!=EXCLUDE_REG) {
7689                 if(!likely[i]) {
7690                   // Might not dirty if likely branch is not taken
7691                   if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7692                   if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7693                   if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7694                   if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7695                   if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7696                   if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7697                   if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7698                   //if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7699                   //if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7700                   if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7701                   if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7702                   if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7703                   if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7704                   if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7705                 }
7706               }
7707             }
7708           }
7709           // Merge in delay slot (won't dirty)
7710           for(r=0;r<HOST_REGS;r++) {
7711             if(r!=EXCLUDE_REG) {
7712               if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7713               if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7714               if((regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7715               if((regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7716               if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7717               if((branch_regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7718               if((branch_regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7719               if((branch_regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7720               if((branch_regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7721               if(branch_regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7722             }
7723           }
7724           if(wr) {
7725             #ifndef DESTRUCTIVE_WRITEBACK
7726             branch_regs[i].dirty&=wont_dirty_i;
7727             #endif
7728             branch_regs[i].dirty|=will_dirty_i;
7729           }
7730         }
7731       }
7732     }
7733     else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
7734     {
7735       // SYSCALL instruction (software interrupt)
7736       will_dirty_i=0;
7737       wont_dirty_i=0;
7738     }
7739     else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
7740     {
7741       // ERET instruction (return from interrupt)
7742       will_dirty_i=0;
7743       wont_dirty_i=0;
7744     }
7745     will_dirty_next=will_dirty_i;
7746     wont_dirty_next=wont_dirty_i;
7747     for(r=0;r<HOST_REGS;r++) {
7748       if(r!=EXCLUDE_REG) {
7749         if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7750         if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7751         if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7752         if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7753         if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7754         if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7755         if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7756         if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7757         if(i>istart) {
7758           if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=FJUMP)
7759           {
7760             // Don't store a register immediately after writing it,
7761             // may prevent dual-issue.
7762             if((regs[i].regmap[r]&63)==rt1[i-1]) wont_dirty_i|=1<<r;
7763             if((regs[i].regmap[r]&63)==rt2[i-1]) wont_dirty_i|=1<<r;
7764           }
7765         }
7766       }
7767     }
7768     // Save it
7769     will_dirty[i]=will_dirty_i;
7770     wont_dirty[i]=wont_dirty_i;
7771     // Mark registers that won't be dirtied as not dirty
7772     if(wr) {
7773       /*printf("wr (%d,%d) %x will:",istart,iend,start+i*4);
7774       for(r=0;r<HOST_REGS;r++) {
7775         if((will_dirty_i>>r)&1) {
7776           printf(" r%d",r);
7777         }
7778       }
7779       printf("\n");*/
7780
7781       //if(i==istart||(itype[i-1]!=RJUMP&&itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=FJUMP)) {
7782         regs[i].dirty|=will_dirty_i;
7783         #ifndef DESTRUCTIVE_WRITEBACK
7784         regs[i].dirty&=wont_dirty_i;
7785         if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
7786         {
7787           if(i<iend-1&&itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000) {
7788             for(r=0;r<HOST_REGS;r++) {
7789               if(r!=EXCLUDE_REG) {
7790                 if(regs[i].regmap[r]==regmap_pre[i+2][r]) {
7791                   regs[i+2].wasdirty&=wont_dirty_i|~(1<<r);
7792                 }else {/*printf("i: %x (%d) mismatch(+2): %d\n",start+i*4,i,r);/*assert(!((wont_dirty_i>>r)&1));*/}
7793               }
7794             }
7795           }
7796         }
7797         else
7798         {
7799           if(i<iend) {
7800             for(r=0;r<HOST_REGS;r++) {
7801               if(r!=EXCLUDE_REG) {
7802                 if(regs[i].regmap[r]==regmap_pre[i+1][r]) {
7803                   regs[i+1].wasdirty&=wont_dirty_i|~(1<<r);
7804                 }else {/*printf("i: %x (%d) mismatch(+1): %d\n",start+i*4,i,r);/*assert(!((wont_dirty_i>>r)&1));*/}
7805               }
7806             }
7807           }
7808         }
7809         #endif
7810       //}
7811     }
7812     // Deal with changed mappings
7813     temp_will_dirty=will_dirty_i;
7814     temp_wont_dirty=wont_dirty_i;
7815     for(r=0;r<HOST_REGS;r++) {
7816       if(r!=EXCLUDE_REG) {
7817         int nr;
7818         if(regs[i].regmap[r]==regmap_pre[i][r]) {
7819           if(wr) {
7820             #ifndef DESTRUCTIVE_WRITEBACK
7821             regs[i].wasdirty&=wont_dirty_i|~(1<<r);
7822             #endif
7823             regs[i].wasdirty|=will_dirty_i&(1<<r);
7824           }
7825         }
7826         else if(regmap_pre[i][r]>=0&&(nr=get_reg(regs[i].regmap,regmap_pre[i][r]))>=0) {
7827           // Register moved to a different register
7828           will_dirty_i&=~(1<<r);
7829           wont_dirty_i&=~(1<<r);
7830           will_dirty_i|=((temp_will_dirty>>nr)&1)<<r;
7831           wont_dirty_i|=((temp_wont_dirty>>nr)&1)<<r;
7832           if(wr) {
7833             #ifndef DESTRUCTIVE_WRITEBACK
7834             regs[i].wasdirty&=wont_dirty_i|~(1<<r);
7835             #endif
7836             regs[i].wasdirty|=will_dirty_i&(1<<r);
7837           }
7838         }
7839         else {
7840           will_dirty_i&=~(1<<r);
7841           wont_dirty_i&=~(1<<r);
7842           if((regmap_pre[i][r]&63)>0 && (regmap_pre[i][r]&63)<34) {
7843             will_dirty_i|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7844             wont_dirty_i|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7845           } else {
7846             wont_dirty_i|=1<<r;
7847             /*printf("i: %x (%d) mismatch: %d\n",start+i*4,i,r);/*assert(!((will_dirty>>r)&1));*/
7848           }
7849         }
7850       }
7851     }
7852   }
7853 }
7854
7855 #ifdef DISASM
7856   /* disassembly */
7857 void disassemble_inst(int i)
7858 {
7859     if (bt[i]) printf("*"); else printf(" ");
7860     switch(itype[i]) {
7861       case UJUMP:
7862         printf (" %x: %s %8x\n",start+i*4,insn[i],ba[i]);break;
7863       case CJUMP:
7864         printf (" %x: %s r%d,r%d,%8x\n",start+i*4,insn[i],rs1[i],rs2[i],i?start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14):*ba);break;
7865       case SJUMP:
7866         printf (" %x: %s r%d,%8x\n",start+i*4,insn[i],rs1[i],start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14));break;
7867       case FJUMP:
7868         printf (" %x: %s %8x\n",start+i*4,insn[i],ba[i]);break;
7869       case RJUMP:
7870         if (opcode[i]==0x9&&rt1[i]!=31)
7871           printf (" %x: %s r%d,r%d\n",start+i*4,insn[i],rt1[i],rs1[i]);
7872         else
7873           printf (" %x: %s r%d\n",start+i*4,insn[i],rs1[i]);
7874         break;
7875       case SPAN:
7876         printf (" %x: %s (pagespan) r%d,r%d,%8x\n",start+i*4,insn[i],rs1[i],rs2[i],ba[i]);break;
7877       case IMM16:
7878         if(opcode[i]==0xf) //LUI
7879           printf (" %x: %s r%d,%4x0000\n",start+i*4,insn[i],rt1[i],imm[i]&0xffff);
7880         else
7881           printf (" %x: %s r%d,r%d,%d\n",start+i*4,insn[i],rt1[i],rs1[i],imm[i]);
7882         break;
7883       case LOAD:
7884       case LOADLR:
7885         printf (" %x: %s r%d,r%d+%x\n",start+i*4,insn[i],rt1[i],rs1[i],imm[i]);
7886         break;
7887       case STORE:
7888       case STORELR:
7889         printf (" %x: %s r%d,r%d+%x\n",start+i*4,insn[i],rs2[i],rs1[i],imm[i]);
7890         break;
7891       case ALU:
7892       case SHIFT:
7893         printf (" %x: %s r%d,r%d,r%d\n",start+i*4,insn[i],rt1[i],rs1[i],rs2[i]);
7894         break;
7895       case MULTDIV:
7896         printf (" %x: %s r%d,r%d\n",start+i*4,insn[i],rs1[i],rs2[i]);
7897         break;
7898       case SHIFTIMM:
7899         printf (" %x: %s r%d,r%d,%d\n",start+i*4,insn[i],rt1[i],rs1[i],imm[i]);
7900         break;
7901       case MOV:
7902         if((opcode2[i]&0x1d)==0x10)
7903           printf (" %x: %s r%d\n",start+i*4,insn[i],rt1[i]);
7904         else if((opcode2[i]&0x1d)==0x11)
7905           printf (" %x: %s r%d\n",start+i*4,insn[i],rs1[i]);
7906         else
7907           printf (" %x: %s\n",start+i*4,insn[i]);
7908         break;
7909       case COP0:
7910         if(opcode2[i]==0)
7911           printf (" %x: %s r%d,cpr0[%d]\n",start+i*4,insn[i],rt1[i],(source[i]>>11)&0x1f); // MFC0
7912         else if(opcode2[i]==4)
7913           printf (" %x: %s r%d,cpr0[%d]\n",start+i*4,insn[i],rs1[i],(source[i]>>11)&0x1f); // MTC0
7914         else printf (" %x: %s\n",start+i*4,insn[i]);
7915         break;
7916       case COP1:
7917         if(opcode2[i]<3)
7918           printf (" %x: %s r%d,cpr1[%d]\n",start+i*4,insn[i],rt1[i],(source[i]>>11)&0x1f); // MFC1
7919         else if(opcode2[i]>3)
7920           printf (" %x: %s r%d,cpr1[%d]\n",start+i*4,insn[i],rs1[i],(source[i]>>11)&0x1f); // MTC1
7921         else printf (" %x: %s\n",start+i*4,insn[i]);
7922         break;
7923       case COP2:
7924         if(opcode2[i]<3)
7925           printf (" %x: %s r%d,cpr2[%d]\n",start+i*4,insn[i],rt1[i],(source[i]>>11)&0x1f); // MFC2
7926         else if(opcode2[i]>3)
7927           printf (" %x: %s r%d,cpr2[%d]\n",start+i*4,insn[i],rs1[i],(source[i]>>11)&0x1f); // MTC2
7928         else printf (" %x: %s\n",start+i*4,insn[i]);
7929         break;
7930       case C1LS:
7931         printf (" %x: %s cpr1[%d],r%d+%x\n",start+i*4,insn[i],(source[i]>>16)&0x1f,rs1[i],imm[i]);
7932         break;
7933       case C2LS:
7934         printf (" %x: %s cpr2[%d],r%d+%x\n",start+i*4,insn[i],(source[i]>>16)&0x1f,rs1[i],imm[i]);
7935         break;
7936       case INTCALL:
7937         printf (" %x: %s (INTCALL)\n",start+i*4,insn[i]);
7938         break;
7939       default:
7940         //printf (" %s %8x\n",insn[i],source[i]);
7941         printf (" %x: %s\n",start+i*4,insn[i]);
7942     }
7943 }
7944 #else
7945 static void disassemble_inst(int i) {}
7946 #endif // DISASM
7947
7948 // clear the state completely, instead of just marking
7949 // things invalid like invalidate_all_pages() does
7950 void new_dynarec_clear_full()
7951 {
7952   int n;
7953   out=(u_char *)BASE_ADDR;
7954   memset(invalid_code,1,sizeof(invalid_code));
7955   memset(hash_table,0xff,sizeof(hash_table));
7956   memset(mini_ht,-1,sizeof(mini_ht));
7957   memset(restore_candidate,0,sizeof(restore_candidate));
7958   memset(shadow,0,sizeof(shadow));
7959   copy=shadow;
7960   expirep=16384; // Expiry pointer, +2 blocks
7961   pending_exception=0;
7962   literalcount=0;
7963   stop_after_jal=0;
7964   inv_code_start=inv_code_end=~0;
7965   // TLB
7966 #ifndef DISABLE_TLB
7967   using_tlb=0;
7968   for(n=0;n<524288;n++) // 0 .. 0x7FFFFFFF
7969     memory_map[n]=-1;
7970   for(n=524288;n<526336;n++) // 0x80000000 .. 0x807FFFFF
7971     memory_map[n]=((u_int)rdram-0x80000000)>>2;
7972   for(n=526336;n<1048576;n++) // 0x80800000 .. 0xFFFFFFFF
7973     memory_map[n]=-1;
7974 #endif
7975   for(n=0;n<4096;n++) ll_clear(jump_in+n);
7976   for(n=0;n<4096;n++) ll_clear(jump_out+n);
7977   for(n=0;n<4096;n++) ll_clear(jump_dirty+n);
7978 }
7979
7980 void new_dynarec_init()
7981 {
7982   printf("Init new dynarec\n");
7983   out=(u_char *)BASE_ADDR;
7984   if (mmap (out, 1<<TARGET_SIZE_2,
7985             PROT_READ | PROT_WRITE | PROT_EXEC,
7986             MAP_FIXED | MAP_PRIVATE | MAP_ANONYMOUS,
7987             -1, 0) <= 0) {printf("mmap() failed\n");}
7988 #ifdef MUPEN64
7989   rdword=&readmem_dword;
7990   fake_pc.f.r.rs=&readmem_dword;
7991   fake_pc.f.r.rt=&readmem_dword;
7992   fake_pc.f.r.rd=&readmem_dword;
7993 #endif
7994   int n;
7995   cycle_multiplier=200;
7996   new_dynarec_clear_full();
7997 #ifdef HOST_IMM8
7998   // Copy this into local area so we don't have to put it in every literal pool
7999   invc_ptr=invalid_code;
8000 #endif
8001 #ifdef MUPEN64
8002   for(n=0;n<0x8000;n++) { // 0 .. 0x7FFFFFFF
8003     writemem[n] = write_nomem_new;
8004     writememb[n] = write_nomemb_new;
8005     writememh[n] = write_nomemh_new;
8006 #ifndef FORCE32
8007     writememd[n] = write_nomemd_new;
8008 #endif
8009     readmem[n] = read_nomem_new;
8010     readmemb[n] = read_nomemb_new;
8011     readmemh[n] = read_nomemh_new;
8012 #ifndef FORCE32
8013     readmemd[n] = read_nomemd_new;
8014 #endif
8015   }
8016   for(n=0x8000;n<0x8080;n++) { // 0x80000000 .. 0x807FFFFF
8017     writemem[n] = write_rdram_new;
8018     writememb[n] = write_rdramb_new;
8019     writememh[n] = write_rdramh_new;
8020 #ifndef FORCE32
8021     writememd[n] = write_rdramd_new;
8022 #endif
8023   }
8024   for(n=0xC000;n<0x10000;n++) { // 0xC0000000 .. 0xFFFFFFFF
8025     writemem[n] = write_nomem_new;
8026     writememb[n] = write_nomemb_new;
8027     writememh[n] = write_nomemh_new;
8028 #ifndef FORCE32
8029     writememd[n] = write_nomemd_new;
8030 #endif
8031     readmem[n] = read_nomem_new;
8032     readmemb[n] = read_nomemb_new;
8033     readmemh[n] = read_nomemh_new;
8034 #ifndef FORCE32
8035     readmemd[n] = read_nomemd_new;
8036 #endif
8037   }
8038 #endif
8039   tlb_hacks();
8040   arch_init();
8041 }
8042
8043 void new_dynarec_cleanup()
8044 {
8045   int n;
8046   if (munmap ((void *)BASE_ADDR, 1<<TARGET_SIZE_2) < 0) {printf("munmap() failed\n");}
8047   for(n=0;n<4096;n++) ll_clear(jump_in+n);
8048   for(n=0;n<4096;n++) ll_clear(jump_out+n);
8049   for(n=0;n<4096;n++) ll_clear(jump_dirty+n);
8050   #ifdef ROM_COPY
8051   if (munmap (ROM_COPY, 67108864) < 0) {printf("munmap() failed\n");}
8052   #endif
8053 }
8054
8055 int new_recompile_block(int addr)
8056 {
8057 /*
8058   if(addr==0x800cd050) {
8059     int block;
8060     for(block=0x80000;block<0x80800;block++) invalidate_block(block);
8061     int n;
8062     for(n=0;n<=2048;n++) ll_clear(jump_dirty+n);
8063   }
8064 */
8065   //if(Count==365117028) tracedebug=1;
8066   assem_debug("NOTCOMPILED: addr = %x -> %x\n", (int)addr, (int)out);
8067   //printf("NOTCOMPILED: addr = %x -> %x\n", (int)addr, (int)out);
8068   //printf("TRACE: count=%d next=%d (compile %x)\n",Count,next_interupt,addr);
8069   //if(debug)
8070   //printf("TRACE: count=%d next=%d (checksum %x)\n",Count,next_interupt,mchecksum());
8071   //printf("fpu mapping=%x enabled=%x\n",(Status & 0x04000000)>>26,(Status & 0x20000000)>>29);
8072   /*if(Count>=312978186) {
8073     rlist();
8074   }*/
8075   //rlist();
8076   start = (u_int)addr&~3;
8077   //assert(((u_int)addr&1)==0);
8078   new_dynarec_did_compile=1;
8079 #ifdef PCSX
8080   if (Config.HLE && start == 0x80001000) // hlecall
8081   {
8082     // XXX: is this enough? Maybe check hleSoftCall?
8083     u_int beginning=(u_int)out;
8084     u_int page=get_page(start);
8085     invalid_code[start>>12]=0;
8086     emit_movimm(start,0);
8087     emit_writeword(0,(int)&pcaddr);
8088     emit_jmp((int)new_dyna_leave);
8089     literal_pool(0);
8090 #ifdef __arm__
8091     __clear_cache((void *)beginning,out);
8092 #endif
8093     ll_add(jump_in+page,start,(void *)beginning);
8094     return 0;
8095   }
8096   else if ((u_int)addr < 0x00200000 ||
8097     (0xa0000000 <= addr && addr < 0xa0200000)) {
8098     // used for BIOS calls mostly?
8099     source = (u_int *)((u_int)rdram+(start&0x1fffff));
8100     pagelimit = (addr&0xa0000000)|0x00200000;
8101   }
8102   else if (!Config.HLE && (
8103 /*    (0x9fc00000 <= addr && addr < 0x9fc80000) ||*/
8104     (0xbfc00000 <= addr && addr < 0xbfc80000))) {
8105     // BIOS
8106     source = (u_int *)((u_int)psxR+(start&0x7ffff));
8107     pagelimit = (addr&0xfff00000)|0x80000;
8108   }
8109   else
8110 #endif
8111 #ifdef MUPEN64
8112   if ((int)addr >= 0xa4000000 && (int)addr < 0xa4001000) {
8113     source = (u_int *)((u_int)SP_DMEM+start-0xa4000000);
8114     pagelimit = 0xa4001000;
8115   }
8116   else
8117 #endif
8118   if ((int)addr >= 0x80000000 && (int)addr < 0x80000000+RAM_SIZE) {
8119     source = (u_int *)((u_int)rdram+start-0x80000000);
8120     pagelimit = 0x80000000+RAM_SIZE;
8121   }
8122 #ifndef DISABLE_TLB
8123   else if ((signed int)addr >= (signed int)0xC0000000) {
8124     //printf("addr=%x mm=%x\n",(u_int)addr,(memory_map[start>>12]<<2));
8125     //if(tlb_LUT_r[start>>12])
8126       //source = (u_int *)(((int)rdram)+(tlb_LUT_r[start>>12]&0xFFFFF000)+(((int)addr)&0xFFF)-0x80000000);
8127     if((signed int)memory_map[start>>12]>=0) {
8128       source = (u_int *)((u_int)(start+(memory_map[start>>12]<<2)));
8129       pagelimit=(start+4096)&0xFFFFF000;
8130       int map=memory_map[start>>12];
8131       int i;
8132       for(i=0;i<5;i++) {
8133         //printf("start: %x next: %x\n",map,memory_map[pagelimit>>12]);
8134         if((map&0xBFFFFFFF)==(memory_map[pagelimit>>12]&0xBFFFFFFF)) pagelimit+=4096;
8135       }
8136       assem_debug("pagelimit=%x\n",pagelimit);
8137       assem_debug("mapping=%x (%x)\n",memory_map[start>>12],(memory_map[start>>12]<<2)+start);
8138     }
8139     else {
8140       assem_debug("Compile at unmapped memory address: %x \n", (int)addr);
8141       //assem_debug("start: %x next: %x\n",memory_map[start>>12],memory_map[(start+4096)>>12]);
8142       return -1; // Caller will invoke exception handler
8143     }
8144     //printf("source= %x\n",(int)source);
8145   }
8146 #endif
8147   else {
8148     printf("Compile at bogus memory address: %x \n", (int)addr);
8149     exit(1);
8150   }
8151
8152   /* Pass 1: disassemble */
8153   /* Pass 2: register dependencies, branch targets */
8154   /* Pass 3: register allocation */
8155   /* Pass 4: branch dependencies */
8156   /* Pass 5: pre-alloc */
8157   /* Pass 6: optimize clean/dirty state */
8158   /* Pass 7: flag 32-bit registers */
8159   /* Pass 8: assembly */
8160   /* Pass 9: linker */
8161   /* Pass 10: garbage collection / free memory */
8162
8163   int i,j;
8164   int done=0;
8165   unsigned int type,op,op2;
8166
8167   //printf("addr = %x source = %x %x\n", addr,source,source[0]);
8168
8169   /* Pass 1 disassembly */
8170
8171   for(i=0;!done;i++) {
8172     bt[i]=0;likely[i]=0;ooo[i]=0;op2=0;
8173     minimum_free_regs[i]=0;
8174     opcode[i]=op=source[i]>>26;
8175     switch(op)
8176     {
8177       case 0x00: strcpy(insn[i],"special"); type=NI;
8178         op2=source[i]&0x3f;
8179         switch(op2)
8180         {
8181           case 0x00: strcpy(insn[i],"SLL"); type=SHIFTIMM; break;
8182           case 0x02: strcpy(insn[i],"SRL"); type=SHIFTIMM; break;
8183           case 0x03: strcpy(insn[i],"SRA"); type=SHIFTIMM; break;
8184           case 0x04: strcpy(insn[i],"SLLV"); type=SHIFT; break;
8185           case 0x06: strcpy(insn[i],"SRLV"); type=SHIFT; break;
8186           case 0x07: strcpy(insn[i],"SRAV"); type=SHIFT; break;
8187           case 0x08: strcpy(insn[i],"JR"); type=RJUMP; break;
8188           case 0x09: strcpy(insn[i],"JALR"); type=RJUMP; break;
8189           case 0x0C: strcpy(insn[i],"SYSCALL"); type=SYSCALL; break;
8190           case 0x0D: strcpy(insn[i],"BREAK"); type=OTHER; break;
8191           case 0x0F: strcpy(insn[i],"SYNC"); type=OTHER; break;
8192           case 0x10: strcpy(insn[i],"MFHI"); type=MOV; break;
8193           case 0x11: strcpy(insn[i],"MTHI"); type=MOV; break;
8194           case 0x12: strcpy(insn[i],"MFLO"); type=MOV; break;
8195           case 0x13: strcpy(insn[i],"MTLO"); type=MOV; break;
8196           case 0x18: strcpy(insn[i],"MULT"); type=MULTDIV; break;
8197           case 0x19: strcpy(insn[i],"MULTU"); type=MULTDIV; break;
8198           case 0x1A: strcpy(insn[i],"DIV"); type=MULTDIV; break;
8199           case 0x1B: strcpy(insn[i],"DIVU"); type=MULTDIV; break;
8200           case 0x20: strcpy(insn[i],"ADD"); type=ALU; break;
8201           case 0x21: strcpy(insn[i],"ADDU"); type=ALU; break;
8202           case 0x22: strcpy(insn[i],"SUB"); type=ALU; break;
8203           case 0x23: strcpy(insn[i],"SUBU"); type=ALU; break;
8204           case 0x24: strcpy(insn[i],"AND"); type=ALU; break;
8205           case 0x25: strcpy(insn[i],"OR"); type=ALU; break;
8206           case 0x26: strcpy(insn[i],"XOR"); type=ALU; break;
8207           case 0x27: strcpy(insn[i],"NOR"); type=ALU; break;
8208           case 0x2A: strcpy(insn[i],"SLT"); type=ALU; break;
8209           case 0x2B: strcpy(insn[i],"SLTU"); type=ALU; break;
8210           case 0x30: strcpy(insn[i],"TGE"); type=NI; break;
8211           case 0x31: strcpy(insn[i],"TGEU"); type=NI; break;
8212           case 0x32: strcpy(insn[i],"TLT"); type=NI; break;
8213           case 0x33: strcpy(insn[i],"TLTU"); type=NI; break;
8214           case 0x34: strcpy(insn[i],"TEQ"); type=NI; break;
8215           case 0x36: strcpy(insn[i],"TNE"); type=NI; break;
8216 #ifndef FORCE32
8217           case 0x14: strcpy(insn[i],"DSLLV"); type=SHIFT; break;
8218           case 0x16: strcpy(insn[i],"DSRLV"); type=SHIFT; break;
8219           case 0x17: strcpy(insn[i],"DSRAV"); type=SHIFT; break;
8220           case 0x1C: strcpy(insn[i],"DMULT"); type=MULTDIV; break;
8221           case 0x1D: strcpy(insn[i],"DMULTU"); type=MULTDIV; break;
8222           case 0x1E: strcpy(insn[i],"DDIV"); type=MULTDIV; break;
8223           case 0x1F: strcpy(insn[i],"DDIVU"); type=MULTDIV; break;
8224           case 0x2C: strcpy(insn[i],"DADD"); type=ALU; break;
8225           case 0x2D: strcpy(insn[i],"DADDU"); type=ALU; break;
8226           case 0x2E: strcpy(insn[i],"DSUB"); type=ALU; break;
8227           case 0x2F: strcpy(insn[i],"DSUBU"); type=ALU; break;
8228           case 0x38: strcpy(insn[i],"DSLL"); type=SHIFTIMM; break;
8229           case 0x3A: strcpy(insn[i],"DSRL"); type=SHIFTIMM; break;
8230           case 0x3B: strcpy(insn[i],"DSRA"); type=SHIFTIMM; break;
8231           case 0x3C: strcpy(insn[i],"DSLL32"); type=SHIFTIMM; break;
8232           case 0x3E: strcpy(insn[i],"DSRL32"); type=SHIFTIMM; break;
8233           case 0x3F: strcpy(insn[i],"DSRA32"); type=SHIFTIMM; break;
8234 #endif
8235         }
8236         break;
8237       case 0x01: strcpy(insn[i],"regimm"); type=NI;
8238         op2=(source[i]>>16)&0x1f;
8239         switch(op2)
8240         {
8241           case 0x00: strcpy(insn[i],"BLTZ"); type=SJUMP; break;
8242           case 0x01: strcpy(insn[i],"BGEZ"); type=SJUMP; break;
8243           case 0x02: strcpy(insn[i],"BLTZL"); type=SJUMP; break;
8244           case 0x03: strcpy(insn[i],"BGEZL"); type=SJUMP; break;
8245           case 0x08: strcpy(insn[i],"TGEI"); type=NI; break;
8246           case 0x09: strcpy(insn[i],"TGEIU"); type=NI; break;
8247           case 0x0A: strcpy(insn[i],"TLTI"); type=NI; break;
8248           case 0x0B: strcpy(insn[i],"TLTIU"); type=NI; break;
8249           case 0x0C: strcpy(insn[i],"TEQI"); type=NI; break;
8250           case 0x0E: strcpy(insn[i],"TNEI"); type=NI; break;
8251           case 0x10: strcpy(insn[i],"BLTZAL"); type=SJUMP; break;
8252           case 0x11: strcpy(insn[i],"BGEZAL"); type=SJUMP; break;
8253           case 0x12: strcpy(insn[i],"BLTZALL"); type=SJUMP; break;
8254           case 0x13: strcpy(insn[i],"BGEZALL"); type=SJUMP; break;
8255         }
8256         break;
8257       case 0x02: strcpy(insn[i],"J"); type=UJUMP; break;
8258       case 0x03: strcpy(insn[i],"JAL"); type=UJUMP; break;
8259       case 0x04: strcpy(insn[i],"BEQ"); type=CJUMP; break;
8260       case 0x05: strcpy(insn[i],"BNE"); type=CJUMP; break;
8261       case 0x06: strcpy(insn[i],"BLEZ"); type=CJUMP; break;
8262       case 0x07: strcpy(insn[i],"BGTZ"); type=CJUMP; break;
8263       case 0x08: strcpy(insn[i],"ADDI"); type=IMM16; break;
8264       case 0x09: strcpy(insn[i],"ADDIU"); type=IMM16; break;
8265       case 0x0A: strcpy(insn[i],"SLTI"); type=IMM16; break;
8266       case 0x0B: strcpy(insn[i],"SLTIU"); type=IMM16; break;
8267       case 0x0C: strcpy(insn[i],"ANDI"); type=IMM16; break;
8268       case 0x0D: strcpy(insn[i],"ORI"); type=IMM16; break;
8269       case 0x0E: strcpy(insn[i],"XORI"); type=IMM16; break;
8270       case 0x0F: strcpy(insn[i],"LUI"); type=IMM16; break;
8271       case 0x10: strcpy(insn[i],"cop0"); type=NI;
8272         op2=(source[i]>>21)&0x1f;
8273         switch(op2)
8274         {
8275           case 0x00: strcpy(insn[i],"MFC0"); type=COP0; break;
8276           case 0x04: strcpy(insn[i],"MTC0"); type=COP0; break;
8277           case 0x10: strcpy(insn[i],"tlb"); type=NI;
8278           switch(source[i]&0x3f)
8279           {
8280             case 0x01: strcpy(insn[i],"TLBR"); type=COP0; break;
8281             case 0x02: strcpy(insn[i],"TLBWI"); type=COP0; break;
8282             case 0x06: strcpy(insn[i],"TLBWR"); type=COP0; break;
8283             case 0x08: strcpy(insn[i],"TLBP"); type=COP0; break;
8284 #ifdef PCSX
8285             case 0x10: strcpy(insn[i],"RFE"); type=COP0; break;
8286 #else
8287             case 0x18: strcpy(insn[i],"ERET"); type=COP0; break;
8288 #endif
8289           }
8290         }
8291         break;
8292       case 0x11: strcpy(insn[i],"cop1"); type=NI;
8293         op2=(source[i]>>21)&0x1f;
8294         switch(op2)
8295         {
8296           case 0x00: strcpy(insn[i],"MFC1"); type=COP1; break;
8297           case 0x01: strcpy(insn[i],"DMFC1"); type=COP1; break;
8298           case 0x02: strcpy(insn[i],"CFC1"); type=COP1; break;
8299           case 0x04: strcpy(insn[i],"MTC1"); type=COP1; break;
8300           case 0x05: strcpy(insn[i],"DMTC1"); type=COP1; break;
8301           case 0x06: strcpy(insn[i],"CTC1"); type=COP1; break;
8302           case 0x08: strcpy(insn[i],"BC1"); type=FJUMP;
8303           switch((source[i]>>16)&0x3)
8304           {
8305             case 0x00: strcpy(insn[i],"BC1F"); break;
8306             case 0x01: strcpy(insn[i],"BC1T"); break;
8307             case 0x02: strcpy(insn[i],"BC1FL"); break;
8308             case 0x03: strcpy(insn[i],"BC1TL"); break;
8309           }
8310           break;
8311           case 0x10: strcpy(insn[i],"C1.S"); type=NI;
8312           switch(source[i]&0x3f)
8313           {
8314             case 0x00: strcpy(insn[i],"ADD.S"); type=FLOAT; break;
8315             case 0x01: strcpy(insn[i],"SUB.S"); type=FLOAT; break;
8316             case 0x02: strcpy(insn[i],"MUL.S"); type=FLOAT; break;
8317             case 0x03: strcpy(insn[i],"DIV.S"); type=FLOAT; break;
8318             case 0x04: strcpy(insn[i],"SQRT.S"); type=FLOAT; break;
8319             case 0x05: strcpy(insn[i],"ABS.S"); type=FLOAT; break;
8320             case 0x06: strcpy(insn[i],"MOV.S"); type=FLOAT; break;
8321             case 0x07: strcpy(insn[i],"NEG.S"); type=FLOAT; break;
8322             case 0x08: strcpy(insn[i],"ROUND.L.S"); type=FCONV; break;
8323             case 0x09: strcpy(insn[i],"TRUNC.L.S"); type=FCONV; break;
8324             case 0x0A: strcpy(insn[i],"CEIL.L.S"); type=FCONV; break;
8325             case 0x0B: strcpy(insn[i],"FLOOR.L.S"); type=FCONV; break;
8326             case 0x0C: strcpy(insn[i],"ROUND.W.S"); type=FCONV; break;
8327             case 0x0D: strcpy(insn[i],"TRUNC.W.S"); type=FCONV; break;
8328             case 0x0E: strcpy(insn[i],"CEIL.W.S"); type=FCONV; break;
8329             case 0x0F: strcpy(insn[i],"FLOOR.W.S"); type=FCONV; break;
8330             case 0x21: strcpy(insn[i],"CVT.D.S"); type=FCONV; break;
8331             case 0x24: strcpy(insn[i],"CVT.W.S"); type=FCONV; break;
8332             case 0x25: strcpy(insn[i],"CVT.L.S"); type=FCONV; break;
8333             case 0x30: strcpy(insn[i],"C.F.S"); type=FCOMP; break;
8334             case 0x31: strcpy(insn[i],"C.UN.S"); type=FCOMP; break;
8335             case 0x32: strcpy(insn[i],"C.EQ.S"); type=FCOMP; break;
8336             case 0x33: strcpy(insn[i],"C.UEQ.S"); type=FCOMP; break;
8337             case 0x34: strcpy(insn[i],"C.OLT.S"); type=FCOMP; break;
8338             case 0x35: strcpy(insn[i],"C.ULT.S"); type=FCOMP; break;
8339             case 0x36: strcpy(insn[i],"C.OLE.S"); type=FCOMP; break;
8340             case 0x37: strcpy(insn[i],"C.ULE.S"); type=FCOMP; break;
8341             case 0x38: strcpy(insn[i],"C.SF.S"); type=FCOMP; break;
8342             case 0x39: strcpy(insn[i],"C.NGLE.S"); type=FCOMP; break;
8343             case 0x3A: strcpy(insn[i],"C.SEQ.S"); type=FCOMP; break;
8344             case 0x3B: strcpy(insn[i],"C.NGL.S"); type=FCOMP; break;
8345             case 0x3C: strcpy(insn[i],"C.LT.S"); type=FCOMP; break;
8346             case 0x3D: strcpy(insn[i],"C.NGE.S"); type=FCOMP; break;
8347             case 0x3E: strcpy(insn[i],"C.LE.S"); type=FCOMP; break;
8348             case 0x3F: strcpy(insn[i],"C.NGT.S"); type=FCOMP; break;
8349           }
8350           break;
8351           case 0x11: strcpy(insn[i],"C1.D"); type=NI;
8352           switch(source[i]&0x3f)
8353           {
8354             case 0x00: strcpy(insn[i],"ADD.D"); type=FLOAT; break;
8355             case 0x01: strcpy(insn[i],"SUB.D"); type=FLOAT; break;
8356             case 0x02: strcpy(insn[i],"MUL.D"); type=FLOAT; break;
8357             case 0x03: strcpy(insn[i],"DIV.D"); type=FLOAT; break;
8358             case 0x04: strcpy(insn[i],"SQRT.D"); type=FLOAT; break;
8359             case 0x05: strcpy(insn[i],"ABS.D"); type=FLOAT; break;
8360             case 0x06: strcpy(insn[i],"MOV.D"); type=FLOAT; break;
8361             case 0x07: strcpy(insn[i],"NEG.D"); type=FLOAT; break;
8362             case 0x08: strcpy(insn[i],"ROUND.L.D"); type=FCONV; break;
8363             case 0x09: strcpy(insn[i],"TRUNC.L.D"); type=FCONV; break;
8364             case 0x0A: strcpy(insn[i],"CEIL.L.D"); type=FCONV; break;
8365             case 0x0B: strcpy(insn[i],"FLOOR.L.D"); type=FCONV; break;
8366             case 0x0C: strcpy(insn[i],"ROUND.W.D"); type=FCONV; break;
8367             case 0x0D: strcpy(insn[i],"TRUNC.W.D"); type=FCONV; break;
8368             case 0x0E: strcpy(insn[i],"CEIL.W.D"); type=FCONV; break;
8369             case 0x0F: strcpy(insn[i],"FLOOR.W.D"); type=FCONV; break;
8370             case 0x20: strcpy(insn[i],"CVT.S.D"); type=FCONV; break;
8371             case 0x24: strcpy(insn[i],"CVT.W.D"); type=FCONV; break;
8372             case 0x25: strcpy(insn[i],"CVT.L.D"); type=FCONV; break;
8373             case 0x30: strcpy(insn[i],"C.F.D"); type=FCOMP; break;
8374             case 0x31: strcpy(insn[i],"C.UN.D"); type=FCOMP; break;
8375             case 0x32: strcpy(insn[i],"C.EQ.D"); type=FCOMP; break;
8376             case 0x33: strcpy(insn[i],"C.UEQ.D"); type=FCOMP; break;
8377             case 0x34: strcpy(insn[i],"C.OLT.D"); type=FCOMP; break;
8378             case 0x35: strcpy(insn[i],"C.ULT.D"); type=FCOMP; break;
8379             case 0x36: strcpy(insn[i],"C.OLE.D"); type=FCOMP; break;
8380             case 0x37: strcpy(insn[i],"C.ULE.D"); type=FCOMP; break;
8381             case 0x38: strcpy(insn[i],"C.SF.D"); type=FCOMP; break;
8382             case 0x39: strcpy(insn[i],"C.NGLE.D"); type=FCOMP; break;
8383             case 0x3A: strcpy(insn[i],"C.SEQ.D"); type=FCOMP; break;
8384             case 0x3B: strcpy(insn[i],"C.NGL.D"); type=FCOMP; break;
8385             case 0x3C: strcpy(insn[i],"C.LT.D"); type=FCOMP; break;
8386             case 0x3D: strcpy(insn[i],"C.NGE.D"); type=FCOMP; break;
8387             case 0x3E: strcpy(insn[i],"C.LE.D"); type=FCOMP; break;
8388             case 0x3F: strcpy(insn[i],"C.NGT.D"); type=FCOMP; break;
8389           }
8390           break;
8391           case 0x14: strcpy(insn[i],"C1.W"); type=NI;
8392           switch(source[i]&0x3f)
8393           {
8394             case 0x20: strcpy(insn[i],"CVT.S.W"); type=FCONV; break;
8395             case 0x21: strcpy(insn[i],"CVT.D.W"); type=FCONV; break;
8396           }
8397           break;
8398           case 0x15: strcpy(insn[i],"C1.L"); type=NI;
8399           switch(source[i]&0x3f)
8400           {
8401             case 0x20: strcpy(insn[i],"CVT.S.L"); type=FCONV; break;
8402             case 0x21: strcpy(insn[i],"CVT.D.L"); type=FCONV; break;
8403           }
8404           break;
8405         }
8406         break;
8407 #ifndef FORCE32
8408       case 0x14: strcpy(insn[i],"BEQL"); type=CJUMP; break;
8409       case 0x15: strcpy(insn[i],"BNEL"); type=CJUMP; break;
8410       case 0x16: strcpy(insn[i],"BLEZL"); type=CJUMP; break;
8411       case 0x17: strcpy(insn[i],"BGTZL"); type=CJUMP; break;
8412       case 0x18: strcpy(insn[i],"DADDI"); type=IMM16; break;
8413       case 0x19: strcpy(insn[i],"DADDIU"); type=IMM16; break;
8414       case 0x1A: strcpy(insn[i],"LDL"); type=LOADLR; break;
8415       case 0x1B: strcpy(insn[i],"LDR"); type=LOADLR; break;
8416 #endif
8417       case 0x20: strcpy(insn[i],"LB"); type=LOAD; break;
8418       case 0x21: strcpy(insn[i],"LH"); type=LOAD; break;
8419       case 0x22: strcpy(insn[i],"LWL"); type=LOADLR; break;
8420       case 0x23: strcpy(insn[i],"LW"); type=LOAD; break;
8421       case 0x24: strcpy(insn[i],"LBU"); type=LOAD; break;
8422       case 0x25: strcpy(insn[i],"LHU"); type=LOAD; break;
8423       case 0x26: strcpy(insn[i],"LWR"); type=LOADLR; break;
8424 #ifndef FORCE32
8425       case 0x27: strcpy(insn[i],"LWU"); type=LOAD; break;
8426 #endif
8427       case 0x28: strcpy(insn[i],"SB"); type=STORE; break;
8428       case 0x29: strcpy(insn[i],"SH"); type=STORE; break;
8429       case 0x2A: strcpy(insn[i],"SWL"); type=STORELR; break;
8430       case 0x2B: strcpy(insn[i],"SW"); type=STORE; break;
8431 #ifndef FORCE32
8432       case 0x2C: strcpy(insn[i],"SDL"); type=STORELR; break;
8433       case 0x2D: strcpy(insn[i],"SDR"); type=STORELR; break;
8434 #endif
8435       case 0x2E: strcpy(insn[i],"SWR"); type=STORELR; break;
8436       case 0x2F: strcpy(insn[i],"CACHE"); type=NOP; break;
8437       case 0x30: strcpy(insn[i],"LL"); type=NI; break;
8438       case 0x31: strcpy(insn[i],"LWC1"); type=C1LS; break;
8439 #ifndef FORCE32
8440       case 0x34: strcpy(insn[i],"LLD"); type=NI; break;
8441       case 0x35: strcpy(insn[i],"LDC1"); type=C1LS; break;
8442       case 0x37: strcpy(insn[i],"LD"); type=LOAD; break;
8443 #endif
8444       case 0x38: strcpy(insn[i],"SC"); type=NI; break;
8445       case 0x39: strcpy(insn[i],"SWC1"); type=C1LS; break;
8446 #ifndef FORCE32
8447       case 0x3C: strcpy(insn[i],"SCD"); type=NI; break;
8448       case 0x3D: strcpy(insn[i],"SDC1"); type=C1LS; break;
8449       case 0x3F: strcpy(insn[i],"SD"); type=STORE; break;
8450 #endif
8451 #ifdef PCSX
8452       case 0x12: strcpy(insn[i],"COP2"); type=NI;
8453         op2=(source[i]>>21)&0x1f;
8454         //if (op2 & 0x10) {
8455         if (source[i]&0x3f) { // use this hack to support old savestates with patched gte insns
8456           if (gte_handlers[source[i]&0x3f]!=NULL) {
8457             if (gte_regnames[source[i]&0x3f]!=NULL)
8458               strcpy(insn[i],gte_regnames[source[i]&0x3f]);
8459             else
8460               snprintf(insn[i], sizeof(insn[i]), "COP2 %x", source[i]&0x3f);
8461             type=C2OP;
8462           }
8463         }
8464         else switch(op2)
8465         {
8466           case 0x00: strcpy(insn[i],"MFC2"); type=COP2; break;
8467           case 0x02: strcpy(insn[i],"CFC2"); type=COP2; break;
8468           case 0x04: strcpy(insn[i],"MTC2"); type=COP2; break;
8469           case 0x06: strcpy(insn[i],"CTC2"); type=COP2; break;
8470         }
8471         break;
8472       case 0x32: strcpy(insn[i],"LWC2"); type=C2LS; break;
8473       case 0x3A: strcpy(insn[i],"SWC2"); type=C2LS; break;
8474       case 0x3B: strcpy(insn[i],"HLECALL"); type=HLECALL; break;
8475 #endif
8476       default: strcpy(insn[i],"???"); type=NI;
8477         printf("NI %08x @%08x (%08x)\n", source[i], addr + i*4, addr);
8478         break;
8479     }
8480     itype[i]=type;
8481     opcode2[i]=op2;
8482     /* Get registers/immediates */
8483     lt1[i]=0;
8484     us1[i]=0;
8485     us2[i]=0;
8486     dep1[i]=0;
8487     dep2[i]=0;
8488     gte_rs[i]=gte_rt[i]=0;
8489     switch(type) {
8490       case LOAD:
8491         rs1[i]=(source[i]>>21)&0x1f;
8492         rs2[i]=0;
8493         rt1[i]=(source[i]>>16)&0x1f;
8494         rt2[i]=0;
8495         imm[i]=(short)source[i];
8496         break;
8497       case STORE:
8498       case STORELR:
8499         rs1[i]=(source[i]>>21)&0x1f;
8500         rs2[i]=(source[i]>>16)&0x1f;
8501         rt1[i]=0;
8502         rt2[i]=0;
8503         imm[i]=(short)source[i];
8504         if(op==0x2c||op==0x2d||op==0x3f) us1[i]=rs2[i]; // 64-bit SDL/SDR/SD
8505         break;
8506       case LOADLR:
8507         // LWL/LWR only load part of the register,
8508         // therefore the target register must be treated as a source too
8509         rs1[i]=(source[i]>>21)&0x1f;
8510         rs2[i]=(source[i]>>16)&0x1f;
8511         rt1[i]=(source[i]>>16)&0x1f;
8512         rt2[i]=0;
8513         imm[i]=(short)source[i];
8514         if(op==0x1a||op==0x1b) us1[i]=rs2[i]; // LDR/LDL
8515         if(op==0x26) dep1[i]=rt1[i]; // LWR
8516         break;
8517       case IMM16:
8518         if (op==0x0f) rs1[i]=0; // LUI instruction has no source register
8519         else rs1[i]=(source[i]>>21)&0x1f;
8520         rs2[i]=0;
8521         rt1[i]=(source[i]>>16)&0x1f;
8522         rt2[i]=0;
8523         if(op>=0x0c&&op<=0x0e) { // ANDI/ORI/XORI
8524           imm[i]=(unsigned short)source[i];
8525         }else{
8526           imm[i]=(short)source[i];
8527         }
8528         if(op==0x18||op==0x19) us1[i]=rs1[i]; // DADDI/DADDIU
8529         if(op==0x0a||op==0x0b) us1[i]=rs1[i]; // SLTI/SLTIU
8530         if(op==0x0d||op==0x0e) dep1[i]=rs1[i]; // ORI/XORI
8531         break;
8532       case UJUMP:
8533         rs1[i]=0;
8534         rs2[i]=0;
8535         rt1[i]=0;
8536         rt2[i]=0;
8537         // The JAL instruction writes to r31.
8538         if (op&1) {
8539           rt1[i]=31;
8540         }
8541         rs2[i]=CCREG;
8542         break;
8543       case RJUMP:
8544         rs1[i]=(source[i]>>21)&0x1f;
8545         rs2[i]=0;
8546         rt1[i]=0;
8547         rt2[i]=0;
8548         // The JALR instruction writes to rd.
8549         if (op2&1) {
8550           rt1[i]=(source[i]>>11)&0x1f;
8551         }
8552         rs2[i]=CCREG;
8553         break;
8554       case CJUMP:
8555         rs1[i]=(source[i]>>21)&0x1f;
8556         rs2[i]=(source[i]>>16)&0x1f;
8557         rt1[i]=0;
8558         rt2[i]=0;
8559         if(op&2) { // BGTZ/BLEZ
8560           rs2[i]=0;
8561         }
8562         us1[i]=rs1[i];
8563         us2[i]=rs2[i];
8564         likely[i]=op>>4;
8565         break;
8566       case SJUMP:
8567         rs1[i]=(source[i]>>21)&0x1f;
8568         rs2[i]=CCREG;
8569         rt1[i]=0;
8570         rt2[i]=0;
8571         us1[i]=rs1[i];
8572         if(op2&0x10) { // BxxAL
8573           rt1[i]=31;
8574           // NOTE: If the branch is not taken, r31 is still overwritten
8575         }
8576         likely[i]=(op2&2)>>1;
8577         break;
8578       case FJUMP:
8579         rs1[i]=FSREG;
8580         rs2[i]=CSREG;
8581         rt1[i]=0;
8582         rt2[i]=0;
8583         likely[i]=((source[i])>>17)&1;
8584         break;
8585       case ALU:
8586         rs1[i]=(source[i]>>21)&0x1f; // source
8587         rs2[i]=(source[i]>>16)&0x1f; // subtract amount
8588         rt1[i]=(source[i]>>11)&0x1f; // destination
8589         rt2[i]=0;
8590         if(op2==0x2a||op2==0x2b) { // SLT/SLTU
8591           us1[i]=rs1[i];us2[i]=rs2[i];
8592         }
8593         else if(op2>=0x24&&op2<=0x27) { // AND/OR/XOR/NOR
8594           dep1[i]=rs1[i];dep2[i]=rs2[i];
8595         }
8596         else if(op2>=0x2c&&op2<=0x2f) { // DADD/DSUB
8597           dep1[i]=rs1[i];dep2[i]=rs2[i];
8598         }
8599         break;
8600       case MULTDIV:
8601         rs1[i]=(source[i]>>21)&0x1f; // source
8602         rs2[i]=(source[i]>>16)&0x1f; // divisor
8603         rt1[i]=HIREG;
8604         rt2[i]=LOREG;
8605         if (op2>=0x1c&&op2<=0x1f) { // DMULT/DMULTU/DDIV/DDIVU
8606           us1[i]=rs1[i];us2[i]=rs2[i];
8607         }
8608         break;
8609       case MOV:
8610         rs1[i]=0;
8611         rs2[i]=0;
8612         rt1[i]=0;
8613         rt2[i]=0;
8614         if(op2==0x10) rs1[i]=HIREG; // MFHI
8615         if(op2==0x11) rt1[i]=HIREG; // MTHI
8616         if(op2==0x12) rs1[i]=LOREG; // MFLO
8617         if(op2==0x13) rt1[i]=LOREG; // MTLO
8618         if((op2&0x1d)==0x10) rt1[i]=(source[i]>>11)&0x1f; // MFxx
8619         if((op2&0x1d)==0x11) rs1[i]=(source[i]>>21)&0x1f; // MTxx
8620         dep1[i]=rs1[i];
8621         break;
8622       case SHIFT:
8623         rs1[i]=(source[i]>>16)&0x1f; // target of shift
8624         rs2[i]=(source[i]>>21)&0x1f; // shift amount
8625         rt1[i]=(source[i]>>11)&0x1f; // destination
8626         rt2[i]=0;
8627         // DSLLV/DSRLV/DSRAV are 64-bit
8628         if(op2>=0x14&&op2<=0x17) us1[i]=rs1[i];
8629         break;
8630       case SHIFTIMM:
8631         rs1[i]=(source[i]>>16)&0x1f;
8632         rs2[i]=0;
8633         rt1[i]=(source[i]>>11)&0x1f;
8634         rt2[i]=0;
8635         imm[i]=(source[i]>>6)&0x1f;
8636         // DSxx32 instructions
8637         if(op2>=0x3c) imm[i]|=0x20;
8638         // DSLL/DSRL/DSRA/DSRA32/DSRL32 but not DSLL32 require 64-bit source
8639         if(op2>=0x38&&op2!=0x3c) us1[i]=rs1[i];
8640         break;
8641       case COP0:
8642         rs1[i]=0;
8643         rs2[i]=0;
8644         rt1[i]=0;
8645         rt2[i]=0;
8646         if(op2==0) rt1[i]=(source[i]>>16)&0x1F; // MFC0
8647         if(op2==4) rs1[i]=(source[i]>>16)&0x1F; // MTC0
8648         if(op2==4&&((source[i]>>11)&0x1f)==12) rt2[i]=CSREG; // Status
8649         if(op2==16) if((source[i]&0x3f)==0x18) rs2[i]=CCREG; // ERET
8650         break;
8651       case COP1:
8652         rs1[i]=0;
8653         rs2[i]=0;
8654         rt1[i]=0;
8655         rt2[i]=0;
8656         if(op2<3) rt1[i]=(source[i]>>16)&0x1F; // MFC1/DMFC1/CFC1
8657         if(op2>3) rs1[i]=(source[i]>>16)&0x1F; // MTC1/DMTC1/CTC1
8658         if(op2==5) us1[i]=rs1[i]; // DMTC1
8659         rs2[i]=CSREG;
8660         break;
8661       case COP2:
8662         rs1[i]=0;
8663         rs2[i]=0;
8664         rt1[i]=0;
8665         rt2[i]=0;
8666         if(op2<3) rt1[i]=(source[i]>>16)&0x1F; // MFC2/CFC2
8667         if(op2>3) rs1[i]=(source[i]>>16)&0x1F; // MTC2/CTC2
8668         rs2[i]=CSREG;
8669         int gr=(source[i]>>11)&0x1F;
8670         switch(op2)
8671         {
8672           case 0x00: gte_rs[i]=1ll<<gr; break; // MFC2
8673           case 0x04: gte_rt[i]=1ll<<gr; break; // MTC2
8674           case 0x02: gte_rs[i]=1ll<<(gr+32); break; // CFC2
8675           case 0x06: gte_rt[i]=1ll<<(gr+32); break; // CTC2
8676         }
8677         break;
8678       case C1LS:
8679         rs1[i]=(source[i]>>21)&0x1F;
8680         rs2[i]=CSREG;
8681         rt1[i]=0;
8682         rt2[i]=0;
8683         imm[i]=(short)source[i];
8684         break;
8685       case C2LS:
8686         rs1[i]=(source[i]>>21)&0x1F;
8687         rs2[i]=0;
8688         rt1[i]=0;
8689         rt2[i]=0;
8690         imm[i]=(short)source[i];
8691         if(op==0x32) gte_rt[i]=1ll<<((source[i]>>16)&0x1F); // LWC2
8692         else gte_rs[i]=1ll<<((source[i]>>16)&0x1F); // SWC2
8693         break;
8694       case C2OP:
8695         rs1[i]=0;
8696         rs2[i]=0;
8697         rt1[i]=0;
8698         rt2[i]=0;
8699         gte_rs[i]=gte_reg_reads[source[i]&0x3f];
8700         gte_rt[i]=gte_reg_writes[source[i]&0x3f];
8701         gte_rt[i]|=1ll<<63; // every op changes flags
8702         if((source[i]&0x3f)==GTE_MVMVA) {
8703           int v = (source[i] >> 15) & 3;
8704           gte_rs[i]&=~0xe3fll;
8705           if(v==3) gte_rs[i]|=0xe00ll;
8706           else gte_rs[i]|=3ll<<(v*2);
8707         }
8708         break;
8709       case FLOAT:
8710       case FCONV:
8711         rs1[i]=0;
8712         rs2[i]=CSREG;
8713         rt1[i]=0;
8714         rt2[i]=0;
8715         break;
8716       case FCOMP:
8717         rs1[i]=FSREG;
8718         rs2[i]=CSREG;
8719         rt1[i]=FSREG;
8720         rt2[i]=0;
8721         break;
8722       case SYSCALL:
8723       case HLECALL:
8724       case INTCALL:
8725         rs1[i]=CCREG;
8726         rs2[i]=0;
8727         rt1[i]=0;
8728         rt2[i]=0;
8729         break;
8730       default:
8731         rs1[i]=0;
8732         rs2[i]=0;
8733         rt1[i]=0;
8734         rt2[i]=0;
8735     }
8736     /* Calculate branch target addresses */
8737     if(type==UJUMP)
8738       ba[i]=((start+i*4+4)&0xF0000000)|(((unsigned int)source[i]<<6)>>4);
8739     else if(type==CJUMP&&rs1[i]==rs2[i]&&(op&1))
8740       ba[i]=start+i*4+8; // Ignore never taken branch
8741     else if(type==SJUMP&&rs1[i]==0&&!(op2&1))
8742       ba[i]=start+i*4+8; // Ignore never taken branch
8743     else if(type==CJUMP||type==SJUMP||type==FJUMP)
8744       ba[i]=start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14);
8745     else ba[i]=-1;
8746 #ifdef PCSX
8747     if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)) {
8748       int do_in_intrp=0;
8749       // branch in delay slot?
8750       if(type==RJUMP||type==UJUMP||type==CJUMP||type==SJUMP||type==FJUMP) {
8751         // don't handle first branch and call interpreter if it's hit
8752         printf("branch in delay slot @%08x (%08x)\n", addr + i*4, addr);
8753         do_in_intrp=1;
8754       }
8755       // basic load delay detection
8756       else if((type==LOAD||type==LOADLR||type==COP0||type==COP2||type==C2LS)&&rt1[i]!=0) {
8757         int t=(ba[i-1]-start)/4;
8758         if(0 <= t && t < i &&(rt1[i]==rs1[t]||rt1[i]==rs2[t])&&itype[t]!=CJUMP&&itype[t]!=SJUMP) {
8759           // jump target wants DS result - potential load delay effect
8760           printf("load delay @%08x (%08x)\n", addr + i*4, addr);
8761           do_in_intrp=1;
8762           bt[t+1]=1; // expected return from interpreter
8763         }
8764         else if(i>=2&&rt1[i-2]==2&&rt1[i]==2&&rs1[i]!=2&&rs2[i]!=2&&rs1[i-1]!=2&&rs2[i-1]!=2&&
8765               !(i>=3&&(itype[i-3]==RJUMP||itype[i-3]==UJUMP||itype[i-3]==CJUMP||itype[i-3]==SJUMP))) {
8766           // v0 overwrite like this is a sign of trouble, bail out
8767           printf("v0 overwrite @%08x (%08x)\n", addr + i*4, addr);
8768           do_in_intrp=1;
8769         }
8770       }
8771       if(do_in_intrp) {
8772         rs1[i-1]=CCREG;
8773         rs2[i-1]=rt1[i-1]=rt2[i-1]=0;
8774         ba[i-1]=-1;
8775         itype[i-1]=INTCALL;
8776         done=2;
8777         i--; // don't compile the DS
8778       }
8779     }
8780 #endif
8781     /* Is this the end of the block? */
8782     if(i>0&&(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)) {
8783       if(rt1[i-1]==0) { // Continue past subroutine call (JAL)
8784         done=2;
8785       }
8786       else {
8787         if(stop_after_jal) done=1;
8788         // Stop on BREAK
8789         if((source[i+1]&0xfc00003f)==0x0d) done=1;
8790       }
8791       // Don't recompile stuff that's already compiled
8792       if(check_addr(start+i*4+4)) done=1;
8793       // Don't get too close to the limit
8794       if(i>MAXBLOCK/2) done=1;
8795     }
8796     if(itype[i]==SYSCALL&&stop_after_jal) done=1;
8797     if(itype[i]==HLECALL||itype[i]==INTCALL) done=2;
8798     if(done==2) {
8799       // Does the block continue due to a branch?
8800       for(j=i-1;j>=0;j--)
8801       {
8802         if(ba[j]==start+i*4) done=j=0; // Branch into delay slot
8803         if(ba[j]==start+i*4+4) done=j=0;
8804         if(ba[j]==start+i*4+8) done=j=0;
8805       }
8806     }
8807     //assert(i<MAXBLOCK-1);
8808     if(start+i*4==pagelimit-4) done=1;
8809     assert(start+i*4<pagelimit);
8810     if (i==MAXBLOCK-1) done=1;
8811     // Stop if we're compiling junk
8812     if(itype[i]==NI&&opcode[i]==0x11) {
8813       done=stop_after_jal=1;
8814       printf("Disabled speculative precompilation\n");
8815     }
8816   }
8817   slen=i;
8818   if(itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==RJUMP||itype[i-1]==FJUMP) {
8819     if(start+i*4==pagelimit) {
8820       itype[i-1]=SPAN;
8821     }
8822   }
8823   assert(slen>0);
8824
8825   /* Pass 2 - Register dependencies and branch targets */
8826
8827   unneeded_registers(0,slen-1,0);
8828
8829   /* Pass 3 - Register allocation */
8830
8831   struct regstat current; // Current register allocations/status
8832   current.is32=1;
8833   current.dirty=0;
8834   current.u=unneeded_reg[0];
8835   current.uu=unneeded_reg_upper[0];
8836   clear_all_regs(current.regmap);
8837   alloc_reg(&current,0,CCREG);
8838   dirty_reg(&current,CCREG);
8839   current.isconst=0;
8840   current.wasconst=0;
8841   current.waswritten=0;
8842   int ds=0;
8843   int cc=0;
8844   int hr=-1;
8845
8846 #ifndef FORCE32
8847   provisional_32bit();
8848 #endif
8849   if((u_int)addr&1) {
8850     // First instruction is delay slot
8851     cc=-1;
8852     bt[1]=1;
8853     ds=1;
8854     unneeded_reg[0]=1;
8855     unneeded_reg_upper[0]=1;
8856     current.regmap[HOST_BTREG]=BTREG;
8857   }
8858
8859   for(i=0;i<slen;i++)
8860   {
8861     if(bt[i])
8862     {
8863       int hr;
8864       for(hr=0;hr<HOST_REGS;hr++)
8865       {
8866         // Is this really necessary?
8867         if(current.regmap[hr]==0) current.regmap[hr]=-1;
8868       }
8869       current.isconst=0;
8870       current.waswritten=0;
8871     }
8872     if(i>1)
8873     {
8874       if((opcode[i-2]&0x2f)==0x05) // BNE/BNEL
8875       {
8876         if(rs1[i-2]==0||rs2[i-2]==0)
8877         {
8878           if(rs1[i-2]) {
8879             current.is32|=1LL<<rs1[i-2];
8880             int hr=get_reg(current.regmap,rs1[i-2]|64);
8881             if(hr>=0) current.regmap[hr]=-1;
8882           }
8883           if(rs2[i-2]) {
8884             current.is32|=1LL<<rs2[i-2];
8885             int hr=get_reg(current.regmap,rs2[i-2]|64);
8886             if(hr>=0) current.regmap[hr]=-1;
8887           }
8888         }
8889       }
8890     }
8891 #ifndef FORCE32
8892     // If something jumps here with 64-bit values
8893     // then promote those registers to 64 bits
8894     if(bt[i])
8895     {
8896       uint64_t temp_is32=current.is32;
8897       for(j=i-1;j>=0;j--)
8898       {
8899         if(ba[j]==start+i*4)
8900           temp_is32&=branch_regs[j].is32;
8901       }
8902       for(j=i;j<slen;j++)
8903       {
8904         if(ba[j]==start+i*4)
8905           //temp_is32=1;
8906           temp_is32&=p32[j];
8907       }
8908       if(temp_is32!=current.is32) {
8909         //printf("dumping 32-bit regs (%x)\n",start+i*4);
8910         #ifndef DESTRUCTIVE_WRITEBACK
8911         if(ds)
8912         #endif
8913         for(hr=0;hr<HOST_REGS;hr++)
8914         {
8915           int r=current.regmap[hr];
8916           if(r>0&&r<64)
8917           {
8918             if((current.dirty>>hr)&((current.is32&~temp_is32)>>r)&1) {
8919               temp_is32|=1LL<<r;
8920               //printf("restore %d\n",r);
8921             }
8922           }
8923         }
8924         current.is32=temp_is32;
8925       }
8926     }
8927 #else
8928     current.is32=-1LL;
8929 #endif
8930
8931     memcpy(regmap_pre[i],current.regmap,sizeof(current.regmap));
8932     regs[i].wasconst=current.isconst;
8933     regs[i].was32=current.is32;
8934     regs[i].wasdirty=current.dirty;
8935     regs[i].loadedconst=0;
8936     #if defined(DESTRUCTIVE_WRITEBACK) && !defined(FORCE32)
8937     // To change a dirty register from 32 to 64 bits, we must write
8938     // it out during the previous cycle (for branches, 2 cycles)
8939     if(i<slen-1&&bt[i+1]&&itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP)
8940     {
8941       uint64_t temp_is32=current.is32;
8942       for(j=i-1;j>=0;j--)
8943       {
8944         if(ba[j]==start+i*4+4)
8945           temp_is32&=branch_regs[j].is32;
8946       }
8947       for(j=i;j<slen;j++)
8948       {
8949         if(ba[j]==start+i*4+4)
8950           //temp_is32=1;
8951           temp_is32&=p32[j];
8952       }
8953       if(temp_is32!=current.is32) {
8954         //printf("pre-dumping 32-bit regs (%x)\n",start+i*4);
8955         for(hr=0;hr<HOST_REGS;hr++)
8956         {
8957           int r=current.regmap[hr];
8958           if(r>0)
8959           {
8960             if((current.dirty>>hr)&((current.is32&~temp_is32)>>(r&63))&1) {
8961               if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP)
8962               {
8963                 if(rs1[i]!=(r&63)&&rs2[i]!=(r&63))
8964                 {
8965                   //printf("dump %d/r%d\n",hr,r);
8966                   current.regmap[hr]=-1;
8967                   if(get_reg(current.regmap,r|64)>=0)
8968                     current.regmap[get_reg(current.regmap,r|64)]=-1;
8969                 }
8970               }
8971             }
8972           }
8973         }
8974       }
8975     }
8976     else if(i<slen-2&&bt[i+2]&&(source[i-1]>>16)!=0x1000&&(itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP))
8977     {
8978       uint64_t temp_is32=current.is32;
8979       for(j=i-1;j>=0;j--)
8980       {
8981         if(ba[j]==start+i*4+8)
8982           temp_is32&=branch_regs[j].is32;
8983       }
8984       for(j=i;j<slen;j++)
8985       {
8986         if(ba[j]==start+i*4+8)
8987           //temp_is32=1;
8988           temp_is32&=p32[j];
8989       }
8990       if(temp_is32!=current.is32) {
8991         //printf("pre-dumping 32-bit regs (%x)\n",start+i*4);
8992         for(hr=0;hr<HOST_REGS;hr++)
8993         {
8994           int r=current.regmap[hr];
8995           if(r>0)
8996           {
8997             if((current.dirty>>hr)&((current.is32&~temp_is32)>>(r&63))&1) {
8998               if(rs1[i]!=(r&63)&&rs2[i]!=(r&63)&&rs1[i+1]!=(r&63)&&rs2[i+1]!=(r&63))
8999               {
9000                 //printf("dump %d/r%d\n",hr,r);
9001                 current.regmap[hr]=-1;
9002                 if(get_reg(current.regmap,r|64)>=0)
9003                   current.regmap[get_reg(current.regmap,r|64)]=-1;
9004               }
9005             }
9006           }
9007         }
9008       }
9009     }
9010     #endif
9011     if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP) {
9012       if(i+1<slen) {
9013         current.u=unneeded_reg[i+1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
9014         current.uu=unneeded_reg_upper[i+1]&~((1LL<<us1[i])|(1LL<<us2[i]));
9015         if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9016         current.u|=1;
9017         current.uu|=1;
9018       } else {
9019         current.u=1;
9020         current.uu=1;
9021       }
9022     } else {
9023       if(i+1<slen) {
9024         current.u=branch_unneeded_reg[i]&~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
9025         current.uu=branch_unneeded_reg_upper[i]&~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
9026         if((~current.uu>>rt1[i+1])&1) current.uu&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
9027         current.u&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
9028         current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
9029         current.u|=1;
9030         current.uu|=1;
9031       } else { printf("oops, branch at end of block with no delay slot\n");exit(1); }
9032     }
9033     is_ds[i]=ds;
9034     if(ds) {
9035       ds=0; // Skip delay slot, already allocated as part of branch
9036       // ...but we need to alloc it in case something jumps here
9037       if(i+1<slen) {
9038         current.u=branch_unneeded_reg[i-1]&unneeded_reg[i+1];
9039         current.uu=branch_unneeded_reg_upper[i-1]&unneeded_reg_upper[i+1];
9040       }else{
9041         current.u=branch_unneeded_reg[i-1];
9042         current.uu=branch_unneeded_reg_upper[i-1];
9043       }
9044       current.u&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
9045       current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
9046       if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9047       current.u|=1;
9048       current.uu|=1;
9049       struct regstat temp;
9050       memcpy(&temp,&current,sizeof(current));
9051       temp.wasdirty=temp.dirty;
9052       temp.was32=temp.is32;
9053       // TODO: Take into account unconditional branches, as below
9054       delayslot_alloc(&temp,i);
9055       memcpy(regs[i].regmap,temp.regmap,sizeof(temp.regmap));
9056       regs[i].wasdirty=temp.wasdirty;
9057       regs[i].was32=temp.was32;
9058       regs[i].dirty=temp.dirty;
9059       regs[i].is32=temp.is32;
9060       regs[i].isconst=0;
9061       regs[i].wasconst=0;
9062       current.isconst=0;
9063       // Create entry (branch target) regmap
9064       for(hr=0;hr<HOST_REGS;hr++)
9065       {
9066         int r=temp.regmap[hr];
9067         if(r>=0) {
9068           if(r!=regmap_pre[i][hr]) {
9069             regs[i].regmap_entry[hr]=-1;
9070           }
9071           else
9072           {
9073             if(r<64){
9074               if((current.u>>r)&1) {
9075                 regs[i].regmap_entry[hr]=-1;
9076                 regs[i].regmap[hr]=-1;
9077                 //Don't clear regs in the delay slot as the branch might need them
9078                 //current.regmap[hr]=-1;
9079               }else
9080                 regs[i].regmap_entry[hr]=r;
9081             }
9082             else {
9083               if((current.uu>>(r&63))&1) {
9084                 regs[i].regmap_entry[hr]=-1;
9085                 regs[i].regmap[hr]=-1;
9086                 //Don't clear regs in the delay slot as the branch might need them
9087                 //current.regmap[hr]=-1;
9088               }else
9089                 regs[i].regmap_entry[hr]=r;
9090             }
9091           }
9092         } else {
9093           // First instruction expects CCREG to be allocated
9094           if(i==0&&hr==HOST_CCREG)
9095             regs[i].regmap_entry[hr]=CCREG;
9096           else
9097             regs[i].regmap_entry[hr]=-1;
9098         }
9099       }
9100     }
9101     else { // Not delay slot
9102       switch(itype[i]) {
9103         case UJUMP:
9104           //current.isconst=0; // DEBUG
9105           //current.wasconst=0; // DEBUG
9106           //regs[i].wasconst=0; // DEBUG
9107           clear_const(&current,rt1[i]);
9108           alloc_cc(&current,i);
9109           dirty_reg(&current,CCREG);
9110           if (rt1[i]==31) {
9111             alloc_reg(&current,i,31);
9112             dirty_reg(&current,31);
9113             //assert(rs1[i+1]!=31&&rs2[i+1]!=31);
9114             //assert(rt1[i+1]!=rt1[i]);
9115             #ifdef REG_PREFETCH
9116             alloc_reg(&current,i,PTEMP);
9117             #endif
9118             //current.is32|=1LL<<rt1[i];
9119           }
9120           ooo[i]=1;
9121           delayslot_alloc(&current,i+1);
9122           //current.isconst=0; // DEBUG
9123           ds=1;
9124           //printf("i=%d, isconst=%x\n",i,current.isconst);
9125           break;
9126         case RJUMP:
9127           //current.isconst=0;
9128           //current.wasconst=0;
9129           //regs[i].wasconst=0;
9130           clear_const(&current,rs1[i]);
9131           clear_const(&current,rt1[i]);
9132           alloc_cc(&current,i);
9133           dirty_reg(&current,CCREG);
9134           if(rs1[i]!=rt1[i+1]&&rs1[i]!=rt2[i+1]) {
9135             alloc_reg(&current,i,rs1[i]);
9136             if (rt1[i]!=0) {
9137               alloc_reg(&current,i,rt1[i]);
9138               dirty_reg(&current,rt1[i]);
9139               assert(rs1[i+1]!=rt1[i]&&rs2[i+1]!=rt1[i]);
9140               assert(rt1[i+1]!=rt1[i]);
9141               #ifdef REG_PREFETCH
9142               alloc_reg(&current,i,PTEMP);
9143               #endif
9144             }
9145             #ifdef USE_MINI_HT
9146             if(rs1[i]==31) { // JALR
9147               alloc_reg(&current,i,RHASH);
9148               #ifndef HOST_IMM_ADDR32
9149               alloc_reg(&current,i,RHTBL);
9150               #endif
9151             }
9152             #endif
9153             delayslot_alloc(&current,i+1);
9154           } else {
9155             // The delay slot overwrites our source register,
9156             // allocate a temporary register to hold the old value.
9157             current.isconst=0;
9158             current.wasconst=0;
9159             regs[i].wasconst=0;
9160             delayslot_alloc(&current,i+1);
9161             current.isconst=0;
9162             alloc_reg(&current,i,RTEMP);
9163           }
9164           //current.isconst=0; // DEBUG
9165           ooo[i]=1;
9166           ds=1;
9167           break;
9168         case CJUMP:
9169           //current.isconst=0;
9170           //current.wasconst=0;
9171           //regs[i].wasconst=0;
9172           clear_const(&current,rs1[i]);
9173           clear_const(&current,rs2[i]);
9174           if((opcode[i]&0x3E)==4) // BEQ/BNE
9175           {
9176             alloc_cc(&current,i);
9177             dirty_reg(&current,CCREG);
9178             if(rs1[i]) alloc_reg(&current,i,rs1[i]);
9179             if(rs2[i]) alloc_reg(&current,i,rs2[i]);
9180             if(!((current.is32>>rs1[i])&(current.is32>>rs2[i])&1))
9181             {
9182               if(rs1[i]) alloc_reg64(&current,i,rs1[i]);
9183               if(rs2[i]) alloc_reg64(&current,i,rs2[i]);
9184             }
9185             if((rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]))||
9186                (rs2[i]&&(rs2[i]==rt1[i+1]||rs2[i]==rt2[i+1]))) {
9187               // The delay slot overwrites one of our conditions.
9188               // Allocate the branch condition registers instead.
9189               current.isconst=0;
9190               current.wasconst=0;
9191               regs[i].wasconst=0;
9192               if(rs1[i]) alloc_reg(&current,i,rs1[i]);
9193               if(rs2[i]) alloc_reg(&current,i,rs2[i]);
9194               if(!((current.is32>>rs1[i])&(current.is32>>rs2[i])&1))
9195               {
9196                 if(rs1[i]) alloc_reg64(&current,i,rs1[i]);
9197                 if(rs2[i]) alloc_reg64(&current,i,rs2[i]);
9198               }
9199             }
9200             else
9201             {
9202               ooo[i]=1;
9203               delayslot_alloc(&current,i+1);
9204             }
9205           }
9206           else
9207           if((opcode[i]&0x3E)==6) // BLEZ/BGTZ
9208           {
9209             alloc_cc(&current,i);
9210             dirty_reg(&current,CCREG);
9211             alloc_reg(&current,i,rs1[i]);
9212             if(!(current.is32>>rs1[i]&1))
9213             {
9214               alloc_reg64(&current,i,rs1[i]);
9215             }
9216             if(rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1])) {
9217               // The delay slot overwrites one of our conditions.
9218               // Allocate the branch condition registers instead.
9219               current.isconst=0;
9220               current.wasconst=0;
9221               regs[i].wasconst=0;
9222               if(rs1[i]) alloc_reg(&current,i,rs1[i]);
9223               if(!((current.is32>>rs1[i])&1))
9224               {
9225                 if(rs1[i]) alloc_reg64(&current,i,rs1[i]);
9226               }
9227             }
9228             else
9229             {
9230               ooo[i]=1;
9231               delayslot_alloc(&current,i+1);
9232             }
9233           }
9234           else
9235           // Don't alloc the delay slot yet because we might not execute it
9236           if((opcode[i]&0x3E)==0x14) // BEQL/BNEL
9237           {
9238             current.isconst=0;
9239             current.wasconst=0;
9240             regs[i].wasconst=0;
9241             alloc_cc(&current,i);
9242             dirty_reg(&current,CCREG);
9243             alloc_reg(&current,i,rs1[i]);
9244             alloc_reg(&current,i,rs2[i]);
9245             if(!((current.is32>>rs1[i])&(current.is32>>rs2[i])&1))
9246             {
9247               alloc_reg64(&current,i,rs1[i]);
9248               alloc_reg64(&current,i,rs2[i]);
9249             }
9250           }
9251           else
9252           if((opcode[i]&0x3E)==0x16) // BLEZL/BGTZL
9253           {
9254             current.isconst=0;
9255             current.wasconst=0;
9256             regs[i].wasconst=0;
9257             alloc_cc(&current,i);
9258             dirty_reg(&current,CCREG);
9259             alloc_reg(&current,i,rs1[i]);
9260             if(!(current.is32>>rs1[i]&1))
9261             {
9262               alloc_reg64(&current,i,rs1[i]);
9263             }
9264           }
9265           ds=1;
9266           //current.isconst=0;
9267           break;
9268         case SJUMP:
9269           //current.isconst=0;
9270           //current.wasconst=0;
9271           //regs[i].wasconst=0;
9272           clear_const(&current,rs1[i]);
9273           clear_const(&current,rt1[i]);
9274           //if((opcode2[i]&0x1E)==0x0) // BLTZ/BGEZ
9275           if((opcode2[i]&0x0E)==0x0) // BLTZ/BGEZ
9276           {
9277             alloc_cc(&current,i);
9278             dirty_reg(&current,CCREG);
9279             alloc_reg(&current,i,rs1[i]);
9280             if(!(current.is32>>rs1[i]&1))
9281             {
9282               alloc_reg64(&current,i,rs1[i]);
9283             }
9284             if (rt1[i]==31) { // BLTZAL/BGEZAL
9285               alloc_reg(&current,i,31);
9286               dirty_reg(&current,31);
9287               //#ifdef REG_PREFETCH
9288               //alloc_reg(&current,i,PTEMP);
9289               //#endif
9290               //current.is32|=1LL<<rt1[i];
9291             }
9292             if((rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1])) // The delay slot overwrites the branch condition.
9293                ||(rt1[i]==31&&(rs1[i+1]==31||rs2[i+1]==31||rt1[i+1]==31||rt2[i+1]==31))) { // DS touches $ra
9294               // Allocate the branch condition registers instead.
9295               current.isconst=0;
9296               current.wasconst=0;
9297               regs[i].wasconst=0;
9298               if(rs1[i]) alloc_reg(&current,i,rs1[i]);
9299               if(!((current.is32>>rs1[i])&1))
9300               {
9301                 if(rs1[i]) alloc_reg64(&current,i,rs1[i]);
9302               }
9303             }
9304             else
9305             {
9306               ooo[i]=1;
9307               delayslot_alloc(&current,i+1);
9308             }
9309           }
9310           else
9311           // Don't alloc the delay slot yet because we might not execute it
9312           if((opcode2[i]&0x1E)==0x2) // BLTZL/BGEZL
9313           {
9314             current.isconst=0;
9315             current.wasconst=0;
9316             regs[i].wasconst=0;
9317             alloc_cc(&current,i);
9318             dirty_reg(&current,CCREG);
9319             alloc_reg(&current,i,rs1[i]);
9320             if(!(current.is32>>rs1[i]&1))
9321             {
9322               alloc_reg64(&current,i,rs1[i]);
9323             }
9324           }
9325           ds=1;
9326           //current.isconst=0;
9327           break;
9328         case FJUMP:
9329           current.isconst=0;
9330           current.wasconst=0;
9331           regs[i].wasconst=0;
9332           if(likely[i]==0) // BC1F/BC1T
9333           {
9334             // TODO: Theoretically we can run out of registers here on x86.
9335             // The delay slot can allocate up to six, and we need to check
9336             // CSREG before executing the delay slot.  Possibly we can drop
9337             // the cycle count and then reload it after checking that the
9338             // FPU is in a usable state, or don't do out-of-order execution.
9339             alloc_cc(&current,i);
9340             dirty_reg(&current,CCREG);
9341             alloc_reg(&current,i,FSREG);
9342             alloc_reg(&current,i,CSREG);
9343             if(itype[i+1]==FCOMP) {
9344               // The delay slot overwrites the branch condition.
9345               // Allocate the branch condition registers instead.
9346               alloc_cc(&current,i);
9347               dirty_reg(&current,CCREG);
9348               alloc_reg(&current,i,CSREG);
9349               alloc_reg(&current,i,FSREG);
9350             }
9351             else {
9352               ooo[i]=1;
9353               delayslot_alloc(&current,i+1);
9354               alloc_reg(&current,i+1,CSREG);
9355             }
9356           }
9357           else
9358           // Don't alloc the delay slot yet because we might not execute it
9359           if(likely[i]) // BC1FL/BC1TL
9360           {
9361             alloc_cc(&current,i);
9362             dirty_reg(&current,CCREG);
9363             alloc_reg(&current,i,CSREG);
9364             alloc_reg(&current,i,FSREG);
9365           }
9366           ds=1;
9367           current.isconst=0;
9368           break;
9369         case IMM16:
9370           imm16_alloc(&current,i);
9371           break;
9372         case LOAD:
9373         case LOADLR:
9374           load_alloc(&current,i);
9375           break;
9376         case STORE:
9377         case STORELR:
9378           store_alloc(&current,i);
9379           break;
9380         case ALU:
9381           alu_alloc(&current,i);
9382           break;
9383         case SHIFT:
9384           shift_alloc(&current,i);
9385           break;
9386         case MULTDIV:
9387           multdiv_alloc(&current,i);
9388           break;
9389         case SHIFTIMM:
9390           shiftimm_alloc(&current,i);
9391           break;
9392         case MOV:
9393           mov_alloc(&current,i);
9394           break;
9395         case COP0:
9396           cop0_alloc(&current,i);
9397           break;
9398         case COP1:
9399         case COP2:
9400           cop1_alloc(&current,i);
9401           break;
9402         case C1LS:
9403           c1ls_alloc(&current,i);
9404           break;
9405         case C2LS:
9406           c2ls_alloc(&current,i);
9407           break;
9408         case C2OP:
9409           c2op_alloc(&current,i);
9410           break;
9411         case FCONV:
9412           fconv_alloc(&current,i);
9413           break;
9414         case FLOAT:
9415           float_alloc(&current,i);
9416           break;
9417         case FCOMP:
9418           fcomp_alloc(&current,i);
9419           break;
9420         case SYSCALL:
9421         case HLECALL:
9422         case INTCALL:
9423           syscall_alloc(&current,i);
9424           break;
9425         case SPAN:
9426           pagespan_alloc(&current,i);
9427           break;
9428       }
9429
9430       // Drop the upper half of registers that have become 32-bit
9431       current.uu|=current.is32&((1LL<<rt1[i])|(1LL<<rt2[i]));
9432       if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP) {
9433         current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
9434         if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9435         current.uu|=1;
9436       } else {
9437         current.uu|=current.is32&((1LL<<rt1[i+1])|(1LL<<rt2[i+1]));
9438         current.uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
9439         if((~current.uu>>rt1[i+1])&1) current.uu&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
9440         current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
9441         current.uu|=1;
9442       }
9443
9444       // Create entry (branch target) regmap
9445       for(hr=0;hr<HOST_REGS;hr++)
9446       {
9447         int r,or,er;
9448         r=current.regmap[hr];
9449         if(r>=0) {
9450           if(r!=regmap_pre[i][hr]) {
9451             // TODO: delay slot (?)
9452             or=get_reg(regmap_pre[i],r); // Get old mapping for this register
9453             if(or<0||(r&63)>=TEMPREG){
9454               regs[i].regmap_entry[hr]=-1;
9455             }
9456             else
9457             {
9458               // Just move it to a different register
9459               regs[i].regmap_entry[hr]=r;
9460               // If it was dirty before, it's still dirty
9461               if((regs[i].wasdirty>>or)&1) dirty_reg(&current,r&63);
9462             }
9463           }
9464           else
9465           {
9466             // Unneeded
9467             if(r==0){
9468               regs[i].regmap_entry[hr]=0;
9469             }
9470             else
9471             if(r<64){
9472               if((current.u>>r)&1) {
9473                 regs[i].regmap_entry[hr]=-1;
9474                 //regs[i].regmap[hr]=-1;
9475                 current.regmap[hr]=-1;
9476               }else
9477                 regs[i].regmap_entry[hr]=r;
9478             }
9479             else {
9480               if((current.uu>>(r&63))&1) {
9481                 regs[i].regmap_entry[hr]=-1;
9482                 //regs[i].regmap[hr]=-1;
9483                 current.regmap[hr]=-1;
9484               }else
9485                 regs[i].regmap_entry[hr]=r;
9486             }
9487           }
9488         } else {
9489           // Branches expect CCREG to be allocated at the target
9490           if(regmap_pre[i][hr]==CCREG)
9491             regs[i].regmap_entry[hr]=CCREG;
9492           else
9493             regs[i].regmap_entry[hr]=-1;
9494         }
9495       }
9496       memcpy(regs[i].regmap,current.regmap,sizeof(current.regmap));
9497     }
9498
9499     if(i>0&&(itype[i-1]==STORE||itype[i-1]==STORELR||(itype[i-1]==C2LS&&opcode[i-1]==0x3a))&&(u_int)imm[i-1]<0x800)
9500       current.waswritten|=1<<rs1[i-1];
9501     current.waswritten&=~(1<<rt1[i]);
9502     current.waswritten&=~(1<<rt2[i]);
9503     if((itype[i]==STORE||itype[i]==STORELR||(itype[i]==C2LS&&opcode[i]==0x3a))&&(u_int)imm[i]>=0x800)
9504       current.waswritten&=~(1<<rs1[i]);
9505
9506     /* Branch post-alloc */
9507     if(i>0)
9508     {
9509       current.was32=current.is32;
9510       current.wasdirty=current.dirty;
9511       switch(itype[i-1]) {
9512         case UJUMP:
9513           memcpy(&branch_regs[i-1],&current,sizeof(current));
9514           branch_regs[i-1].isconst=0;
9515           branch_regs[i-1].wasconst=0;
9516           branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1]));
9517           branch_regs[i-1].uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i-1])|(1LL<<us2[i-1]));
9518           alloc_cc(&branch_regs[i-1],i-1);
9519           dirty_reg(&branch_regs[i-1],CCREG);
9520           if(rt1[i-1]==31) { // JAL
9521             alloc_reg(&branch_regs[i-1],i-1,31);
9522             dirty_reg(&branch_regs[i-1],31);
9523             branch_regs[i-1].is32|=1LL<<31;
9524           }
9525           memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9526           memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9527           break;
9528         case RJUMP:
9529           memcpy(&branch_regs[i-1],&current,sizeof(current));
9530           branch_regs[i-1].isconst=0;
9531           branch_regs[i-1].wasconst=0;
9532           branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1]));
9533           branch_regs[i-1].uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i-1])|(1LL<<us2[i-1]));
9534           alloc_cc(&branch_regs[i-1],i-1);
9535           dirty_reg(&branch_regs[i-1],CCREG);
9536           alloc_reg(&branch_regs[i-1],i-1,rs1[i-1]);
9537           if(rt1[i-1]!=0) { // JALR
9538             alloc_reg(&branch_regs[i-1],i-1,rt1[i-1]);
9539             dirty_reg(&branch_regs[i-1],rt1[i-1]);
9540             branch_regs[i-1].is32|=1LL<<rt1[i-1];
9541           }
9542           #ifdef USE_MINI_HT
9543           if(rs1[i-1]==31) { // JALR
9544             alloc_reg(&branch_regs[i-1],i-1,RHASH);
9545             #ifndef HOST_IMM_ADDR32
9546             alloc_reg(&branch_regs[i-1],i-1,RHTBL);
9547             #endif
9548           }
9549           #endif
9550           memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9551           memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9552           break;
9553         case CJUMP:
9554           if((opcode[i-1]&0x3E)==4) // BEQ/BNE
9555           {
9556             alloc_cc(&current,i-1);
9557             dirty_reg(&current,CCREG);
9558             if((rs1[i-1]&&(rs1[i-1]==rt1[i]||rs1[i-1]==rt2[i]))||
9559                (rs2[i-1]&&(rs2[i-1]==rt1[i]||rs2[i-1]==rt2[i]))) {
9560               // The delay slot overwrote one of our conditions
9561               // Delay slot goes after the test (in order)
9562               current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
9563               current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i]));
9564               if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9565               current.u|=1;
9566               current.uu|=1;
9567               delayslot_alloc(&current,i);
9568               current.isconst=0;
9569             }
9570             else
9571             {
9572               current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1]));
9573               current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i-1])|(1LL<<us2[i-1]));
9574               // Alloc the branch condition registers
9575               if(rs1[i-1]) alloc_reg(&current,i-1,rs1[i-1]);
9576               if(rs2[i-1]) alloc_reg(&current,i-1,rs2[i-1]);
9577               if(!((current.is32>>rs1[i-1])&(current.is32>>rs2[i-1])&1))
9578               {
9579                 if(rs1[i-1]) alloc_reg64(&current,i-1,rs1[i-1]);
9580                 if(rs2[i-1]) alloc_reg64(&current,i-1,rs2[i-1]);
9581               }
9582             }
9583             memcpy(&branch_regs[i-1],&current,sizeof(current));
9584             branch_regs[i-1].isconst=0;
9585             branch_regs[i-1].wasconst=0;
9586             memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
9587             memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9588           }
9589           else
9590           if((opcode[i-1]&0x3E)==6) // BLEZ/BGTZ
9591           {
9592             alloc_cc(&current,i-1);
9593             dirty_reg(&current,CCREG);
9594             if(rs1[i-1]==rt1[i]||rs1[i-1]==rt2[i]) {
9595               // The delay slot overwrote the branch condition
9596               // Delay slot goes after the test (in order)
9597               current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
9598               current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i]));
9599               if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9600               current.u|=1;
9601               current.uu|=1;
9602               delayslot_alloc(&current,i);
9603               current.isconst=0;
9604             }
9605             else
9606             {
9607               current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]);
9608               current.uu=branch_unneeded_reg_upper[i-1]&~(1LL<<us1[i-1]);
9609               // Alloc the branch condition register
9610               alloc_reg(&current,i-1,rs1[i-1]);
9611               if(!(current.is32>>rs1[i-1]&1))
9612               {
9613                 alloc_reg64(&current,i-1,rs1[i-1]);
9614               }
9615             }
9616             memcpy(&branch_regs[i-1],&current,sizeof(current));
9617             branch_regs[i-1].isconst=0;
9618             branch_regs[i-1].wasconst=0;
9619             memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
9620             memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9621           }
9622           else
9623           // Alloc the delay slot in case the branch is taken
9624           if((opcode[i-1]&0x3E)==0x14) // BEQL/BNEL
9625           {
9626             memcpy(&branch_regs[i-1],&current,sizeof(current));
9627             branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9628             branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9629             if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9630             alloc_cc(&branch_regs[i-1],i);
9631             dirty_reg(&branch_regs[i-1],CCREG);
9632             delayslot_alloc(&branch_regs[i-1],i);
9633             branch_regs[i-1].isconst=0;
9634             alloc_reg(&current,i,CCREG); // Not taken path
9635             dirty_reg(&current,CCREG);
9636             memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9637           }
9638           else
9639           if((opcode[i-1]&0x3E)==0x16) // BLEZL/BGTZL
9640           {
9641             memcpy(&branch_regs[i-1],&current,sizeof(current));
9642             branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9643             branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9644             if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9645             alloc_cc(&branch_regs[i-1],i);
9646             dirty_reg(&branch_regs[i-1],CCREG);
9647             delayslot_alloc(&branch_regs[i-1],i);
9648             branch_regs[i-1].isconst=0;
9649             alloc_reg(&current,i,CCREG); // Not taken path
9650             dirty_reg(&current,CCREG);
9651             memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9652           }
9653           break;
9654         case SJUMP:
9655           //if((opcode2[i-1]&0x1E)==0) // BLTZ/BGEZ
9656           if((opcode2[i-1]&0x0E)==0) // BLTZ/BGEZ
9657           {
9658             alloc_cc(&current,i-1);
9659             dirty_reg(&current,CCREG);
9660             if(rs1[i-1]==rt1[i]||rs1[i-1]==rt2[i]) {
9661               // The delay slot overwrote the branch condition
9662               // Delay slot goes after the test (in order)
9663               current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
9664               current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i]));
9665               if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9666               current.u|=1;
9667               current.uu|=1;
9668               delayslot_alloc(&current,i);
9669               current.isconst=0;
9670             }
9671             else
9672             {
9673               current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]);
9674               current.uu=branch_unneeded_reg_upper[i-1]&~(1LL<<us1[i-1]);
9675               // Alloc the branch condition register
9676               alloc_reg(&current,i-1,rs1[i-1]);
9677               if(!(current.is32>>rs1[i-1]&1))
9678               {
9679                 alloc_reg64(&current,i-1,rs1[i-1]);
9680               }
9681             }
9682             memcpy(&branch_regs[i-1],&current,sizeof(current));
9683             branch_regs[i-1].isconst=0;
9684             branch_regs[i-1].wasconst=0;
9685             memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
9686             memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9687           }
9688           else
9689           // Alloc the delay slot in case the branch is taken
9690           if((opcode2[i-1]&0x1E)==2) // BLTZL/BGEZL
9691           {
9692             memcpy(&branch_regs[i-1],&current,sizeof(current));
9693             branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9694             branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9695             if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9696             alloc_cc(&branch_regs[i-1],i);
9697             dirty_reg(&branch_regs[i-1],CCREG);
9698             delayslot_alloc(&branch_regs[i-1],i);
9699             branch_regs[i-1].isconst=0;
9700             alloc_reg(&current,i,CCREG); // Not taken path
9701             dirty_reg(&current,CCREG);
9702             memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9703           }
9704           // FIXME: BLTZAL/BGEZAL
9705           if(opcode2[i-1]&0x10) { // BxxZAL
9706             alloc_reg(&branch_regs[i-1],i-1,31);
9707             dirty_reg(&branch_regs[i-1],31);
9708             branch_regs[i-1].is32|=1LL<<31;
9709           }
9710           break;
9711         case FJUMP:
9712           if(likely[i-1]==0) // BC1F/BC1T
9713           {
9714             alloc_cc(&current,i-1);
9715             dirty_reg(&current,CCREG);
9716             if(itype[i]==FCOMP) {
9717               // The delay slot overwrote the branch condition
9718               // Delay slot goes after the test (in order)
9719               delayslot_alloc(&current,i);
9720               current.isconst=0;
9721             }
9722             else
9723             {
9724               current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]);
9725               current.uu=branch_unneeded_reg_upper[i-1]&~(1LL<<us1[i-1]);
9726               // Alloc the branch condition register
9727               alloc_reg(&current,i-1,FSREG);
9728             }
9729             memcpy(&branch_regs[i-1],&current,sizeof(current));
9730             memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
9731           }
9732           else // BC1FL/BC1TL
9733           {
9734             // Alloc the delay slot in case the branch is taken
9735             memcpy(&branch_regs[i-1],&current,sizeof(current));
9736             branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9737             branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9738             if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9739             alloc_cc(&branch_regs[i-1],i);
9740             dirty_reg(&branch_regs[i-1],CCREG);
9741             delayslot_alloc(&branch_regs[i-1],i);
9742             branch_regs[i-1].isconst=0;
9743             alloc_reg(&current,i,CCREG); // Not taken path
9744             dirty_reg(&current,CCREG);
9745             memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9746           }
9747           break;
9748       }
9749
9750       if(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)
9751       {
9752         if(rt1[i-1]==31) // JAL/JALR
9753         {
9754           // Subroutine call will return here, don't alloc any registers
9755           current.is32=1;
9756           current.dirty=0;
9757           clear_all_regs(current.regmap);
9758           alloc_reg(&current,i,CCREG);
9759           dirty_reg(&current,CCREG);
9760         }
9761         else if(i+1<slen)
9762         {
9763           // Internal branch will jump here, match registers to caller
9764           current.is32=0x3FFFFFFFFLL;
9765           current.dirty=0;
9766           clear_all_regs(current.regmap);
9767           alloc_reg(&current,i,CCREG);
9768           dirty_reg(&current,CCREG);
9769           for(j=i-1;j>=0;j--)
9770           {
9771             if(ba[j]==start+i*4+4) {
9772               memcpy(current.regmap,branch_regs[j].regmap,sizeof(current.regmap));
9773               current.is32=branch_regs[j].is32;
9774               current.dirty=branch_regs[j].dirty;
9775               break;
9776             }
9777           }
9778           while(j>=0) {
9779             if(ba[j]==start+i*4+4) {
9780               for(hr=0;hr<HOST_REGS;hr++) {
9781                 if(current.regmap[hr]!=branch_regs[j].regmap[hr]) {
9782                   current.regmap[hr]=-1;
9783                 }
9784                 current.is32&=branch_regs[j].is32;
9785                 current.dirty&=branch_regs[j].dirty;
9786               }
9787             }
9788             j--;
9789           }
9790         }
9791       }
9792     }
9793
9794     // Count cycles in between branches
9795     ccadj[i]=cc;
9796     if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP||itype[i]==SYSCALL||itype[i]==HLECALL))
9797     {
9798       cc=0;
9799     }
9800 #if defined(PCSX) && !defined(DRC_DBG)
9801     else if(itype[i]==C2OP&&gte_cycletab[source[i]&0x3f]>2)
9802     {
9803       // GTE runs in parallel until accessed, divide by 2 for a rough guess
9804       cc+=gte_cycletab[source[i]&0x3f]/2;
9805     }
9806     else if(/*itype[i]==LOAD||*/itype[i]==STORE||itype[i]==C1LS) // load causes weird timing issues
9807     {
9808       cc+=2; // 2 cycle penalty (after CLOCK_DIVIDER)
9809     }
9810     else if(itype[i]==C2LS)
9811     {
9812       cc+=4;
9813     }
9814 #endif
9815     else
9816     {
9817       cc++;
9818     }
9819
9820     flush_dirty_uppers(&current);
9821     if(!is_ds[i]) {
9822       regs[i].is32=current.is32;
9823       regs[i].dirty=current.dirty;
9824       regs[i].isconst=current.isconst;
9825       memcpy(constmap[i],current.constmap,sizeof(current.constmap));
9826     }
9827     for(hr=0;hr<HOST_REGS;hr++) {
9828       if(hr!=EXCLUDE_REG&&regs[i].regmap[hr]>=0) {
9829         if(regmap_pre[i][hr]!=regs[i].regmap[hr]) {
9830           regs[i].wasconst&=~(1<<hr);
9831         }
9832       }
9833     }
9834     if(current.regmap[HOST_BTREG]==BTREG) current.regmap[HOST_BTREG]=-1;
9835     regs[i].waswritten=current.waswritten;
9836   }
9837
9838   /* Pass 4 - Cull unused host registers */
9839
9840   uint64_t nr=0;
9841
9842   for (i=slen-1;i>=0;i--)
9843   {
9844     int hr;
9845     if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
9846     {
9847       if(ba[i]<start || ba[i]>=(start+slen*4))
9848       {
9849         // Branch out of this block, don't need anything
9850         nr=0;
9851       }
9852       else
9853       {
9854         // Internal branch
9855         // Need whatever matches the target
9856         nr=0;
9857         int t=(ba[i]-start)>>2;
9858         for(hr=0;hr<HOST_REGS;hr++)
9859         {
9860           if(regs[i].regmap_entry[hr]>=0) {
9861             if(regs[i].regmap_entry[hr]==regs[t].regmap_entry[hr]) nr|=1<<hr;
9862           }
9863         }
9864       }
9865       // Conditional branch may need registers for following instructions
9866       if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
9867       {
9868         if(i<slen-2) {
9869           nr|=needed_reg[i+2];
9870           for(hr=0;hr<HOST_REGS;hr++)
9871           {
9872             if(regmap_pre[i+2][hr]>=0&&get_reg(regs[i+2].regmap_entry,regmap_pre[i+2][hr])<0) nr&=~(1<<hr);
9873             //if((regmap_entry[i+2][hr])>=0) if(!((nr>>hr)&1)) printf("%x-bogus(%d=%d)\n",start+i*4,hr,regmap_entry[i+2][hr]);
9874           }
9875         }
9876       }
9877       // Don't need stuff which is overwritten
9878       //if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr);
9879       //if(regs[i].regmap[hr]<0) nr&=~(1<<hr);
9880       // Merge in delay slot
9881       for(hr=0;hr<HOST_REGS;hr++)
9882       {
9883         if(!likely[i]) {
9884           // These are overwritten unless the branch is "likely"
9885           // and the delay slot is nullified if not taken
9886           if(rt1[i+1]&&rt1[i+1]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9887           if(rt2[i+1]&&rt2[i+1]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9888         }
9889         if(us1[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9890         if(us2[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9891         if(rs1[i+1]==regmap_pre[i][hr]) nr|=1<<hr;
9892         if(rs2[i+1]==regmap_pre[i][hr]) nr|=1<<hr;
9893         if(us1[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9894         if(us2[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9895         if(rs1[i+1]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9896         if(rs2[i+1]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9897         if(dep1[i+1]&&!((unneeded_reg_upper[i]>>dep1[i+1])&1)) {
9898           if(dep1[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9899           if(dep2[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9900         }
9901         if(dep2[i+1]&&!((unneeded_reg_upper[i]>>dep2[i+1])&1)) {
9902           if(dep1[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9903           if(dep2[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9904         }
9905         if(itype[i+1]==STORE || itype[i+1]==STORELR || (opcode[i+1]&0x3b)==0x39 || (opcode[i+1]&0x3b)==0x3a) {
9906           if(regmap_pre[i][hr]==INVCP) nr|=1<<hr;
9907           if(regs[i].regmap_entry[hr]==INVCP) nr|=1<<hr;
9908         }
9909       }
9910     }
9911     else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
9912     {
9913       // SYSCALL instruction (software interrupt)
9914       nr=0;
9915     }
9916     else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
9917     {
9918       // ERET instruction (return from interrupt)
9919       nr=0;
9920     }
9921     else // Non-branch
9922     {
9923       if(i<slen-1) {
9924         for(hr=0;hr<HOST_REGS;hr++) {
9925           if(regmap_pre[i+1][hr]>=0&&get_reg(regs[i+1].regmap_entry,regmap_pre[i+1][hr])<0) nr&=~(1<<hr);
9926           if(regs[i].regmap[hr]!=regmap_pre[i+1][hr]) nr&=~(1<<hr);
9927           if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr);
9928           if(regs[i].regmap[hr]<0) nr&=~(1<<hr);
9929         }
9930       }
9931     }
9932     for(hr=0;hr<HOST_REGS;hr++)
9933     {
9934       // Overwritten registers are not needed
9935       if(rt1[i]&&rt1[i]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9936       if(rt2[i]&&rt2[i]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9937       if(FTEMP==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9938       // Source registers are needed
9939       if(us1[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9940       if(us2[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9941       if(rs1[i]==regmap_pre[i][hr]) nr|=1<<hr;
9942       if(rs2[i]==regmap_pre[i][hr]) nr|=1<<hr;
9943       if(us1[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9944       if(us2[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9945       if(rs1[i]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9946       if(rs2[i]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9947       if(dep1[i]&&!((unneeded_reg_upper[i]>>dep1[i])&1)) {
9948         if(dep1[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9949         if(dep1[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9950       }
9951       if(dep2[i]&&!((unneeded_reg_upper[i]>>dep2[i])&1)) {
9952         if(dep2[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9953         if(dep2[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9954       }
9955       if(itype[i]==STORE || itype[i]==STORELR || (opcode[i]&0x3b)==0x39 || (opcode[i]&0x3b)==0x3a) {
9956         if(regmap_pre[i][hr]==INVCP) nr|=1<<hr;
9957         if(regs[i].regmap_entry[hr]==INVCP) nr|=1<<hr;
9958       }
9959       // Don't store a register immediately after writing it,
9960       // may prevent dual-issue.
9961       // But do so if this is a branch target, otherwise we
9962       // might have to load the register before the branch.
9963       if(i>0&&!bt[i]&&((regs[i].wasdirty>>hr)&1)) {
9964         if((regmap_pre[i][hr]>0&&regmap_pre[i][hr]<64&&!((unneeded_reg[i]>>regmap_pre[i][hr])&1)) ||
9965            (regmap_pre[i][hr]>64&&!((unneeded_reg_upper[i]>>(regmap_pre[i][hr]&63))&1)) ) {
9966           if(rt1[i-1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9967           if(rt2[i-1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9968         }
9969         if((regs[i].regmap_entry[hr]>0&&regs[i].regmap_entry[hr]<64&&!((unneeded_reg[i]>>regs[i].regmap_entry[hr])&1)) ||
9970            (regs[i].regmap_entry[hr]>64&&!((unneeded_reg_upper[i]>>(regs[i].regmap_entry[hr]&63))&1)) ) {
9971           if(rt1[i-1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9972           if(rt2[i-1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9973         }
9974       }
9975     }
9976     // Cycle count is needed at branches.  Assume it is needed at the target too.
9977     if(i==0||bt[i]||itype[i]==CJUMP||itype[i]==FJUMP||itype[i]==SPAN) {
9978       if(regmap_pre[i][HOST_CCREG]==CCREG) nr|=1<<HOST_CCREG;
9979       if(regs[i].regmap_entry[HOST_CCREG]==CCREG) nr|=1<<HOST_CCREG;
9980     }
9981     // Save it
9982     needed_reg[i]=nr;
9983
9984     // Deallocate unneeded registers
9985     for(hr=0;hr<HOST_REGS;hr++)
9986     {
9987       if(!((nr>>hr)&1)) {
9988         if(regs[i].regmap_entry[hr]!=CCREG) regs[i].regmap_entry[hr]=-1;
9989         if((regs[i].regmap[hr]&63)!=rs1[i] && (regs[i].regmap[hr]&63)!=rs2[i] &&
9990            (regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] &&
9991            (regs[i].regmap[hr]&63)!=PTEMP && (regs[i].regmap[hr]&63)!=CCREG)
9992         {
9993           if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
9994           {
9995             if(likely[i]) {
9996               regs[i].regmap[hr]=-1;
9997               regs[i].isconst&=~(1<<hr);
9998               if(i<slen-2) {
9999                 regmap_pre[i+2][hr]=-1;
10000                 regs[i+2].wasconst&=~(1<<hr);
10001               }
10002             }
10003           }
10004         }
10005         if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
10006         {
10007           int d1=0,d2=0,map=0,temp=0;
10008           if(get_reg(regs[i].regmap,rt1[i+1]|64)>=0||get_reg(branch_regs[i].regmap,rt1[i+1]|64)>=0)
10009           {
10010             d1=dep1[i+1];
10011             d2=dep2[i+1];
10012           }
10013           if(using_tlb) {
10014             if(itype[i+1]==LOAD || itype[i+1]==LOADLR ||
10015                itype[i+1]==STORE || itype[i+1]==STORELR ||
10016                itype[i+1]==C1LS || itype[i+1]==C2LS)
10017             map=TLREG;
10018           } else
10019           if(itype[i+1]==STORE || itype[i+1]==STORELR ||
10020              (opcode[i+1]&0x3b)==0x39 || (opcode[i+1]&0x3b)==0x3a) { // SWC1/SDC1 || SWC2/SDC2
10021             map=INVCP;
10022           }
10023           if(itype[i+1]==LOADLR || itype[i+1]==STORELR ||
10024              itype[i+1]==C1LS || itype[i+1]==C2LS)
10025             temp=FTEMP;
10026           if((regs[i].regmap[hr]&63)!=rs1[i] && (regs[i].regmap[hr]&63)!=rs2[i] &&
10027              (regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] &&
10028              (regs[i].regmap[hr]&63)!=rt1[i+1] && (regs[i].regmap[hr]&63)!=rt2[i+1] &&
10029              (regs[i].regmap[hr]^64)!=us1[i+1] && (regs[i].regmap[hr]^64)!=us2[i+1] &&
10030              (regs[i].regmap[hr]^64)!=d1 && (regs[i].regmap[hr]^64)!=d2 &&
10031              regs[i].regmap[hr]!=rs1[i+1] && regs[i].regmap[hr]!=rs2[i+1] &&
10032              (regs[i].regmap[hr]&63)!=temp && regs[i].regmap[hr]!=PTEMP &&
10033              regs[i].regmap[hr]!=RHASH && regs[i].regmap[hr]!=RHTBL &&
10034              regs[i].regmap[hr]!=RTEMP && regs[i].regmap[hr]!=CCREG &&
10035              regs[i].regmap[hr]!=map )
10036           {
10037             regs[i].regmap[hr]=-1;
10038             regs[i].isconst&=~(1<<hr);
10039             if((branch_regs[i].regmap[hr]&63)!=rs1[i] && (branch_regs[i].regmap[hr]&63)!=rs2[i] &&
10040                (branch_regs[i].regmap[hr]&63)!=rt1[i] && (branch_regs[i].regmap[hr]&63)!=rt2[i] &&
10041                (branch_regs[i].regmap[hr]&63)!=rt1[i+1] && (branch_regs[i].regmap[hr]&63)!=rt2[i+1] &&
10042                (branch_regs[i].regmap[hr]^64)!=us1[i+1] && (branch_regs[i].regmap[hr]^64)!=us2[i+1] &&
10043                (branch_regs[i].regmap[hr]^64)!=d1 && (branch_regs[i].regmap[hr]^64)!=d2 &&
10044                branch_regs[i].regmap[hr]!=rs1[i+1] && branch_regs[i].regmap[hr]!=rs2[i+1] &&
10045                (branch_regs[i].regmap[hr]&63)!=temp && branch_regs[i].regmap[hr]!=PTEMP &&
10046                branch_regs[i].regmap[hr]!=RHASH && branch_regs[i].regmap[hr]!=RHTBL &&
10047                branch_regs[i].regmap[hr]!=RTEMP && branch_regs[i].regmap[hr]!=CCREG &&
10048                branch_regs[i].regmap[hr]!=map)
10049             {
10050               branch_regs[i].regmap[hr]=-1;
10051               branch_regs[i].regmap_entry[hr]=-1;
10052               if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
10053               {
10054                 if(!likely[i]&&i<slen-2) {
10055                   regmap_pre[i+2][hr]=-1;
10056                   regs[i+2].wasconst&=~(1<<hr);
10057                 }
10058               }
10059             }
10060           }
10061         }
10062         else
10063         {
10064           // Non-branch
10065           if(i>0)
10066           {
10067             int d1=0,d2=0,map=-1,temp=-1;
10068             if(get_reg(regs[i].regmap,rt1[i]|64)>=0)
10069             {
10070               d1=dep1[i];
10071               d2=dep2[i];
10072             }
10073             if(using_tlb) {
10074               if(itype[i]==LOAD || itype[i]==LOADLR ||
10075                  itype[i]==STORE || itype[i]==STORELR ||
10076                  itype[i]==C1LS || itype[i]==C2LS)
10077               map=TLREG;
10078             } else if(itype[i]==STORE || itype[i]==STORELR ||
10079                       (opcode[i]&0x3b)==0x39 || (opcode[i]&0x3b)==0x3a) { // SWC1/SDC1 || SWC2/SDC2
10080               map=INVCP;
10081             }
10082             if(itype[i]==LOADLR || itype[i]==STORELR ||
10083                itype[i]==C1LS || itype[i]==C2LS)
10084               temp=FTEMP;
10085             if((regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] &&
10086                (regs[i].regmap[hr]^64)!=us1[i] && (regs[i].regmap[hr]^64)!=us2[i] &&
10087                (regs[i].regmap[hr]^64)!=d1 && (regs[i].regmap[hr]^64)!=d2 &&
10088                regs[i].regmap[hr]!=rs1[i] && regs[i].regmap[hr]!=rs2[i] &&
10089                (regs[i].regmap[hr]&63)!=temp && regs[i].regmap[hr]!=map &&
10090                (itype[i]!=SPAN||regs[i].regmap[hr]!=CCREG))
10091             {
10092               if(i<slen-1&&!is_ds[i]) {
10093                 if(regmap_pre[i+1][hr]!=-1 || regs[i].regmap[hr]!=-1)
10094                 if(regmap_pre[i+1][hr]!=regs[i].regmap[hr])
10095                 if(regs[i].regmap[hr]<64||!((regs[i].was32>>(regs[i].regmap[hr]&63))&1))
10096                 {
10097                   printf("fail: %x (%d %d!=%d)\n",start+i*4,hr,regmap_pre[i+1][hr],regs[i].regmap[hr]);
10098                   assert(regmap_pre[i+1][hr]==regs[i].regmap[hr]);
10099                 }
10100                 regmap_pre[i+1][hr]=-1;
10101                 if(regs[i+1].regmap_entry[hr]==CCREG) regs[i+1].regmap_entry[hr]=-1;
10102                 regs[i+1].wasconst&=~(1<<hr);
10103               }
10104               regs[i].regmap[hr]=-1;
10105               regs[i].isconst&=~(1<<hr);
10106             }
10107           }
10108         }
10109       }
10110     }
10111   }
10112
10113   /* Pass 5 - Pre-allocate registers */
10114
10115   // If a register is allocated during a loop, try to allocate it for the
10116   // entire loop, if possible.  This avoids loading/storing registers
10117   // inside of the loop.
10118
10119   signed char f_regmap[HOST_REGS];
10120   clear_all_regs(f_regmap);
10121   for(i=0;i<slen-1;i++)
10122   {
10123     if(itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
10124     {
10125       if(ba[i]>=start && ba[i]<(start+i*4))
10126       if(itype[i+1]==NOP||itype[i+1]==MOV||itype[i+1]==ALU
10127       ||itype[i+1]==SHIFTIMM||itype[i+1]==IMM16||itype[i+1]==LOAD
10128       ||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS
10129       ||itype[i+1]==SHIFT||itype[i+1]==COP1||itype[i+1]==FLOAT
10130       ||itype[i+1]==FCOMP||itype[i+1]==FCONV
10131       ||itype[i+1]==COP2||itype[i+1]==C2LS||itype[i+1]==C2OP)
10132       {
10133         int t=(ba[i]-start)>>2;
10134         if(t>0&&(itype[t-1]!=UJUMP&&itype[t-1]!=RJUMP&&itype[t-1]!=CJUMP&&itype[t-1]!=SJUMP&&itype[t-1]!=FJUMP)) // loop_preload can't handle jumps into delay slots
10135         if(t<2||(itype[t-2]!=UJUMP&&itype[t-2]!=RJUMP)||rt1[t-2]!=31) // call/ret assumes no registers allocated
10136         for(hr=0;hr<HOST_REGS;hr++)
10137         {
10138           if(regs[i].regmap[hr]>64) {
10139             if(!((regs[i].dirty>>hr)&1))
10140               f_regmap[hr]=regs[i].regmap[hr];
10141             else f_regmap[hr]=-1;
10142           }
10143           else if(regs[i].regmap[hr]>=0) {
10144             if(f_regmap[hr]!=regs[i].regmap[hr]) {
10145               // dealloc old register
10146               int n;
10147               for(n=0;n<HOST_REGS;n++)
10148               {
10149                 if(f_regmap[n]==regs[i].regmap[hr]) {f_regmap[n]=-1;}
10150               }
10151               // and alloc new one
10152               f_regmap[hr]=regs[i].regmap[hr];
10153             }
10154           }
10155           if(branch_regs[i].regmap[hr]>64) {
10156             if(!((branch_regs[i].dirty>>hr)&1))
10157               f_regmap[hr]=branch_regs[i].regmap[hr];
10158             else f_regmap[hr]=-1;
10159           }
10160           else if(branch_regs[i].regmap[hr]>=0) {
10161             if(f_regmap[hr]!=branch_regs[i].regmap[hr]) {
10162               // dealloc old register
10163               int n;
10164               for(n=0;n<HOST_REGS;n++)
10165               {
10166                 if(f_regmap[n]==branch_regs[i].regmap[hr]) {f_regmap[n]=-1;}
10167               }
10168               // and alloc new one
10169               f_regmap[hr]=branch_regs[i].regmap[hr];
10170             }
10171           }
10172           if(ooo[i]) {
10173             if(count_free_regs(regs[i].regmap)<=minimum_free_regs[i+1])
10174               f_regmap[hr]=branch_regs[i].regmap[hr];
10175           }else{
10176             if(count_free_regs(branch_regs[i].regmap)<=minimum_free_regs[i+1])
10177               f_regmap[hr]=branch_regs[i].regmap[hr];
10178           }
10179           // Avoid dirty->clean transition
10180           #ifdef DESTRUCTIVE_WRITEBACK
10181           if(t>0) if(get_reg(regmap_pre[t],f_regmap[hr])>=0) if((regs[t].wasdirty>>get_reg(regmap_pre[t],f_regmap[hr]))&1) f_regmap[hr]=-1;
10182           #endif
10183           // This check is only strictly required in the DESTRUCTIVE_WRITEBACK
10184           // case above, however it's always a good idea.  We can't hoist the
10185           // load if the register was already allocated, so there's no point
10186           // wasting time analyzing most of these cases.  It only "succeeds"
10187           // when the mapping was different and the load can be replaced with
10188           // a mov, which is of negligible benefit.  So such cases are
10189           // skipped below.
10190           if(f_regmap[hr]>0) {
10191             if(regs[t].regmap[hr]==f_regmap[hr]||(regs[t].regmap_entry[hr]<0&&get_reg(regmap_pre[t],f_regmap[hr])<0)) {
10192               int r=f_regmap[hr];
10193               for(j=t;j<=i;j++)
10194               {
10195                 //printf("Test %x -> %x, %x %d/%d\n",start+i*4,ba[i],start+j*4,hr,r);
10196                 if(r<34&&((unneeded_reg[j]>>r)&1)) break;
10197                 if(r>63&&((unneeded_reg_upper[j]>>(r&63))&1)) break;
10198                 if(r>63) {
10199                   // NB This can exclude the case where the upper-half
10200                   // register is lower numbered than the lower-half
10201                   // register.  Not sure if it's worth fixing...
10202                   if(get_reg(regs[j].regmap,r&63)<0) break;
10203                   if(get_reg(regs[j].regmap_entry,r&63)<0) break;
10204                   if(regs[j].is32&(1LL<<(r&63))) break;
10205                 }
10206                 if(regs[j].regmap[hr]==f_regmap[hr]&&(f_regmap[hr]&63)<TEMPREG) {
10207                   //printf("Hit %x -> %x, %x %d/%d\n",start+i*4,ba[i],start+j*4,hr,r);
10208                   int k;
10209                   if(regs[i].regmap[hr]==-1&&branch_regs[i].regmap[hr]==-1) {
10210                     if(get_reg(regs[i+2].regmap,f_regmap[hr])>=0) break;
10211                     if(r>63) {
10212                       if(get_reg(regs[i].regmap,r&63)<0) break;
10213                       if(get_reg(branch_regs[i].regmap,r&63)<0) break;
10214                     }
10215                     k=i;
10216                     while(k>1&&regs[k-1].regmap[hr]==-1) {
10217                       if(count_free_regs(regs[k-1].regmap)<=minimum_free_regs[k-1]) {
10218                         //printf("no free regs for store %x\n",start+(k-1)*4);
10219                         break;
10220                       }
10221                       if(get_reg(regs[k-1].regmap,f_regmap[hr])>=0) {
10222                         //printf("no-match due to different register\n");
10223                         break;
10224                       }
10225                       if(itype[k-2]==UJUMP||itype[k-2]==RJUMP||itype[k-2]==CJUMP||itype[k-2]==SJUMP||itype[k-2]==FJUMP) {
10226                         //printf("no-match due to branch\n");
10227                         break;
10228                       }
10229                       // call/ret fast path assumes no registers allocated
10230                       if(k>2&&(itype[k-3]==UJUMP||itype[k-3]==RJUMP)&&rt1[k-3]==31) {
10231                         break;
10232                       }
10233                       if(r>63) {
10234                         // NB This can exclude the case where the upper-half
10235                         // register is lower numbered than the lower-half
10236                         // register.  Not sure if it's worth fixing...
10237                         if(get_reg(regs[k-1].regmap,r&63)<0) break;
10238                         if(regs[k-1].is32&(1LL<<(r&63))) break;
10239                       }
10240                       k--;
10241                     }
10242                     if(i<slen-1) {
10243                       if((regs[k].is32&(1LL<<f_regmap[hr]))!=
10244                         (regs[i+2].was32&(1LL<<f_regmap[hr]))) {
10245                         //printf("bad match after branch\n");
10246                         break;
10247                       }
10248                     }
10249                     if(regs[k-1].regmap[hr]==f_regmap[hr]&&regmap_pre[k][hr]==f_regmap[hr]) {
10250                       //printf("Extend r%d, %x ->\n",hr,start+k*4);
10251                       while(k<i) {
10252                         regs[k].regmap_entry[hr]=f_regmap[hr];
10253                         regs[k].regmap[hr]=f_regmap[hr];
10254                         regmap_pre[k+1][hr]=f_regmap[hr];
10255                         regs[k].wasdirty&=~(1<<hr);
10256                         regs[k].dirty&=~(1<<hr);
10257                         regs[k].wasdirty|=(1<<hr)&regs[k-1].dirty;
10258                         regs[k].dirty|=(1<<hr)&regs[k].wasdirty;
10259                         regs[k].wasconst&=~(1<<hr);
10260                         regs[k].isconst&=~(1<<hr);
10261                         k++;
10262                       }
10263                     }
10264                     else {
10265                       //printf("Fail Extend r%d, %x ->\n",hr,start+k*4);
10266                       break;
10267                     }
10268                     assert(regs[i-1].regmap[hr]==f_regmap[hr]);
10269                     if(regs[i-1].regmap[hr]==f_regmap[hr]&&regmap_pre[i][hr]==f_regmap[hr]) {
10270                       //printf("OK fill %x (r%d)\n",start+i*4,hr);
10271                       regs[i].regmap_entry[hr]=f_regmap[hr];
10272                       regs[i].regmap[hr]=f_regmap[hr];
10273                       regs[i].wasdirty&=~(1<<hr);
10274                       regs[i].dirty&=~(1<<hr);
10275                       regs[i].wasdirty|=(1<<hr)&regs[i-1].dirty;
10276                       regs[i].dirty|=(1<<hr)&regs[i-1].dirty;
10277                       regs[i].wasconst&=~(1<<hr);
10278                       regs[i].isconst&=~(1<<hr);
10279                       branch_regs[i].regmap_entry[hr]=f_regmap[hr];
10280                       branch_regs[i].wasdirty&=~(1<<hr);
10281                       branch_regs[i].wasdirty|=(1<<hr)&regs[i].dirty;
10282                       branch_regs[i].regmap[hr]=f_regmap[hr];
10283                       branch_regs[i].dirty&=~(1<<hr);
10284                       branch_regs[i].dirty|=(1<<hr)&regs[i].dirty;
10285                       branch_regs[i].wasconst&=~(1<<hr);
10286                       branch_regs[i].isconst&=~(1<<hr);
10287                       if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000) {
10288                         regmap_pre[i+2][hr]=f_regmap[hr];
10289                         regs[i+2].wasdirty&=~(1<<hr);
10290                         regs[i+2].wasdirty|=(1<<hr)&regs[i].dirty;
10291                         assert((branch_regs[i].is32&(1LL<<f_regmap[hr]))==
10292                           (regs[i+2].was32&(1LL<<f_regmap[hr])));
10293                       }
10294                     }
10295                   }
10296                   for(k=t;k<j;k++) {
10297                     // Alloc register clean at beginning of loop,
10298                     // but may dirty it in pass 6
10299                     regs[k].regmap_entry[hr]=f_regmap[hr];
10300                     regs[k].regmap[hr]=f_regmap[hr];
10301                     regs[k].dirty&=~(1<<hr);
10302                     regs[k].wasconst&=~(1<<hr);
10303                     regs[k].isconst&=~(1<<hr);
10304                     if(itype[k]==UJUMP||itype[k]==RJUMP||itype[k]==CJUMP||itype[k]==SJUMP||itype[k]==FJUMP) {
10305                       branch_regs[k].regmap_entry[hr]=f_regmap[hr];
10306                       branch_regs[k].regmap[hr]=f_regmap[hr];
10307                       branch_regs[k].dirty&=~(1<<hr);
10308                       branch_regs[k].wasconst&=~(1<<hr);
10309                       branch_regs[k].isconst&=~(1<<hr);
10310                       if(itype[k]!=RJUMP&&itype[k]!=UJUMP&&(source[k]>>16)!=0x1000) {
10311                         regmap_pre[k+2][hr]=f_regmap[hr];
10312                         regs[k+2].wasdirty&=~(1<<hr);
10313                         assert((branch_regs[k].is32&(1LL<<f_regmap[hr]))==
10314                           (regs[k+2].was32&(1LL<<f_regmap[hr])));
10315                       }
10316                     }
10317                     else
10318                     {
10319                       regmap_pre[k+1][hr]=f_regmap[hr];
10320                       regs[k+1].wasdirty&=~(1<<hr);
10321                     }
10322                   }
10323                   if(regs[j].regmap[hr]==f_regmap[hr])
10324                     regs[j].regmap_entry[hr]=f_regmap[hr];
10325                   break;
10326                 }
10327                 if(j==i) break;
10328                 if(regs[j].regmap[hr]>=0)
10329                   break;
10330                 if(get_reg(regs[j].regmap,f_regmap[hr])>=0) {
10331                   //printf("no-match due to different register\n");
10332                   break;
10333                 }
10334                 if((regs[j+1].is32&(1LL<<f_regmap[hr]))!=(regs[j].is32&(1LL<<f_regmap[hr]))) {
10335                   //printf("32/64 mismatch %x %d\n",start+j*4,hr);
10336                   break;
10337                 }
10338                 if(itype[j]==UJUMP||itype[j]==RJUMP||(source[j]>>16)==0x1000)
10339                 {
10340                   // Stop on unconditional branch
10341                   break;
10342                 }
10343                 if(itype[j]==CJUMP||itype[j]==SJUMP||itype[j]==FJUMP)
10344                 {
10345                   if(ooo[j]) {
10346                     if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j+1])
10347                       break;
10348                   }else{
10349                     if(count_free_regs(branch_regs[j].regmap)<=minimum_free_regs[j+1])
10350                       break;
10351                   }
10352                   if(get_reg(branch_regs[j].regmap,f_regmap[hr])>=0) {
10353                     //printf("no-match due to different register (branch)\n");
10354                     break;
10355                   }
10356                 }
10357                 if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j]) {
10358                   //printf("No free regs for store %x\n",start+j*4);
10359                   break;
10360                 }
10361                 if(f_regmap[hr]>=64) {
10362                   if(regs[j].is32&(1LL<<(f_regmap[hr]&63))) {
10363                     break;
10364                   }
10365                   else
10366                   {
10367                     if(get_reg(regs[j].regmap,f_regmap[hr]&63)<0) {
10368                       break;
10369                     }
10370                   }
10371                 }
10372               }
10373             }
10374           }
10375         }
10376       }
10377     }else{
10378       // Non branch or undetermined branch target
10379       for(hr=0;hr<HOST_REGS;hr++)
10380       {
10381         if(hr!=EXCLUDE_REG) {
10382           if(regs[i].regmap[hr]>64) {
10383             if(!((regs[i].dirty>>hr)&1))
10384               f_regmap[hr]=regs[i].regmap[hr];
10385           }
10386           else if(regs[i].regmap[hr]>=0) {
10387             if(f_regmap[hr]!=regs[i].regmap[hr]) {
10388               // dealloc old register
10389               int n;
10390               for(n=0;n<HOST_REGS;n++)
10391               {
10392                 if(f_regmap[n]==regs[i].regmap[hr]) {f_regmap[n]=-1;}
10393               }
10394               // and alloc new one
10395               f_regmap[hr]=regs[i].regmap[hr];
10396             }
10397           }
10398         }
10399       }
10400       // Try to restore cycle count at branch targets
10401       if(bt[i]) {
10402         for(j=i;j<slen-1;j++) {
10403           if(regs[j].regmap[HOST_CCREG]!=-1) break;
10404           if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j]) {
10405             //printf("no free regs for store %x\n",start+j*4);
10406             break;
10407           }
10408         }
10409         if(regs[j].regmap[HOST_CCREG]==CCREG) {
10410           int k=i;
10411           //printf("Extend CC, %x -> %x\n",start+k*4,start+j*4);
10412           while(k<j) {
10413             regs[k].regmap_entry[HOST_CCREG]=CCREG;
10414             regs[k].regmap[HOST_CCREG]=CCREG;
10415             regmap_pre[k+1][HOST_CCREG]=CCREG;
10416             regs[k+1].wasdirty|=1<<HOST_CCREG;
10417             regs[k].dirty|=1<<HOST_CCREG;
10418             regs[k].wasconst&=~(1<<HOST_CCREG);
10419             regs[k].isconst&=~(1<<HOST_CCREG);
10420             k++;
10421           }
10422           regs[j].regmap_entry[HOST_CCREG]=CCREG;
10423         }
10424         // Work backwards from the branch target
10425         if(j>i&&f_regmap[HOST_CCREG]==CCREG)
10426         {
10427           //printf("Extend backwards\n");
10428           int k;
10429           k=i;
10430           while(regs[k-1].regmap[HOST_CCREG]==-1) {
10431             if(count_free_regs(regs[k-1].regmap)<=minimum_free_regs[k-1]) {
10432               //printf("no free regs for store %x\n",start+(k-1)*4);
10433               break;
10434             }
10435             k--;
10436           }
10437           if(regs[k-1].regmap[HOST_CCREG]==CCREG) {
10438             //printf("Extend CC, %x ->\n",start+k*4);
10439             while(k<=i) {
10440               regs[k].regmap_entry[HOST_CCREG]=CCREG;
10441               regs[k].regmap[HOST_CCREG]=CCREG;
10442               regmap_pre[k+1][HOST_CCREG]=CCREG;
10443               regs[k+1].wasdirty|=1<<HOST_CCREG;
10444               regs[k].dirty|=1<<HOST_CCREG;
10445               regs[k].wasconst&=~(1<<HOST_CCREG);
10446               regs[k].isconst&=~(1<<HOST_CCREG);
10447               k++;
10448             }
10449           }
10450           else {
10451             //printf("Fail Extend CC, %x ->\n",start+k*4);
10452           }
10453         }
10454       }
10455       if(itype[i]!=STORE&&itype[i]!=STORELR&&itype[i]!=C1LS&&itype[i]!=SHIFT&&
10456          itype[i]!=NOP&&itype[i]!=MOV&&itype[i]!=ALU&&itype[i]!=SHIFTIMM&&
10457          itype[i]!=IMM16&&itype[i]!=LOAD&&itype[i]!=COP1&&itype[i]!=FLOAT&&
10458          itype[i]!=FCONV&&itype[i]!=FCOMP)
10459       {
10460         memcpy(f_regmap,regs[i].regmap,sizeof(f_regmap));
10461       }
10462     }
10463   }
10464
10465   // Cache memory offset or tlb map pointer if a register is available
10466   #ifndef HOST_IMM_ADDR32
10467   #ifndef RAM_OFFSET
10468   if(using_tlb)
10469   #endif
10470   {
10471     int earliest_available[HOST_REGS];
10472     int loop_start[HOST_REGS];
10473     int score[HOST_REGS];
10474     int end[HOST_REGS];
10475     int reg=using_tlb?MMREG:ROREG;
10476
10477     // Init
10478     for(hr=0;hr<HOST_REGS;hr++) {
10479       score[hr]=0;earliest_available[hr]=0;
10480       loop_start[hr]=MAXBLOCK;
10481     }
10482     for(i=0;i<slen-1;i++)
10483     {
10484       // Can't do anything if no registers are available
10485       if(count_free_regs(regs[i].regmap)<=minimum_free_regs[i]) {
10486         for(hr=0;hr<HOST_REGS;hr++) {
10487           score[hr]=0;earliest_available[hr]=i+1;
10488           loop_start[hr]=MAXBLOCK;
10489         }
10490       }
10491       if(itype[i]==UJUMP||itype[i]==RJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP) {
10492         if(!ooo[i]) {
10493           if(count_free_regs(branch_regs[i].regmap)<=minimum_free_regs[i+1]) {
10494             for(hr=0;hr<HOST_REGS;hr++) {
10495               score[hr]=0;earliest_available[hr]=i+1;
10496               loop_start[hr]=MAXBLOCK;
10497             }
10498           }
10499         }else{
10500           if(count_free_regs(regs[i].regmap)<=minimum_free_regs[i+1]) {
10501             for(hr=0;hr<HOST_REGS;hr++) {
10502               score[hr]=0;earliest_available[hr]=i+1;
10503               loop_start[hr]=MAXBLOCK;
10504             }
10505           }
10506         }
10507       }
10508       // Mark unavailable registers
10509       for(hr=0;hr<HOST_REGS;hr++) {
10510         if(regs[i].regmap[hr]>=0) {
10511           score[hr]=0;earliest_available[hr]=i+1;
10512           loop_start[hr]=MAXBLOCK;
10513         }
10514         if(itype[i]==UJUMP||itype[i]==RJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP) {
10515           if(branch_regs[i].regmap[hr]>=0) {
10516             score[hr]=0;earliest_available[hr]=i+2;
10517             loop_start[hr]=MAXBLOCK;
10518           }
10519         }
10520       }
10521       // No register allocations after unconditional jumps
10522       if(itype[i]==UJUMP||itype[i]==RJUMP||(source[i]>>16)==0x1000)
10523       {
10524         for(hr=0;hr<HOST_REGS;hr++) {
10525           score[hr]=0;earliest_available[hr]=i+2;
10526           loop_start[hr]=MAXBLOCK;
10527         }
10528         i++; // Skip delay slot too
10529         //printf("skip delay slot: %x\n",start+i*4);
10530       }
10531       else
10532       // Possible match
10533       if(itype[i]==LOAD||itype[i]==LOADLR||
10534          itype[i]==STORE||itype[i]==STORELR||itype[i]==C1LS) {
10535         for(hr=0;hr<HOST_REGS;hr++) {
10536           if(hr!=EXCLUDE_REG) {
10537             end[hr]=i-1;
10538             for(j=i;j<slen-1;j++) {
10539               if(regs[j].regmap[hr]>=0) break;
10540               if(itype[j]==UJUMP||itype[j]==RJUMP||itype[j]==CJUMP||itype[j]==SJUMP||itype[j]==FJUMP) {
10541                 if(branch_regs[j].regmap[hr]>=0) break;
10542                 if(ooo[j]) {
10543                   if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j+1]) break;
10544                 }else{
10545                   if(count_free_regs(branch_regs[j].regmap)<=minimum_free_regs[j+1]) break;
10546                 }
10547               }
10548               else if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j]) break;
10549               if(itype[j]==UJUMP||itype[j]==RJUMP||itype[j]==CJUMP||itype[j]==SJUMP||itype[j]==FJUMP) {
10550                 int t=(ba[j]-start)>>2;
10551                 if(t<j&&t>=earliest_available[hr]) {
10552                   if(t==1||(t>1&&itype[t-2]!=UJUMP&&itype[t-2]!=RJUMP)||(t>1&&rt1[t-2]!=31)) { // call/ret assumes no registers allocated
10553                     // Score a point for hoisting loop invariant
10554                     if(t<loop_start[hr]) loop_start[hr]=t;
10555                     //printf("set loop_start: i=%x j=%x (%x)\n",start+i*4,start+j*4,start+t*4);
10556                     score[hr]++;
10557                     end[hr]=j;
10558                   }
10559                 }
10560                 else if(t<j) {
10561                   if(regs[t].regmap[hr]==reg) {
10562                     // Score a point if the branch target matches this register
10563                     score[hr]++;
10564                     end[hr]=j;
10565                   }
10566                 }
10567                 if(itype[j+1]==LOAD||itype[j+1]==LOADLR||
10568                    itype[j+1]==STORE||itype[j+1]==STORELR||itype[j+1]==C1LS) {
10569                   score[hr]++;
10570                   end[hr]=j;
10571                 }
10572               }
10573               if(itype[j]==UJUMP||itype[j]==RJUMP||(source[j]>>16)==0x1000)
10574               {
10575                 // Stop on unconditional branch
10576                 break;
10577               }
10578               else
10579               if(itype[j]==LOAD||itype[j]==LOADLR||
10580                  itype[j]==STORE||itype[j]==STORELR||itype[j]==C1LS) {
10581                 score[hr]++;
10582                 end[hr]=j;
10583               }
10584             }
10585           }
10586         }
10587         // Find highest score and allocate that register
10588         int maxscore=0;
10589         for(hr=0;hr<HOST_REGS;hr++) {
10590           if(hr!=EXCLUDE_REG) {
10591             if(score[hr]>score[maxscore]) {
10592               maxscore=hr;
10593               //printf("highest score: %d %d (%x->%x)\n",score[hr],hr,start+i*4,start+end[hr]*4);
10594             }
10595           }
10596         }
10597         if(score[maxscore]>1)
10598         {
10599           if(i<loop_start[maxscore]) loop_start[maxscore]=i;
10600           for(j=loop_start[maxscore];j<slen&&j<=end[maxscore];j++) {
10601             //if(regs[j].regmap[maxscore]>=0) {printf("oops: %x %x was %d=%d\n",loop_start[maxscore]*4+start,j*4+start,maxscore,regs[j].regmap[maxscore]);}
10602             assert(regs[j].regmap[maxscore]<0);
10603             if(j>loop_start[maxscore]) regs[j].regmap_entry[maxscore]=reg;
10604             regs[j].regmap[maxscore]=reg;
10605             regs[j].dirty&=~(1<<maxscore);
10606             regs[j].wasconst&=~(1<<maxscore);
10607             regs[j].isconst&=~(1<<maxscore);
10608             if(itype[j]==UJUMP||itype[j]==RJUMP||itype[j]==CJUMP||itype[j]==SJUMP||itype[j]==FJUMP) {
10609               branch_regs[j].regmap[maxscore]=reg;
10610               branch_regs[j].wasdirty&=~(1<<maxscore);
10611               branch_regs[j].dirty&=~(1<<maxscore);
10612               branch_regs[j].wasconst&=~(1<<maxscore);
10613               branch_regs[j].isconst&=~(1<<maxscore);
10614               if(itype[j]!=RJUMP&&itype[j]!=UJUMP&&(source[j]>>16)!=0x1000) {
10615                 regmap_pre[j+2][maxscore]=reg;
10616                 regs[j+2].wasdirty&=~(1<<maxscore);
10617               }
10618               // loop optimization (loop_preload)
10619               int t=(ba[j]-start)>>2;
10620               if(t==loop_start[maxscore]) {
10621                 if(t==1||(t>1&&itype[t-2]!=UJUMP&&itype[t-2]!=RJUMP)||(t>1&&rt1[t-2]!=31)) // call/ret assumes no registers allocated
10622                   regs[t].regmap_entry[maxscore]=reg;
10623               }
10624             }
10625             else
10626             {
10627               if(j<1||(itype[j-1]!=RJUMP&&itype[j-1]!=UJUMP&&itype[j-1]!=CJUMP&&itype[j-1]!=SJUMP&&itype[j-1]!=FJUMP)) {
10628                 regmap_pre[j+1][maxscore]=reg;
10629                 regs[j+1].wasdirty&=~(1<<maxscore);
10630               }
10631             }
10632           }
10633           i=j-1;
10634           if(itype[j-1]==RJUMP||itype[j-1]==UJUMP||itype[j-1]==CJUMP||itype[j-1]==SJUMP||itype[j-1]==FJUMP) i++; // skip delay slot
10635           for(hr=0;hr<HOST_REGS;hr++) {
10636             score[hr]=0;earliest_available[hr]=i+i;
10637             loop_start[hr]=MAXBLOCK;
10638           }
10639         }
10640       }
10641     }
10642   }
10643   #endif
10644
10645   // This allocates registers (if possible) one instruction prior
10646   // to use, which can avoid a load-use penalty on certain CPUs.
10647   for(i=0;i<slen-1;i++)
10648   {
10649     if(!i||(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP))
10650     {
10651       if(!bt[i+1])
10652       {
10653         if(itype[i]==ALU||itype[i]==MOV||itype[i]==LOAD||itype[i]==SHIFTIMM||itype[i]==IMM16
10654            ||((itype[i]==COP1||itype[i]==COP2)&&opcode2[i]<3))
10655         {
10656           if(rs1[i+1]) {
10657             if((hr=get_reg(regs[i+1].regmap,rs1[i+1]))>=0)
10658             {
10659               if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10660               {
10661                 regs[i].regmap[hr]=regs[i+1].regmap[hr];
10662                 regmap_pre[i+1][hr]=regs[i+1].regmap[hr];
10663                 regs[i+1].regmap_entry[hr]=regs[i+1].regmap[hr];
10664                 regs[i].isconst&=~(1<<hr);
10665                 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10666                 constmap[i][hr]=constmap[i+1][hr];
10667                 regs[i+1].wasdirty&=~(1<<hr);
10668                 regs[i].dirty&=~(1<<hr);
10669               }
10670             }
10671           }
10672           if(rs2[i+1]) {
10673             if((hr=get_reg(regs[i+1].regmap,rs2[i+1]))>=0)
10674             {
10675               if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10676               {
10677                 regs[i].regmap[hr]=regs[i+1].regmap[hr];
10678                 regmap_pre[i+1][hr]=regs[i+1].regmap[hr];
10679                 regs[i+1].regmap_entry[hr]=regs[i+1].regmap[hr];
10680                 regs[i].isconst&=~(1<<hr);
10681                 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10682                 constmap[i][hr]=constmap[i+1][hr];
10683                 regs[i+1].wasdirty&=~(1<<hr);
10684                 regs[i].dirty&=~(1<<hr);
10685               }
10686             }
10687           }
10688           // Preload target address for load instruction (non-constant)
10689           if(itype[i+1]==LOAD&&rs1[i+1]&&get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10690             if((hr=get_reg(regs[i+1].regmap,rt1[i+1]))>=0)
10691             {
10692               if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10693               {
10694                 regs[i].regmap[hr]=rs1[i+1];
10695                 regmap_pre[i+1][hr]=rs1[i+1];
10696                 regs[i+1].regmap_entry[hr]=rs1[i+1];
10697                 regs[i].isconst&=~(1<<hr);
10698                 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10699                 constmap[i][hr]=constmap[i+1][hr];
10700                 regs[i+1].wasdirty&=~(1<<hr);
10701                 regs[i].dirty&=~(1<<hr);
10702               }
10703             }
10704           }
10705           // Load source into target register
10706           if(lt1[i+1]&&get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10707             if((hr=get_reg(regs[i+1].regmap,rt1[i+1]))>=0)
10708             {
10709               if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10710               {
10711                 regs[i].regmap[hr]=rs1[i+1];
10712                 regmap_pre[i+1][hr]=rs1[i+1];
10713                 regs[i+1].regmap_entry[hr]=rs1[i+1];
10714                 regs[i].isconst&=~(1<<hr);
10715                 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10716                 constmap[i][hr]=constmap[i+1][hr];
10717                 regs[i+1].wasdirty&=~(1<<hr);
10718                 regs[i].dirty&=~(1<<hr);
10719               }
10720             }
10721           }
10722           // Preload map address
10723           #ifndef HOST_IMM_ADDR32
10724           if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS||itype[i+1]==C2LS) {
10725             hr=get_reg(regs[i+1].regmap,TLREG);
10726             if(hr>=0) {
10727               int sr=get_reg(regs[i+1].regmap,rs1[i+1]);
10728               if(sr>=0&&((regs[i+1].wasconst>>sr)&1)) {
10729                 int nr;
10730                 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10731                 {
10732                   regs[i].regmap[hr]=MGEN1+((i+1)&1);
10733                   regmap_pre[i+1][hr]=MGEN1+((i+1)&1);
10734                   regs[i+1].regmap_entry[hr]=MGEN1+((i+1)&1);
10735                   regs[i].isconst&=~(1<<hr);
10736                   regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10737                   constmap[i][hr]=constmap[i+1][hr];
10738                   regs[i+1].wasdirty&=~(1<<hr);
10739                   regs[i].dirty&=~(1<<hr);
10740                 }
10741                 else if((nr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1))>=0)
10742                 {
10743                   // move it to another register
10744                   regs[i+1].regmap[hr]=-1;
10745                   regmap_pre[i+2][hr]=-1;
10746                   regs[i+1].regmap[nr]=TLREG;
10747                   regmap_pre[i+2][nr]=TLREG;
10748                   regs[i].regmap[nr]=MGEN1+((i+1)&1);
10749                   regmap_pre[i+1][nr]=MGEN1+((i+1)&1);
10750                   regs[i+1].regmap_entry[nr]=MGEN1+((i+1)&1);
10751                   regs[i].isconst&=~(1<<nr);
10752                   regs[i+1].isconst&=~(1<<nr);
10753                   regs[i].dirty&=~(1<<nr);
10754                   regs[i+1].wasdirty&=~(1<<nr);
10755                   regs[i+1].dirty&=~(1<<nr);
10756                   regs[i+2].wasdirty&=~(1<<nr);
10757                 }
10758               }
10759             }
10760           }
10761           #endif
10762           // Address for store instruction (non-constant)
10763           if(itype[i+1]==STORE||itype[i+1]==STORELR
10764              ||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a) { // SB/SH/SW/SD/SWC1/SDC1/SWC2/SDC2
10765             if(get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10766               hr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1);
10767               if(hr<0) hr=get_reg(regs[i+1].regmap,-1);
10768               else {regs[i+1].regmap[hr]=AGEN1+((i+1)&1);regs[i+1].isconst&=~(1<<hr);}
10769               assert(hr>=0);
10770               if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10771               {
10772                 regs[i].regmap[hr]=rs1[i+1];
10773                 regmap_pre[i+1][hr]=rs1[i+1];
10774                 regs[i+1].regmap_entry[hr]=rs1[i+1];
10775                 regs[i].isconst&=~(1<<hr);
10776                 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10777                 constmap[i][hr]=constmap[i+1][hr];
10778                 regs[i+1].wasdirty&=~(1<<hr);
10779                 regs[i].dirty&=~(1<<hr);
10780               }
10781             }
10782           }
10783           if(itype[i+1]==LOADLR||(opcode[i+1]&0x3b)==0x31||(opcode[i+1]&0x3b)==0x32) { // LWC1/LDC1, LWC2/LDC2
10784             if(get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10785               int nr;
10786               hr=get_reg(regs[i+1].regmap,FTEMP);
10787               assert(hr>=0);
10788               if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10789               {
10790                 regs[i].regmap[hr]=rs1[i+1];
10791                 regmap_pre[i+1][hr]=rs1[i+1];
10792                 regs[i+1].regmap_entry[hr]=rs1[i+1];
10793                 regs[i].isconst&=~(1<<hr);
10794                 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10795                 constmap[i][hr]=constmap[i+1][hr];
10796                 regs[i+1].wasdirty&=~(1<<hr);
10797                 regs[i].dirty&=~(1<<hr);
10798               }
10799               else if((nr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1))>=0)
10800               {
10801                 // move it to another register
10802                 regs[i+1].regmap[hr]=-1;
10803                 regmap_pre[i+2][hr]=-1;
10804                 regs[i+1].regmap[nr]=FTEMP;
10805                 regmap_pre[i+2][nr]=FTEMP;
10806                 regs[i].regmap[nr]=rs1[i+1];
10807                 regmap_pre[i+1][nr]=rs1[i+1];
10808                 regs[i+1].regmap_entry[nr]=rs1[i+1];
10809                 regs[i].isconst&=~(1<<nr);
10810                 regs[i+1].isconst&=~(1<<nr);
10811                 regs[i].dirty&=~(1<<nr);
10812                 regs[i+1].wasdirty&=~(1<<nr);
10813                 regs[i+1].dirty&=~(1<<nr);
10814                 regs[i+2].wasdirty&=~(1<<nr);
10815               }
10816             }
10817           }
10818           if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR/*||itype[i+1]==C1LS||||itype[i+1]==C2LS*/) {
10819             if(itype[i+1]==LOAD)
10820               hr=get_reg(regs[i+1].regmap,rt1[i+1]);
10821             if(itype[i+1]==LOADLR||(opcode[i+1]&0x3b)==0x31||(opcode[i+1]&0x3b)==0x32) // LWC1/LDC1, LWC2/LDC2
10822               hr=get_reg(regs[i+1].regmap,FTEMP);
10823             if(itype[i+1]==STORE||itype[i+1]==STORELR||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a) { // SWC1/SDC1/SWC2/SDC2
10824               hr=get_reg(regs[i+1].regmap,AGEN1+((i+1)&1));
10825               if(hr<0) hr=get_reg(regs[i+1].regmap,-1);
10826             }
10827             if(hr>=0&&regs[i].regmap[hr]<0) {
10828               int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
10829               if(rs>=0&&((regs[i+1].wasconst>>rs)&1)) {
10830                 regs[i].regmap[hr]=AGEN1+((i+1)&1);
10831                 regmap_pre[i+1][hr]=AGEN1+((i+1)&1);
10832                 regs[i+1].regmap_entry[hr]=AGEN1+((i+1)&1);
10833                 regs[i].isconst&=~(1<<hr);
10834                 regs[i+1].wasdirty&=~(1<<hr);
10835                 regs[i].dirty&=~(1<<hr);
10836               }
10837             }
10838           }
10839         }
10840       }
10841     }
10842   }
10843
10844   /* Pass 6 - Optimize clean/dirty state */
10845   clean_registers(0,slen-1,1);
10846
10847   /* Pass 7 - Identify 32-bit registers */
10848 #ifndef FORCE32
10849   provisional_r32();
10850
10851   u_int r32=0;
10852
10853   for (i=slen-1;i>=0;i--)
10854   {
10855     int hr;
10856     if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
10857     {
10858       if(ba[i]<start || ba[i]>=(start+slen*4))
10859       {
10860         // Branch out of this block, don't need anything
10861         r32=0;
10862       }
10863       else
10864       {
10865         // Internal branch
10866         // Need whatever matches the target
10867         // (and doesn't get overwritten by the delay slot instruction)
10868         r32=0;
10869         int t=(ba[i]-start)>>2;
10870         if(ba[i]>start+i*4) {
10871           // Forward branch
10872           if(!(requires_32bit[t]&~regs[i].was32))
10873             r32|=requires_32bit[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
10874         }else{
10875           // Backward branch
10876           //if(!(regs[t].was32&~unneeded_reg_upper[t]&~regs[i].was32))
10877           //  r32|=regs[t].was32&~unneeded_reg_upper[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
10878           if(!(pr32[t]&~regs[i].was32))
10879             r32|=pr32[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
10880         }
10881       }
10882       // Conditional branch may need registers for following instructions
10883       if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
10884       {
10885         if(i<slen-2) {
10886           r32|=requires_32bit[i+2];
10887           r32&=regs[i].was32;
10888           // Mark this address as a branch target since it may be called
10889           // upon return from interrupt
10890           bt[i+2]=1;
10891         }
10892       }
10893       // Merge in delay slot
10894       if(!likely[i]) {
10895         // These are overwritten unless the branch is "likely"
10896         // and the delay slot is nullified if not taken
10897         r32&=~(1LL<<rt1[i+1]);
10898         r32&=~(1LL<<rt2[i+1]);
10899       }
10900       // Assume these are needed (delay slot)
10901       if(us1[i+1]>0)
10902       {
10903         if((regs[i].was32>>us1[i+1])&1) r32|=1LL<<us1[i+1];
10904       }
10905       if(us2[i+1]>0)
10906       {
10907         if((regs[i].was32>>us2[i+1])&1) r32|=1LL<<us2[i+1];
10908       }
10909       if(dep1[i+1]&&!((unneeded_reg_upper[i]>>dep1[i+1])&1))
10910       {
10911         if((regs[i].was32>>dep1[i+1])&1) r32|=1LL<<dep1[i+1];
10912       }
10913       if(dep2[i+1]&&!((unneeded_reg_upper[i]>>dep2[i+1])&1))
10914       {
10915         if((regs[i].was32>>dep2[i+1])&1) r32|=1LL<<dep2[i+1];
10916       }
10917     }
10918     else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
10919     {
10920       // SYSCALL instruction (software interrupt)
10921       r32=0;
10922     }
10923     else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
10924     {
10925       // ERET instruction (return from interrupt)
10926       r32=0;
10927     }
10928     // Check 32 bits
10929     r32&=~(1LL<<rt1[i]);
10930     r32&=~(1LL<<rt2[i]);
10931     if(us1[i]>0)
10932     {
10933       if((regs[i].was32>>us1[i])&1) r32|=1LL<<us1[i];
10934     }
10935     if(us2[i]>0)
10936     {
10937       if((regs[i].was32>>us2[i])&1) r32|=1LL<<us2[i];
10938     }
10939     if(dep1[i]&&!((unneeded_reg_upper[i]>>dep1[i])&1))
10940     {
10941       if((regs[i].was32>>dep1[i])&1) r32|=1LL<<dep1[i];
10942     }
10943     if(dep2[i]&&!((unneeded_reg_upper[i]>>dep2[i])&1))
10944     {
10945       if((regs[i].was32>>dep2[i])&1) r32|=1LL<<dep2[i];
10946     }
10947     requires_32bit[i]=r32;
10948
10949     // Dirty registers which are 32-bit, require 32-bit input
10950     // as they will be written as 32-bit values
10951     for(hr=0;hr<HOST_REGS;hr++)
10952     {
10953       if(regs[i].regmap_entry[hr]>0&&regs[i].regmap_entry[hr]<64) {
10954         if((regs[i].was32>>regs[i].regmap_entry[hr])&(regs[i].wasdirty>>hr)&1) {
10955           if(!((unneeded_reg_upper[i]>>regs[i].regmap_entry[hr])&1))
10956           requires_32bit[i]|=1LL<<regs[i].regmap_entry[hr];
10957         }
10958       }
10959     }
10960     //requires_32bit[i]=is32[i]&~unneeded_reg_upper[i]; // DEBUG
10961   }
10962 #else
10963   for (i=slen-1;i>=0;i--)
10964   {
10965     if(itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
10966     {
10967       // Conditional branch
10968       if((source[i]>>16)!=0x1000&&i<slen-2) {
10969         // Mark this address as a branch target since it may be called
10970         // upon return from interrupt
10971         bt[i+2]=1;
10972       }
10973     }
10974   }
10975 #endif
10976
10977   if(itype[slen-1]==SPAN) {
10978     bt[slen-1]=1; // Mark as a branch target so instruction can restart after exception
10979   }
10980
10981 #ifdef DISASM
10982   /* Debug/disassembly */
10983   for(i=0;i<slen;i++)
10984   {
10985     printf("U:");
10986     int r;
10987     for(r=1;r<=CCREG;r++) {
10988       if((unneeded_reg[i]>>r)&1) {
10989         if(r==HIREG) printf(" HI");
10990         else if(r==LOREG) printf(" LO");
10991         else printf(" r%d",r);
10992       }
10993     }
10994 #ifndef FORCE32
10995     printf(" UU:");
10996     for(r=1;r<=CCREG;r++) {
10997       if(((unneeded_reg_upper[i]&~unneeded_reg[i])>>r)&1) {
10998         if(r==HIREG) printf(" HI");
10999         else if(r==LOREG) printf(" LO");
11000         else printf(" r%d",r);
11001       }
11002     }
11003     printf(" 32:");
11004     for(r=0;r<=CCREG;r++) {
11005       //if(((is32[i]>>r)&(~unneeded_reg[i]>>r))&1) {
11006       if((regs[i].was32>>r)&1) {
11007         if(r==CCREG) printf(" CC");
11008         else if(r==HIREG) printf(" HI");
11009         else if(r==LOREG) printf(" LO");
11010         else printf(" r%d",r);
11011       }
11012     }
11013 #endif
11014     printf("\n");
11015     #if defined(__i386__) || defined(__x86_64__)
11016     printf("pre: eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",regmap_pre[i][0],regmap_pre[i][1],regmap_pre[i][2],regmap_pre[i][3],regmap_pre[i][5],regmap_pre[i][6],regmap_pre[i][7]);
11017     #endif
11018     #ifdef __arm__
11019     printf("pre: r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d\n",regmap_pre[i][0],regmap_pre[i][1],regmap_pre[i][2],regmap_pre[i][3],regmap_pre[i][4],regmap_pre[i][5],regmap_pre[i][6],regmap_pre[i][7],regmap_pre[i][8],regmap_pre[i][9],regmap_pre[i][10],regmap_pre[i][12]);
11020     #endif
11021     printf("needs: ");
11022     if(needed_reg[i]&1) printf("eax ");
11023     if((needed_reg[i]>>1)&1) printf("ecx ");
11024     if((needed_reg[i]>>2)&1) printf("edx ");
11025     if((needed_reg[i]>>3)&1) printf("ebx ");
11026     if((needed_reg[i]>>5)&1) printf("ebp ");
11027     if((needed_reg[i]>>6)&1) printf("esi ");
11028     if((needed_reg[i]>>7)&1) printf("edi ");
11029     printf("r:");
11030     for(r=0;r<=CCREG;r++) {
11031       //if(((requires_32bit[i]>>r)&(~unneeded_reg[i]>>r))&1) {
11032       if((requires_32bit[i]>>r)&1) {
11033         if(r==CCREG) printf(" CC");
11034         else if(r==HIREG) printf(" HI");
11035         else if(r==LOREG) printf(" LO");
11036         else printf(" r%d",r);
11037       }
11038     }
11039     printf("\n");
11040     /*printf("pr:");
11041     for(r=0;r<=CCREG;r++) {
11042       //if(((requires_32bit[i]>>r)&(~unneeded_reg[i]>>r))&1) {
11043       if((pr32[i]>>r)&1) {
11044         if(r==CCREG) printf(" CC");
11045         else if(r==HIREG) printf(" HI");
11046         else if(r==LOREG) printf(" LO");
11047         else printf(" r%d",r);
11048       }
11049     }
11050     if(pr32[i]!=requires_32bit[i]) printf(" OOPS");
11051     printf("\n");*/
11052     #if defined(__i386__) || defined(__x86_64__)
11053     printf("entry: eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",regs[i].regmap_entry[0],regs[i].regmap_entry[1],regs[i].regmap_entry[2],regs[i].regmap_entry[3],regs[i].regmap_entry[5],regs[i].regmap_entry[6],regs[i].regmap_entry[7]);
11054     printf("dirty: ");
11055     if(regs[i].wasdirty&1) printf("eax ");
11056     if((regs[i].wasdirty>>1)&1) printf("ecx ");
11057     if((regs[i].wasdirty>>2)&1) printf("edx ");
11058     if((regs[i].wasdirty>>3)&1) printf("ebx ");
11059     if((regs[i].wasdirty>>5)&1) printf("ebp ");
11060     if((regs[i].wasdirty>>6)&1) printf("esi ");
11061     if((regs[i].wasdirty>>7)&1) printf("edi ");
11062     #endif
11063     #ifdef __arm__
11064     printf("entry: r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d\n",regs[i].regmap_entry[0],regs[i].regmap_entry[1],regs[i].regmap_entry[2],regs[i].regmap_entry[3],regs[i].regmap_entry[4],regs[i].regmap_entry[5],regs[i].regmap_entry[6],regs[i].regmap_entry[7],regs[i].regmap_entry[8],regs[i].regmap_entry[9],regs[i].regmap_entry[10],regs[i].regmap_entry[12]);
11065     printf("dirty: ");
11066     if(regs[i].wasdirty&1) printf("r0 ");
11067     if((regs[i].wasdirty>>1)&1) printf("r1 ");
11068     if((regs[i].wasdirty>>2)&1) printf("r2 ");
11069     if((regs[i].wasdirty>>3)&1) printf("r3 ");
11070     if((regs[i].wasdirty>>4)&1) printf("r4 ");
11071     if((regs[i].wasdirty>>5)&1) printf("r5 ");
11072     if((regs[i].wasdirty>>6)&1) printf("r6 ");
11073     if((regs[i].wasdirty>>7)&1) printf("r7 ");
11074     if((regs[i].wasdirty>>8)&1) printf("r8 ");
11075     if((regs[i].wasdirty>>9)&1) printf("r9 ");
11076     if((regs[i].wasdirty>>10)&1) printf("r10 ");
11077     if((regs[i].wasdirty>>12)&1) printf("r12 ");
11078     #endif
11079     printf("\n");
11080     disassemble_inst(i);
11081     //printf ("ccadj[%d] = %d\n",i,ccadj[i]);
11082     #if defined(__i386__) || defined(__x86_64__)
11083     printf("eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d dirty: ",regs[i].regmap[0],regs[i].regmap[1],regs[i].regmap[2],regs[i].regmap[3],regs[i].regmap[5],regs[i].regmap[6],regs[i].regmap[7]);
11084     if(regs[i].dirty&1) printf("eax ");
11085     if((regs[i].dirty>>1)&1) printf("ecx ");
11086     if((regs[i].dirty>>2)&1) printf("edx ");
11087     if((regs[i].dirty>>3)&1) printf("ebx ");
11088     if((regs[i].dirty>>5)&1) printf("ebp ");
11089     if((regs[i].dirty>>6)&1) printf("esi ");
11090     if((regs[i].dirty>>7)&1) printf("edi ");
11091     #endif
11092     #ifdef __arm__
11093     printf("r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d dirty: ",regs[i].regmap[0],regs[i].regmap[1],regs[i].regmap[2],regs[i].regmap[3],regs[i].regmap[4],regs[i].regmap[5],regs[i].regmap[6],regs[i].regmap[7],regs[i].regmap[8],regs[i].regmap[9],regs[i].regmap[10],regs[i].regmap[12]);
11094     if(regs[i].dirty&1) printf("r0 ");
11095     if((regs[i].dirty>>1)&1) printf("r1 ");
11096     if((regs[i].dirty>>2)&1) printf("r2 ");
11097     if((regs[i].dirty>>3)&1) printf("r3 ");
11098     if((regs[i].dirty>>4)&1) printf("r4 ");
11099     if((regs[i].dirty>>5)&1) printf("r5 ");
11100     if((regs[i].dirty>>6)&1) printf("r6 ");
11101     if((regs[i].dirty>>7)&1) printf("r7 ");
11102     if((regs[i].dirty>>8)&1) printf("r8 ");
11103     if((regs[i].dirty>>9)&1) printf("r9 ");
11104     if((regs[i].dirty>>10)&1) printf("r10 ");
11105     if((regs[i].dirty>>12)&1) printf("r12 ");
11106     #endif
11107     printf("\n");
11108     if(regs[i].isconst) {
11109       printf("constants: ");
11110       #if defined(__i386__) || defined(__x86_64__)
11111       if(regs[i].isconst&1) printf("eax=%x ",(int)constmap[i][0]);
11112       if((regs[i].isconst>>1)&1) printf("ecx=%x ",(int)constmap[i][1]);
11113       if((regs[i].isconst>>2)&1) printf("edx=%x ",(int)constmap[i][2]);
11114       if((regs[i].isconst>>3)&1) printf("ebx=%x ",(int)constmap[i][3]);
11115       if((regs[i].isconst>>5)&1) printf("ebp=%x ",(int)constmap[i][5]);
11116       if((regs[i].isconst>>6)&1) printf("esi=%x ",(int)constmap[i][6]);
11117       if((regs[i].isconst>>7)&1) printf("edi=%x ",(int)constmap[i][7]);
11118       #endif
11119       #ifdef __arm__
11120       if(regs[i].isconst&1) printf("r0=%x ",(int)constmap[i][0]);
11121       if((regs[i].isconst>>1)&1) printf("r1=%x ",(int)constmap[i][1]);
11122       if((regs[i].isconst>>2)&1) printf("r2=%x ",(int)constmap[i][2]);
11123       if((regs[i].isconst>>3)&1) printf("r3=%x ",(int)constmap[i][3]);
11124       if((regs[i].isconst>>4)&1) printf("r4=%x ",(int)constmap[i][4]);
11125       if((regs[i].isconst>>5)&1) printf("r5=%x ",(int)constmap[i][5]);
11126       if((regs[i].isconst>>6)&1) printf("r6=%x ",(int)constmap[i][6]);
11127       if((regs[i].isconst>>7)&1) printf("r7=%x ",(int)constmap[i][7]);
11128       if((regs[i].isconst>>8)&1) printf("r8=%x ",(int)constmap[i][8]);
11129       if((regs[i].isconst>>9)&1) printf("r9=%x ",(int)constmap[i][9]);
11130       if((regs[i].isconst>>10)&1) printf("r10=%x ",(int)constmap[i][10]);
11131       if((regs[i].isconst>>12)&1) printf("r12=%x ",(int)constmap[i][12]);
11132       #endif
11133       printf("\n");
11134     }
11135 #ifndef FORCE32
11136     printf(" 32:");
11137     for(r=0;r<=CCREG;r++) {
11138       if((regs[i].is32>>r)&1) {
11139         if(r==CCREG) printf(" CC");
11140         else if(r==HIREG) printf(" HI");
11141         else if(r==LOREG) printf(" LO");
11142         else printf(" r%d",r);
11143       }
11144     }
11145     printf("\n");
11146 #endif
11147     /*printf(" p32:");
11148     for(r=0;r<=CCREG;r++) {
11149       if((p32[i]>>r)&1) {
11150         if(r==CCREG) printf(" CC");
11151         else if(r==HIREG) printf(" HI");
11152         else if(r==LOREG) printf(" LO");
11153         else printf(" r%d",r);
11154       }
11155     }
11156     if(p32[i]!=regs[i].is32) printf(" NO MATCH\n");
11157     else printf("\n");*/
11158     if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP) {
11159       #if defined(__i386__) || defined(__x86_64__)
11160       printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d dirty: ",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
11161       if(branch_regs[i].dirty&1) printf("eax ");
11162       if((branch_regs[i].dirty>>1)&1) printf("ecx ");
11163       if((branch_regs[i].dirty>>2)&1) printf("edx ");
11164       if((branch_regs[i].dirty>>3)&1) printf("ebx ");
11165       if((branch_regs[i].dirty>>5)&1) printf("ebp ");
11166       if((branch_regs[i].dirty>>6)&1) printf("esi ");
11167       if((branch_regs[i].dirty>>7)&1) printf("edi ");
11168       #endif
11169       #ifdef __arm__
11170       printf("branch(%d): r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d dirty: ",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[4],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7],branch_regs[i].regmap[8],branch_regs[i].regmap[9],branch_regs[i].regmap[10],branch_regs[i].regmap[12]);
11171       if(branch_regs[i].dirty&1) printf("r0 ");
11172       if((branch_regs[i].dirty>>1)&1) printf("r1 ");
11173       if((branch_regs[i].dirty>>2)&1) printf("r2 ");
11174       if((branch_regs[i].dirty>>3)&1) printf("r3 ");
11175       if((branch_regs[i].dirty>>4)&1) printf("r4 ");
11176       if((branch_regs[i].dirty>>5)&1) printf("r5 ");
11177       if((branch_regs[i].dirty>>6)&1) printf("r6 ");
11178       if((branch_regs[i].dirty>>7)&1) printf("r7 ");
11179       if((branch_regs[i].dirty>>8)&1) printf("r8 ");
11180       if((branch_regs[i].dirty>>9)&1) printf("r9 ");
11181       if((branch_regs[i].dirty>>10)&1) printf("r10 ");
11182       if((branch_regs[i].dirty>>12)&1) printf("r12 ");
11183       #endif
11184 #ifndef FORCE32
11185       printf(" 32:");
11186       for(r=0;r<=CCREG;r++) {
11187         if((branch_regs[i].is32>>r)&1) {
11188           if(r==CCREG) printf(" CC");
11189           else if(r==HIREG) printf(" HI");
11190           else if(r==LOREG) printf(" LO");
11191           else printf(" r%d",r);
11192         }
11193       }
11194       printf("\n");
11195 #endif
11196     }
11197   }
11198 #endif // DISASM
11199
11200   /* Pass 8 - Assembly */
11201   linkcount=0;stubcount=0;
11202   ds=0;is_delayslot=0;
11203   cop1_usable=0;
11204   uint64_t is32_pre=0;
11205   u_int dirty_pre=0;
11206   u_int beginning=(u_int)out;
11207   if((u_int)addr&1) {
11208     ds=1;
11209     pagespan_ds();
11210   }
11211   u_int instr_addr0_override=0;
11212
11213 #ifdef PCSX
11214   if (start == 0x80030000) {
11215     // nasty hack for fastbios thing
11216     // override block entry to this code
11217     instr_addr0_override=(u_int)out;
11218     emit_movimm(start,0);
11219     // abuse io address var as a flag that we
11220     // have already returned here once
11221     emit_readword((int)&address,1);
11222     emit_writeword(0,(int)&pcaddr);
11223     emit_writeword(0,(int)&address);
11224     emit_cmp(0,1);
11225     emit_jne((int)new_dyna_leave);
11226   }
11227 #endif
11228   for(i=0;i<slen;i++)
11229   {
11230     //if(ds) printf("ds: ");
11231     disassemble_inst(i);
11232     if(ds) {
11233       ds=0; // Skip delay slot
11234       if(bt[i]) assem_debug("OOPS - branch into delay slot\n");
11235       instr_addr[i]=0;
11236     } else {
11237       speculate_register_values(i);
11238       #ifndef DESTRUCTIVE_WRITEBACK
11239       if(i<2||(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000))
11240       {
11241         wb_sx(regmap_pre[i],regs[i].regmap_entry,regs[i].wasdirty,is32_pre,regs[i].was32,
11242               unneeded_reg[i],unneeded_reg_upper[i]);
11243         wb_valid(regmap_pre[i],regs[i].regmap_entry,dirty_pre,regs[i].wasdirty,is32_pre,
11244               unneeded_reg[i],unneeded_reg_upper[i]);
11245       }
11246       if((itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)&&!likely[i]) {
11247         is32_pre=branch_regs[i].is32;
11248         dirty_pre=branch_regs[i].dirty;
11249       }else{
11250         is32_pre=regs[i].is32;
11251         dirty_pre=regs[i].dirty;
11252       }
11253       #endif
11254       // write back
11255       if(i<2||(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000))
11256       {
11257         wb_invalidate(regmap_pre[i],regs[i].regmap_entry,regs[i].wasdirty,regs[i].was32,
11258                       unneeded_reg[i],unneeded_reg_upper[i]);
11259         loop_preload(regmap_pre[i],regs[i].regmap_entry);
11260       }
11261       // branch target entry point
11262       instr_addr[i]=(u_int)out;
11263       assem_debug("<->\n");
11264       // load regs
11265       if(regs[i].regmap_entry[HOST_CCREG]==CCREG&&regs[i].regmap[HOST_CCREG]!=CCREG)
11266         wb_register(CCREG,regs[i].regmap_entry,regs[i].wasdirty,regs[i].was32);
11267       load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs1[i],rs2[i]);
11268       address_generation(i,&regs[i],regs[i].regmap_entry);
11269       load_consts(regmap_pre[i],regs[i].regmap,regs[i].was32,i);
11270       if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
11271       {
11272         // Load the delay slot registers if necessary
11273         if(rs1[i+1]!=rs1[i]&&rs1[i+1]!=rs2[i]&&(rs1[i+1]!=rt1[i]||rt1[i]==0))
11274           load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs1[i+1],rs1[i+1]);
11275         if(rs2[i+1]!=rs1[i+1]&&rs2[i+1]!=rs1[i]&&rs2[i+1]!=rs2[i]&&(rs2[i+1]!=rt1[i]||rt1[i]==0))
11276           load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs2[i+1],rs2[i+1]);
11277         if(itype[i+1]==STORE||itype[i+1]==STORELR||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a)
11278           load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,INVCP,INVCP);
11279       }
11280       else if(i+1<slen)
11281       {
11282         // Preload registers for following instruction
11283         if(rs1[i+1]!=rs1[i]&&rs1[i+1]!=rs2[i])
11284           if(rs1[i+1]!=rt1[i]&&rs1[i+1]!=rt2[i])
11285             load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs1[i+1],rs1[i+1]);
11286         if(rs2[i+1]!=rs1[i+1]&&rs2[i+1]!=rs1[i]&&rs2[i+1]!=rs2[i])
11287           if(rs2[i+1]!=rt1[i]&&rs2[i+1]!=rt2[i])
11288             load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs2[i+1],rs2[i+1]);
11289       }
11290       // TODO: if(is_ooo(i)) address_generation(i+1);
11291       if(itype[i]==CJUMP||itype[i]==FJUMP)
11292         load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,CCREG,CCREG);
11293       if(itype[i]==STORE||itype[i]==STORELR||(opcode[i]&0x3b)==0x39||(opcode[i]&0x3b)==0x3a)
11294         load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,INVCP,INVCP);
11295       if(bt[i]) cop1_usable=0;
11296       // assemble
11297       switch(itype[i]) {
11298         case ALU:
11299           alu_assemble(i,&regs[i]);break;
11300         case IMM16:
11301           imm16_assemble(i,&regs[i]);break;
11302         case SHIFT:
11303           shift_assemble(i,&regs[i]);break;
11304         case SHIFTIMM:
11305           shiftimm_assemble(i,&regs[i]);break;
11306         case LOAD:
11307           load_assemble(i,&regs[i]);break;
11308         case LOADLR:
11309           loadlr_assemble(i,&regs[i]);break;
11310         case STORE:
11311           store_assemble(i,&regs[i]);break;
11312         case STORELR:
11313           storelr_assemble(i,&regs[i]);break;
11314         case COP0:
11315           cop0_assemble(i,&regs[i]);break;
11316         case COP1:
11317           cop1_assemble(i,&regs[i]);break;
11318         case C1LS:
11319           c1ls_assemble(i,&regs[i]);break;
11320         case COP2:
11321           cop2_assemble(i,&regs[i]);break;
11322         case C2LS:
11323           c2ls_assemble(i,&regs[i]);break;
11324         case C2OP:
11325           c2op_assemble(i,&regs[i]);break;
11326         case FCONV:
11327           fconv_assemble(i,&regs[i]);break;
11328         case FLOAT:
11329           float_assemble(i,&regs[i]);break;
11330         case FCOMP:
11331           fcomp_assemble(i,&regs[i]);break;
11332         case MULTDIV:
11333           multdiv_assemble(i,&regs[i]);break;
11334         case MOV:
11335           mov_assemble(i,&regs[i]);break;
11336         case SYSCALL:
11337           syscall_assemble(i,&regs[i]);break;
11338         case HLECALL:
11339           hlecall_assemble(i,&regs[i]);break;
11340         case INTCALL:
11341           intcall_assemble(i,&regs[i]);break;
11342         case UJUMP:
11343           ujump_assemble(i,&regs[i]);ds=1;break;
11344         case RJUMP:
11345           rjump_assemble(i,&regs[i]);ds=1;break;
11346         case CJUMP:
11347           cjump_assemble(i,&regs[i]);ds=1;break;
11348         case SJUMP:
11349           sjump_assemble(i,&regs[i]);ds=1;break;
11350         case FJUMP:
11351           fjump_assemble(i,&regs[i]);ds=1;break;
11352         case SPAN:
11353           pagespan_assemble(i,&regs[i]);break;
11354       }
11355       if(itype[i]==UJUMP||itype[i]==RJUMP||(source[i]>>16)==0x1000)
11356         literal_pool(1024);
11357       else
11358         literal_pool_jumpover(256);
11359     }
11360   }
11361   //assert(itype[i-2]==UJUMP||itype[i-2]==RJUMP||(source[i-2]>>16)==0x1000);
11362   // If the block did not end with an unconditional branch,
11363   // add a jump to the next instruction.
11364   if(i>1) {
11365     if(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000&&itype[i-1]!=SPAN) {
11366       assert(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP);
11367       assert(i==slen);
11368       if(itype[i-2]!=CJUMP&&itype[i-2]!=SJUMP&&itype[i-2]!=FJUMP) {
11369         store_regs_bt(regs[i-1].regmap,regs[i-1].is32,regs[i-1].dirty,start+i*4);
11370         if(regs[i-1].regmap[HOST_CCREG]!=CCREG)
11371           emit_loadreg(CCREG,HOST_CCREG);
11372         emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i-1]+1),HOST_CCREG);
11373       }
11374       else if(!likely[i-2])
11375       {
11376         store_regs_bt(branch_regs[i-2].regmap,branch_regs[i-2].is32,branch_regs[i-2].dirty,start+i*4);
11377         assert(branch_regs[i-2].regmap[HOST_CCREG]==CCREG);
11378       }
11379       else
11380       {
11381         store_regs_bt(regs[i-2].regmap,regs[i-2].is32,regs[i-2].dirty,start+i*4);
11382         assert(regs[i-2].regmap[HOST_CCREG]==CCREG);
11383       }
11384       add_to_linker((int)out,start+i*4,0);
11385       emit_jmp(0);
11386     }
11387   }
11388   else
11389   {
11390     assert(i>0);
11391     assert(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP);
11392     store_regs_bt(regs[i-1].regmap,regs[i-1].is32,regs[i-1].dirty,start+i*4);
11393     if(regs[i-1].regmap[HOST_CCREG]!=CCREG)
11394       emit_loadreg(CCREG,HOST_CCREG);
11395     emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i-1]+1),HOST_CCREG);
11396     add_to_linker((int)out,start+i*4,0);
11397     emit_jmp(0);
11398   }
11399
11400   // TODO: delay slot stubs?
11401   // Stubs
11402   for(i=0;i<stubcount;i++)
11403   {
11404     switch(stubs[i][0])
11405     {
11406       case LOADB_STUB:
11407       case LOADH_STUB:
11408       case LOADW_STUB:
11409       case LOADD_STUB:
11410       case LOADBU_STUB:
11411       case LOADHU_STUB:
11412         do_readstub(i);break;
11413       case STOREB_STUB:
11414       case STOREH_STUB:
11415       case STOREW_STUB:
11416       case STORED_STUB:
11417         do_writestub(i);break;
11418       case CC_STUB:
11419         do_ccstub(i);break;
11420       case INVCODE_STUB:
11421         do_invstub(i);break;
11422       case FP_STUB:
11423         do_cop1stub(i);break;
11424       case STORELR_STUB:
11425         do_unalignedwritestub(i);break;
11426     }
11427   }
11428
11429   if (instr_addr0_override)
11430     instr_addr[0] = instr_addr0_override;
11431
11432   /* Pass 9 - Linker */
11433   for(i=0;i<linkcount;i++)
11434   {
11435     assem_debug("%8x -> %8x\n",link_addr[i][0],link_addr[i][1]);
11436     literal_pool(64);
11437     if(!link_addr[i][2])
11438     {
11439       void *stub=out;
11440       void *addr=check_addr(link_addr[i][1]);
11441       emit_extjump(link_addr[i][0],link_addr[i][1]);
11442       if(addr) {
11443         set_jump_target(link_addr[i][0],(int)addr);
11444         add_link(link_addr[i][1],stub);
11445       }
11446       else set_jump_target(link_addr[i][0],(int)stub);
11447     }
11448     else
11449     {
11450       // Internal branch
11451       int target=(link_addr[i][1]-start)>>2;
11452       assert(target>=0&&target<slen);
11453       assert(instr_addr[target]);
11454       //#ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
11455       //set_jump_target_fillslot(link_addr[i][0],instr_addr[target],link_addr[i][2]>>1);
11456       //#else
11457       set_jump_target(link_addr[i][0],instr_addr[target]);
11458       //#endif
11459     }
11460   }
11461   // External Branch Targets (jump_in)
11462   if(copy+slen*4>(void *)shadow+sizeof(shadow)) copy=shadow;
11463   for(i=0;i<slen;i++)
11464   {
11465     if(bt[i]||i==0)
11466     {
11467       if(instr_addr[i]) // TODO - delay slots (=null)
11468       {
11469         u_int vaddr=start+i*4;
11470         u_int page=get_page(vaddr);
11471         u_int vpage=get_vpage(vaddr);
11472         literal_pool(256);
11473         //if(!(is32[i]&(~unneeded_reg_upper[i])&~(1LL<<CCREG)))
11474 #ifndef FORCE32
11475         if(!requires_32bit[i])
11476 #else
11477         if(1)
11478 #endif
11479         {
11480           assem_debug("%8x (%d) <- %8x\n",instr_addr[i],i,start+i*4);
11481           assem_debug("jump_in: %x\n",start+i*4);
11482           ll_add(jump_dirty+vpage,vaddr,(void *)out);
11483           int entry_point=do_dirty_stub(i);
11484           ll_add(jump_in+page,vaddr,(void *)entry_point);
11485           // If there was an existing entry in the hash table,
11486           // replace it with the new address.
11487           // Don't add new entries.  We'll insert the
11488           // ones that actually get used in check_addr().
11489           int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
11490           if(ht_bin[0]==vaddr) {
11491             ht_bin[1]=entry_point;
11492           }
11493           if(ht_bin[2]==vaddr) {
11494             ht_bin[3]=entry_point;
11495           }
11496         }
11497         else
11498         {
11499           u_int r=requires_32bit[i]|!!(requires_32bit[i]>>32);
11500           assem_debug("%8x (%d) <- %8x\n",instr_addr[i],i,start+i*4);
11501           assem_debug("jump_in: %x (restricted - %x)\n",start+i*4,r);
11502           //int entry_point=(int)out;
11503           ////assem_debug("entry_point: %x\n",entry_point);
11504           //load_regs_entry(i);
11505           //if(entry_point==(int)out)
11506           //  entry_point=instr_addr[i];
11507           //else
11508           //  emit_jmp(instr_addr[i]);
11509           //ll_add_32(jump_in+page,vaddr,r,(void *)entry_point);
11510           ll_add_32(jump_dirty+vpage,vaddr,r,(void *)out);
11511           int entry_point=do_dirty_stub(i);
11512           ll_add_32(jump_in+page,vaddr,r,(void *)entry_point);
11513         }
11514       }
11515     }
11516   }
11517   // Write out the literal pool if necessary
11518   literal_pool(0);
11519   #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
11520   // Align code
11521   if(((u_int)out)&7) emit_addnop(13);
11522   #endif
11523   assert((u_int)out-beginning<MAX_OUTPUT_BLOCK_SIZE);
11524   //printf("shadow buffer: %x-%x\n",(int)copy,(int)copy+slen*4);
11525   memcpy(copy,source,slen*4);
11526   copy+=slen*4;
11527
11528   #ifdef __arm__
11529   __clear_cache((void *)beginning,out);
11530   #endif
11531
11532   // If we're within 256K of the end of the buffer,
11533   // start over from the beginning. (Is 256K enough?)
11534   if((int)out>BASE_ADDR+(1<<TARGET_SIZE_2)-MAX_OUTPUT_BLOCK_SIZE) out=(u_char *)BASE_ADDR;
11535
11536   // Trap writes to any of the pages we compiled
11537   for(i=start>>12;i<=(start+slen*4)>>12;i++) {
11538     invalid_code[i]=0;
11539 #ifndef DISABLE_TLB
11540     memory_map[i]|=0x40000000;
11541     if((signed int)start>=(signed int)0xC0000000) {
11542       assert(using_tlb);
11543       j=(((u_int)i<<12)+(memory_map[i]<<2)-(u_int)rdram+(u_int)0x80000000)>>12;
11544       invalid_code[j]=0;
11545       memory_map[j]|=0x40000000;
11546       //printf("write protect physical page: %x (virtual %x)\n",j<<12,start);
11547     }
11548 #endif
11549   }
11550   inv_code_start=inv_code_end=~0;
11551 #ifdef PCSX
11552   // for PCSX we need to mark all mirrors too
11553   if(get_page(start)<(RAM_SIZE>>12))
11554     for(i=start>>12;i<=(start+slen*4)>>12;i++)
11555       invalid_code[((u_int)0x00000000>>12)|(i&0x1ff)]=
11556       invalid_code[((u_int)0x80000000>>12)|(i&0x1ff)]=
11557       invalid_code[((u_int)0xa0000000>>12)|(i&0x1ff)]=0;
11558 #endif
11559
11560   /* Pass 10 - Free memory by expiring oldest blocks */
11561
11562   int end=((((int)out-BASE_ADDR)>>(TARGET_SIZE_2-16))+16384)&65535;
11563   while(expirep!=end)
11564   {
11565     int shift=TARGET_SIZE_2-3; // Divide into 8 blocks
11566     int base=BASE_ADDR+((expirep>>13)<<shift); // Base address of this block
11567     inv_debug("EXP: Phase %d\n",expirep);
11568     switch((expirep>>11)&3)
11569     {
11570       case 0:
11571         // Clear jump_in and jump_dirty
11572         ll_remove_matching_addrs(jump_in+(expirep&2047),base,shift);
11573         ll_remove_matching_addrs(jump_dirty+(expirep&2047),base,shift);
11574         ll_remove_matching_addrs(jump_in+2048+(expirep&2047),base,shift);
11575         ll_remove_matching_addrs(jump_dirty+2048+(expirep&2047),base,shift);
11576         break;
11577       case 1:
11578         // Clear pointers
11579         ll_kill_pointers(jump_out[expirep&2047],base,shift);
11580         ll_kill_pointers(jump_out[(expirep&2047)+2048],base,shift);
11581         break;
11582       case 2:
11583         // Clear hash table
11584         for(i=0;i<32;i++) {
11585           int *ht_bin=hash_table[((expirep&2047)<<5)+i];
11586           if((ht_bin[3]>>shift)==(base>>shift) ||
11587              ((ht_bin[3]-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(base>>shift)) {
11588             inv_debug("EXP: Remove hash %x -> %x\n",ht_bin[2],ht_bin[3]);
11589             ht_bin[2]=ht_bin[3]=-1;
11590           }
11591           if((ht_bin[1]>>shift)==(base>>shift) ||
11592              ((ht_bin[1]-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(base>>shift)) {
11593             inv_debug("EXP: Remove hash %x -> %x\n",ht_bin[0],ht_bin[1]);
11594             ht_bin[0]=ht_bin[2];
11595             ht_bin[1]=ht_bin[3];
11596             ht_bin[2]=ht_bin[3]=-1;
11597           }
11598         }
11599         break;
11600       case 3:
11601         // Clear jump_out
11602         #ifdef __arm__
11603         if((expirep&2047)==0)
11604           do_clear_cache();
11605         #endif
11606         ll_remove_matching_addrs(jump_out+(expirep&2047),base,shift);
11607         ll_remove_matching_addrs(jump_out+2048+(expirep&2047),base,shift);
11608         break;
11609     }
11610     expirep=(expirep+1)&65535;
11611   }
11612   return 0;
11613 }
11614
11615 // vim:shiftwidth=2:expandtab