1 /* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
2 * Mupen64plus - new_dynarec.c *
3 * Copyright (C) 2009-2011 Ari64 *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. *
19 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
22 #include <stdint.h> //include for uint64_t
27 #include <libkern/OSCacheControl.h>
30 #include <3ds_utils.h>
37 #include "new_dynarec_config.h"
38 #include "../psxhle.h"
39 #include "../psxinterpreter.h"
41 #include "emu_if.h" // emulator interface
42 #include "linkage_offsets.h"
43 #include "compiler_features.h"
44 #include "arm_features.h"
47 #define ARRAY_SIZE(x) (sizeof(x) / sizeof(x[0]))
50 #define min(a, b) ((b) < (a) ? (b) : (a))
53 #define max(a, b) ((b) > (a) ? (b) : (a))
58 //#define REGMAP_PRINT // with DISASM only
63 #define assem_debug printf
65 #define assem_debug(...)
67 //#define inv_debug printf
68 #define inv_debug(...)
71 #include "assem_x86.h"
74 #include "assem_x64.h"
77 #include "assem_arm.h"
80 #include "assem_arm64.h"
83 #define RAM_SIZE 0x200000
85 #define MAX_OUTPUT_BLOCK_SIZE 262144
86 #define EXPIRITY_OFFSET (MAX_OUTPUT_BLOCK_SIZE * 2)
87 #define PAGE_COUNT 1024
89 #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
90 #define INVALIDATE_USE_COND_CALL
94 // apparently Vita has a 16MB limit, so either we cut tc in half,
95 // or use this hack (it's a hack because tc size was designed to be power-of-2)
96 #define TC_REDUCE_BYTES 4096
98 #define TC_REDUCE_BYTES 0
103 struct tramp_insns ops[2048 / sizeof(struct tramp_insns)];
104 const void *f[2048 / sizeof(void *)];
109 u_char translation_cache[(1 << TARGET_SIZE_2) - TC_REDUCE_BYTES];
110 struct ndrc_tramp tramp;
113 #ifdef BASE_ADDR_DYNAMIC
114 static struct ndrc_mem *ndrc;
116 static struct ndrc_mem ndrc_ __attribute__((aligned(4096)));
117 static struct ndrc_mem *ndrc = &ndrc_;
119 #ifdef TC_WRITE_OFFSET
121 # include <sys/types.h>
122 # include <sys/stat.h>
126 static long ndrc_write_ofs;
127 #define NDRC_WRITE_OFFSET(x) (void *)((char *)(x) + ndrc_write_ofs)
129 #define NDRC_WRITE_OFFSET(x) (x)
152 // regmap_pre[i] - regs before [i] insn starts; dirty things here that
153 // don't match .regmap will be written back
154 // [i].regmap_entry - regs that must be set up if someone jumps here
155 // [i].regmap - regs [i] insn will read/(over)write
156 // branch_regs[i].* - same as above but for branches, takes delay slot into account
159 signed char regmap_entry[HOST_REGS];
160 signed char regmap[HOST_REGS];
164 u_int wasconst; // before; for example 'lw r2, (r2)' wasconst is true
165 u_int isconst; // ... but isconst is false when r2 is known (hr)
166 u_int loadedconst; // host regs that have constants loaded
167 //u_int waswritten; // MIPS regs that were used as store base before
197 struct block_info *next;
200 u_int start; // vaddr of the block start
201 u_int len; // of the whole block source
206 u_char inv_near_misses;
224 static struct decoded_insn
227 u_char opcode; // bits 31-26
228 u_char opcode2; // (depends on opcode)
241 u_char is_delay_load:1; // is_load + MFC/CFC
242 u_char is_exception:1; // unconditional, also interp. fallback
243 u_char may_except:1; // might generate an exception
246 static struct compile_info
251 signed char min_free_regs;
253 signed char reserved[2];
257 static char invalid_code[0x100000];
258 static struct ht_entry hash_table[65536];
259 static struct block_info *blocks[PAGE_COUNT];
260 static struct jump_info *jumps[PAGE_COUNT];
262 static u_int *source;
263 static uint64_t gte_rs[MAXBLOCK]; // gte: 32 data and 32 ctl regs
264 static uint64_t gte_rt[MAXBLOCK];
265 static uint64_t gte_unneeded[MAXBLOCK];
266 static u_int smrv[32]; // speculated MIPS register values
267 static u_int smrv_strong; // mask or regs that are likely to have correct values
268 static u_int smrv_weak; // same, but somewhat less likely
269 static u_int smrv_strong_next; // same, but after current insn executes
270 static u_int smrv_weak_next;
271 static uint64_t unneeded_reg[MAXBLOCK];
272 static uint64_t branch_unneeded_reg[MAXBLOCK];
273 // see 'struct regstat' for a description
274 static signed char regmap_pre[MAXBLOCK][HOST_REGS];
275 // contains 'real' consts at [i] insn, but may differ from what's actually
276 // loaded in host reg as 'final' value is always loaded, see get_final_value()
277 static uint32_t current_constmap[HOST_REGS];
278 static uint32_t constmap[MAXBLOCK][HOST_REGS];
279 static struct regstat regs[MAXBLOCK];
280 static struct regstat branch_regs[MAXBLOCK];
282 static void *instr_addr[MAXBLOCK];
283 static struct link_entry link_addr[MAXBLOCK];
284 static int linkcount;
285 static struct code_stub stubs[MAXBLOCK*3];
286 static int stubcount;
287 static u_int literals[1024][2];
288 static int literalcount;
289 static int is_delayslot;
290 static char shadow[1048576] __attribute__((aligned(16)));
292 static u_int expirep;
293 static u_int stop_after_jal;
294 static u_int f1_hack;
296 static int stat_bc_direct;
297 static int stat_bc_pre;
298 static int stat_bc_restore;
299 static int stat_ht_lookups;
300 static int stat_jump_in_lookups;
301 static int stat_restore_tries;
302 static int stat_restore_compares;
303 static int stat_inv_addr_calls;
304 static int stat_inv_hits;
305 static int stat_blocks;
306 static int stat_links;
307 #define stat_inc(s) s++
308 #define stat_dec(s) s--
309 #define stat_clear(s) s = 0
313 #define stat_clear(s)
316 int new_dynarec_hacks;
317 int new_dynarec_hacks_pergame;
318 int new_dynarec_hacks_old;
319 int new_dynarec_did_compile;
321 #define HACK_ENABLED(x) ((new_dynarec_hacks | new_dynarec_hacks_pergame) & (x))
323 extern int cycle_count; // ... until end of the timeslice, counts -N -> 0
324 extern int last_count; // last absolute target, often = next_interupt
326 extern int pending_exception;
327 extern int branch_target;
328 extern uintptr_t ram_offset;
329 extern uintptr_t mini_ht[32][2];
331 /* registers that may be allocated */
333 #define LOREG 32 // lo
334 #define HIREG 33 // hi
335 //#define FSREG 34 // FPU status (FCSR)
336 #define CSREG 35 // Coprocessor status
337 #define CCREG 36 // Cycle count
338 #define INVCP 37 // Pointer to invalid_code
339 //#define MMREG 38 // Pointer to memory_map
340 #define ROREG 39 // ram offset (if rdram!=0x80000000)
342 #define FTEMP 40 // FPU temporary register
343 #define PTEMP 41 // Prefetch temporary register
344 //#define TLREG 42 // TLB mapping offset
345 #define RHASH 43 // Return address hash
346 #define RHTBL 44 // Return address hash table address
347 #define RTEMP 45 // JR/JALR address register
349 #define AGEN1 46 // Address generation temporary register (pass5b_preallocate2)
350 //#define AGEN2 47 // Address generation temporary register
351 #define BTREG 50 // Branch target temporary register
353 /* instruction types */
354 #define NOP 0 // No operation
355 #define LOAD 1 // Load
356 #define STORE 2 // Store
357 #define LOADLR 3 // Unaligned load
358 #define STORELR 4 // Unaligned store
359 #define MOV 5 // Move (hi/lo only)
360 #define ALU 6 // Arithmetic/logic
361 #define MULTDIV 7 // Multiply/divide
362 #define SHIFT 8 // Shift by register
363 #define SHIFTIMM 9// Shift by immediate
364 #define IMM16 10 // 16-bit immediate
365 #define RJUMP 11 // Unconditional jump to register
366 #define UJUMP 12 // Unconditional jump
367 #define CJUMP 13 // Conditional branch (BEQ/BNE/BGTZ/BLEZ)
368 #define SJUMP 14 // Conditional branch (regimm format)
369 #define COP0 15 // Coprocessor 0
371 #define SYSCALL 22// SYSCALL,BREAK
372 #define OTHER 23 // Other/unknown - do nothing
373 #define HLECALL 26// PCSX fake opcodes for HLE
374 #define COP2 27 // Coprocessor 2 move
375 #define C2LS 28 // Coprocessor 2 load/store
376 #define C2OP 29 // Coprocessor 2 operation
377 #define INTCALL 30// Call interpreter to handle rare corner cases
384 #define DJT_1 (void *)1l // no function, just a label in assem_debug log
385 #define DJT_2 (void *)2l
390 void jump_syscall (u_int u0, u_int u1, u_int pc);
391 void jump_syscall_ds(u_int u0, u_int u1, u_int pc);
392 void jump_break (u_int u0, u_int u1, u_int pc);
393 void jump_break_ds(u_int u0, u_int u1, u_int pc);
394 void jump_overflow (u_int u0, u_int u1, u_int pc);
395 void jump_overflow_ds(u_int u0, u_int u1, u_int pc);
396 void jump_addrerror (u_int cause, u_int addr, u_int pc);
397 void jump_addrerror_ds(u_int cause, u_int addr, u_int pc);
398 void jump_to_new_pc();
399 void call_gteStall();
400 void new_dyna_leave();
402 void *ndrc_get_addr_ht_param(u_int vaddr, int can_compile);
403 void *ndrc_get_addr_ht(u_int vaddr);
404 void ndrc_add_jump_out(u_int vaddr, void *src);
405 void ndrc_write_invalidate_one(u_int addr);
406 static void ndrc_write_invalidate_many(u_int addr, u_int end);
408 static int new_recompile_block(u_int addr);
409 static void invalidate_block(struct block_info *block);
410 static void exception_assemble(int i, const struct regstat *i_regs, int ccadj_);
412 // Needed by assembler
413 static void wb_register(signed char r, const signed char regmap[], uint64_t dirty);
414 static void wb_dirtys(const signed char i_regmap[], uint64_t i_dirty);
415 static void wb_needed_dirtys(const signed char i_regmap[], uint64_t i_dirty, int addr);
416 static void load_all_regs(const signed char i_regmap[]);
417 static void load_needed_regs(const signed char i_regmap[], const signed char next_regmap[]);
418 static void load_regs_entry(int t);
419 static void load_all_consts(const signed char regmap[], u_int dirty, int i);
420 static u_int get_host_reglist(const signed char *regmap);
422 static int get_final_value(int hr, int i, int *value);
423 static void add_stub(enum stub_type type, void *addr, void *retaddr,
424 u_int a, uintptr_t b, uintptr_t c, u_int d, u_int e);
425 static void add_stub_r(enum stub_type type, void *addr, void *retaddr,
426 int i, int addr_reg, const struct regstat *i_regs, int ccadj, u_int reglist);
427 static void add_to_linker(void *addr, u_int target, int ext);
428 static void *get_direct_memhandler(void *table, u_int addr,
429 enum stub_type type, uintptr_t *addr_host);
430 static void cop2_do_stall_check(u_int op, int i, const struct regstat *i_regs, u_int reglist);
431 static void pass_args(int a0, int a1);
432 static void emit_far_jump(const void *f);
433 static void emit_far_call(const void *f);
436 #include <psp2/kernel/sysmem.h>
438 // note: this interacts with RetroArch's Vita bootstrap code: bootstrap/vita/sbrk.c
439 extern int getVMBlock();
440 int _newlib_vm_size_user = sizeof(*ndrc);
443 static void mprotect_w_x(void *start, void *end, int is_x)
447 // *Open* enables write on all memory that was
448 // allocated by sceKernelAllocMemBlockForVM()?
450 sceKernelCloseVMDomain();
452 sceKernelOpenVMDomain();
453 #elif defined(HAVE_LIBNX)
455 // check to avoid the full flush in jitTransitionToExecutable()
456 if (g_jit.type != JitType_CodeMemory) {
458 rc = jitTransitionToExecutable(&g_jit);
460 rc = jitTransitionToWritable(&g_jit);
462 ;//SysPrintf("jitTransition %d %08x\n", is_x, rc);
464 #elif defined(TC_WRITE_OFFSET)
465 // separated rx and rw areas are always available
467 u_long mstart = (u_long)start & ~4095ul;
468 u_long mend = (u_long)end;
469 if (mprotect((void *)mstart, mend - mstart,
470 PROT_READ | (is_x ? PROT_EXEC : PROT_WRITE)) != 0)
471 SysPrintf("mprotect(%c) failed: %s\n", is_x ? 'x' : 'w', strerror(errno));
476 static void start_tcache_write(void *start, void *end)
478 mprotect_w_x(start, end, 0);
481 static void end_tcache_write(void *start, void *end)
483 #if defined(__arm__) || defined(__aarch64__)
484 size_t len = (char *)end - (char *)start;
485 #if defined(__BLACKBERRY_QNX__)
486 msync(start, len, MS_SYNC | MS_CACHE_ONLY | MS_INVALIDATE_ICACHE);
487 #elif defined(__MACH__)
488 sys_cache_control(kCacheFunctionPrepareForExecution, start, len);
490 sceKernelSyncVMDomain(sceBlock, start, len);
492 ctr_flush_invalidate_cache();
493 #elif defined(HAVE_LIBNX)
494 if (g_jit.type == JitType_CodeMemory) {
495 armDCacheClean(start, len);
496 armICacheInvalidate((char *)start - ndrc_write_ofs, len);
497 // as of v4.2.1 libnx lacks isb
498 __asm__ volatile("isb" ::: "memory");
500 #elif defined(__aarch64__)
501 // as of 2021, __clear_cache() is still broken on arm64
502 // so here is a custom one :(
503 clear_cache_arm64(start, end);
505 __clear_cache(start, end);
510 mprotect_w_x(start, end, 1);
513 static void *start_block(void)
515 u_char *end = out + MAX_OUTPUT_BLOCK_SIZE;
516 if (end > ndrc->translation_cache + sizeof(ndrc->translation_cache))
517 end = ndrc->translation_cache + sizeof(ndrc->translation_cache);
518 start_tcache_write(NDRC_WRITE_OFFSET(out), NDRC_WRITE_OFFSET(end));
522 static void end_block(void *start)
524 end_tcache_write(NDRC_WRITE_OFFSET(start), NDRC_WRITE_OFFSET(out));
527 #ifdef NDRC_CACHE_FLUSH_ALL
529 static int needs_clear_cache;
531 static void mark_clear_cache(void *target)
533 if (!needs_clear_cache) {
534 start_tcache_write(NDRC_WRITE_OFFSET(ndrc), NDRC_WRITE_OFFSET(ndrc + 1));
535 needs_clear_cache = 1;
539 static void do_clear_cache(void)
541 if (needs_clear_cache) {
542 end_tcache_write(NDRC_WRITE_OFFSET(ndrc), NDRC_WRITE_OFFSET(ndrc + 1));
543 needs_clear_cache = 0;
549 // also takes care of w^x mappings when patching code
550 static u_int needs_clear_cache[1<<(TARGET_SIZE_2-17)];
552 static void mark_clear_cache(void *target)
554 uintptr_t offset = (u_char *)target - ndrc->translation_cache;
555 u_int mask = 1u << ((offset >> 12) & 31);
556 if (!(needs_clear_cache[offset >> 17] & mask)) {
557 char *start = (char *)NDRC_WRITE_OFFSET((uintptr_t)target & ~4095l);
558 start_tcache_write(start, start + 4095);
559 needs_clear_cache[offset >> 17] |= mask;
563 // Clearing the cache is rather slow on ARM Linux, so mark the areas
564 // that need to be cleared, and then only clear these areas once.
565 static void do_clear_cache(void)
568 for (i = 0; i < (1<<(TARGET_SIZE_2-17)); i++)
570 u_int bitmap = needs_clear_cache[i];
573 for (j = 0; j < 32; j++)
576 if (!(bitmap & (1u << j)))
579 start = ndrc->translation_cache + i*131072 + j*4096;
581 for (j++; j < 32; j++) {
582 if (!(bitmap & (1u << j)))
586 end_tcache_write(NDRC_WRITE_OFFSET(start), NDRC_WRITE_OFFSET(end));
588 needs_clear_cache[i] = 0;
592 #endif // NDRC_CACHE_FLUSH_ALL
594 #define NO_CYCLE_PENALTY_THR 12
596 int cycle_multiplier_old;
597 static int cycle_multiplier_active;
599 static int CLOCK_ADJUST(int x)
601 int m = cycle_multiplier_active;
602 int s = (x >> 31) | 1;
603 return (x * m + s * 50) / 100;
606 static int ds_writes_rjump_rs(int i)
608 return dops[i].rs1 != 0
609 && (dops[i].rs1 == dops[i+1].rt1 || dops[i].rs1 == dops[i+1].rt2
610 || dops[i].rs1 == dops[i].rt1); // overwrites itself - same effect
613 // psx addr mirror masking (for invalidation)
614 static u_int pmmask(u_int vaddr)
616 vaddr &= ~0xe0000000;
617 if (vaddr < 0x01000000)
618 vaddr &= ~0x00e00000; // RAM mirrors
622 static u_int get_page(u_int vaddr)
624 u_int page = pmmask(vaddr) >> 12;
625 if (page >= PAGE_COUNT / 2)
626 page = PAGE_COUNT / 2 + (page & (PAGE_COUNT / 2 - 1));
630 // get a page for looking for a block that has vaddr
631 // (needed because the block may start in previous page)
632 static u_int get_page_prev(u_int vaddr)
634 assert(MAXBLOCK <= (1 << 12));
635 u_int page = get_page(vaddr);
641 static struct ht_entry *hash_table_get(u_int vaddr)
643 return &hash_table[((vaddr>>16)^vaddr)&0xFFFF];
646 static void hash_table_add(u_int vaddr, void *tcaddr)
648 struct ht_entry *ht_bin = hash_table_get(vaddr);
650 ht_bin->vaddr[1] = ht_bin->vaddr[0];
651 ht_bin->tcaddr[1] = ht_bin->tcaddr[0];
652 ht_bin->vaddr[0] = vaddr;
653 ht_bin->tcaddr[0] = tcaddr;
656 static void hash_table_remove(int vaddr)
658 //printf("remove hash: %x\n",vaddr);
659 struct ht_entry *ht_bin = hash_table_get(vaddr);
660 if (ht_bin->vaddr[1] == vaddr) {
661 ht_bin->vaddr[1] = -1;
662 ht_bin->tcaddr[1] = NULL;
664 if (ht_bin->vaddr[0] == vaddr) {
665 ht_bin->vaddr[0] = ht_bin->vaddr[1];
666 ht_bin->tcaddr[0] = ht_bin->tcaddr[1];
667 ht_bin->vaddr[1] = -1;
668 ht_bin->tcaddr[1] = NULL;
672 static void mark_invalid_code(u_int vaddr, u_int len, char invalid)
674 u_int vaddr_m = vaddr & 0x1fffffff;
676 for (i = vaddr_m & ~0xfff; i < vaddr_m + len; i += 0x1000) {
677 // ram mirrors, but should not hurt bios
678 for (j = 0; j < 0x800000; j += 0x200000) {
679 invalid_code[(i|j) >> 12] =
680 invalid_code[(i|j|0x80000000u) >> 12] =
681 invalid_code[(i|j|0xa0000000u) >> 12] = invalid;
684 if (!invalid && vaddr + len > inv_code_start && vaddr <= inv_code_end)
685 inv_code_start = inv_code_end = ~0;
688 static int doesnt_expire_soon(u_char *tcaddr)
690 u_int diff = (u_int)(tcaddr - out) & ((1u << TARGET_SIZE_2) - 1u);
691 return diff > EXPIRITY_OFFSET + MAX_OUTPUT_BLOCK_SIZE;
694 static unused void check_for_block_changes(u_int start, u_int end)
696 u_int start_page = get_page_prev(start);
697 u_int end_page = get_page(end - 1);
700 for (page = start_page; page <= end_page; page++) {
701 struct block_info *block;
702 for (block = blocks[page]; block != NULL; block = block->next) {
705 if (memcmp(block->source, block->copy, block->len)) {
706 printf("bad block %08x-%08x %016llx %016llx @%08x\n",
707 block->start, block->start + block->len,
708 *(long long *)block->source, *(long long *)block->copy, psxRegs.pc);
716 static void *try_restore_block(u_int vaddr, u_int start_page, u_int end_page)
718 void *found_clean = NULL;
721 stat_inc(stat_restore_tries);
722 for (page = start_page; page <= end_page; page++) {
723 struct block_info *block;
724 for (block = blocks[page]; block != NULL; block = block->next) {
725 if (vaddr < block->start)
727 if (!block->is_dirty || vaddr >= block->start + block->len)
729 for (i = 0; i < block->jump_in_cnt; i++)
730 if (block->jump_in[i].vaddr == vaddr)
732 if (i == block->jump_in_cnt)
734 assert(block->source && block->copy);
735 stat_inc(stat_restore_compares);
736 if (memcmp(block->source, block->copy, block->len))
739 block->is_dirty = block->inv_near_misses = 0;
740 found_clean = block->jump_in[i].addr;
741 hash_table_add(vaddr, found_clean);
742 mark_invalid_code(block->start, block->len, 0);
743 stat_inc(stat_bc_restore);
744 inv_debug("INV: restored %08x %p (%d)\n", vaddr, found_clean, block->jump_in_cnt);
751 // Get address from virtual address
752 // This is called from the recompiled JR/JALR instructions
753 static void noinline *get_addr(u_int vaddr, int can_compile)
755 u_int start_page = get_page_prev(vaddr);
756 u_int i, page, end_page = get_page(vaddr);
757 void *found_clean = NULL;
759 stat_inc(stat_jump_in_lookups);
760 for (page = start_page; page <= end_page; page++) {
761 const struct block_info *block;
762 for (block = blocks[page]; block != NULL; block = block->next) {
763 if (vaddr < block->start)
765 if (block->is_dirty || vaddr >= block->start + block->len)
767 for (i = 0; i < block->jump_in_cnt; i++)
768 if (block->jump_in[i].vaddr == vaddr)
770 if (i == block->jump_in_cnt)
772 found_clean = block->jump_in[i].addr;
773 hash_table_add(vaddr, found_clean);
777 found_clean = try_restore_block(vaddr, start_page, end_page);
784 int r = new_recompile_block(vaddr);
786 return ndrc_get_addr_ht(vaddr);
788 // generate an address error
792 psxRegs.CP0.n.Cause &= 0x300;
793 psxRegs.CP0.n.EPC = vaddr;
795 psxRegs.CP0.n.Cause |= R3000E_AdEL << 2;
796 psxRegs.CP0.n.BadVAddr = vaddr;
798 psxRegs.CP0.n.Cause |= R3000E_IBE << 2;
799 psxRegs.pc = 0x80000080;
800 return ndrc_get_addr_ht(0x80000080);
803 // Look up address in hash table first
804 void *ndrc_get_addr_ht_param(u_int vaddr, int can_compile)
806 //check_for_block_changes(vaddr, vaddr + MAXBLOCK);
807 const struct ht_entry *ht_bin = hash_table_get(vaddr);
808 u_int vaddr_a = vaddr & ~3;
809 stat_inc(stat_ht_lookups);
810 if (ht_bin->vaddr[0] == vaddr_a) return ht_bin->tcaddr[0];
811 if (ht_bin->vaddr[1] == vaddr_a) return ht_bin->tcaddr[1];
812 return get_addr(vaddr, can_compile);
815 void *ndrc_get_addr_ht(u_int vaddr)
817 return ndrc_get_addr_ht_param(vaddr, 1);
820 static void clear_all_regs(signed char regmap[])
822 memset(regmap, -1, sizeof(regmap[0]) * HOST_REGS);
825 // get_reg: get allocated host reg from mips reg
826 // returns -1 if no such mips reg was allocated
827 #if defined(__arm__) && defined(HAVE_ARMV6) && HOST_REGS == 13 && EXCLUDE_REG == 11
829 extern signed char get_reg(const signed char regmap[], signed char r);
833 static signed char get_reg(const signed char regmap[], signed char r)
836 for (hr = 0; hr < HOST_REGS; hr++) {
837 if (hr == EXCLUDE_REG)
847 // get reg suitable for writing
848 static signed char get_reg_w(const signed char regmap[], signed char r)
850 return r == 0 ? -1 : get_reg(regmap, r);
853 // get reg as mask bit (1 << hr)
854 static u_int get_regm(const signed char regmap[], signed char r)
856 return (1u << (get_reg(regmap, r) & 31)) & ~(1u << 31);
859 static signed char get_reg_temp(const signed char regmap[])
862 for (hr = 0; hr < HOST_REGS; hr++) {
863 if (hr == EXCLUDE_REG)
865 if (regmap[hr] == (signed char)-1)
871 // Find a register that is available for two consecutive cycles
872 static signed char get_reg2(signed char regmap1[], const signed char regmap2[], int r)
875 for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&®map1[hr]==r&®map2[hr]==r) return hr;
879 // reverse reg map: mips -> host
880 #define RRMAP_SIZE 64
881 static void make_rregs(const signed char regmap[], signed char rrmap[RRMAP_SIZE],
882 u_int *regs_can_change)
884 u_int r, hr, hr_can_change = 0;
885 memset(rrmap, -1, RRMAP_SIZE);
886 for (hr = 0; hr < HOST_REGS; )
889 rrmap[r & (RRMAP_SIZE - 1)] = hr;
890 // only add mips $1-$31+$lo, others shifted out
891 hr_can_change |= (uint64_t)1 << (hr + ((r - 1) & 32));
893 if (hr == EXCLUDE_REG)
896 hr_can_change |= 1u << (rrmap[33] & 31);
897 hr_can_change |= 1u << (rrmap[CCREG] & 31);
898 hr_can_change &= ~(1u << 31);
899 *regs_can_change = hr_can_change;
902 // same as get_reg, but takes rrmap
903 static signed char get_rreg(signed char rrmap[RRMAP_SIZE], signed char r)
905 assert(0 <= r && r < RRMAP_SIZE);
909 static int count_free_regs(const signed char regmap[])
913 for(hr=0;hr<HOST_REGS;hr++)
915 if(hr!=EXCLUDE_REG) {
916 if(regmap[hr]<0) count++;
922 static void dirty_reg(struct regstat *cur, signed char reg)
926 hr = get_reg(cur->regmap, reg);
931 static void set_const(struct regstat *cur, signed char reg, uint32_t value)
935 hr = get_reg(cur->regmap, reg);
937 cur->isconst |= 1<<hr;
938 current_constmap[hr] = value;
942 static void clear_const(struct regstat *cur, signed char reg)
946 hr = get_reg(cur->regmap, reg);
948 cur->isconst &= ~(1<<hr);
951 static int is_const(const struct regstat *cur, signed char reg)
954 if (reg < 0) return 0;
956 hr = get_reg(cur->regmap, reg);
958 return (cur->isconst>>hr)&1;
962 static uint32_t get_const(const struct regstat *cur, signed char reg)
966 hr = get_reg(cur->regmap, reg);
968 return current_constmap[hr];
970 SysPrintf("Unknown constant in r%d\n", reg);
974 // Least soon needed registers
975 // Look at the next ten instructions and see which registers
976 // will be used. Try not to reallocate these.
977 static void lsn(u_char hsn[], int i, int *preferred_reg)
987 if (dops[i+j].is_ujump)
989 // Don't go past an unconditonal jump
996 if(dops[i+j].rs1) hsn[dops[i+j].rs1]=j;
997 if(dops[i+j].rs2) hsn[dops[i+j].rs2]=j;
998 if(dops[i+j].rt1) hsn[dops[i+j].rt1]=j;
999 if(dops[i+j].rt2) hsn[dops[i+j].rt2]=j;
1000 if(dops[i+j].itype==STORE || dops[i+j].itype==STORELR) {
1001 // Stores can allocate zero
1002 hsn[dops[i+j].rs1]=j;
1003 hsn[dops[i+j].rs2]=j;
1005 if (ram_offset && (dops[i+j].is_load || dops[i+j].is_store))
1007 // On some architectures stores need invc_ptr
1008 #if defined(HOST_IMM8)
1009 if (dops[i+j].is_store)
1012 if(i+j>=0&&(dops[i+j].itype==UJUMP||dops[i+j].itype==CJUMP||dops[i+j].itype==SJUMP))
1020 if(cinfo[i+b].ba>=start && cinfo[i+b].ba<(start+slen*4))
1022 // Follow first branch
1023 int t=(cinfo[i+b].ba-start)>>2;
1024 j=7-b;if(t+j>=slen) j=slen-t-1;
1027 if(dops[t+j].rs1) if(hsn[dops[t+j].rs1]>j+b+2) hsn[dops[t+j].rs1]=j+b+2;
1028 if(dops[t+j].rs2) if(hsn[dops[t+j].rs2]>j+b+2) hsn[dops[t+j].rs2]=j+b+2;
1029 //if(dops[t+j].rt1) if(hsn[dops[t+j].rt1]>j+b+2) hsn[dops[t+j].rt1]=j+b+2;
1030 //if(dops[t+j].rt2) if(hsn[dops[t+j].rt2]>j+b+2) hsn[dops[t+j].rt2]=j+b+2;
1033 // TODO: preferred register based on backward branch
1035 // Delay slot should preferably not overwrite branch conditions or cycle count
1036 if (i > 0 && dops[i-1].is_jump) {
1037 if(dops[i-1].rs1) if(hsn[dops[i-1].rs1]>1) hsn[dops[i-1].rs1]=1;
1038 if(dops[i-1].rs2) if(hsn[dops[i-1].rs2]>1) hsn[dops[i-1].rs2]=1;
1040 // ...or hash tables
1044 // Coprocessor load/store needs FTEMP, even if not declared
1045 if(dops[i].itype==C2LS) {
1048 // Load L/R also uses FTEMP as a temporary register
1049 if(dops[i].itype==LOADLR) {
1052 // Also SWL/SWR/SDL/SDR
1053 if(dops[i].opcode==0x2a||dops[i].opcode==0x2e||dops[i].opcode==0x2c||dops[i].opcode==0x2d) {
1056 // Don't remove the miniht registers
1057 if(dops[i].itype==UJUMP||dops[i].itype==RJUMP)
1064 // We only want to allocate registers if we're going to use them again soon
1065 static int needed_again(int r, int i)
1071 if (i > 0 && dops[i-1].is_ujump)
1073 if(cinfo[i-1].ba<start || cinfo[i-1].ba>start+slen*4-4)
1074 return 0; // Don't need any registers if exiting the block
1082 if (dops[i+j].is_ujump)
1084 // Don't go past an unconditonal jump
1088 if (dops[i+j].is_exception)
1095 if(dops[i+j].rs1==r) rn=j;
1096 if(dops[i+j].rs2==r) rn=j;
1097 if((unneeded_reg[i+j]>>r)&1) rn=10;
1098 if(i+j>=0&&(dops[i+j].itype==UJUMP||dops[i+j].itype==CJUMP||dops[i+j].itype==SJUMP))
1108 // Try to match register allocations at the end of a loop with those
1110 static int loop_reg(int i, int r, int hr)
1119 if (dops[i+j].is_ujump)
1121 // Don't go past an unconditonal jump
1128 if(dops[i-1].itype==UJUMP||dops[i-1].itype==CJUMP||dops[i-1].itype==SJUMP)
1134 if((unneeded_reg[i+k]>>r)&1) return hr;
1135 if(i+k>=0&&(dops[i+k].itype==UJUMP||dops[i+k].itype==CJUMP||dops[i+k].itype==SJUMP))
1137 if(cinfo[i+k].ba>=start && cinfo[i+k].ba<(start+i*4))
1139 int t=(cinfo[i+k].ba-start)>>2;
1140 int reg=get_reg(regs[t].regmap_entry,r);
1141 if(reg>=0) return reg;
1142 //reg=get_reg(regs[t+1].regmap_entry,r);
1143 //if(reg>=0) return reg;
1151 // Allocate every register, preserving source/target regs
1152 static void alloc_all(struct regstat *cur,int i)
1156 for(hr=0;hr<HOST_REGS;hr++) {
1157 if(hr!=EXCLUDE_REG) {
1158 if((cur->regmap[hr]!=dops[i].rs1)&&(cur->regmap[hr]!=dops[i].rs2)&&
1159 (cur->regmap[hr]!=dops[i].rt1)&&(cur->regmap[hr]!=dops[i].rt2))
1162 cur->dirty&=~(1<<hr);
1165 if(cur->regmap[hr]==0)
1168 cur->dirty&=~(1<<hr);
1175 static int host_tempreg_in_use;
1177 static void host_tempreg_acquire(void)
1179 assert(!host_tempreg_in_use);
1180 host_tempreg_in_use = 1;
1183 static void host_tempreg_release(void)
1185 host_tempreg_in_use = 0;
1188 static void host_tempreg_acquire(void) {}
1189 static void host_tempreg_release(void) {}
1193 extern void gen_interupt();
1194 extern void do_insn_cmp();
1195 #define FUNCNAME(f) { f, " " #f }
1196 static const struct {
1199 } function_names[] = {
1200 FUNCNAME(cc_interrupt),
1201 FUNCNAME(gen_interupt),
1202 FUNCNAME(ndrc_get_addr_ht),
1203 FUNCNAME(jump_handler_read8),
1204 FUNCNAME(jump_handler_read16),
1205 FUNCNAME(jump_handler_read32),
1206 FUNCNAME(jump_handler_write8),
1207 FUNCNAME(jump_handler_write16),
1208 FUNCNAME(jump_handler_write32),
1209 FUNCNAME(ndrc_write_invalidate_one),
1210 FUNCNAME(ndrc_write_invalidate_many),
1211 FUNCNAME(jump_to_new_pc),
1212 FUNCNAME(jump_break),
1213 FUNCNAME(jump_break_ds),
1214 FUNCNAME(jump_syscall),
1215 FUNCNAME(jump_syscall_ds),
1216 FUNCNAME(jump_overflow),
1217 FUNCNAME(jump_overflow_ds),
1218 FUNCNAME(jump_addrerror),
1219 FUNCNAME(jump_addrerror_ds),
1220 FUNCNAME(call_gteStall),
1221 FUNCNAME(new_dyna_leave),
1222 FUNCNAME(pcsx_mtc0),
1223 FUNCNAME(pcsx_mtc0_ds),
1226 FUNCNAME(do_memhandler_pre),
1227 FUNCNAME(do_memhandler_post),
1230 FUNCNAME(do_insn_cmp),
1234 static const char *func_name(const void *a)
1237 for (i = 0; i < sizeof(function_names)/sizeof(function_names[0]); i++)
1238 if (function_names[i].addr == a)
1239 return function_names[i].name;
1243 static const char *fpofs_name(u_int ofs)
1245 u_int *p = (u_int *)&dynarec_local + ofs/sizeof(u_int);
1246 static char buf[64];
1248 #define ofscase(x) case LO_##x: return " ; " #x
1249 ofscase(next_interupt);
1250 ofscase(last_count);
1251 ofscase(pending_exception);
1262 ofscase(ram_offset);
1266 if (psxRegs.GPR.r <= p && p < &psxRegs.GPR.r[32])
1267 snprintf(buf, sizeof(buf), " ; r%d", (int)(p - psxRegs.GPR.r));
1268 else if (psxRegs.CP0.r <= p && p < &psxRegs.CP0.r[32])
1269 snprintf(buf, sizeof(buf), " ; cp0 $%d", (int)(p - psxRegs.CP0.r));
1270 else if (psxRegs.CP2D.r <= p && p < &psxRegs.CP2D.r[32])
1271 snprintf(buf, sizeof(buf), " ; cp2d $%d", (int)(p - psxRegs.CP2D.r));
1272 else if (psxRegs.CP2C.r <= p && p < &psxRegs.CP2C.r[32])
1273 snprintf(buf, sizeof(buf), " ; cp2c $%d", (int)(p - psxRegs.CP2C.r));
1277 #define func_name(x) ""
1278 #define fpofs_name(x) ""
1282 #include "assem_x86.c"
1285 #include "assem_x64.c"
1288 #include "assem_arm.c"
1291 #include "assem_arm64.c"
1294 static void *get_trampoline(const void *f)
1296 struct ndrc_tramp *tramp = NDRC_WRITE_OFFSET(&ndrc->tramp);
1299 for (i = 0; i < ARRAY_SIZE(tramp->f); i++) {
1300 if (tramp->f[i] == f || tramp->f[i] == NULL)
1303 if (i == ARRAY_SIZE(tramp->f)) {
1304 SysPrintf("trampoline table is full, last func %p\n", f);
1307 if (tramp->f[i] == NULL) {
1308 start_tcache_write(&tramp->f[i], &tramp->f[i + 1]);
1310 end_tcache_write(&tramp->f[i], &tramp->f[i + 1]);
1312 // invalidate the RX mirror (unsure if necessary, but just in case...)
1313 armDCacheFlush(&ndrc->tramp.f[i], sizeof(ndrc->tramp.f[i]));
1316 return &ndrc->tramp.ops[i];
1319 static void emit_far_jump(const void *f)
1321 if (can_jump_or_call(f)) {
1326 f = get_trampoline(f);
1330 static void emit_far_call(const void *f)
1332 if (can_jump_or_call(f)) {
1337 f = get_trampoline(f);
1341 // Check if an address is already compiled
1342 // but don't return addresses which are about to expire from the cache
1343 static void *check_addr(u_int vaddr)
1345 struct ht_entry *ht_bin = hash_table_get(vaddr);
1347 for (i = 0; i < ARRAY_SIZE(ht_bin->vaddr); i++) {
1348 if (ht_bin->vaddr[i] == vaddr)
1349 if (doesnt_expire_soon(ht_bin->tcaddr[i]))
1350 return ht_bin->tcaddr[i];
1353 // refactor to get_addr_nocompile?
1354 u_int start_page = get_page_prev(vaddr);
1355 u_int page, end_page = get_page(vaddr);
1357 stat_inc(stat_jump_in_lookups);
1358 for (page = start_page; page <= end_page; page++) {
1359 const struct block_info *block;
1360 for (block = blocks[page]; block != NULL; block = block->next) {
1361 if (vaddr < block->start)
1363 if (block->is_dirty || vaddr >= block->start + block->len)
1365 if (!doesnt_expire_soon(ndrc->translation_cache + block->tc_offs))
1367 for (i = 0; i < block->jump_in_cnt; i++)
1368 if (block->jump_in[i].vaddr == vaddr)
1370 if (i == block->jump_in_cnt)
1373 // Update existing entry with current address
1374 void *addr = block->jump_in[i].addr;
1375 if (ht_bin->vaddr[0] == vaddr) {
1376 ht_bin->tcaddr[0] = addr;
1379 if (ht_bin->vaddr[1] == vaddr) {
1380 ht_bin->tcaddr[1] = addr;
1383 // Insert into hash table with low priority.
1384 // Don't evict existing entries, as they are probably
1385 // addresses that are being accessed frequently.
1386 if (ht_bin->vaddr[0] == -1) {
1387 ht_bin->vaddr[0] = vaddr;
1388 ht_bin->tcaddr[0] = addr;
1390 else if (ht_bin->vaddr[1] == -1) {
1391 ht_bin->vaddr[1] = vaddr;
1392 ht_bin->tcaddr[1] = addr;
1400 static void blocks_clear(struct block_info **head)
1402 struct block_info *cur, *next;
1404 if ((cur = *head)) {
1414 static int blocks_remove_matching_addrs(struct block_info **head,
1415 u_int base_offs, int shift)
1417 struct block_info *next;
1420 if ((((*head)->tc_offs ^ base_offs) >> shift) == 0) {
1421 inv_debug("EXP: rm block %08x (tc_offs %x)\n", (*head)->start, (*head)->tc_offs);
1422 invalidate_block(*head);
1423 next = (*head)->next;
1426 stat_dec(stat_blocks);
1431 head = &((*head)->next);
1437 // This is called when we write to a compiled block (see do_invstub)
1438 static void unlink_jumps_vaddr_range(u_int start, u_int end)
1440 u_int page, start_page = get_page(start), end_page = get_page(end - 1);
1443 for (page = start_page; page <= end_page; page++) {
1444 struct jump_info *ji = jumps[page];
1447 for (i = 0; i < ji->count; ) {
1448 if (ji->e[i].target_vaddr < start || ji->e[i].target_vaddr >= end) {
1453 inv_debug("INV: rm link to %08x (tc_offs %zx)\n", ji->e[i].target_vaddr,
1454 (u_char *)ji->e[i].stub - ndrc->translation_cache);
1455 void *host_addr = find_extjump_insn(ji->e[i].stub);
1456 mark_clear_cache(host_addr);
1457 set_jump_target(host_addr, ji->e[i].stub); // point back to dyna_linker stub
1459 stat_dec(stat_links);
1461 if (i < ji->count) {
1462 ji->e[i] = ji->e[ji->count];
1470 static void unlink_jumps_tc_range(struct jump_info *ji, u_int base_offs, int shift)
1475 for (i = 0; i < ji->count; ) {
1476 u_int tc_offs = (u_char *)ji->e[i].stub - ndrc->translation_cache;
1477 if (((tc_offs ^ base_offs) >> shift) != 0) {
1482 inv_debug("EXP: rm link to %08x (tc_offs %x)\n", ji->e[i].target_vaddr, tc_offs);
1483 stat_dec(stat_links);
1485 if (i < ji->count) {
1486 ji->e[i] = ji->e[ji->count];
1493 static void invalidate_block(struct block_info *block)
1497 block->is_dirty = 1;
1498 unlink_jumps_vaddr_range(block->start, block->start + block->len);
1499 for (i = 0; i < block->jump_in_cnt; i++)
1500 hash_table_remove(block->jump_in[i].vaddr);
1503 static int invalidate_range(u_int start, u_int end,
1504 u32 *inv_start_ret, u32 *inv_end_ret)
1506 struct block_info *last_block = NULL;
1507 u_int start_page = get_page_prev(start);
1508 u_int end_page = get_page(end - 1);
1509 u_int start_m = pmmask(start);
1510 u_int end_m = pmmask(end - 1);
1511 u_int inv_start, inv_end;
1512 u_int blk_start_m, blk_end_m;
1516 // additional area without code (to supplement invalid_code[]), [start, end)
1517 // avoids excessive ndrc_write_invalidate*() calls
1518 inv_start = start_m & ~0xfff;
1519 inv_end = end_m | 0xfff;
1521 for (page = start_page; page <= end_page; page++) {
1522 struct block_info *block;
1523 for (block = blocks[page]; block != NULL; block = block->next) {
1524 if (block->is_dirty)
1527 blk_end_m = pmmask(block->start + block->len);
1528 if (blk_end_m <= start_m) {
1529 inv_start = max(inv_start, blk_end_m);
1532 blk_start_m = pmmask(block->start);
1533 if (end_m <= blk_start_m) {
1534 inv_end = min(inv_end, blk_start_m - 1);
1537 if (!block->source) // "hack" block - leave it alone
1541 invalidate_block(block);
1542 stat_inc(stat_inv_hits);
1546 if (!hit && last_block && last_block->source) {
1547 // could be some leftover unused block, uselessly trapping writes
1548 last_block->inv_near_misses++;
1549 if (last_block->inv_near_misses > 128) {
1550 invalidate_block(last_block);
1551 stat_inc(stat_inv_hits);
1558 memset(mini_ht, -1, sizeof(mini_ht));
1562 if (inv_start <= (start_m & ~0xfff) && inv_end >= (start_m | 0xfff))
1563 // the whole page is empty now
1564 mark_invalid_code(start, 1, 1);
1566 if (inv_start_ret) *inv_start_ret = inv_start | (start & 0xe0000000);
1567 if (inv_end_ret) *inv_end_ret = inv_end | (end & 0xe0000000);
1571 void new_dynarec_invalidate_range(unsigned int start, unsigned int end)
1573 invalidate_range(start, end, NULL, NULL);
1576 static void ndrc_write_invalidate_many(u_int start, u_int end)
1578 // this check is done by the caller
1579 //if (inv_code_start<=addr&&addr<=inv_code_end) { rhits++; return; }
1580 int ret = invalidate_range(start, end, &inv_code_start, &inv_code_end);
1582 int invc = invalid_code[start >> 12];
1583 u_int len = end - start;
1585 printf("INV ADDR: %08x/%02x hit %d blocks\n", start, len, ret);
1587 printf("INV ADDR: %08x/%02x miss, inv %08x-%08x invc %d->%d\n", start, len,
1588 inv_code_start, inv_code_end, invc, invalid_code[start >> 12]);
1589 check_for_block_changes(start, end);
1591 stat_inc(stat_inv_addr_calls);
1595 void ndrc_write_invalidate_one(u_int addr)
1597 ndrc_write_invalidate_many(addr, addr + 4);
1600 // This is called when loading a save state.
1601 // Anything could have changed, so invalidate everything.
1602 void new_dynarec_invalidate_all_pages(void)
1604 struct block_info *block;
1606 for (page = 0; page < ARRAY_SIZE(blocks); page++) {
1607 for (block = blocks[page]; block != NULL; block = block->next) {
1608 if (block->is_dirty)
1610 if (!block->source) // hack block?
1612 invalidate_block(block);
1617 memset(mini_ht, -1, sizeof(mini_ht));
1622 // Add an entry to jump_out after making a link
1623 // src should point to code by emit_extjump()
1624 void ndrc_add_jump_out(u_int vaddr, void *src)
1626 inv_debug("ndrc_add_jump_out: %p -> %x\n", src, vaddr);
1627 u_int page = get_page(vaddr);
1628 struct jump_info *ji;
1630 stat_inc(stat_links);
1631 check_extjump2(src);
1634 ji = malloc(sizeof(*ji) + sizeof(ji->e[0]) * 16);
1638 else if (ji->count >= ji->alloc) {
1640 ji = realloc(ji, sizeof(*ji) + sizeof(ji->e[0]) * ji->alloc);
1643 ji->e[ji->count].target_vaddr = vaddr;
1644 ji->e[ji->count].stub = src;
1648 /* Register allocation */
1650 // Note: registers are allocated clean (unmodified state)
1651 // if you intend to modify the register, you must call dirty_reg().
1652 static void alloc_reg(struct regstat *cur,int i,signed char reg)
1655 int preferred_reg = PREFERRED_REG_FIRST
1656 + reg % (PREFERRED_REG_LAST - PREFERRED_REG_FIRST + 1);
1657 if (reg == CCREG) preferred_reg = HOST_CCREG;
1658 if (reg == PTEMP || reg == FTEMP) preferred_reg = 12;
1659 assert(PREFERRED_REG_FIRST != EXCLUDE_REG && EXCLUDE_REG != HOST_REGS);
1662 // Don't allocate unused registers
1663 if((cur->u>>reg)&1) return;
1665 // see if it's already allocated
1666 if (get_reg(cur->regmap, reg) >= 0)
1669 // Keep the same mapping if the register was already allocated in a loop
1670 preferred_reg = loop_reg(i,reg,preferred_reg);
1672 // Try to allocate the preferred register
1673 if(cur->regmap[preferred_reg]==-1) {
1674 cur->regmap[preferred_reg]=reg;
1675 cur->dirty&=~(1<<preferred_reg);
1676 cur->isconst&=~(1<<preferred_reg);
1679 r=cur->regmap[preferred_reg];
1682 cur->regmap[preferred_reg]=reg;
1683 cur->dirty&=~(1<<preferred_reg);
1684 cur->isconst&=~(1<<preferred_reg);
1688 // Clear any unneeded registers
1689 // We try to keep the mapping consistent, if possible, because it
1690 // makes branches easier (especially loops). So we try to allocate
1691 // first (see above) before removing old mappings. If this is not
1692 // possible then go ahead and clear out the registers that are no
1694 for(hr=0;hr<HOST_REGS;hr++)
1699 if((cur->u>>r)&1) {cur->regmap[hr]=-1;break;}
1703 // Try to allocate any available register, but prefer
1704 // registers that have not been used recently.
1706 for (hr = PREFERRED_REG_FIRST; ; ) {
1707 if (cur->regmap[hr] < 0) {
1708 int oldreg = regs[i-1].regmap[hr];
1709 if (oldreg < 0 || (oldreg != dops[i-1].rs1 && oldreg != dops[i-1].rs2
1710 && oldreg != dops[i-1].rt1 && oldreg != dops[i-1].rt2))
1712 cur->regmap[hr]=reg;
1713 cur->dirty&=~(1<<hr);
1714 cur->isconst&=~(1<<hr);
1719 if (hr == EXCLUDE_REG)
1721 if (hr == HOST_REGS)
1723 if (hr == PREFERRED_REG_FIRST)
1728 // Try to allocate any available register
1729 for (hr = PREFERRED_REG_FIRST; ; ) {
1730 if (cur->regmap[hr] < 0) {
1731 cur->regmap[hr]=reg;
1732 cur->dirty&=~(1<<hr);
1733 cur->isconst&=~(1<<hr);
1737 if (hr == EXCLUDE_REG)
1739 if (hr == HOST_REGS)
1741 if (hr == PREFERRED_REG_FIRST)
1745 // Ok, now we have to evict someone
1746 // Pick a register we hopefully won't need soon
1747 u_char hsn[MAXREG+1];
1748 memset(hsn,10,sizeof(hsn));
1750 lsn(hsn,i,&preferred_reg);
1751 //printf("eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",cur->regmap[0],cur->regmap[1],cur->regmap[2],cur->regmap[3],cur->regmap[5],cur->regmap[6],cur->regmap[7]);
1752 //printf("hsn(%x): %d %d %d %d %d %d %d\n",start+i*4,hsn[cur->regmap[0]&63],hsn[cur->regmap[1]&63],hsn[cur->regmap[2]&63],hsn[cur->regmap[3]&63],hsn[cur->regmap[5]&63],hsn[cur->regmap[6]&63],hsn[cur->regmap[7]&63]);
1754 // Don't evict the cycle count at entry points, otherwise the entry
1755 // stub will have to write it.
1756 if(dops[i].bt&&hsn[CCREG]>2) hsn[CCREG]=2;
1757 if (i>1 && hsn[CCREG] > 2 && dops[i-2].is_jump) hsn[CCREG]=2;
1760 // Alloc preferred register if available
1761 if(hsn[r=cur->regmap[preferred_reg]&63]==j) {
1762 for(hr=0;hr<HOST_REGS;hr++) {
1763 // Evict both parts of a 64-bit register
1764 if(cur->regmap[hr]==r) {
1766 cur->dirty&=~(1<<hr);
1767 cur->isconst&=~(1<<hr);
1770 cur->regmap[preferred_reg]=reg;
1773 for(r=1;r<=MAXREG;r++)
1775 if(hsn[r]==j&&r!=dops[i-1].rs1&&r!=dops[i-1].rs2&&r!=dops[i-1].rt1&&r!=dops[i-1].rt2) {
1776 for(hr=0;hr<HOST_REGS;hr++) {
1777 if(hr!=HOST_CCREG||j<hsn[CCREG]) {
1778 if(cur->regmap[hr]==r) {
1779 cur->regmap[hr]=reg;
1780 cur->dirty&=~(1<<hr);
1781 cur->isconst&=~(1<<hr);
1792 for(r=1;r<=MAXREG;r++)
1795 for(hr=0;hr<HOST_REGS;hr++) {
1796 if(cur->regmap[hr]==r) {
1797 cur->regmap[hr]=reg;
1798 cur->dirty&=~(1<<hr);
1799 cur->isconst&=~(1<<hr);
1806 SysPrintf("This shouldn't happen (alloc_reg)");abort();
1809 // Allocate a temporary register. This is done without regard to
1810 // dirty status or whether the register we request is on the unneeded list
1811 // Note: This will only allocate one register, even if called multiple times
1812 static void alloc_reg_temp(struct regstat *cur,int i,signed char reg)
1815 int preferred_reg = -1;
1817 // see if it's already allocated
1818 for(hr=0;hr<HOST_REGS;hr++)
1820 if(hr!=EXCLUDE_REG&&cur->regmap[hr]==reg) return;
1823 // Try to allocate any available register
1824 for(hr=HOST_REGS-1;hr>=0;hr--) {
1825 if(hr!=EXCLUDE_REG&&cur->regmap[hr]==-1) {
1826 cur->regmap[hr]=reg;
1827 cur->dirty&=~(1<<hr);
1828 cur->isconst&=~(1<<hr);
1833 // Find an unneeded register
1834 for(hr=HOST_REGS-1;hr>=0;hr--)
1840 if(i==0||((unneeded_reg[i-1]>>r)&1)) {
1841 cur->regmap[hr]=reg;
1842 cur->dirty&=~(1<<hr);
1843 cur->isconst&=~(1<<hr);
1850 // Ok, now we have to evict someone
1851 // Pick a register we hopefully won't need soon
1852 // TODO: we might want to follow unconditional jumps here
1853 // TODO: get rid of dupe code and make this into a function
1854 u_char hsn[MAXREG+1];
1855 memset(hsn,10,sizeof(hsn));
1857 lsn(hsn,i,&preferred_reg);
1858 //printf("hsn: %d %d %d %d %d %d %d\n",hsn[cur->regmap[0]&63],hsn[cur->regmap[1]&63],hsn[cur->regmap[2]&63],hsn[cur->regmap[3]&63],hsn[cur->regmap[5]&63],hsn[cur->regmap[6]&63],hsn[cur->regmap[7]&63]);
1860 // Don't evict the cycle count at entry points, otherwise the entry
1861 // stub will have to write it.
1862 if(dops[i].bt&&hsn[CCREG]>2) hsn[CCREG]=2;
1863 if (i>1 && hsn[CCREG] > 2 && dops[i-2].is_jump) hsn[CCREG]=2;
1866 for(r=1;r<=MAXREG;r++)
1868 if(hsn[r]==j&&r!=dops[i-1].rs1&&r!=dops[i-1].rs2&&r!=dops[i-1].rt1&&r!=dops[i-1].rt2) {
1869 for(hr=0;hr<HOST_REGS;hr++) {
1870 if(hr!=HOST_CCREG||hsn[CCREG]>2) {
1871 if(cur->regmap[hr]==r) {
1872 cur->regmap[hr]=reg;
1873 cur->dirty&=~(1<<hr);
1874 cur->isconst&=~(1<<hr);
1885 for(r=1;r<=MAXREG;r++)
1888 for(hr=0;hr<HOST_REGS;hr++) {
1889 if(cur->regmap[hr]==r) {
1890 cur->regmap[hr]=reg;
1891 cur->dirty&=~(1<<hr);
1892 cur->isconst&=~(1<<hr);
1899 SysPrintf("This shouldn't happen");abort();
1902 static void mov_alloc(struct regstat *current,int i)
1904 if (dops[i].rs1 == HIREG || dops[i].rs1 == LOREG) {
1905 alloc_cc(current,i); // for stalls
1906 dirty_reg(current,CCREG);
1909 // Note: Don't need to actually alloc the source registers
1910 //alloc_reg(current,i,dops[i].rs1);
1911 alloc_reg(current,i,dops[i].rt1);
1913 clear_const(current,dops[i].rs1);
1914 clear_const(current,dops[i].rt1);
1915 dirty_reg(current,dops[i].rt1);
1918 static void shiftimm_alloc(struct regstat *current,int i)
1920 if(dops[i].opcode2<=0x3) // SLL/SRL/SRA
1923 if(dops[i].rs1&&needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1);
1924 else dops[i].use_lt1=!!dops[i].rs1;
1925 alloc_reg(current,i,dops[i].rt1);
1926 dirty_reg(current,dops[i].rt1);
1927 if(is_const(current,dops[i].rs1)) {
1928 int v=get_const(current,dops[i].rs1);
1929 if(dops[i].opcode2==0x00) set_const(current,dops[i].rt1,v<<cinfo[i].imm);
1930 if(dops[i].opcode2==0x02) set_const(current,dops[i].rt1,(u_int)v>>cinfo[i].imm);
1931 if(dops[i].opcode2==0x03) set_const(current,dops[i].rt1,v>>cinfo[i].imm);
1933 else clear_const(current,dops[i].rt1);
1938 clear_const(current,dops[i].rs1);
1939 clear_const(current,dops[i].rt1);
1942 if(dops[i].opcode2>=0x38&&dops[i].opcode2<=0x3b) // DSLL/DSRL/DSRA
1946 if(dops[i].opcode2==0x3c) // DSLL32
1950 if(dops[i].opcode2==0x3e) // DSRL32
1954 if(dops[i].opcode2==0x3f) // DSRA32
1960 static void shift_alloc(struct regstat *current,int i)
1963 if(dops[i].opcode2<=0x07) // SLLV/SRLV/SRAV
1965 if(dops[i].rs1) alloc_reg(current,i,dops[i].rs1);
1966 if(dops[i].rs2) alloc_reg(current,i,dops[i].rs2);
1967 alloc_reg(current,i,dops[i].rt1);
1968 if(dops[i].rt1==dops[i].rs2) {
1969 alloc_reg_temp(current,i,-1);
1970 cinfo[i].min_free_regs=1;
1972 } else { // DSLLV/DSRLV/DSRAV
1975 clear_const(current,dops[i].rs1);
1976 clear_const(current,dops[i].rs2);
1977 clear_const(current,dops[i].rt1);
1978 dirty_reg(current,dops[i].rt1);
1982 static void alu_alloc(struct regstat *current,int i)
1984 if(dops[i].opcode2>=0x20&&dops[i].opcode2<=0x23) { // ADD/ADDU/SUB/SUBU
1986 if(dops[i].rs1&&dops[i].rs2) {
1987 alloc_reg(current,i,dops[i].rs1);
1988 alloc_reg(current,i,dops[i].rs2);
1991 if(dops[i].rs1&&needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1);
1992 if(dops[i].rs2&&needed_again(dops[i].rs2,i)) alloc_reg(current,i,dops[i].rs2);
1994 alloc_reg(current,i,dops[i].rt1);
1996 if (dops[i].may_except) {
1997 alloc_cc(current, i); // for exceptions
1998 alloc_reg_temp(current, i, -1);
1999 cinfo[i].min_free_regs = 1;
2002 else if(dops[i].opcode2==0x2a||dops[i].opcode2==0x2b) { // SLT/SLTU
2004 alloc_reg(current,i,dops[i].rs1);
2005 alloc_reg(current,i,dops[i].rs2);
2006 alloc_reg(current,i,dops[i].rt1);
2009 else if(dops[i].opcode2>=0x24&&dops[i].opcode2<=0x27) { // AND/OR/XOR/NOR
2011 if(dops[i].rs1&&dops[i].rs2) {
2012 alloc_reg(current,i,dops[i].rs1);
2013 alloc_reg(current,i,dops[i].rs2);
2017 if(dops[i].rs1&&needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1);
2018 if(dops[i].rs2&&needed_again(dops[i].rs2,i)) alloc_reg(current,i,dops[i].rs2);
2020 alloc_reg(current,i,dops[i].rt1);
2023 clear_const(current,dops[i].rs1);
2024 clear_const(current,dops[i].rs2);
2025 clear_const(current,dops[i].rt1);
2026 dirty_reg(current,dops[i].rt1);
2029 static void imm16_alloc(struct regstat *current,int i)
2031 if(dops[i].rs1&&needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1);
2032 else dops[i].use_lt1=!!dops[i].rs1;
2033 if(dops[i].rt1) alloc_reg(current,i,dops[i].rt1);
2034 if(dops[i].opcode==0x0a||dops[i].opcode==0x0b) { // SLTI/SLTIU
2035 clear_const(current,dops[i].rs1);
2036 clear_const(current,dops[i].rt1);
2038 else if(dops[i].opcode>=0x0c&&dops[i].opcode<=0x0e) { // ANDI/ORI/XORI
2039 if(is_const(current,dops[i].rs1)) {
2040 int v=get_const(current,dops[i].rs1);
2041 if(dops[i].opcode==0x0c) set_const(current,dops[i].rt1,v&cinfo[i].imm);
2042 if(dops[i].opcode==0x0d) set_const(current,dops[i].rt1,v|cinfo[i].imm);
2043 if(dops[i].opcode==0x0e) set_const(current,dops[i].rt1,v^cinfo[i].imm);
2045 else clear_const(current,dops[i].rt1);
2047 else if(dops[i].opcode==0x08||dops[i].opcode==0x09) { // ADDI/ADDIU
2048 if(is_const(current,dops[i].rs1)) {
2049 int v=get_const(current,dops[i].rs1);
2050 set_const(current,dops[i].rt1,v+cinfo[i].imm);
2052 else clear_const(current,dops[i].rt1);
2053 if (dops[i].may_except) {
2054 alloc_cc(current, i); // for exceptions
2055 alloc_reg_temp(current, i, -1);
2056 cinfo[i].min_free_regs = 1;
2060 set_const(current,dops[i].rt1,cinfo[i].imm<<16); // LUI
2062 dirty_reg(current,dops[i].rt1);
2065 static void load_alloc(struct regstat *current,int i)
2068 clear_const(current,dops[i].rt1);
2069 //if(dops[i].rs1!=dops[i].rt1&&needed_again(dops[i].rs1,i)) clear_const(current,dops[i].rs1); // Does this help or hurt?
2070 if(!dops[i].rs1) current->u&=~1LL; // Allow allocating r0 if it's the source register
2071 if (needed_again(dops[i].rs1, i))
2072 alloc_reg(current, i, dops[i].rs1);
2074 alloc_reg(current, i, ROREG);
2075 if (dops[i].may_except) {
2076 alloc_cc(current, i); // for exceptions
2077 dirty_reg(current, CCREG);
2080 if(dops[i].rt1&&!((current->u>>dops[i].rt1)&1)) {
2081 alloc_reg(current,i,dops[i].rt1);
2082 assert(get_reg_w(current->regmap, dops[i].rt1)>=0);
2083 dirty_reg(current,dops[i].rt1);
2084 // LWL/LWR need a temporary register for the old value
2085 if(dops[i].opcode==0x22||dops[i].opcode==0x26)
2087 alloc_reg(current,i,FTEMP);
2093 // Load to r0 or unneeded register (dummy load)
2094 // but we still need a register to calculate the address
2095 if(dops[i].opcode==0x22||dops[i].opcode==0x26)
2096 alloc_reg(current,i,FTEMP); // LWL/LWR need another temporary
2100 alloc_reg_temp(current, i, -1);
2101 cinfo[i].min_free_regs = 1;
2105 static void store_alloc(struct regstat *current,int i)
2107 clear_const(current,dops[i].rs2);
2108 if(!(dops[i].rs2)) current->u&=~1LL; // Allow allocating r0 if necessary
2109 if(needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1);
2110 alloc_reg(current,i,dops[i].rs2);
2112 alloc_reg(current, i, ROREG);
2113 #if defined(HOST_IMM8)
2114 // On CPUs without 32-bit immediates we need a pointer to invalid_code
2115 alloc_reg(current, i, INVCP);
2117 if (dops[i].opcode == 0x2a || dops[i].opcode == 0x2e) { // SWL/SWL
2118 alloc_reg(current,i,FTEMP);
2120 if (dops[i].may_except) {
2121 alloc_cc(current, i); // for exceptions
2122 dirty_reg(current, CCREG);
2124 // We need a temporary register for address generation
2125 alloc_reg_temp(current,i,-1);
2126 cinfo[i].min_free_regs=1;
2129 static void c2ls_alloc(struct regstat *current,int i)
2131 clear_const(current,dops[i].rt1);
2132 if(needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1);
2133 alloc_reg(current,i,FTEMP);
2135 alloc_reg(current, i, ROREG);
2136 #if defined(HOST_IMM8)
2137 // On CPUs without 32-bit immediates we need a pointer to invalid_code
2138 if (dops[i].opcode == 0x3a) // SWC2
2139 alloc_reg(current,i,INVCP);
2141 if (dops[i].may_except) {
2142 alloc_cc(current, i); // for exceptions
2143 dirty_reg(current, CCREG);
2145 // We need a temporary register for address generation
2146 alloc_reg_temp(current,i,-1);
2147 cinfo[i].min_free_regs=1;
2150 #ifndef multdiv_alloc
2151 static void multdiv_alloc(struct regstat *current,int i)
2158 // case 0x1D: DMULTU
2161 clear_const(current,dops[i].rs1);
2162 clear_const(current,dops[i].rs2);
2163 alloc_cc(current,i); // for stalls
2164 if(dops[i].rs1&&dops[i].rs2)
2166 if((dops[i].opcode2&4)==0) // 32-bit
2168 current->u&=~(1LL<<HIREG);
2169 current->u&=~(1LL<<LOREG);
2170 alloc_reg(current,i,HIREG);
2171 alloc_reg(current,i,LOREG);
2172 alloc_reg(current,i,dops[i].rs1);
2173 alloc_reg(current,i,dops[i].rs2);
2174 dirty_reg(current,HIREG);
2175 dirty_reg(current,LOREG);
2184 // Multiply by zero is zero.
2185 // MIPS does not have a divide by zero exception.
2186 // The result is undefined, we return zero.
2187 alloc_reg(current,i,HIREG);
2188 alloc_reg(current,i,LOREG);
2189 dirty_reg(current,HIREG);
2190 dirty_reg(current,LOREG);
2195 static void cop0_alloc(struct regstat *current,int i)
2197 if(dops[i].opcode2==0) // MFC0
2200 clear_const(current,dops[i].rt1);
2201 alloc_reg(current,i,dops[i].rt1);
2202 dirty_reg(current,dops[i].rt1);
2205 else if(dops[i].opcode2==4) // MTC0
2208 clear_const(current,dops[i].rs1);
2209 alloc_reg(current,i,dops[i].rs1);
2210 alloc_all(current,i);
2213 alloc_all(current,i); // FIXME: Keep r0
2215 alloc_reg(current,i,0);
2217 cinfo[i].min_free_regs = HOST_REGS;
2221 static void rfe_alloc(struct regstat *current, int i)
2223 alloc_all(current, i);
2224 cinfo[i].min_free_regs = HOST_REGS;
2227 static void cop2_alloc(struct regstat *current,int i)
2229 if (dops[i].opcode2 < 3) // MFC2/CFC2
2231 alloc_cc(current,i); // for stalls
2232 dirty_reg(current,CCREG);
2234 clear_const(current,dops[i].rt1);
2235 alloc_reg(current,i,dops[i].rt1);
2236 dirty_reg(current,dops[i].rt1);
2239 else if (dops[i].opcode2 > 3) // MTC2/CTC2
2242 clear_const(current,dops[i].rs1);
2243 alloc_reg(current,i,dops[i].rs1);
2247 alloc_reg(current,i,0);
2250 alloc_reg_temp(current,i,-1);
2251 cinfo[i].min_free_regs=1;
2254 static void c2op_alloc(struct regstat *current,int i)
2256 alloc_cc(current,i); // for stalls
2257 dirty_reg(current,CCREG);
2258 alloc_reg_temp(current,i,-1);
2261 static void syscall_alloc(struct regstat *current,int i)
2263 alloc_cc(current,i);
2264 dirty_reg(current,CCREG);
2265 alloc_all(current,i);
2266 cinfo[i].min_free_regs=HOST_REGS;
2270 static void delayslot_alloc(struct regstat *current,int i)
2272 switch(dops[i].itype) {
2280 imm16_alloc(current,i);
2284 load_alloc(current,i);
2288 store_alloc(current,i);
2291 alu_alloc(current,i);
2294 shift_alloc(current,i);
2297 multdiv_alloc(current,i);
2300 shiftimm_alloc(current,i);
2303 mov_alloc(current,i);
2306 cop0_alloc(current,i);
2309 rfe_alloc(current,i);
2312 cop2_alloc(current,i);
2315 c2ls_alloc(current,i);
2318 c2op_alloc(current,i);
2323 static void add_stub(enum stub_type type, void *addr, void *retaddr,
2324 u_int a, uintptr_t b, uintptr_t c, u_int d, u_int e)
2326 assert(stubcount < ARRAY_SIZE(stubs));
2327 stubs[stubcount].type = type;
2328 stubs[stubcount].addr = addr;
2329 stubs[stubcount].retaddr = retaddr;
2330 stubs[stubcount].a = a;
2331 stubs[stubcount].b = b;
2332 stubs[stubcount].c = c;
2333 stubs[stubcount].d = d;
2334 stubs[stubcount].e = e;
2338 static void add_stub_r(enum stub_type type, void *addr, void *retaddr,
2339 int i, int addr_reg, const struct regstat *i_regs, int ccadj, u_int reglist)
2341 add_stub(type, addr, retaddr, i, addr_reg, (uintptr_t)i_regs, ccadj, reglist);
2344 // Write out a single register
2345 static void wb_register(signed char r, const signed char regmap[], uint64_t dirty)
2348 for(hr=0;hr<HOST_REGS;hr++) {
2349 if(hr!=EXCLUDE_REG) {
2352 assert(regmap[hr]<64);
2353 emit_storereg(r,hr);
2360 static void wb_valid(signed char pre[],signed char entry[],u_int dirty_pre,u_int dirty,uint64_t u)
2362 //if(dirty_pre==dirty) return;
2364 for (hr = 0; hr < HOST_REGS; hr++) {
2366 if (r < 1 || r > 33 || ((u >> r) & 1))
2368 if (((dirty_pre & ~dirty) >> hr) & 1)
2369 emit_storereg(r, hr);
2374 static void pass_args(int a0, int a1)
2378 emit_mov(a0,2); emit_mov(a1,1); emit_mov(2,0);
2380 else if(a0!=0&&a1==0) {
2382 if (a0>=0) emit_mov(a0,0);
2385 if(a0>=0&&a0!=0) emit_mov(a0,0);
2386 if(a1>=0&&a1!=1) emit_mov(a1,1);
2390 static void alu_assemble(int i, const struct regstat *i_regs, int ccadj_)
2392 if(dops[i].opcode2>=0x20&&dops[i].opcode2<=0x23) { // ADD/ADDU/SUB/SUBU
2393 int do_oflow = dops[i].may_except; // ADD/SUB with exceptions enabled
2394 if (dops[i].rt1 || do_oflow) {
2395 int do_exception_check = 0;
2396 signed char s1, s2, t, tmp;
2397 t = get_reg_w(i_regs->regmap, dops[i].rt1);
2398 tmp = get_reg_temp(i_regs->regmap);
2401 //if (t < 0 && do_oflow) // broken s2
2404 s1 = get_reg(i_regs->regmap, dops[i].rs1);
2405 s2 = get_reg(i_regs->regmap, dops[i].rs2);
2406 if (dops[i].rs1 && dops[i].rs2) {
2409 if (dops[i].opcode2 & 2) {
2411 emit_subs(s1, s2, tmp);
2412 do_exception_check = 1;
2419 emit_adds(s1, s2, tmp);
2420 do_exception_check = 1;
2426 else if(dops[i].rs1) {
2427 if(s1>=0) emit_mov(s1,t);
2428 else emit_loadreg(dops[i].rs1,t);
2430 else if(dops[i].rs2) {
2432 emit_loadreg(dops[i].rs2, t);
2435 if (dops[i].opcode2 & 2) {
2438 do_exception_check = 1;
2449 if (do_exception_check) {
2452 if (t >= 0 && tmp != t)
2454 add_stub_r(OVERFLOW_STUB, jaddr, out, i, 0, i_regs, ccadj_, 0);
2458 else if(dops[i].opcode2==0x2a||dops[i].opcode2==0x2b) { // SLT/SLTU
2460 signed char s1l,s2l,t;
2462 t=get_reg_w(i_regs->regmap, dops[i].rt1);
2465 s1l=get_reg(i_regs->regmap,dops[i].rs1);
2466 s2l=get_reg(i_regs->regmap,dops[i].rs2);
2467 if(dops[i].rs2==0) // rx<r0
2469 if(dops[i].opcode2==0x2a&&dops[i].rs1!=0) { // SLT
2471 emit_shrimm(s1l,31,t);
2473 else // SLTU (unsigned can not be less than zero, 0<0)
2476 else if(dops[i].rs1==0) // r0<rx
2479 if(dops[i].opcode2==0x2a) // SLT
2480 emit_set_gz32(s2l,t);
2481 else // SLTU (set if not zero)
2482 emit_set_nz32(s2l,t);
2485 assert(s1l>=0);assert(s2l>=0);
2486 if(dops[i].opcode2==0x2a) // SLT
2487 emit_set_if_less32(s1l,s2l,t);
2489 emit_set_if_carry32(s1l,s2l,t);
2495 else if(dops[i].opcode2>=0x24&&dops[i].opcode2<=0x27) { // AND/OR/XOR/NOR
2497 signed char s1l,s2l,tl;
2498 tl=get_reg_w(i_regs->regmap, dops[i].rt1);
2501 s1l=get_reg(i_regs->regmap,dops[i].rs1);
2502 s2l=get_reg(i_regs->regmap,dops[i].rs2);
2503 if(dops[i].rs1&&dops[i].rs2) {
2506 if(dops[i].opcode2==0x24) { // AND
2507 emit_and(s1l,s2l,tl);
2509 if(dops[i].opcode2==0x25) { // OR
2510 emit_or(s1l,s2l,tl);
2512 if(dops[i].opcode2==0x26) { // XOR
2513 emit_xor(s1l,s2l,tl);
2515 if(dops[i].opcode2==0x27) { // NOR
2516 emit_or(s1l,s2l,tl);
2522 if(dops[i].opcode2==0x24) { // AND
2525 if(dops[i].opcode2==0x25||dops[i].opcode2==0x26) { // OR/XOR
2527 if(s1l>=0) emit_mov(s1l,tl);
2528 else emit_loadreg(dops[i].rs1,tl); // CHECK: regmap_entry?
2532 if(s2l>=0) emit_mov(s2l,tl);
2533 else emit_loadreg(dops[i].rs2,tl); // CHECK: regmap_entry?
2535 else emit_zeroreg(tl);
2537 if(dops[i].opcode2==0x27) { // NOR
2539 if(s1l>=0) emit_not(s1l,tl);
2541 emit_loadreg(dops[i].rs1,tl);
2547 if(s2l>=0) emit_not(s2l,tl);
2549 emit_loadreg(dops[i].rs2,tl);
2553 else emit_movimm(-1,tl);
2562 static void imm16_assemble(int i, const struct regstat *i_regs, int ccadj_)
2564 if (dops[i].opcode==0x0f) { // LUI
2567 t=get_reg_w(i_regs->regmap, dops[i].rt1);
2570 if(!((i_regs->isconst>>t)&1))
2571 emit_movimm(cinfo[i].imm<<16,t);
2575 if(dops[i].opcode==0x08||dops[i].opcode==0x09) { // ADDI/ADDIU
2576 int is_addi = dops[i].may_except;
2577 if (dops[i].rt1 || is_addi) {
2578 signed char s, t, tmp;
2579 t=get_reg_w(i_regs->regmap, dops[i].rt1);
2580 s=get_reg(i_regs->regmap,dops[i].rs1);
2582 tmp = get_reg_temp(i_regs->regmap);
2588 if(!((i_regs->isconst>>t)&1)) {
2589 int sum, do_exception_check = 0;
2591 if(i_regs->regmap_entry[t]!=dops[i].rs1) emit_loadreg(dops[i].rs1,t);
2593 emit_addimm_and_set_flags3(t, cinfo[i].imm, tmp);
2594 do_exception_check = 1;
2597 emit_addimm(t, cinfo[i].imm, t);
2599 if (!((i_regs->wasconst >> s) & 1)) {
2601 emit_addimm_and_set_flags3(s, cinfo[i].imm, tmp);
2602 do_exception_check = 1;
2605 emit_addimm(s, cinfo[i].imm, t);
2608 int oflow = add_overflow(constmap[i][s], cinfo[i].imm, sum);
2609 if (is_addi && oflow)
2610 do_exception_check = 2;
2612 emit_movimm(sum, t);
2615 if (do_exception_check) {
2617 if (do_exception_check == 2)
2624 add_stub_r(OVERFLOW_STUB, jaddr, out, i, 0, i_regs, ccadj_, 0);
2630 if(!((i_regs->isconst>>t)&1))
2631 emit_movimm(cinfo[i].imm,t);
2636 else if(dops[i].opcode==0x0a||dops[i].opcode==0x0b) { // SLTI/SLTIU
2638 //assert(dops[i].rs1!=0); // r0 might be valid, but it's probably a bug
2640 t=get_reg_w(i_regs->regmap, dops[i].rt1);
2641 sl=get_reg(i_regs->regmap,dops[i].rs1);
2645 if(dops[i].opcode==0x0a) { // SLTI
2647 if(i_regs->regmap_entry[t]!=dops[i].rs1) emit_loadreg(dops[i].rs1,t);
2648 emit_slti32(t,cinfo[i].imm,t);
2650 emit_slti32(sl,cinfo[i].imm,t);
2655 if(i_regs->regmap_entry[t]!=dops[i].rs1) emit_loadreg(dops[i].rs1,t);
2656 emit_sltiu32(t,cinfo[i].imm,t);
2658 emit_sltiu32(sl,cinfo[i].imm,t);
2662 // SLTI(U) with r0 is just stupid,
2663 // nonetheless examples can be found
2664 if(dops[i].opcode==0x0a) // SLTI
2665 if(0<cinfo[i].imm) emit_movimm(1,t);
2666 else emit_zeroreg(t);
2669 if(cinfo[i].imm) emit_movimm(1,t);
2670 else emit_zeroreg(t);
2676 else if(dops[i].opcode>=0x0c&&dops[i].opcode<=0x0e) { // ANDI/ORI/XORI
2679 tl=get_reg_w(i_regs->regmap, dops[i].rt1);
2680 sl=get_reg(i_regs->regmap,dops[i].rs1);
2681 if(tl>=0 && !((i_regs->isconst>>tl)&1)) {
2682 if(dops[i].opcode==0x0c) //ANDI
2686 if(i_regs->regmap_entry[tl]!=dops[i].rs1) emit_loadreg(dops[i].rs1,tl);
2687 emit_andimm(tl,cinfo[i].imm,tl);
2689 if(!((i_regs->wasconst>>sl)&1))
2690 emit_andimm(sl,cinfo[i].imm,tl);
2692 emit_movimm(constmap[i][sl]&cinfo[i].imm,tl);
2702 if(i_regs->regmap_entry[tl]!=dops[i].rs1) emit_loadreg(dops[i].rs1,tl);
2704 if(dops[i].opcode==0x0d) { // ORI
2706 emit_orimm(tl,cinfo[i].imm,tl);
2708 if(!((i_regs->wasconst>>sl)&1))
2709 emit_orimm(sl,cinfo[i].imm,tl);
2711 emit_movimm(constmap[i][sl]|cinfo[i].imm,tl);
2714 if(dops[i].opcode==0x0e) { // XORI
2716 emit_xorimm(tl,cinfo[i].imm,tl);
2718 if(!((i_regs->wasconst>>sl)&1))
2719 emit_xorimm(sl,cinfo[i].imm,tl);
2721 emit_movimm(constmap[i][sl]^cinfo[i].imm,tl);
2726 emit_movimm(cinfo[i].imm,tl);
2734 static void shiftimm_assemble(int i, const struct regstat *i_regs)
2736 if(dops[i].opcode2<=0x3) // SLL/SRL/SRA
2740 t=get_reg_w(i_regs->regmap, dops[i].rt1);
2741 s=get_reg(i_regs->regmap,dops[i].rs1);
2743 if(t>=0&&!((i_regs->isconst>>t)&1)){
2750 if(s<0&&i_regs->regmap_entry[t]!=dops[i].rs1) emit_loadreg(dops[i].rs1,t);
2752 if(dops[i].opcode2==0) // SLL
2754 emit_shlimm(s<0?t:s,cinfo[i].imm,t);
2756 if(dops[i].opcode2==2) // SRL
2758 emit_shrimm(s<0?t:s,cinfo[i].imm,t);
2760 if(dops[i].opcode2==3) // SRA
2762 emit_sarimm(s<0?t:s,cinfo[i].imm,t);
2766 if(s>=0 && s!=t) emit_mov(s,t);
2770 //emit_storereg(dops[i].rt1,t); //DEBUG
2773 if(dops[i].opcode2>=0x38&&dops[i].opcode2<=0x3b) // DSLL/DSRL/DSRA
2777 if(dops[i].opcode2==0x3c) // DSLL32
2781 if(dops[i].opcode2==0x3e) // DSRL32
2785 if(dops[i].opcode2==0x3f) // DSRA32
2791 #ifndef shift_assemble
2792 static void shift_assemble(int i, const struct regstat *i_regs)
2794 signed char s,t,shift;
2795 if (dops[i].rt1 == 0)
2797 assert(dops[i].opcode2<=0x07); // SLLV/SRLV/SRAV
2798 t = get_reg(i_regs->regmap, dops[i].rt1);
2799 s = get_reg(i_regs->regmap, dops[i].rs1);
2800 shift = get_reg(i_regs->regmap, dops[i].rs2);
2806 else if(dops[i].rs2==0) {
2808 if(s!=t) emit_mov(s,t);
2811 host_tempreg_acquire();
2812 emit_andimm(shift,31,HOST_TEMPREG);
2813 switch(dops[i].opcode2) {
2815 emit_shl(s,HOST_TEMPREG,t);
2818 emit_shr(s,HOST_TEMPREG,t);
2821 emit_sar(s,HOST_TEMPREG,t);
2826 host_tempreg_release();
2840 static int get_ptr_mem_type(u_int a)
2842 if(a < 0x00200000) {
2843 if(a<0x1000&&((start>>20)==0xbfc||(start>>24)==0xa0))
2844 // return wrong, must use memhandler for BIOS self-test to pass
2845 // 007 does similar stuff from a00 mirror, weird stuff
2849 if(0x1f800000 <= a && a < 0x1f801000)
2851 if(0x80200000 <= a && a < 0x80800000)
2853 if(0xa0000000 <= a && a < 0xa0200000)
2858 static int get_ro_reg(const struct regstat *i_regs, int host_tempreg_free)
2860 int r = get_reg(i_regs->regmap, ROREG);
2861 if (r < 0 && host_tempreg_free) {
2862 host_tempreg_acquire();
2863 emit_loadreg(ROREG, r = HOST_TEMPREG);
2870 static void *emit_fastpath_cmp_jump(int i, const struct regstat *i_regs,
2871 int addr, int *offset_reg, int *addr_reg_override, int ccadj_)
2875 int mr = dops[i].rs1;
2878 if(((smrv_strong|smrv_weak)>>mr)&1) {
2879 type=get_ptr_mem_type(smrv[mr]);
2880 //printf("set %08x @%08x r%d %d\n", smrv[mr], start+i*4, mr, type);
2883 // use the mirror we are running on
2884 type=get_ptr_mem_type(start);
2885 //printf("set nospec @%08x r%d %d\n", start+i*4, mr, type);
2888 if (dops[i].may_except) {
2890 u_int op = dops[i].opcode;
2891 int mask = ((op & 0x37) == 0x21 || op == 0x25) ? 1 : 3; // LH/SH/LHU
2893 emit_testimm(addr, mask);
2896 add_stub_r(ALIGNMENT_STUB, jaddr, out, i, addr, i_regs, ccadj_, 0);
2899 if(type==MTYPE_8020) { // RAM 80200000+ mirror
2900 host_tempreg_acquire();
2901 emit_andimm(addr,~0x00e00000,HOST_TEMPREG);
2902 addr=*addr_reg_override=HOST_TEMPREG;
2905 else if(type==MTYPE_0000) { // RAM 0 mirror
2906 host_tempreg_acquire();
2907 emit_orimm(addr,0x80000000,HOST_TEMPREG);
2908 addr=*addr_reg_override=HOST_TEMPREG;
2911 else if(type==MTYPE_A000) { // RAM A mirror
2912 host_tempreg_acquire();
2913 emit_andimm(addr,~0x20000000,HOST_TEMPREG);
2914 addr=*addr_reg_override=HOST_TEMPREG;
2917 else if(type==MTYPE_1F80) { // scratchpad
2918 if (psxH == (void *)0x1f800000) {
2919 host_tempreg_acquire();
2920 emit_xorimm(addr,0x1f800000,HOST_TEMPREG);
2921 emit_cmpimm(HOST_TEMPREG,0x1000);
2922 host_tempreg_release();
2927 // do the usual RAM check, jump will go to the right handler
2932 if (type == 0) // need ram check
2934 emit_cmpimm(addr,RAM_SIZE);
2936 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
2937 // Hint to branch predictor that the branch is unlikely to be taken
2938 if (dops[i].rs1 >= 28)
2939 emit_jno_unlikely(0);
2943 if (ram_offset != 0)
2944 *offset_reg = get_ro_reg(i_regs, 0);
2950 // return memhandler, or get directly accessable address and return 0
2951 static void *get_direct_memhandler(void *table, u_int addr,
2952 enum stub_type type, uintptr_t *addr_host)
2954 uintptr_t msb = 1ull << (sizeof(uintptr_t)*8 - 1);
2955 uintptr_t l1, l2 = 0;
2956 l1 = ((uintptr_t *)table)[addr>>12];
2958 uintptr_t v = l1 << 1;
2959 *addr_host = v + addr;
2964 if (type == LOADB_STUB || type == LOADBU_STUB || type == STOREB_STUB)
2965 l2 = ((uintptr_t *)l1)[0x1000/4 + 0x1000/2 + (addr&0xfff)];
2966 else if (type == LOADH_STUB || type == LOADHU_STUB || type == STOREH_STUB)
2967 l2 = ((uintptr_t *)l1)[0x1000/4 + (addr&0xfff)/2];
2969 l2 = ((uintptr_t *)l1)[(addr&0xfff)/4];
2971 uintptr_t v = l2 << 1;
2972 *addr_host = v + (addr&0xfff);
2975 return (void *)(l2 << 1);
2979 static u_int get_host_reglist(const signed char *regmap)
2981 u_int reglist = 0, hr;
2982 for (hr = 0; hr < HOST_REGS; hr++) {
2983 if (hr != EXCLUDE_REG && regmap[hr] >= 0)
2989 static u_int reglist_exclude(u_int reglist, int r1, int r2)
2992 reglist &= ~(1u << r1);
2994 reglist &= ~(1u << r2);
2998 // find a temp caller-saved register not in reglist (so assumed to be free)
2999 static int reglist_find_free(u_int reglist)
3001 u_int free_regs = ~reglist & CALLER_SAVE_REGS;
3004 return __builtin_ctz(free_regs);
3007 static void do_load_word(int a, int rt, int offset_reg)
3009 if (offset_reg >= 0)
3010 emit_ldr_dualindexed(offset_reg, a, rt);
3012 emit_readword_indexed(0, a, rt);
3015 static void do_store_word(int a, int ofs, int rt, int offset_reg, int preseve_a)
3017 if (offset_reg < 0) {
3018 emit_writeword_indexed(rt, ofs, a);
3022 emit_addimm(a, ofs, a);
3023 emit_str_dualindexed(offset_reg, a, rt);
3024 if (ofs != 0 && preseve_a)
3025 emit_addimm(a, -ofs, a);
3028 static void do_store_hword(int a, int ofs, int rt, int offset_reg, int preseve_a)
3030 if (offset_reg < 0) {
3031 emit_writehword_indexed(rt, ofs, a);
3035 emit_addimm(a, ofs, a);
3036 emit_strh_dualindexed(offset_reg, a, rt);
3037 if (ofs != 0 && preseve_a)
3038 emit_addimm(a, -ofs, a);
3041 static void do_store_byte(int a, int rt, int offset_reg)
3043 if (offset_reg >= 0)
3044 emit_strb_dualindexed(offset_reg, a, rt);
3046 emit_writebyte_indexed(rt, 0, a);
3049 static void load_assemble(int i, const struct regstat *i_regs, int ccadj_)
3051 int addr = cinfo[i].addr;
3055 int memtarget=0,c=0;
3056 int offset_reg = -1;
3057 int fastio_reg_override = -1;
3058 u_int reglist=get_host_reglist(i_regs->regmap);
3059 tl=get_reg_w(i_regs->regmap, dops[i].rt1);
3060 s=get_reg(i_regs->regmap,dops[i].rs1);
3061 offset=cinfo[i].imm;
3062 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
3064 c=(i_regs->wasconst>>s)&1;
3066 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
3069 //printf("load_assemble: c=%d\n",c);
3070 //if(c) printf("load_assemble: const=%lx\n",(long)constmap[i][s]+offset);
3071 if(tl<0 && ((!c||(((u_int)constmap[i][s]+offset)>>16)==0x1f80) || dops[i].rt1==0)) {
3072 // could be FIFO, must perform the read
3074 assem_debug("(forced read)\n");
3075 tl = get_reg_temp(i_regs->regmap); // may be == addr
3080 //printf("load_assemble: c=%d\n",c);
3081 //if(c) printf("load_assemble: const=%lx\n",(long)constmap[i][s]+offset);
3085 // Strmnnrmn's speed hack
3086 if(dops[i].rs1!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
3089 jaddr = emit_fastpath_cmp_jump(i, i_regs, addr,
3090 &offset_reg, &fastio_reg_override, ccadj_);
3093 else if (ram_offset && memtarget) {
3094 offset_reg = get_ro_reg(i_regs, 0);
3096 int dummy=(dops[i].rt1==0)||(tl!=get_reg_w(i_regs->regmap, dops[i].rt1)); // ignore loads to r0 and unneeded reg
3097 switch (dops[i].opcode) {
3102 if (fastio_reg_override >= 0)
3103 a = fastio_reg_override;
3105 if (offset_reg >= 0)
3106 emit_ldrsb_dualindexed(offset_reg, a, tl);
3108 emit_movsbl_indexed(0, a, tl);
3111 add_stub_r(LOADB_STUB,jaddr,out,i,addr,i_regs,ccadj_,reglist);
3114 inline_readstub(LOADB_STUB,i,constmap[i][s]+offset,i_regs->regmap,dops[i].rt1,ccadj_,reglist);
3120 if (fastio_reg_override >= 0)
3121 a = fastio_reg_override;
3122 if (offset_reg >= 0)
3123 emit_ldrsh_dualindexed(offset_reg, a, tl);
3125 emit_movswl_indexed(0, a, tl);
3128 add_stub_r(LOADH_STUB,jaddr,out,i,addr,i_regs,ccadj_,reglist);
3131 inline_readstub(LOADH_STUB,i,constmap[i][s]+offset,i_regs->regmap,dops[i].rt1,ccadj_,reglist);
3137 if (fastio_reg_override >= 0)
3138 a = fastio_reg_override;
3139 do_load_word(a, tl, offset_reg);
3142 add_stub_r(LOADW_STUB,jaddr,out,i,addr,i_regs,ccadj_,reglist);
3145 inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,dops[i].rt1,ccadj_,reglist);
3151 if (fastio_reg_override >= 0)
3152 a = fastio_reg_override;
3154 if (offset_reg >= 0)
3155 emit_ldrb_dualindexed(offset_reg, a, tl);
3157 emit_movzbl_indexed(0, a, tl);
3160 add_stub_r(LOADBU_STUB,jaddr,out,i,addr,i_regs,ccadj_,reglist);
3163 inline_readstub(LOADBU_STUB,i,constmap[i][s]+offset,i_regs->regmap,dops[i].rt1,ccadj_,reglist);
3169 if (fastio_reg_override >= 0)
3170 a = fastio_reg_override;
3171 if (offset_reg >= 0)
3172 emit_ldrh_dualindexed(offset_reg, a, tl);
3174 emit_movzwl_indexed(0, a, tl);
3177 add_stub_r(LOADHU_STUB,jaddr,out,i,addr,i_regs,ccadj_,reglist);
3180 inline_readstub(LOADHU_STUB,i,constmap[i][s]+offset,i_regs->regmap,dops[i].rt1,ccadj_,reglist);
3186 if (fastio_reg_override == HOST_TEMPREG || offset_reg == HOST_TEMPREG)
3187 host_tempreg_release();
3190 #ifndef loadlr_assemble
3191 static void loadlr_assemble(int i, const struct regstat *i_regs, int ccadj_)
3193 int addr = cinfo[i].addr;
3194 int s,tl,temp,temp2;
3197 int memtarget=0,c=0;
3198 int offset_reg = -1;
3199 int fastio_reg_override = -1;
3200 u_int reglist=get_host_reglist(i_regs->regmap);
3201 tl=get_reg_w(i_regs->regmap, dops[i].rt1);
3202 s=get_reg(i_regs->regmap,dops[i].rs1);
3203 temp=get_reg_temp(i_regs->regmap);
3204 temp2=get_reg(i_regs->regmap,FTEMP);
3205 offset=cinfo[i].imm;
3209 c=(i_regs->wasconst>>s)&1;
3211 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
3215 emit_shlimm(addr,3,temp);
3216 if (dops[i].opcode==0x22||dops[i].opcode==0x26) {
3217 emit_andimm(addr,0xFFFFFFFC,temp2); // LWL/LWR
3219 emit_andimm(addr,0xFFFFFFF8,temp2); // LDL/LDR
3221 jaddr = emit_fastpath_cmp_jump(i, i_regs, temp2,
3222 &offset_reg, &fastio_reg_override, ccadj_);
3225 if (ram_offset && memtarget) {
3226 offset_reg = get_ro_reg(i_regs, 0);
3228 if (dops[i].opcode==0x22||dops[i].opcode==0x26) {
3229 emit_movimm(((constmap[i][s]+offset)<<3)&24,temp); // LWL/LWR
3231 emit_movimm(((constmap[i][s]+offset)<<3)&56,temp); // LDL/LDR
3234 if (dops[i].opcode==0x22||dops[i].opcode==0x26) { // LWL/LWR
3237 if (fastio_reg_override >= 0)
3238 a = fastio_reg_override;
3239 do_load_word(a, temp2, offset_reg);
3240 if (fastio_reg_override == HOST_TEMPREG || offset_reg == HOST_TEMPREG)
3241 host_tempreg_release();
3242 if(jaddr) add_stub_r(LOADW_STUB,jaddr,out,i,temp2,i_regs,ccadj_,reglist);
3245 inline_readstub(LOADW_STUB,i,(constmap[i][s]+offset)&0xFFFFFFFC,i_regs->regmap,FTEMP,ccadj_,reglist);
3248 emit_andimm(temp,24,temp);
3249 if (dops[i].opcode==0x22) // LWL
3250 emit_xorimm(temp,24,temp);
3251 host_tempreg_acquire();
3252 emit_movimm(-1,HOST_TEMPREG);
3253 if (dops[i].opcode==0x26) {
3254 emit_shr(temp2,temp,temp2);
3255 emit_bic_lsr(tl,HOST_TEMPREG,temp,tl);
3257 emit_shl(temp2,temp,temp2);
3258 emit_bic_lsl(tl,HOST_TEMPREG,temp,tl);
3260 host_tempreg_release();
3261 emit_or(temp2,tl,tl);
3263 //emit_storereg(dops[i].rt1,tl); // DEBUG
3265 if (dops[i].opcode==0x1A||dops[i].opcode==0x1B) { // LDL/LDR
3271 static void do_invstub(int n)
3274 assem_debug("do_invstub\n");
3275 u_int reglist = stubs[n].a;
3276 u_int addrr = stubs[n].b;
3277 int ofs_start = stubs[n].c;
3278 int ofs_end = stubs[n].d;
3279 int len = ofs_end - ofs_start;
3282 set_jump_target(stubs[n].addr, out);
3284 if (addrr != 0 || ofs_start != 0)
3285 emit_addimm(addrr, ofs_start, 0);
3286 emit_readword(&inv_code_start, 2);
3287 emit_readword(&inv_code_end, 3);
3289 emit_addimm(0, len + 4, (rightr = 1));
3291 emit_cmpcs(3, rightr);
3294 void *func = (len != 0)
3295 ? (void *)ndrc_write_invalidate_many
3296 : (void *)ndrc_write_invalidate_one;
3297 emit_far_call(func);
3298 set_jump_target(jaddr, out);
3299 restore_regs(reglist);
3300 emit_jmp(stubs[n].retaddr);
3303 static void do_store_smc_check(int i, const struct regstat *i_regs, u_int reglist, int addr)
3305 if (HACK_ENABLED(NDHACK_NO_SMC_CHECK))
3307 // this can't be used any more since we started to check exact
3308 // block boundaries in invalidate_range()
3309 //if (i_regs->waswritten & (1<<dops[i].rs1))
3311 // (naively) assume nobody will run code from stack
3312 if (dops[i].rs1 == 29)
3315 int j, imm_maxdiff = 32, imm_min = cinfo[i].imm, imm_max = cinfo[i].imm, count = 1;
3316 if (i < slen - 1 && dops[i+1].is_store && dops[i+1].rs1 == dops[i].rs1
3317 && abs(cinfo[i+1].imm - cinfo[i].imm) <= imm_maxdiff)
3319 for (j = i - 1; j >= 0; j--) {
3320 if (!dops[j].is_store || dops[j].rs1 != dops[i].rs1
3321 || abs(cinfo[j].imm - cinfo[j+1].imm) > imm_maxdiff)
3324 if (imm_min > cinfo[j].imm)
3325 imm_min = cinfo[j].imm;
3326 if (imm_max < cinfo[j].imm)
3327 imm_max = cinfo[j].imm;
3329 #if defined(HOST_IMM8)
3330 int ir = get_reg(i_regs->regmap, INVCP);
3332 host_tempreg_acquire();
3333 emit_ldrb_indexedsr12_reg(ir, addr, HOST_TEMPREG);
3335 emit_cmpmem_indexedsr12_imm(invalid_code, addr, 1);
3338 #ifdef INVALIDATE_USE_COND_CALL
3340 emit_cmpimm(HOST_TEMPREG, 1);
3341 emit_callne(invalidate_addr_reg[addr]);
3342 host_tempreg_release();
3346 void *jaddr = emit_cbz(HOST_TEMPREG, 0);
3347 host_tempreg_release();
3348 imm_min -= cinfo[i].imm;
3349 imm_max -= cinfo[i].imm;
3350 add_stub(INVCODE_STUB, jaddr, out, reglist|(1<<HOST_CCREG),
3351 addr, imm_min, imm_max, 0);
3354 static void store_assemble(int i, const struct regstat *i_regs, int ccadj_)
3357 int addr = cinfo[i].addr;
3360 enum stub_type type=0;
3361 int memtarget=0,c=0;
3362 int offset_reg = -1;
3363 int fastio_reg_override = -1;
3364 u_int reglist=get_host_reglist(i_regs->regmap);
3365 tl=get_reg(i_regs->regmap,dops[i].rs2);
3366 s=get_reg(i_regs->regmap,dops[i].rs1);
3367 offset=cinfo[i].imm;
3369 c=(i_regs->wasconst>>s)&1;
3371 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
3376 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
3378 jaddr = emit_fastpath_cmp_jump(i, i_regs, addr,
3379 &offset_reg, &fastio_reg_override, ccadj_);
3381 else if (ram_offset && memtarget) {
3382 offset_reg = get_ro_reg(i_regs, 0);
3385 switch (dops[i].opcode) {
3389 if (fastio_reg_override >= 0)
3390 a = fastio_reg_override;
3391 do_store_byte(a, tl, offset_reg);
3398 if (fastio_reg_override >= 0)
3399 a = fastio_reg_override;
3400 do_store_hword(a, 0, tl, offset_reg, 1);
3407 if (fastio_reg_override >= 0)
3408 a = fastio_reg_override;
3409 do_store_word(a, 0, tl, offset_reg, 1);
3416 if (fastio_reg_override == HOST_TEMPREG || offset_reg == HOST_TEMPREG)
3417 host_tempreg_release();
3419 // PCSX store handlers don't check invcode again
3421 add_stub_r(type,jaddr,out,i,addr,i_regs,ccadj_,reglist);
3426 do_store_smc_check(i, i_regs, reglist, addr);
3429 u_int addr_val=constmap[i][s]+offset;
3431 add_stub_r(type,jaddr,out,i,addr,i_regs,ccadj_,reglist);
3432 } else if(c&&!memtarget) {
3433 inline_writestub(type,i,addr_val,i_regs->regmap,dops[i].rs2,ccadj_,reglist);
3435 // basic current block modification detection..
3436 // not looking back as that should be in mips cache already
3437 // (see Spyro2 title->attract mode)
3438 if(c&&start+i*4<addr_val&&addr_val<start+slen*4) {
3439 SysPrintf("write to %08x hits block %08x, pc=%08x\n",addr_val,start,start+i*4);
3440 assert(i_regs->regmap==regs[i].regmap); // not delay slot
3441 if(i_regs->regmap==regs[i].regmap) {
3442 load_all_consts(regs[i].regmap_entry,regs[i].wasdirty,i);
3443 wb_dirtys(regs[i].regmap_entry,regs[i].wasdirty);
3444 emit_movimm(start+i*4+4,0);
3445 emit_writeword(0,&pcaddr);
3446 emit_addimm(HOST_CCREG,2,HOST_CCREG);
3447 emit_far_call(ndrc_get_addr_ht);
3453 static void storelr_assemble(int i, const struct regstat *i_regs, int ccadj_)
3455 int addr = cinfo[i].addr;
3459 void *case1, *case23, *case3;
3460 void *done0, *done1, *done2;
3461 int memtarget=0,c=0;
3462 int offset_reg = -1;
3463 u_int reglist=get_host_reglist(i_regs->regmap);
3464 tl=get_reg(i_regs->regmap,dops[i].rs2);
3465 s=get_reg(i_regs->regmap,dops[i].rs1);
3466 offset=cinfo[i].imm;
3468 c=(i_regs->isconst>>s)&1;
3470 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
3476 emit_cmpimm(addr, RAM_SIZE);
3477 if (!offset && s != addr) emit_mov(s, addr);
3483 if(!memtarget||!dops[i].rs1) {
3489 offset_reg = get_ro_reg(i_regs, 0);
3491 if (dops[i].opcode==0x2C||dops[i].opcode==0x2D) { // SDL/SDR
3495 emit_testimm(addr,2);
3498 emit_testimm(addr,1);
3502 if (dops[i].opcode == 0x2A) { // SWL
3503 // Write msb into least significant byte
3504 if (dops[i].rs2) emit_rorimm(tl, 24, tl);
3505 do_store_byte(addr, tl, offset_reg);
3506 if (dops[i].rs2) emit_rorimm(tl, 8, tl);
3508 else if (dops[i].opcode == 0x2E) { // SWR
3509 // Write entire word
3510 do_store_word(addr, 0, tl, offset_reg, 1);
3515 set_jump_target(case1, out);
3516 if (dops[i].opcode == 0x2A) { // SWL
3517 // Write two msb into two least significant bytes
3518 if (dops[i].rs2) emit_rorimm(tl, 16, tl);
3519 do_store_hword(addr, -1, tl, offset_reg, 0);
3520 if (dops[i].rs2) emit_rorimm(tl, 16, tl);
3522 else if (dops[i].opcode == 0x2E) { // SWR
3523 // Write 3 lsb into three most significant bytes
3524 do_store_byte(addr, tl, offset_reg);
3525 if (dops[i].rs2) emit_rorimm(tl, 8, tl);
3526 do_store_hword(addr, 1, tl, offset_reg, 0);
3527 if (dops[i].rs2) emit_rorimm(tl, 24, tl);
3532 set_jump_target(case23, out);
3533 emit_testimm(addr,1);
3537 if (dops[i].opcode==0x2A) { // SWL
3538 // Write 3 msb into three least significant bytes
3539 if (dops[i].rs2) emit_rorimm(tl, 8, tl);
3540 do_store_hword(addr, -2, tl, offset_reg, 1);
3541 if (dops[i].rs2) emit_rorimm(tl, 16, tl);
3542 do_store_byte(addr, tl, offset_reg);
3543 if (dops[i].rs2) emit_rorimm(tl, 8, tl);
3545 else if (dops[i].opcode == 0x2E) { // SWR
3546 // Write two lsb into two most significant bytes
3547 do_store_hword(addr, 0, tl, offset_reg, 1);
3552 set_jump_target(case3, out);
3553 if (dops[i].opcode == 0x2A) { // SWL
3554 do_store_word(addr, -3, tl, offset_reg, 0);
3556 else if (dops[i].opcode == 0x2E) { // SWR
3557 do_store_byte(addr, tl, offset_reg);
3559 set_jump_target(done0, out);
3560 set_jump_target(done1, out);
3561 set_jump_target(done2, out);
3562 if (offset_reg == HOST_TEMPREG)
3563 host_tempreg_release();
3565 add_stub_r(STORELR_STUB,jaddr,out,i,addr,i_regs,ccadj_,reglist);
3566 do_store_smc_check(i, i_regs, reglist, addr);
3569 static void cop0_assemble(int i, const struct regstat *i_regs, int ccadj_)
3571 if(dops[i].opcode2==0) // MFC0
3573 signed char t=get_reg_w(i_regs->regmap, dops[i].rt1);
3574 u_int copr=(source[i]>>11)&0x1f;
3575 if(t>=0&&dops[i].rt1!=0) {
3576 emit_readword(®_cop0[copr],t);
3579 else if(dops[i].opcode2==4) // MTC0
3581 signed char s=get_reg(i_regs->regmap,dops[i].rs1);
3582 char copr=(source[i]>>11)&0x1f;
3584 wb_register(dops[i].rs1,i_regs->regmap,i_regs->dirty);
3585 if(copr==9||copr==11||copr==12||copr==13) {
3586 emit_readword(&last_count,HOST_TEMPREG);
3587 emit_loadreg(CCREG,HOST_CCREG); // TODO: do proper reg alloc
3588 emit_add(HOST_CCREG,HOST_TEMPREG,HOST_CCREG);
3589 emit_addimm(HOST_CCREG,ccadj_,HOST_CCREG);
3590 emit_writeword(HOST_CCREG,&psxRegs.cycle);
3592 // What a mess. The status register (12) can enable interrupts,
3593 // so needs a special case to handle a pending interrupt.
3594 // The interrupt must be taken immediately, because a subsequent
3595 // instruction might disable interrupts again.
3596 if(copr==12||copr==13) {
3598 // burn cycles to cause cc_interrupt, which will
3599 // reschedule next_interupt. Relies on CCREG from above.
3600 assem_debug("MTC0 DS %d\n", copr);
3601 emit_writeword(HOST_CCREG,&last_count);
3602 emit_movimm(0,HOST_CCREG);
3603 emit_storereg(CCREG,HOST_CCREG);
3604 emit_loadreg(dops[i].rs1,1);
3605 emit_movimm(copr,0);
3606 emit_far_call(pcsx_mtc0_ds);
3607 emit_loadreg(dops[i].rs1,s);
3610 emit_movimm(start+i*4+4,HOST_TEMPREG);
3611 emit_writeword(HOST_TEMPREG,&pcaddr);
3612 emit_movimm(0,HOST_TEMPREG);
3613 emit_writeword(HOST_TEMPREG,&pending_exception);
3616 emit_loadreg(dops[i].rs1,1);
3619 emit_movimm(copr,0);
3620 emit_far_call(pcsx_mtc0);
3621 if(copr==9||copr==11||copr==12||copr==13) {
3622 emit_readword(&psxRegs.cycle,HOST_CCREG);
3623 emit_readword(&next_interupt,HOST_TEMPREG);
3624 emit_addimm(HOST_CCREG,-ccadj_,HOST_CCREG);
3625 emit_sub(HOST_CCREG,HOST_TEMPREG,HOST_CCREG);
3626 emit_writeword(HOST_TEMPREG,&last_count);
3627 emit_storereg(CCREG,HOST_CCREG);
3629 if(copr==12||copr==13) {
3630 assert(!is_delayslot);
3631 emit_readword(&pending_exception,HOST_TEMPREG);
3632 emit_test(HOST_TEMPREG,HOST_TEMPREG);
3635 emit_readword(&pcaddr, 0);
3636 emit_addimm(HOST_CCREG,2,HOST_CCREG);
3637 emit_far_call(ndrc_get_addr_ht);
3639 set_jump_target(jaddr, out);
3641 emit_loadreg(dops[i].rs1,s);
3645 static void rfe_assemble(int i, const struct regstat *i_regs)
3647 emit_readword(&psxRegs.CP0.n.SR, 0);
3648 emit_andimm(0, 0x3c, 1);
3649 emit_andimm(0, ~0xf, 0);
3650 emit_orrshr_imm(1, 2, 0);
3651 emit_writeword(0, &psxRegs.CP0.n.SR);
3654 static int cop2_is_stalling_op(int i, int *cycles)
3656 if (dops[i].opcode == 0x3a) { // SWC2
3660 if (dops[i].itype == COP2 && (dops[i].opcode2 == 0 || dops[i].opcode2 == 2)) { // MFC2/CFC2
3664 if (dops[i].itype == C2OP) {
3665 *cycles = gte_cycletab[source[i] & 0x3f];
3668 // ... what about MTC2/CTC2/LWC2?
3673 static void log_gte_stall(int stall, u_int cycle)
3675 if ((u_int)stall <= 44)
3676 printf("x stall %2d %u\n", stall, cycle + last_count);
3679 static void emit_log_gte_stall(int i, int stall, u_int reglist)
3683 emit_movimm(stall, 0);
3685 emit_mov(HOST_TEMPREG, 0);
3686 emit_addimm(HOST_CCREG, cinfo[i].ccadj, 1);
3687 emit_far_call(log_gte_stall);
3688 restore_regs(reglist);
3692 static void cop2_do_stall_check(u_int op, int i, const struct regstat *i_regs, u_int reglist)
3694 int j = i, other_gte_op_cycles = -1, stall = -MAXBLOCK, cycles_passed;
3695 int rtmp = reglist_find_free(reglist);
3697 if (HACK_ENABLED(NDHACK_NO_STALLS))
3699 if (get_reg(i_regs->regmap, CCREG) != HOST_CCREG) {
3700 // happens occasionally... cc evicted? Don't bother then
3701 //printf("no cc %08x\n", start + i*4);
3705 for (j = i - 1; j >= 0; j--) {
3706 //if (dops[j].is_ds) break;
3707 if (cop2_is_stalling_op(j, &other_gte_op_cycles) || dops[j].bt)
3709 if (j > 0 && cinfo[j - 1].ccadj > cinfo[j].ccadj)
3714 cycles_passed = cinfo[i].ccadj - cinfo[j].ccadj;
3715 if (other_gte_op_cycles >= 0)
3716 stall = other_gte_op_cycles - cycles_passed;
3717 else if (cycles_passed >= 44)
3718 stall = 0; // can't stall
3719 if (stall == -MAXBLOCK && rtmp >= 0) {
3720 // unknown stall, do the expensive runtime check
3721 assem_debug("; cop2_do_stall_check\n");
3724 emit_movimm(gte_cycletab[op], 0);
3725 emit_addimm(HOST_CCREG, cinfo[i].ccadj, 1);
3726 emit_far_call(call_gteStall);
3727 restore_regs(reglist);
3729 host_tempreg_acquire();
3730 emit_readword(&psxRegs.gteBusyCycle, rtmp);
3731 emit_addimm(rtmp, -cinfo[i].ccadj, rtmp);
3732 emit_sub(rtmp, HOST_CCREG, HOST_TEMPREG);
3733 emit_cmpimm(HOST_TEMPREG, 44);
3734 emit_cmovb_reg(rtmp, HOST_CCREG);
3735 //emit_log_gte_stall(i, 0, reglist);
3736 host_tempreg_release();
3739 else if (stall > 0) {
3740 //emit_log_gte_stall(i, stall, reglist);
3741 emit_addimm(HOST_CCREG, stall, HOST_CCREG);
3744 // save gteBusyCycle, if needed
3745 if (gte_cycletab[op] == 0)
3747 other_gte_op_cycles = -1;
3748 for (j = i + 1; j < slen; j++) {
3749 if (cop2_is_stalling_op(j, &other_gte_op_cycles))
3751 if (dops[j].is_jump) {
3753 if (j + 1 < slen && cop2_is_stalling_op(j + 1, &other_gte_op_cycles))
3758 if (other_gte_op_cycles >= 0)
3759 // will handle stall when assembling that op
3761 cycles_passed = cinfo[min(j, slen -1)].ccadj - cinfo[i].ccadj;
3762 if (cycles_passed >= 44)
3764 assem_debug("; save gteBusyCycle\n");
3765 host_tempreg_acquire();
3767 emit_readword(&last_count, HOST_TEMPREG);
3768 emit_add(HOST_TEMPREG, HOST_CCREG, HOST_TEMPREG);
3769 emit_addimm(HOST_TEMPREG, cinfo[i].ccadj, HOST_TEMPREG);
3770 emit_addimm(HOST_TEMPREG, gte_cycletab[op]), HOST_TEMPREG);
3771 emit_writeword(HOST_TEMPREG, &psxRegs.gteBusyCycle);
3773 emit_addimm(HOST_CCREG, cinfo[i].ccadj + gte_cycletab[op], HOST_TEMPREG);
3774 emit_writeword(HOST_TEMPREG, &psxRegs.gteBusyCycle);
3776 host_tempreg_release();
3779 static int is_mflohi(int i)
3781 return (dops[i].itype == MOV && (dops[i].rs1 == HIREG || dops[i].rs1 == LOREG));
3784 static int check_multdiv(int i, int *cycles)
3786 if (dops[i].itype != MULTDIV)
3788 if (dops[i].opcode2 == 0x18 || dops[i].opcode2 == 0x19) // MULT(U)
3789 *cycles = 11; // approx from 7 11 14
3795 static void multdiv_prepare_stall(int i, const struct regstat *i_regs, int ccadj_)
3797 int j, found = 0, c = 0;
3798 if (HACK_ENABLED(NDHACK_NO_STALLS))
3800 if (get_reg(i_regs->regmap, CCREG) != HOST_CCREG) {
3801 // happens occasionally... cc evicted? Don't bother then
3804 for (j = i + 1; j < slen; j++) {
3807 if ((found = is_mflohi(j)))
3809 if (dops[j].is_jump) {
3811 if (j + 1 < slen && (found = is_mflohi(j + 1)))
3817 // handle all in multdiv_do_stall()
3819 check_multdiv(i, &c);
3821 assem_debug("; muldiv prepare stall %d\n", c);
3822 host_tempreg_acquire();
3823 emit_addimm(HOST_CCREG, ccadj_ + c, HOST_TEMPREG);
3824 emit_writeword(HOST_TEMPREG, &psxRegs.muldivBusyCycle);
3825 host_tempreg_release();
3828 static void multdiv_do_stall(int i, const struct regstat *i_regs)
3830 int j, known_cycles = 0;
3831 u_int reglist = get_host_reglist(i_regs->regmap);
3832 int rtmp = get_reg_temp(i_regs->regmap);
3834 rtmp = reglist_find_free(reglist);
3835 if (HACK_ENABLED(NDHACK_NO_STALLS))
3837 if (get_reg(i_regs->regmap, CCREG) != HOST_CCREG || rtmp < 0) {
3838 // happens occasionally... cc evicted? Don't bother then
3839 //printf("no cc/rtmp %08x\n", start + i*4);
3843 for (j = i - 1; j >= 0; j--) {
3844 if (dops[j].is_ds) break;
3845 if (check_multdiv(j, &known_cycles))
3848 // already handled by this op
3850 if (dops[j].bt || (j > 0 && cinfo[j - 1].ccadj > cinfo[j].ccadj))
3855 if (known_cycles > 0) {
3856 known_cycles -= cinfo[i].ccadj - cinfo[j].ccadj;
3857 assem_debug("; muldiv stall resolved %d\n", known_cycles);
3858 if (known_cycles > 0)
3859 emit_addimm(HOST_CCREG, known_cycles, HOST_CCREG);
3862 assem_debug("; muldiv stall unresolved\n");
3863 host_tempreg_acquire();
3864 emit_readword(&psxRegs.muldivBusyCycle, rtmp);
3865 emit_addimm(rtmp, -cinfo[i].ccadj, rtmp);
3866 emit_sub(rtmp, HOST_CCREG, HOST_TEMPREG);
3867 emit_cmpimm(HOST_TEMPREG, 37);
3868 emit_cmovb_reg(rtmp, HOST_CCREG);
3869 //emit_log_gte_stall(i, 0, reglist);
3870 host_tempreg_release();
3873 static void cop2_get_dreg(u_int copr,signed char tl,signed char temp)
3883 emit_readword(®_cop2d[copr],tl);
3884 emit_signextend16(tl,tl);
3885 emit_writeword(tl,®_cop2d[copr]); // hmh
3892 emit_readword(®_cop2d[copr],tl);
3893 emit_andimm(tl,0xffff,tl);
3894 emit_writeword(tl,®_cop2d[copr]);
3897 emit_readword(®_cop2d[14],tl); // SXY2
3898 emit_writeword(tl,®_cop2d[copr]);
3902 c2op_mfc2_29_assemble(tl,temp);
3905 emit_readword(®_cop2d[copr],tl);
3910 static void cop2_put_dreg(u_int copr,signed char sl,signed char temp)
3914 emit_readword(®_cop2d[13],temp); // SXY1
3915 emit_writeword(sl,®_cop2d[copr]);
3916 emit_writeword(temp,®_cop2d[12]); // SXY0
3917 emit_readword(®_cop2d[14],temp); // SXY2
3918 emit_writeword(sl,®_cop2d[14]);
3919 emit_writeword(temp,®_cop2d[13]); // SXY1
3922 emit_andimm(sl,0x001f,temp);
3923 emit_shlimm(temp,7,temp);
3924 emit_writeword(temp,®_cop2d[9]);
3925 emit_andimm(sl,0x03e0,temp);
3926 emit_shlimm(temp,2,temp);
3927 emit_writeword(temp,®_cop2d[10]);
3928 emit_andimm(sl,0x7c00,temp);
3929 emit_shrimm(temp,3,temp);
3930 emit_writeword(temp,®_cop2d[11]);
3931 emit_writeword(sl,®_cop2d[28]);
3934 emit_xorsar_imm(sl,sl,31,temp);
3935 #if defined(HAVE_ARMV5) || defined(__aarch64__)
3936 emit_clz(temp,temp);
3938 emit_movs(temp,HOST_TEMPREG);
3939 emit_movimm(0,temp);
3940 emit_jeq((int)out+4*4);
3941 emit_addpl_imm(temp,1,temp);
3942 emit_lslpls_imm(HOST_TEMPREG,1,HOST_TEMPREG);
3943 emit_jns((int)out-2*4);
3945 emit_writeword(sl,®_cop2d[30]);
3946 emit_writeword(temp,®_cop2d[31]);
3951 emit_writeword(sl,®_cop2d[copr]);
3956 static void c2ls_assemble(int i, const struct regstat *i_regs, int ccadj_)
3961 int memtarget=0,c=0;
3963 enum stub_type type;
3964 int offset_reg = -1;
3965 int fastio_reg_override = -1;
3966 u_int reglist=get_host_reglist(i_regs->regmap);
3967 u_int copr=(source[i]>>16)&0x1f;
3968 s=get_reg(i_regs->regmap,dops[i].rs1);
3969 tl=get_reg(i_regs->regmap,FTEMP);
3970 offset=cinfo[i].imm;
3971 assert(dops[i].rs1>0);
3974 if(i_regs->regmap[HOST_CCREG]==CCREG)
3975 reglist&=~(1<<HOST_CCREG);
3980 if (dops[i].opcode==0x3a) { // SWC2
3983 if(s>=0) c=(i_regs->wasconst>>s)&1;
3984 memtarget=c&&(((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE);
3986 cop2_do_stall_check(0, i, i_regs, reglist);
3988 if (dops[i].opcode==0x3a) { // SWC2
3989 cop2_get_dreg(copr,tl,-1);
3997 emit_jmp(0); // inline_readstub/inline_writestub?
4001 jaddr2 = emit_fastpath_cmp_jump(i, i_regs, ar,
4002 &offset_reg, &fastio_reg_override, ccadj_);
4004 else if (ram_offset && memtarget) {
4005 offset_reg = get_ro_reg(i_regs, 0);
4007 switch (dops[i].opcode) {
4008 case 0x32: { // LWC2
4010 if (fastio_reg_override >= 0)
4011 a = fastio_reg_override;
4012 do_load_word(a, tl, offset_reg);
4015 case 0x3a: { // SWC2
4016 #ifdef DESTRUCTIVE_SHIFT
4017 if(!offset&&!c&&s>=0) emit_mov(s,ar);
4020 if (fastio_reg_override >= 0)
4021 a = fastio_reg_override;
4022 do_store_word(a, 0, tl, offset_reg, 1);
4029 if (fastio_reg_override == HOST_TEMPREG || offset_reg == HOST_TEMPREG)
4030 host_tempreg_release();
4032 add_stub_r(type,jaddr2,out,i,ar,i_regs,ccadj_,reglist);
4033 if(dops[i].opcode==0x3a) // SWC2
4034 do_store_smc_check(i, i_regs, reglist, ar);
4035 if (dops[i].opcode==0x32) { // LWC2
4036 host_tempreg_acquire();
4037 cop2_put_dreg(copr,tl,HOST_TEMPREG);
4038 host_tempreg_release();
4042 static void cop2_assemble(int i, const struct regstat *i_regs)
4044 u_int copr = (source[i]>>11) & 0x1f;
4045 signed char temp = get_reg_temp(i_regs->regmap);
4047 if (!HACK_ENABLED(NDHACK_NO_STALLS)) {
4048 u_int reglist = reglist_exclude(get_host_reglist(i_regs->regmap), temp, -1);
4049 if (dops[i].opcode2 == 0 || dops[i].opcode2 == 2) { // MFC2/CFC2
4050 signed char tl = get_reg(i_regs->regmap, dops[i].rt1);
4051 reglist = reglist_exclude(reglist, tl, -1);
4053 cop2_do_stall_check(0, i, i_regs, reglist);
4055 if (dops[i].opcode2==0) { // MFC2
4056 signed char tl=get_reg_w(i_regs->regmap, dops[i].rt1);
4057 if(tl>=0&&dops[i].rt1!=0)
4058 cop2_get_dreg(copr,tl,temp);
4060 else if (dops[i].opcode2==4) { // MTC2
4061 signed char sl=get_reg(i_regs->regmap,dops[i].rs1);
4062 cop2_put_dreg(copr,sl,temp);
4064 else if (dops[i].opcode2==2) // CFC2
4066 signed char tl=get_reg_w(i_regs->regmap, dops[i].rt1);
4067 if(tl>=0&&dops[i].rt1!=0)
4068 emit_readword(®_cop2c[copr],tl);
4070 else if (dops[i].opcode2==6) // CTC2
4072 signed char sl=get_reg(i_regs->regmap,dops[i].rs1);
4081 emit_signextend16(sl,temp);
4084 c2op_ctc2_31_assemble(sl,temp);
4090 emit_writeword(temp,®_cop2c[copr]);
4095 static void do_unalignedwritestub(int n)
4097 assem_debug("do_unalignedwritestub %x\n",start+stubs[n].a*4);
4099 set_jump_target(stubs[n].addr, out);
4102 struct regstat *i_regs=(struct regstat *)stubs[n].c;
4103 int addr=stubs[n].b;
4104 u_int reglist=stubs[n].e;
4105 signed char *i_regmap=i_regs->regmap;
4106 int temp2=get_reg(i_regmap,FTEMP);
4108 rt=get_reg(i_regmap,dops[i].rs2);
4111 assert(dops[i].opcode==0x2a||dops[i].opcode==0x2e); // SWL/SWR only implemented
4113 reglist&=~(1<<temp2);
4115 // don't bother with it and call write handler
4118 int cc=get_reg(i_regmap,CCREG);
4120 emit_loadreg(CCREG,2);
4121 emit_addimm(cc<0?2:cc,(int)stubs[n].d+1,2);
4122 emit_far_call((dops[i].opcode==0x2a?jump_handle_swl:jump_handle_swr));
4123 emit_addimm(0,-((int)stubs[n].d+1),cc<0?2:cc);
4125 emit_storereg(CCREG,2);
4126 restore_regs(reglist);
4127 emit_jmp(stubs[n].retaddr); // return address
4130 static void do_overflowstub(int n)
4132 assem_debug("do_overflowstub %x\n", start + (u_int)stubs[n].a * 4);
4135 struct regstat *i_regs = (struct regstat *)stubs[n].c;
4136 int ccadj = stubs[n].d;
4137 set_jump_target(stubs[n].addr, out);
4138 wb_dirtys(regs[i].regmap, regs[i].dirty);
4139 exception_assemble(i, i_regs, ccadj);
4142 static void do_alignmentstub(int n)
4144 assem_debug("do_alignmentstub %x\n", start + (u_int)stubs[n].a * 4);
4147 struct regstat *i_regs = (struct regstat *)stubs[n].c;
4148 int ccadj = stubs[n].d;
4149 int is_store = dops[i].itype == STORE || dops[i].opcode == 0x3A; // SWC2
4150 int cause = (dops[i].opcode & 3) << 28;
4151 cause |= is_store ? (R3000E_AdES << 2) : (R3000E_AdEL << 2);
4152 set_jump_target(stubs[n].addr, out);
4153 wb_dirtys(regs[i].regmap, regs[i].dirty);
4154 if (stubs[n].b != 1)
4155 emit_mov(stubs[n].b, 1); // faulting address
4156 emit_movimm(cause, 0);
4157 exception_assemble(i, i_regs, ccadj);
4160 #ifndef multdiv_assemble
4161 void multdiv_assemble(int i,struct regstat *i_regs)
4163 printf("Need multdiv_assemble for this architecture.\n");
4168 static void mov_assemble(int i, const struct regstat *i_regs)
4170 //if(dops[i].opcode2==0x10||dops[i].opcode2==0x12) { // MFHI/MFLO
4171 //if(dops[i].opcode2==0x11||dops[i].opcode2==0x13) { // MTHI/MTLO
4174 tl=get_reg_w(i_regs->regmap, dops[i].rt1);
4177 sl=get_reg(i_regs->regmap,dops[i].rs1);
4178 if(sl>=0) emit_mov(sl,tl);
4179 else emit_loadreg(dops[i].rs1,tl);
4182 if (dops[i].rs1 == HIREG || dops[i].rs1 == LOREG) // MFHI/MFLO
4183 multdiv_do_stall(i, i_regs);
4186 // call interpreter, exception handler, things that change pc/regs/cycles ...
4187 static void call_c_cpu_handler(int i, const struct regstat *i_regs, int ccadj_, u_int pc, void *func)
4189 signed char ccreg=get_reg(i_regs->regmap,CCREG);
4190 assert(ccreg==HOST_CCREG);
4191 assert(!is_delayslot);
4194 emit_movimm(pc,3); // Get PC
4195 emit_readword(&last_count,2);
4196 emit_writeword(3,&psxRegs.pc);
4197 emit_addimm(HOST_CCREG,ccadj_,HOST_CCREG);
4198 emit_add(2,HOST_CCREG,2);
4199 emit_writeword(2,&psxRegs.cycle);
4200 emit_addimm_ptr(FP,(u_char *)&psxRegs - (u_char *)&dynarec_local,0);
4201 emit_far_call(func);
4202 emit_far_jump(jump_to_new_pc);
4205 static void exception_assemble(int i, const struct regstat *i_regs, int ccadj_)
4207 // 'break' tends to be littered around to catch things like
4208 // division by 0 and is almost never executed, so don't emit much code here
4210 if (dops[i].itype == ALU || dops[i].itype == IMM16)
4211 func = is_delayslot ? jump_overflow_ds : jump_overflow;
4212 else if (dops[i].itype == LOAD || dops[i].itype == STORE)
4213 func = is_delayslot ? jump_addrerror_ds : jump_addrerror;
4214 else if (dops[i].opcode2 == 0x0C)
4215 func = is_delayslot ? jump_syscall_ds : jump_syscall;
4217 func = is_delayslot ? jump_break_ds : jump_break;
4218 if (get_reg(i_regs->regmap, CCREG) != HOST_CCREG) // evicted
4219 emit_loadreg(CCREG, HOST_CCREG);
4220 emit_movimm(start + i*4, 2); // pc
4221 emit_addimm(HOST_CCREG, ccadj_ + CLOCK_ADJUST(1), HOST_CCREG);
4222 emit_far_jump(func);
4225 static void hlecall_bad()
4230 static void hlecall_assemble(int i, const struct regstat *i_regs, int ccadj_)
4232 void *hlefunc = hlecall_bad;
4233 uint32_t hleCode = source[i] & 0x03ffffff;
4234 if (hleCode < ARRAY_SIZE(psxHLEt))
4235 hlefunc = psxHLEt[hleCode];
4237 call_c_cpu_handler(i, i_regs, ccadj_, start + i*4+4, hlefunc);
4240 static void intcall_assemble(int i, const struct regstat *i_regs, int ccadj_)
4242 call_c_cpu_handler(i, i_regs, ccadj_, start + i*4, execI);
4245 static void speculate_mov(int rs,int rt)
4248 smrv_strong_next|=1<<rt;
4253 static void speculate_mov_weak(int rs,int rt)
4256 smrv_weak_next|=1<<rt;
4261 static void speculate_register_values(int i)
4264 memcpy(smrv,psxRegs.GPR.r,sizeof(smrv));
4265 // gp,sp are likely to stay the same throughout the block
4266 smrv_strong_next=(1<<28)|(1<<29)|(1<<30);
4267 smrv_weak_next=~smrv_strong_next;
4268 //printf(" llr %08x\n", smrv[4]);
4270 smrv_strong=smrv_strong_next;
4271 smrv_weak=smrv_weak_next;
4272 switch(dops[i].itype) {
4274 if ((smrv_strong>>dops[i].rs1)&1) speculate_mov(dops[i].rs1,dops[i].rt1);
4275 else if((smrv_strong>>dops[i].rs2)&1) speculate_mov(dops[i].rs2,dops[i].rt1);
4276 else if((smrv_weak>>dops[i].rs1)&1) speculate_mov_weak(dops[i].rs1,dops[i].rt1);
4277 else if((smrv_weak>>dops[i].rs2)&1) speculate_mov_weak(dops[i].rs2,dops[i].rt1);
4279 smrv_strong_next&=~(1<<dops[i].rt1);
4280 smrv_weak_next&=~(1<<dops[i].rt1);
4284 smrv_strong_next&=~(1<<dops[i].rt1);
4285 smrv_weak_next&=~(1<<dops[i].rt1);
4288 if(dops[i].rt1&&is_const(®s[i],dops[i].rt1)) {
4289 int value,hr=get_reg_w(regs[i].regmap, dops[i].rt1);
4291 if(get_final_value(hr,i,&value))
4292 smrv[dops[i].rt1]=value;
4293 else smrv[dops[i].rt1]=constmap[i][hr];
4294 smrv_strong_next|=1<<dops[i].rt1;
4298 if ((smrv_strong>>dops[i].rs1)&1) speculate_mov(dops[i].rs1,dops[i].rt1);
4299 else if((smrv_weak>>dops[i].rs1)&1) speculate_mov_weak(dops[i].rs1,dops[i].rt1);
4303 if(start<0x2000&&(dops[i].rt1==26||(smrv[dops[i].rt1]>>24)==0xa0)) {
4304 // special case for BIOS
4305 smrv[dops[i].rt1]=0xa0000000;
4306 smrv_strong_next|=1<<dops[i].rt1;
4313 smrv_strong_next&=~(1<<dops[i].rt1);
4314 smrv_weak_next&=~(1<<dops[i].rt1);
4318 if(dops[i].opcode2==0||dops[i].opcode2==2) { // MFC/CFC
4319 smrv_strong_next&=~(1<<dops[i].rt1);
4320 smrv_weak_next&=~(1<<dops[i].rt1);
4324 if (dops[i].opcode==0x32) { // LWC2
4325 smrv_strong_next&=~(1<<dops[i].rt1);
4326 smrv_weak_next&=~(1<<dops[i].rt1);
4332 printf("x %08x %08x %d %d c %08x %08x\n",smrv[r],start+i*4,
4333 ((smrv_strong>>r)&1),(smrv_weak>>r)&1,regs[i].isconst,regs[i].wasconst);
4337 static void ujump_assemble(int i, const struct regstat *i_regs);
4338 static void rjump_assemble(int i, const struct regstat *i_regs);
4339 static void cjump_assemble(int i, const struct regstat *i_regs);
4340 static void sjump_assemble(int i, const struct regstat *i_regs);
4342 static int assemble(int i, const struct regstat *i_regs, int ccadj_)
4345 switch (dops[i].itype) {
4347 alu_assemble(i, i_regs, ccadj_);
4350 imm16_assemble(i, i_regs, ccadj_);
4353 shift_assemble(i, i_regs);
4356 shiftimm_assemble(i, i_regs);
4359 load_assemble(i, i_regs, ccadj_);
4362 loadlr_assemble(i, i_regs, ccadj_);
4365 store_assemble(i, i_regs, ccadj_);
4368 storelr_assemble(i, i_regs, ccadj_);
4371 cop0_assemble(i, i_regs, ccadj_);
4374 rfe_assemble(i, i_regs);
4377 cop2_assemble(i, i_regs);
4380 c2ls_assemble(i, i_regs, ccadj_);
4383 c2op_assemble(i, i_regs);
4386 multdiv_assemble(i, i_regs);
4387 multdiv_prepare_stall(i, i_regs, ccadj_);
4390 mov_assemble(i, i_regs);
4393 exception_assemble(i, i_regs, ccadj_);
4396 hlecall_assemble(i, i_regs, ccadj_);
4399 intcall_assemble(i, i_regs, ccadj_);
4402 ujump_assemble(i, i_regs);
4406 rjump_assemble(i, i_regs);
4410 cjump_assemble(i, i_regs);
4414 sjump_assemble(i, i_regs);
4419 // not handled, just skip
4427 static void ds_assemble(int i, const struct regstat *i_regs)
4429 speculate_register_values(i);
4431 switch (dops[i].itype) {
4439 SysPrintf("Jump in the delay slot. This is probably a bug.\n");
4442 assemble(i, i_regs, cinfo[i].ccadj);
4447 // Is the branch target a valid internal jump?
4448 static int internal_branch(int addr)
4450 if(addr&1) return 0; // Indirect (register) jump
4451 if(addr>=start && addr<start+slen*4-4)
4458 static void wb_invalidate(signed char pre[],signed char entry[],uint64_t dirty,uint64_t u)
4461 for(hr=0;hr<HOST_REGS;hr++) {
4462 if(hr!=EXCLUDE_REG) {
4463 if(pre[hr]!=entry[hr]) {
4466 if(get_reg(entry,pre[hr])<0) {
4468 if(!((u>>pre[hr])&1))
4469 emit_storereg(pre[hr],hr);
4476 // Move from one register to another (no writeback)
4477 for(hr=0;hr<HOST_REGS;hr++) {
4478 if(hr!=EXCLUDE_REG) {
4479 if(pre[hr]!=entry[hr]) {
4480 if(pre[hr]>=0&&pre[hr]<TEMPREG) {
4482 if((nr=get_reg(entry,pre[hr]))>=0) {
4491 // Load the specified registers
4492 // This only loads the registers given as arguments because
4493 // we don't want to load things that will be overwritten
4494 static inline void load_reg(signed char entry[], signed char regmap[], int rs)
4496 int hr = get_reg(regmap, rs);
4497 if (hr >= 0 && entry[hr] != regmap[hr])
4498 emit_loadreg(regmap[hr], hr);
4501 static void load_regs(signed char entry[], signed char regmap[], int rs1, int rs2)
4503 load_reg(entry, regmap, rs1);
4505 load_reg(entry, regmap, rs2);
4508 // Load registers prior to the start of a loop
4509 // so that they are not loaded within the loop
4510 static void loop_preload(signed char pre[],signed char entry[])
4513 for (hr = 0; hr < HOST_REGS; hr++) {
4515 if (r >= 0 && pre[hr] != r && get_reg(pre, r) < 0) {
4516 assem_debug("loop preload:\n");
4518 emit_loadreg(r, hr);
4523 // Generate address for load/store instruction
4524 // goes to AGEN (or temp) for writes, FTEMP for LOADLR and cop1/2 loads
4525 // AGEN is assigned by pass5b_preallocate2
4526 static void address_generation(int i, const struct regstat *i_regs, signed char entry[])
4528 if (dops[i].is_load || dops[i].is_store) {
4530 int agr = AGEN1 + (i&1);
4531 if(dops[i].itype==LOAD) {
4532 if (!dops[i].may_except)
4533 ra = get_reg_w(i_regs->regmap, dops[i].rt1); // reuse dest for agen
4535 ra = get_reg_temp(i_regs->regmap);
4537 if(dops[i].itype==LOADLR) {
4538 ra=get_reg(i_regs->regmap,FTEMP);
4540 if(dops[i].itype==STORE||dops[i].itype==STORELR) {
4541 ra=get_reg(i_regs->regmap,agr);
4542 if(ra<0) ra=get_reg_temp(i_regs->regmap);
4544 if(dops[i].itype==C2LS) {
4545 if (dops[i].opcode == 0x32) // LWC2
4546 ra=get_reg(i_regs->regmap,FTEMP);
4548 ra=get_reg(i_regs->regmap,agr);
4549 if(ra<0) ra=get_reg_temp(i_regs->regmap);
4552 int rs = get_reg(i_regs->regmap, dops[i].rs1);
4555 int offset = cinfo[i].imm;
4556 int add_offset = offset != 0;
4557 int c=(i_regs->wasconst>>rs)&1;
4558 if(dops[i].rs1==0) {
4559 // Using r0 as a base address
4561 if(!entry||entry[ra]!=agr) {
4562 if (dops[i].opcode==0x22||dops[i].opcode==0x26) {
4563 emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR
4565 emit_movimm(offset,ra);
4567 } // else did it in the previous cycle
4573 if (!entry || entry[ra] != dops[i].rs1)
4574 emit_loadreg(dops[i].rs1, ra);
4576 //if(!entry||entry[ra]!=dops[i].rs1)
4577 // printf("poor load scheduling!\n");
4580 if(dops[i].rs1!=dops[i].rt1||dops[i].itype!=LOAD) {
4582 if(!entry||entry[ra]!=agr) {
4583 if (dops[i].opcode==0x22||dops[i].opcode==0x26) {
4584 emit_movimm((constmap[i][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR
4586 emit_movimm(constmap[i][rs]+offset,ra);
4587 regs[i].loadedconst|=1<<ra;
4589 } // else did it in the previous cycle
4592 else // else load_consts already did it
4596 else if (dops[i].itype == STORELR) { // overwrites addr
4607 emit_addimm(rs,offset,ra);
4609 emit_addimm(ra,offset,ra);
4614 assert(cinfo[i].addr >= 0);
4616 // Preload constants for next instruction
4617 if (dops[i+1].is_load || dops[i+1].is_store) {
4620 agr=AGEN1+((i+1)&1);
4621 ra=get_reg(i_regs->regmap,agr);
4623 int rs=get_reg(regs[i+1].regmap,dops[i+1].rs1);
4624 int offset=cinfo[i+1].imm;
4625 int c=(regs[i+1].wasconst>>rs)&1;
4626 if(c&&(dops[i+1].rs1!=dops[i+1].rt1||dops[i+1].itype!=LOAD)) {
4627 if (dops[i+1].opcode==0x22||dops[i+1].opcode==0x26) {
4628 emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR
4629 }else if (dops[i+1].opcode==0x1a||dops[i+1].opcode==0x1b) {
4630 emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFF8,ra); // LDL/LDR
4632 emit_movimm(constmap[i+1][rs]+offset,ra);
4633 regs[i+1].loadedconst|=1<<ra;
4636 else if(dops[i+1].rs1==0) {
4637 // Using r0 as a base address
4638 if (dops[i+1].opcode==0x22||dops[i+1].opcode==0x26) {
4639 emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR
4640 }else if (dops[i+1].opcode==0x1a||dops[i+1].opcode==0x1b) {
4641 emit_movimm(offset&0xFFFFFFF8,ra); // LDL/LDR
4643 emit_movimm(offset,ra);
4650 static int get_final_value(int hr, int i, int *value)
4652 int reg=regs[i].regmap[hr];
4654 if(regs[i+1].regmap[hr]!=reg) break;
4655 if(!((regs[i+1].isconst>>hr)&1)) break;
4656 if(dops[i+1].bt) break;
4660 if (dops[i].is_jump) {
4661 *value=constmap[i][hr];
4665 if (dops[i+1].is_jump) {
4666 // Load in delay slot, out-of-order execution
4667 if(dops[i+2].itype==LOAD&&dops[i+2].rs1==reg&&dops[i+2].rt1==reg&&((regs[i+1].wasconst>>hr)&1))
4669 // Precompute load address
4670 *value=constmap[i][hr]+cinfo[i+2].imm;
4674 if(dops[i+1].itype==LOAD&&dops[i+1].rs1==reg&&dops[i+1].rt1==reg)
4676 // Precompute load address
4677 *value=constmap[i][hr]+cinfo[i+1].imm;
4678 //printf("c=%x imm=%lx\n",(long)constmap[i][hr],cinfo[i+1].imm);
4683 *value=constmap[i][hr];
4684 //printf("c=%lx\n",(long)constmap[i][hr]);
4685 if(i==slen-1) return 1;
4687 return !((unneeded_reg[i+1]>>reg)&1);
4690 // Load registers with known constants
4691 static void load_consts(signed char pre[],signed char regmap[],int i)
4694 // propagate loaded constant flags
4695 if(i==0||dops[i].bt)
4696 regs[i].loadedconst=0;
4698 for(hr=0;hr<HOST_REGS;hr++) {
4699 if(hr!=EXCLUDE_REG&®map[hr]>=0&&((regs[i-1].isconst>>hr)&1)&&pre[hr]==regmap[hr]
4700 &®map[hr]==regs[i-1].regmap[hr]&&((regs[i-1].loadedconst>>hr)&1))
4702 regs[i].loadedconst|=1<<hr;
4707 for(hr=0;hr<HOST_REGS;hr++) {
4708 if(hr!=EXCLUDE_REG&®map[hr]>=0) {
4709 //if(entry[hr]!=regmap[hr]) {
4710 if(!((regs[i].loadedconst>>hr)&1)) {
4711 assert(regmap[hr]<64);
4712 if(((regs[i].isconst>>hr)&1)&®map[hr]>0) {
4713 int value,similar=0;
4714 if(get_final_value(hr,i,&value)) {
4715 // see if some other register has similar value
4716 for(hr2=0;hr2<HOST_REGS;hr2++) {
4717 if(hr2!=EXCLUDE_REG&&((regs[i].loadedconst>>hr2)&1)) {
4718 if(is_similar_value(value,constmap[i][hr2])) {
4726 if(get_final_value(hr2,i,&value2)) // is this needed?
4727 emit_movimm_from(value2,hr2,value,hr);
4729 emit_movimm(value,hr);
4735 emit_movimm(value,hr);
4738 regs[i].loadedconst|=1<<hr;
4745 static void load_all_consts(const signed char regmap[], u_int dirty, int i)
4749 for(hr=0;hr<HOST_REGS;hr++) {
4750 if(hr!=EXCLUDE_REG&®map[hr]>=0&&((dirty>>hr)&1)) {
4751 assert(regmap[hr] < 64);
4752 if(((regs[i].isconst>>hr)&1)&®map[hr]>0) {
4753 int value=constmap[i][hr];
4758 emit_movimm(value,hr);
4765 // Write out all dirty registers (except cycle count)
4766 static void wb_dirtys(const signed char i_regmap[], uint64_t i_dirty)
4769 for(hr=0;hr<HOST_REGS;hr++) {
4770 if(hr!=EXCLUDE_REG) {
4771 if(i_regmap[hr]>0) {
4772 if(i_regmap[hr]!=CCREG) {
4773 if((i_dirty>>hr)&1) {
4774 assert(i_regmap[hr]<64);
4775 emit_storereg(i_regmap[hr],hr);
4783 // Write out dirty registers that we need to reload (pair with load_needed_regs)
4784 // This writes the registers not written by store_regs_bt
4785 static void wb_needed_dirtys(const signed char i_regmap[], uint64_t i_dirty, int addr)
4788 int t=(addr-start)>>2;
4789 for(hr=0;hr<HOST_REGS;hr++) {
4790 if(hr!=EXCLUDE_REG) {
4791 if(i_regmap[hr]>0) {
4792 if(i_regmap[hr]!=CCREG) {
4793 if(i_regmap[hr]==regs[t].regmap_entry[hr] && ((regs[t].dirty>>hr)&1)) {
4794 if((i_dirty>>hr)&1) {
4795 assert(i_regmap[hr]<64);
4796 emit_storereg(i_regmap[hr],hr);
4805 // Load all registers (except cycle count)
4806 static void load_all_regs(const signed char i_regmap[])
4809 for(hr=0;hr<HOST_REGS;hr++) {
4810 if(hr!=EXCLUDE_REG) {
4811 if(i_regmap[hr]==0) {
4815 if(i_regmap[hr]>0 && i_regmap[hr]<TEMPREG && i_regmap[hr]!=CCREG)
4817 emit_loadreg(i_regmap[hr],hr);
4823 // Load all current registers also needed by next instruction
4824 static void load_needed_regs(const signed char i_regmap[], const signed char next_regmap[])
4827 for(hr=0;hr<HOST_REGS;hr++) {
4828 if(hr!=EXCLUDE_REG) {
4829 if(get_reg(next_regmap,i_regmap[hr])>=0) {
4830 if(i_regmap[hr]==0) {
4834 if(i_regmap[hr]>0 && i_regmap[hr]<TEMPREG && i_regmap[hr]!=CCREG)
4836 emit_loadreg(i_regmap[hr],hr);
4843 // Load all regs, storing cycle count if necessary
4844 static void load_regs_entry(int t)
4847 if(dops[t].is_ds) emit_addimm(HOST_CCREG,CLOCK_ADJUST(1),HOST_CCREG);
4848 else if(cinfo[t].ccadj) emit_addimm(HOST_CCREG,-cinfo[t].ccadj,HOST_CCREG);
4849 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) {
4850 emit_storereg(CCREG,HOST_CCREG);
4853 for(hr=0;hr<HOST_REGS;hr++) {
4854 if(regs[t].regmap_entry[hr]>=0&®s[t].regmap_entry[hr]<TEMPREG) {
4855 if(regs[t].regmap_entry[hr]==0) {
4858 else if(regs[t].regmap_entry[hr]!=CCREG)
4860 emit_loadreg(regs[t].regmap_entry[hr],hr);
4866 // Store dirty registers prior to branch
4867 static void store_regs_bt(signed char i_regmap[],uint64_t i_dirty,int addr)
4869 if(internal_branch(addr))
4871 int t=(addr-start)>>2;
4873 for(hr=0;hr<HOST_REGS;hr++) {
4874 if(hr!=EXCLUDE_REG) {
4875 if(i_regmap[hr]>0 && i_regmap[hr]!=CCREG) {
4876 if(i_regmap[hr]!=regs[t].regmap_entry[hr] || !((regs[t].dirty>>hr)&1)) {
4877 if((i_dirty>>hr)&1) {
4878 assert(i_regmap[hr]<64);
4879 if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4880 emit_storereg(i_regmap[hr],hr);
4889 // Branch out of this block, write out all dirty regs
4890 wb_dirtys(i_regmap,i_dirty);
4894 // Load all needed registers for branch target
4895 static void load_regs_bt(signed char i_regmap[],uint64_t i_dirty,int addr)
4897 //if(addr>=start && addr<(start+slen*4))
4898 if(internal_branch(addr))
4900 int t=(addr-start)>>2;
4902 // Store the cycle count before loading something else
4903 if(i_regmap[HOST_CCREG]!=CCREG) {
4904 assert(i_regmap[HOST_CCREG]==-1);
4906 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) {
4907 emit_storereg(CCREG,HOST_CCREG);
4910 for(hr=0;hr<HOST_REGS;hr++) {
4911 if(hr!=EXCLUDE_REG&®s[t].regmap_entry[hr]>=0&®s[t].regmap_entry[hr]<TEMPREG) {
4912 if(i_regmap[hr]!=regs[t].regmap_entry[hr]) {
4913 if(regs[t].regmap_entry[hr]==0) {
4916 else if(regs[t].regmap_entry[hr]!=CCREG)
4918 emit_loadreg(regs[t].regmap_entry[hr],hr);
4926 static int match_bt(signed char i_regmap[],uint64_t i_dirty,int addr)
4928 if(addr>=start && addr<start+slen*4-4)
4930 int t=(addr-start)>>2;
4932 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) return 0;
4933 for(hr=0;hr<HOST_REGS;hr++)
4937 if(i_regmap[hr]!=regs[t].regmap_entry[hr])
4939 if(regs[t].regmap_entry[hr]>=0&&(regs[t].regmap_entry[hr]|64)<TEMPREG+64)
4946 if(i_regmap[hr]<TEMPREG)
4948 if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4951 else if(i_regmap[hr]>=64&&i_regmap[hr]<TEMPREG+64)
4957 else // Same register but is it 32-bit or dirty?
4960 if(!((regs[t].dirty>>hr)&1))
4964 if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4966 //printf("%x: dirty no match\n",addr);
4974 // Delay slots are not valid branch targets
4975 //if(t>0&&(dops[t-1].is_jump) return 0;
4976 // Delay slots require additional processing, so do not match
4977 if(dops[t].is_ds) return 0;
4982 for(hr=0;hr<HOST_REGS;hr++)
4988 if(hr!=HOST_CCREG||i_regmap[hr]!=CCREG)
5003 static void drc_dbg_emit_do_cmp(int i, int ccadj_)
5005 extern void do_insn_cmp();
5007 u_int hr, reglist = get_host_reglist(regs[i].regmap);
5009 assem_debug("//do_insn_cmp %08x\n", start+i*4);
5011 // write out changed consts to match the interpreter
5012 if (i > 0 && !dops[i].bt) {
5013 for (hr = 0; hr < HOST_REGS; hr++) {
5014 int reg = regs[i].regmap_entry[hr]; // regs[i-1].regmap[hr];
5015 if (hr == EXCLUDE_REG || reg <= 0)
5017 if (!((regs[i-1].isconst >> hr) & 1))
5019 if (i > 1 && reg == regs[i-2].regmap[hr] && constmap[i-1][hr] == constmap[i-2][hr])
5021 emit_movimm(constmap[i-1][hr],0);
5022 emit_storereg(reg, 0);
5025 emit_movimm(start+i*4,0);
5026 emit_writeword(0,&pcaddr);
5027 int cc = get_reg(regs[i].regmap_entry, CCREG);
5029 emit_loadreg(CCREG, cc = 0);
5030 emit_addimm(cc, ccadj_, 0);
5031 emit_writeword(0, &psxRegs.cycle);
5032 emit_far_call(do_insn_cmp);
5033 //emit_readword(&cycle,0);
5034 //emit_addimm(0,2,0);
5035 //emit_writeword(0,&cycle);
5037 restore_regs(reglist);
5038 assem_debug("\\\\do_insn_cmp\n");
5041 #define drc_dbg_emit_do_cmp(x,y)
5044 // Used when a branch jumps into the delay slot of another branch
5045 static void ds_assemble_entry(int i)
5047 int t = (cinfo[i].ba - start) >> 2;
5048 int ccadj_ = -CLOCK_ADJUST(1);
5050 instr_addr[t] = out;
5051 assem_debug("Assemble delay slot at %x\n",cinfo[i].ba);
5052 assem_debug("<->\n");
5053 drc_dbg_emit_do_cmp(t, ccadj_);
5054 if(regs[t].regmap_entry[HOST_CCREG]==CCREG&®s[t].regmap[HOST_CCREG]!=CCREG)
5055 wb_register(CCREG,regs[t].regmap_entry,regs[t].wasdirty);
5056 load_regs(regs[t].regmap_entry,regs[t].regmap,dops[t].rs1,dops[t].rs2);
5057 address_generation(t,®s[t],regs[t].regmap_entry);
5058 if (ram_offset && (dops[t].is_load || dops[t].is_store))
5059 load_reg(regs[t].regmap_entry,regs[t].regmap,ROREG);
5060 if (dops[t].is_store)
5061 load_reg(regs[t].regmap_entry,regs[t].regmap,INVCP);
5063 switch (dops[t].itype) {
5071 SysPrintf("Jump in the delay slot. This is probably a bug.\n");
5074 assemble(t, ®s[t], ccadj_);
5076 store_regs_bt(regs[t].regmap,regs[t].dirty,cinfo[i].ba+4);
5077 load_regs_bt(regs[t].regmap,regs[t].dirty,cinfo[i].ba+4);
5078 if(internal_branch(cinfo[i].ba+4))
5079 assem_debug("branch: internal\n");
5081 assem_debug("branch: external\n");
5082 assert(internal_branch(cinfo[i].ba+4));
5083 add_to_linker(out,cinfo[i].ba+4,internal_branch(cinfo[i].ba+4));
5087 // Load 2 immediates optimizing for small code size
5088 static void emit_mov2imm_compact(int imm1,u_int rt1,int imm2,u_int rt2)
5090 emit_movimm(imm1,rt1);
5091 emit_movimm_from(imm1,rt1,imm2,rt2);
5094 static void do_cc(int i, const signed char i_regmap[], int *adj,
5095 int addr, int taken, int invert)
5097 int count, count_plus2;
5101 if(dops[i].itype==RJUMP)
5105 //if(cinfo[i].ba>=start && cinfo[i].ba<(start+slen*4))
5106 if(internal_branch(cinfo[i].ba))
5108 t=(cinfo[i].ba-start)>>2;
5109 if(dops[t].is_ds) *adj=-CLOCK_ADJUST(1); // Branch into delay slot adds an extra cycle
5110 else *adj=cinfo[t].ccadj;
5116 count = cinfo[i].ccadj;
5117 count_plus2 = count + CLOCK_ADJUST(2);
5118 if(taken==TAKEN && i==(cinfo[i].ba-start)>>2 && source[i+1]==0) {
5120 if(count&1) emit_addimm_and_set_flags(2*(count+2),HOST_CCREG);
5122 //emit_subfrommem(&idlecount,HOST_CCREG); // Count idle cycles
5123 emit_andimm(HOST_CCREG,3,HOST_CCREG);
5127 else if(*adj==0||invert) {
5128 int cycles = count_plus2;
5133 if(-NO_CYCLE_PENALTY_THR<rel&&rel<0)
5134 cycles=*adj+count+2-*adj;
5137 emit_addimm_and_set_flags(cycles, HOST_CCREG);
5143 emit_cmpimm(HOST_CCREG, -count_plus2);
5147 add_stub(CC_STUB,jaddr,idle?idle:out,(*adj==0||invert||idle)?0:count_plus2,i,addr,taken,0);
5150 static void do_ccstub(int n)
5153 assem_debug("do_ccstub %x\n",start+(u_int)stubs[n].b*4);
5154 set_jump_target(stubs[n].addr, out);
5156 if(stubs[n].d==NULLDS) {
5157 // Delay slot instruction is nullified ("likely" branch)
5158 wb_dirtys(regs[i].regmap,regs[i].dirty);
5160 else if(stubs[n].d!=TAKEN) {
5161 wb_dirtys(branch_regs[i].regmap,branch_regs[i].dirty);
5164 if(internal_branch(cinfo[i].ba))
5165 wb_needed_dirtys(branch_regs[i].regmap,branch_regs[i].dirty,cinfo[i].ba);
5169 // Save PC as return address
5170 emit_movimm(stubs[n].c,0);
5171 emit_writeword(0,&pcaddr);
5175 // Return address depends on which way the branch goes
5176 if(dops[i].itype==CJUMP||dops[i].itype==SJUMP)
5178 int s1l=get_reg(branch_regs[i].regmap,dops[i].rs1);
5179 int s2l=get_reg(branch_regs[i].regmap,dops[i].rs2);
5185 else if(dops[i].rs2==0)
5190 #ifdef DESTRUCTIVE_WRITEBACK
5192 if((branch_regs[i].dirty>>s1l)&&1)
5193 emit_loadreg(dops[i].rs1,s1l);
5196 if((branch_regs[i].dirty>>s1l)&1)
5197 emit_loadreg(dops[i].rs2,s1l);
5200 if((branch_regs[i].dirty>>s2l)&1)
5201 emit_loadreg(dops[i].rs2,s2l);
5204 int addr=-1,alt=-1,ntaddr=-1;
5207 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
5208 branch_regs[i].regmap[hr]!=dops[i].rs1 &&
5209 branch_regs[i].regmap[hr]!=dops[i].rs2 )
5217 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
5218 branch_regs[i].regmap[hr]!=dops[i].rs1 &&
5219 branch_regs[i].regmap[hr]!=dops[i].rs2 )
5225 if ((dops[i].opcode & 0x3e) == 6) // BLEZ/BGTZ needs another register
5229 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
5230 branch_regs[i].regmap[hr]!=dops[i].rs1 &&
5231 branch_regs[i].regmap[hr]!=dops[i].rs2 )
5237 assert(hr<HOST_REGS);
5239 if (dops[i].opcode == 4) // BEQ
5241 #ifdef HAVE_CMOV_IMM
5242 if(s2l>=0) emit_cmp(s1l,s2l);
5243 else emit_test(s1l,s1l);
5244 emit_cmov2imm_e_ne_compact(cinfo[i].ba,start+i*4+8,addr);
5246 emit_mov2imm_compact(cinfo[i].ba,addr,start+i*4+8,alt);
5247 if(s2l>=0) emit_cmp(s1l,s2l);
5248 else emit_test(s1l,s1l);
5249 emit_cmovne_reg(alt,addr);
5252 else if (dops[i].opcode == 5) // BNE
5254 #ifdef HAVE_CMOV_IMM
5255 if(s2l>=0) emit_cmp(s1l,s2l);
5256 else emit_test(s1l,s1l);
5257 emit_cmov2imm_e_ne_compact(start+i*4+8,cinfo[i].ba,addr);
5259 emit_mov2imm_compact(start+i*4+8,addr,cinfo[i].ba,alt);
5260 if(s2l>=0) emit_cmp(s1l,s2l);
5261 else emit_test(s1l,s1l);
5262 emit_cmovne_reg(alt,addr);
5265 else if (dops[i].opcode == 6) // BLEZ
5267 //emit_movimm(cinfo[i].ba,alt);
5268 //emit_movimm(start+i*4+8,addr);
5269 emit_mov2imm_compact(cinfo[i].ba,alt,start+i*4+8,addr);
5271 emit_cmovl_reg(alt,addr);
5273 else if (dops[i].opcode == 7) // BGTZ
5275 //emit_movimm(cinfo[i].ba,addr);
5276 //emit_movimm(start+i*4+8,ntaddr);
5277 emit_mov2imm_compact(cinfo[i].ba,addr,start+i*4+8,ntaddr);
5279 emit_cmovl_reg(ntaddr,addr);
5281 else if (dops[i].itype == SJUMP) // BLTZ/BGEZ
5283 //emit_movimm(cinfo[i].ba,alt);
5284 //emit_movimm(start+i*4+8,addr);
5285 emit_mov2imm_compact(cinfo[i].ba,
5286 (dops[i].opcode2 & 1) ? addr : alt, start + i*4 + 8,
5287 (dops[i].opcode2 & 1) ? alt : addr);
5289 emit_cmovs_reg(alt,addr);
5291 emit_writeword(addr, &pcaddr);
5294 if(dops[i].itype==RJUMP)
5296 int r=get_reg(branch_regs[i].regmap,dops[i].rs1);
5297 if (ds_writes_rjump_rs(i)) {
5298 r=get_reg(branch_regs[i].regmap,RTEMP);
5300 emit_writeword(r,&pcaddr);
5302 else {SysPrintf("Unknown branch type in do_ccstub\n");abort();}
5304 // Update cycle count
5305 assert(branch_regs[i].regmap[HOST_CCREG]==CCREG||branch_regs[i].regmap[HOST_CCREG]==-1);
5306 if(stubs[n].a) emit_addimm(HOST_CCREG,(int)stubs[n].a,HOST_CCREG);
5307 emit_far_call(cc_interrupt);
5308 if(stubs[n].a) emit_addimm(HOST_CCREG,-(int)stubs[n].a,HOST_CCREG);
5309 if(stubs[n].d==TAKEN) {
5310 if(internal_branch(cinfo[i].ba))
5311 load_needed_regs(branch_regs[i].regmap,regs[(cinfo[i].ba-start)>>2].regmap_entry);
5312 else if(dops[i].itype==RJUMP) {
5313 if(get_reg(branch_regs[i].regmap,RTEMP)>=0)
5314 emit_readword(&pcaddr,get_reg(branch_regs[i].regmap,RTEMP));
5316 emit_loadreg(dops[i].rs1,get_reg(branch_regs[i].regmap,dops[i].rs1));
5318 }else if(stubs[n].d==NOTTAKEN) {
5319 if(i<slen-2) load_needed_regs(branch_regs[i].regmap,regmap_pre[i+2]);
5320 else load_all_regs(branch_regs[i].regmap);
5321 }else if(stubs[n].d==NULLDS) {
5322 // Delay slot instruction is nullified ("likely" branch)
5323 if(i<slen-2) load_needed_regs(regs[i].regmap,regmap_pre[i+2]);
5324 else load_all_regs(regs[i].regmap);
5326 load_all_regs(branch_regs[i].regmap);
5328 if (stubs[n].retaddr)
5329 emit_jmp(stubs[n].retaddr);
5331 do_jump_vaddr(stubs[n].e);
5334 static void add_to_linker(void *addr, u_int target, int is_internal)
5336 assert(linkcount < ARRAY_SIZE(link_addr));
5337 link_addr[linkcount].addr = addr;
5338 link_addr[linkcount].target = target;
5339 link_addr[linkcount].internal = is_internal;
5343 static void ujump_assemble_write_ra(int i)
5346 unsigned int return_address;
5347 rt=get_reg(branch_regs[i].regmap,31);
5348 assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5350 return_address=start+i*4+8;
5353 if(internal_branch(return_address)&&dops[i+1].rt1!=31) {
5354 int temp=-1; // note: must be ds-safe
5358 if(temp>=0) do_miniht_insert(return_address,rt,temp);
5359 else emit_movimm(return_address,rt);
5367 if(i_regmap[temp]!=PTEMP) emit_movimm((uintptr_t)hash_table_get(return_address),temp);
5370 emit_movimm(return_address,rt); // PC into link register
5372 emit_prefetch(hash_table_get(return_address));
5378 static void ujump_assemble(int i, const struct regstat *i_regs)
5381 if(i==(cinfo[i].ba-start)>>2) assem_debug("idle loop\n");
5382 address_generation(i+1,i_regs,regs[i].regmap_entry);
5384 int temp=get_reg(branch_regs[i].regmap,PTEMP);
5385 if(dops[i].rt1==31&&temp>=0)
5387 signed char *i_regmap=i_regs->regmap;
5388 int return_address=start+i*4+8;
5389 if(get_reg(branch_regs[i].regmap,31)>0)
5390 if(i_regmap[temp]==PTEMP) emit_movimm((uintptr_t)hash_table_get(return_address),temp);
5393 if(dops[i].rt1==31&&(dops[i].rt1==dops[i+1].rs1||dops[i].rt1==dops[i+1].rs2)) {
5394 ujump_assemble_write_ra(i); // writeback ra for DS
5397 ds_assemble(i+1,i_regs);
5398 uint64_t bc_unneeded=branch_regs[i].u;
5399 bc_unneeded|=1|(1LL<<dops[i].rt1);
5400 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,bc_unneeded);
5401 load_reg(regs[i].regmap,branch_regs[i].regmap,CCREG);
5402 if(!ra_done&&dops[i].rt1==31)
5403 ujump_assemble_write_ra(i);
5405 cc=get_reg(branch_regs[i].regmap,CCREG);
5406 assert(cc==HOST_CCREG);
5407 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,cinfo[i].ba);
5409 if(dops[i].rt1==31&&temp>=0) emit_prefetchreg(temp);
5411 do_cc(i,branch_regs[i].regmap,&adj,cinfo[i].ba,TAKEN,0);
5412 if(adj) emit_addimm(cc, cinfo[i].ccadj + CLOCK_ADJUST(2) - adj, cc);
5413 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,cinfo[i].ba);
5414 if(internal_branch(cinfo[i].ba))
5415 assem_debug("branch: internal\n");
5417 assem_debug("branch: external\n");
5418 if (internal_branch(cinfo[i].ba) && dops[(cinfo[i].ba-start)>>2].is_ds) {
5419 ds_assemble_entry(i);
5422 add_to_linker(out,cinfo[i].ba,internal_branch(cinfo[i].ba));
5427 static void rjump_assemble_write_ra(int i)
5429 int rt,return_address;
5430 assert(dops[i+1].rt1!=dops[i].rt1);
5431 assert(dops[i+1].rt2!=dops[i].rt1);
5432 rt=get_reg_w(branch_regs[i].regmap, dops[i].rt1);
5433 assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5435 return_address=start+i*4+8;
5439 if(i_regmap[temp]!=PTEMP) emit_movimm((uintptr_t)hash_table_get(return_address),temp);
5442 emit_movimm(return_address,rt); // PC into link register
5444 emit_prefetch(hash_table_get(return_address));
5448 static void rjump_assemble(int i, const struct regstat *i_regs)
5453 rs=get_reg(branch_regs[i].regmap,dops[i].rs1);
5455 if (ds_writes_rjump_rs(i)) {
5456 // Delay slot abuse, make a copy of the branch address register
5457 temp=get_reg(branch_regs[i].regmap,RTEMP);
5459 assert(regs[i].regmap[temp]==RTEMP);
5463 address_generation(i+1,i_regs,regs[i].regmap_entry);
5467 if((temp=get_reg(branch_regs[i].regmap,PTEMP))>=0) {
5468 signed char *i_regmap=i_regs->regmap;
5469 int return_address=start+i*4+8;
5470 if(i_regmap[temp]==PTEMP) emit_movimm((uintptr_t)hash_table_get(return_address),temp);
5475 if(dops[i].rs1==31) {
5476 int rh=get_reg(regs[i].regmap,RHASH);
5477 if(rh>=0) do_preload_rhash(rh);
5480 if(dops[i].rt1!=0&&(dops[i].rt1==dops[i+1].rs1||dops[i].rt1==dops[i+1].rs2)) {
5481 rjump_assemble_write_ra(i);
5484 ds_assemble(i+1,i_regs);
5485 uint64_t bc_unneeded=branch_regs[i].u;
5486 bc_unneeded|=1|(1LL<<dops[i].rt1);
5487 bc_unneeded&=~(1LL<<dops[i].rs1);
5488 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,bc_unneeded);
5489 load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i].rs1,CCREG);
5490 if(!ra_done&&dops[i].rt1!=0)
5491 rjump_assemble_write_ra(i);
5492 cc=get_reg(branch_regs[i].regmap,CCREG);
5493 assert(cc==HOST_CCREG);
5496 int rh=get_reg(branch_regs[i].regmap,RHASH);
5497 int ht=get_reg(branch_regs[i].regmap,RHTBL);
5498 if(dops[i].rs1==31) {
5499 if(regs[i].regmap[rh]!=RHASH) do_preload_rhash(rh);
5500 do_preload_rhtbl(ht);
5504 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,-1);
5505 #ifdef DESTRUCTIVE_WRITEBACK
5506 if((branch_regs[i].dirty>>rs)&1) {
5507 if(dops[i].rs1!=dops[i+1].rt1&&dops[i].rs1!=dops[i+1].rt2) {
5508 emit_loadreg(dops[i].rs1,rs);
5513 if(dops[i].rt1==31&&temp>=0) emit_prefetchreg(temp);
5516 if(dops[i].rs1==31) {
5517 do_miniht_load(ht,rh);
5520 //do_cc(i,branch_regs[i].regmap,&adj,-1,TAKEN);
5521 //if(adj) emit_addimm(cc,2*(cinfo[i].ccadj+2-adj),cc); // ??? - Shouldn't happen
5523 emit_addimm_and_set_flags(cinfo[i].ccadj + CLOCK_ADJUST(2), HOST_CCREG);
5524 add_stub(CC_STUB,out,NULL,0,i,-1,TAKEN,rs);
5525 if (dops[i+1].itype == RFE)
5526 // special case for RFE
5530 //load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,-1);
5532 if(dops[i].rs1==31) {
5533 do_miniht_jump(rs,rh,ht);
5540 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5541 if(dops[i].rt1!=31&&i<slen-2&&(((u_int)out)&7)) emit_mov(13,13);
5545 static void cjump_assemble(int i, const struct regstat *i_regs)
5547 const signed char *i_regmap = i_regs->regmap;
5550 match=match_bt(branch_regs[i].regmap,branch_regs[i].dirty,cinfo[i].ba);
5551 assem_debug("match=%d\n",match);
5553 int unconditional=0,nop=0;
5555 int internal=internal_branch(cinfo[i].ba);
5556 if(i==(cinfo[i].ba-start)>>2) assem_debug("idle loop\n");
5557 if(!match) invert=1;
5558 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5559 if(i>(cinfo[i].ba-start)>>2) invert=1;
5562 invert=1; // because of near cond. branches
5566 s1l=get_reg(branch_regs[i].regmap,dops[i].rs1);
5567 s2l=get_reg(branch_regs[i].regmap,dops[i].rs2);
5570 s1l=get_reg(i_regmap,dops[i].rs1);
5571 s2l=get_reg(i_regmap,dops[i].rs2);
5573 if(dops[i].rs1==0&&dops[i].rs2==0)
5575 if(dops[i].opcode&1) nop=1;
5576 else unconditional=1;
5577 //assert(dops[i].opcode!=5);
5578 //assert(dops[i].opcode!=7);
5579 //assert(dops[i].opcode!=0x15);
5580 //assert(dops[i].opcode!=0x17);
5582 else if(dops[i].rs1==0)
5587 else if(dops[i].rs2==0)
5593 // Out of order execution (delay slot first)
5595 address_generation(i+1,i_regs,regs[i].regmap_entry);
5596 ds_assemble(i+1,i_regs);
5598 uint64_t bc_unneeded=branch_regs[i].u;
5599 bc_unneeded&=~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
5601 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,bc_unneeded);
5602 load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i].rs1,dops[i].rs2);
5603 load_reg(regs[i].regmap,branch_regs[i].regmap,CCREG);
5604 cc=get_reg(branch_regs[i].regmap,CCREG);
5605 assert(cc==HOST_CCREG);
5607 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,cinfo[i].ba);
5608 //do_cc(i,branch_regs[i].regmap,&adj,unconditional?cinfo[i].ba:-1,unconditional);
5609 //assem_debug("cycle count (adj)\n");
5611 do_cc(i,branch_regs[i].regmap,&adj,cinfo[i].ba,TAKEN,0);
5612 if(i!=(cinfo[i].ba-start)>>2 || source[i+1]!=0) {
5613 if(adj) emit_addimm(cc, cinfo[i].ccadj + CLOCK_ADJUST(2) - adj, cc);
5614 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,cinfo[i].ba);
5616 assem_debug("branch: internal\n");
5618 assem_debug("branch: external\n");
5619 if (internal && dops[(cinfo[i].ba-start)>>2].is_ds) {
5620 ds_assemble_entry(i);
5623 add_to_linker(out,cinfo[i].ba,internal);
5626 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5627 if(((u_int)out)&7) emit_addnop(0);
5632 emit_addimm_and_set_flags(cinfo[i].ccadj + CLOCK_ADJUST(2), cc);
5635 add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0);
5638 void *taken = NULL, *nottaken = NULL, *nottaken1 = NULL;
5639 do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
5640 if(adj&&!invert) emit_addimm(cc, cinfo[i].ccadj + CLOCK_ADJUST(2) - adj, cc);
5642 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5644 if(dops[i].opcode==4) // BEQ
5646 if(s2l>=0) emit_cmp(s1l,s2l);
5647 else emit_test(s1l,s1l);
5652 add_to_linker(out,cinfo[i].ba,internal);
5656 if(dops[i].opcode==5) // BNE
5658 if(s2l>=0) emit_cmp(s1l,s2l);
5659 else emit_test(s1l,s1l);
5664 add_to_linker(out,cinfo[i].ba,internal);
5668 if(dops[i].opcode==6) // BLEZ
5675 add_to_linker(out,cinfo[i].ba,internal);
5679 if(dops[i].opcode==7) // BGTZ
5686 add_to_linker(out,cinfo[i].ba,internal);
5691 if(taken) set_jump_target(taken, out);
5692 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5693 if (match && (!internal || !dops[(cinfo[i].ba-start)>>2].is_ds)) {
5695 emit_addimm(cc,-adj,cc);
5696 add_to_linker(out,cinfo[i].ba,internal);
5699 add_to_linker(out,cinfo[i].ba,internal*2);
5705 if(adj) emit_addimm(cc,-adj,cc);
5706 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,cinfo[i].ba);
5707 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,cinfo[i].ba);
5709 assem_debug("branch: internal\n");
5711 assem_debug("branch: external\n");
5712 if (internal && dops[(cinfo[i].ba - start) >> 2].is_ds) {
5713 ds_assemble_entry(i);
5716 add_to_linker(out,cinfo[i].ba,internal);
5720 set_jump_target(nottaken, out);
5723 if(nottaken1) set_jump_target(nottaken1, out);
5725 if(!invert) emit_addimm(cc,adj,cc);
5727 } // (!unconditional)
5731 // In-order execution (branch first)
5732 void *taken = NULL, *nottaken = NULL, *nottaken1 = NULL;
5733 if(!unconditional&&!nop) {
5734 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5736 if((dops[i].opcode&0x2f)==4) // BEQ
5738 if(s2l>=0) emit_cmp(s1l,s2l);
5739 else emit_test(s1l,s1l);
5743 if((dops[i].opcode&0x2f)==5) // BNE
5745 if(s2l>=0) emit_cmp(s1l,s2l);
5746 else emit_test(s1l,s1l);
5750 if((dops[i].opcode&0x2f)==6) // BLEZ
5756 if((dops[i].opcode&0x2f)==7) // BGTZ
5762 } // if(!unconditional)
5764 uint64_t ds_unneeded=branch_regs[i].u;
5765 ds_unneeded&=~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2));
5769 if(taken) set_jump_target(taken, out);
5770 assem_debug("1:\n");
5771 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,ds_unneeded);
5773 load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i+1].rs1,dops[i+1].rs2);
5774 address_generation(i+1,&branch_regs[i],0);
5776 load_reg(regs[i].regmap,branch_regs[i].regmap,ROREG);
5777 load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,INVCP);
5778 ds_assemble(i+1,&branch_regs[i]);
5779 cc=get_reg(branch_regs[i].regmap,CCREG);
5781 emit_loadreg(CCREG,cc=HOST_CCREG);
5782 // CHECK: Is the following instruction (fall thru) allocated ok?
5784 assert(cc==HOST_CCREG);
5785 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,cinfo[i].ba);
5786 do_cc(i,i_regmap,&adj,cinfo[i].ba,TAKEN,0);
5787 assem_debug("cycle count (adj)\n");
5788 if(adj) emit_addimm(cc, cinfo[i].ccadj + CLOCK_ADJUST(2) - adj, cc);
5789 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,cinfo[i].ba);
5791 assem_debug("branch: internal\n");
5793 assem_debug("branch: external\n");
5794 if (internal && dops[(cinfo[i].ba - start) >> 2].is_ds) {
5795 ds_assemble_entry(i);
5798 add_to_linker(out,cinfo[i].ba,internal);
5803 if(!unconditional) {
5804 if(nottaken1) set_jump_target(nottaken1, out);
5805 set_jump_target(nottaken, out);
5806 assem_debug("2:\n");
5807 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,ds_unneeded);
5809 load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i+1].rs1,dops[i+1].rs2);
5810 address_generation(i+1,&branch_regs[i],0);
5812 load_reg(regs[i].regmap,branch_regs[i].regmap,ROREG);
5813 load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,INVCP);
5814 ds_assemble(i+1,&branch_regs[i]);
5815 cc=get_reg(branch_regs[i].regmap,CCREG);
5817 // Cycle count isn't in a register, temporarily load it then write it out
5818 emit_loadreg(CCREG,HOST_CCREG);
5819 emit_addimm_and_set_flags(cinfo[i].ccadj + CLOCK_ADJUST(2), HOST_CCREG);
5822 add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0);
5823 emit_storereg(CCREG,HOST_CCREG);
5826 cc=get_reg(i_regmap,CCREG);
5827 assert(cc==HOST_CCREG);
5828 emit_addimm_and_set_flags(cinfo[i].ccadj + CLOCK_ADJUST(2), cc);
5831 add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0);
5837 static void sjump_assemble(int i, const struct regstat *i_regs)
5839 const signed char *i_regmap = i_regs->regmap;
5842 match=match_bt(branch_regs[i].regmap,branch_regs[i].dirty,cinfo[i].ba);
5843 assem_debug("smatch=%d ooo=%d\n", match, dops[i].ooo);
5845 int unconditional=0,nevertaken=0;
5847 int internal=internal_branch(cinfo[i].ba);
5848 if(i==(cinfo[i].ba-start)>>2) assem_debug("idle loop\n");
5849 if(!match) invert=1;
5850 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5851 if(i>(cinfo[i].ba-start)>>2) invert=1;
5854 invert=1; // because of near cond. branches
5857 //if(dops[i].opcode2>=0x10) return; // FIXME (BxxZAL)
5858 //assert(dops[i].opcode2<0x10||dops[i].rs1==0); // FIXME (BxxZAL)
5861 s1l=get_reg(branch_regs[i].regmap,dops[i].rs1);
5864 s1l=get_reg(i_regmap,dops[i].rs1);
5868 if(dops[i].opcode2&1) unconditional=1;
5870 // These are never taken (r0 is never less than zero)
5871 //assert(dops[i].opcode2!=0);
5872 //assert(dops[i].opcode2!=2);
5873 //assert(dops[i].opcode2!=0x10);
5874 //assert(dops[i].opcode2!=0x12);
5878 // Out of order execution (delay slot first)
5880 address_generation(i+1,i_regs,regs[i].regmap_entry);
5881 ds_assemble(i+1,i_regs);
5883 uint64_t bc_unneeded=branch_regs[i].u;
5884 bc_unneeded&=~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
5886 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,bc_unneeded);
5887 load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i].rs1,dops[i].rs1);
5888 load_reg(regs[i].regmap,branch_regs[i].regmap,CCREG);
5889 if(dops[i].rt1==31) {
5890 int rt,return_address;
5891 rt=get_reg(branch_regs[i].regmap,31);
5892 assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5894 // Save the PC even if the branch is not taken
5895 return_address=start+i*4+8;
5896 emit_movimm(return_address,rt); // PC into link register
5898 if(!nevertaken) emit_prefetch(hash_table_get(return_address));
5902 cc=get_reg(branch_regs[i].regmap,CCREG);
5903 assert(cc==HOST_CCREG);
5905 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,cinfo[i].ba);
5906 //do_cc(i,branch_regs[i].regmap,&adj,unconditional?cinfo[i].ba:-1,unconditional);
5907 assem_debug("cycle count (adj)\n");
5909 do_cc(i,branch_regs[i].regmap,&adj,cinfo[i].ba,TAKEN,0);
5910 if(i!=(cinfo[i].ba-start)>>2 || source[i+1]!=0) {
5911 if(adj) emit_addimm(cc, cinfo[i].ccadj + CLOCK_ADJUST(2) - adj, cc);
5912 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,cinfo[i].ba);
5914 assem_debug("branch: internal\n");
5916 assem_debug("branch: external\n");
5917 if (internal && dops[(cinfo[i].ba - start) >> 2].is_ds) {
5918 ds_assemble_entry(i);
5921 add_to_linker(out,cinfo[i].ba,internal);
5924 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5925 if(((u_int)out)&7) emit_addnop(0);
5929 else if(nevertaken) {
5930 emit_addimm_and_set_flags(cinfo[i].ccadj + CLOCK_ADJUST(2), cc);
5933 add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0);
5936 void *nottaken = NULL;
5937 do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
5938 if(adj&&!invert) emit_addimm(cc, cinfo[i].ccadj + CLOCK_ADJUST(2) - adj, cc);
5941 if ((dops[i].opcode2 & 1) == 0) // BLTZ/BLTZAL
5948 add_to_linker(out,cinfo[i].ba,internal);
5959 add_to_linker(out,cinfo[i].ba,internal);
5966 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5967 if (match && (!internal || !dops[(cinfo[i].ba - start) >> 2].is_ds)) {
5969 emit_addimm(cc,-adj,cc);
5970 add_to_linker(out,cinfo[i].ba,internal);
5973 add_to_linker(out,cinfo[i].ba,internal*2);
5979 if(adj) emit_addimm(cc,-adj,cc);
5980 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,cinfo[i].ba);
5981 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,cinfo[i].ba);
5983 assem_debug("branch: internal\n");
5985 assem_debug("branch: external\n");
5986 if (internal && dops[(cinfo[i].ba - start) >> 2].is_ds) {
5987 ds_assemble_entry(i);
5990 add_to_linker(out,cinfo[i].ba,internal);
5994 set_jump_target(nottaken, out);
5998 if(!invert) emit_addimm(cc,adj,cc);
6000 } // (!unconditional)
6004 // In-order execution (branch first)
6006 void *nottaken = NULL;
6007 if (!unconditional) {
6009 emit_test(s1l, s1l);
6011 if (dops[i].rt1 == 31) {
6012 int rt, return_address;
6013 rt = get_reg(branch_regs[i].regmap,31);
6015 // Save the PC even if the branch is not taken
6016 return_address = start + i*4+8;
6017 emit_movimm(return_address, rt); // PC into link register
6019 emit_prefetch(hash_table_get(return_address));
6023 if (!unconditional) {
6025 if (!(dops[i].opcode2 & 1)) // BLTZ/BLTZAL
6031 uint64_t ds_unneeded=branch_regs[i].u;
6032 ds_unneeded&=~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2));
6036 //assem_debug("1:\n");
6037 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,ds_unneeded);
6039 load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i+1].rs1,dops[i+1].rs2);
6040 address_generation(i+1,&branch_regs[i],0);
6042 load_reg(regs[i].regmap,branch_regs[i].regmap,ROREG);
6043 load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,INVCP);
6044 ds_assemble(i+1,&branch_regs[i]);
6045 cc=get_reg(branch_regs[i].regmap,CCREG);
6047 emit_loadreg(CCREG,cc=HOST_CCREG);
6048 // CHECK: Is the following instruction (fall thru) allocated ok?
6050 assert(cc==HOST_CCREG);
6051 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,cinfo[i].ba);
6052 do_cc(i,i_regmap,&adj,cinfo[i].ba,TAKEN,0);
6053 assem_debug("cycle count (adj)\n");
6054 if(adj) emit_addimm(cc, cinfo[i].ccadj + CLOCK_ADJUST(2) - adj, cc);
6055 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,cinfo[i].ba);
6057 assem_debug("branch: internal\n");
6059 assem_debug("branch: external\n");
6060 if (internal && dops[(cinfo[i].ba - start) >> 2].is_ds) {
6061 ds_assemble_entry(i);
6064 add_to_linker(out,cinfo[i].ba,internal);
6069 if(!unconditional) {
6070 set_jump_target(nottaken, out);
6071 assem_debug("1:\n");
6072 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,ds_unneeded);
6073 load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i+1].rs1,dops[i+1].rs2);
6074 address_generation(i+1,&branch_regs[i],0);
6076 load_reg(regs[i].regmap,branch_regs[i].regmap,ROREG);
6077 load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,INVCP);
6078 ds_assemble(i+1,&branch_regs[i]);
6079 cc=get_reg(branch_regs[i].regmap,CCREG);
6081 // Cycle count isn't in a register, temporarily load it then write it out
6082 emit_loadreg(CCREG,HOST_CCREG);
6083 emit_addimm_and_set_flags(cinfo[i].ccadj + CLOCK_ADJUST(2), HOST_CCREG);
6086 add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0);
6087 emit_storereg(CCREG,HOST_CCREG);
6090 cc=get_reg(i_regmap,CCREG);
6091 assert(cc==HOST_CCREG);
6092 emit_addimm_and_set_flags(cinfo[i].ccadj + CLOCK_ADJUST(2), cc);
6095 add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0);
6101 static void check_regmap(signed char *regmap)
6105 for (i = 0; i < HOST_REGS; i++) {
6108 for (j = i + 1; j < HOST_REGS; j++)
6109 assert(regmap[i] != regmap[j]);
6115 #include <inttypes.h>
6116 static char insn[MAXBLOCK][10];
6118 #define set_mnemonic(i_, n_) \
6119 strcpy(insn[i_], n_)
6121 void print_regmap(const char *name, const signed char *regmap)
6125 fputs(name, stdout);
6126 for (i = 0; i < HOST_REGS; i++) {
6129 l = snprintf(buf, sizeof(buf), "$%d", regmap[i]);
6133 printf(" r%d=%s", i, buf);
6135 fputs("\n", stdout);
6139 void disassemble_inst(int i)
6141 if (dops[i].bt) printf("*"); else printf(" ");
6142 switch(dops[i].itype) {
6144 printf (" %x: %s %8x\n",start+i*4,insn[i],cinfo[i].ba);break;
6146 printf (" %x: %s r%d,r%d,%8x\n",start+i*4,insn[i],dops[i].rs1,dops[i].rs2,i?start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14):cinfo[i].ba);break;
6148 printf (" %x: %s r%d,%8x\n",start+i*4,insn[i],dops[i].rs1,start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14));break;
6150 if (dops[i].opcode2 == 9 && dops[i].rt1 != 31)
6151 printf (" %x: %s r%d,r%d\n",start+i*4,insn[i],dops[i].rt1,dops[i].rs1);
6153 printf (" %x: %s r%d\n",start+i*4,insn[i],dops[i].rs1);
6156 if(dops[i].opcode==0xf) //LUI
6157 printf (" %x: %s r%d,%4x0000\n",start+i*4,insn[i],dops[i].rt1,cinfo[i].imm&0xffff);
6159 printf (" %x: %s r%d,r%d,%d\n",start+i*4,insn[i],dops[i].rt1,dops[i].rs1,cinfo[i].imm);
6163 printf (" %x: %s r%d,r%d+%x\n",start+i*4,insn[i],dops[i].rt1,dops[i].rs1,cinfo[i].imm);
6167 printf (" %x: %s r%d,r%d+%x\n",start+i*4,insn[i],dops[i].rs2,dops[i].rs1,cinfo[i].imm);
6171 printf (" %x: %s r%d,r%d,r%d\n",start+i*4,insn[i],dops[i].rt1,dops[i].rs1,dops[i].rs2);
6174 printf (" %x: %s r%d,r%d\n",start+i*4,insn[i],dops[i].rs1,dops[i].rs2);
6177 printf (" %x: %s r%d,r%d,%d\n",start+i*4,insn[i],dops[i].rt1,dops[i].rs1,cinfo[i].imm);
6180 if((dops[i].opcode2&0x1d)==0x10)
6181 printf (" %x: %s r%d\n",start+i*4,insn[i],dops[i].rt1);
6182 else if((dops[i].opcode2&0x1d)==0x11)
6183 printf (" %x: %s r%d\n",start+i*4,insn[i],dops[i].rs1);
6185 printf (" %x: %s\n",start+i*4,insn[i]);
6188 if(dops[i].opcode2==0)
6189 printf (" %x: %s r%d,cpr0[%d]\n",start+i*4,insn[i],dops[i].rt1,(source[i]>>11)&0x1f); // MFC0
6190 else if(dops[i].opcode2==4)
6191 printf (" %x: %s r%d,cpr0[%d]\n",start+i*4,insn[i],dops[i].rs1,(source[i]>>11)&0x1f); // MTC0
6192 else printf (" %x: %s\n",start+i*4,insn[i]);
6195 if(dops[i].opcode2<3)
6196 printf (" %x: %s r%d,cpr2[%d]\n",start+i*4,insn[i],dops[i].rt1,(source[i]>>11)&0x1f); // MFC2
6197 else if(dops[i].opcode2>3)
6198 printf (" %x: %s r%d,cpr2[%d]\n",start+i*4,insn[i],dops[i].rs1,(source[i]>>11)&0x1f); // MTC2
6199 else printf (" %x: %s\n",start+i*4,insn[i]);
6202 printf (" %x: %s cpr2[%d],r%d+%x\n",start+i*4,insn[i],(source[i]>>16)&0x1f,dops[i].rs1,cinfo[i].imm);
6205 printf (" %x: %s (INTCALL)\n",start+i*4,insn[i]);
6208 //printf (" %s %8x\n",insn[i],source[i]);
6209 printf (" %x: %s\n",start+i*4,insn[i]);
6211 #ifndef REGMAP_PRINT
6214 printf("D: %"PRIx64" WD: %"PRIx64" U: %"PRIx64" hC: %x hWC: %x hLC: %x\n",
6215 regs[i].dirty, regs[i].wasdirty, unneeded_reg[i],
6216 regs[i].isconst, regs[i].wasconst, regs[i].loadedconst);
6217 print_regmap("pre: ", regmap_pre[i]);
6218 print_regmap("entry: ", regs[i].regmap_entry);
6219 print_regmap("map: ", regs[i].regmap);
6220 if (dops[i].is_jump) {
6221 print_regmap("bentry:", branch_regs[i].regmap_entry);
6222 print_regmap("bmap: ", branch_regs[i].regmap);
6226 #define set_mnemonic(i_, n_)
6227 static void disassemble_inst(int i) {}
6230 #define DRC_TEST_VAL 0x74657374
6232 static noinline void new_dynarec_test(void)
6234 int (*testfunc)(void);
6239 // check structure linkage
6240 if ((u_char *)rcnts - (u_char *)&psxRegs != sizeof(psxRegs))
6242 SysPrintf("linkage_arm* miscompilation/breakage detected.\n");
6245 SysPrintf("(%p) testing if we can run recompiled code @%p...\n",
6246 new_dynarec_test, out);
6247 ((volatile u_int *)NDRC_WRITE_OFFSET(out))[0]++; // make the cache dirty
6249 for (i = 0; i < ARRAY_SIZE(ret); i++) {
6250 out = ndrc->translation_cache;
6251 beginning = start_block();
6252 emit_movimm(DRC_TEST_VAL + i, 0); // test
6255 end_block(beginning);
6256 testfunc = beginning;
6257 ret[i] = testfunc();
6260 if (ret[0] == DRC_TEST_VAL && ret[1] == DRC_TEST_VAL + 1)
6261 SysPrintf("test passed.\n");
6263 SysPrintf("test failed, will likely crash soon (r=%08x %08x)\n", ret[0], ret[1]);
6264 out = ndrc->translation_cache;
6267 // clear the state completely, instead of just marking
6268 // things invalid like invalidate_all_pages() does
6269 void new_dynarec_clear_full(void)
6272 out = ndrc->translation_cache;
6273 memset(invalid_code,1,sizeof(invalid_code));
6274 memset(hash_table,0xff,sizeof(hash_table));
6275 memset(mini_ht,-1,sizeof(mini_ht));
6276 memset(shadow,0,sizeof(shadow));
6278 expirep = EXPIRITY_OFFSET;
6279 pending_exception=0;
6282 inv_code_start=inv_code_end=~0;
6285 for (n = 0; n < ARRAY_SIZE(blocks); n++)
6286 blocks_clear(&blocks[n]);
6287 for (n = 0; n < ARRAY_SIZE(jumps); n++) {
6291 stat_clear(stat_blocks);
6292 stat_clear(stat_links);
6294 cycle_multiplier_old = Config.cycle_multiplier;
6295 new_dynarec_hacks_old = new_dynarec_hacks;
6298 void new_dynarec_init(void)
6300 SysPrintf("Init new dynarec, ndrc size %x\n", (int)sizeof(*ndrc));
6305 #ifdef BASE_ADDR_DYNAMIC
6307 sceBlock = getVMBlock(); //sceKernelAllocMemBlockForVM("code", sizeof(*ndrc));
6309 SysPrintf("sceKernelAllocMemBlockForVM failed: %x\n", sceBlock);
6310 int ret = sceKernelGetMemBlockBase(sceBlock, (void **)&ndrc);
6312 SysPrintf("sceKernelGetMemBlockBase failed: %x\n", ret);
6313 sceKernelOpenVMDomain();
6314 sceClibPrintf("translation_cache = 0x%08lx\n ", (long)ndrc->translation_cache);
6315 #elif defined(_MSC_VER)
6316 ndrc = VirtualAlloc(NULL, sizeof(*ndrc), MEM_COMMIT | MEM_RESERVE,
6317 PAGE_EXECUTE_READWRITE);
6318 #elif defined(HAVE_LIBNX)
6319 Result rc = jitCreate(&g_jit, sizeof(*ndrc));
6321 SysPrintf("jitCreate failed: %08x\n", rc);
6322 SysPrintf("jitCreate: RX: %p RW: %p type: %d\n", g_jit.rx_addr, g_jit.rw_addr, g_jit.type);
6323 jitTransitionToWritable(&g_jit);
6324 ndrc = g_jit.rx_addr;
6325 ndrc_write_ofs = (char *)g_jit.rw_addr - (char *)ndrc;
6326 memset(NDRC_WRITE_OFFSET(&ndrc->tramp), 0, sizeof(ndrc->tramp));
6328 uintptr_t desired_addr = 0;
6329 int prot = PROT_READ | PROT_WRITE | PROT_EXEC;
6330 int flags = MAP_PRIVATE | MAP_ANONYMOUS;
6334 desired_addr = ((uintptr_t)&_end + 0xffffff) & ~0xffffffl;
6336 #ifdef TC_WRITE_OFFSET
6337 // mostly for testing
6338 fd = open("/dev/shm/pcsxr", O_CREAT | O_RDWR, 0600);
6339 ftruncate(fd, sizeof(*ndrc));
6340 void *mw = mmap(NULL, sizeof(*ndrc), PROT_READ | PROT_WRITE,
6341 (flags = MAP_SHARED), fd, 0);
6342 assert(mw != MAP_FAILED);
6343 prot = PROT_READ | PROT_EXEC;
6345 ndrc = mmap((void *)desired_addr, sizeof(*ndrc), prot, flags, fd, 0);
6346 if (ndrc == MAP_FAILED) {
6347 SysPrintf("mmap() failed: %s\n", strerror(errno));
6350 #ifdef TC_WRITE_OFFSET
6351 ndrc_write_ofs = (char *)mw - (char *)ndrc;
6355 #ifndef NO_WRITE_EXEC
6356 // not all systems allow execute in data segment by default
6357 // size must be 4K aligned for 3DS?
6358 if (mprotect(ndrc, sizeof(*ndrc),
6359 PROT_READ | PROT_WRITE | PROT_EXEC) != 0)
6360 SysPrintf("mprotect() failed: %s\n", strerror(errno));
6363 out = ndrc->translation_cache;
6364 new_dynarec_clear_full();
6366 // Copy this into local area so we don't have to put it in every literal pool
6367 invc_ptr=invalid_code;
6371 ram_offset=(uintptr_t)rdram-0x80000000;
6373 SysPrintf("warning: RAM is not directly mapped, performance will suffer\n");
6374 SysPrintf("Mapped (RAM/scrp/ROM/LUTs/TC):\n");
6375 SysPrintf("%p/%p/%p/%p/%p\n", psxM, psxH, psxR, mem_rtab, out);
6378 void new_dynarec_cleanup(void)
6381 #ifdef BASE_ADDR_DYNAMIC
6383 // sceBlock is managed by retroarch's bootstrap code
6384 //sceKernelFreeMemBlock(sceBlock);
6386 #elif defined(HAVE_LIBNX)
6390 if (munmap(ndrc, sizeof(*ndrc)) < 0)
6391 SysPrintf("munmap() failed\n");
6395 for (n = 0; n < ARRAY_SIZE(blocks); n++)
6396 blocks_clear(&blocks[n]);
6397 for (n = 0; n < ARRAY_SIZE(jumps); n++) {
6401 stat_clear(stat_blocks);
6402 stat_clear(stat_links);
6403 new_dynarec_print_stats();
6406 static u_int *get_source_start(u_int addr, u_int *limit)
6408 if (addr < 0x00200000 ||
6409 (0xa0000000 <= addr && addr < 0xa0200000))
6411 // used for BIOS calls mostly?
6412 *limit = (addr&0xa0000000)|0x00200000;
6413 return (u_int *)(rdram + (addr&0x1fffff));
6415 else if (!Config.HLE && (
6416 /* (0x9fc00000 <= addr && addr < 0x9fc80000) ||*/
6417 (0xbfc00000 <= addr && addr < 0xbfc80000)))
6419 // BIOS. The multiplier should be much higher as it's uncached 8bit mem,
6420 // but timings in PCSX are too tied to the interpreter's 2-per-insn assumption
6421 if (!HACK_ENABLED(NDHACK_OVERRIDE_CYCLE_M))
6422 cycle_multiplier_active = 200;
6424 *limit = (addr & 0xfff00000) | 0x80000;
6425 return (u_int *)((u_char *)psxR + (addr&0x7ffff));
6427 else if (addr >= 0x80000000 && addr < 0x80000000+RAM_SIZE) {
6428 *limit = (addr & 0x80600000) + 0x00200000;
6429 return (u_int *)(rdram + (addr&0x1fffff));
6434 static u_int scan_for_ret(u_int addr)
6439 mem = get_source_start(addr, &limit);
6443 if (limit > addr + 0x1000)
6444 limit = addr + 0x1000;
6445 for (; addr < limit; addr += 4, mem++) {
6446 if (*mem == 0x03e00008) // jr $ra
6452 struct savestate_block {
6457 static int addr_cmp(const void *p1_, const void *p2_)
6459 const struct savestate_block *p1 = p1_, *p2 = p2_;
6460 return p1->addr - p2->addr;
6463 int new_dynarec_save_blocks(void *save, int size)
6465 struct savestate_block *sblocks = save;
6466 int maxcount = size / sizeof(sblocks[0]);
6467 struct savestate_block tmp_blocks[1024];
6468 struct block_info *block;
6469 int p, s, d, o, bcnt;
6473 for (p = 0; p < ARRAY_SIZE(blocks); p++) {
6475 for (block = blocks[p]; block != NULL; block = block->next) {
6476 if (block->is_dirty)
6478 tmp_blocks[bcnt].addr = block->start;
6479 tmp_blocks[bcnt].regflags = block->reg_sv_flags;
6484 qsort(tmp_blocks, bcnt, sizeof(tmp_blocks[0]), addr_cmp);
6486 addr = tmp_blocks[0].addr;
6487 for (s = d = 0; s < bcnt; s++) {
6488 if (tmp_blocks[s].addr < addr)
6490 if (d == 0 || tmp_blocks[d-1].addr != tmp_blocks[s].addr)
6491 tmp_blocks[d++] = tmp_blocks[s];
6492 addr = scan_for_ret(tmp_blocks[s].addr);
6495 if (o + d > maxcount)
6497 memcpy(&sblocks[o], tmp_blocks, d * sizeof(sblocks[0]));
6501 return o * sizeof(sblocks[0]);
6504 void new_dynarec_load_blocks(const void *save, int size)
6506 const struct savestate_block *sblocks = save;
6507 int count = size / sizeof(sblocks[0]);
6508 struct block_info *block;
6509 u_int regs_save[32];
6514 // restore clean blocks, if any
6515 for (page = 0, b = i = 0; page < ARRAY_SIZE(blocks); page++) {
6516 for (block = blocks[page]; block != NULL; block = block->next, b++) {
6517 if (!block->is_dirty)
6519 assert(block->source && block->copy);
6520 if (memcmp(block->source, block->copy, block->len))
6523 // see try_restore_block
6524 block->is_dirty = 0;
6525 mark_invalid_code(block->start, block->len, 0);
6529 inv_debug("load_blocks: %d/%d clean blocks\n", i, b);
6531 // change GPRs for speculation to at least partially work..
6532 memcpy(regs_save, &psxRegs.GPR, sizeof(regs_save));
6533 for (i = 1; i < 32; i++)
6534 psxRegs.GPR.r[i] = 0x80000000;
6536 for (b = 0; b < count; b++) {
6537 for (f = sblocks[b].regflags, i = 0; f; f >>= 1, i++) {
6539 psxRegs.GPR.r[i] = 0x1f800000;
6542 ndrc_get_addr_ht(sblocks[b].addr);
6544 for (f = sblocks[b].regflags, i = 0; f; f >>= 1, i++) {
6546 psxRegs.GPR.r[i] = 0x80000000;
6550 memcpy(&psxRegs.GPR, regs_save, sizeof(regs_save));
6553 void new_dynarec_print_stats(void)
6556 printf("cc %3d,%3d,%3d lu%6d,%3d,%3d c%3d inv%3d,%3d tc_offs %zu b %u,%u\n",
6557 stat_bc_pre, stat_bc_direct, stat_bc_restore,
6558 stat_ht_lookups, stat_jump_in_lookups, stat_restore_tries,
6559 stat_restore_compares, stat_inv_addr_calls, stat_inv_hits,
6560 out - ndrc->translation_cache, stat_blocks, stat_links);
6561 stat_bc_direct = stat_bc_pre = stat_bc_restore =
6562 stat_ht_lookups = stat_jump_in_lookups = stat_restore_tries =
6563 stat_restore_compares = stat_inv_addr_calls = stat_inv_hits = 0;
6567 static int apply_hacks(void)
6570 if (HACK_ENABLED(NDHACK_NO_COMPAT_HACKS))
6572 /* special hack(s) */
6573 for (i = 0; i < slen - 4; i++)
6575 // lui a4, 0xf200; jal <rcnt_read>; addu a0, 2; slti v0, 28224
6576 if (source[i] == 0x3c04f200 && dops[i+1].itype == UJUMP
6577 && source[i+2] == 0x34840002 && dops[i+3].opcode == 0x0a
6578 && cinfo[i+3].imm == 0x6e40 && dops[i+3].rs1 == 2)
6580 SysPrintf("PE2 hack @%08x\n", start + (i+3)*4);
6581 dops[i + 3].itype = NOP;
6585 if (i > 10 && source[i-1] == 0 && source[i-2] == 0x03e00008
6586 && source[i-4] == 0x8fbf0018 && source[i-6] == 0x00c0f809
6587 && dops[i-7].itype == STORE)
6590 if (dops[i].itype == IMM16)
6592 // swl r2, 15(r6); swr r2, 12(r6); sw r6, *; jalr r6
6593 if (dops[i].itype == STORELR && dops[i].rs1 == 6
6594 && dops[i-1].itype == STORELR && dops[i-1].rs1 == 6)
6596 SysPrintf("F1 hack from %08x, old dst %08x\n", start, hack_addr);
6604 static noinline void pass1_disassemble(u_int pagelimit)
6606 int i, j, done = 0, ni_count = 0;
6607 unsigned int type,op,op2,op3;
6609 for (i = 0; !done; i++)
6611 int force_j_to_interpreter = 0;
6612 memset(&dops[i], 0, sizeof(dops[i]));
6613 memset(&cinfo[i], 0, sizeof(cinfo[i]));
6616 dops[i].opcode = op = source[i] >> 26;
6619 set_mnemonic(i, "???");
6622 case 0x00: set_mnemonic(i, "special");
6626 case 0x00: set_mnemonic(i, "SLL"); type=SHIFTIMM; break;
6627 case 0x02: set_mnemonic(i, "SRL"); type=SHIFTIMM; break;
6628 case 0x03: set_mnemonic(i, "SRA"); type=SHIFTIMM; break;
6629 case 0x04: set_mnemonic(i, "SLLV"); type=SHIFT; break;
6630 case 0x06: set_mnemonic(i, "SRLV"); type=SHIFT; break;
6631 case 0x07: set_mnemonic(i, "SRAV"); type=SHIFT; break;
6632 case 0x08: set_mnemonic(i, "JR"); type=RJUMP; break;
6633 case 0x09: set_mnemonic(i, "JALR"); type=RJUMP; break;
6634 case 0x0C: set_mnemonic(i, "SYSCALL"); type=SYSCALL; break;
6635 case 0x0D: set_mnemonic(i, "BREAK"); type=SYSCALL; break;
6636 case 0x0F: set_mnemonic(i, "SYNC"); type=OTHER; break;
6637 case 0x10: set_mnemonic(i, "MFHI"); type=MOV; break;
6638 case 0x11: set_mnemonic(i, "MTHI"); type=MOV; break;
6639 case 0x12: set_mnemonic(i, "MFLO"); type=MOV; break;
6640 case 0x13: set_mnemonic(i, "MTLO"); type=MOV; break;
6641 case 0x18: set_mnemonic(i, "MULT"); type=MULTDIV; break;
6642 case 0x19: set_mnemonic(i, "MULTU"); type=MULTDIV; break;
6643 case 0x1A: set_mnemonic(i, "DIV"); type=MULTDIV; break;
6644 case 0x1B: set_mnemonic(i, "DIVU"); type=MULTDIV; break;
6645 case 0x20: set_mnemonic(i, "ADD"); type=ALU; break;
6646 case 0x21: set_mnemonic(i, "ADDU"); type=ALU; break;
6647 case 0x22: set_mnemonic(i, "SUB"); type=ALU; break;
6648 case 0x23: set_mnemonic(i, "SUBU"); type=ALU; break;
6649 case 0x24: set_mnemonic(i, "AND"); type=ALU; break;
6650 case 0x25: set_mnemonic(i, "OR"); type=ALU; break;
6651 case 0x26: set_mnemonic(i, "XOR"); type=ALU; break;
6652 case 0x27: set_mnemonic(i, "NOR"); type=ALU; break;
6653 case 0x2A: set_mnemonic(i, "SLT"); type=ALU; break;
6654 case 0x2B: set_mnemonic(i, "SLTU"); type=ALU; break;
6657 case 0x01: set_mnemonic(i, "regimm");
6659 op2 = (source[i] >> 16) & 0x1f;
6662 case 0x10: set_mnemonic(i, "BLTZAL"); break;
6663 case 0x11: set_mnemonic(i, "BGEZAL"); break;
6666 set_mnemonic(i, "BGEZ");
6668 set_mnemonic(i, "BLTZ");
6671 case 0x02: set_mnemonic(i, "J"); type=UJUMP; break;
6672 case 0x03: set_mnemonic(i, "JAL"); type=UJUMP; break;
6673 case 0x04: set_mnemonic(i, "BEQ"); type=CJUMP; break;
6674 case 0x05: set_mnemonic(i, "BNE"); type=CJUMP; break;
6675 case 0x06: set_mnemonic(i, "BLEZ"); type=CJUMP; break;
6676 case 0x07: set_mnemonic(i, "BGTZ"); type=CJUMP; break;
6677 case 0x08: set_mnemonic(i, "ADDI"); type=IMM16; break;
6678 case 0x09: set_mnemonic(i, "ADDIU"); type=IMM16; break;
6679 case 0x0A: set_mnemonic(i, "SLTI"); type=IMM16; break;
6680 case 0x0B: set_mnemonic(i, "SLTIU"); type=IMM16; break;
6681 case 0x0C: set_mnemonic(i, "ANDI"); type=IMM16; break;
6682 case 0x0D: set_mnemonic(i, "ORI"); type=IMM16; break;
6683 case 0x0E: set_mnemonic(i, "XORI"); type=IMM16; break;
6684 case 0x0F: set_mnemonic(i, "LUI"); type=IMM16; break;
6685 case 0x10: set_mnemonic(i, "COP0");
6686 op2 = (source[i]>>21) & 0x1f;
6688 op3 = source[i] & 0x1f;
6691 case 0x01: case 0x02: case 0x06: case 0x08: type = INTCALL; break;
6692 case 0x10: set_mnemonic(i, "RFE"); type=RFE; break;
6693 default: type = OTHER; break;
6701 set_mnemonic(i, "MFC0");
6702 rd = (source[i] >> 11) & 0x1F;
6703 if (!(0x00000417u & (1u << rd)))
6706 case 0x04: set_mnemonic(i, "MTC0"); type=COP0; break;
6708 case 0x06: type = INTCALL; break;
6709 default: type = OTHER; break;
6712 case 0x11: set_mnemonic(i, "COP1");
6713 op2=(source[i]>>21)&0x1f;
6715 case 0x12: set_mnemonic(i, "COP2");
6716 op2=(source[i]>>21)&0x1f;
6719 if (gte_handlers[source[i]&0x3f]!=NULL) {
6721 if (gte_regnames[source[i]&0x3f]!=NULL)
6722 strcpy(insn[i],gte_regnames[source[i]&0x3f]);
6724 snprintf(insn[i], sizeof(insn[i]), "COP2 %x", source[i]&0x3f);
6731 case 0x00: set_mnemonic(i, "MFC2"); type=COP2; break;
6732 case 0x02: set_mnemonic(i, "CFC2"); type=COP2; break;
6733 case 0x04: set_mnemonic(i, "MTC2"); type=COP2; break;
6734 case 0x06: set_mnemonic(i, "CTC2"); type=COP2; break;
6737 case 0x13: set_mnemonic(i, "COP3");
6738 op2=(source[i]>>21)&0x1f;
6740 case 0x20: set_mnemonic(i, "LB"); type=LOAD; break;
6741 case 0x21: set_mnemonic(i, "LH"); type=LOAD; break;
6742 case 0x22: set_mnemonic(i, "LWL"); type=LOADLR; break;
6743 case 0x23: set_mnemonic(i, "LW"); type=LOAD; break;
6744 case 0x24: set_mnemonic(i, "LBU"); type=LOAD; break;
6745 case 0x25: set_mnemonic(i, "LHU"); type=LOAD; break;
6746 case 0x26: set_mnemonic(i, "LWR"); type=LOADLR; break;
6747 case 0x28: set_mnemonic(i, "SB"); type=STORE; break;
6748 case 0x29: set_mnemonic(i, "SH"); type=STORE; break;
6749 case 0x2A: set_mnemonic(i, "SWL"); type=STORELR; break;
6750 case 0x2B: set_mnemonic(i, "SW"); type=STORE; break;
6751 case 0x2E: set_mnemonic(i, "SWR"); type=STORELR; break;
6752 case 0x32: set_mnemonic(i, "LWC2"); type=C2LS; break;
6753 case 0x3A: set_mnemonic(i, "SWC2"); type=C2LS; break;
6755 if (Config.HLE && (source[i] & 0x03ffffff) < ARRAY_SIZE(psxHLEt)) {
6756 set_mnemonic(i, "HLECALL");
6763 if (type == INTCALL)
6764 SysPrintf("NI %08x @%08x (%08x)\n", source[i], start + i*4, start);
6766 dops[i].opcode2=op2;
6767 /* Get registers/immediates */
6769 gte_rs[i]=gte_rt[i]=0;
6776 dops[i].rs1=(source[i]>>21)&0x1f;
6777 dops[i].rt1=(source[i]>>16)&0x1f;
6778 cinfo[i].imm=(short)source[i];
6782 dops[i].rs1=(source[i]>>21)&0x1f;
6783 dops[i].rs2=(source[i]>>16)&0x1f;
6784 cinfo[i].imm=(short)source[i];
6787 // LWL/LWR only load part of the register,
6788 // therefore the target register must be treated as a source too
6789 dops[i].rs1=(source[i]>>21)&0x1f;
6790 dops[i].rs2=(source[i]>>16)&0x1f;
6791 dops[i].rt1=(source[i]>>16)&0x1f;
6792 cinfo[i].imm=(short)source[i];
6795 if (op==0x0f) dops[i].rs1=0; // LUI instruction has no source register
6796 else dops[i].rs1=(source[i]>>21)&0x1f;
6798 dops[i].rt1=(source[i]>>16)&0x1f;
6799 if(op>=0x0c&&op<=0x0e) { // ANDI/ORI/XORI
6800 cinfo[i].imm=(unsigned short)source[i];
6802 cinfo[i].imm=(short)source[i];
6806 // The JAL instruction writes to r31.
6813 dops[i].rs1=(source[i]>>21)&0x1f;
6814 // The JALR instruction writes to rd.
6816 dops[i].rt1=(source[i]>>11)&0x1f;
6821 dops[i].rs1=(source[i]>>21)&0x1f;
6822 dops[i].rs2=(source[i]>>16)&0x1f;
6823 if(op&2) { // BGTZ/BLEZ
6828 dops[i].rs1=(source[i]>>21)&0x1f;
6830 if (op2 == 0x10 || op2 == 0x11) { // BxxAL
6832 // NOTE: If the branch is not taken, r31 is still overwritten
6836 dops[i].rs1=(source[i]>>21)&0x1f; // source
6837 dops[i].rs2=(source[i]>>16)&0x1f; // subtract amount
6838 dops[i].rt1=(source[i]>>11)&0x1f; // destination
6841 dops[i].rs1=(source[i]>>21)&0x1f; // source
6842 dops[i].rs2=(source[i]>>16)&0x1f; // divisor
6847 if(op2==0x10) dops[i].rs1=HIREG; // MFHI
6848 if(op2==0x11) dops[i].rt1=HIREG; // MTHI
6849 if(op2==0x12) dops[i].rs1=LOREG; // MFLO
6850 if(op2==0x13) dops[i].rt1=LOREG; // MTLO
6851 if((op2&0x1d)==0x10) dops[i].rt1=(source[i]>>11)&0x1f; // MFxx
6852 if((op2&0x1d)==0x11) dops[i].rs1=(source[i]>>21)&0x1f; // MTxx
6855 dops[i].rs1=(source[i]>>16)&0x1f; // target of shift
6856 dops[i].rs2=(source[i]>>21)&0x1f; // shift amount
6857 dops[i].rt1=(source[i]>>11)&0x1f; // destination
6860 dops[i].rs1=(source[i]>>16)&0x1f;
6862 dops[i].rt1=(source[i]>>11)&0x1f;
6863 cinfo[i].imm=(source[i]>>6)&0x1f;
6866 if(op2==0) dops[i].rt1=(source[i]>>16)&0x1F; // MFC0
6867 if(op2==4) dops[i].rs1=(source[i]>>16)&0x1F; // MTC0
6868 if(op2==4&&((source[i]>>11)&0x1f)==12) dops[i].rt2=CSREG; // Status
6871 if(op2<3) dops[i].rt1=(source[i]>>16)&0x1F; // MFC2/CFC2
6872 if(op2>3) dops[i].rs1=(source[i]>>16)&0x1F; // MTC2/CTC2
6874 int gr=(source[i]>>11)&0x1F;
6877 case 0x00: gte_rs[i]=1ll<<gr; break; // MFC2
6878 case 0x04: gte_rt[i]=1ll<<gr; break; // MTC2
6879 case 0x02: gte_rs[i]=1ll<<(gr+32); break; // CFC2
6880 case 0x06: gte_rt[i]=1ll<<(gr+32); break; // CTC2
6884 dops[i].rs1=(source[i]>>21)&0x1F;
6885 cinfo[i].imm=(short)source[i];
6886 if(op==0x32) gte_rt[i]=1ll<<((source[i]>>16)&0x1F); // LWC2
6887 else gte_rs[i]=1ll<<((source[i]>>16)&0x1F); // SWC2
6890 gte_rs[i]=gte_reg_reads[source[i]&0x3f];
6891 gte_rt[i]=gte_reg_writes[source[i]&0x3f];
6892 gte_rt[i]|=1ll<<63; // every op changes flags
6893 if((source[i]&0x3f)==GTE_MVMVA) {
6894 int v = (source[i] >> 15) & 3;
6895 gte_rs[i]&=~0xe3fll;
6896 if(v==3) gte_rs[i]|=0xe00ll;
6897 else gte_rs[i]|=3ll<<(v*2);
6908 /* Calculate branch target addresses */
6910 cinfo[i].ba=((start+i*4+4)&0xF0000000)|(((unsigned int)source[i]<<6)>>4);
6911 else if(type==CJUMP&&dops[i].rs1==dops[i].rs2&&(op&1))
6912 cinfo[i].ba=start+i*4+8; // Ignore never taken branch
6913 else if(type==SJUMP&&dops[i].rs1==0&&!(op2&1))
6914 cinfo[i].ba=start+i*4+8; // Ignore never taken branch
6915 else if(type==CJUMP||type==SJUMP)
6916 cinfo[i].ba=start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14);
6918 /* simplify always (not)taken branches */
6919 if (type == CJUMP && dops[i].rs1 == dops[i].rs2) {
6920 dops[i].rs1 = dops[i].rs2 = 0;
6922 dops[i].itype = type = UJUMP;
6923 dops[i].rs2 = CCREG;
6926 else if (type == SJUMP && dops[i].rs1 == 0 && (op2 & 1))
6927 dops[i].itype = type = UJUMP;
6929 dops[i].is_jump = type == RJUMP || type == UJUMP || type == CJUMP || type == SJUMP;
6930 dops[i].is_ujump = type == RJUMP || type == UJUMP;
6931 dops[i].is_load = type == LOAD || type == LOADLR || op == 0x32; // LWC2
6932 dops[i].is_delay_load = (dops[i].is_load || (source[i] & 0xf3d00000) == 0x40000000); // MFC/CFC
6933 dops[i].is_store = type == STORE || type == STORELR || op == 0x3a; // SWC2
6934 dops[i].is_exception = type == SYSCALL || type == HLECALL || type == INTCALL;
6935 dops[i].may_except = dops[i].is_exception || (type == ALU && (op2 == 0x20 || op2 == 0x22)) || op == 8;
6937 if (((op & 0x37) == 0x21 || op == 0x25) // LH/SH/LHU
6938 && ((cinfo[i].imm & 1) || Config.PreciseExceptions))
6939 dops[i].may_except = 1;
6940 if (((op & 0x37) == 0x23 || (op & 0x37) == 0x32) // LW/SW/LWC2/SWC2
6941 && ((cinfo[i].imm & 3) || Config.PreciseExceptions))
6942 dops[i].may_except = 1;
6944 /* rare messy cases to just pass over to the interpreter */
6945 if (i > 0 && dops[i-1].is_jump) {
6947 // branch in delay slot?
6948 if (dops[i].is_jump) {
6949 // don't handle first branch and call interpreter if it's hit
6950 SysPrintf("branch in DS @%08x (%08x)\n", start + i*4, start);
6951 force_j_to_interpreter = 1;
6953 // basic load delay detection through a branch
6954 else if (dops[i].is_delay_load && dops[i].rt1 != 0) {
6955 int t=(cinfo[i-1].ba-start)/4;
6956 if(0 <= t && t < i &&(dops[i].rt1==dops[t].rs1||dops[i].rt1==dops[t].rs2)&&dops[t].itype!=CJUMP&&dops[t].itype!=SJUMP) {
6957 // jump target wants DS result - potential load delay effect
6958 SysPrintf("load delay in DS @%08x (%08x)\n", start + i*4, start);
6959 force_j_to_interpreter = 1;
6960 dops[t+1].bt=1; // expected return from interpreter
6962 else if(i>=2&&dops[i-2].rt1==2&&dops[i].rt1==2&&dops[i].rs1!=2&&dops[i].rs2!=2&&dops[i-1].rs1!=2&&dops[i-1].rs2!=2&&
6963 !(i>=3&&dops[i-3].is_jump)) {
6964 // v0 overwrite like this is a sign of trouble, bail out
6965 SysPrintf("v0 overwrite @%08x (%08x)\n", start + i*4, start);
6966 force_j_to_interpreter = 1;
6970 else if (i > 0 && dops[i-1].is_delay_load && dops[i-1].rt1 != 0
6971 && (dops[i].rs1 == dops[i-1].rt1 || dops[i].rs2 == dops[i-1].rt1)) {
6972 SysPrintf("load delay @%08x (%08x)\n", start + i*4, start);
6973 for (j = i - 1; j > 0 && dops[j-1].is_delay_load; j--)
6974 if (dops[j-1].rt1 != dops[i-1].rt1)
6976 force_j_to_interpreter = 1;
6978 if (force_j_to_interpreter) {
6979 memset(&dops[j], 0, sizeof(dops[j]));
6980 dops[j].itype = INTCALL;
6981 dops[j].rs1 = CCREG;
6984 i = j; // don't compile the problematic branch/load/etc
6987 /* Is this the end of the block? */
6988 if (i > 0 && dops[i-1].is_ujump) {
6989 if (dops[i-1].rt1 == 0) { // not jal
6990 int found_bbranch = 0, t = (cinfo[i-1].ba - start) / 4;
6991 if ((u_int)(t - i) < 64 && start + (t+64)*4 < pagelimit) {
6992 // scan for a branch back to i+1
6993 for (j = t; j < t + 64; j++) {
6994 int tmpop = source[j] >> 26;
6995 if (tmpop == 1 || ((tmpop & ~3) == 4)) {
6996 int t2 = j + 1 + (int)(signed short)source[j];
6998 //printf("blk expand %08x<-%08x\n", start + (i+1)*4, start + j*4);
7009 if(stop_after_jal) done=1;
7011 if((source[i+1]&0xfc00003f)==0x0d) done=1;
7013 // Don't recompile stuff that's already compiled
7014 if(check_addr(start+i*4+4)) done=1;
7015 // Don't get too close to the limit
7016 if(i>MAXBLOCK/2) done=1;
7018 if (dops[i].itype == HLECALL)
7020 else if (dops[i].itype == INTCALL)
7022 else if (dops[i].is_exception)
7023 done = stop_after_jal ? 1 : 2;
7025 // Does the block continue due to a branch?
7028 if(cinfo[j].ba==start+i*4) done=j=0; // Branch into delay slot
7029 if(cinfo[j].ba==start+i*4+4) done=j=0;
7030 if(cinfo[j].ba==start+i*4+8) done=j=0;
7033 //assert(i<MAXBLOCK-1);
7034 if(start+i*4==pagelimit-4) done=1;
7035 assert(start+i*4<pagelimit);
7036 if (i==MAXBLOCK-1) done=1;
7037 // Stop if we're compiling junk
7038 if (dops[i].itype == INTCALL && (++ni_count > 8 || dops[i].opcode == 0x11)) {
7039 done=stop_after_jal=1;
7040 SysPrintf("Disabled speculative precompilation\n");
7043 while (i > 0 && dops[i-1].is_jump)
7046 assert(!dops[i-1].is_jump);
7050 // Basic liveness analysis for MIPS registers
7051 static noinline void pass2_unneeded_regs(int istart,int iend,int r)
7054 uint64_t u,gte_u,b,gte_b;
7055 uint64_t temp_u,temp_gte_u=0;
7056 uint64_t gte_u_unknown=0;
7057 if (HACK_ENABLED(NDHACK_GTE_UNNEEDED))
7061 gte_u=gte_u_unknown;
7063 //u=unneeded_reg[iend+1];
7065 gte_u=gte_unneeded[iend+1];
7068 for (i=iend;i>=istart;i--)
7070 //printf("unneeded registers i=%d (%d,%d) r=%d\n",i,istart,iend,r);
7073 // If subroutine call, flag return address as a possible branch target
7074 if(dops[i].rt1==31 && i<slen-2) dops[i+2].bt=1;
7076 if(cinfo[i].ba<start || cinfo[i].ba>=(start+slen*4))
7078 // Branch out of this block, flush all regs
7080 gte_u=gte_u_unknown;
7081 branch_unneeded_reg[i]=u;
7082 // Merge in delay slot
7083 u|=(1LL<<dops[i+1].rt1)|(1LL<<dops[i+1].rt2);
7084 u&=~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2));
7087 gte_u&=~gte_rs[i+1];
7091 // Internal branch, flag target
7092 dops[(cinfo[i].ba-start)>>2].bt=1;
7093 if(cinfo[i].ba<=start+i*4) {
7095 if(dops[i].is_ujump)
7097 // Unconditional branch
7101 // Conditional branch (not taken case)
7102 temp_u=unneeded_reg[i+2];
7103 temp_gte_u&=gte_unneeded[i+2];
7105 // Merge in delay slot
7106 temp_u|=(1LL<<dops[i+1].rt1)|(1LL<<dops[i+1].rt2);
7107 temp_u&=~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2));
7109 temp_gte_u|=gte_rt[i+1];
7110 temp_gte_u&=~gte_rs[i+1];
7111 temp_u|=(1LL<<dops[i].rt1)|(1LL<<dops[i].rt2);
7112 temp_u&=~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
7114 temp_gte_u|=gte_rt[i];
7115 temp_gte_u&=~gte_rs[i];
7116 unneeded_reg[i]=temp_u;
7117 gte_unneeded[i]=temp_gte_u;
7118 // Only go three levels deep. This recursion can take an
7119 // excessive amount of time if there are a lot of nested loops.
7121 pass2_unneeded_regs((cinfo[i].ba-start)>>2,i-1,r+1);
7123 unneeded_reg[(cinfo[i].ba-start)>>2]=1;
7124 gte_unneeded[(cinfo[i].ba-start)>>2]=gte_u_unknown;
7127 if (dops[i].is_ujump)
7129 // Unconditional branch
7130 u=unneeded_reg[(cinfo[i].ba-start)>>2];
7131 gte_u=gte_unneeded[(cinfo[i].ba-start)>>2];
7132 branch_unneeded_reg[i]=u;
7133 // Merge in delay slot
7134 u|=(1LL<<dops[i+1].rt1)|(1LL<<dops[i+1].rt2);
7135 u&=~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2));
7138 gte_u&=~gte_rs[i+1];
7140 // Conditional branch
7141 b=unneeded_reg[(cinfo[i].ba-start)>>2];
7142 gte_b=gte_unneeded[(cinfo[i].ba-start)>>2];
7143 branch_unneeded_reg[i]=b;
7144 // Branch delay slot
7145 b|=(1LL<<dops[i+1].rt1)|(1LL<<dops[i+1].rt2);
7146 b&=~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2));
7149 gte_b&=~gte_rs[i+1];
7153 branch_unneeded_reg[i]&=unneeded_reg[i+2];
7155 branch_unneeded_reg[i]=1;
7161 else if(dops[i].may_except)
7163 // SYSCALL instruction, etc or conditional exception
7166 else if (dops[i].itype == RFE)
7171 // Written registers are unneeded
7172 u|=1LL<<dops[i].rt1;
7173 u|=1LL<<dops[i].rt2;
7175 // Accessed registers are needed
7176 u&=~(1LL<<dops[i].rs1);
7177 u&=~(1LL<<dops[i].rs2);
7179 if(gte_rs[i]&&dops[i].rt1&&(unneeded_reg[i+1]&(1ll<<dops[i].rt1)))
7180 gte_u|=gte_rs[i]>e_unneeded[i+1]; // MFC2/CFC2 to dead register, unneeded
7181 // Source-target dependencies
7182 // R0 is always unneeded
7186 gte_unneeded[i]=gte_u;
7188 printf("ur (%d,%d) %x: ",istart,iend,start+i*4);
7191 for(r=1;r<=CCREG;r++) {
7192 if((unneeded_reg[i]>>r)&1) {
7193 if(r==HIREG) printf(" HI");
7194 else if(r==LOREG) printf(" LO");
7195 else printf(" r%d",r);
7203 static noinline void pass3_register_alloc(u_int addr)
7205 struct regstat current; // Current register allocations/status
7206 clear_all_regs(current.regmap_entry);
7207 clear_all_regs(current.regmap);
7208 current.wasdirty = current.dirty = 0;
7209 current.u = unneeded_reg[0];
7210 alloc_reg(¤t, 0, CCREG);
7211 dirty_reg(¤t, CCREG);
7212 current.wasconst = 0;
7213 current.isconst = 0;
7214 current.loadedconst = 0;
7215 //current.waswritten = 0;
7222 // First instruction is delay slot
7227 current.regmap[HOST_BTREG]=BTREG;
7234 for(hr=0;hr<HOST_REGS;hr++)
7236 // Is this really necessary?
7237 if(current.regmap[hr]==0) current.regmap[hr]=-1;
7240 //current.waswritten=0;
7243 memcpy(regmap_pre[i],current.regmap,sizeof(current.regmap));
7244 regs[i].wasconst=current.isconst;
7245 regs[i].wasdirty=current.dirty;
7249 regs[i].loadedconst=0;
7250 if (!dops[i].is_jump) {
7252 current.u=unneeded_reg[i+1]&~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
7259 current.u=branch_unneeded_reg[i]&~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2));
7260 current.u&=~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
7263 SysPrintf("oops, branch at end of block with no delay slot @%08x\n", start + i*4);
7269 ds=0; // Skip delay slot, already allocated as part of branch
7270 // ...but we need to alloc it in case something jumps here
7272 current.u=branch_unneeded_reg[i-1]&unneeded_reg[i+1];
7274 current.u=branch_unneeded_reg[i-1];
7276 current.u&=~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
7278 struct regstat temp;
7279 memcpy(&temp,¤t,sizeof(current));
7280 temp.wasdirty=temp.dirty;
7281 // TODO: Take into account unconditional branches, as below
7282 delayslot_alloc(&temp,i);
7283 memcpy(regs[i].regmap,temp.regmap,sizeof(temp.regmap));
7284 regs[i].wasdirty=temp.wasdirty;
7285 regs[i].dirty=temp.dirty;
7289 // Create entry (branch target) regmap
7290 for(hr=0;hr<HOST_REGS;hr++)
7292 int r=temp.regmap[hr];
7294 if(r!=regmap_pre[i][hr]) {
7295 regs[i].regmap_entry[hr]=-1;
7300 if((current.u>>r)&1) {
7301 regs[i].regmap_entry[hr]=-1;
7302 regs[i].regmap[hr]=-1;
7303 //Don't clear regs in the delay slot as the branch might need them
7304 //current.regmap[hr]=-1;
7306 regs[i].regmap_entry[hr]=r;
7309 // First instruction expects CCREG to be allocated
7310 if(i==0&&hr==HOST_CCREG)
7311 regs[i].regmap_entry[hr]=CCREG;
7313 regs[i].regmap_entry[hr]=-1;
7317 else { // Not delay slot
7318 switch(dops[i].itype) {
7320 //current.isconst=0; // DEBUG
7321 //current.wasconst=0; // DEBUG
7322 //regs[i].wasconst=0; // DEBUG
7323 clear_const(¤t,dops[i].rt1);
7324 alloc_cc(¤t,i);
7325 dirty_reg(¤t,CCREG);
7326 if (dops[i].rt1==31) {
7327 alloc_reg(¤t,i,31);
7328 dirty_reg(¤t,31);
7329 //assert(dops[i+1].rs1!=31&&dops[i+1].rs2!=31);
7330 //assert(dops[i+1].rt1!=dops[i].rt1);
7332 alloc_reg(¤t,i,PTEMP);
7336 delayslot_alloc(¤t,i+1);
7337 //current.isconst=0; // DEBUG
7341 //current.isconst=0;
7342 //current.wasconst=0;
7343 //regs[i].wasconst=0;
7344 clear_const(¤t,dops[i].rs1);
7345 clear_const(¤t,dops[i].rt1);
7346 alloc_cc(¤t,i);
7347 dirty_reg(¤t,CCREG);
7348 if (!ds_writes_rjump_rs(i)) {
7349 alloc_reg(¤t,i,dops[i].rs1);
7350 if (dops[i].rt1!=0) {
7351 alloc_reg(¤t,i,dops[i].rt1);
7352 dirty_reg(¤t,dops[i].rt1);
7353 assert(dops[i+1].rs1!=dops[i].rt1&&dops[i+1].rs2!=dops[i].rt1);
7354 assert(dops[i+1].rt1!=dops[i].rt1);
7356 alloc_reg(¤t,i,PTEMP);
7360 if(dops[i].rs1==31) { // JALR
7361 alloc_reg(¤t,i,RHASH);
7362 alloc_reg(¤t,i,RHTBL);
7365 delayslot_alloc(¤t,i+1);
7367 // The delay slot overwrites our source register,
7368 // allocate a temporary register to hold the old value.
7372 delayslot_alloc(¤t,i+1);
7374 alloc_reg(¤t,i,RTEMP);
7376 //current.isconst=0; // DEBUG
7381 //current.isconst=0;
7382 //current.wasconst=0;
7383 //regs[i].wasconst=0;
7384 clear_const(¤t,dops[i].rs1);
7385 clear_const(¤t,dops[i].rs2);
7386 if((dops[i].opcode&0x3E)==4) // BEQ/BNE
7388 alloc_cc(¤t,i);
7389 dirty_reg(¤t,CCREG);
7390 if(dops[i].rs1) alloc_reg(¤t,i,dops[i].rs1);
7391 if(dops[i].rs2) alloc_reg(¤t,i,dops[i].rs2);
7392 if((dops[i].rs1&&(dops[i].rs1==dops[i+1].rt1||dops[i].rs1==dops[i+1].rt2))||
7393 (dops[i].rs2&&(dops[i].rs2==dops[i+1].rt1||dops[i].rs2==dops[i+1].rt2))) {
7394 // The delay slot overwrites one of our conditions.
7395 // Allocate the branch condition registers instead.
7399 if(dops[i].rs1) alloc_reg(¤t,i,dops[i].rs1);
7400 if(dops[i].rs2) alloc_reg(¤t,i,dops[i].rs2);
7405 delayslot_alloc(¤t,i+1);
7409 if((dops[i].opcode&0x3E)==6) // BLEZ/BGTZ
7411 alloc_cc(¤t,i);
7412 dirty_reg(¤t,CCREG);
7413 alloc_reg(¤t,i,dops[i].rs1);
7414 if(dops[i].rs1&&(dops[i].rs1==dops[i+1].rt1||dops[i].rs1==dops[i+1].rt2)) {
7415 // The delay slot overwrites one of our conditions.
7416 // Allocate the branch condition registers instead.
7420 if(dops[i].rs1) alloc_reg(¤t,i,dops[i].rs1);
7425 delayslot_alloc(¤t,i+1);
7429 // Don't alloc the delay slot yet because we might not execute it
7430 if((dops[i].opcode&0x3E)==0x14) // BEQL/BNEL
7435 alloc_cc(¤t,i);
7436 dirty_reg(¤t,CCREG);
7437 alloc_reg(¤t,i,dops[i].rs1);
7438 alloc_reg(¤t,i,dops[i].rs2);
7441 if((dops[i].opcode&0x3E)==0x16) // BLEZL/BGTZL
7446 alloc_cc(¤t,i);
7447 dirty_reg(¤t,CCREG);
7448 alloc_reg(¤t,i,dops[i].rs1);
7451 //current.isconst=0;
7454 clear_const(¤t,dops[i].rs1);
7455 clear_const(¤t,dops[i].rt1);
7457 alloc_cc(¤t,i);
7458 dirty_reg(¤t,CCREG);
7459 alloc_reg(¤t,i,dops[i].rs1);
7460 if (dops[i].rt1 == 31) { // BLTZAL/BGEZAL
7461 alloc_reg(¤t,i,31);
7462 dirty_reg(¤t,31);
7465 (dops[i].rs1==dops[i+1].rt1||dops[i].rs1==dops[i+1].rt2)) // The delay slot overwrites the branch condition.
7466 ||(dops[i].rt1 == 31 && dops[i].rs1 == 31) // overwrites it's own condition
7467 ||(dops[i].rt1==31&&(dops[i+1].rs1==31||dops[i+1].rs2==31||dops[i+1].rt1==31||dops[i+1].rt2==31))) { // DS touches $ra
7468 // Allocate the branch condition registers instead.
7472 if(dops[i].rs1) alloc_reg(¤t,i,dops[i].rs1);
7477 delayslot_alloc(¤t,i+1);
7481 //current.isconst=0;
7484 imm16_alloc(¤t,i);
7488 load_alloc(¤t,i);
7492 store_alloc(¤t,i);
7495 alu_alloc(¤t,i);
7498 shift_alloc(¤t,i);
7501 multdiv_alloc(¤t,i);
7504 shiftimm_alloc(¤t,i);
7507 mov_alloc(¤t,i);
7510 cop0_alloc(¤t,i);
7513 rfe_alloc(¤t,i);
7516 cop2_alloc(¤t,i);
7519 c2ls_alloc(¤t,i);
7522 c2op_alloc(¤t,i);
7527 syscall_alloc(¤t,i);
7531 // Create entry (branch target) regmap
7532 for(hr=0;hr<HOST_REGS;hr++)
7535 r=current.regmap[hr];
7537 if(r!=regmap_pre[i][hr]) {
7538 // TODO: delay slot (?)
7539 or=get_reg(regmap_pre[i],r); // Get old mapping for this register
7540 if(or<0||r>=TEMPREG){
7541 regs[i].regmap_entry[hr]=-1;
7545 // Just move it to a different register
7546 regs[i].regmap_entry[hr]=r;
7547 // If it was dirty before, it's still dirty
7548 if((regs[i].wasdirty>>or)&1) dirty_reg(¤t,r);
7555 regs[i].regmap_entry[hr]=0;
7560 if((current.u>>r)&1) {
7561 regs[i].regmap_entry[hr]=-1;
7562 //regs[i].regmap[hr]=-1;
7563 current.regmap[hr]=-1;
7565 regs[i].regmap_entry[hr]=r;
7569 // Branches expect CCREG to be allocated at the target
7570 if(regmap_pre[i][hr]==CCREG)
7571 regs[i].regmap_entry[hr]=CCREG;
7573 regs[i].regmap_entry[hr]=-1;
7576 memcpy(regs[i].regmap,current.regmap,sizeof(current.regmap));
7579 #if 0 // see do_store_smc_check()
7580 if(i>0&&(dops[i-1].itype==STORE||dops[i-1].itype==STORELR||(dops[i-1].itype==C2LS&&dops[i-1].opcode==0x3a))&&(u_int)cinfo[i-1].imm<0x800)
7581 current.waswritten|=1<<dops[i-1].rs1;
7582 current.waswritten&=~(1<<dops[i].rt1);
7583 current.waswritten&=~(1<<dops[i].rt2);
7584 if((dops[i].itype==STORE||dops[i].itype==STORELR||(dops[i].itype==C2LS&&dops[i].opcode==0x3a))&&(u_int)cinfo[i].imm>=0x800)
7585 current.waswritten&=~(1<<dops[i].rs1);
7588 /* Branch post-alloc */
7591 current.wasdirty=current.dirty;
7592 switch(dops[i-1].itype) {
7594 memcpy(&branch_regs[i-1],¤t,sizeof(current));
7595 branch_regs[i-1].isconst=0;
7596 branch_regs[i-1].wasconst=0;
7597 branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<<dops[i-1].rs1)|(1LL<<dops[i-1].rs2));
7598 alloc_cc(&branch_regs[i-1],i-1);
7599 dirty_reg(&branch_regs[i-1],CCREG);
7600 if(dops[i-1].rt1==31) { // JAL
7601 alloc_reg(&branch_regs[i-1],i-1,31);
7602 dirty_reg(&branch_regs[i-1],31);
7604 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
7605 memcpy(constmap[i],constmap[i-1],sizeof(constmap[i]));
7608 memcpy(&branch_regs[i-1],¤t,sizeof(current));
7609 branch_regs[i-1].isconst=0;
7610 branch_regs[i-1].wasconst=0;
7611 branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<<dops[i-1].rs1)|(1LL<<dops[i-1].rs2));
7612 alloc_cc(&branch_regs[i-1],i-1);
7613 dirty_reg(&branch_regs[i-1],CCREG);
7614 alloc_reg(&branch_regs[i-1],i-1,dops[i-1].rs1);
7615 if(dops[i-1].rt1!=0) { // JALR
7616 alloc_reg(&branch_regs[i-1],i-1,dops[i-1].rt1);
7617 dirty_reg(&branch_regs[i-1],dops[i-1].rt1);
7620 if(dops[i-1].rs1==31) { // JALR
7621 alloc_reg(&branch_regs[i-1],i-1,RHASH);
7622 alloc_reg(&branch_regs[i-1],i-1,RHTBL);
7625 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
7626 memcpy(constmap[i],constmap[i-1],sizeof(constmap[i]));
7629 if((dops[i-1].opcode&0x3E)==4) // BEQ/BNE
7631 alloc_cc(¤t,i-1);
7632 dirty_reg(¤t,CCREG);
7633 if((dops[i-1].rs1&&(dops[i-1].rs1==dops[i].rt1||dops[i-1].rs1==dops[i].rt2))||
7634 (dops[i-1].rs2&&(dops[i-1].rs2==dops[i].rt1||dops[i-1].rs2==dops[i].rt2))) {
7635 // The delay slot overwrote one of our conditions
7636 // Delay slot goes after the test (in order)
7637 current.u=branch_unneeded_reg[i-1]&~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
7639 delayslot_alloc(¤t,i);
7644 current.u=branch_unneeded_reg[i-1]&~((1LL<<dops[i-1].rs1)|(1LL<<dops[i-1].rs2));
7645 // Alloc the branch condition registers
7646 if(dops[i-1].rs1) alloc_reg(¤t,i-1,dops[i-1].rs1);
7647 if(dops[i-1].rs2) alloc_reg(¤t,i-1,dops[i-1].rs2);
7649 memcpy(&branch_regs[i-1],¤t,sizeof(current));
7650 branch_regs[i-1].isconst=0;
7651 branch_regs[i-1].wasconst=0;
7652 memcpy(&branch_regs[i-1].regmap_entry,¤t.regmap,sizeof(current.regmap));
7653 memcpy(constmap[i],constmap[i-1],sizeof(constmap[i]));
7656 if((dops[i-1].opcode&0x3E)==6) // BLEZ/BGTZ
7658 alloc_cc(¤t,i-1);
7659 dirty_reg(¤t,CCREG);
7660 if(dops[i-1].rs1==dops[i].rt1||dops[i-1].rs1==dops[i].rt2) {
7661 // The delay slot overwrote the branch condition
7662 // Delay slot goes after the test (in order)
7663 current.u=branch_unneeded_reg[i-1]&~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
7665 delayslot_alloc(¤t,i);
7670 current.u=branch_unneeded_reg[i-1]&~(1LL<<dops[i-1].rs1);
7671 // Alloc the branch condition register
7672 alloc_reg(¤t,i-1,dops[i-1].rs1);
7674 memcpy(&branch_regs[i-1],¤t,sizeof(current));
7675 branch_regs[i-1].isconst=0;
7676 branch_regs[i-1].wasconst=0;
7677 memcpy(&branch_regs[i-1].regmap_entry,¤t.regmap,sizeof(current.regmap));
7678 memcpy(constmap[i],constmap[i-1],sizeof(constmap[i]));
7681 // Alloc the delay slot in case the branch is taken
7682 if((dops[i-1].opcode&0x3E)==0x14) // BEQL/BNEL
7684 memcpy(&branch_regs[i-1],¤t,sizeof(current));
7685 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2)|(1LL<<dops[i].rt1)|(1LL<<dops[i].rt2)))|1;
7686 alloc_cc(&branch_regs[i-1],i);
7687 dirty_reg(&branch_regs[i-1],CCREG);
7688 delayslot_alloc(&branch_regs[i-1],i);
7689 branch_regs[i-1].isconst=0;
7690 alloc_reg(¤t,i,CCREG); // Not taken path
7691 dirty_reg(¤t,CCREG);
7692 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
7695 if((dops[i-1].opcode&0x3E)==0x16) // BLEZL/BGTZL
7697 memcpy(&branch_regs[i-1],¤t,sizeof(current));
7698 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2)|(1LL<<dops[i].rt1)|(1LL<<dops[i].rt2)))|1;
7699 alloc_cc(&branch_regs[i-1],i);
7700 dirty_reg(&branch_regs[i-1],CCREG);
7701 delayslot_alloc(&branch_regs[i-1],i);
7702 branch_regs[i-1].isconst=0;
7703 alloc_reg(¤t,i,CCREG); // Not taken path
7704 dirty_reg(¤t,CCREG);
7705 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
7710 alloc_cc(¤t,i-1);
7711 dirty_reg(¤t,CCREG);
7712 if(dops[i-1].rs1==dops[i].rt1||dops[i-1].rs1==dops[i].rt2) {
7713 // The delay slot overwrote the branch condition
7714 // Delay slot goes after the test (in order)
7715 current.u=branch_unneeded_reg[i-1]&~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
7717 delayslot_alloc(¤t,i);
7722 current.u=branch_unneeded_reg[i-1]&~(1LL<<dops[i-1].rs1);
7723 // Alloc the branch condition register
7724 alloc_reg(¤t,i-1,dops[i-1].rs1);
7726 memcpy(&branch_regs[i-1],¤t,sizeof(current));
7727 branch_regs[i-1].isconst=0;
7728 branch_regs[i-1].wasconst=0;
7729 memcpy(&branch_regs[i-1].regmap_entry,¤t.regmap,sizeof(current.regmap));
7730 memcpy(constmap[i],constmap[i-1],sizeof(constmap[i]));
7732 // FIXME: BLTZAL/BGEZAL
7733 if ((dops[i-1].opcode2 & 0x1e) == 0x10) { // BxxZAL
7734 alloc_reg(&branch_regs[i-1],i-1,31);
7735 dirty_reg(&branch_regs[i-1],31);
7740 if (dops[i-1].is_ujump)
7742 if(dops[i-1].rt1==31) // JAL/JALR
7744 // Subroutine call will return here, don't alloc any registers
7746 clear_all_regs(current.regmap);
7747 alloc_reg(¤t,i,CCREG);
7748 dirty_reg(¤t,CCREG);
7752 // Internal branch will jump here, match registers to caller
7754 clear_all_regs(current.regmap);
7755 alloc_reg(¤t,i,CCREG);
7756 dirty_reg(¤t,CCREG);
7759 if(cinfo[j].ba==start+i*4+4) {
7760 memcpy(current.regmap,branch_regs[j].regmap,sizeof(current.regmap));
7761 current.dirty=branch_regs[j].dirty;
7766 if(cinfo[j].ba==start+i*4+4) {
7767 for(hr=0;hr<HOST_REGS;hr++) {
7768 if(current.regmap[hr]!=branch_regs[j].regmap[hr]) {
7769 current.regmap[hr]=-1;
7771 current.dirty&=branch_regs[j].dirty;
7780 // Count cycles in between branches
7781 cinfo[i].ccadj = CLOCK_ADJUST(cc);
7782 if (i > 0 && (dops[i-1].is_jump || dops[i].is_exception))
7786 #if !defined(DRC_DBG)
7787 else if(dops[i].itype==C2OP&>e_cycletab[source[i]&0x3f]>2)
7789 // this should really be removed since the real stalls have been implemented,
7790 // but doing so causes sizeable perf regression against the older version
7791 u_int gtec = gte_cycletab[source[i] & 0x3f];
7792 cc += HACK_ENABLED(NDHACK_NO_STALLS) ? gtec/2 : 2;
7794 else if(i>1&&dops[i].itype==STORE&&dops[i-1].itype==STORE&&dops[i-2].itype==STORE&&!dops[i].bt)
7798 else if(dops[i].itype==C2LS)
7800 // same as with C2OP
7801 cc += HACK_ENABLED(NDHACK_NO_STALLS) ? 4 : 2;
7809 if(!dops[i].is_ds) {
7810 regs[i].dirty=current.dirty;
7811 regs[i].isconst=current.isconst;
7812 memcpy(constmap[i],current_constmap,sizeof(constmap[i]));
7814 for(hr=0;hr<HOST_REGS;hr++) {
7815 if(hr!=EXCLUDE_REG&®s[i].regmap[hr]>=0) {
7816 if(regmap_pre[i][hr]!=regs[i].regmap[hr]) {
7817 regs[i].wasconst&=~(1<<hr);
7821 if(current.regmap[HOST_BTREG]==BTREG) current.regmap[HOST_BTREG]=-1;
7822 //regs[i].waswritten=current.waswritten;
7826 static noinline void pass4_cull_unused_regs(void)
7828 u_int last_needed_regs[4] = {0,0,0,0};
7832 for (i=slen-1;i>=0;i--)
7835 __builtin_prefetch(regs[i-2].regmap);
7838 if(cinfo[i].ba<start || cinfo[i].ba>=(start+slen*4))
7840 // Branch out of this block, don't need anything
7846 // Need whatever matches the target
7848 int t=(cinfo[i].ba-start)>>2;
7849 for(hr=0;hr<HOST_REGS;hr++)
7851 if(regs[i].regmap_entry[hr]>=0) {
7852 if(regs[i].regmap_entry[hr]==regs[t].regmap_entry[hr]) nr|=1<<hr;
7856 // Conditional branch may need registers for following instructions
7857 if (!dops[i].is_ujump)
7860 nr |= last_needed_regs[(i+2) & 3];
7861 for(hr=0;hr<HOST_REGS;hr++)
7863 if(regmap_pre[i+2][hr]>=0&&get_reg(regs[i+2].regmap_entry,regmap_pre[i+2][hr])<0) nr&=~(1<<hr);
7864 //if((regmap_entry[i+2][hr])>=0) if(!((nr>>hr)&1)) printf("%x-bogus(%d=%d)\n",start+i*4,hr,regmap_entry[i+2][hr]);
7868 // Don't need stuff which is overwritten
7869 //if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr);
7870 //if(regs[i].regmap[hr]<0) nr&=~(1<<hr);
7871 // Merge in delay slot
7872 if (dops[i+1].rt1) nr &= ~get_regm(regs[i].regmap, dops[i+1].rt1);
7873 if (dops[i+1].rt2) nr &= ~get_regm(regs[i].regmap, dops[i+1].rt2);
7874 nr |= get_regm(regmap_pre[i], dops[i+1].rs1);
7875 nr |= get_regm(regmap_pre[i], dops[i+1].rs2);
7876 nr |= get_regm(regs[i].regmap_entry, dops[i+1].rs1);
7877 nr |= get_regm(regs[i].regmap_entry, dops[i+1].rs2);
7878 if (ram_offset && (dops[i+1].is_load || dops[i+1].is_store)) {
7879 nr |= get_regm(regmap_pre[i], ROREG);
7880 nr |= get_regm(regs[i].regmap_entry, ROREG);
7882 if (dops[i+1].is_store) {
7883 nr |= get_regm(regmap_pre[i], INVCP);
7884 nr |= get_regm(regs[i].regmap_entry, INVCP);
7887 else if (dops[i].is_exception)
7889 // SYSCALL instruction, etc
7895 for(hr=0;hr<HOST_REGS;hr++) {
7896 if(regmap_pre[i+1][hr]>=0&&get_reg(regs[i+1].regmap_entry,regmap_pre[i+1][hr])<0) nr&=~(1<<hr);
7897 if(regs[i].regmap[hr]!=regmap_pre[i+1][hr]) nr&=~(1<<hr);
7898 if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr);
7899 if(regs[i].regmap[hr]<0) nr&=~(1<<hr);
7903 // Overwritten registers are not needed
7904 if (dops[i].rt1) nr &= ~get_regm(regs[i].regmap, dops[i].rt1);
7905 if (dops[i].rt2) nr &= ~get_regm(regs[i].regmap, dops[i].rt2);
7906 nr &= ~get_regm(regs[i].regmap, FTEMP);
7907 // Source registers are needed
7908 nr |= get_regm(regmap_pre[i], dops[i].rs1);
7909 nr |= get_regm(regmap_pre[i], dops[i].rs2);
7910 nr |= get_regm(regs[i].regmap_entry, dops[i].rs1);
7911 nr |= get_regm(regs[i].regmap_entry, dops[i].rs2);
7912 if (ram_offset && (dops[i].is_load || dops[i].is_store)) {
7913 nr |= get_regm(regmap_pre[i], ROREG);
7914 nr |= get_regm(regs[i].regmap_entry, ROREG);
7916 if (dops[i].is_store) {
7917 nr |= get_regm(regmap_pre[i], INVCP);
7918 nr |= get_regm(regs[i].regmap_entry, INVCP);
7921 if (i > 0 && !dops[i].bt && regs[i].wasdirty)
7922 for(hr=0;hr<HOST_REGS;hr++)
7924 // Don't store a register immediately after writing it,
7925 // may prevent dual-issue.
7926 // But do so if this is a branch target, otherwise we
7927 // might have to load the register before the branch.
7928 if((regs[i].wasdirty>>hr)&1) {
7929 if((regmap_pre[i][hr]>0&&!((unneeded_reg[i]>>regmap_pre[i][hr])&1))) {
7930 if(dops[i-1].rt1==regmap_pre[i][hr]) nr|=1<<hr;
7931 if(dops[i-1].rt2==regmap_pre[i][hr]) nr|=1<<hr;
7933 if((regs[i].regmap_entry[hr]>0&&!((unneeded_reg[i]>>regs[i].regmap_entry[hr])&1))) {
7934 if(dops[i-1].rt1==regs[i].regmap_entry[hr]) nr|=1<<hr;
7935 if(dops[i-1].rt2==regs[i].regmap_entry[hr]) nr|=1<<hr;
7939 // Cycle count is needed at branches. Assume it is needed at the target too.
7940 if(i==0||dops[i].bt||dops[i].itype==CJUMP) {
7941 if(regmap_pre[i][HOST_CCREG]==CCREG) nr|=1<<HOST_CCREG;
7942 if(regs[i].regmap_entry[HOST_CCREG]==CCREG) nr|=1<<HOST_CCREG;
7945 last_needed_regs[i & 3] = nr;
7947 // Deallocate unneeded registers
7948 for(hr=0;hr<HOST_REGS;hr++)
7951 if(regs[i].regmap_entry[hr]!=CCREG) regs[i].regmap_entry[hr]=-1;
7954 int map1 = 0, map2 = 0, temp = 0; // or -1 ??
7955 if (dops[i+1].is_load || dops[i+1].is_store)
7957 if (dops[i+1].is_store)
7959 if(dops[i+1].itype==LOADLR || dops[i+1].itype==STORELR || dops[i+1].itype==C2LS)
7961 if(regs[i].regmap[hr]!=dops[i].rs1 && regs[i].regmap[hr]!=dops[i].rs2 &&
7962 regs[i].regmap[hr]!=dops[i].rt1 && regs[i].regmap[hr]!=dops[i].rt2 &&
7963 regs[i].regmap[hr]!=dops[i+1].rt1 && regs[i].regmap[hr]!=dops[i+1].rt2 &&
7964 regs[i].regmap[hr]!=dops[i+1].rs1 && regs[i].regmap[hr]!=dops[i+1].rs2 &&
7965 regs[i].regmap[hr]!=temp && regs[i].regmap[hr]!=PTEMP &&
7966 regs[i].regmap[hr]!=RHASH && regs[i].regmap[hr]!=RHTBL &&
7967 regs[i].regmap[hr]!=RTEMP && regs[i].regmap[hr]!=CCREG &&
7968 regs[i].regmap[hr]!=map1 && regs[i].regmap[hr]!=map2)
7970 regs[i].regmap[hr]=-1;
7971 regs[i].isconst&=~(1<<hr);
7972 regs[i].dirty&=~(1<<hr);
7973 regs[i+1].wasdirty&=~(1<<hr);
7974 if(branch_regs[i].regmap[hr]!=dops[i].rs1 && branch_regs[i].regmap[hr]!=dops[i].rs2 &&
7975 branch_regs[i].regmap[hr]!=dops[i].rt1 && branch_regs[i].regmap[hr]!=dops[i].rt2 &&
7976 branch_regs[i].regmap[hr]!=dops[i+1].rt1 && branch_regs[i].regmap[hr]!=dops[i+1].rt2 &&
7977 branch_regs[i].regmap[hr]!=dops[i+1].rs1 && branch_regs[i].regmap[hr]!=dops[i+1].rs2 &&
7978 branch_regs[i].regmap[hr]!=temp && branch_regs[i].regmap[hr]!=PTEMP &&
7979 branch_regs[i].regmap[hr]!=RHASH && branch_regs[i].regmap[hr]!=RHTBL &&
7980 branch_regs[i].regmap[hr]!=RTEMP && branch_regs[i].regmap[hr]!=CCREG &&
7981 branch_regs[i].regmap[hr]!=map1 && branch_regs[i].regmap[hr]!=map2)
7983 branch_regs[i].regmap[hr]=-1;
7984 branch_regs[i].regmap_entry[hr]=-1;
7985 if (!dops[i].is_ujump)
7988 regmap_pre[i+2][hr]=-1;
7989 regs[i+2].wasconst&=~(1<<hr);
8000 int map1 = -1, map2 = -1, temp=-1;
8001 if (dops[i].is_load || dops[i].is_store)
8003 if (dops[i].is_store)
8005 if (dops[i].itype==LOADLR || dops[i].itype==STORELR || dops[i].itype==C2LS)
8007 if(regs[i].regmap[hr]!=dops[i].rt1 && regs[i].regmap[hr]!=dops[i].rt2 &&
8008 regs[i].regmap[hr]!=dops[i].rs1 && regs[i].regmap[hr]!=dops[i].rs2 &&
8009 regs[i].regmap[hr]!=temp && regs[i].regmap[hr]!=map1 && regs[i].regmap[hr]!=map2 &&
8010 //(dops[i].itype!=SPAN||regs[i].regmap[hr]!=CCREG)
8011 regs[i].regmap[hr] != CCREG)
8013 if(i<slen-1&&!dops[i].is_ds) {
8014 assert(regs[i].regmap[hr]<64);
8015 if(regmap_pre[i+1][hr]!=-1 || regs[i].regmap[hr]>0)
8016 if(regmap_pre[i+1][hr]!=regs[i].regmap[hr])
8018 SysPrintf("fail: %x (%d %d!=%d)\n",start+i*4,hr,regmap_pre[i+1][hr],regs[i].regmap[hr]);
8019 assert(regmap_pre[i+1][hr]==regs[i].regmap[hr]);
8021 regmap_pre[i+1][hr]=-1;
8022 if(regs[i+1].regmap_entry[hr]==CCREG) regs[i+1].regmap_entry[hr]=-1;
8023 regs[i+1].wasconst&=~(1<<hr);
8025 regs[i].regmap[hr]=-1;
8026 regs[i].isconst&=~(1<<hr);
8027 regs[i].dirty&=~(1<<hr);
8028 regs[i+1].wasdirty&=~(1<<hr);
8037 // If a register is allocated during a loop, try to allocate it for the
8038 // entire loop, if possible. This avoids loading/storing registers
8039 // inside of the loop.
8040 static noinline void pass5a_preallocate1(void)
8043 signed char f_regmap[HOST_REGS];
8044 clear_all_regs(f_regmap);
8045 for(i=0;i<slen-1;i++)
8047 if(dops[i].itype==UJUMP||dops[i].itype==CJUMP||dops[i].itype==SJUMP)
8049 if(cinfo[i].ba>=start && cinfo[i].ba<(start+i*4))
8050 if(dops[i+1].itype==NOP||dops[i+1].itype==MOV||dops[i+1].itype==ALU
8051 ||dops[i+1].itype==SHIFTIMM||dops[i+1].itype==IMM16||dops[i+1].itype==LOAD
8052 ||dops[i+1].itype==STORE||dops[i+1].itype==STORELR
8053 ||dops[i+1].itype==SHIFT
8054 ||dops[i+1].itype==COP2||dops[i+1].itype==C2LS||dops[i+1].itype==C2OP)
8056 int t=(cinfo[i].ba-start)>>2;
8057 if(t > 0 && !dops[t-1].is_jump) // loop_preload can't handle jumps into delay slots
8058 if(t<2||(dops[t-2].itype!=UJUMP&&dops[t-2].itype!=RJUMP)||dops[t-2].rt1!=31) // call/ret assumes no registers allocated
8059 for(hr=0;hr<HOST_REGS;hr++)
8061 if(regs[i].regmap[hr]>=0) {
8062 if(f_regmap[hr]!=regs[i].regmap[hr]) {
8063 // dealloc old register
8065 for(n=0;n<HOST_REGS;n++)
8067 if(f_regmap[n]==regs[i].regmap[hr]) {f_regmap[n]=-1;}
8069 // and alloc new one
8070 f_regmap[hr]=regs[i].regmap[hr];
8073 if(branch_regs[i].regmap[hr]>=0) {
8074 if(f_regmap[hr]!=branch_regs[i].regmap[hr]) {
8075 // dealloc old register
8077 for(n=0;n<HOST_REGS;n++)
8079 if(f_regmap[n]==branch_regs[i].regmap[hr]) {f_regmap[n]=-1;}
8081 // and alloc new one
8082 f_regmap[hr]=branch_regs[i].regmap[hr];
8086 if(count_free_regs(regs[i].regmap)<=cinfo[i+1].min_free_regs)
8087 f_regmap[hr]=branch_regs[i].regmap[hr];
8089 if(count_free_regs(branch_regs[i].regmap)<=cinfo[i+1].min_free_regs)
8090 f_regmap[hr]=branch_regs[i].regmap[hr];
8092 // Avoid dirty->clean transition
8093 #ifdef DESTRUCTIVE_WRITEBACK
8094 if(t>0) if(get_reg(regmap_pre[t],f_regmap[hr])>=0) if((regs[t].wasdirty>>get_reg(regmap_pre[t],f_regmap[hr]))&1) f_regmap[hr]=-1;
8096 // This check is only strictly required in the DESTRUCTIVE_WRITEBACK
8097 // case above, however it's always a good idea. We can't hoist the
8098 // load if the register was already allocated, so there's no point
8099 // wasting time analyzing most of these cases. It only "succeeds"
8100 // when the mapping was different and the load can be replaced with
8101 // a mov, which is of negligible benefit. So such cases are
8103 if(f_regmap[hr]>0) {
8104 if(regs[t].regmap[hr]==f_regmap[hr]||(regs[t].regmap_entry[hr]<0&&get_reg(regmap_pre[t],f_regmap[hr])<0)) {
8108 //printf("Test %x -> %x, %x %d/%d\n",start+i*4,cinfo[i].ba,start+j*4,hr,r);
8109 if(r<34&&((unneeded_reg[j]>>r)&1)) break;
8111 if(regs[j].regmap[hr]==f_regmap[hr]&&f_regmap[hr]<TEMPREG) {
8112 //printf("Hit %x -> %x, %x %d/%d\n",start+i*4,cinfo[i].ba,start+j*4,hr,r);
8114 if(regs[i].regmap[hr]==-1&&branch_regs[i].regmap[hr]==-1) {
8115 if(get_reg(regs[i].regmap,f_regmap[hr])>=0) break;
8116 if(get_reg(regs[i+2].regmap,f_regmap[hr])>=0) break;
8118 while(k>1&®s[k-1].regmap[hr]==-1) {
8119 if(count_free_regs(regs[k-1].regmap)<=cinfo[k-1].min_free_regs) {
8120 //printf("no free regs for store %x\n",start+(k-1)*4);
8123 if(get_reg(regs[k-1].regmap,f_regmap[hr])>=0) {
8124 //printf("no-match due to different register\n");
8127 if (dops[k-2].is_jump) {
8128 //printf("no-match due to branch\n");
8131 // call/ret fast path assumes no registers allocated
8132 if(k>2&&(dops[k-3].itype==UJUMP||dops[k-3].itype==RJUMP)&&dops[k-3].rt1==31) {
8137 if(regs[k-1].regmap[hr]==f_regmap[hr]&®map_pre[k][hr]==f_regmap[hr]) {
8138 //printf("Extend r%d, %x ->\n",hr,start+k*4);
8140 regs[k].regmap_entry[hr]=f_regmap[hr];
8141 regs[k].regmap[hr]=f_regmap[hr];
8142 regmap_pre[k+1][hr]=f_regmap[hr];
8143 regs[k].wasdirty&=~(1<<hr);
8144 regs[k].dirty&=~(1<<hr);
8145 regs[k].wasdirty|=(1<<hr)®s[k-1].dirty;
8146 regs[k].dirty|=(1<<hr)®s[k].wasdirty;
8147 regs[k].wasconst&=~(1<<hr);
8148 regs[k].isconst&=~(1<<hr);
8153 //printf("Fail Extend r%d, %x ->\n",hr,start+k*4);
8156 assert(regs[i-1].regmap[hr]==f_regmap[hr]);
8157 if(regs[i-1].regmap[hr]==f_regmap[hr]&®map_pre[i][hr]==f_regmap[hr]) {
8158 //printf("OK fill %x (r%d)\n",start+i*4,hr);
8159 regs[i].regmap_entry[hr]=f_regmap[hr];
8160 regs[i].regmap[hr]=f_regmap[hr];
8161 regs[i].wasdirty&=~(1<<hr);
8162 regs[i].dirty&=~(1<<hr);
8163 regs[i].wasdirty|=(1<<hr)®s[i-1].dirty;
8164 regs[i].dirty|=(1<<hr)®s[i-1].dirty;
8165 regs[i].wasconst&=~(1<<hr);
8166 regs[i].isconst&=~(1<<hr);
8167 branch_regs[i].regmap_entry[hr]=f_regmap[hr];
8168 branch_regs[i].wasdirty&=~(1<<hr);
8169 branch_regs[i].wasdirty|=(1<<hr)®s[i].dirty;
8170 branch_regs[i].regmap[hr]=f_regmap[hr];
8171 branch_regs[i].dirty&=~(1<<hr);
8172 branch_regs[i].dirty|=(1<<hr)®s[i].dirty;
8173 branch_regs[i].wasconst&=~(1<<hr);
8174 branch_regs[i].isconst&=~(1<<hr);
8175 if (!dops[i].is_ujump) {
8176 regmap_pre[i+2][hr]=f_regmap[hr];
8177 regs[i+2].wasdirty&=~(1<<hr);
8178 regs[i+2].wasdirty|=(1<<hr)®s[i].dirty;
8183 // Alloc register clean at beginning of loop,
8184 // but may dirty it in pass 6
8185 regs[k].regmap_entry[hr]=f_regmap[hr];
8186 regs[k].regmap[hr]=f_regmap[hr];
8187 regs[k].dirty&=~(1<<hr);
8188 regs[k].wasconst&=~(1<<hr);
8189 regs[k].isconst&=~(1<<hr);
8190 if (dops[k].is_jump) {
8191 branch_regs[k].regmap_entry[hr]=f_regmap[hr];
8192 branch_regs[k].regmap[hr]=f_regmap[hr];
8193 branch_regs[k].dirty&=~(1<<hr);
8194 branch_regs[k].wasconst&=~(1<<hr);
8195 branch_regs[k].isconst&=~(1<<hr);
8196 if (!dops[k].is_ujump) {
8197 regmap_pre[k+2][hr]=f_regmap[hr];
8198 regs[k+2].wasdirty&=~(1<<hr);
8203 regmap_pre[k+1][hr]=f_regmap[hr];
8204 regs[k+1].wasdirty&=~(1<<hr);
8207 if(regs[j].regmap[hr]==f_regmap[hr])
8208 regs[j].regmap_entry[hr]=f_regmap[hr];
8212 if(regs[j].regmap[hr]>=0)
8214 if(get_reg(regs[j].regmap,f_regmap[hr])>=0) {
8215 //printf("no-match due to different register\n");
8218 if (dops[j].is_ujump)
8220 // Stop on unconditional branch
8223 if(dops[j].itype==CJUMP||dops[j].itype==SJUMP)
8226 if(count_free_regs(regs[j].regmap)<=cinfo[j+1].min_free_regs)
8229 if(count_free_regs(branch_regs[j].regmap)<=cinfo[j+1].min_free_regs)
8232 if(get_reg(branch_regs[j].regmap,f_regmap[hr])>=0) {
8233 //printf("no-match due to different register (branch)\n");
8237 if(count_free_regs(regs[j].regmap)<=cinfo[j].min_free_regs) {
8238 //printf("No free regs for store %x\n",start+j*4);
8241 assert(f_regmap[hr]<64);
8248 // Non branch or undetermined branch target
8249 for(hr=0;hr<HOST_REGS;hr++)
8251 if(hr!=EXCLUDE_REG) {
8252 if(regs[i].regmap[hr]>=0) {
8253 if(f_regmap[hr]!=regs[i].regmap[hr]) {
8254 // dealloc old register
8256 for(n=0;n<HOST_REGS;n++)
8258 if(f_regmap[n]==regs[i].regmap[hr]) {f_regmap[n]=-1;}
8260 // and alloc new one
8261 f_regmap[hr]=regs[i].regmap[hr];
8266 // Try to restore cycle count at branch targets
8268 for(j=i;j<slen-1;j++) {
8269 if(regs[j].regmap[HOST_CCREG]!=-1) break;
8270 if(count_free_regs(regs[j].regmap)<=cinfo[j].min_free_regs) {
8271 //printf("no free regs for store %x\n",start+j*4);
8275 if(regs[j].regmap[HOST_CCREG]==CCREG) {
8277 //printf("Extend CC, %x -> %x\n",start+k*4,start+j*4);
8279 regs[k].regmap_entry[HOST_CCREG]=CCREG;
8280 regs[k].regmap[HOST_CCREG]=CCREG;
8281 regmap_pre[k+1][HOST_CCREG]=CCREG;
8282 regs[k+1].wasdirty|=1<<HOST_CCREG;
8283 regs[k].dirty|=1<<HOST_CCREG;
8284 regs[k].wasconst&=~(1<<HOST_CCREG);
8285 regs[k].isconst&=~(1<<HOST_CCREG);
8288 regs[j].regmap_entry[HOST_CCREG]=CCREG;
8290 // Work backwards from the branch target
8291 if(j>i&&f_regmap[HOST_CCREG]==CCREG)
8293 //printf("Extend backwards\n");
8296 while(regs[k-1].regmap[HOST_CCREG]==-1) {
8297 if(count_free_regs(regs[k-1].regmap)<=cinfo[k-1].min_free_regs) {
8298 //printf("no free regs for store %x\n",start+(k-1)*4);
8303 if(regs[k-1].regmap[HOST_CCREG]==CCREG) {
8304 //printf("Extend CC, %x ->\n",start+k*4);
8306 regs[k].regmap_entry[HOST_CCREG]=CCREG;
8307 regs[k].regmap[HOST_CCREG]=CCREG;
8308 regmap_pre[k+1][HOST_CCREG]=CCREG;
8309 regs[k+1].wasdirty|=1<<HOST_CCREG;
8310 regs[k].dirty|=1<<HOST_CCREG;
8311 regs[k].wasconst&=~(1<<HOST_CCREG);
8312 regs[k].isconst&=~(1<<HOST_CCREG);
8317 //printf("Fail Extend CC, %x ->\n",start+k*4);
8321 if(dops[i].itype!=STORE&&dops[i].itype!=STORELR&&dops[i].itype!=SHIFT&&
8322 dops[i].itype!=NOP&&dops[i].itype!=MOV&&dops[i].itype!=ALU&&dops[i].itype!=SHIFTIMM&&
8323 dops[i].itype!=IMM16&&dops[i].itype!=LOAD)
8325 memcpy(f_regmap,regs[i].regmap,sizeof(f_regmap));
8331 // This allocates registers (if possible) one instruction prior
8332 // to use, which can avoid a load-use penalty on certain CPUs.
8333 static noinline void pass5b_preallocate2(void)
8336 for(i=0;i<slen-1;i++)
8338 if (!i || !dops[i-1].is_jump)
8342 int j, can_steal = 1;
8343 for (j = i; j < i + 2; j++) {
8345 if (cinfo[j].min_free_regs == 0)
8347 for (hr = 0; hr < HOST_REGS; hr++)
8348 if (hr != EXCLUDE_REG && regs[j].regmap[hr] < 0)
8350 if (free_regs <= cinfo[j].min_free_regs) {
8357 if(dops[i].itype==ALU||dops[i].itype==MOV||dops[i].itype==LOAD||dops[i].itype==SHIFTIMM||dops[i].itype==IMM16
8358 ||(dops[i].itype==COP2&&dops[i].opcode2<3))
8361 if((hr=get_reg(regs[i+1].regmap,dops[i+1].rs1))>=0)
8363 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
8365 regs[i].regmap[hr]=regs[i+1].regmap[hr];
8366 regmap_pre[i+1][hr]=regs[i+1].regmap[hr];
8367 regs[i+1].regmap_entry[hr]=regs[i+1].regmap[hr];
8368 regs[i].isconst&=~(1<<hr);
8369 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
8370 constmap[i][hr]=constmap[i+1][hr];
8371 regs[i+1].wasdirty&=~(1<<hr);
8372 regs[i].dirty&=~(1<<hr);
8377 if((hr=get_reg(regs[i+1].regmap,dops[i+1].rs2))>=0)
8379 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
8381 regs[i].regmap[hr]=regs[i+1].regmap[hr];
8382 regmap_pre[i+1][hr]=regs[i+1].regmap[hr];
8383 regs[i+1].regmap_entry[hr]=regs[i+1].regmap[hr];
8384 regs[i].isconst&=~(1<<hr);
8385 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
8386 constmap[i][hr]=constmap[i+1][hr];
8387 regs[i+1].wasdirty&=~(1<<hr);
8388 regs[i].dirty&=~(1<<hr);
8392 // Preload target address for load instruction (non-constant)
8393 if(dops[i+1].itype==LOAD&&dops[i+1].rs1&&get_reg(regs[i+1].regmap,dops[i+1].rs1)<0) {
8394 if((hr=get_reg_w(regs[i+1].regmap, dops[i+1].rt1))>=0)
8396 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
8398 regs[i].regmap[hr]=dops[i+1].rs1;
8399 regmap_pre[i+1][hr]=dops[i+1].rs1;
8400 regs[i+1].regmap_entry[hr]=dops[i+1].rs1;
8401 regs[i].isconst&=~(1<<hr);
8402 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
8403 constmap[i][hr]=constmap[i+1][hr];
8404 regs[i+1].wasdirty&=~(1<<hr);
8405 regs[i].dirty&=~(1<<hr);
8409 // Load source into target register
8410 if(dops[i+1].use_lt1&&get_reg(regs[i+1].regmap,dops[i+1].rs1)<0) {
8411 if((hr=get_reg_w(regs[i+1].regmap, dops[i+1].rt1))>=0)
8413 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
8415 regs[i].regmap[hr]=dops[i+1].rs1;
8416 regmap_pre[i+1][hr]=dops[i+1].rs1;
8417 regs[i+1].regmap_entry[hr]=dops[i+1].rs1;
8418 regs[i].isconst&=~(1<<hr);
8419 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
8420 constmap[i][hr]=constmap[i+1][hr];
8421 regs[i+1].wasdirty&=~(1<<hr);
8422 regs[i].dirty&=~(1<<hr);
8426 // Address for store instruction (non-constant)
8427 if (dops[i+1].is_store) { // SB/SH/SW/SWC2
8428 if(get_reg(regs[i+1].regmap,dops[i+1].rs1)<0) {
8429 hr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1);
8430 if(hr<0) hr=get_reg_temp(regs[i+1].regmap);
8432 regs[i+1].regmap[hr]=AGEN1+((i+1)&1);
8433 regs[i+1].isconst&=~(1<<hr);
8434 regs[i+1].dirty&=~(1<<hr);
8435 regs[i+2].wasdirty&=~(1<<hr);
8438 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
8440 regs[i].regmap[hr]=dops[i+1].rs1;
8441 regmap_pre[i+1][hr]=dops[i+1].rs1;
8442 regs[i+1].regmap_entry[hr]=dops[i+1].rs1;
8443 regs[i].isconst&=~(1<<hr);
8444 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
8445 constmap[i][hr]=constmap[i+1][hr];
8446 regs[i+1].wasdirty&=~(1<<hr);
8447 regs[i].dirty&=~(1<<hr);
8451 if (dops[i+1].itype == LOADLR || dops[i+1].opcode == 0x32) { // LWC2
8452 if(get_reg(regs[i+1].regmap,dops[i+1].rs1)<0) {
8454 hr=get_reg(regs[i+1].regmap,FTEMP);
8456 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
8458 regs[i].regmap[hr]=dops[i+1].rs1;
8459 regmap_pre[i+1][hr]=dops[i+1].rs1;
8460 regs[i+1].regmap_entry[hr]=dops[i+1].rs1;
8461 regs[i].isconst&=~(1<<hr);
8462 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
8463 constmap[i][hr]=constmap[i+1][hr];
8464 regs[i+1].wasdirty&=~(1<<hr);
8465 regs[i].dirty&=~(1<<hr);
8467 else if((nr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1))>=0)
8469 // move it to another register
8470 regs[i+1].regmap[hr]=-1;
8471 regmap_pre[i+2][hr]=-1;
8472 regs[i+1].regmap[nr]=FTEMP;
8473 regmap_pre[i+2][nr]=FTEMP;
8474 regs[i].regmap[nr]=dops[i+1].rs1;
8475 regmap_pre[i+1][nr]=dops[i+1].rs1;
8476 regs[i+1].regmap_entry[nr]=dops[i+1].rs1;
8477 regs[i].isconst&=~(1<<nr);
8478 regs[i+1].isconst&=~(1<<nr);
8479 regs[i].dirty&=~(1<<nr);
8480 regs[i+1].wasdirty&=~(1<<nr);
8481 regs[i+1].dirty&=~(1<<nr);
8482 regs[i+2].wasdirty&=~(1<<nr);
8486 if(dops[i+1].itype==LOAD||dops[i+1].itype==LOADLR||dops[i+1].itype==STORE||dops[i+1].itype==STORELR/*||dops[i+1].itype==C2LS*/) {
8488 if(dops[i+1].itype==LOAD)
8489 hr=get_reg_w(regs[i+1].regmap, dops[i+1].rt1);
8490 if (dops[i+1].itype == LOADLR || dops[i+1].opcode == 0x32) // LWC2
8491 hr=get_reg(regs[i+1].regmap,FTEMP);
8492 if (dops[i+1].is_store) {
8493 hr=get_reg(regs[i+1].regmap,AGEN1+((i+1)&1));
8494 if(hr<0) hr=get_reg_temp(regs[i+1].regmap);
8496 if(hr>=0&®s[i].regmap[hr]<0) {
8497 int rs=get_reg(regs[i+1].regmap,dops[i+1].rs1);
8498 if(rs>=0&&((regs[i+1].wasconst>>rs)&1)) {
8499 regs[i].regmap[hr]=AGEN1+((i+1)&1);
8500 regmap_pre[i+1][hr]=AGEN1+((i+1)&1);
8501 regs[i+1].regmap_entry[hr]=AGEN1+((i+1)&1);
8502 regs[i].isconst&=~(1<<hr);
8503 regs[i+1].wasdirty&=~(1<<hr);
8504 regs[i].dirty&=~(1<<hr);
8514 // Write back dirty registers as soon as we will no longer modify them,
8515 // so that we don't end up with lots of writes at the branches.
8516 static noinline void pass6_clean_registers(int istart, int iend, int wr)
8518 static u_int wont_dirty[MAXBLOCK];
8519 static u_int will_dirty[MAXBLOCK];
8522 u_int will_dirty_i,will_dirty_next,temp_will_dirty;
8523 u_int wont_dirty_i,wont_dirty_next,temp_wont_dirty;
8525 will_dirty_i=will_dirty_next=0;
8526 wont_dirty_i=wont_dirty_next=0;
8528 will_dirty_i=will_dirty_next=will_dirty[iend+1];
8529 wont_dirty_i=wont_dirty_next=wont_dirty[iend+1];
8531 for (i=iend;i>=istart;i--)
8533 signed char rregmap_i[RRMAP_SIZE];
8534 u_int hr_candirty = 0;
8535 assert(HOST_REGS < 32);
8536 make_rregs(regs[i].regmap, rregmap_i, &hr_candirty);
8537 __builtin_prefetch(regs[i-1].regmap);
8540 signed char branch_rregmap_i[RRMAP_SIZE];
8541 u_int branch_hr_candirty = 0;
8542 make_rregs(branch_regs[i].regmap, branch_rregmap_i, &branch_hr_candirty);
8543 if(cinfo[i].ba<start || cinfo[i].ba>=(start+slen*4))
8545 // Branch out of this block, flush all regs
8547 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt1) & 31);
8548 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt2) & 31);
8549 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt1) & 31);
8550 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt2) & 31);
8551 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, CCREG) & 31);
8552 will_dirty_i &= branch_hr_candirty;
8553 if (dops[i].is_ujump)
8555 // Unconditional branch
8557 // Merge in delay slot (will dirty)
8558 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31);
8559 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31);
8560 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt1) & 31);
8561 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt2) & 31);
8562 will_dirty_i |= 1u << (get_rreg(rregmap_i, CCREG) & 31);
8563 will_dirty_i &= hr_candirty;
8567 // Conditional branch
8568 wont_dirty_i = wont_dirty_next;
8569 // Merge in delay slot (will dirty)
8570 // (the original code had no explanation why these 2 are commented out)
8571 //will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31);
8572 //will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31);
8573 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt1) & 31);
8574 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt2) & 31);
8575 will_dirty_i |= 1u << (get_rreg(rregmap_i, CCREG) & 31);
8576 will_dirty_i &= hr_candirty;
8578 // Merge in delay slot (wont dirty)
8579 wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31);
8580 wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31);
8581 wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt1) & 31);
8582 wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt2) & 31);
8583 wont_dirty_i |= 1u << (get_rreg(rregmap_i, CCREG) & 31);
8584 wont_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt1) & 31);
8585 wont_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt2) & 31);
8586 wont_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt1) & 31);
8587 wont_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt2) & 31);
8588 wont_dirty_i |= 1u << (get_rreg(branch_rregmap_i, CCREG) & 31);
8589 wont_dirty_i &= ~(1u << 31);
8591 #ifndef DESTRUCTIVE_WRITEBACK
8592 branch_regs[i].dirty&=wont_dirty_i;
8594 branch_regs[i].dirty|=will_dirty_i;
8600 if(cinfo[i].ba<=start+i*4) {
8602 if (dops[i].is_ujump)
8604 // Unconditional branch
8607 // Merge in delay slot (will dirty)
8608 temp_will_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt1) & 31);
8609 temp_will_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt2) & 31);
8610 temp_will_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt1) & 31);
8611 temp_will_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt2) & 31);
8612 temp_will_dirty |= 1u << (get_rreg(branch_rregmap_i, CCREG) & 31);
8613 temp_will_dirty &= branch_hr_candirty;
8614 temp_will_dirty |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31);
8615 temp_will_dirty |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31);
8616 temp_will_dirty |= 1u << (get_rreg(rregmap_i, dops[i+1].rt1) & 31);
8617 temp_will_dirty |= 1u << (get_rreg(rregmap_i, dops[i+1].rt2) & 31);
8618 temp_will_dirty |= 1u << (get_rreg(rregmap_i, CCREG) & 31);
8619 temp_will_dirty &= hr_candirty;
8621 // Conditional branch (not taken case)
8622 temp_will_dirty=will_dirty_next;
8623 temp_wont_dirty=wont_dirty_next;
8624 // Merge in delay slot (will dirty)
8625 temp_will_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt1) & 31);
8626 temp_will_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt2) & 31);
8627 temp_will_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt1) & 31);
8628 temp_will_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt2) & 31);
8629 temp_will_dirty |= 1u << (get_rreg(branch_rregmap_i, CCREG) & 31);
8630 temp_will_dirty &= branch_hr_candirty;
8631 //temp_will_dirty |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31);
8632 //temp_will_dirty |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31);
8633 temp_will_dirty |= 1u << (get_rreg(rregmap_i, dops[i+1].rt1) & 31);
8634 temp_will_dirty |= 1u << (get_rreg(rregmap_i, dops[i+1].rt2) & 31);
8635 temp_will_dirty |= 1u << (get_rreg(rregmap_i, CCREG) & 31);
8636 temp_will_dirty &= hr_candirty;
8638 // Merge in delay slot (wont dirty)
8639 temp_wont_dirty |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31);
8640 temp_wont_dirty |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31);
8641 temp_wont_dirty |= 1u << (get_rreg(rregmap_i, dops[i+1].rt1) & 31);
8642 temp_wont_dirty |= 1u << (get_rreg(rregmap_i, dops[i+1].rt2) & 31);
8643 temp_wont_dirty |= 1u << (get_rreg(rregmap_i, CCREG) & 31);
8644 temp_wont_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt1) & 31);
8645 temp_wont_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt2) & 31);
8646 temp_wont_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt1) & 31);
8647 temp_wont_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt2) & 31);
8648 temp_wont_dirty |= 1u << (get_rreg(branch_rregmap_i, CCREG) & 31);
8649 temp_wont_dirty &= ~(1u << 31);
8650 // Deal with changed mappings
8652 for(r=0;r<HOST_REGS;r++) {
8653 if(r!=EXCLUDE_REG) {
8654 if(regs[i].regmap[r]!=regmap_pre[i][r]) {
8655 temp_will_dirty&=~(1<<r);
8656 temp_wont_dirty&=~(1<<r);
8657 if(regmap_pre[i][r]>0 && regmap_pre[i][r]<34) {
8658 temp_will_dirty|=((unneeded_reg[i]>>regmap_pre[i][r])&1)<<r;
8659 temp_wont_dirty|=((unneeded_reg[i]>>regmap_pre[i][r])&1)<<r;
8661 temp_will_dirty|=1<<r;
8662 temp_wont_dirty|=1<<r;
8669 will_dirty[i]=temp_will_dirty;
8670 wont_dirty[i]=temp_wont_dirty;
8671 pass6_clean_registers((cinfo[i].ba-start)>>2,i-1,0);
8673 // Limit recursion. It can take an excessive amount
8674 // of time if there are a lot of nested loops.
8675 will_dirty[(cinfo[i].ba-start)>>2]=0;
8676 wont_dirty[(cinfo[i].ba-start)>>2]=-1;
8681 if (dops[i].is_ujump)
8683 // Unconditional branch
8686 //if(cinfo[i].ba>start+i*4) { // Disable recursion (for debugging)
8687 for(r=0;r<HOST_REGS;r++) {
8688 if(r!=EXCLUDE_REG) {
8689 if(branch_regs[i].regmap[r]==regs[(cinfo[i].ba-start)>>2].regmap_entry[r]) {
8690 will_dirty_i|=will_dirty[(cinfo[i].ba-start)>>2]&(1<<r);
8691 wont_dirty_i|=wont_dirty[(cinfo[i].ba-start)>>2]&(1<<r);
8693 if(branch_regs[i].regmap[r]>=0) {
8694 will_dirty_i|=((unneeded_reg[(cinfo[i].ba-start)>>2]>>branch_regs[i].regmap[r])&1)<<r;
8695 wont_dirty_i|=((unneeded_reg[(cinfo[i].ba-start)>>2]>>branch_regs[i].regmap[r])&1)<<r;
8700 // Merge in delay slot
8701 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt1) & 31);
8702 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt2) & 31);
8703 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt1) & 31);
8704 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt2) & 31);
8705 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, CCREG) & 31);
8706 will_dirty_i &= branch_hr_candirty;
8707 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31);
8708 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31);
8709 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt1) & 31);
8710 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt2) & 31);
8711 will_dirty_i |= 1u << (get_rreg(rregmap_i, CCREG) & 31);
8712 will_dirty_i &= hr_candirty;
8714 // Conditional branch
8715 will_dirty_i=will_dirty_next;
8716 wont_dirty_i=wont_dirty_next;
8717 //if(cinfo[i].ba>start+i*4) // Disable recursion (for debugging)
8718 for(r=0;r<HOST_REGS;r++) {
8719 if(r!=EXCLUDE_REG) {
8720 signed char target_reg=branch_regs[i].regmap[r];
8721 if(target_reg==regs[(cinfo[i].ba-start)>>2].regmap_entry[r]) {
8722 will_dirty_i&=will_dirty[(cinfo[i].ba-start)>>2]&(1<<r);
8723 wont_dirty_i|=wont_dirty[(cinfo[i].ba-start)>>2]&(1<<r);
8725 else if(target_reg>=0) {
8726 will_dirty_i&=((unneeded_reg[(cinfo[i].ba-start)>>2]>>target_reg)&1)<<r;
8727 wont_dirty_i|=((unneeded_reg[(cinfo[i].ba-start)>>2]>>target_reg)&1)<<r;
8731 // Merge in delay slot
8732 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt1) & 31);
8733 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt2) & 31);
8734 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt1) & 31);
8735 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt2) & 31);
8736 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, CCREG) & 31);
8737 will_dirty_i &= branch_hr_candirty;
8738 //will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31);
8739 //will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31);
8740 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt1) & 31);
8741 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt2) & 31);
8742 will_dirty_i |= 1u << (get_rreg(rregmap_i, CCREG) & 31);
8743 will_dirty_i &= hr_candirty;
8745 // Merge in delay slot (won't dirty)
8746 wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31);
8747 wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31);
8748 wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt1) & 31);
8749 wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt2) & 31);
8750 wont_dirty_i |= 1u << (get_rreg(rregmap_i, CCREG) & 31);
8751 wont_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt1) & 31);
8752 wont_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt2) & 31);
8753 wont_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt1) & 31);
8754 wont_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt2) & 31);
8755 wont_dirty_i |= 1u << (get_rreg(branch_rregmap_i, CCREG) & 31);
8756 wont_dirty_i &= ~(1u << 31);
8758 #ifndef DESTRUCTIVE_WRITEBACK
8759 branch_regs[i].dirty&=wont_dirty_i;
8761 branch_regs[i].dirty|=will_dirty_i;
8766 else if (dops[i].is_exception)
8768 // SYSCALL instruction, etc
8772 will_dirty_next=will_dirty_i;
8773 wont_dirty_next=wont_dirty_i;
8774 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31);
8775 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31);
8776 will_dirty_i |= 1u << (get_rreg(rregmap_i, CCREG) & 31);
8777 will_dirty_i &= hr_candirty;
8778 wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31);
8779 wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31);
8780 wont_dirty_i |= 1u << (get_rreg(rregmap_i, CCREG) & 31);
8781 wont_dirty_i &= ~(1u << 31);
8782 if (i > istart && !dops[i].is_jump) {
8783 // Don't store a register immediately after writing it,
8784 // may prevent dual-issue.
8785 wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i-1].rt1) & 31);
8786 wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i-1].rt2) & 31);
8789 will_dirty[i]=will_dirty_i;
8790 wont_dirty[i]=wont_dirty_i;
8791 // Mark registers that won't be dirtied as not dirty
8793 regs[i].dirty|=will_dirty_i;
8794 #ifndef DESTRUCTIVE_WRITEBACK
8795 regs[i].dirty&=wont_dirty_i;
8798 if (i < iend-1 && !dops[i].is_ujump) {
8799 for(r=0;r<HOST_REGS;r++) {
8800 if(r!=EXCLUDE_REG) {
8801 if(regs[i].regmap[r]==regmap_pre[i+2][r]) {
8802 regs[i+2].wasdirty&=wont_dirty_i|~(1<<r);
8803 }else {/*printf("i: %x (%d) mismatch(+2): %d\n",start+i*4,i,r);assert(!((wont_dirty_i>>r)&1));*/}
8811 for(r=0;r<HOST_REGS;r++) {
8812 if(r!=EXCLUDE_REG) {
8813 if(regs[i].regmap[r]==regmap_pre[i+1][r]) {
8814 regs[i+1].wasdirty&=wont_dirty_i|~(1<<r);
8815 }else {/*printf("i: %x (%d) mismatch(+1): %d\n",start+i*4,i,r);assert(!((wont_dirty_i>>r)&1));*/}
8822 // Deal with changed mappings
8823 temp_will_dirty=will_dirty_i;
8824 temp_wont_dirty=wont_dirty_i;
8825 for(r=0;r<HOST_REGS;r++) {
8826 if(r!=EXCLUDE_REG) {
8828 if(regs[i].regmap[r]==regmap_pre[i][r]) {
8830 #ifndef DESTRUCTIVE_WRITEBACK
8831 regs[i].wasdirty&=wont_dirty_i|~(1<<r);
8833 regs[i].wasdirty|=will_dirty_i&(1<<r);
8836 else if(regmap_pre[i][r]>=0&&(nr=get_rreg(rregmap_i,regmap_pre[i][r]))>=0) {
8837 // Register moved to a different register
8838 will_dirty_i&=~(1<<r);
8839 wont_dirty_i&=~(1<<r);
8840 will_dirty_i|=((temp_will_dirty>>nr)&1)<<r;
8841 wont_dirty_i|=((temp_wont_dirty>>nr)&1)<<r;
8843 #ifndef DESTRUCTIVE_WRITEBACK
8844 regs[i].wasdirty&=wont_dirty_i|~(1<<r);
8846 regs[i].wasdirty|=will_dirty_i&(1<<r);
8850 will_dirty_i&=~(1<<r);
8851 wont_dirty_i&=~(1<<r);
8852 if(regmap_pre[i][r]>0 && regmap_pre[i][r]<34) {
8853 will_dirty_i|=((unneeded_reg[i]>>regmap_pre[i][r])&1)<<r;
8854 wont_dirty_i|=((unneeded_reg[i]>>regmap_pre[i][r])&1)<<r;
8857 /*printf("i: %x (%d) mismatch: %d\n",start+i*4,i,r);assert(!((will_dirty>>r)&1));*/
8865 static noinline void pass10_expire_blocks(void)
8867 u_int step = MAX_OUTPUT_BLOCK_SIZE / PAGE_COUNT / 2;
8868 // not sizeof(ndrc->translation_cache) due to vita hack
8869 u_int step_mask = ((1u << TARGET_SIZE_2) - 1u) & ~(step - 1u);
8870 u_int end = (out - ndrc->translation_cache + EXPIRITY_OFFSET) & step_mask;
8871 u_int base_shift = __builtin_ctz(MAX_OUTPUT_BLOCK_SIZE);
8874 for (; expirep != end; expirep = ((expirep + step) & step_mask))
8876 u_int base_offs = expirep & ~(MAX_OUTPUT_BLOCK_SIZE - 1);
8877 u_int block_i = expirep / step & (PAGE_COUNT - 1);
8878 u_int phase = (expirep >> (base_shift - 1)) & 1u;
8879 if (!(expirep & (MAX_OUTPUT_BLOCK_SIZE / 2 - 1))) {
8880 inv_debug("EXP: base_offs %x/%lx phase %u\n", base_offs,
8881 (long)(out - ndrc->translation_cache), phase);
8885 hit = blocks_remove_matching_addrs(&blocks[block_i], base_offs, base_shift);
8889 memset(mini_ht, -1, sizeof(mini_ht));
8894 unlink_jumps_tc_range(jumps[block_i], base_offs, base_shift);
8898 static struct block_info *new_block_info(u_int start, u_int len,
8899 const void *source, const void *copy, u_char *beginning, u_short jump_in_count)
8901 struct block_info **b_pptr;
8902 struct block_info *block;
8903 u_int page = get_page(start);
8905 block = malloc(sizeof(*block) + jump_in_count * sizeof(block->jump_in[0]));
8907 assert(jump_in_count > 0);
8908 block->source = source;
8910 block->start = start;
8912 block->reg_sv_flags = 0;
8913 block->tc_offs = beginning - ndrc->translation_cache;
8914 //block->tc_len = out - beginning;
8915 block->is_dirty = 0;
8916 block->inv_near_misses = 0;
8917 block->jump_in_cnt = jump_in_count;
8919 // insert sorted by start mirror-unmasked vaddr
8920 for (b_pptr = &blocks[page]; ; b_pptr = &((*b_pptr)->next)) {
8921 if (*b_pptr == NULL || (*b_pptr)->start >= start) {
8922 block->next = *b_pptr;
8927 stat_inc(stat_blocks);
8931 static int new_recompile_block(u_int addr)
8933 u_int pagelimit = 0;
8934 u_int state_rflags = 0;
8937 assem_debug("NOTCOMPILED: addr = %x -> %p\n", addr, out);
8940 if (addr != hack_addr) {
8941 SysPrintf("game crash @%08x, ra=%08x\n", addr, psxRegs.GPR.n.ra);
8947 // this is just for speculation
8948 for (i = 1; i < 32; i++) {
8949 if ((psxRegs.GPR.r[i] & 0xffff0000) == 0x1f800000)
8950 state_rflags |= 1 << i;
8954 new_dynarec_did_compile=1;
8955 if (Config.HLE && start == 0x80001000) // hlecall
8957 // XXX: is this enough? Maybe check hleSoftCall?
8958 void *beginning = start_block();
8960 emit_movimm(start,0);
8961 emit_writeword(0,&pcaddr);
8962 emit_far_jump(new_dyna_leave);
8964 end_block(beginning);
8965 struct block_info *block = new_block_info(start, 4, NULL, NULL, beginning, 1);
8966 block->jump_in[0].vaddr = start;
8967 block->jump_in[0].addr = beginning;
8970 else if (f1_hack && hack_addr == 0) {
8971 void *beginning = start_block();
8972 emit_movimm(start, 0);
8973 emit_writeword(0, &hack_addr);
8974 emit_readword(&psxRegs.GPR.n.sp, 0);
8975 emit_readptr(&mem_rtab, 1);
8976 emit_shrimm(0, 12, 2);
8977 emit_readptr_dualindexedx_ptrlen(1, 2, 1);
8978 emit_addimm(0, 0x18, 0);
8979 emit_adds_ptr(1, 1, 1);
8980 emit_ldr_dualindexed(1, 0, 0);
8981 emit_writeword(0, &psxRegs.GPR.r[26]); // lw k0, 0x18(sp)
8982 emit_far_call(ndrc_get_addr_ht);
8983 emit_jmpreg(0); // jr k0
8985 end_block(beginning);
8987 struct block_info *block = new_block_info(start, 4, NULL, NULL, beginning, 1);
8988 block->jump_in[0].vaddr = start;
8989 block->jump_in[0].addr = beginning;
8990 SysPrintf("F1 hack to %08x\n", start);
8994 cycle_multiplier_active = Config.cycle_multiplier_override && Config.cycle_multiplier == CYCLE_MULT_DEFAULT
8995 ? Config.cycle_multiplier_override : Config.cycle_multiplier;
8997 source = get_source_start(start, &pagelimit);
8998 if (source == NULL) {
8999 if (addr != hack_addr) {
9000 SysPrintf("Compile at bogus memory address: %08x\n", addr);
9007 /* Pass 1: disassemble */
9008 /* Pass 2: register dependencies, branch targets */
9009 /* Pass 3: register allocation */
9010 /* Pass 4: branch dependencies */
9011 /* Pass 5: pre-alloc */
9012 /* Pass 6: optimize clean/dirty state */
9013 /* Pass 7: flag 32-bit registers */
9014 /* Pass 8: assembly */
9015 /* Pass 9: linker */
9016 /* Pass 10: garbage collection / free memory */
9018 /* Pass 1 disassembly */
9020 pass1_disassemble(pagelimit);
9022 int clear_hack_addr = apply_hacks();
9024 /* Pass 2 - Register dependencies and branch targets */
9026 pass2_unneeded_regs(0,slen-1,0);
9028 /* Pass 3 - Register allocation */
9030 pass3_register_alloc(addr);
9032 /* Pass 4 - Cull unused host registers */
9034 pass4_cull_unused_regs();
9036 /* Pass 5 - Pre-allocate registers */
9038 pass5a_preallocate1();
9039 pass5b_preallocate2();
9041 /* Pass 6 - Optimize clean/dirty state */
9042 pass6_clean_registers(0, slen-1, 1);
9044 /* Pass 7 - Identify 32-bit registers */
9045 for (i=slen-1;i>=0;i--)
9047 if(dops[i].itype==CJUMP||dops[i].itype==SJUMP)
9049 // Conditional branch
9050 if((source[i]>>16)!=0x1000&&i<slen-2) {
9051 // Mark this address as a branch target since it may be called
9052 // upon return from interrupt
9058 /* Pass 8 - Assembly */
9059 linkcount=0;stubcount=0;
9062 void *beginning=start_block();
9063 void *instr_addr0_override = NULL;
9066 if (start == 0x80030000) {
9067 // nasty hack for the fastbios thing
9068 // override block entry to this code
9069 instr_addr0_override = out;
9070 emit_movimm(start,0);
9071 // abuse io address var as a flag that we
9072 // have already returned here once
9073 emit_readword(&address,1);
9074 emit_writeword(0,&pcaddr);
9075 emit_writeword(0,&address);
9078 emit_jeq(out + 4*2);
9079 emit_far_jump(new_dyna_leave);
9081 emit_jne(new_dyna_leave);
9086 __builtin_prefetch(regs[i+1].regmap);
9087 check_regmap(regmap_pre[i]);
9088 check_regmap(regs[i].regmap_entry);
9089 check_regmap(regs[i].regmap);
9090 //if(ds) printf("ds: ");
9091 disassemble_inst(i);
9093 ds=0; // Skip delay slot
9094 if(dops[i].bt) assem_debug("OOPS - branch into delay slot\n");
9095 instr_addr[i] = NULL;
9097 speculate_register_values(i);
9098 #ifndef DESTRUCTIVE_WRITEBACK
9099 if (i < 2 || !dops[i-2].is_ujump)
9101 wb_valid(regmap_pre[i],regs[i].regmap_entry,dirty_pre,regs[i].wasdirty,unneeded_reg[i]);
9103 if((dops[i].itype==CJUMP||dops[i].itype==SJUMP)) {
9104 dirty_pre=branch_regs[i].dirty;
9106 dirty_pre=regs[i].dirty;
9110 if (i < 2 || !dops[i-2].is_ujump)
9112 wb_invalidate(regmap_pre[i],regs[i].regmap_entry,regs[i].wasdirty,unneeded_reg[i]);
9113 loop_preload(regmap_pre[i],regs[i].regmap_entry);
9115 // branch target entry point
9116 instr_addr[i] = out;
9117 assem_debug("<->\n");
9118 drc_dbg_emit_do_cmp(i, cinfo[i].ccadj);
9119 if (clear_hack_addr) {
9121 emit_writeword(0, &hack_addr);
9122 clear_hack_addr = 0;
9126 if(regs[i].regmap_entry[HOST_CCREG]==CCREG&®s[i].regmap[HOST_CCREG]!=CCREG)
9127 wb_register(CCREG,regs[i].regmap_entry,regs[i].wasdirty);
9128 load_regs(regs[i].regmap_entry,regs[i].regmap,dops[i].rs1,dops[i].rs2);
9129 address_generation(i,®s[i],regs[i].regmap_entry);
9130 load_consts(regmap_pre[i],regs[i].regmap,i);
9133 // Load the delay slot registers if necessary
9134 if(dops[i+1].rs1!=dops[i].rs1&&dops[i+1].rs1!=dops[i].rs2&&(dops[i+1].rs1!=dops[i].rt1||dops[i].rt1==0))
9135 load_regs(regs[i].regmap_entry,regs[i].regmap,dops[i+1].rs1,dops[i+1].rs1);
9136 if(dops[i+1].rs2!=dops[i+1].rs1&&dops[i+1].rs2!=dops[i].rs1&&dops[i+1].rs2!=dops[i].rs2&&(dops[i+1].rs2!=dops[i].rt1||dops[i].rt1==0))
9137 load_regs(regs[i].regmap_entry,regs[i].regmap,dops[i+1].rs2,dops[i+1].rs2);
9138 if (ram_offset && (dops[i+1].is_load || dops[i+1].is_store))
9139 load_reg(regs[i].regmap_entry,regs[i].regmap,ROREG);
9140 if (dops[i+1].is_store)
9141 load_reg(regs[i].regmap_entry,regs[i].regmap,INVCP);
9145 // Preload registers for following instruction
9146 if(dops[i+1].rs1!=dops[i].rs1&&dops[i+1].rs1!=dops[i].rs2)
9147 if(dops[i+1].rs1!=dops[i].rt1&&dops[i+1].rs1!=dops[i].rt2)
9148 load_regs(regs[i].regmap_entry,regs[i].regmap,dops[i+1].rs1,dops[i+1].rs1);
9149 if(dops[i+1].rs2!=dops[i+1].rs1&&dops[i+1].rs2!=dops[i].rs1&&dops[i+1].rs2!=dops[i].rs2)
9150 if(dops[i+1].rs2!=dops[i].rt1&&dops[i+1].rs2!=dops[i].rt2)
9151 load_regs(regs[i].regmap_entry,regs[i].regmap,dops[i+1].rs2,dops[i+1].rs2);
9153 // TODO: if(is_ooo(i)) address_generation(i+1);
9154 if (!dops[i].is_jump || dops[i].itype == CJUMP)
9155 load_reg(regs[i].regmap_entry,regs[i].regmap,CCREG);
9156 if (ram_offset && (dops[i].is_load || dops[i].is_store))
9157 load_reg(regs[i].regmap_entry,regs[i].regmap,ROREG);
9158 if (dops[i].is_store)
9159 load_reg(regs[i].regmap_entry,regs[i].regmap,INVCP);
9161 ds = assemble(i, ®s[i], cinfo[i].ccadj);
9163 if (dops[i].is_ujump)
9166 literal_pool_jumpover(256);
9171 if (slen > 0 && dops[slen-1].itype == INTCALL) {
9172 // no ending needed for this block since INTCALL never returns
9174 // If the block did not end with an unconditional branch,
9175 // add a jump to the next instruction.
9177 if (!dops[i-2].is_ujump) {
9178 assert(!dops[i-1].is_jump);
9180 if(dops[i-2].itype!=CJUMP&&dops[i-2].itype!=SJUMP) {
9181 store_regs_bt(regs[i-1].regmap,regs[i-1].dirty,start+i*4);
9182 if(regs[i-1].regmap[HOST_CCREG]!=CCREG)
9183 emit_loadreg(CCREG,HOST_CCREG);
9184 emit_addimm(HOST_CCREG, cinfo[i-1].ccadj + CLOCK_ADJUST(1), HOST_CCREG);
9188 store_regs_bt(branch_regs[i-2].regmap,branch_regs[i-2].dirty,start+i*4);
9189 assert(branch_regs[i-2].regmap[HOST_CCREG]==CCREG);
9191 add_to_linker(out,start+i*4,0);
9198 assert(!dops[i-1].is_jump);
9199 store_regs_bt(regs[i-1].regmap,regs[i-1].dirty,start+i*4);
9200 if(regs[i-1].regmap[HOST_CCREG]!=CCREG)
9201 emit_loadreg(CCREG,HOST_CCREG);
9202 emit_addimm(HOST_CCREG, cinfo[i-1].ccadj + CLOCK_ADJUST(1), HOST_CCREG);
9203 add_to_linker(out,start+i*4,0);
9208 for(i = 0; i < stubcount; i++)
9210 switch(stubs[i].type)
9217 do_readstub(i);break;
9221 do_writestub(i);break;
9225 do_invstub(i);break;
9227 do_unalignedwritestub(i);break;
9229 do_overflowstub(i); break;
9230 case ALIGNMENT_STUB:
9231 do_alignmentstub(i); break;
9237 if (instr_addr0_override)
9238 instr_addr[0] = instr_addr0_override;
9241 /* check for improper expiration */
9242 for (i = 0; i < ARRAY_SIZE(jumps); i++) {
9246 for (j = 0; j < jumps[i]->count; j++)
9247 assert(jumps[i]->e[j].stub < beginning || (u_char *)jumps[i]->e[j].stub > out);
9251 /* Pass 9 - Linker */
9252 for(i=0;i<linkcount;i++)
9254 assem_debug("%p -> %8x\n",link_addr[i].addr,link_addr[i].target);
9256 if (!link_addr[i].internal)
9259 void *addr = check_addr(link_addr[i].target);
9260 emit_extjump(link_addr[i].addr, link_addr[i].target);
9262 set_jump_target(link_addr[i].addr, addr);
9263 ndrc_add_jump_out(link_addr[i].target,stub);
9266 set_jump_target(link_addr[i].addr, stub);
9271 int target=(link_addr[i].target-start)>>2;
9272 assert(target>=0&&target<slen);
9273 assert(instr_addr[target]);
9274 //#ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
9275 //set_jump_target_fillslot(link_addr[i].addr,instr_addr[target],link_addr[i].ext>>1);
9277 set_jump_target(link_addr[i].addr, instr_addr[target]);
9282 u_int source_len = slen*4;
9283 if (dops[slen-1].itype == INTCALL && source_len > 4)
9284 // no need to treat the last instruction as compiled
9285 // as interpreter fully handles it
9288 if ((u_char *)copy + source_len > (u_char *)shadow + sizeof(shadow))
9291 // External Branch Targets (jump_in)
9292 int jump_in_count = 1;
9293 assert(instr_addr[0]);
9294 for (i = 1; i < slen; i++)
9296 if (dops[i].bt && instr_addr[i])
9300 struct block_info *block =
9301 new_block_info(start, slen * 4, source, copy, beginning, jump_in_count);
9302 block->reg_sv_flags = state_rflags;
9305 for (i = 0; i < slen; i++)
9307 if ((i == 0 || dops[i].bt) && instr_addr[i])
9309 assem_debug("%p (%d) <- %8x\n", instr_addr[i], i, start + i*4);
9310 u_int vaddr = start + i*4;
9316 entry = instr_addr[i];
9318 emit_jmp(instr_addr[i]);
9320 block->jump_in[jump_in_i].vaddr = vaddr;
9321 block->jump_in[jump_in_i].addr = entry;
9325 assert(jump_in_i == jump_in_count);
9326 hash_table_add(block->jump_in[0].vaddr, block->jump_in[0].addr);
9327 // Write out the literal pool if necessary
9329 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
9331 if(((u_int)out)&7) emit_addnop(13);
9333 assert(out - (u_char *)beginning < MAX_OUTPUT_BLOCK_SIZE);
9334 //printf("shadow buffer: %p-%p\n",copy,(u_char *)copy+slen*4);
9335 memcpy(copy, source, source_len);
9338 end_block(beginning);
9340 // If we're within 256K of the end of the buffer,
9341 // start over from the beginning. (Is 256K enough?)
9342 if (out > ndrc->translation_cache + sizeof(ndrc->translation_cache) - MAX_OUTPUT_BLOCK_SIZE)
9343 out = ndrc->translation_cache;
9345 // Trap writes to any of the pages we compiled
9346 mark_invalid_code(start, slen*4, 0);
9348 /* Pass 10 - Free memory by expiring oldest blocks */
9350 pass10_expire_blocks();
9355 stat_inc(stat_bc_direct);
9359 // vim:shiftwidth=2:expandtab