libpcsxcore/new_dynarec/pcsxmem.c

   1 /*
   2  * (C) Gražvydas "notaz" Ignotas, 2010-2011
   3  *
   4  * This work is licensed under the terms of GNU GPL version 2 or later.
   5  * See the COPYING file in the top-level directory.
   6  */
   7
   8 #include <stdio.h>
   9 #include "../psxhw.h"
  10 #include "../cdrom.h"
  11 #include "../mdec.h"
  12 #include "../gpu.h"
  13 #include "../psxmem_map.h"
  14 #include "emu_if.h"
  15 #include "pcsxmem.h"
  16
  17 #ifdef __thumb__
  18 #error the dynarec is incompatible with Thumb functions,
  19 #error please add -marm to compile flags
  20 #endif
  21
  22 //#define memprintf printf
  23 #define memprintf(...)
  24
  25 static uintptr_t *mem_readtab;
  26 static uintptr_t *mem_writetab;
  27 static uintptr_t mem_iortab[(1+2+4) * 0x1000 / 4];
  28 static uintptr_t mem_iowtab[(1+2+4) * 0x1000 / 4];
  29 static uintptr_t mem_ffrtab[(1+2+4) * 0x1000 / 4];
  30 static uintptr_t mem_ffwtab[(1+2+4) * 0x1000 / 4];
  31 //static uintptr_t mem_unmrtab[(1+2+4) * 0x1000 / 4];
  32 static uintptr_t mem_unmwtab[(1+2+4) * 0x1000 / 4];
  33
  34 static
  35 #ifdef __clang__
  36 // When this is called in a loop, and 'h' is a function pointer, clang will crash.
  37 __attribute__ ((noinline))
  38 #endif
  39 void map_item(uintptr_t *out, const void *h, uintptr_t flag)
  40 {
  41         uintptr_t hv = (uintptr_t)h;
  42         if (hv & 1) {
  43                 SysPrintf("FATAL: %p has LSB set\n", h);
  44                 abort();
  45         }
  46         *out = (hv >> 1) | (flag << (sizeof(hv) * 8 - 1));
  47 }
  48
  49 // size must be power of 2, at least 4k
  50 #define map_l1_mem(tab, i, addr, size, base) \
  51         map_item(&tab[((u32)(addr) >> 12) + i], \
  52                  (u8 *)(base) - (u32)((addr) + ((i << 12) & ~(size - 1))), 0)
  53
  54 #define IOMEM32(a) (((a) & 0xfff) / 4)
  55 #define IOMEM16(a) (0x1000/4 + (((a) & 0xfff) / 2))
  56 #define IOMEM8(a)  (0x1000/4 + 0x1000/2 + ((a) & 0xfff))
  57
  58 u32 zero_mem[0x1000/4];
  59 static u32 ffff_mem[0x1000/4];
  60
  61 static u32 read_mem_dummy(u32 addr)
  62 {
  63         // use 'addr' and not 'address', yes the api is weird...
  64         memprintf("unmapped r %08x @%08x %u\n", addr, psxRegs.pc, psxRegs.cycle);
  65         return 0xffffffff;
  66 }
  67
  68 static void write_mem_dummy(u32 data)
  69 {
  70         if (!(psxRegs.CP0.n.SR & (1 << 16)))
  71                 memprintf("unmapped w %08x, %08x @%08x %u\n",
  72                           address, data, psxRegs.pc, psxRegs.cycle);
  73 }
  74
  75 /* IO handlers */
  76 static u32 io_read_sio16()
  77 {
  78         return sioRead8();
  79 }
  80
  81 static u32 io_read_sio32()
  82 {
  83         return sioRead8();
  84 }
  85
  86 static void io_write_sio16(u32 value)
  87 {
  88         sioWrite8((unsigned char)value);
  89         sioWrite8((unsigned char)(value>>8));
  90 }
  91
  92 static void io_write_sio32(u32 value)
  93 {
  94         sioWrite8((unsigned char)value);
  95         sioWrite8((unsigned char)(value >>  8));
  96         sioWrite8((unsigned char)(value >> 16));
  97         sioWrite8((unsigned char)(value >> 24));
  98 }
  99
 100 static u32 io_read_sio2_status()
 101 {
 102         return 0x80;
 103 }
 104
 105 #if !defined(DRC_DBG) && defined(__arm__)
 106
 107 static void map_rcnt_rcount0(u32 mode)
 108 {
 109         if (mode & 0x001) { // sync mode
 110                 map_item(&mem_iortab[IOMEM32(0x1100)], psxRcntRcount0, 1);
 111                 map_item(&mem_iortab[IOMEM16(0x1100)], psxRcntRcount0, 1);
 112         }
 113         else if (mode & 0x100) { // pixel clock
 114                 map_item(&mem_iortab[IOMEM32(0x1100)], rcnt0_read_count_m1, 1);
 115                 map_item(&mem_iortab[IOMEM16(0x1100)], rcnt0_read_count_m1, 1);
 116         }
 117         else {
 118                 map_item(&mem_iortab[IOMEM32(0x1100)], rcnt0_read_count_m0, 1);
 119                 map_item(&mem_iortab[IOMEM16(0x1100)], rcnt0_read_count_m0, 1);
 120         }
 121 }
 122
 123 static void map_rcnt_rcount1(u32 mode)
 124 {
 125         if (mode & 0x001) { // sync mode
 126                 map_item(&mem_iortab[IOMEM32(0x1110)], psxRcntRcount1, 1);
 127                 map_item(&mem_iortab[IOMEM16(0x1110)], psxRcntRcount1, 1);
 128         }
 129         else if (mode & 0x100) { // hcnt
 130                 map_item(&mem_iortab[IOMEM32(0x1110)], rcnt1_read_count_m1, 1);
 131                 map_item(&mem_iortab[IOMEM16(0x1110)], rcnt1_read_count_m1, 1);
 132         }
 133         else {
 134                 map_item(&mem_iortab[IOMEM32(0x1110)], rcnt1_read_count_m0, 1);
 135                 map_item(&mem_iortab[IOMEM16(0x1110)], rcnt1_read_count_m0, 1);
 136         }
 137 }
 138
 139 static void map_rcnt_rcount2(u32 mode)
 140 {
 141         if ((mode & 7) == 1 || (mode & 7) == 7) { // sync mode
 142                 map_item(&mem_iortab[IOMEM32(0x1120)], &psxH[0x1000], 0);
 143                 map_item(&mem_iortab[IOMEM16(0x1120)], &psxH[0x1000], 0);
 144         }
 145         else if (mode & 0x200) { // clk/8
 146                 map_item(&mem_iortab[IOMEM32(0x1120)], rcnt2_read_count_m1, 1);
 147                 map_item(&mem_iortab[IOMEM16(0x1120)], rcnt2_read_count_m1, 1);
 148         }
 149         else {
 150                 map_item(&mem_iortab[IOMEM32(0x1120)], rcnt2_read_count_m0, 1);
 151                 map_item(&mem_iortab[IOMEM16(0x1120)], rcnt2_read_count_m0, 1);
 152         }
 153 }
 154
 155 #else
 156 #define map_rcnt_rcount0(mode)
 157 #define map_rcnt_rcount1(mode)
 158 #define map_rcnt_rcount2(mode)
 159 #endif
 160
 161 #define make_rcnt_funcs(i) \
 162 static u32 io_rcnt_read_mode##i()   { return psxRcntRmode(i); } \
 163 static u32 io_rcnt_read_target##i() { return psxRcntRtarget(i); } \
 164 static void io_rcnt_write_count##i(u32 val)  { psxRcntWcount(i, val & 0xffff); } \
 165 static void io_rcnt_write_mode##i(u32 val)   { psxRcntWmode(i, val); map_rcnt_rcount##i(val); } \
 166 static void io_rcnt_write_target##i(u32 val) { psxRcntWtarget(i, val & 0xffff); }
 167
 168 make_rcnt_funcs(0)
 169 make_rcnt_funcs(1)
 170 make_rcnt_funcs(2)
 171
 172 static u32 io_spu_read8_even(u32 addr)
 173 {
 174         return SPU_readRegister(addr, psxRegs.cycle) & 0xff;
 175 }
 176
 177 static u32 io_spu_read8_odd(u32 addr)
 178 {
 179         return SPU_readRegister(addr, psxRegs.cycle) >> 8;
 180 }
 181
 182 static u32 io_spu_read16(u32 addr)
 183 {
 184         return SPU_readRegister(addr, psxRegs.cycle);
 185 }
 186
 187 static u32 io_spu_read32(u32 addr)
 188 {
 189         u32 ret;
 190         ret  = SPU_readRegister(addr, psxRegs.cycle);
 191         ret |= SPU_readRegister(addr + 2, psxRegs.cycle) << 16;
 192         return ret;
 193 }
 194
 195 static void io_spu_write16(u32 value)
 196 {
 197         // meh
 198         SPU_writeRegister(address, value, psxRegs.cycle);
 199 }
 200
 201 static void io_spu_write32(u32 value)
 202 {
 203         SPUwriteRegister wfunc = SPU_writeRegister;
 204         u32 a = address;
 205
 206         wfunc(a, value & 0xffff, psxRegs.cycle);
 207         wfunc(a + 2, value >> 16, psxRegs.cycle);
 208 }
 209
 210 void new_dyna_pcsx_mem_isolate(int enable)
 211 {
 212         int i;
 213
 214         // note: apparently 0xa0000000 uncached access still works,
 215         // at least read does for sure, so assume write does too
 216         memprintf("mem isolate %d\n", enable);
 217         if (enable) {
 218                 for (i = 0; i < (0x800000 >> 12); i++) {
 219                         map_item(&mem_writetab[0x80000|i], mem_unmwtab, 1);
 220                         map_item(&mem_writetab[0x00000|i], mem_unmwtab, 1);
 221                         //map_item(&mem_writetab[0xa0000|i], mem_unmwtab, 1);
 222                 }
 223         }
 224         else {
 225                 for (i = 0; i < (0x800000 >> 12); i++) {
 226                         map_l1_mem(mem_writetab, i, 0x80000000, 0x200000, psxM);
 227                         map_l1_mem(mem_writetab, i, 0x00000000, 0x200000, psxM);
 228                         map_l1_mem(mem_writetab, i, 0xa0000000, 0x200000, psxM);
 229                 }
 230         }
 231 }
 232
 233 static u32 read_biu(u32 addr)
 234 {
 235         if (addr != 0xfffe0130)
 236                 return read_mem_dummy(addr);
 237
 238         memprintf("read_biu  %08x @%08x %u\n",
 239                 psxRegs.biuReg, psxRegs.pc, psxRegs.cycle);
 240         return psxRegs.biuReg;
 241 }
 242
 243 static void write_biu(u32 value)
 244 {
 245         if (address != 0xfffe0130) {
 246                 write_mem_dummy(value);
 247                 return;
 248         }
 249
 250         memprintf("write_biu %08x @%08x %u\n", value, psxRegs.pc, psxRegs.cycle);
 251         psxRegs.biuReg = value;
 252 }
 253
 254 /*  scph7001 (pc = 8003de60, v1 = 1f8010f0):
 255   lhu     $t9, 0($v1)
 256   li      $at, 0xFFF0FFFF
 257   and     $t0, $t9, $at
 258   lui     $at, 8
 259   or      $t1, $t0, $at
 260   sh      $t1, 0($v1)
 261 */
 262 #define make_forcew32_func(addr) \
 263 static void io_write_force32_##addr(u32 value) \
 264 { \
 265         psxHu32ref(0x##addr) = SWAPu32(value); \
 266 }
 267 make_forcew32_func(1014)
 268 make_forcew32_func(1060)
 269 make_forcew32_func(1080)
 270 make_forcew32_func(1090)
 271 make_forcew32_func(10a0)
 272 make_forcew32_func(10b0)
 273 make_forcew32_func(10c0)
 274 make_forcew32_func(10e0)
 275 make_forcew32_func(10f0)
 276
 277 void new_dyna_pcsx_mem_load_state(void)
 278 {
 279         map_rcnt_rcount0(rcnts[0].mode);
 280         map_rcnt_rcount1(rcnts[1].mode);
 281         map_rcnt_rcount2(rcnts[2].mode);
 282 }
 283
 284 int pcsxmem_is_handler_dynamic(unsigned int addr)
 285 {
 286         if ((addr & 0xfffff000) != 0x1f801000)
 287                 return 0;
 288
 289         addr &= 0xffff;
 290         return addr == 0x1100 || addr == 0x1110 || addr == 0x1120;
 291 }
 292
 293 void new_dyna_pcsx_mem_init(void)
 294 {
 295         int i;
 296
 297         memset(ffff_mem, 0xff, sizeof(ffff_mem));
 298
 299         // have to map these further to keep tcache close to .text
 300         mem_readtab = psxMap(0x08000000, 0x200000 * sizeof(mem_readtab[0]), 0, MAP_TAG_LUTS);
 301         if (mem_readtab == NULL) {
 302                 SysPrintf("failed to map mem tables\n");
 303                 exit(1);
 304         }
 305         mem_writetab = mem_readtab + 0x100000;
 306
 307         // 1st level lookup:
 308         //   0: direct mem
 309         //   1: use 2nd lookup
 310         // 2nd level lookup:
 311         //   0: direct mem variable
 312         //   1: memhandler
 313
 314         // default/unmapped memhandlers
 315         for (i = 0; i < 0x100000; i++) {
 316                 //map_item(&mem_readtab[i], mem_unmrtab, 1);
 317                 map_l1_mem(mem_readtab, i, 0, 0x1000, ffff_mem);
 318                 map_item(&mem_writetab[i], mem_unmwtab, 1);
 319         }
 320
 321         // RAM and it's mirrors
 322         for (i = 0; i < (0x800000 >> 12); i++) {
 323                 map_l1_mem(mem_readtab,  i, 0x80000000, 0x200000, psxM);
 324                 map_l1_mem(mem_readtab,  i, 0x00000000, 0x200000, psxM);
 325                 map_l1_mem(mem_readtab,  i, 0xa0000000, 0x200000, psxM);
 326         }
 327         new_dyna_pcsx_mem_isolate(0);
 328
 329         // BIOS and it's mirrors
 330         for (i = 0; i < (0x80000 >> 12); i++) {
 331                 map_l1_mem(mem_readtab, i, 0x1fc00000, 0x80000, psxR);
 332                 map_l1_mem(mem_readtab, i, 0xbfc00000, 0x80000, psxR);
 333         }
 334
 335         // scratchpad
 336         map_l1_mem(mem_readtab, 0, 0x1f800000, 0x1000, psxH);
 337         map_l1_mem(mem_readtab, 0, 0x9f800000, 0x1000, psxH);
 338         map_l1_mem(mem_writetab, 0, 0x1f800000, 0x1000, psxH);
 339         map_l1_mem(mem_writetab, 0, 0x9f800000, 0x1000, psxH);
 340
 341         // I/O
 342         map_item(&mem_readtab[0x1f801000u >> 12], mem_iortab, 1);
 343         map_item(&mem_readtab[0x9f801000u >> 12], mem_iortab, 1);
 344         map_item(&mem_readtab[0xbf801000u >> 12], mem_iortab, 1);
 345         map_item(&mem_writetab[0x1f801000u >> 12], mem_iowtab, 1);
 346         map_item(&mem_writetab[0x9f801000u >> 12], mem_iowtab, 1);
 347         map_item(&mem_writetab[0xbf801000u >> 12], mem_iowtab, 1);
 348
 349         // L2
 350         // unmapped tables
 351         for (i = 0; i < (1+2+4) * 0x1000 / 4; i++)
 352                 map_item(&mem_unmwtab[i], write_mem_dummy, 1);
 353
 354         // fill IO tables
 355         for (i = 0; i < 0x1000/4; i++) {
 356                 map_item(&mem_iortab[i], &psxH[0x1000], 0);
 357                 map_item(&mem_iowtab[i], &psxH[0x1000], 0);
 358         }
 359         for (; i < 0x1000/4 + 0x1000/2; i++) {
 360                 map_item(&mem_iortab[i], &psxH[0x1000], 0);
 361                 map_item(&mem_iowtab[i], &psxH[0x1000], 0);
 362         }
 363         for (; i < 0x1000/4 + 0x1000/2 + 0x1000; i++) {
 364                 map_item(&mem_iortab[i], &psxH[0x1000], 0);
 365                 map_item(&mem_iowtab[i], &psxH[0x1000], 0);
 366         }
 367
 368         map_item(&mem_iortab[IOMEM32(0x1040)], io_read_sio32, 1);
 369         map_item(&mem_iortab[IOMEM32(0x1044)], sioReadStat16, 1);
 370         map_item(&mem_iortab[IOMEM32(0x1100)], psxRcntRcount0, 1);
 371         map_item(&mem_iortab[IOMEM32(0x1104)], io_rcnt_read_mode0, 1);
 372         map_item(&mem_iortab[IOMEM32(0x1108)], io_rcnt_read_target0, 1);
 373         map_item(&mem_iortab[IOMEM32(0x1110)], psxRcntRcount1, 1);
 374         map_item(&mem_iortab[IOMEM32(0x1114)], io_rcnt_read_mode1, 1);
 375         map_item(&mem_iortab[IOMEM32(0x1118)], io_rcnt_read_target1, 1);
 376         map_item(&mem_iortab[IOMEM32(0x1120)], psxRcntRcount2, 1);
 377         map_item(&mem_iortab[IOMEM32(0x1124)], io_rcnt_read_mode2, 1);
 378         map_item(&mem_iortab[IOMEM32(0x1128)], io_rcnt_read_target2, 1);
 379 //      map_item(&mem_iortab[IOMEM32(0x1810)], GPU_readData, 1);
 380         map_item(&mem_iortab[IOMEM32(0x1814)], psxHwReadGpuSR, 1);
 381         map_item(&mem_iortab[IOMEM32(0x1820)], mdecRead0, 1);
 382         map_item(&mem_iortab[IOMEM32(0x1824)], mdecRead1, 1);
 383
 384         map_item(&mem_iortab[IOMEM16(0x1040)], io_read_sio16, 1);
 385         map_item(&mem_iortab[IOMEM16(0x1044)], sioReadStat16, 1);
 386         map_item(&mem_iortab[IOMEM16(0x1048)], sioReadMode16, 1);
 387         map_item(&mem_iortab[IOMEM16(0x104a)], sioReadCtrl16, 1);
 388         map_item(&mem_iortab[IOMEM16(0x104e)], sioReadBaud16, 1);
 389         map_item(&mem_iortab[IOMEM16(0x1054)], io_read_sio2_status, 1);
 390         map_item(&mem_iortab[IOMEM16(0x1100)], psxRcntRcount0, 1);
 391         map_item(&mem_iortab[IOMEM16(0x1104)], io_rcnt_read_mode0, 1);
 392         map_item(&mem_iortab[IOMEM16(0x1108)], io_rcnt_read_target0, 1);
 393         map_item(&mem_iortab[IOMEM16(0x1110)], psxRcntRcount1, 1);
 394         map_item(&mem_iortab[IOMEM16(0x1114)], io_rcnt_read_mode1, 1);
 395         map_item(&mem_iortab[IOMEM16(0x1118)], io_rcnt_read_target1, 1);
 396         map_item(&mem_iortab[IOMEM16(0x1120)], psxRcntRcount2, 1);
 397         map_item(&mem_iortab[IOMEM16(0x1124)], io_rcnt_read_mode2, 1);
 398         map_item(&mem_iortab[IOMEM16(0x1128)], io_rcnt_read_target2, 1);
 399
 400         map_item(&mem_iortab[IOMEM8(0x1040)], sioRead8, 1);
 401         map_item(&mem_iortab[IOMEM8(0x1800)], cdrRead0, 1);
 402         map_item(&mem_iortab[IOMEM8(0x1801)], cdrRead1, 1);
 403         map_item(&mem_iortab[IOMEM8(0x1802)], cdrRead2, 1);
 404         map_item(&mem_iortab[IOMEM8(0x1803)], cdrRead3, 1);
 405
 406         for (i = 0x1c00; i < 0x2000; i += 2) {
 407                 map_item(&mem_iortab[IOMEM8(i)], io_spu_read8_even, 1);
 408                 map_item(&mem_iortab[IOMEM8(i+1)], io_spu_read8_odd, 1);
 409                 map_item(&mem_iortab[IOMEM16(i)], io_spu_read16, 1);
 410                 map_item(&mem_iortab[IOMEM32(i)], io_spu_read32, 1);
 411         }
 412
 413         // write(u32 data)
 414         map_item(&mem_iowtab[IOMEM32(0x1040)], io_write_sio32, 1);
 415         map_item(&mem_iowtab[IOMEM32(0x1070)], psxHwWriteIstat, 1);
 416         map_item(&mem_iowtab[IOMEM32(0x1074)], psxHwWriteImask, 1);
 417         map_item(&mem_iowtab[IOMEM32(0x1088)], psxHwWriteChcr0, 1);
 418         map_item(&mem_iowtab[IOMEM32(0x108c)], psxHwWriteChcr0, 1);
 419         map_item(&mem_iowtab[IOMEM32(0x1098)], psxHwWriteChcr1, 1);
 420         map_item(&mem_iowtab[IOMEM32(0x109c)], psxHwWriteChcr1, 1);
 421         map_item(&mem_iowtab[IOMEM32(0x10a8)], psxHwWriteChcr2, 1);
 422         map_item(&mem_iowtab[IOMEM32(0x10ac)], psxHwWriteChcr2, 1);
 423         map_item(&mem_iowtab[IOMEM32(0x10b8)], psxHwWriteChcr3, 1);
 424         map_item(&mem_iowtab[IOMEM32(0x10bc)], psxHwWriteChcr3, 1);
 425         map_item(&mem_iowtab[IOMEM32(0x10c8)], psxHwWriteChcr4, 1);
 426         map_item(&mem_iowtab[IOMEM32(0x10cc)], psxHwWriteChcr4, 1);
 427         map_item(&mem_iowtab[IOMEM32(0x10e8)], psxHwWriteChcr6, 1);
 428         map_item(&mem_iowtab[IOMEM32(0x10ec)], psxHwWriteChcr6, 1);
 429         map_item(&mem_iowtab[IOMEM32(0x10f4)], psxHwWriteDmaIcr32, 1);
 430         map_item(&mem_iowtab[IOMEM32(0x1100)], io_rcnt_write_count0, 1);
 431         map_item(&mem_iowtab[IOMEM32(0x1104)], io_rcnt_write_mode0, 1);
 432         map_item(&mem_iowtab[IOMEM32(0x1108)], io_rcnt_write_target0, 1);
 433         map_item(&mem_iowtab[IOMEM32(0x1110)], io_rcnt_write_count1, 1);
 434         map_item(&mem_iowtab[IOMEM32(0x1114)], io_rcnt_write_mode1, 1);
 435         map_item(&mem_iowtab[IOMEM32(0x1118)], io_rcnt_write_target1, 1);
 436         map_item(&mem_iowtab[IOMEM32(0x1120)], io_rcnt_write_count2, 1);
 437         map_item(&mem_iowtab[IOMEM32(0x1124)], io_rcnt_write_mode2, 1);
 438         map_item(&mem_iowtab[IOMEM32(0x1128)], io_rcnt_write_target2, 1);
 439 //      map_item(&mem_iowtab[IOMEM32(0x1810)], GPU_writeData, 1);
 440         map_item(&mem_iowtab[IOMEM32(0x1814)], psxHwWriteGpuSR, 1);
 441         map_item(&mem_iowtab[IOMEM32(0x1820)], mdecWrite0, 1);
 442         map_item(&mem_iowtab[IOMEM32(0x1824)], mdecWrite1, 1);
 443
 444         map_item(&mem_iowtab[IOMEM16(0x1014)], io_write_force32_1014, 1);
 445         map_item(&mem_iowtab[IOMEM16(0x1040)], io_write_sio16, 1);
 446         map_item(&mem_iowtab[IOMEM16(0x1044)], sioWriteStat16, 1);
 447         map_item(&mem_iowtab[IOMEM16(0x1048)], sioWriteMode16, 1);
 448         map_item(&mem_iowtab[IOMEM16(0x104a)], sioWriteCtrl16, 1);
 449         map_item(&mem_iowtab[IOMEM16(0x104e)], sioWriteBaud16, 1);
 450         map_item(&mem_iowtab[IOMEM16(0x1060)], io_write_force32_1060, 1);
 451         map_item(&mem_iowtab[IOMEM16(0x1070)], psxHwWriteIstat, 1);
 452         map_item(&mem_iowtab[IOMEM16(0x1074)], psxHwWriteImask, 1);
 453         map_item(&mem_iowtab[IOMEM16(0x1080)], io_write_force32_1080, 1);
 454         map_item(&mem_iowtab[IOMEM16(0x1088)], psxHwWriteChcr0, 1);
 455         map_item(&mem_iowtab[IOMEM16(0x108c)], psxHwWriteChcr0, 1);
 456         map_item(&mem_iowtab[IOMEM16(0x1090)], io_write_force32_1090, 1);
 457         map_item(&mem_iowtab[IOMEM16(0x1098)], psxHwWriteChcr1, 1);
 458         map_item(&mem_iowtab[IOMEM16(0x109c)], psxHwWriteChcr1, 1);
 459         map_item(&mem_iowtab[IOMEM16(0x10a0)], io_write_force32_10a0, 1);
 460         map_item(&mem_iowtab[IOMEM16(0x10a8)], psxHwWriteChcr2, 1);
 461         map_item(&mem_iowtab[IOMEM16(0x10ac)], psxHwWriteChcr2, 1);
 462         map_item(&mem_iowtab[IOMEM16(0x10b0)], io_write_force32_10b0, 1);
 463         map_item(&mem_iowtab[IOMEM16(0x10b8)], psxHwWriteChcr3, 1);
 464         map_item(&mem_iowtab[IOMEM16(0x10bc)], psxHwWriteChcr3, 1);
 465         map_item(&mem_iowtab[IOMEM16(0x10c0)], io_write_force32_10c0, 1);
 466         map_item(&mem_iowtab[IOMEM16(0x10c8)], psxHwWriteChcr4, 1);
 467         map_item(&mem_iowtab[IOMEM16(0x10cc)], psxHwWriteChcr4, 1);
 468         map_item(&mem_iowtab[IOMEM16(0x10e0)], io_write_force32_10e0, 1);
 469         map_item(&mem_iowtab[IOMEM16(0x10e8)], psxHwWriteChcr6, 1);
 470         map_item(&mem_iowtab[IOMEM16(0x10ec)], psxHwWriteChcr6, 1);
 471         map_item(&mem_iowtab[IOMEM16(0x10f0)], io_write_force32_10f0, 1);
 472         map_item(&mem_iowtab[IOMEM16(0x10f4)], psxHwWriteDmaIcr32, 1);
 473         map_item(&mem_iowtab[IOMEM16(0x1100)], io_rcnt_write_count0, 1);
 474         map_item(&mem_iowtab[IOMEM16(0x1104)], io_rcnt_write_mode0, 1);
 475         map_item(&mem_iowtab[IOMEM16(0x1108)], io_rcnt_write_target0, 1);
 476         map_item(&mem_iowtab[IOMEM16(0x1110)], io_rcnt_write_count1, 1);
 477         map_item(&mem_iowtab[IOMEM16(0x1114)], io_rcnt_write_mode1, 1);
 478         map_item(&mem_iowtab[IOMEM16(0x1118)], io_rcnt_write_target1, 1);
 479         map_item(&mem_iowtab[IOMEM16(0x1120)], io_rcnt_write_count2, 1);
 480         map_item(&mem_iowtab[IOMEM16(0x1124)], io_rcnt_write_mode2, 1);
 481         map_item(&mem_iowtab[IOMEM16(0x1128)], io_rcnt_write_target2, 1);
 482
 483         map_item(&mem_iowtab[IOMEM8(0x1040)], sioWrite8, 1);
 484         map_item(&mem_iowtab[IOMEM8(0x1800)], cdrWrite0, 1);
 485         map_item(&mem_iowtab[IOMEM8(0x1801)], cdrWrite1, 1);
 486         map_item(&mem_iowtab[IOMEM8(0x1802)], cdrWrite2, 1);
 487         map_item(&mem_iowtab[IOMEM8(0x1803)], cdrWrite3, 1);
 488
 489         for (i = 0x1c00; i < 0x2000; i += 2) {
 490                 map_item(&mem_iowtab[IOMEM16(i)], io_spu_write16, 1);
 491                 map_item(&mem_iowtab[IOMEM32(i)], io_spu_write32, 1);
 492         }
 493
 494         // misc
 495         map_item(&mem_readtab[0xfffe0130u >> 12], mem_ffrtab, 1);
 496         map_item(&mem_writetab[0xfffe0130u >> 12], mem_ffwtab, 1);
 497         for (i = 0; i < 0x1000/4 + 0x1000/2 + 0x1000; i++) {
 498                 map_item(&mem_ffrtab[i], read_biu, 1);
 499                 map_item(&mem_ffwtab[i], write_biu, 1);
 500         }
 501
 502         mem_rtab = mem_readtab;
 503         mem_wtab = mem_writetab;
 504
 505         new_dyna_pcsx_mem_load_state();
 506 }
 507
 508 void new_dyna_pcsx_mem_reset(void)
 509 {
 510         // plugins might change so update the pointers
 511         map_item(&mem_iortab[IOMEM32(0x1810)], GPU_readData, 1);
 512         map_item(&mem_iowtab[IOMEM32(0x1810)], GPU_writeData, 1);
 513         if (Config.hacks.gpu_busy)
 514                 map_item(&mem_iortab[IOMEM32(0x1814)], psxHwReadGpuSRbusyHack, 1);
 515         else
 516                 map_item(&mem_iortab[IOMEM32(0x1814)], psxHwReadGpuSR, 1);
 517 }
 518
 519 void new_dyna_pcsx_mem_shutdown(void)
 520 {
 521         psxUnmap(mem_readtab, 0x200000 * sizeof(mem_readtab[0]), MAP_TAG_LUTS);
 522         mem_writetab = mem_readtab = NULL;
 523 }