libpcsxcore/r3000a.c

   1 /***************************************************************************
   2  *   Copyright (C) 2007 Ryan Schultz, PCSX-df Team, PCSX team              *
   3  *                                                                         *
   4  *   This program is free software; you can redistribute it and/or modify  *
   5  *   it under the terms of the GNU General Public License as published by  *
   6  *   the Free Software Foundation; either version 2 of the License, or     *
   7  *   (at your option) any later version.                                   *
   8  *                                                                         *
   9  *   This program is distributed in the hope that it will be useful,       *
  10  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  11  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  12  *   GNU General Public License for more details.                          *
  13  *                                                                         *
  14  *   You should have received a copy of the GNU General Public License     *
  15  *   along with this program; if not, write to the                         *
  16  *   Free Software Foundation, Inc.,                                       *
  17  *   51 Franklin Street, Fifth Floor, Boston, MA 02111-1307 USA.           *
  18  ***************************************************************************/
  19
  20 /*
  21 * R3000A CPU functions.
  22 */
  23
  24 #include "r3000a.h"
  25 #include "cdrom.h"
  26 #include "mdec.h"
  27 #include "gte.h"
  28 #include "psxinterpreter.h"
  29 #include "../include/compiler_features.h"
  30
  31 R3000Acpu *psxCpu = NULL;
  32 #ifdef DRC_DISABLE
  33 psxRegisters psxRegs;
  34 #endif
  35
  36 int psxInit() {
  37         SysPrintf(_("Running PCSX Version %s (%s).\n"), PCSX_VERSION, __DATE__);
  38
  39 #ifndef DRC_DISABLE
  40         if (Config.Cpu == CPU_INTERPRETER) {
  41                 psxCpu = &psxInt;
  42         } else psxCpu = &psxRec;
  43 #else
  44         Config.Cpu = CPU_INTERPRETER;
  45         psxCpu = &psxInt;
  46 #endif
  47
  48         Log = 0;
  49
  50         if (psxMemInit() == -1) return -1;
  51
  52         return psxCpu->Init();
  53 }
  54
  55 void psxReset() {
  56         boolean introBypassed = FALSE;
  57         psxMemReset();
  58
  59         memset(&psxRegs, 0, sizeof(psxRegs));
  60
  61         psxRegs.pc = 0xbfc00000; // Start in bootstrap
  62
  63         psxRegs.CP0.n.SR   = 0x10600000; // COP0 enabled | BEV = 1 | TS = 1
  64         psxRegs.CP0.n.PRid = 0x00000002; // PRevID = Revision ID, same as R3000A
  65         if (Config.HLE) {
  66                 psxRegs.CP0.n.SR |= 1u << 30;    // COP2 enabled
  67                 psxRegs.CP0.n.SR &= ~(1u << 22); // RAM exception vector
  68         }
  69
  70         psxCpu->ApplyConfig();
  71         psxCpu->Reset();
  72
  73         psxHwReset();
  74         psxBiosInit();
  75
  76         if (!Config.HLE) {
  77                 psxExecuteBios();
  78                 if (psxRegs.pc == 0x80030000 && !Config.SlowBoot) {
  79                         BiosBootBypass();
  80                         introBypassed = TRUE;
  81                 }
  82         }
  83         if (Config.HLE || introBypassed)
  84                 psxBiosSetupBootState();
  85
  86 #ifdef EMU_LOG
  87         EMU_LOG("*BIOS END*\n");
  88 #endif
  89         Log = 0;
  90 }
  91
  92 void psxShutdown() {
  93         psxBiosShutdown();
  94
  95         psxCpu->Shutdown();
  96
  97         psxMemShutdown();
  98 }
  99
 100 // cp0 is passed separately for lightrec to be less messy
 101 void psxException(u32 cause, enum R3000Abdt bdt, psxCP0Regs *cp0) {
 102         u32 opcode = intFakeFetch(psxRegs.pc);
 103
 104         if (unlikely(!Config.HLE && (opcode >> 25) == 0x25)) {
 105                 // "hokuto no ken" / "Crash Bandicot 2" ...
 106                 // BIOS does not allow to return to GTE instructions
 107                 // (just skips it, supposedly because it's scheduled already)
 108                 // so we execute it here
 109                 psxCP2Regs *cp2 = (psxCP2Regs *)(cp0 + 1);
 110                 psxRegs.code = opcode;
 111                 psxCP2[opcode & 0x3f](cp2);
 112         }
 113
 114         // Set the Cause
 115         cp0->n.Cause = (bdt << 30) | (cp0->n.Cause & 0x700) | cause;
 116
 117         // Set the EPC & PC
 118         cp0->n.EPC = bdt ? psxRegs.pc - 4 : psxRegs.pc;
 119
 120         if (cp0->n.SR & 0x400000)
 121                 psxRegs.pc = 0xbfc00180;
 122         else
 123                 psxRegs.pc = 0x80000080;
 124
 125         // Set the SR
 126         cp0->n.SR = (cp0->n.SR & ~0x3f) | ((cp0->n.SR & 0x0f) << 2);
 127 }
 128
 129 void psxBranchTest() {
 130         if ((psxRegs.cycle - psxNextsCounter) >= psxNextCounter)
 131                 psxRcntUpdate();
 132
 133         if (psxRegs.interrupt) {
 134                 if ((psxRegs.interrupt & (1 << PSXINT_SIO))) { // sio
 135                         if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_SIO].sCycle) >= psxRegs.intCycle[PSXINT_SIO].cycle) {
 136                                 psxRegs.interrupt &= ~(1 << PSXINT_SIO);
 137                                 sioInterrupt();
 138                         }
 139                 }
 140                 if (psxRegs.interrupt & (1 << PSXINT_CDR)) { // cdr
 141                         if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_CDR].sCycle) >= psxRegs.intCycle[PSXINT_CDR].cycle) {
 142                                 psxRegs.interrupt &= ~(1 << PSXINT_CDR);
 143                                 cdrInterrupt();
 144                         }
 145                 }
 146                 if (psxRegs.interrupt & (1 << PSXINT_CDREAD)) { // cdr read
 147                         if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_CDREAD].sCycle) >= psxRegs.intCycle[PSXINT_CDREAD].cycle) {
 148                                 psxRegs.interrupt &= ~(1 << PSXINT_CDREAD);
 149                                 cdrPlayReadInterrupt();
 150                         }
 151                 }
 152                 if (psxRegs.interrupt & (1 << PSXINT_GPUDMA)) { // gpu dma
 153                         if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_GPUDMA].sCycle) >= psxRegs.intCycle[PSXINT_GPUDMA].cycle) {
 154                                 psxRegs.interrupt &= ~(1 << PSXINT_GPUDMA);
 155                                 gpuInterrupt();
 156                         }
 157                 }
 158                 if (psxRegs.interrupt & (1 << PSXINT_MDECOUTDMA)) { // mdec out dma
 159                         if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_MDECOUTDMA].sCycle) >= psxRegs.intCycle[PSXINT_MDECOUTDMA].cycle) {
 160                                 psxRegs.interrupt &= ~(1 << PSXINT_MDECOUTDMA);
 161                                 mdec1Interrupt();
 162                         }
 163                 }
 164                 if (psxRegs.interrupt & (1 << PSXINT_SPUDMA)) { // spu dma
 165                         if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_SPUDMA].sCycle) >= psxRegs.intCycle[PSXINT_SPUDMA].cycle) {
 166                                 psxRegs.interrupt &= ~(1 << PSXINT_SPUDMA);
 167                                 spuInterrupt();
 168                         }
 169                 }
 170                 if (psxRegs.interrupt & (1 << PSXINT_MDECINDMA)) { // mdec in
 171                         if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_MDECINDMA].sCycle) >= psxRegs.intCycle[PSXINT_MDECINDMA].cycle) {
 172                                 psxRegs.interrupt &= ~(1 << PSXINT_MDECINDMA);
 173                                 mdec0Interrupt();
 174                         }
 175                 }
 176                 if (psxRegs.interrupt & (1 << PSXINT_GPUOTCDMA)) { // gpu otc
 177                         if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_GPUOTCDMA].sCycle) >= psxRegs.intCycle[PSXINT_GPUOTCDMA].cycle) {
 178                                 psxRegs.interrupt &= ~(1 << PSXINT_GPUOTCDMA);
 179                                 gpuotcInterrupt();
 180                         }
 181                 }
 182                 if (psxRegs.interrupt & (1 << PSXINT_CDRDMA)) { // cdrom
 183                         if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_CDRDMA].sCycle) >= psxRegs.intCycle[PSXINT_CDRDMA].cycle) {
 184                                 psxRegs.interrupt &= ~(1 << PSXINT_CDRDMA);
 185                                 cdrDmaInterrupt();
 186                         }
 187                 }
 188                 if (psxRegs.interrupt & (1 << PSXINT_CDRLID)) { // cdr lid states
 189                         if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_CDRLID].sCycle) >= psxRegs.intCycle[PSXINT_CDRLID].cycle) {
 190                                 psxRegs.interrupt &= ~(1 << PSXINT_CDRLID);
 191                                 cdrLidSeekInterrupt();
 192                         }
 193                 }
 194                 if (psxRegs.interrupt & (1 << PSXINT_IRQ10)) { // irq10 - controller port pin8
 195                         if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_IRQ10].sCycle) >= psxRegs.intCycle[PSXINT_IRQ10].cycle) {
 196                                 psxRegs.interrupt &= ~(1 << PSXINT_IRQ10);
 197                                 irq10Interrupt();
 198                         }
 199                 }
 200                 if (psxRegs.interrupt & (1 << PSXINT_SPU_UPDATE)) { // scheduled spu update
 201                         if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_SPU_UPDATE].sCycle) >= psxRegs.intCycle[PSXINT_SPU_UPDATE].cycle) {
 202                                 psxRegs.interrupt &= ~(1 << PSXINT_SPU_UPDATE);
 203                                 spuUpdate();
 204                         }
 205                 }
 206         }
 207
 208         psxRegs.CP0.n.Cause &= ~0x400;
 209         if (psxHu32(0x1070) & psxHu32(0x1074))
 210                 psxRegs.CP0.n.Cause |= 0x400;
 211         if (((psxRegs.CP0.n.Cause | 1) & psxRegs.CP0.n.SR & 0x401) == 0x401)
 212                 psxException(0, 0, &psxRegs.CP0);
 213 }
 214
 215 void psxJumpTest() {
 216         if (!Config.HLE && Config.PsxOut) {
 217                 u32 call = psxRegs.GPR.n.t1 & 0xff;
 218                 switch (psxRegs.pc & 0x1fffff) {
 219                         case 0xa0:
 220 #ifdef PSXBIOS_LOG
 221                                 if (call != 0x28 && call != 0xe) {
 222                                         PSXBIOS_LOG("Bios call a0: %s (%x) %x,%x,%x,%x\n", biosA0n[call], call, psxRegs.GPR.n.a0, psxRegs.GPR.n.a1, psxRegs.GPR.n.a2, psxRegs.GPR.n.a3); }
 223 #endif
 224                                 if (biosA0[call])
 225                                         biosA0[call]();
 226                                 break;
 227                         case 0xb0:
 228 #ifdef PSXBIOS_LOG
 229                                 if (call != 0x17 && call != 0xb) {
 230                                         PSXBIOS_LOG("Bios call b0: %s (%x) %x,%x,%x,%x\n", biosB0n[call], call, psxRegs.GPR.n.a0, psxRegs.GPR.n.a1, psxRegs.GPR.n.a2, psxRegs.GPR.n.a3); }
 231 #endif
 232                                 if (biosB0[call])
 233                                         biosB0[call]();
 234                                 break;
 235                         case 0xc0:
 236 #ifdef PSXBIOS_LOG
 237                                 PSXBIOS_LOG("Bios call c0: %s (%x) %x,%x,%x,%x\n", biosC0n[call], call, psxRegs.GPR.n.a0, psxRegs.GPR.n.a1, psxRegs.GPR.n.a2, psxRegs.GPR.n.a3);
 238 #endif
 239                                 if (biosC0[call])
 240                                         biosC0[call]();
 241                                 break;
 242                 }
 243         }
 244 }
 245
 246 void psxExecuteBios() {
 247         int i;
 248         for (i = 0; i < 5000000; i++) {
 249                 psxCpu->ExecuteBlock(EXEC_CALLER_BOOT);
 250                 if ((psxRegs.pc & 0xff800000) == 0x80000000)
 251                         break;
 252         }
 253         if (psxRegs.pc != 0x80030000)
 254                 SysPrintf("non-standard BIOS detected (%d, %08x)\n", i, psxRegs.pc);
 255 }
 256
 257 // irq10 stuff, very preliminary
 258 static int irq10count;
 259
 260 static void psxScheduleIrq10One(u32 cycles_abs) {
 261         // schedule relative to frame start
 262         u32 c = cycles_abs - rcnts[3].cycleStart;
 263         assert((s32)c >= 0);
 264         psxRegs.interrupt |= 1 << PSXINT_IRQ10;
 265         psxRegs.intCycle[PSXINT_IRQ10].cycle = c;
 266         psxRegs.intCycle[PSXINT_IRQ10].sCycle = rcnts[3].cycleStart;
 267         new_dyna_set_event_abs(PSXINT_IRQ10, cycles_abs);
 268 }
 269
 270 void irq10Interrupt() {
 271         u32 prevc = psxRegs.intCycle[PSXINT_IRQ10].sCycle
 272                 + psxRegs.intCycle[PSXINT_IRQ10].cycle;
 273
 274         psxHu32ref(0x1070) |= SWAPu32(0x400);
 275
 276 #if 0
 277         s32 framec = psxRegs.cycle - rcnts[3].cycleStart;
 278         printf("%d:%03d irq10 #%d %3d m=%d,%d\n", frame_counter,
 279                 (s32)((float)framec / (PSXCLK / 60 / 263.0f)),
 280                 irq10count, psxRegs.cycle - prevc,
 281                 (psxRegs.CP0.n.SR & 0x401) != 0x401, !(psxHu32(0x1074) & 0x400));
 282 #endif
 283         if (--irq10count > 0)
 284                 psxScheduleIrq10One(prevc + PSXCLK / 60 / 263);
 285 }
 286
 287 void psxScheduleIrq10(int irq_count, int x_cycles, int y) {
 288         //printf("%s %d, %d, %d\n", __func__, irq_count, x_cycles, y);
 289         u32 cycles_per_frame = Config.PsxType ? PSXCLK / 50 : PSXCLK / 60;
 290         u32 cycles = rcnts[3].cycleStart + cycles_per_frame;
 291         cycles += y * cycles_per_frame / (Config.PsxType ? 314 : 263);
 292         cycles += x_cycles;
 293         psxScheduleIrq10One(cycles);
 294         irq10count = irq_count;
 295 }