libpcsxcore/r3000a.c

   1 /***************************************************************************
   2  *   Copyright (C) 2007 Ryan Schultz, PCSX-df Team, PCSX team              *
   3  *                                                                         *
   4  *   This program is free software; you can redistribute it and/or modify  *
   5  *   it under the terms of the GNU General Public License as published by  *
   6  *   the Free Software Foundation; either version 2 of the License, or     *
   7  *   (at your option) any later version.                                   *
   8  *                                                                         *
   9  *   This program is distributed in the hope that it will be useful,       *
  10  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  11  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  12  *   GNU General Public License for more details.                          *
  13  *                                                                         *
  14  *   You should have received a copy of the GNU General Public License     *
  15  *   along with this program; if not, write to the                         *
  16  *   Free Software Foundation, Inc.,                                       *
  17  *   51 Franklin Street, Fifth Floor, Boston, MA 02111-1307 USA.           *
  18  ***************************************************************************/
  19
  20 /*
  21 * R3000A CPU functions.
  22 */
  23
  24 #include "r3000a.h"
  25 #include "cdrom.h"
  26 #include "mdec.h"
  27 #include "gte.h"
  28 #include "psxinterpreter.h"
  29 #include "../include/compiler_features.h"
  30
  31 R3000Acpu *psxCpu = NULL;
  32 #ifdef DRC_DISABLE
  33 psxRegisters psxRegs;
  34 #endif
  35
  36 int psxInit() {
  37         SysPrintf(_("Running PCSX Version %s (%s).\n"), PCSX_VERSION, __DATE__);
  38
  39 #ifndef DRC_DISABLE
  40         if (Config.Cpu == CPU_INTERPRETER) {
  41                 psxCpu = &psxInt;
  42         } else psxCpu = &psxRec;
  43 #else
  44         Config.Cpu = CPU_INTERPRETER;
  45         psxCpu = &psxInt;
  46 #endif
  47
  48         Log = 0;
  49
  50         if (psxMemInit() == -1) return -1;
  51
  52         return psxCpu->Init();
  53 }
  54
  55 void psxReset() {
  56         psxMemReset();
  57
  58         memset(&psxRegs, 0, sizeof(psxRegs));
  59
  60         psxRegs.pc = 0xbfc00000; // Start in bootstrap
  61
  62         psxRegs.CP0.n.SR   = 0x10600000; // COP0 enabled | BEV = 1 | TS = 1
  63         psxRegs.CP0.n.PRid = 0x00000002; // PRevID = Revision ID, same as R3000A
  64         if (Config.HLE)
  65                 psxRegs.CP0.n.SR |= 1u << 30; // COP2 enabled
  66
  67         psxCpu->ApplyConfig();
  68         psxCpu->Reset();
  69
  70         psxHwReset();
  71         psxBiosInit();
  72
  73         BiosLikeGPUSetup(); // a bit of a hack but whatever
  74
  75         if (!Config.HLE) {
  76                 psxExecuteBios();
  77                 if (psxRegs.pc == 0x80030000 && !Config.SlowBoot)
  78                         BiosBootBypass();
  79         }
  80
  81 #ifdef EMU_LOG
  82         EMU_LOG("*BIOS END*\n");
  83 #endif
  84         Log = 0;
  85 }
  86
  87 void psxShutdown() {
  88         psxBiosShutdown();
  89
  90         psxCpu->Shutdown();
  91
  92         psxMemShutdown();
  93 }
  94
  95 // cp0 is passed separately for lightrec to be less messy
  96 void psxException(u32 cause, enum R3000Abdt bdt, psxCP0Regs *cp0) {
  97         u32 opcode = intFakeFetch(psxRegs.pc);
  98
  99         if (unlikely(!Config.HLE && (opcode >> 25) == 0x25)) {
 100                 // "hokuto no ken" / "Crash Bandicot 2" ...
 101                 // BIOS does not allow to return to GTE instructions
 102                 // (just skips it, supposedly because it's scheduled already)
 103                 // so we execute it here
 104                 psxCP2Regs *cp2 = (psxCP2Regs *)(cp0 + 1);
 105                 psxRegs.code = opcode;
 106                 psxCP2[opcode & 0x3f](cp2);
 107         }
 108
 109         // Set the Cause
 110         cp0->n.Cause = (bdt << 30) | (cp0->n.Cause & 0x300) | cause;
 111
 112         // Set the EPC & PC
 113         cp0->n.EPC = bdt ? psxRegs.pc - 4 : psxRegs.pc;
 114
 115         if (cp0->n.SR & 0x400000)
 116                 psxRegs.pc = 0xbfc00180;
 117         else
 118                 psxRegs.pc = 0x80000080;
 119
 120         // Set the SR
 121         cp0->n.SR = (cp0->n.SR & ~0x3f) | ((cp0->n.SR & 0x0f) << 2);
 122 }
 123
 124 void psxBranchTest() {
 125         if ((psxRegs.cycle - psxNextsCounter) >= psxNextCounter)
 126                 psxRcntUpdate();
 127
 128         if (psxRegs.interrupt) {
 129                 if ((psxRegs.interrupt & (1 << PSXINT_SIO))) { // sio
 130                         if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_SIO].sCycle) >= psxRegs.intCycle[PSXINT_SIO].cycle) {
 131                                 psxRegs.interrupt &= ~(1 << PSXINT_SIO);
 132                                 sioInterrupt();
 133                         }
 134                 }
 135                 if (psxRegs.interrupt & (1 << PSXINT_CDR)) { // cdr
 136                         if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_CDR].sCycle) >= psxRegs.intCycle[PSXINT_CDR].cycle) {
 137                                 psxRegs.interrupt &= ~(1 << PSXINT_CDR);
 138                                 cdrInterrupt();
 139                         }
 140                 }
 141                 if (psxRegs.interrupt & (1 << PSXINT_CDREAD)) { // cdr read
 142                         if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_CDREAD].sCycle) >= psxRegs.intCycle[PSXINT_CDREAD].cycle) {
 143                                 psxRegs.interrupt &= ~(1 << PSXINT_CDREAD);
 144                                 cdrPlayReadInterrupt();
 145                         }
 146                 }
 147                 if (psxRegs.interrupt & (1 << PSXINT_GPUDMA)) { // gpu dma
 148                         if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_GPUDMA].sCycle) >= psxRegs.intCycle[PSXINT_GPUDMA].cycle) {
 149                                 psxRegs.interrupt &= ~(1 << PSXINT_GPUDMA);
 150                                 gpuInterrupt();
 151                         }
 152                 }
 153                 if (psxRegs.interrupt & (1 << PSXINT_MDECOUTDMA)) { // mdec out dma
 154                         if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_MDECOUTDMA].sCycle) >= psxRegs.intCycle[PSXINT_MDECOUTDMA].cycle) {
 155                                 psxRegs.interrupt &= ~(1 << PSXINT_MDECOUTDMA);
 156                                 mdec1Interrupt();
 157                         }
 158                 }
 159                 if (psxRegs.interrupt & (1 << PSXINT_SPUDMA)) { // spu dma
 160                         if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_SPUDMA].sCycle) >= psxRegs.intCycle[PSXINT_SPUDMA].cycle) {
 161                                 psxRegs.interrupt &= ~(1 << PSXINT_SPUDMA);
 162                                 spuInterrupt();
 163                         }
 164                 }
 165                 if (psxRegs.interrupt & (1 << PSXINT_MDECINDMA)) { // mdec in
 166                         if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_MDECINDMA].sCycle) >= psxRegs.intCycle[PSXINT_MDECINDMA].cycle) {
 167                                 psxRegs.interrupt &= ~(1 << PSXINT_MDECINDMA);
 168                                 mdec0Interrupt();
 169                         }
 170                 }
 171                 if (psxRegs.interrupt & (1 << PSXINT_GPUOTCDMA)) { // gpu otc
 172                         if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_GPUOTCDMA].sCycle) >= psxRegs.intCycle[PSXINT_GPUOTCDMA].cycle) {
 173                                 psxRegs.interrupt &= ~(1 << PSXINT_GPUOTCDMA);
 174                                 gpuotcInterrupt();
 175                         }
 176                 }
 177                 if (psxRegs.interrupt & (1 << PSXINT_CDRDMA)) { // cdrom
 178                         if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_CDRDMA].sCycle) >= psxRegs.intCycle[PSXINT_CDRDMA].cycle) {
 179                                 psxRegs.interrupt &= ~(1 << PSXINT_CDRDMA);
 180                                 cdrDmaInterrupt();
 181                         }
 182                 }
 183                 if (psxRegs.interrupt & (1 << PSXINT_CDRLID)) { // cdr lid states
 184                         if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_CDRLID].sCycle) >= psxRegs.intCycle[PSXINT_CDRLID].cycle) {
 185                                 psxRegs.interrupt &= ~(1 << PSXINT_CDRLID);
 186                                 cdrLidSeekInterrupt();
 187                         }
 188                 }
 189                 if (psxRegs.interrupt & (1 << PSXINT_SPU_UPDATE)) { // scheduled spu update
 190                         if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_SPU_UPDATE].sCycle) >= psxRegs.intCycle[PSXINT_SPU_UPDATE].cycle) {
 191                                 psxRegs.interrupt &= ~(1 << PSXINT_SPU_UPDATE);
 192                                 spuUpdate();
 193                         }
 194                 }
 195         }
 196
 197         if (psxHu32(0x1070) & psxHu32(0x1074)) {
 198                 if ((psxRegs.CP0.n.SR & 0x401) == 0x401) {
 199 #ifdef PSXCPU_LOG
 200                         PSXCPU_LOG("Interrupt: %x %x\n", psxHu32(0x1070), psxHu32(0x1074));
 201 #endif
 202 //                      SysPrintf("Interrupt (%x): %x %x\n", psxRegs.cycle, psxHu32(0x1070), psxHu32(0x1074));
 203                         psxException(0x400, 0, &psxRegs.CP0);
 204                 }
 205         }
 206 }
 207
 208 void psxJumpTest() {
 209         if (!Config.HLE && Config.PsxOut) {
 210                 u32 call = psxRegs.GPR.n.t1 & 0xff;
 211                 switch (psxRegs.pc & 0x1fffff) {
 212                         case 0xa0:
 213 #ifdef PSXBIOS_LOG
 214                                 if (call != 0x28 && call != 0xe) {
 215                                         PSXBIOS_LOG("Bios call a0: %s (%x) %x,%x,%x,%x\n", biosA0n[call], call, psxRegs.GPR.n.a0, psxRegs.GPR.n.a1, psxRegs.GPR.n.a2, psxRegs.GPR.n.a3); }
 216 #endif
 217                                 if (biosA0[call])
 218                                         biosA0[call]();
 219                                 break;
 220                         case 0xb0:
 221 #ifdef PSXBIOS_LOG
 222                                 if (call != 0x17 && call != 0xb) {
 223                                         PSXBIOS_LOG("Bios call b0: %s (%x) %x,%x,%x,%x\n", biosB0n[call], call, psxRegs.GPR.n.a0, psxRegs.GPR.n.a1, psxRegs.GPR.n.a2, psxRegs.GPR.n.a3); }
 224 #endif
 225                                 if (biosB0[call])
 226                                         biosB0[call]();
 227                                 break;
 228                         case 0xc0:
 229 #ifdef PSXBIOS_LOG
 230                                 PSXBIOS_LOG("Bios call c0: %s (%x) %x,%x,%x,%x\n", biosC0n[call], call, psxRegs.GPR.n.a0, psxRegs.GPR.n.a1, psxRegs.GPR.n.a2, psxRegs.GPR.n.a3);
 231 #endif
 232                                 if (biosC0[call])
 233                                         biosC0[call]();
 234                                 break;
 235                 }
 236         }
 237 }
 238
 239 void psxExecuteBios() {
 240         int i;
 241         for (i = 0; i < 5000000; i++) {
 242                 psxCpu->ExecuteBlock(EXEC_CALLER_BOOT);
 243                 if ((psxRegs.pc & 0xff800000) == 0x80000000)
 244                         break;
 245         }
 246         if (psxRegs.pc != 0x80030000)
 247                 SysPrintf("non-standard BIOS detected (%d, %08x)\n", i, psxRegs.pc);
 248 }
 249