libpcsxcore/r3000a.c

   1 /***************************************************************************
   2  *   Copyright (C) 2007 Ryan Schultz, PCSX-df Team, PCSX team              *
   3  *                                                                         *
   4  *   This program is free software; you can redistribute it and/or modify  *
   5  *   it under the terms of the GNU General Public License as published by  *
   6  *   the Free Software Foundation; either version 2 of the License, or     *
   7  *   (at your option) any later version.                                   *
   8  *                                                                         *
   9  *   This program is distributed in the hope that it will be useful,       *
  10  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  11  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  12  *   GNU General Public License for more details.                          *
  13  *                                                                         *
  14  *   You should have received a copy of the GNU General Public License     *
  15  *   along with this program; if not, write to the                         *
  16  *   Free Software Foundation, Inc.,                                       *
  17  *   51 Franklin Street, Fifth Floor, Boston, MA 02111-1307 USA.           *
  18  ***************************************************************************/
  19
  20 /*
  21 * R3000A CPU functions.
  22 */
  23
  24 #include "r3000a.h"
  25 #include "cdrom.h"
  26 #include "mdec.h"
  27 #include "gte.h"
  28 #include "psxinterpreter.h"
  29 #include "psxbios.h"
  30 #include "../include/compiler_features.h"
  31
  32 R3000Acpu *psxCpu = NULL;
  33 #ifdef DRC_DISABLE
  34 psxRegisters psxRegs;
  35 #endif
  36
  37 int psxInit() {
  38         SysPrintf(_("Running PCSX Version %s (%s).\n"), PCSX_VERSION, __DATE__);
  39
  40 #ifndef DRC_DISABLE
  41         if (Config.Cpu == CPU_INTERPRETER) {
  42                 psxCpu = &psxInt;
  43         } else psxCpu = &psxRec;
  44 #else
  45         Config.Cpu = CPU_INTERPRETER;
  46         psxCpu = &psxInt;
  47 #endif
  48
  49         Log = 0;
  50
  51         if (psxMemInit() == -1) return -1;
  52
  53         return psxCpu->Init();
  54 }
  55
  56 void psxReset() {
  57         boolean introBypassed = FALSE;
  58         psxMemReset();
  59
  60         memset(&psxRegs, 0, sizeof(psxRegs));
  61
  62         psxRegs.pc = 0xbfc00000; // Start in bootstrap
  63
  64         psxRegs.CP0.n.SR   = 0x10600000; // COP0 enabled | BEV = 1 | TS = 1
  65         psxRegs.CP0.n.PRid = 0x00000002; // PRevID = Revision ID, same as R3000A
  66         if (Config.HLE) {
  67                 psxRegs.CP0.n.SR |= 1u << 30;    // COP2 enabled
  68                 psxRegs.CP0.n.SR &= ~(1u << 22); // RAM exception vector
  69         }
  70
  71         psxCpu->ApplyConfig();
  72         psxCpu->Reset();
  73
  74         psxHwReset();
  75         psxBiosInit();
  76
  77         if (!Config.HLE) {
  78                 psxExecuteBios();
  79                 if (psxRegs.pc == 0x80030000 && !Config.SlowBoot) {
  80                         BiosBootBypass();
  81                         introBypassed = TRUE;
  82                 }
  83         }
  84         if (Config.HLE || introBypassed)
  85                 psxBiosSetupBootState();
  86
  87 #ifdef EMU_LOG
  88         EMU_LOG("*BIOS END*\n");
  89 #endif
  90         Log = 0;
  91 }
  92
  93 void psxShutdown() {
  94         psxBiosShutdown();
  95
  96         psxCpu->Shutdown();
  97
  98         psxMemShutdown();
  99 }
 100
 101 // cp0 is passed separately for lightrec to be less messy
 102 void psxException(u32 cause, enum R3000Abdt bdt, psxCP0Regs *cp0) {
 103         u32 opcode = intFakeFetch(psxRegs.pc);
 104
 105         if (unlikely(!Config.HLE && (opcode >> 25) == 0x25)) {
 106                 // "hokuto no ken" / "Crash Bandicot 2" ...
 107                 // BIOS does not allow to return to GTE instructions
 108                 // (just skips it, supposedly because it's scheduled already)
 109                 // so we execute it here
 110                 psxCP2Regs *cp2 = (psxCP2Regs *)(cp0 + 1);
 111                 psxRegs.code = opcode;
 112                 psxCP2[opcode & 0x3f](cp2);
 113         }
 114
 115         // Set the Cause
 116         cp0->n.Cause = (bdt << 30) | (cp0->n.Cause & 0x700) | cause;
 117
 118         // Set the EPC & PC
 119         cp0->n.EPC = bdt ? psxRegs.pc - 4 : psxRegs.pc;
 120
 121         if (cp0->n.SR & 0x400000)
 122                 psxRegs.pc = 0xbfc00180;
 123         else
 124                 psxRegs.pc = 0x80000080;
 125
 126         // Set the SR
 127         cp0->n.SR = (cp0->n.SR & ~0x3f) | ((cp0->n.SR & 0x0f) << 2);
 128 }
 129
 130 void psxBranchTest() {
 131         if ((psxRegs.cycle - psxNextsCounter) >= psxNextCounter)
 132                 psxRcntUpdate();
 133
 134         if (psxRegs.interrupt) {
 135                 if ((psxRegs.interrupt & (1 << PSXINT_SIO))) { // sio
 136                         if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_SIO].sCycle) >= psxRegs.intCycle[PSXINT_SIO].cycle) {
 137                                 psxRegs.interrupt &= ~(1 << PSXINT_SIO);
 138                                 sioInterrupt();
 139                         }
 140                 }
 141                 if (psxRegs.interrupt & (1 << PSXINT_CDR)) { // cdr
 142                         if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_CDR].sCycle) >= psxRegs.intCycle[PSXINT_CDR].cycle) {
 143                                 psxRegs.interrupt &= ~(1 << PSXINT_CDR);
 144                                 cdrInterrupt();
 145                         }
 146                 }
 147                 if (psxRegs.interrupt & (1 << PSXINT_CDREAD)) { // cdr read
 148                         if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_CDREAD].sCycle) >= psxRegs.intCycle[PSXINT_CDREAD].cycle) {
 149                                 psxRegs.interrupt &= ~(1 << PSXINT_CDREAD);
 150                                 cdrPlayReadInterrupt();
 151                         }
 152                 }
 153                 if (psxRegs.interrupt & (1 << PSXINT_GPUDMA)) { // gpu dma
 154                         if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_GPUDMA].sCycle) >= psxRegs.intCycle[PSXINT_GPUDMA].cycle) {
 155                                 psxRegs.interrupt &= ~(1 << PSXINT_GPUDMA);
 156                                 gpuInterrupt();
 157                         }
 158                 }
 159                 if (psxRegs.interrupt & (1 << PSXINT_MDECOUTDMA)) { // mdec out dma
 160                         if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_MDECOUTDMA].sCycle) >= psxRegs.intCycle[PSXINT_MDECOUTDMA].cycle) {
 161                                 psxRegs.interrupt &= ~(1 << PSXINT_MDECOUTDMA);
 162                                 mdec1Interrupt();
 163                         }
 164                 }
 165                 if (psxRegs.interrupt & (1 << PSXINT_SPUDMA)) { // spu dma
 166                         if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_SPUDMA].sCycle) >= psxRegs.intCycle[PSXINT_SPUDMA].cycle) {
 167                                 psxRegs.interrupt &= ~(1 << PSXINT_SPUDMA);
 168                                 spuInterrupt();
 169                         }
 170                 }
 171                 if (psxRegs.interrupt & (1 << PSXINT_MDECINDMA)) { // mdec in
 172                         if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_MDECINDMA].sCycle) >= psxRegs.intCycle[PSXINT_MDECINDMA].cycle) {
 173                                 psxRegs.interrupt &= ~(1 << PSXINT_MDECINDMA);
 174                                 mdec0Interrupt();
 175                         }
 176                 }
 177                 if (psxRegs.interrupt & (1 << PSXINT_GPUOTCDMA)) { // gpu otc
 178                         if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_GPUOTCDMA].sCycle) >= psxRegs.intCycle[PSXINT_GPUOTCDMA].cycle) {
 179                                 psxRegs.interrupt &= ~(1 << PSXINT_GPUOTCDMA);
 180                                 gpuotcInterrupt();
 181                         }
 182                 }
 183                 if (psxRegs.interrupt & (1 << PSXINT_CDRDMA)) { // cdrom
 184                         if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_CDRDMA].sCycle) >= psxRegs.intCycle[PSXINT_CDRDMA].cycle) {
 185                                 psxRegs.interrupt &= ~(1 << PSXINT_CDRDMA);
 186                                 cdrDmaInterrupt();
 187                         }
 188                 }
 189                 if (psxRegs.interrupt & (1 << PSXINT_CDRLID)) { // cdr lid states
 190                         if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_CDRLID].sCycle) >= psxRegs.intCycle[PSXINT_CDRLID].cycle) {
 191                                 psxRegs.interrupt &= ~(1 << PSXINT_CDRLID);
 192                                 cdrLidSeekInterrupt();
 193                         }
 194                 }
 195                 if (psxRegs.interrupt & (1 << PSXINT_IRQ10)) { // irq10 - controller port pin8
 196                         if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_IRQ10].sCycle) >= psxRegs.intCycle[PSXINT_IRQ10].cycle) {
 197                                 psxRegs.interrupt &= ~(1 << PSXINT_IRQ10);
 198                                 irq10Interrupt();
 199                         }
 200                 }
 201                 if (psxRegs.interrupt & (1 << PSXINT_SPU_UPDATE)) { // scheduled spu update
 202                         if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_SPU_UPDATE].sCycle) >= psxRegs.intCycle[PSXINT_SPU_UPDATE].cycle) {
 203                                 psxRegs.interrupt &= ~(1 << PSXINT_SPU_UPDATE);
 204                                 spuUpdate();
 205                         }
 206                 }
 207         }
 208
 209         psxRegs.CP0.n.Cause &= ~0x400;
 210         if (psxHu32(0x1070) & psxHu32(0x1074))
 211                 psxRegs.CP0.n.Cause |= 0x400;
 212         if (((psxRegs.CP0.n.Cause | 1) & psxRegs.CP0.n.SR & 0x401) == 0x401)
 213                 psxException(0, 0, &psxRegs.CP0);
 214         else if (unlikely(psxRegs.pc == psxRegs.biosBranchCheck))
 215                 psxBiosCheckBranch();
 216 }
 217
 218 void psxJumpTest() {
 219         if (!Config.HLE && Config.PsxOut) {
 220                 u32 call = psxRegs.GPR.n.t1 & 0xff;
 221                 switch (psxRegs.pc & 0x1fffff) {
 222                         case 0xa0:
 223 #ifdef PSXBIOS_LOG
 224                                 if (call != 0x28 && call != 0xe) {
 225                                         PSXBIOS_LOG("Bios call a0: %s (%x) %x,%x,%x,%x\n", biosA0n[call], call, psxRegs.GPR.n.a0, psxRegs.GPR.n.a1, psxRegs.GPR.n.a2, psxRegs.GPR.n.a3); }
 226 #endif
 227                                 if (biosA0[call])
 228                                         biosA0[call]();
 229                                 break;
 230                         case 0xb0:
 231 #ifdef PSXBIOS_LOG
 232                                 if (call != 0x17 && call != 0xb) {
 233                                         PSXBIOS_LOG("Bios call b0: %s (%x) %x,%x,%x,%x\n", biosB0n[call], call, psxRegs.GPR.n.a0, psxRegs.GPR.n.a1, psxRegs.GPR.n.a2, psxRegs.GPR.n.a3); }
 234 #endif
 235                                 if (biosB0[call])
 236                                         biosB0[call]();
 237                                 break;
 238                         case 0xc0:
 239 #ifdef PSXBIOS_LOG
 240                                 PSXBIOS_LOG("Bios call c0: %s (%x) %x,%x,%x,%x\n", biosC0n[call], call, psxRegs.GPR.n.a0, psxRegs.GPR.n.a1, psxRegs.GPR.n.a2, psxRegs.GPR.n.a3);
 241 #endif
 242                                 if (biosC0[call])
 243                                         biosC0[call]();
 244                                 break;
 245                 }
 246         }
 247 }
 248
 249 void psxExecuteBios() {
 250         int i;
 251         for (i = 0; i < 5000000; i++) {
 252                 psxCpu->ExecuteBlock(EXEC_CALLER_BOOT);
 253                 if ((psxRegs.pc & 0xff800000) == 0x80000000)
 254                         break;
 255         }
 256         if (psxRegs.pc != 0x80030000)
 257                 SysPrintf("non-standard BIOS detected (%d, %08x)\n", i, psxRegs.pc);
 258 }
 259
 260 // irq10 stuff, very preliminary
 261 static int irq10count;
 262
 263 static void psxScheduleIrq10One(u32 cycles_abs) {
 264         // schedule relative to frame start
 265         u32 c = cycles_abs - rcnts[3].cycleStart;
 266         assert((s32)c >= 0);
 267         psxRegs.interrupt |= 1 << PSXINT_IRQ10;
 268         psxRegs.intCycle[PSXINT_IRQ10].cycle = c;
 269         psxRegs.intCycle[PSXINT_IRQ10].sCycle = rcnts[3].cycleStart;
 270         new_dyna_set_event_abs(PSXINT_IRQ10, cycles_abs);
 271 }
 272
 273 void irq10Interrupt() {
 274         u32 prevc = psxRegs.intCycle[PSXINT_IRQ10].sCycle
 275                 + psxRegs.intCycle[PSXINT_IRQ10].cycle;
 276
 277         psxHu32ref(0x1070) |= SWAPu32(0x400);
 278
 279 #if 0
 280         s32 framec = psxRegs.cycle - rcnts[3].cycleStart;
 281         printf("%d:%03d irq10 #%d %3d m=%d,%d\n", frame_counter,
 282                 (s32)((float)framec / (PSXCLK / 60 / 263.0f)),
 283                 irq10count, psxRegs.cycle - prevc,
 284                 (psxRegs.CP0.n.SR & 0x401) != 0x401, !(psxHu32(0x1074) & 0x400));
 285 #endif
 286         if (--irq10count > 0) {
 287                 u32 cycles_per_line = Config.PsxType
 288                         ? PSXCLK / 50 / 314 : PSXCLK / 60 / 263;
 289                 psxScheduleIrq10One(prevc + cycles_per_line);
 290         }
 291 }
 292
 293 void psxScheduleIrq10(int irq_count, int x_cycles, int y) {
 294         //printf("%s %d, %d, %d\n", __func__, irq_count, x_cycles, y);
 295         u32 cycles_per_frame = Config.PsxType ? PSXCLK / 50 : PSXCLK / 60;
 296         u32 cycles = rcnts[3].cycleStart + cycles_per_frame;
 297         cycles += y * cycles_per_frame / (Config.PsxType ? 314 : 263);
 298         cycles += x_cycles;
 299         psxScheduleIrq10One(cycles);
 300         irq10count = irq_count;
 301 }