libpcsxcore/r3000a.h

   1 /***************************************************************************
   2  *   Copyright (C) 2007 Ryan Schultz, PCSX-df Team, PCSX team              *
   3  *                                                                         *
   4  *   This program is free software; you can redistribute it and/or modify  *
   5  *   it under the terms of the GNU General Public License as published by  *
   6  *   the Free Software Foundation; either version 2 of the License, or     *
   7  *   (at your option) any later version.                                   *
   8  *                                                                         *
   9  *   This program is distributed in the hope that it will be useful,       *
  10  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  11  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  12  *   GNU General Public License for more details.                          *
  13  *                                                                         *
  14  *   You should have received a copy of the GNU General Public License     *
  15  *   along with this program; if not, write to the                         *
  16  *   Free Software Foundation, Inc.,                                       *
  17  *   51 Franklin Street, Fifth Floor, Boston, MA 02111-1307 USA.           *
  18  ***************************************************************************/
  19
  20 #ifndef __R3000A_H__
  21 #define __R3000A_H__
  22
  23 #ifdef __cplusplus
  24 extern "C" {
  25 #endif
  26
  27 #include "psxcommon.h"
  28 #include "psxmem.h"
  29 #include "psxcounters.h"
  30 #include "psxbios.h"
  31
  32 #ifdef ICACHE_EMULATION
  33 enum {
  34         R3000ACPU_NOTIFY_CACHE_ISOLATED = 0,
  35         R3000ACPU_NOTIFY_CACHE_UNISOLATED = 1,
  36         R3000ACPU_NOTIFY_DMA3_EXE_LOAD = 2
  37 };
  38 extern uint32_t *Read_ICache(uint32_t pc);
  39 #endif
  40
  41 typedef struct {
  42         int  (*Init)();
  43         void (*Reset)();
  44         void (*Execute)();              /* executes up to a break */
  45         void (*ExecuteBlock)(); /* executes up to a jump */
  46         void (*Clear)(u32 Addr, u32 Size);
  47 #ifdef ICACHE_EMULATION
  48         void (*Notify)(int note, void *data);
  49 #endif
  50         void (*Shutdown)();
  51 } R3000Acpu;
  52
  53 extern R3000Acpu *psxCpu;
  54 extern R3000Acpu psxInt;
  55 extern R3000Acpu psxRec;
  56
  57 typedef union {
  58 #if defined(__BIGENDIAN__)
  59         struct { u8 h3, h2, h, l; } b;
  60         struct { s8 h3, h2, h, l; } sb;
  61         struct { u16 h, l; } w;
  62         struct { s16 h, l; } sw;
  63 #else
  64         struct { u8 l, h, h2, h3; } b;
  65         struct { u16 l, h; } w;
  66         struct { s8 l, h, h2, h3; } sb;
  67         struct { s16 l, h; } sw;
  68 #endif
  69 } PAIR;
  70
  71 typedef union {
  72         struct {
  73                 u32   r0, at, v0, v1, a0, a1, a2, a3,
  74                                                 t0, t1, t2, t3, t4, t5, t6, t7,
  75                                                 s0, s1, s2, s3, s4, s5, s6, s7,
  76                                                 t8, t9, k0, k1, gp, sp, s8, ra, lo, hi;
  77         } n;
  78         u32 r[34]; /* Lo, Hi in r[32] and r[33] */
  79         PAIR p[34];
  80 } psxGPRRegs;
  81
  82 typedef union {
  83         struct {
  84                 u32     Index,     Random,    EntryLo0,  EntryLo1,
  85                                                 Context,   PageMask,  Wired,     Reserved0,
  86                                                 BadVAddr,  Count,     EntryHi,   Compare,
  87                                                 Status,    Cause,     EPC,       PRid,
  88                                                 Config,    LLAddr,    WatchLO,   WatchHI,
  89                                                 XContext,  Reserved1, Reserved2, Reserved3,
  90                                                 Reserved4, Reserved5, ECC,       CacheErr,
  91                                                 TagLo,     TagHi,     ErrorEPC,  Reserved6;
  92         } n;
  93         u32 r[32];
  94         PAIR p[32];
  95 } psxCP0Regs;
  96
  97 typedef struct {
  98         short x, y;
  99 } SVector2D;
 100
 101 typedef struct {
 102         short z, pad;
 103 } SVector2Dz;
 104
 105 typedef struct {
 106         short x, y, z, pad;
 107 } SVector3D;
 108
 109 typedef struct {
 110         short x, y, z, pad;
 111 } LVector3D;
 112
 113 typedef struct {
 114         unsigned char r, g, b, c;
 115 } CBGR;
 116
 117 typedef struct {
 118         short m11, m12, m13, m21, m22, m23, m31, m32, m33, pad;
 119 } SMatrix3D;
 120
 121 typedef union {
 122         struct {
 123                 SVector3D     v0, v1, v2;
 124                 CBGR          rgb;
 125                 s32          otz;
 126                 s32          ir0, ir1, ir2, ir3;
 127                 SVector2D     sxy0, sxy1, sxy2, sxyp;
 128                 SVector2Dz    sz0, sz1, sz2, sz3;
 129                 CBGR          rgb0, rgb1, rgb2;
 130                 s32          reserved;
 131                 s32          mac0, mac1, mac2, mac3;
 132                 u32 irgb, orgb;
 133                 s32          lzcs, lzcr;
 134         } n;
 135         u32 r[32];
 136         PAIR p[32];
 137 } psxCP2Data;
 138
 139 typedef union {
 140         struct {
 141                 SMatrix3D rMatrix;
 142                 s32      trX, trY, trZ;
 143                 SMatrix3D lMatrix;
 144                 s32      rbk, gbk, bbk;
 145                 SMatrix3D cMatrix;
 146                 s32      rfc, gfc, bfc;
 147                 s32      ofx, ofy;
 148                 s32      h;
 149                 s32      dqa, dqb;
 150                 s32      zsf3, zsf4;
 151                 s32      flag;
 152         } n;
 153         u32 r[32];
 154         PAIR p[32];
 155 } psxCP2Ctrl;
 156
 157 enum {
 158         PSXINT_SIO = 0,
 159         PSXINT_CDR,
 160         PSXINT_CDREAD,
 161         PSXINT_GPUDMA,
 162         PSXINT_MDECOUTDMA,
 163         PSXINT_SPUDMA,
 164         PSXINT_GPUBUSY,
 165         PSXINT_MDECINDMA,
 166         PSXINT_GPUOTCDMA,
 167         PSXINT_CDRDMA,
 168         PSXINT_NEWDRC_CHECK,
 169         PSXINT_RCNT,
 170         PSXINT_CDRLID,
 171         PSXINT_CDRPLAY,
 172         PSXINT_SPU_UPDATE,
 173         PSXINT_COUNT
 174 };
 175
 176 typedef struct psxCP2Regs {
 177         psxCP2Data CP2D;        /* Cop2 data registers */
 178         psxCP2Ctrl CP2C;        /* Cop2 control registers */
 179 } psxCP2Regs;
 180
 181 typedef struct {
 182         psxGPRRegs GPR;         /* General Purpose Registers */
 183         psxCP0Regs CP0;         /* Coprocessor0 Registers */
 184         union {
 185                 struct {
 186                         psxCP2Data CP2D;        /* Cop2 data registers */
 187                         psxCP2Ctrl CP2C;        /* Cop2 control registers */
 188                 };
 189                 psxCP2Regs CP2;
 190         };
 191     u32 pc;                             /* Program counter */
 192     u32 code;                   /* The instruction */
 193         u32 cycle;
 194         u32 interrupt;
 195         struct { u32 sCycle, cycle; } intCycle[32];
 196         u32 gteBusyCycle;
 197         // warning: changing anything in psxRegisters requires update of all
 198         // asm in libpcsxcore/new_dynarec/, but this member can be replaced
 199         u32 reserved[3];
 200 } psxRegisters;
 201
 202 extern psxRegisters psxRegs;
 203
 204 /* new_dynarec stuff */
 205 extern u32 event_cycles[PSXINT_COUNT];
 206 extern u32 next_interupt;
 207
 208 void new_dyna_before_save(void);
 209 void new_dyna_after_save(void);
 210 void new_dyna_freeze(void *f, int mode);
 211
 212 #define new_dyna_set_event(e, c) { \
 213         s32 c_ = c; \
 214         u32 abs_ = psxRegs.cycle + c_; \
 215         s32 odi_ = next_interupt - psxRegs.cycle; \
 216         event_cycles[e] = abs_; \
 217         if (c_ < odi_) { \
 218                 /*printf("%u: next_interupt %d -> %d (%u)\n", psxRegs.cycle, odi_, c_, abs_);*/ \
 219                 next_interupt = abs_; \
 220         } \
 221 }
 222
 223 #if defined(__BIGENDIAN__)
 224
 225 #define _i32(x) *(s32 *)&x
 226 #define _u32(x) x
 227
 228 #define _i16(x) (((short *)&x)[1])
 229 #define _u16(x) (((unsigned short *)&x)[1])
 230
 231 #define _i8(x) (((char *)&x)[3])
 232 #define _u8(x) (((unsigned char *)&x)[3])
 233
 234 #else
 235
 236 #define _i32(x) *(s32 *)&x
 237 #define _u32(x) x
 238
 239 #define _i16(x) *(short *)&x
 240 #define _u16(x) *(unsigned short *)&x
 241
 242 #define _i8(x) *(char *)&x
 243 #define _u8(x) *(unsigned char *)&x
 244
 245 #endif
 246
 247 /**** R3000A Instruction Macros ****/
 248 #define _PC_       psxRegs.pc       // The next PC to be executed
 249
 250 #define _fOp_(code)             ((code >> 26)       )  // The opcode part of the instruction register
 251 #define _fFunct_(code)  ((code      ) & 0x3F)  // The funct part of the instruction register
 252 #define _fRd_(code)             ((code >> 11) & 0x1F)  // The rd part of the instruction register
 253 #define _fRt_(code)             ((code >> 16) & 0x1F)  // The rt part of the instruction register
 254 #define _fRs_(code)             ((code >> 21) & 0x1F)  // The rs part of the instruction register
 255 #define _fSa_(code)             ((code >>  6) & 0x1F)  // The sa part of the instruction register
 256 #define _fIm_(code)             ((u16)code)            // The immediate part of the instruction register
 257 #define _fTarget_(code) (code & 0x03ffffff)    // The target part of the instruction register
 258
 259 #define _fImm_(code)    ((s16)code)            // sign-extended immediate
 260 #define _fImmU_(code)   (code&0xffff)          // zero-extended immediate
 261
 262 #define _Op_     _fOp_(psxRegs.code)
 263 #define _Funct_  _fFunct_(psxRegs.code)
 264 #define _Rd_     _fRd_(psxRegs.code)
 265 #define _Rt_     _fRt_(psxRegs.code)
 266 #define _Rs_     _fRs_(psxRegs.code)
 267 #define _Sa_     _fSa_(psxRegs.code)
 268 #define _Im_     _fIm_(psxRegs.code)
 269 #define _Target_ _fTarget_(psxRegs.code)
 270
 271 #define _Imm_    _fImm_(psxRegs.code)
 272 #define _ImmU_   _fImmU_(psxRegs.code)
 273
 274 #define _rRs_   psxRegs.GPR.r[_Rs_]   // Rs register
 275 #define _rRt_   psxRegs.GPR.r[_Rt_]   // Rt register
 276 #define _rRd_   psxRegs.GPR.r[_Rd_]   // Rd register
 277 #define _rSa_   psxRegs.GPR.r[_Sa_]   // Sa register
 278 #define _rFs_   psxRegs.CP0.r[_Rd_]   // Fs register
 279
 280 #define _c2dRs_ psxRegs.CP2D.r[_Rs_]  // Rs cop2 data register
 281 #define _c2dRt_ psxRegs.CP2D.r[_Rt_]  // Rt cop2 data register
 282 #define _c2dRd_ psxRegs.CP2D.r[_Rd_]  // Rd cop2 data register
 283 #define _c2dSa_ psxRegs.CP2D.r[_Sa_]  // Sa cop2 data register
 284
 285 #define _rHi_   psxRegs.GPR.n.hi   // The HI register
 286 #define _rLo_   psxRegs.GPR.n.lo   // The LO register
 287
 288 #define _JumpTarget_    ((_Target_ * 4) + (_PC_ & 0xf0000000))   // Calculates the target during a jump instruction
 289 #define _BranchTarget_  ((s16)_Im_ * 4 + _PC_)                 // Calculates the target during a branch instruction
 290
 291 #define _SetLink(x)     psxRegs.GPR.r[x] = _PC_ + 4;       // Sets the return address in the link register
 292
 293 int  psxInit();
 294 void psxReset();
 295 void psxShutdown();
 296 void psxException(u32 code, u32 bd);
 297 void psxBranchTest();
 298 void psxExecuteBios();
 299 int  psxTestLoadDelay(int reg, u32 tmp);
 300 void psxDelayTest(int reg, u32 bpc);
 301 void psxTestSWInts();
 302 void psxJumpTest();
 303
 304 #ifdef __cplusplus
 305 }
 306 #endif
 307 #endif