[picodrive.git] / cpu / drc / emit_arm.c

// Basic macros to emit ARM instructions and some utils

// (c) Copyright 2008-2009, Grazvydas "notaz" Ignotas
// Free for non-commercial use.

#define CONTEXT_REG 7

// XXX: tcache_ptr type for SVP and SH2 compilers differs..
#define EMIT_PTR(ptr, x) \
	do { \
		*(u32 *)ptr = x; \
		ptr = (void *)((u8 *)ptr + sizeof(u32)); \
		COUNT_OP; \
	} while (0)

#define EMIT(x) EMIT_PTR(tcache_ptr, x)

#define A_R4M  (1 << 4)
#define A_R5M  (1 << 5)
#define A_R6M  (1 << 6)
#define A_R7M  (1 << 7)
#define A_R8M  (1 << 8)
#define A_R9M  (1 << 9)
#define A_R10M (1 << 10)
#define A_R11M (1 << 11)
#define A_R14M (1 << 14)

#define A_COND_AL 0xe
#define A_COND_EQ 0x0
#define A_COND_NE 0x1
#define A_COND_MI 0x4
#define A_COND_PL 0x5
#define A_COND_LE 0xd

/* addressing mode 1 */
#define A_AM1_LSL 0
#define A_AM1_LSR 1
#define A_AM1_ASR 2
#define A_AM1_ROR 3

#define A_AM1_IMM(ror2,imm8)                  (((ror2)<<8) | (imm8) | 0x02000000)
#define A_AM1_REG_XIMM(shift_imm,shift_op,rm) (((shift_imm)<<7) | ((shift_op)<<5) | (rm))
#define A_AM1_REG_XREG(rs,shift_op,rm)        (((rs)<<8) | ((shift_op)<<5) | 0x10 | (rm))

/* data processing op */
#define A_OP_AND 0x0
#define A_OP_EOR 0x1
#define A_OP_SUB 0x2
#define A_OP_RSB 0x3
#define A_OP_ADD 0x4
#define A_OP_TST 0x8
#define A_OP_CMP 0xa
#define A_OP_ORR 0xc
#define A_OP_MOV 0xd
#define A_OP_BIC 0xe

#define EOP_C_DOP_X(cond,op,s,rn,rd,shifter_op) \
	EMIT(((cond)<<28) | ((op)<< 21) | ((s)<<20) | ((rn)<<16) | ((rd)<<12) | (shifter_op))

#define EOP_C_DOP_IMM(     cond,op,s,rn,rd,ror2,imm8)             EOP_C_DOP_X(cond,op,s,rn,rd,A_AM1_IMM(ror2,imm8))
#define EOP_C_DOP_REG_XIMM(cond,op,s,rn,rd,shift_imm,shift_op,rm) EOP_C_DOP_X(cond,op,s,rn,rd,A_AM1_REG_XIMM(shift_imm,shift_op,rm))
#define EOP_C_DOP_REG_XREG(cond,op,s,rn,rd,rs,       shift_op,rm) EOP_C_DOP_X(cond,op,s,rn,rd,A_AM1_REG_XREG(rs,       shift_op,rm))

#define EOP_MOV_IMM(rd,   ror2,imm8) EOP_C_DOP_IMM(A_COND_AL,A_OP_MOV,0, 0,rd,ror2,imm8)
#define EOP_ORR_IMM(rd,rn,ror2,imm8) EOP_C_DOP_IMM(A_COND_AL,A_OP_ORR,0,rn,rd,ror2,imm8)
#define EOP_ADD_IMM(rd,rn,ror2,imm8) EOP_C_DOP_IMM(A_COND_AL,A_OP_ADD,0,rn,rd,ror2,imm8)
#define EOP_BIC_IMM(rd,rn,ror2,imm8) EOP_C_DOP_IMM(A_COND_AL,A_OP_BIC,0,rn,rd,ror2,imm8)
#define EOP_AND_IMM(rd,rn,ror2,imm8) EOP_C_DOP_IMM(A_COND_AL,A_OP_AND,0,rn,rd,ror2,imm8)
#define EOP_SUB_IMM(rd,rn,ror2,imm8) EOP_C_DOP_IMM(A_COND_AL,A_OP_SUB,0,rn,rd,ror2,imm8)
#define EOP_TST_IMM(   rn,ror2,imm8) EOP_C_DOP_IMM(A_COND_AL,A_OP_TST,1,rn, 0,ror2,imm8)
#define EOP_CMP_IMM(   rn,ror2,imm8) EOP_C_DOP_IMM(A_COND_AL,A_OP_CMP,1,rn, 0,ror2,imm8)
#define EOP_RSB_IMM(rd,rn,ror2,imm8) EOP_C_DOP_IMM(A_COND_AL,A_OP_RSB,0,rn,rd,ror2,imm8)

#define EOP_MOV_REG(s,   rd,shift_imm,shift_op,rm) EOP_C_DOP_REG_XIMM(A_COND_AL,A_OP_MOV,s, 0,rd,shift_imm,shift_op,rm)
#define EOP_ORR_REG(s,rn,rd,shift_imm,shift_op,rm) EOP_C_DOP_REG_XIMM(A_COND_AL,A_OP_ORR,s,rn,rd,shift_imm,shift_op,rm)
#define EOP_ADD_REG(s,rn,rd,shift_imm,shift_op,rm) EOP_C_DOP_REG_XIMM(A_COND_AL,A_OP_ADD,s,rn,rd,shift_imm,shift_op,rm)
#define EOP_TST_REG(  rn,   shift_imm,shift_op,rm) EOP_C_DOP_REG_XIMM(A_COND_AL,A_OP_TST,1,rn, 0,shift_imm,shift_op,rm)

#define EOP_MOV_REG2(s,   rd,rs,shift_op,rm) EOP_C_DOP_REG_XREG(A_COND_AL,A_OP_MOV,s, 0,rd,rs,shift_op,rm)
#define EOP_ADD_REG2(s,rn,rd,rs,shift_op,rm) EOP_C_DOP_REG_XREG(A_COND_AL,A_OP_ADD,s,rn,rd,rs,shift_op,rm)
#define EOP_SUB_REG2(s,rn,rd,rs,shift_op,rm) EOP_C_DOP_REG_XREG(A_COND_AL,A_OP_SUB,s,rn,rd,rs,shift_op,rm)

#define EOP_MOV_REG_SIMPLE(rd,rm)           EOP_MOV_REG(0,rd,0,A_AM1_LSL,rm)
#define EOP_MOV_REG_LSL(rd,   rm,shift_imm) EOP_MOV_REG(0,rd,shift_imm,A_AM1_LSL,rm)
#define EOP_MOV_REG_LSR(rd,   rm,shift_imm) EOP_MOV_REG(0,rd,shift_imm,A_AM1_LSR,rm)
#define EOP_MOV_REG_ASR(rd,   rm,shift_imm) EOP_MOV_REG(0,rd,shift_imm,A_AM1_ASR,rm)
#define EOP_MOV_REG_ROR(rd,   rm,shift_imm) EOP_MOV_REG(0,rd,shift_imm,A_AM1_ROR,rm)

#define EOP_ORR_REG_SIMPLE(rd,rm)           EOP_ORR_REG(0,rd,rd,0,A_AM1_LSL,rm)
#define EOP_ORR_REG_LSL(rd,rn,rm,shift_imm) EOP_ORR_REG(0,rn,rd,shift_imm,A_AM1_LSL,rm)
#define EOP_ORR_REG_LSR(rd,rn,rm,shift_imm) EOP_ORR_REG(0,rn,rd,shift_imm,A_AM1_LSR,rm)
#define EOP_ORR_REG_ASR(rd,rn,rm,shift_imm) EOP_ORR_REG(0,rn,rd,shift_imm,A_AM1_ASR,rm)
#define EOP_ORR_REG_ROR(rd,rn,rm,shift_imm) EOP_ORR_REG(0,rn,rd,shift_imm,A_AM1_ROR,rm)

#define EOP_ADD_REG_SIMPLE(rd,rm)           EOP_ADD_REG(0,rd,rd,0,A_AM1_LSL,rm)
#define EOP_ADD_REG_LSL(rd,rn,rm,shift_imm) EOP_ADD_REG(0,rn,rd,shift_imm,A_AM1_LSL,rm)
#define EOP_ADD_REG_LSR(rd,rn,rm,shift_imm) EOP_ADD_REG(0,rn,rd,shift_imm,A_AM1_LSR,rm)

#define EOP_TST_REG_SIMPLE(rn,rm)           EOP_TST_REG(  rn,   0,A_AM1_LSL,rm)

#define EOP_MOV_REG2_LSL(rd,   rm,rs)       EOP_MOV_REG2(0,   rd,rs,A_AM1_LSL,rm)
#define EOP_MOV_REG2_ROR(rd,   rm,rs)       EOP_MOV_REG2(0,   rd,rs,A_AM1_ROR,rm)
#define EOP_ADD_REG2_LSL(rd,rn,rm,rs)       EOP_ADD_REG2(0,rn,rd,rs,A_AM1_LSL,rm)
#define EOP_SUB_REG2_LSL(rd,rn,rm,rs)       EOP_SUB_REG2(0,rn,rd,rs,A_AM1_LSL,rm)

/* addressing mode 2 */
#define EOP_C_AM2_IMM(cond,u,b,l,rn,rd,offset_12) \
	EMIT(((cond)<<28) | 0x05000000 | ((u)<<23) | ((b)<<22) | ((l)<<20) | ((rn)<<16) | ((rd)<<12) | (offset_12))

/* addressing mode 3 */
#define EOP_C_AM3(cond,u,r,l,rn,rd,s,h,immed_reg) \
	EMIT(((cond)<<28) | 0x01000090 | ((u)<<23) | ((r)<<22) | ((l)<<20) | ((rn)<<16) | ((rd)<<12) | \
			((s)<<6) | ((h)<<5) | (immed_reg))

#define EOP_C_AM3_IMM(cond,u,l,rn,rd,s,h,offset_8) EOP_C_AM3(cond,u,1,l,rn,rd,s,h,(((offset_8)&0xf0)<<4)|((offset_8)&0xf))

#define EOP_C_AM3_REG(cond,u,l,rn,rd,s,h,rm)       EOP_C_AM3(cond,u,0,l,rn,rd,s,h,rm)

/* ldr and str */
#define EOP_LDR_IMM(   rd,rn,offset_12) EOP_C_AM2_IMM(A_COND_AL,1,0,1,rn,rd,offset_12)
#define EOP_LDR_NEGIMM(rd,rn,offset_12) EOP_C_AM2_IMM(A_COND_AL,0,0,1,rn,rd,offset_12)
#define EOP_LDR_SIMPLE(rd,rn)           EOP_C_AM2_IMM(A_COND_AL,1,0,1,rn,rd,0)
#define EOP_STR_IMM(   rd,rn,offset_12) EOP_C_AM2_IMM(A_COND_AL,1,0,0,rn,rd,offset_12)
#define EOP_STR_SIMPLE(rd,rn)           EOP_C_AM2_IMM(A_COND_AL,1,0,0,rn,rd,0)

#define EOP_LDRH_IMM(   rd,rn,offset_8)  EOP_C_AM3_IMM(A_COND_AL,1,1,rn,rd,0,1,offset_8)
#define EOP_LDRH_SIMPLE(rd,rn)           EOP_C_AM3_IMM(A_COND_AL,1,1,rn,rd,0,1,0)
#define EOP_LDRH_REG(   rd,rn,rm)        EOP_C_AM3_REG(A_COND_AL,1,1,rn,rd,0,1,rm)
#define EOP_STRH_IMM(   rd,rn,offset_8)  EOP_C_AM3_IMM(A_COND_AL,1,0,rn,rd,0,1,offset_8)
#define EOP_STRH_SIMPLE(rd,rn)           EOP_C_AM3_IMM(A_COND_AL,1,0,rn,rd,0,1,0)
#define EOP_STRH_REG(   rd,rn,rm)        EOP_C_AM3_REG(A_COND_AL,1,0,rn,rd,0,1,rm)

/* ldm and stm */
#define EOP_XXM(cond,p,u,s,w,l,rn,list) \
	EMIT(((cond)<<28) | (1<<27) | ((p)<<24) | ((u)<<23) | ((s)<<22) | ((w)<<21) | ((l)<<20) | ((rn)<<16) | (list))

#define EOP_STMFD_ST(list) EOP_XXM(A_COND_AL,1,0,0,1,0,13,list)
#define EOP_LDMFD_ST(list) EOP_XXM(A_COND_AL,0,1,0,1,1,13,list)

/* branches */
#define EOP_C_BX(cond,rm) \
	EMIT(((cond)<<28) | 0x012fff10 | (rm))

#define EOP_BX(rm) EOP_C_BX(A_COND_AL,rm)

#define EOP_C_B(cond,l,signed_immed_24) \
	EMIT(((cond)<<28) | 0x0a000000 | ((l)<<24) | (signed_immed_24))

#define EOP_B( signed_immed_24) EOP_C_B(A_COND_AL,0,signed_immed_24)
#define EOP_BL(signed_immed_24) EOP_C_B(A_COND_AL,1,signed_immed_24)

/* misc */
#define EOP_C_MUL(cond,s,rd,rs,rm) \
	EMIT(((cond)<<28) | ((s)<<20) | ((rd)<<16) | ((rs)<<8) | 0x90 | (rm))

#define EOP_MUL(rd,rm,rs) EOP_C_MUL(A_COND_AL,0,rd,rs,rm) // note: rd != rm

#define EOP_C_MRS(cond,rd) \
	EMIT(((cond)<<28) | 0x010f0000 | ((rd)<<12))

#define EOP_C_MSR_IMM(cond,ror2,imm) \
	EMIT(((cond)<<28) | 0x0328f000 | ((ror2)<<8) | (imm)) // cpsr_f

#define EOP_C_MSR_REG(cond,rm) \
	EMIT(((cond)<<28) | 0x0128f000 | (rm)) // cpsr_f

#define EOP_MRS(rd)           EOP_C_MRS(A_COND_AL,rd)
#define EOP_MSR_IMM(ror2,imm) EOP_C_MSR_IMM(A_COND_AL,ror2,imm)
#define EOP_MSR_REG(rm)       EOP_C_MSR_REG(A_COND_AL,rm)


static void emith_op_imm(int cond, int op, int r, unsigned int imm)
{
	int ror2, rn = r;
	u32 v;

	if (op == A_OP_MOV)
		rn = 0;
	else if (imm == 0)
		return;

	for (v = imm, ror2 = 0; v != 0 || op == A_OP_MOV; v >>= 8, ror2 -= 8/2) {
		/* shift down to get 'best' rot2 */
		for (; v && !(v & 3); v >>= 2)
			ror2--;

		EOP_C_DOP_IMM(cond, op, 0, rn, r, ror2 & 0x0f, v & 0xff);

		if (op == A_OP_MOV) {
			op = A_OP_ORR;
			rn = r;
		}
	}
}

#define is_offset_24(val) \
	((val) >= (int)0xff000000 && (val) <= 0x00ffffff)

static int emith_xbranch(int cond, void *target, int is_call)
{
	int val = (u32 *)target - (u32 *)tcache_ptr - 2;
	int direct = is_offset_24(val);
	u32 *start_ptr = (u32 *)tcache_ptr;

	if (direct)
	{
		EOP_C_B(cond,is_call,val & 0xffffff);		// b, bl target
	}
	else
	{
#ifdef __EPOC32__
//		elprintf(EL_SVP, "emitting indirect jmp %08x->%08x", tcache_ptr, target);
		if (is_call)
			EOP_ADD_IMM(14,15,0,8);			// add lr,pc,#8
		EOP_C_AM2_IMM(cond,1,0,1,15,15,0);		// ldrcc pc,[pc]
		EOP_MOV_REG_SIMPLE(15,15);			// mov pc, pc
		EMIT((u32)target);
#else
		// should never happen
		elprintf(EL_STATUS|EL_SVP|EL_ANOMALY, "indirect jmp %08x->%08x", target, tcache_ptr);
		exit(1);
#endif
	}

	return (u32 *)tcache_ptr - start_ptr;
}


#define EMITH_CONDITIONAL(code, is_nonzero) { \
	u32 val, cond, *ptr; \
	cond = (is_nonzero) ? A_COND_NE : A_COND_EQ; \
	ptr = (void *)tcache_ptr; \
	tcache_ptr = (void *)(ptr + 1); \
	code; \
	val = (u32 *)tcache_ptr - (ptr + 2); \
	EMIT_PTR(ptr, ((cond)<<28) | 0x0a000000 | (val & 0xffffff)); \
}

#define emith_move_r_r(dst, src) \
	EOP_MOV_REG_SIMPLE(dst, src)

#define emith_move_r_imm(r, imm) \
	emith_op_imm(A_COND_AL, A_OP_MOV, r, imm)

#define emith_add_r_imm(r, imm) \
	emith_op_imm(A_COND_AL, A_OP_ADD, r, imm)

#define emith_sub_r_imm(r, imm) \
	emith_op_imm(A_COND_AL, A_OP_SUB, r, imm)

#define emith_ctx_read(r, offs) \
	EOP_LDR_IMM(r, CONTEXT_REG, offs)

#define emith_ctx_write(r, offs) \
	EOP_STR_IMM(r, CONTEXT_REG, offs)

// upto 4 args
#define emith_pass_arg_r(arg, reg) \
	EOP_MOV_REG_SIMPLE(arg, reg)

#define emith_pass_arg_imm(arg, imm) \
	emith_move_r_imm(arg, imm)

#define emith_call_cond(cond, target) \
	emith_xbranch(cond, target, 1)

#define emith_jump_cond(cond, target) \
	emith_xbranch(cond, target, 0)

#define emith_call(target) \
	emith_call_cond(A_COND_AL, target)

#define emith_jump(target) \
	emith_jump_cond(A_COND_AL, target)

/* SH2 drc specific */
#define emith_test_t() { \
	int r = rcache_get_reg(SHR_SR, RC_GR_READ); \
	EOP_TST_IMM(r, 0, 1); \
}
Commit	Line	Data
65ca3034	1	// Basic macros to emit ARM instructions and some utils
65ca3034	2
65c75cb0	3	// (c) Copyright 2008-2009, Grazvydas "notaz" Ignotas
65ca3034	4	// Free for non-commercial use.
65ca3034	5
65c75cb0	6	#define CONTEXT_REG 7
	7
	8	// XXX: tcache_ptr type for SVP and SH2 compilers differs..
	9	#define EMIT_PTR(ptr, x) \
	10	do { \
	11	(u32 )ptr = x; \
	12	ptr = (void )((u8 )ptr + sizeof(u32)); \
553c3eaa	13	COUNT_OP; \
65c75cb0	14	} while (0)
	15
	16	#define EMIT(x) EMIT_PTR(tcache_ptr, x)
5c129565	17
e807ac75	18	#define A_R4M (1 << 4)
	19	#define A_R5M (1 << 5)
	20	#define A_R6M (1 << 6)
	21	#define A_R7M (1 << 7)
	22	#define A_R8M (1 << 8)
	23	#define A_R9M (1 << 9)
	24	#define A_R10M (1 << 10)
	25	#define A_R11M (1 << 11)
5c129565	26	#define A_R14M (1 << 14)
	27
	28	#define A_COND_AL 0xe
b9c1d012	29	#define A_COND_EQ 0x0
bad5731d	30	#define A_COND_NE 0x1
	31	#define A_COND_MI 0x4
	32	#define A_COND_PL 0x5
45883918	33	#define A_COND_LE 0xd
5c129565	34
	35	/* addressing mode 1 */
	36	#define A_AM1_LSL 0
	37	#define A_AM1_LSR 1
	38	#define A_AM1_ASR 2
	39	#define A_AM1_ROR 3
	40
	41	#define A_AM1_IMM(ror2,imm8) (((ror2)<<8) \| (imm8) \| 0x02000000)
	42	#define A_AM1_REG_XIMM(shift_imm,shift_op,rm) (((shift_imm)<<7) \| ((shift_op)<<5) \| (rm))
89fea1e9	43	#define A_AM1_REG_XREG(rs,shift_op,rm) (((rs)<<8) \| ((shift_op)<<5) \| 0x10 \| (rm))
5c129565	44
5c129565	45	/* data processing op */
5d817c91	46	#define A_OP_AND 0x0
89fea1e9	47	#define A_OP_EOR 0x1
5d817c91	48	#define A_OP_SUB 0x2
89fea1e9	49	#define A_OP_RSB 0x3
f48f5e3b	50	#define A_OP_ADD 0x4
b9c1d012	51	#define A_OP_TST 0x8
0e4d7ba5	52	#define A_OP_CMP 0xa
5c129565	53	#define A_OP_ORR 0xc
5c129565	54	#define A_OP_MOV 0xd
5d817c91	55	#define A_OP_BIC 0xe
5c129565	56
	57	#define EOP_C_DOP_X(cond,op,s,rn,rd,shifter_op) \
	58	EMIT(((cond)<<28) \| ((op)<< 21) \| ((s)<<20) \| ((rn)<<16) \| ((rd)<<12) \| (shifter_op))
	59
89fea1e9	60	#define EOP_C_DOP_IMM( cond,op,s,rn,rd,ror2,imm8) EOP_C_DOP_X(cond,op,s,rn,rd,A_AM1_IMM(ror2,imm8))
	61	#define EOP_C_DOP_REG_XIMM(cond,op,s,rn,rd,shift_imm,shift_op,rm) EOP_C_DOP_X(cond,op,s,rn,rd,A_AM1_REG_XIMM(shift_imm,shift_op,rm))
	62	#define EOP_C_DOP_REG_XREG(cond,op,s,rn,rd,rs, shift_op,rm) EOP_C_DOP_X(cond,op,s,rn,rd,A_AM1_REG_XREG(rs, shift_op,rm))
5c129565	63
5d817c91	64	#define EOP_MOV_IMM(rd, ror2,imm8) EOP_C_DOP_IMM(A_COND_AL,A_OP_MOV,0, 0,rd,ror2,imm8)
	65	#define EOP_ORR_IMM(rd,rn,ror2,imm8) EOP_C_DOP_IMM(A_COND_AL,A_OP_ORR,0,rn,rd,ror2,imm8)
	66	#define EOP_ADD_IMM(rd,rn,ror2,imm8) EOP_C_DOP_IMM(A_COND_AL,A_OP_ADD,0,rn,rd,ror2,imm8)
	67	#define EOP_BIC_IMM(rd,rn,ror2,imm8) EOP_C_DOP_IMM(A_COND_AL,A_OP_BIC,0,rn,rd,ror2,imm8)
	68	#define EOP_AND_IMM(rd,rn,ror2,imm8) EOP_C_DOP_IMM(A_COND_AL,A_OP_AND,0,rn,rd,ror2,imm8)
d274c33b	69	#define EOP_SUB_IMM(rd,rn,ror2,imm8) EOP_C_DOP_IMM(A_COND_AL,A_OP_SUB,0,rn,rd,ror2,imm8)
bad5731d	70	#define EOP_TST_IMM( rn,ror2,imm8) EOP_C_DOP_IMM(A_COND_AL,A_OP_TST,1,rn, 0,ror2,imm8)
45883918	71	#define EOP_CMP_IMM( rn,ror2,imm8) EOP_C_DOP_IMM(A_COND_AL,A_OP_CMP,1,rn, 0,ror2,imm8)
89fea1e9	72	#define EOP_RSB_IMM(rd,rn,ror2,imm8) EOP_C_DOP_IMM(A_COND_AL,A_OP_RSB,0,rn,rd,ror2,imm8)
5c129565	73
89fea1e9	74	#define EOP_MOV_REG(s, rd,shift_imm,shift_op,rm) EOP_C_DOP_REG_XIMM(A_COND_AL,A_OP_MOV,s, 0,rd,shift_imm,shift_op,rm)
	75	#define EOP_ORR_REG(s,rn,rd,shift_imm,shift_op,rm) EOP_C_DOP_REG_XIMM(A_COND_AL,A_OP_ORR,s,rn,rd,shift_imm,shift_op,rm)
	76	#define EOP_ADD_REG(s,rn,rd,shift_imm,shift_op,rm) EOP_C_DOP_REG_XIMM(A_COND_AL,A_OP_ADD,s,rn,rd,shift_imm,shift_op,rm)
	77	#define EOP_TST_REG( rn, shift_imm,shift_op,rm) EOP_C_DOP_REG_XIMM(A_COND_AL,A_OP_TST,1,rn, 0,shift_imm,shift_op,rm)
	78
	79	#define EOP_MOV_REG2(s, rd,rs,shift_op,rm) EOP_C_DOP_REG_XREG(A_COND_AL,A_OP_MOV,s, 0,rd,rs,shift_op,rm)
	80	#define EOP_ADD_REG2(s,rn,rd,rs,shift_op,rm) EOP_C_DOP_REG_XREG(A_COND_AL,A_OP_ADD,s,rn,rd,rs,shift_op,rm)
	81	#define EOP_SUB_REG2(s,rn,rd,rs,shift_op,rm) EOP_C_DOP_REG_XREG(A_COND_AL,A_OP_SUB,s,rn,rd,rs,shift_op,rm)
5c129565	82
5d817c91	83	#define EOP_MOV_REG_SIMPLE(rd,rm) EOP_MOV_REG(0,rd,0,A_AM1_LSL,rm)
	84	#define EOP_MOV_REG_LSL(rd, rm,shift_imm) EOP_MOV_REG(0,rd,shift_imm,A_AM1_LSL,rm)
	85	#define EOP_MOV_REG_LSR(rd, rm,shift_imm) EOP_MOV_REG(0,rd,shift_imm,A_AM1_LSR,rm)
	86	#define EOP_MOV_REG_ASR(rd, rm,shift_imm) EOP_MOV_REG(0,rd,shift_imm,A_AM1_ASR,rm)
	87	#define EOP_MOV_REG_ROR(rd, rm,shift_imm) EOP_MOV_REG(0,rd,shift_imm,A_AM1_ROR,rm)
5c129565	88
5d817c91	89	#define EOP_ORR_REG_SIMPLE(rd,rm) EOP_ORR_REG(0,rd,rd,0,A_AM1_LSL,rm)
	90	#define EOP_ORR_REG_LSL(rd,rn,rm,shift_imm) EOP_ORR_REG(0,rn,rd,shift_imm,A_AM1_LSL,rm)
	91	#define EOP_ORR_REG_LSR(rd,rn,rm,shift_imm) EOP_ORR_REG(0,rn,rd,shift_imm,A_AM1_LSR,rm)
	92	#define EOP_ORR_REG_ASR(rd,rn,rm,shift_imm) EOP_ORR_REG(0,rn,rd,shift_imm,A_AM1_ASR,rm)
	93	#define EOP_ORR_REG_ROR(rd,rn,rm,shift_imm) EOP_ORR_REG(0,rn,rd,shift_imm,A_AM1_ROR,rm)
	94
	95	#define EOP_ADD_REG_SIMPLE(rd,rm) EOP_ADD_REG(0,rd,rd,0,A_AM1_LSL,rm)
	96	#define EOP_ADD_REG_LSL(rd,rn,rm,shift_imm) EOP_ADD_REG(0,rn,rd,shift_imm,A_AM1_LSL,rm)
	97	#define EOP_ADD_REG_LSR(rd,rn,rm,shift_imm) EOP_ADD_REG(0,rn,rd,shift_imm,A_AM1_LSR,rm)
f48f5e3b	98
b9c1d012	99	#define EOP_TST_REG_SIMPLE(rn,rm) EOP_TST_REG( rn, 0,A_AM1_LSL,rm)
b9c1d012	100
89fea1e9	101	#define EOP_MOV_REG2_LSL(rd, rm,rs) EOP_MOV_REG2(0, rd,rs,A_AM1_LSL,rm)
	102	#define EOP_MOV_REG2_ROR(rd, rm,rs) EOP_MOV_REG2(0, rd,rs,A_AM1_ROR,rm)
	103	#define EOP_ADD_REG2_LSL(rd,rn,rm,rs) EOP_ADD_REG2(0,rn,rd,rs,A_AM1_LSL,rm)
	104	#define EOP_SUB_REG2_LSL(rd,rn,rm,rs) EOP_SUB_REG2(0,rn,rd,rs,A_AM1_LSL,rm)
	105
f48f5e3b	106	/* addressing mode 2 */
f48f5e3b	107	#define EOP_C_AM2_IMM(cond,u,b,l,rn,rd,offset_12) \
5c129565	108	EMIT(((cond)<<28) \| 0x05000000 \| ((u)<<23) \| ((b)<<22) \| ((l)<<20) \| ((rn)<<16) \| ((rd)<<12) \| (offset_12))
5c129565	109
f48f5e3b	110	/* addressing mode 3 */
ede7220f	111	#define EOP_C_AM3(cond,u,r,l,rn,rd,s,h,immed_reg) \
	112	EMIT(((cond)<<28) \| 0x01000090 \| ((u)<<23) \| ((r)<<22) \| ((l)<<20) \| ((rn)<<16) \| ((rd)<<12) \| \
	113	((s)<<6) \| ((h)<<5) \| (immed_reg))
	114
	115	#define EOP_C_AM3_IMM(cond,u,l,rn,rd,s,h,offset_8) EOP_C_AM3(cond,u,1,l,rn,rd,s,h,(((offset_8)&0xf0)<<4)\|((offset_8)&0xf))
	116
	117	#define EOP_C_AM3_REG(cond,u,l,rn,rd,s,h,rm) EOP_C_AM3(cond,u,0,l,rn,rd,s,h,rm)
f48f5e3b	118
	119	/* ldr and str */
	120	#define EOP_LDR_IMM( rd,rn,offset_12) EOP_C_AM2_IMM(A_COND_AL,1,0,1,rn,rd,offset_12)
	121	#define EOP_LDR_NEGIMM(rd,rn,offset_12) EOP_C_AM2_IMM(A_COND_AL,0,0,1,rn,rd,offset_12)
	122	#define EOP_LDR_SIMPLE(rd,rn) EOP_C_AM2_IMM(A_COND_AL,1,0,1,rn,rd,0)
	123	#define EOP_STR_IMM( rd,rn,offset_12) EOP_C_AM2_IMM(A_COND_AL,1,0,0,rn,rd,offset_12)
	124	#define EOP_STR_SIMPLE(rd,rn) EOP_C_AM2_IMM(A_COND_AL,1,0,0,rn,rd,0)
	125
5d817c91	126	#define EOP_LDRH_IMM( rd,rn,offset_8) EOP_C_AM3_IMM(A_COND_AL,1,1,rn,rd,0,1,offset_8)
5d817c91	127	#define EOP_LDRH_SIMPLE(rd,rn) EOP_C_AM3_IMM(A_COND_AL,1,1,rn,rd,0,1,0)
ede7220f	128	#define EOP_LDRH_REG( rd,rn,rm) EOP_C_AM3_REG(A_COND_AL,1,1,rn,rd,0,1,rm)
5d817c91	129	#define EOP_STRH_IMM( rd,rn,offset_8) EOP_C_AM3_IMM(A_COND_AL,1,0,rn,rd,0,1,offset_8)
5d817c91	130	#define EOP_STRH_SIMPLE(rd,rn) EOP_C_AM3_IMM(A_COND_AL,1,0,rn,rd,0,1,0)
d5276282	131	#define EOP_STRH_REG( rd,rn,rm) EOP_C_AM3_REG(A_COND_AL,1,0,rn,rd,0,1,rm)
5c129565	132
	133	/* ldm and stm */
	134	#define EOP_XXM(cond,p,u,s,w,l,rn,list) \
	135	EMIT(((cond)<<28) \| (1<<27) \| ((p)<<24) \| ((u)<<23) \| ((s)<<22) \| ((w)<<21) \| ((l)<<20) \| ((rn)<<16) \| (list))
	136
	137	#define EOP_STMFD_ST(list) EOP_XXM(A_COND_AL,1,0,0,1,0,13,list)
	138	#define EOP_LDMFD_ST(list) EOP_XXM(A_COND_AL,0,1,0,1,1,13,list)
	139
	140	/* branches */
	141	#define EOP_C_BX(cond,rm) \
	142	EMIT(((cond)<<28) \| 0x012fff10 \| (rm))
	143
	144	#define EOP_BX(rm) EOP_C_BX(A_COND_AL,rm)
	145
e807ac75	146	#define EOP_C_B(cond,l,signed_immed_24) \
	147	EMIT(((cond)<<28) \| 0x0a000000 \| ((l)<<24) \| (signed_immed_24))
	148
	149	#define EOP_B( signed_immed_24) EOP_C_B(A_COND_AL,0,signed_immed_24)
	150	#define EOP_BL(signed_immed_24) EOP_C_B(A_COND_AL,1,signed_immed_24)
	151
d274c33b	152	/* misc */
	153	#define EOP_C_MUL(cond,s,rd,rs,rm) \
	154	EMIT(((cond)<<28) \| ((s)<<20) \| ((rd)<<16) \| ((rs)<<8) \| 0x90 \| (rm))
	155
	156	#define EOP_MUL(rd,rm,rs) EOP_C_MUL(A_COND_AL,0,rd,rs,rm) // note: rd != rm
	157
bad5731d	158	#define EOP_C_MRS(cond,rd) \
89fea1e9	159	EMIT(((cond)<<28) \| 0x010f0000 \| ((rd)<<12))
5c129565	160
6e39239f	161	#define EOP_C_MSR_IMM(cond,ror2,imm) \
	162	EMIT(((cond)<<28) \| 0x0328f000 \| ((ror2)<<8) \| (imm)) // cpsr_f
	163
	164	#define EOP_C_MSR_REG(cond,rm) \
	165	EMIT(((cond)<<28) \| 0x0128f000 \| (rm)) // cpsr_f
	166
	167	#define EOP_MRS(rd) EOP_C_MRS(A_COND_AL,rd)
	168	#define EOP_MSR_IMM(ror2,imm) EOP_C_MSR_IMM(A_COND_AL,ror2,imm)
	169	#define EOP_MSR_REG(rm) EOP_C_MSR_REG(A_COND_AL,rm)
bad5731d	170
bad5731d	171
65c75cb0	172	static void emith_op_imm(int cond, int op, int r, unsigned int imm)
5c129565	173	{
553c3eaa	174	int ror2, rn = r;
553c3eaa	175	u32 v;
65c75cb0	176
553c3eaa	177	if (op == A_OP_MOV)
	178	rn = 0;
	179	else if (imm == 0)
65c75cb0	180	return;
65c75cb0	181
553c3eaa	182	for (v = imm, ror2 = 0; v != 0 \|\| op == A_OP_MOV; v >>= 8, ror2 -= 8/2) {
	183	/* shift down to get 'best' rot2 */
	184	for (; v && !(v & 3); v >>= 2)
	185	ror2--;
65c75cb0	186
553c3eaa	187	EOP_C_DOP_IMM(cond, op, 0, rn, r, ror2 & 0x0f, v & 0xff);
	188
	189	if (op == A_OP_MOV) {
	190	op = A_OP_ORR;
	191	rn = r;
	192	}
	193	}
259ed0ea	194	}
259ed0ea	195
65c75cb0	196	#define is_offset_24(val) \
65c75cb0	197	((val) >= (int)0xff000000 && (val) <= 0x00ffffff)
5c129565	198
65c75cb0	199	static int emith_xbranch(int cond, void *target, int is_call)
5c129565	200	{
65c75cb0	201	int val = (u32 )target - (u32 )tcache_ptr - 2;
f8af9634	202	int direct = is_offset_24(val);
65c75cb0	203	u32 start_ptr = (u32 )tcache_ptr;
259ed0ea	204
f8af9634	205	if (direct)
	206	{
	207	EOP_C_B(cond,is_call,val & 0xffffff); // b, bl target
	208	}
	209	else
	210	{
	211	#ifdef __EPOC32__
	212	// elprintf(EL_SVP, "emitting indirect jmp %08x->%08x", tcache_ptr, target);
	213	if (is_call)
	214	EOP_ADD_IMM(14,15,0,8); // add lr,pc,#8
	215	EOP_C_AM2_IMM(cond,1,0,1,15,15,0); // ldrcc pc,[pc]
	216	EOP_MOV_REG_SIMPLE(15,15); // mov pc, pc
	217	EMIT((u32)target);
	218	#else
	219	// should never happen
	220	elprintf(EL_STATUS\|EL_SVP\|EL_ANOMALY, "indirect jmp %08x->%08x", target, tcache_ptr);
	221	exit(1);
	222	#endif
	223	}
	224
65c75cb0	225	return (u32 *)tcache_ptr - start_ptr;
5c129565	226	}
5c129565	227
5c129565	228
65c75cb0	229	#define EMITH_CONDITIONAL(code, is_nonzero) { \
	230	u32 val, cond, *ptr; \
	231	cond = (is_nonzero) ? A_COND_NE : A_COND_EQ; \
	232	ptr = (void *)tcache_ptr; \
	233	tcache_ptr = (void *)(ptr + 1); \
	234	code; \
	235	val = (u32 *)tcache_ptr - (ptr + 2); \
	236	EMIT_PTR(ptr, ((cond)<<28) \| 0x0a000000 \| (val & 0xffffff)); \
	237	}
	238
	239	#define emith_move_r_r(dst, src) \
	240	EOP_MOV_REG_SIMPLE(dst, src)
	241
	242	#define emith_move_r_imm(r, imm) \
	243	emith_op_imm(A_COND_AL, A_OP_MOV, r, imm)
	244
	245	#define emith_add_r_imm(r, imm) \
	246	emith_op_imm(A_COND_AL, A_OP_ADD, r, imm)
	247
	248	#define emith_sub_r_imm(r, imm) \
	249	emith_op_imm(A_COND_AL, A_OP_SUB, r, imm)
	250
	251	#define emith_ctx_read(r, offs) \
	252	EOP_LDR_IMM(r, CONTEXT_REG, offs)
	253
	254	#define emith_ctx_write(r, offs) \
	255	EOP_STR_IMM(r, CONTEXT_REG, offs)
	256
65c75cb0	257	// upto 4 args
	258	#define emith_pass_arg_r(arg, reg) \
	259	EOP_MOV_REG_SIMPLE(arg, reg)
	260
	261	#define emith_pass_arg_imm(arg, imm) \
	262	emith_move_r_imm(arg, imm)
	263
	264	#define emith_call_cond(cond, target) \
	265	emith_xbranch(cond, target, 1)
	266
	267	#define emith_jump_cond(cond, target) \
	268	emith_xbranch(cond, target, 0)
	269
	270	#define emith_call(target) \
	271	emith_call_cond(A_COND_AL, target)
	272
	273	#define emith_jump(target) \
	274	emith_jump_cond(A_COND_AL, target)
	275
	276	/* SH2 drc specific */
	277	#define emith_test_t() { \
c18edb34	278	int r = rcache_get_reg(SHR_SR, RC_GR_READ); \
65c75cb0	279	EOP_TST_IMM(r, 0, 1); \
	280	}
	281
	282