[picodrive.git] / cpu / sh2 / compiler.c

/*
 * vim:shiftwidth=2:expandtab
 */
#include <stdio.h>
#include <stdlib.h>
#include <assert.h>

#include "../../pico/pico_int.h"
#include "sh2.h"
#include "compiler.h"
#include "../drc/cmn.h"

#ifndef DRC_DEBUG
#define DRC_DEBUG 0
#endif

#define dbg(l,...) { \
  if ((l) & DRC_DEBUG) \
    elprintf(EL_STATUS, ##__VA_ARGS__); \
}

#if DRC_DEBUG
#include "mame/sh2dasm.h"
#include <platform/linux/host_dasm.h>
static int insns_compiled, hash_collisions, host_insn_count;
#endif
#if (DRC_DEBUG & 2)
static u8 *tcache_dsm_ptrs[3];
static char sh2dasm_buff[64];
#define do_host_disasm(tcid) \
  host_dasm(tcache_dsm_ptrs[tcid], tcache_ptr - tcache_dsm_ptrs[tcid]); \
  tcache_dsm_ptrs[tcid] = tcache_ptr
#else
#define do_host_disasm(x)
#endif

#define BLOCK_CYCLE_LIMIT 100
#define MAX_BLOCK_SIZE (BLOCK_CYCLE_LIMIT * 6 * 6)

// we have 3 translation cache buffers, split from one drc/cmn buffer.
// BIOS shares tcache with data array because it's only used for init
// and can be discarded early
static const int tcache_sizes[3] = {
  DRC_TCACHE_SIZE * 6 / 8, // ROM, DRAM
  DRC_TCACHE_SIZE / 8, // BIOS, data array in master sh2
  DRC_TCACHE_SIZE / 8, // ... slave
};

static u8 *tcache_bases[3];
static u8 *tcache_ptrs[3];

// ptr for code emiters
static u8 *tcache_ptr;

#ifdef ARM
#include "../drc/emit_arm.c"

static const int reg_map_g2h[] = {
	-1, -1, -1, -1,
	-1, -1, -1, -1,
	-1, -1, -1, -1,
	-1, -1, -1, -1,
	-1, -1, -1, -1,
	-1, -1, -1, -1,
};

#else
#include "../drc/emit_x86.c"

static const int reg_map_g2h[] = {
	-1, -1, -1, -1,
	-1, -1, -1, -1,
	-1, -1, -1, -1,
	-1, -1, -1, -1,
	-1, -1, -1, -1,
	-1, -1, -1, -1,
};

#endif

typedef enum {
  SHR_R0 = 0, SHR_R15 = 15,
  SHR_PC,  SHR_PPC, SHR_PR,   SHR_SR,
  SHR_GBR, SHR_VBR, SHR_MACH, SHR_MACL,
} sh2_reg_e;

typedef struct block_desc_ {
  u32 addr;			// SH2 PC address
  u32 end_addr;                 // TODO rm?
  void *tcache_ptr;		// translated block for above PC
  struct block_desc_ *next;     // next block with the same PC hash
#if (DRC_DEBUG & 1)
  int refcount;
#endif
} block_desc;

static const int block_max_counts[3] = {
  4*1024,
  256,
  256,
};
static block_desc *block_tables[3];
static int block_counts[3];

// ROM hash table
#define MAX_HASH_ENTRIES 1024
#define HASH_MASK (MAX_HASH_ENTRIES - 1)
static void **hash_table;

extern void sh2_drc_entry(SH2 *sh2, void *block);
extern void sh2_drc_exit(void);

// tmp
extern void __attribute__((regparm(2))) sh2_do_op(SH2 *sh2, int opcode);
static void __attribute__((regparm(1))) sh2_test_irq(SH2 *sh2);

static void flush_tcache(int tcid)
{
  printf("tcache #%d flush! (%d/%d, bds %d/%d)\n", tcid,
    tcache_ptrs[tcid] - tcache_bases[tcid], tcache_sizes[tcid],
    block_counts[tcid], block_max_counts[tcid]);

  block_counts[tcid] = 0;
  tcache_ptrs[tcid] = tcache_bases[tcid];
  if (tcid == 0) { // ROM, RAM
    memset(hash_table, 0, sizeof(hash_table[0]) * MAX_HASH_ENTRIES);
    memset(Pico32xMem->drcblk_ram, 0, sizeof(Pico32xMem->drcblk_ram));
  }
  else
    memset(Pico32xMem->drcblk_da[tcid - 1], 0, sizeof(Pico32xMem->drcblk_da[0]));
#if (DRC_DEBUG & 2)
  tcache_dsm_ptrs[tcid] = tcache_bases[tcid];
#endif
}

static void *dr_find_block(block_desc *tab, u32 addr)
{
  for (tab = tab->next; tab != NULL; tab = tab->next)
    if (tab->addr == addr)
      break;

  if (tab != NULL)
    return tab->tcache_ptr;

  printf("block miss for %08x\n", addr);
  return NULL;
}

static block_desc *dr_add_block(u32 addr, int tcache_id, int *blk_id)
{
  int *bcount = &block_counts[tcache_id];
  block_desc *bd;

  if (*bcount >= block_max_counts[tcache_id])
    return NULL;

  bd = &block_tables[tcache_id][*bcount];
  bd->addr = addr;
  bd->tcache_ptr = tcache_ptr;
  *blk_id = *bcount;
  (*bcount)++;

  return bd;
}

#define HASH_FUNC(hash_tab, addr) \
  ((block_desc **)(hash_tab))[(addr) & HASH_MASK]

// ---------------------------------------------------------------

static void emit_move_r_imm32(sh2_reg_e dst, u32 imm)
{
  int host_dst = reg_map_g2h[dst];
  int tmp = 0;

  if (host_dst != -1)
    tmp = host_dst;
  emith_move_r_imm(tmp, imm);
  if (host_dst == -1)
    emith_ctx_write(tmp, dst * 4);
}

static void emit_move_r_r(sh2_reg_e dst, sh2_reg_e src)
{
  int host_dst = reg_map_g2h[dst], host_src = reg_map_g2h[src];
  int tmp = 0;

  if (host_dst != -1 && host_src != -1) {
    emith_move_r_r(host_dst, host_src);
    return;
  }

  if (host_src != -1)
    tmp = host_src;
  if (host_dst != -1)
    tmp = host_dst;

  if (host_src == -1)
    emith_ctx_read(tmp, src * 4);
  if (host_dst == -1)
    emith_ctx_write(tmp, dst * 4);
}

static void emit_braf(sh2_reg_e reg, u32 pc)
{
  int host_reg = reg_map_g2h[reg];
  if (host_reg == -1) {
    emith_ctx_read(0, reg * 4);
  } else
    emith_move_r_r(0, host_reg);
  emith_add_r_imm(0, pc);

  emith_ctx_write(0, SHR_PPC * 4);
}

/*
static int sh2_translate_op4(int op)
{
  switch (op & 0x000f)
  {
  case 0x0b:
  default:
    emith_pass_arg(2, sh2, op);
    emith_call(sh2_do_op);
    break;
  }

  return 0;
}
*/

#define DELAYED_OP \
  delayed_op = 2

#define CHECK_UNHANDLED_BITS(mask) { \
  if ((op & (mask)) != 0) \
    goto default_; \
}

static void *sh2_translate(SH2 *sh2, block_desc *other_block)
{
  void *block_entry;
  block_desc *this_block;
  unsigned int pc = sh2->pc;
  int op, delayed_op = 0, test_irq = 0;
  int tcache_id = 0, blkid = 0;
  int cycles = 0;
  u32 tmp, tmp2;

  // validate PC
  tmp = sh2->pc >> 29;
  if ((tmp != 0 && tmp != 1 && tmp != 6) || sh2->pc == 0) {
    printf("invalid PC, aborting: %08x\n", sh2->pc);
    // FIXME: be less destructive
    exit(1);
  }

  if ((sh2->pc & 0xe0000000) == 0xc0000000 || (sh2->pc & ~0xfff) == 0) {
    // data_array, BIOS have separate tcache (shared)
    tcache_id = 1 + sh2->is_slave;
  }

  tcache_ptr = tcache_ptrs[tcache_id];
  this_block = dr_add_block(pc, tcache_id, &blkid);

  tmp = tcache_ptr - tcache_bases[tcache_id];
  if (tmp > tcache_sizes[tcache_id] - MAX_BLOCK_SIZE || this_block == NULL) {
    flush_tcache(tcache_id);
    tcache_ptr = tcache_ptrs[tcache_id];
    other_block = NULL; // also gone too due to flush
    this_block = dr_add_block(pc, tcache_id, &blkid);
  }

  this_block->next = other_block;
  if ((sh2->pc & 0xc6000000) == 0x02000000) // ROM
    HASH_FUNC(hash_table, pc) = this_block;

  block_entry = tcache_ptr;
#if (DRC_DEBUG & 1)
  printf("== %csh2 block #%d,%d %08x -> %p\n", sh2->is_slave ? 's' : 'm',
    tcache_id, block_counts[tcache_id], pc, block_entry);
  if (other_block != NULL) {
    printf(" hash collision with %08x\n", other_block->addr);
    hash_collisions++;
  }
#endif

  while (cycles < BLOCK_CYCLE_LIMIT || delayed_op)
  {
    if (delayed_op > 0)
      delayed_op--;

    op = p32x_sh2_read16(pc, sh2);

#if (DRC_DEBUG & 3)
    insns_compiled++;
#if (DRC_DEBUG & 2)
    DasmSH2(sh2dasm_buff, pc, op);
    printf("%08x %04x %s\n", pc, op, sh2dasm_buff);
#endif
#endif

    pc += 2;
    cycles++;

    switch ((op >> 12) & 0x0f)
    {
    case 0x00:
      switch (op & 0x0f) {
      case 0x03:
        CHECK_UNHANDLED_BITS(0xd0);
        // BRAF Rm    0000mmmm00100011
        // BSRF Rm    0000mmmm00000011
        DELAYED_OP;
        if (!(op & 0x20))
          emit_move_r_imm32(SHR_PR, pc + 2);
        emit_braf((op >> 8) & 0x0f, pc + 2);
        cycles++;
        goto end_op;
      case 0x09:
        CHECK_UNHANDLED_BITS(0xf0);
        // NOP        0000000000001001
        goto end_op;
      case 0x0b:
        CHECK_UNHANDLED_BITS(0xd0);
        DELAYED_OP;
        if (!(op & 0x20)) {
          // RTS        0000000000001011
          emit_move_r_r(SHR_PPC, SHR_PR);
          cycles++;
        } else {
          // RTE        0000000000101011
          //emit_move_r_r(SHR_PC, SHR_PR);
          emit_move_r_imm32(SHR_PC, pc - 2);
          emith_pass_arg_r(0, CONTEXT_REG);
          emith_pass_arg_imm(1, op);
          emith_call(sh2_do_op);
          emit_move_r_r(SHR_PPC, SHR_PC);
          test_irq = 1;
          cycles += 3;
        }
        goto end_op;
      }
      goto default_;

    case 0x04:
      switch (op & 0x0f) {
      case 0x07:
        if ((op & 0xf0) != 0)
          goto default_;
        // LDC.L @Rm+,SR  0100mmmm00000111
        test_irq = 1;
        goto default_;
      case 0x0b:
        if ((op & 0xd0) != 0)
          goto default_;
        // JMP  @Rm   0100mmmm00101011
        // JSR  @Rm   0100mmmm00001011
        DELAYED_OP;
        if (!(op & 0x20))
          emit_move_r_imm32(SHR_PR, pc + 2);
        emit_move_r_r(SHR_PPC, (op >> 8) & 0x0f);
        cycles++;
        goto end_op;
      case 0x0e:
        if ((op & 0xf0) != 0)
          goto default_;
        // LDC Rm,SR  0100mmmm00001110
        test_irq = 1;
        goto default_;
      }
      goto default_;

    case 0x08:
      switch (op & 0x0f00) {
      // BT/S label 10001101dddddddd
      case 0x0d00:
      // BF/S label 10001111dddddddd
      case 0x0f00:
        DELAYED_OP;
        cycles--;
        // fallthrough
      // BT   label 10001001dddddddd
      case 0x0900:
      // BF   label 10001011dddddddd
      case 0x0b00:
        tmp = ((signed int)(op << 24) >> 23);
        tmp2 = delayed_op ? SHR_PPC : SHR_PC;
        emit_move_r_imm32(tmp2, pc + (delayed_op ? 2 : 0));
        emith_test_t();
        EMITH_CONDITIONAL(emit_move_r_imm32(tmp2, pc + tmp + 2), (op & 0x0200) ? 1 : 0);
        cycles += 2;
        if (!delayed_op)
          goto end_block;
        goto end_op;
      }
      goto default_;

    case 0x0a:
      // BRA  label 1010dddddddddddd
      DELAYED_OP;
    do_bra:
      tmp = ((signed int)(op << 20) >> 19);
      emit_move_r_imm32(SHR_PPC, pc + tmp + 2);
      cycles++;
      break;

    case 0x0b:
      // BSR  label 1011dddddddddddd
      DELAYED_OP;
      emit_move_r_imm32(SHR_PR, pc + 2);
      goto do_bra;

    default:
    default_:
      emit_move_r_imm32(SHR_PC, pc - 2);
      emith_pass_arg_r(0, CONTEXT_REG);
      emith_pass_arg_imm(1, op);
      emith_call(sh2_do_op);
      break;
    }

end_op:
    if (delayed_op == 1)
      emit_move_r_r(SHR_PC, SHR_PPC);

    if (test_irq && delayed_op != 2) {
      emith_pass_arg_r(0, CONTEXT_REG);
      emith_call(sh2_test_irq);
      break;
    }
    if (delayed_op == 1)
      break;

    do_host_disasm(tcache_id);
  }

end_block:
  this_block->end_addr = pc;

  // mark memory blocks as containing compiled code
  if ((sh2->pc & 0xe0000000) == 0xc0000000 || (sh2->pc & ~0xfff) == 0) {
    // data array, BIOS
    u16 *drcblk = Pico32xMem->drcblk_da[sh2->is_slave];
    tmp =  (this_block->addr & 0xfff) >> SH2_DRCBLK_DA_SHIFT;
    tmp2 = (this_block->end_addr & 0xfff) >> SH2_DRCBLK_DA_SHIFT;
    Pico32xMem->drcblk_da[sh2->is_slave][tmp] = (blkid << 1) | 1;
    for (++tmp; tmp < tmp2; tmp++) {
      if (drcblk[tmp])
        break; // dont overwrite overlay block
      drcblk[tmp] = blkid << 1;
    }
  }
  else if ((this_block->addr & 0xc7fc0000) == 0x06000000) { // DRAM
    tmp =  (this_block->addr & 0x3ffff) >> SH2_DRCBLK_RAM_SHIFT;
    tmp2 = (this_block->end_addr & 0x3ffff) >> SH2_DRCBLK_RAM_SHIFT;
    Pico32xMem->drcblk_ram[tmp] = (blkid << 1) | 1;
    for (++tmp; tmp < tmp2; tmp++) {
      if (Pico32xMem->drcblk_ram[tmp])
        break;
      Pico32xMem->drcblk_ram[tmp] = blkid << 1;
    }
  }

  if (reg_map_g2h[SHR_SR] == -1) {
    emith_ctx_sub(cycles << 12, SHR_SR * 4);
  } else
    emith_sub_r_imm(reg_map_g2h[SHR_SR], cycles << 12);
  emith_jump(sh2_drc_exit);
  tcache_ptrs[tcache_id] = tcache_ptr;

  do_host_disasm(tcache_id);
  dbg(1, " block #%d,%d tcache %d/%d, insns %d -> %d %.3f",
    tcache_id, block_counts[tcache_id],
    tcache_ptr - tcache_bases[tcache_id], tcache_sizes[tcache_id],
    insns_compiled, host_insn_count, (double)host_insn_count / insns_compiled);
  if ((sh2->pc & 0xc6000000) == 0x02000000) // ROM
    dbg(1, "  hash collisions %d/%d", hash_collisions, block_counts[tcache_id]);
  return block_entry;
/*
unimplemented:
  // last op
  do_host_disasm(tcache_id);
  exit(1);
*/
}

void __attribute__((noinline)) sh2_drc_dispatcher(SH2 *sh2)
{
  while (((signed int)sh2->sr >> 12) > 0)
  {
    void *block = NULL;
    block_desc *bd = NULL;

    // FIXME: must avoid doing it so often..
    sh2_test_irq(sh2);

    // we have full block id tables for data_array and RAM
    // BIOS goes to data_array table too
    if ((sh2->pc & 0xff000000) == 0xc0000000 || (sh2->pc & ~0xfff) == 0) {
      int blkid = Pico32xMem->drcblk_da[sh2->is_slave][(sh2->pc & 0xfff) >> SH2_DRCBLK_DA_SHIFT];
      if (blkid & 1) {
        bd = &block_tables[1 + sh2->is_slave][blkid >> 1];
        block = bd->tcache_ptr;
      }
    }
    // RAM
    else if ((sh2->pc & 0xc6000000) == 0x06000000) {
      int blkid = Pico32xMem->drcblk_ram[(sh2->pc & 0x3ffff) >> SH2_DRCBLK_RAM_SHIFT];
      if (blkid & 1) {
        bd = &block_tables[0][blkid >> 1];
        block = bd->tcache_ptr;
      }
    }
    // ROM
    else if ((sh2->pc & 0xc6000000) == 0x02000000) {
      bd = HASH_FUNC(hash_table, sh2->pc);

      if (bd != NULL) {
        if (bd->addr == sh2->pc)
          block = bd->tcache_ptr;
        else
          block = dr_find_block(bd, sh2->pc);
      }
    }

    if (block == NULL)
      block = sh2_translate(sh2, bd);

    dbg(4, "= %csh2 enter %08x %p, c=%d", sh2->is_slave ? 's' : 'm',
      sh2->pc, block, (signed int)sh2->sr >> 12);
#if (DRC_DEBUG & 1)
    if (bd != NULL)
      bd->refcount++;
#endif
    sh2_drc_entry(sh2, block);
  }
}

static void sh2_smc_rm_block(u16 *drcblk, u16 *p, block_desc *btab, u32 a)
{
  u16 id = *p >> 1;
  block_desc *bd = btab + id;

  dbg(1, "  killing block %08x", bd->addr);
  bd->addr = bd->end_addr = 0;

  while (p > drcblk && (p[-1] >> 1) == id)
    p--;

  // check for possible overlay block
  if (p > 0 && p[-1] != 0) {
    bd = btab + (p[-1] >> 1);
    if (bd->addr <= a && a < bd->end_addr)
      sh2_smc_rm_block(drcblk, p - 1, btab, a);
  }

  do {
    *p++ = 0;
  }
  while ((*p >> 1) == id);
}

void sh2_drc_wcheck_ram(unsigned int a, int val, int cpuid)
{
  u16 *drcblk = Pico32xMem->drcblk_ram;
  u16 *p = drcblk + ((a & 0x3ffff) >> SH2_DRCBLK_RAM_SHIFT);

  dbg(1, "%csh2 smc check @%08x", cpuid ? 's' : 'm', a);
  sh2_smc_rm_block(drcblk, p, block_tables[0], a);
}

void sh2_drc_wcheck_da(unsigned int a, int val, int cpuid)
{
  u16 *drcblk = Pico32xMem->drcblk_da[cpuid];
  u16 *p = drcblk + ((a & 0xfff) >> SH2_DRCBLK_DA_SHIFT);

  dbg(1, "%csh2 smc check @%08x", cpuid ? 's' : 'm', a);
  sh2_smc_rm_block(drcblk, p, block_tables[1 + cpuid], a);
}

void sh2_execute(SH2 *sh2, int cycles)
{
  sh2->cycles_aim += cycles;
  cycles = sh2->cycles_aim - sh2->cycles_done;

  // cycles are kept in SHR_SR unused bits (upper 20)
  sh2->sr &= 0x3f3;
  sh2->sr |= cycles << 12;
  sh2_drc_dispatcher(sh2);

  sh2->cycles_done += cycles - ((signed int)sh2->sr >> 12);
}

static void __attribute__((regparm(1))) sh2_test_irq(SH2 *sh2)
{
  if (sh2->pending_level > ((sh2->sr >> 4) & 0x0f))
  {
    if (sh2->pending_irl > sh2->pending_int_irq)
      sh2_do_irq(sh2, sh2->pending_irl, 64 + sh2->pending_irl/2);
    else {
      sh2_do_irq(sh2, sh2->pending_int_irq, sh2->pending_int_vector);
      sh2->pending_int_irq = 0; // auto-clear
      sh2->pending_level = sh2->pending_irl;
    }
  }
}

#if (DRC_DEBUG & 1)
static void block_stats(void)
{
  int c, b, i, total = 0;

  for (b = 0; b < ARRAY_SIZE(block_tables); b++)
    for (i = 0; i < block_counts[b]; i++)
      if (block_tables[b][i].addr != 0)
        total += block_tables[b][i].refcount;

  for (c = 0; c < 10; c++) {
    block_desc *blk, *maxb = NULL;
    int max = 0;
    for (b = 0; b < ARRAY_SIZE(block_tables); b++) {
      for (i = 0; i < block_counts[b]; i++) {
        blk = &block_tables[b][i];
        if (blk->addr != 0 && blk->refcount > max) {
          max = blk->refcount;
          maxb = blk;
        }
      }
    }
    if (maxb == NULL)
      break;
    printf("%08x %9d %2.3f%%\n", maxb->addr, maxb->refcount,
      (double)maxb->refcount / total * 100.0);
    maxb->refcount = 0;
  }
}
#endif

int sh2_drc_init(SH2 *sh2)
{
  if (block_tables[0] == NULL) {
    int i, cnt;
    cnt = block_max_counts[0] + block_max_counts[1] + block_max_counts[2];
    block_tables[0] = calloc(cnt, sizeof(*block_tables[0]));
    if (block_tables[0] == NULL)
      return -1;

    memset(block_counts, 0, sizeof(block_counts));
    tcache_bases[0] = tcache_ptrs[0] = tcache;

    for (i = 1; i < ARRAY_SIZE(block_tables); i++) {
      block_tables[i] = block_tables[i - 1] + block_max_counts[i - 1];
      tcache_bases[i] = tcache_ptrs[i] = tcache_bases[i - 1] + tcache_sizes[i - 1];
    }

#if (DRC_DEBUG & 2)
    for (i = 0; i < ARRAY_SIZE(block_tables); i++)
      tcache_dsm_ptrs[i] = tcache_bases[i];
#endif
#if (DRC_DEBUG & 1)
    hash_collisions = 0;
#endif
  }

  if (hash_table == NULL) {
    hash_table = calloc(sizeof(hash_table[0]), MAX_HASH_ENTRIES);
    if (hash_table == NULL)
      return -1;
  }

  return 0;
}

void sh2_drc_finish(SH2 *sh2)
{
  if (block_tables[0] != NULL) {
#if (DRC_DEBUG & 1)
    block_stats();
#endif
    free(block_tables[0]);
    memset(block_tables, 0, sizeof(block_tables));
  }

  if (hash_table != NULL) {
    free(hash_table);
    hash_table = NULL;
  }
}
Commit	Line	Data
e898de13	1	/*
	2	* vim:shiftwidth=2:expandtab
	3	*/
679af8a3	4	#include <stdio.h>
	5	#include <stdlib.h>
	6	#include <assert.h>
41397701	7
f4bb5d6b	8	#include "../../pico/pico_int.h"
679af8a3	9	#include "sh2.h"
	10	#include "compiler.h"
	11	#include "../drc/cmn.h"
	12
e898de13	13	#ifndef DRC_DEBUG
	14	#define DRC_DEBUG 0
	15	#endif
	16
f4bb5d6b	17	#define dbg(l,...) { \
	18	if ((l) & DRC_DEBUG) \
	19	elprintf(EL_STATUS, ##__VA_ARGS__); \
	20	}
	21
e898de13	22	#if DRC_DEBUG
	23	#include "mame/sh2dasm.h"
	24	#include <platform/linux/host_dasm.h>
	25	static int insns_compiled, hash_collisions, host_insn_count;
	26	#endif
	27	#if (DRC_DEBUG & 2)
f4bb5d6b	28	static u8 *tcache_dsm_ptrs[3];
e898de13	29	static char sh2dasm_buff[64];
f4bb5d6b	30	#define do_host_disasm(tcid) \
	31	host_dasm(tcache_dsm_ptrs[tcid], tcache_ptr - tcache_dsm_ptrs[tcid]); \
	32	tcache_dsm_ptrs[tcid] = tcache_ptr
	33	#else
	34	#define do_host_disasm(x)
e898de13	35	#endif
e898de13	36
679af8a3	37	#define BLOCK_CYCLE_LIMIT 100
f4bb5d6b	38	#define MAX_BLOCK_SIZE (BLOCK_CYCLE_LIMIT * 6 * 6)
	39
	40	// we have 3 translation cache buffers, split from one drc/cmn buffer.
	41	// BIOS shares tcache with data array because it's only used for init
	42	// and can be discarded early
	43	static const int tcache_sizes[3] = {
	44	DRC_TCACHE_SIZE * 6 / 8, // ROM, DRAM
	45	DRC_TCACHE_SIZE / 8, // BIOS, data array in master sh2
	46	DRC_TCACHE_SIZE / 8, // ... slave
	47	};
679af8a3	48
f4bb5d6b	49	static u8 *tcache_bases[3];
	50	static u8 *tcache_ptrs[3];
	51
	52	// ptr for code emiters
	53	static u8 *tcache_ptr;
e898de13	54
65c75cb0	55	#ifdef ARM
	56	#include "../drc/emit_arm.c"
	57
	58	static const int reg_map_g2h[] = {
	59	-1, -1, -1, -1,
	60	-1, -1, -1, -1,
	61	-1, -1, -1, -1,
	62	-1, -1, -1, -1,
	63	-1, -1, -1, -1,
	64	-1, -1, -1, -1,
	65	};
	66
	67	#else
e898de13	68	#include "../drc/emit_x86.c"
e898de13	69
65c75cb0	70	static const int reg_map_g2h[] = {
	71	-1, -1, -1, -1,
	72	-1, -1, -1, -1,
	73	-1, -1, -1, -1,
	74	-1, -1, -1, -1,
	75	-1, -1, -1, -1,
	76	-1, -1, -1, -1,
	77	};
	78
	79	#endif
	80
679af8a3	81	typedef enum {
	82	SHR_R0 = 0, SHR_R15 = 15,
	83	SHR_PC, SHR_PPC, SHR_PR, SHR_SR,
	84	SHR_GBR, SHR_VBR, SHR_MACH, SHR_MACL,
	85	} sh2_reg_e;
	86
	87	typedef struct block_desc_ {
	88	u32 addr; // SH2 PC address
f4bb5d6b	89	u32 end_addr; // TODO rm?
679af8a3	90	void *tcache_ptr; // translated block for above PC
f4bb5d6b	91	struct block_desc_ *next; // next block with the same PC hash
	92	#if (DRC_DEBUG & 1)
	93	int refcount;
	94	#endif
679af8a3	95	} block_desc;
679af8a3	96
f4bb5d6b	97	static const int block_max_counts[3] = {
	98	4*1024,
	99	256,
	100	256,
	101	};
	102	static block_desc *block_tables[3];
	103	static int block_counts[3];
679af8a3	104
f4bb5d6b	105	// ROM hash table
679af8a3	106	#define MAX_HASH_ENTRIES 1024
679af8a3	107	#define HASH_MASK (MAX_HASH_ENTRIES - 1)
f4bb5d6b	108	static void **hash_table;
679af8a3	109
679af8a3	110	extern void sh2_drc_entry(SH2 sh2, void block);
	111	extern void sh2_drc_exit(void);
	112
	113	// tmp
	114	extern void __attribute__((regparm(2))) sh2_do_op(SH2 *sh2, int opcode);
e898de13	115	static void __attribute__((regparm(1))) sh2_test_irq(SH2 *sh2);
679af8a3	116
f4bb5d6b	117	static void flush_tcache(int tcid)
	118	{
	119	printf("tcache #%d flush! (%d/%d, bds %d/%d)\n", tcid,
	120	tcache_ptrs[tcid] - tcache_bases[tcid], tcache_sizes[tcid],
	121	block_counts[tcid], block_max_counts[tcid]);
	122
	123	block_counts[tcid] = 0;
	124	tcache_ptrs[tcid] = tcache_bases[tcid];
	125	if (tcid == 0) { // ROM, RAM
	126	memset(hash_table, 0, sizeof(hash_table[0]) * MAX_HASH_ENTRIES);
	127	memset(Pico32xMem->drcblk_ram, 0, sizeof(Pico32xMem->drcblk_ram));
	128	}
	129	else
	130	memset(Pico32xMem->drcblk_da[tcid - 1], 0, sizeof(Pico32xMem->drcblk_da[0]));
	131	#if (DRC_DEBUG & 2)
	132	tcache_dsm_ptrs[tcid] = tcache_bases[tcid];
	133	#endif
	134	}
	135
679af8a3	136	static void dr_find_block(block_desc tab, u32 addr)
	137	{
	138	for (tab = tab->next; tab != NULL; tab = tab->next)
	139	if (tab->addr == addr)
	140	break;
	141
	142	if (tab != NULL)
	143	return tab->tcache_ptr;
	144
	145	printf("block miss for %08x\n", addr);
	146	return NULL;
	147	}
	148
f4bb5d6b	149	static block_desc dr_add_block(u32 addr, int tcache_id, int blk_id)
679af8a3	150	{
f4bb5d6b	151	int *bcount = &block_counts[tcache_id];
679af8a3	152	block_desc *bd;
679af8a3	153
f4bb5d6b	154	if (*bcount >= block_max_counts[tcache_id])
f4bb5d6b	155	return NULL;
679af8a3	156
f4bb5d6b	157	bd = &block_tables[tcache_id][*bcount];
679af8a3	158	bd->addr = addr;
679af8a3	159	bd->tcache_ptr = tcache_ptr;
f4bb5d6b	160	blk_id = bcount;
f4bb5d6b	161	(*bcount)++;
679af8a3	162
	163	return bd;
	164	}
	165
	166	#define HASH_FUNC(hash_tab, addr) \
	167	((block_desc **)(hash_tab))[(addr) & HASH_MASK]
	168
	169	// ---------------------------------------------------------------
	170
	171	static void emit_move_r_imm32(sh2_reg_e dst, u32 imm)
41397701	172	{
679af8a3	173	int host_dst = reg_map_g2h[dst];
	174	int tmp = 0;
	175
	176	if (host_dst != -1)
	177	tmp = host_dst;
	178	emith_move_r_imm(tmp, imm);
	179	if (host_dst == -1)
	180	emith_ctx_write(tmp, dst * 4);
	181	}
	182
	183	static void emit_move_r_r(sh2_reg_e dst, sh2_reg_e src)
	184	{
	185	int host_dst = reg_map_g2h[dst], host_src = reg_map_g2h[src];
	186	int tmp = 0;
	187
	188	if (host_dst != -1 && host_src != -1) {
	189	emith_move_r_r(host_dst, host_src);
	190	return;
	191	}
	192
	193	if (host_src != -1)
	194	tmp = host_src;
	195	if (host_dst != -1)
	196	tmp = host_dst;
	197
	198	if (host_src == -1)
	199	emith_ctx_read(tmp, src * 4);
	200	if (host_dst == -1)
	201	emith_ctx_write(tmp, dst * 4);
	202	}
	203
	204	static void emit_braf(sh2_reg_e reg, u32 pc)
	205	{
	206	int host_reg = reg_map_g2h[reg];
	207	if (host_reg == -1) {
	208	emith_ctx_read(0, reg * 4);
	209	} else
	210	emith_move_r_r(0, host_reg);
	211	emith_add_r_imm(0, pc);
	212
e898de13	213	emith_ctx_write(0, SHR_PPC * 4);
679af8a3	214	}
679af8a3	215
679af8a3	216	/*
	217	static int sh2_translate_op4(int op)
	218	{
	219	switch (op & 0x000f)
	220	{
	221	case 0x0b:
	222	default:
	223	emith_pass_arg(2, sh2, op);
	224	emith_call(sh2_do_op);
	225	break;
	226	}
	227
	228	return 0;
	229	}
	230	*/
	231
e898de13	232	#define DELAYED_OP \
	233	delayed_op = 2
	234
	235	#define CHECK_UNHANDLED_BITS(mask) { \
	236	if ((op & (mask)) != 0) \
	237	goto default_; \
	238	}
	239
679af8a3	240	static void sh2_translate(SH2 sh2, block_desc *other_block)
679af8a3	241	{
f4bb5d6b	242	void *block_entry;
679af8a3	243	block_desc *this_block;
41397701	244	unsigned int pc = sh2->pc;
e898de13	245	int op, delayed_op = 0, test_irq = 0;
f4bb5d6b	246	int tcache_id = 0, blkid = 0;
679af8a3	247	int cycles = 0;
e898de13	248	u32 tmp, tmp2;
679af8a3	249
f4bb5d6b	250	// validate PC
	251	tmp = sh2->pc >> 29;
	252	if ((tmp != 0 && tmp != 1 && tmp != 6) \|\| sh2->pc == 0) {
	253	printf("invalid PC, aborting: %08x\n", sh2->pc);
	254	// FIXME: be less destructive
	255	exit(1);
	256	}
	257
	258	if ((sh2->pc & 0xe0000000) == 0xc0000000 \|\| (sh2->pc & ~0xfff) == 0) {
	259	// data_array, BIOS have separate tcache (shared)
	260	tcache_id = 1 + sh2->is_slave;
	261	}
	262
	263	tcache_ptr = tcache_ptrs[tcache_id];
	264	this_block = dr_add_block(pc, tcache_id, &blkid);
	265
	266	tmp = tcache_ptr - tcache_bases[tcache_id];
	267	if (tmp > tcache_sizes[tcache_id] - MAX_BLOCK_SIZE \|\| this_block == NULL) {
	268	flush_tcache(tcache_id);
	269	tcache_ptr = tcache_ptrs[tcache_id];
	270	other_block = NULL; // also gone too due to flush
	271	this_block = dr_add_block(pc, tcache_id, &blkid);
	272	}
e898de13	273
f4bb5d6b	274	this_block->next = other_block;
	275	if ((sh2->pc & 0xc6000000) == 0x02000000) // ROM
	276	HASH_FUNC(hash_table, pc) = this_block;
679af8a3	277
f4bb5d6b	278	block_entry = tcache_ptr;
e898de13	279	#if (DRC_DEBUG & 1)
f4bb5d6b	280	printf("== %csh2 block #%d,%d %08x -> %p\n", sh2->is_slave ? 's' : 'm',
f4bb5d6b	281	tcache_id, block_counts[tcache_id], pc, block_entry);
e898de13	282	if (other_block != NULL) {
	283	printf(" hash collision with %08x\n", other_block->addr);
	284	hash_collisions++;
	285	}
679af8a3	286	#endif
679af8a3	287
e898de13	288	while (cycles < BLOCK_CYCLE_LIMIT \|\| delayed_op)
679af8a3	289	{
e898de13	290	if (delayed_op > 0)
	291	delayed_op--;
	292
2b2b46b0	293	op = p32x_sh2_read16(pc, sh2);
e898de13	294
	295	#if (DRC_DEBUG & 3)
	296	insns_compiled++;
	297	#if (DRC_DEBUG & 2)
	298	DasmSH2(sh2dasm_buff, pc, op);
	299	printf("%08x %04x %s\n", pc, op, sh2dasm_buff);
	300	#endif
679af8a3	301	#endif
679af8a3	302
	303	pc += 2;
	304	cycles++;
	305
	306	switch ((op >> 12) & 0x0f)
	307	{
	308	case 0x00:
e898de13	309	switch (op & 0x0f) {
	310	case 0x03:
	311	CHECK_UNHANDLED_BITS(0xd0);
	312	// BRAF Rm 0000mmmm00100011
	313	// BSRF Rm 0000mmmm00000011
679af8a3	314	DELAYED_OP;
e898de13	315	if (!(op & 0x20))
	316	emit_move_r_imm32(SHR_PR, pc + 2);
	317	emit_braf((op >> 8) & 0x0f, pc + 2);
679af8a3	318	cycles++;
e898de13	319	goto end_op;
	320	case 0x09:
	321	CHECK_UNHANDLED_BITS(0xf0);
	322	// NOP 0000000000001001
	323	goto end_op;
	324	case 0x0b:
	325	CHECK_UNHANDLED_BITS(0xd0);
679af8a3	326	DELAYED_OP;
e898de13	327	if (!(op & 0x20)) {
	328	// RTS 0000000000001011
	329	emit_move_r_r(SHR_PPC, SHR_PR);
	330	cycles++;
	331	} else {
	332	// RTE 0000000000101011
	333	//emit_move_r_r(SHR_PC, SHR_PR);
	334	emit_move_r_imm32(SHR_PC, pc - 2);
f4bb5d6b	335	emith_pass_arg_r(0, CONTEXT_REG);
f4bb5d6b	336	emith_pass_arg_imm(1, op);
e898de13	337	emith_call(sh2_do_op);
	338	emit_move_r_r(SHR_PPC, SHR_PC);
	339	test_irq = 1;
	340	cycles += 3;
	341	}
	342	goto end_op;
679af8a3	343	}
	344	goto default_;
	345
	346	case 0x04:
e898de13	347	switch (op & 0x0f) {
	348	case 0x07:
	349	if ((op & 0xf0) != 0)
	350	goto default_;
	351	// LDC.L @Rm+,SR 0100mmmm00000111
	352	test_irq = 1;
	353	goto default_;
	354	case 0x0b:
	355	if ((op & 0xd0) != 0)
	356	goto default_;
	357	// JMP @Rm 0100mmmm00101011
	358	// JSR @Rm 0100mmmm00001011
679af8a3	359	DELAYED_OP;
e898de13	360	if (!(op & 0x20))
	361	emit_move_r_imm32(SHR_PR, pc + 2);
	362	emit_move_r_r(SHR_PPC, (op >> 8) & 0x0f);
679af8a3	363	cycles++;
e898de13	364	goto end_op;
	365	case 0x0e:
	366	if ((op & 0xf0) != 0)
	367	goto default_;
	368	// LDC Rm,SR 0100mmmm00001110
	369	test_irq = 1;
	370	goto default_;
679af8a3	371	}
	372	goto default_;
	373
e898de13	374	case 0x08:
679af8a3	375	switch (op & 0x0f00) {
	376	// BT/S label 10001101dddddddd
	377	case 0x0d00:
	378	// BF/S label 10001111dddddddd
	379	case 0x0f00:
	380	DELAYED_OP;
	381	cycles--;
679af8a3	382	// fallthrough
	383	// BT label 10001001dddddddd
	384	case 0x0900:
	385	// BF label 10001011dddddddd
	386	case 0x0b00:
679af8a3	387	tmp = ((signed int)(op << 24) >> 23);
e898de13	388	tmp2 = delayed_op ? SHR_PPC : SHR_PC;
	389	emit_move_r_imm32(tmp2, pc + (delayed_op ? 2 : 0));
	390	emith_test_t();
65c75cb0	391	EMITH_CONDITIONAL(emit_move_r_imm32(tmp2, pc + tmp + 2), (op & 0x0200) ? 1 : 0);
e898de13	392	cycles += 2;
	393	if (!delayed_op)
	394	goto end_block;
	395	goto end_op;
679af8a3	396	}
679af8a3	397	goto default_;
679af8a3	398
	399	case 0x0a:
	400	// BRA label 1010dddddddddddd
	401	DELAYED_OP;
	402	do_bra:
	403	tmp = ((signed int)(op << 20) >> 19);
e898de13	404	emit_move_r_imm32(SHR_PPC, pc + tmp + 2);
679af8a3	405	cycles++;
e898de13	406	break;
679af8a3	407
	408	case 0x0b:
	409	// BSR label 1011dddddddddddd
	410	DELAYED_OP;
e898de13	411	emit_move_r_imm32(SHR_PR, pc + 2);
679af8a3	412	goto do_bra;
	413
	414	default:
	415	default_:
	416	emit_move_r_imm32(SHR_PC, pc - 2);
f4bb5d6b	417	emith_pass_arg_r(0, CONTEXT_REG);
f4bb5d6b	418	emith_pass_arg_imm(1, op);
679af8a3	419	emith_call(sh2_do_op);
	420	break;
	421	}
	422
e898de13	423	end_op:
6add7875	424	if (delayed_op == 1)
e898de13	425	emit_move_r_r(SHR_PC, SHR_PPC);
6add7875	426
e898de13	427	if (test_irq && delayed_op != 2) {
f4bb5d6b	428	emith_pass_arg_r(0, CONTEXT_REG);
e898de13	429	emith_call(sh2_test_irq);
	430	break;
	431	}
6add7875	432	if (delayed_op == 1)
6add7875	433	break;
e898de13	434
f4bb5d6b	435	do_host_disasm(tcache_id);
679af8a3	436	}
	437
	438	end_block:
f4bb5d6b	439	this_block->end_addr = pc;
	440
	441	// mark memory blocks as containing compiled code
	442	if ((sh2->pc & 0xe0000000) == 0xc0000000 \|\| (sh2->pc & ~0xfff) == 0) {
	443	// data array, BIOS
	444	u16 *drcblk = Pico32xMem->drcblk_da[sh2->is_slave];
	445	tmp = (this_block->addr & 0xfff) >> SH2_DRCBLK_DA_SHIFT;
	446	tmp2 = (this_block->end_addr & 0xfff) >> SH2_DRCBLK_DA_SHIFT;
	447	Pico32xMem->drcblk_da[sh2->is_slave][tmp] = (blkid << 1) \| 1;
	448	for (++tmp; tmp < tmp2; tmp++) {
	449	if (drcblk[tmp])
	450	break; // dont overwrite overlay block
	451	drcblk[tmp] = blkid << 1;
	452	}
	453	}
	454	else if ((this_block->addr & 0xc7fc0000) == 0x06000000) { // DRAM
	455	tmp = (this_block->addr & 0x3ffff) >> SH2_DRCBLK_RAM_SHIFT;
	456	tmp2 = (this_block->end_addr & 0x3ffff) >> SH2_DRCBLK_RAM_SHIFT;
	457	Pico32xMem->drcblk_ram[tmp] = (blkid << 1) \| 1;
	458	for (++tmp; tmp < tmp2; tmp++) {
	459	if (Pico32xMem->drcblk_ram[tmp])
	460	break;
	461	Pico32xMem->drcblk_ram[tmp] = blkid << 1;
	462	}
679af8a3	463	}
	464
	465	if (reg_map_g2h[SHR_SR] == -1) {
	466	emith_ctx_sub(cycles << 12, SHR_SR * 4);
	467	} else
	468	emith_sub_r_imm(reg_map_g2h[SHR_SR], cycles << 12);
	469	emith_jump(sh2_drc_exit);
f4bb5d6b	470	tcache_ptrs[tcache_id] = tcache_ptr;
	471
	472	do_host_disasm(tcache_id);
	473	dbg(1, " block #%d,%d tcache %d/%d, insns %d -> %d %.3f",
	474	tcache_id, block_counts[tcache_id],
	475	tcache_ptr - tcache_bases[tcache_id], tcache_sizes[tcache_id],
	476	insns_compiled, host_insn_count, (double)host_insn_count / insns_compiled);
	477	if ((sh2->pc & 0xc6000000) == 0x02000000) // ROM
	478	dbg(1, " hash collisions %d/%d", hash_collisions, block_counts[tcache_id]);
679af8a3	479	return block_entry;
f4bb5d6b	480	/*
679af8a3	481	unimplemented:
679af8a3	482	// last op
f4bb5d6b	483	do_host_disasm(tcache_id);
679af8a3	484	exit(1);
f4bb5d6b	485	*/
679af8a3	486	}
	487
	488	void __attribute__((noinline)) sh2_drc_dispatcher(SH2 *sh2)
	489	{
	490	while (((signed int)sh2->sr >> 12) > 0)
	491	{
679af8a3	492	void *block = NULL;
f4bb5d6b	493	block_desc *bd = NULL;
6add7875	494
	495	// FIXME: must avoid doing it so often..
	496	sh2_test_irq(sh2);
	497
f4bb5d6b	498	// we have full block id tables for data_array and RAM
	499	// BIOS goes to data_array table too
	500	if ((sh2->pc & 0xff000000) == 0xc0000000 \|\| (sh2->pc & ~0xfff) == 0) {
	501	int blkid = Pico32xMem->drcblk_da[sh2->is_slave][(sh2->pc & 0xfff) >> SH2_DRCBLK_DA_SHIFT];
	502	if (blkid & 1) {
	503	bd = &block_tables[1 + sh2->is_slave][blkid >> 1];
	504	block = bd->tcache_ptr;
	505	}
	506	}
	507	// RAM
	508	else if ((sh2->pc & 0xc6000000) == 0x06000000) {
	509	int blkid = Pico32xMem->drcblk_ram[(sh2->pc & 0x3ffff) >> SH2_DRCBLK_RAM_SHIFT];
	510	if (blkid & 1) {
	511	bd = &block_tables[0][blkid >> 1];
679af8a3	512	block = bd->tcache_ptr;
f4bb5d6b	513	}
	514	}
	515	// ROM
	516	else if ((sh2->pc & 0xc6000000) == 0x02000000) {
	517	bd = HASH_FUNC(hash_table, sh2->pc);
	518
	519	if (bd != NULL) {
	520	if (bd->addr == sh2->pc)
	521	block = bd->tcache_ptr;
	522	else
	523	block = dr_find_block(bd, sh2->pc);
	524	}
679af8a3	525	}
	526
	527	if (block == NULL)
	528	block = sh2_translate(sh2, bd);
	529
f4bb5d6b	530	dbg(4, "= %csh2 enter %08x %p, c=%d", sh2->is_slave ? 's' : 'm',
	531	sh2->pc, block, (signed int)sh2->sr >> 12);
	532	#if (DRC_DEBUG & 1)
	533	if (bd != NULL)
	534	bd->refcount++;
679af8a3	535	#endif
	536	sh2_drc_entry(sh2, block);
	537	}
	538	}
	539
f4bb5d6b	540	static void sh2_smc_rm_block(u16 drcblk, u16 p, block_desc *btab, u32 a)
	541	{
	542	u16 id = *p >> 1;
	543	block_desc *bd = btab + id;
	544
	545	dbg(1, " killing block %08x", bd->addr);
	546	bd->addr = bd->end_addr = 0;
	547
	548	while (p > drcblk && (p[-1] >> 1) == id)
	549	p--;
	550
	551	// check for possible overlay block
	552	if (p > 0 && p[-1] != 0) {
	553	bd = btab + (p[-1] >> 1);
	554	if (bd->addr <= a && a < bd->end_addr)
	555	sh2_smc_rm_block(drcblk, p - 1, btab, a);
	556	}
	557
	558	do {
	559	*p++ = 0;
	560	}
	561	while ((*p >> 1) == id);
	562	}
	563
	564	void sh2_drc_wcheck_ram(unsigned int a, int val, int cpuid)
	565	{
	566	u16 *drcblk = Pico32xMem->drcblk_ram;
	567	u16 *p = drcblk + ((a & 0x3ffff) >> SH2_DRCBLK_RAM_SHIFT);
	568
	569	dbg(1, "%csh2 smc check @%08x", cpuid ? 's' : 'm', a);
	570	sh2_smc_rm_block(drcblk, p, block_tables[0], a);
	571	}
	572
	573	void sh2_drc_wcheck_da(unsigned int a, int val, int cpuid)
	574	{
	575	u16 *drcblk = Pico32xMem->drcblk_da[cpuid];
	576	u16 *p = drcblk + ((a & 0xfff) >> SH2_DRCBLK_DA_SHIFT);
	577
	578	dbg(1, "%csh2 smc check @%08x", cpuid ? 's' : 'm', a);
	579	sh2_smc_rm_block(drcblk, p, block_tables[1 + cpuid], a);
	580	}
	581
679af8a3	582	void sh2_execute(SH2 *sh2, int cycles)
	583	{
	584	sh2->cycles_aim += cycles;
	585	cycles = sh2->cycles_aim - sh2->cycles_done;
	586
	587	// cycles are kept in SHR_SR unused bits (upper 20)
	588	sh2->sr &= 0x3f3;
	589	sh2->sr \|= cycles << 12;
	590	sh2_drc_dispatcher(sh2);
	591
	592	sh2->cycles_done += cycles - ((signed int)sh2->sr >> 12);
	593	}
	594
e898de13	595	static void __attribute__((regparm(1))) sh2_test_irq(SH2 *sh2)
679af8a3	596	{
6add7875	597	if (sh2->pending_level > ((sh2->sr >> 4) & 0x0f))
	598	{
	599	if (sh2->pending_irl > sh2->pending_int_irq)
	600	sh2_do_irq(sh2, sh2->pending_irl, 64 + sh2->pending_irl/2);
	601	else {
	602	sh2_do_irq(sh2, sh2->pending_int_irq, sh2->pending_int_vector);
	603	sh2->pending_int_irq = 0; // auto-clear
	604	sh2->pending_level = sh2->pending_irl;
	605	}
	606	}
679af8a3	607	}
679af8a3	608
f4bb5d6b	609	#if (DRC_DEBUG & 1)
	610	static void block_stats(void)
	611	{
	612	int c, b, i, total = 0;
	613
	614	for (b = 0; b < ARRAY_SIZE(block_tables); b++)
	615	for (i = 0; i < block_counts[b]; i++)
	616	if (block_tables[b][i].addr != 0)
	617	total += block_tables[b][i].refcount;
	618
	619	for (c = 0; c < 10; c++) {
	620	block_desc blk, maxb = NULL;
	621	int max = 0;
	622	for (b = 0; b < ARRAY_SIZE(block_tables); b++) {
	623	for (i = 0; i < block_counts[b]; i++) {
	624	blk = &block_tables[b][i];
	625	if (blk->addr != 0 && blk->refcount > max) {
	626	max = blk->refcount;
	627	maxb = blk;
	628	}
	629	}
	630	}
	631	if (maxb == NULL)
	632	break;
	633	printf("%08x %9d %2.3f%%\n", maxb->addr, maxb->refcount,
	634	(double)maxb->refcount / total * 100.0);
	635	maxb->refcount = 0;
	636	}
	637	}
	638	#endif
	639
679af8a3	640	int sh2_drc_init(SH2 *sh2)
679af8a3	641	{
f4bb5d6b	642	if (block_tables[0] == NULL) {
	643	int i, cnt;
	644	cnt = block_max_counts[0] + block_max_counts[1] + block_max_counts[2];
	645	block_tables[0] = calloc(cnt, sizeof(*block_tables[0]));
	646	if (block_tables[0] == NULL)
e898de13	647	return -1;
e898de13	648
f4bb5d6b	649	memset(block_counts, 0, sizeof(block_counts));
	650	tcache_bases[0] = tcache_ptrs[0] = tcache;
	651
	652	for (i = 1; i < ARRAY_SIZE(block_tables); i++) {
	653	block_tables[i] = block_tables[i - 1] + block_max_counts[i - 1];
	654	tcache_bases[i] = tcache_ptrs[i] = tcache_bases[i - 1] + tcache_sizes[i - 1];
	655	}
	656
	657	#if (DRC_DEBUG & 2)
	658	for (i = 0; i < ARRAY_SIZE(block_tables); i++)
	659	tcache_dsm_ptrs[i] = tcache_bases[i];
	660	#endif
e898de13	661	#if (DRC_DEBUG & 1)
	662	hash_collisions = 0;
	663	#endif
679af8a3	664	}
679af8a3	665
f4bb5d6b	666	if (hash_table == NULL) {
	667	hash_table = calloc(sizeof(hash_table[0]), MAX_HASH_ENTRIES);
	668	if (hash_table == NULL)
	669	return -1;
	670	}
41397701	671
679af8a3	672	return 0;
41397701	673	}
41397701	674
e898de13	675	void sh2_drc_finish(SH2 *sh2)
e898de13	676	{
f4bb5d6b	677	if (block_tables[0] != NULL) {
	678	#if (DRC_DEBUG & 1)
	679	block_stats();
	680	#endif
	681	free(block_tables[0]);
	682	memset(block_tables, 0, sizeof(block_tables));
e898de13	683	}
e898de13	684
f4bb5d6b	685	if (hash_table != NULL) {
	686	free(hash_table);
	687	hash_table = NULL;
	688	}
e898de13	689	}