[picodrive.git] / pico / cd / LC89510.c

/***********************************************************\r
 *                                                         *\r
 * This source file was taken from the Gens project        *\r
 * Written by Stéphane Dallongeville                       *\r
 * Copyright (c) 2002 by Stéphane Dallongeville            *\r
 * Modified/adapted for PicoDrive by notaz, 2007           *\r
 *                                                         *\r
 ***********************************************************/\r
\r
#include "../pico_int.h"\r
\r
#define CDC_DMA_SPEED 256\r
\r
\r
static void CDD_Reset(void)\r
{\r
	// Reseting CDD\r
\r
	memset(Pico_mcd->s68k_regs+0x34, 0, 2*2); // CDD.Fader, CDD.Control\r
	Pico_mcd->cdd.Status = 0;\r
	Pico_mcd->cdd.Minute = 0;\r
	Pico_mcd->cdd.Seconde = 0;\r
	Pico_mcd->cdd.Frame = 0;\r
	Pico_mcd->cdd.Ext = 0;\r
\r
	// clear receive status and transfer command\r
	memset(Pico_mcd->s68k_regs+0x38, 0, 20);\r
	Pico_mcd->s68k_regs[0x38+9] = 0xF;		// Default checksum\r
}\r
\r
\r
static void CDC_Reset(void)\r
{\r
	// Reseting CDC\r
\r
	memset(Pico_mcd->cdc.Buffer, 0, sizeof(Pico_mcd->cdc.Buffer));\r
\r
	Pico_mcd->cdc.COMIN = 0;\r
	Pico_mcd->cdc.IFSTAT = 0xFF;\r
	Pico_mcd->cdc.DAC.N = 0;\r
	Pico_mcd->cdc.DBC.N = 0;\r
	Pico_mcd->cdc.HEAD.N = 0x01000000;\r
	Pico_mcd->cdc.PT.N = 0;\r
	Pico_mcd->cdc.WA.N = 2352 * 2;\r
	Pico_mcd->cdc.STAT.N = 0x00000080;\r
	Pico_mcd->cdc.SBOUT = 0;\r
	Pico_mcd->cdc.IFCTRL = 0;\r
	Pico_mcd->cdc.CTRL.N = 0;\r
\r
	Pico_mcd->cdc.Decode_Reg_Read = 0;\r
	Pico_mcd->scd.Status_CDC &= ~0x08;\r
}\r
\r
\r
PICO_INTERNAL void LC89510_Reset(void)\r
{\r
	CDD_Reset();\r
	CDC_Reset();\r
\r
	// clear DMA_Adr & Stop_Watch\r
	memset(Pico_mcd->s68k_regs + 0xA, 0, 4);\r
}\r
\r
\r
PICO_INTERNAL void Update_CDC_TRansfer(int which)\r
{\r
	unsigned int DMA_Adr, dep, length;\r
	unsigned short *dest;\r
	unsigned char  *src;\r
\r
	if (1) //Pico_mcd->cdc.DBC.N <= (CDC_DMA_SPEED * 2))\r
	{\r
		length = (Pico_mcd->cdc.DBC.N + 1) >> 1;\r
		Pico_mcd->scd.Status_CDC &= ~0x08;	// Last transfer\r
		Pico_mcd->s68k_regs[4] |=  0x80;	// End data transfer\r
		Pico_mcd->s68k_regs[4] &= ~0x40;	// no more data ready\r
		Pico_mcd->cdc.IFSTAT |= 0x08;		// No more data transfer in progress\r
\r
		if (Pico_mcd->cdc.IFCTRL & 0x40)	// DTEIEN = Data Trasnfer End Interrupt Enable ?\r
		{\r
			Pico_mcd->cdc.IFSTAT &= ~0x40;\r
\r
			if (Pico_mcd->s68k_regs[0x33] & PCDS_IEN5)\r
			{\r
				elprintf(EL_INTS, "cdc DTE irq 5");\r
				SekInterruptS68k(5);\r
			}\r
		}\r
	}\r
	else length = CDC_DMA_SPEED;\r
\r
\r
	// TODO: dst bounds checking?\r
	src = Pico_mcd->cdc.Buffer + Pico_mcd->cdc.DAC.N;\r
	DMA_Adr = (Pico_mcd->s68k_regs[0xA]<<8) | Pico_mcd->s68k_regs[0xB];\r
\r
	if (which == 7) // WORD RAM\r
	{\r
		if (Pico_mcd->s68k_regs[3] & 4)\r
		{\r
			// test: Final Fight\r
			int bank = !(Pico_mcd->s68k_regs[3]&1);\r
			dep = ((DMA_Adr & 0x3FFF) << 3);\r
			cdprintf("CD DMA # %04x -> word_ram1M # %06x, len=%i",\r
					Pico_mcd->cdc.DAC.N, dep, length);\r
\r
			dest = (unsigned short *) (Pico_mcd->word_ram1M[bank] + dep);\r
\r
			memcpy16bswap(dest, src, length);\r
\r
			/*{ // debug\r
				unsigned char *b1 = Pico_mcd->word_ram1M[bank] + dep;\r
				unsigned char *b2 = (unsigned char *)(dest+length) - 8;\r
				dprintf("%02x %02x %02x %02x .. %02x %02x %02x %02x",\r
					b1[0], b1[1], b1[4], b1[5], b2[0], b2[1], b2[4], b2[5]);\r
			}*/\r
		}\r
		else\r
		{\r
			dep = ((DMA_Adr & 0x7FFF) << 3);\r
			cdprintf("CD DMA # %04x -> word_ram2M # %06x, len=%i",\r
					Pico_mcd->cdc.DAC.N, dep, length);\r
			dest = (unsigned short *) (Pico_mcd->word_ram2M + dep);\r
\r
			memcpy16bswap(dest, src, length);\r
\r
			/*{ // debug\r
				unsigned char *b1 = Pico_mcd->word_ram2M + dep;\r
				unsigned char *b2 = (unsigned char *)(dest+length) - 4;\r
				dprintf("%02x %02x %02x %02x .. %02x %02x %02x %02x",\r
					b1[0], b1[1], b1[2], b1[3], b2[0], b2[1], b2[2], b2[3]);\r
			}*/\r
		}\r
	}\r
	else if (which == 4) // PCM RAM (check: popful Mail)\r
	{\r
		dep = (DMA_Adr & 0x03FF) << 2;\r
		cdprintf("CD DMA # %04x -> PCM[%i] # %04x, len=%i",\r
			Pico_mcd->cdc.DAC.N, Pico_mcd->pcm.bank, dep, length);\r
		dest = (unsigned short *) (Pico_mcd->pcm_ram_b[Pico_mcd->pcm.bank] + dep);\r
\r
		if (Pico_mcd->cdc.DAC.N & 1) /* unaligned src? */\r
			memcpy(dest, src, length*2);\r
		else	memcpy16(dest, (unsigned short *) src, length);\r
	}\r
	else if (which == 5) // PRG RAM\r
	{\r
		dep = DMA_Adr << 3;\r
		dest = (unsigned short *) (Pico_mcd->prg_ram + dep);\r
		cdprintf("CD DMA # %04x -> prg_ram # %06x, len=%i",\r
				Pico_mcd->cdc.DAC.N, dep, length);\r
\r
		memcpy16bswap(dest, src, length);\r
\r
		/*{ // debug\r
			unsigned char *b1 = Pico_mcd->prg_ram + dep;\r
			unsigned char *b2 = (unsigned char *)(dest+length) - 4;\r
			dprintf("%02x %02x %02x %02x .. %02x %02x %02x %02x",\r
				b1[0], b1[1], b1[2], b1[3], b2[0], b2[1], b2[2], b2[3]);\r
		}*/\r
	}\r
\r
	length <<= 1;\r
	Pico_mcd->cdc.DAC.N = (Pico_mcd->cdc.DAC.N + length) & 0xFFFF;\r
	if (Pico_mcd->scd.Status_CDC & 0x08) Pico_mcd->cdc.DBC.N -= length;\r
	else Pico_mcd->cdc.DBC.N = 0;\r
\r
	// update DMA_Adr\r
	length >>= 2;\r
	if (which != 4) length >>= 1;\r
	DMA_Adr += length;\r
	Pico_mcd->s68k_regs[0xA] = DMA_Adr >> 8;\r
	Pico_mcd->s68k_regs[0xB] = DMA_Adr;\r
}\r
\r
\r
PICO_INTERNAL_ASM unsigned short Read_CDC_Host(int is_sub)\r
{\r
	int addr;\r
\r
	if (!(Pico_mcd->scd.Status_CDC & 0x08))\r
	{\r
		// Transfer data disabled\r
		cdprintf("Read_CDC_Host FIXME: Transfer data disabled");\r
		return 0;\r
	}\r
\r
	if ((is_sub && (Pico_mcd->s68k_regs[4] & 7) != 3) ||\r
		(!is_sub && (Pico_mcd->s68k_regs[4] & 7) != 2))\r
	{\r
		// Wrong setting\r
		cdprintf("Read_CDC_Host FIXME: Wrong setting");\r
		return 0;\r
	}\r
\r
	Pico_mcd->cdc.DBC.N -= 2;\r
\r
	if (Pico_mcd->cdc.DBC.N <= 0)\r
	{\r
		Pico_mcd->cdc.DBC.N = 0;\r
		Pico_mcd->scd.Status_CDC &= ~0x08;		// Last transfer\r
		Pico_mcd->s68k_regs[4] |=  0x80;		// End data transfer\r
		Pico_mcd->s68k_regs[4] &= ~0x40;		// no more data ready\r
		Pico_mcd->cdc.IFSTAT |= 0x08;			// No more data transfer in progress\r
\r
		if (Pico_mcd->cdc.IFCTRL & 0x40)		// DTEIEN = Data Transfer End Interrupt Enable ?\r
		{\r
			Pico_mcd->cdc.IFSTAT &= ~0x40;\r
\r
			if (Pico_mcd->s68k_regs[0x33]&(1<<5)) {\r
				elprintf(EL_INTS, "m68k: s68k irq 5");\r
				SekInterruptS68k(5);\r
			}\r
\r
			cdprintf("CDC - DTE interrupt");\r
		}\r
	}\r
\r
	addr = Pico_mcd->cdc.DAC.N;\r
	Pico_mcd->cdc.DAC.N += 2;\r
\r
	cdprintf("Read_CDC_Host sub=%i d=%04x dac=%04x dbc=%04x", is_sub,\r
		(Pico_mcd->cdc.Buffer[addr]<<8) | Pico_mcd->cdc.Buffer[addr+1], Pico_mcd->cdc.DAC.N, Pico_mcd->cdc.DBC.N);\r
\r
	return (Pico_mcd->cdc.Buffer[addr]<<8) | Pico_mcd->cdc.Buffer[addr+1];\r
}\r
\r
\r
PICO_INTERNAL void CDC_Update_Header(void)\r
{\r
	if (Pico_mcd->cdc.CTRL.B.B1 & 0x01)		// Sub-Header wanted ?\r
	{\r
		Pico_mcd->cdc.HEAD.B.B0 = 0;\r
		Pico_mcd->cdc.HEAD.B.B1 = 0;\r
		Pico_mcd->cdc.HEAD.B.B2 = 0;\r
		Pico_mcd->cdc.HEAD.B.B3 = 0;\r
	}\r
	else\r
	{\r
		_msf MSF;\r
\r
		LBA_to_MSF(Pico_mcd->scd.Cur_LBA, &MSF);\r
\r
		Pico_mcd->cdc.HEAD.B.B0 = INT_TO_BCDB(MSF.M);\r
		Pico_mcd->cdc.HEAD.B.B1 = INT_TO_BCDB(MSF.S);\r
		Pico_mcd->cdc.HEAD.B.B2 = INT_TO_BCDB(MSF.F);\r
		Pico_mcd->cdc.HEAD.B.B3 = 0x01;\r
	}\r
}\r
\r
\r
PICO_INTERNAL unsigned char CDC_Read_Reg(void)\r
{\r
	unsigned char ret;\r
\r
	switch(Pico_mcd->s68k_regs[5] & 0xF)\r
	{\r
		case 0x0: // COMIN\r
			cdprintf("CDC read reg 00 = %.2X", Pico_mcd->cdc.COMIN);\r
\r
			Pico_mcd->s68k_regs[5] = 0x1;\r
			return Pico_mcd->cdc.COMIN;\r
\r
		case 0x1: // IFSTAT\r
			cdprintf("CDC read reg 01 = %.2X", Pico_mcd->cdc.IFSTAT);\r
\r
			Pico_mcd->cdc.Decode_Reg_Read |= (1 << 1);		// Reg 1 (decoding)\r
			Pico_mcd->s68k_regs[5] = 0x2;\r
			return Pico_mcd->cdc.IFSTAT;\r
\r
		case 0x2: // DBCL\r
			cdprintf("CDC read reg 02 = %.2X", Pico_mcd->cdc.DBC.B.L);\r
\r
			Pico_mcd->s68k_regs[5] = 0x3;\r
			return Pico_mcd->cdc.DBC.B.L;\r
\r
		case 0x3: // DBCH\r
			cdprintf("CDC read reg 03 = %.2X", Pico_mcd->cdc.DBC.B.H);\r
\r
			Pico_mcd->s68k_regs[5] = 0x4;\r
			return Pico_mcd->cdc.DBC.B.H;\r
\r
		case 0x4: // HEAD0\r
			cdprintf("CDC read reg 04 = %.2X", Pico_mcd->cdc.HEAD.B.B0);\r
\r
			Pico_mcd->cdc.Decode_Reg_Read |= (1 << 4);		// Reg 4 (decoding)\r
			Pico_mcd->s68k_regs[5] = 0x5;\r
			return Pico_mcd->cdc.HEAD.B.B0;\r
\r
		case 0x5: // HEAD1\r
			cdprintf("CDC read reg 05 = %.2X", Pico_mcd->cdc.HEAD.B.B1);\r
\r
			Pico_mcd->cdc.Decode_Reg_Read |= (1 << 5);		// Reg 5 (decoding)\r
			Pico_mcd->s68k_regs[5] = 0x6;\r
			return Pico_mcd->cdc.HEAD.B.B1;\r
\r
		case 0x6: // HEAD2\r
			cdprintf("CDC read reg 06 = %.2X", Pico_mcd->cdc.HEAD.B.B2);\r
\r
			Pico_mcd->cdc.Decode_Reg_Read |= (1 << 6);		// Reg 6 (decoding)\r
			Pico_mcd->s68k_regs[5] = 0x7;\r
			return Pico_mcd->cdc.HEAD.B.B2;\r
\r
		case 0x7: // HEAD3\r
			cdprintf("CDC read reg 07 = %.2X", Pico_mcd->cdc.HEAD.B.B3);\r
\r
			Pico_mcd->cdc.Decode_Reg_Read |= (1 << 7);		// Reg 7 (decoding)\r
			Pico_mcd->s68k_regs[5] = 0x8;\r
			return Pico_mcd->cdc.HEAD.B.B3;\r
\r
		case 0x8: // PTL\r
			cdprintf("CDC read reg 08 = %.2X", Pico_mcd->cdc.PT.B.L);\r
\r
			Pico_mcd->cdc.Decode_Reg_Read |= (1 << 8);		// Reg 8 (decoding)\r
			Pico_mcd->s68k_regs[5] = 0x9;\r
			return Pico_mcd->cdc.PT.B.L;\r
\r
		case 0x9: // PTH\r
			cdprintf("CDC read reg 09 = %.2X", Pico_mcd->cdc.PT.B.H);\r
\r
			Pico_mcd->cdc.Decode_Reg_Read |= (1 << 9);		// Reg 9 (decoding)\r
			Pico_mcd->s68k_regs[5] = 0xA;\r
			return Pico_mcd->cdc.PT.B.H;\r
\r
		case 0xA: // WAL\r
			cdprintf("CDC read reg 10 = %.2X", Pico_mcd->cdc.WA.B.L);\r
\r
			Pico_mcd->s68k_regs[5] = 0xB;\r
			return Pico_mcd->cdc.WA.B.L;\r
\r
		case 0xB: // WAH\r
			cdprintf("CDC read reg 11 = %.2X", Pico_mcd->cdc.WA.B.H);\r
\r
			Pico_mcd->s68k_regs[5] = 0xC;\r
			return Pico_mcd->cdc.WA.B.H;\r
\r
		case 0xC: // STAT0\r
			cdprintf("CDC read reg 12 = %.2X", Pico_mcd->cdc.STAT.B.B0);\r
\r
			Pico_mcd->cdc.Decode_Reg_Read |= (1 << 12);		// Reg 12 (decoding)\r
			Pico_mcd->s68k_regs[5] = 0xD;\r
			return Pico_mcd->cdc.STAT.B.B0;\r
\r
		case 0xD: // STAT1\r
			cdprintf("CDC read reg 13 = %.2X", Pico_mcd->cdc.STAT.B.B1);\r
\r
			Pico_mcd->cdc.Decode_Reg_Read |= (1 << 13);		// Reg 13 (decoding)\r
			Pico_mcd->s68k_regs[5] = 0xE;\r
			return Pico_mcd->cdc.STAT.B.B1;\r
\r
		case 0xE: // STAT2\r
			cdprintf("CDC read reg 14 = %.2X", Pico_mcd->cdc.STAT.B.B2);\r
\r
			Pico_mcd->cdc.Decode_Reg_Read |= (1 << 14);		// Reg 14 (decoding)\r
			Pico_mcd->s68k_regs[5] = 0xF;\r
			return Pico_mcd->cdc.STAT.B.B2;\r
\r
		case 0xF: // STAT3\r
			cdprintf("CDC read reg 15 = %.2X", Pico_mcd->cdc.STAT.B.B3);\r
\r
			ret = Pico_mcd->cdc.STAT.B.B3;\r
			Pico_mcd->cdc.IFSTAT |= 0x20;			// decoding interrupt flag cleared\r
			if ((Pico_mcd->cdc.CTRL.B.B0 & 0x80) && (Pico_mcd->cdc.IFCTRL & 0x20))\r
			{\r
				if ((Pico_mcd->cdc.Decode_Reg_Read & 0x73F2) == 0x73F2)\r
					Pico_mcd->cdc.STAT.B.B3 = 0x80;\r
			}\r
			return ret;\r
	}\r
\r
	return 0;\r
}\r
\r
\r
PICO_INTERNAL void CDC_Write_Reg(unsigned char Data)\r
{\r
	cdprintf("CDC write reg%02d = %.2X", Pico_mcd->s68k_regs[5] & 0xF, Data);\r
\r
	switch (Pico_mcd->s68k_regs[5] & 0xF)\r
	{\r
		case 0x0: // SBOUT\r
			Pico_mcd->s68k_regs[5] = 0x1;\r
			Pico_mcd->cdc.SBOUT = Data;\r
\r
			break;\r
\r
		case 0x1: // IFCTRL\r
			Pico_mcd->s68k_regs[5] = 0x2;\r
			Pico_mcd->cdc.IFCTRL = Data;\r
\r
			if ((Pico_mcd->cdc.IFCTRL & 0x02) == 0)		// Stop data transfer\r
			{\r
				Pico_mcd->cdc.DBC.N = 0;\r
				Pico_mcd->scd.Status_CDC &= ~0x08;\r
				Pico_mcd->cdc.IFSTAT |= 0x08;		// No more data transfer in progress\r
			}\r
			break;\r
\r
		case 0x2: // DBCL\r
			Pico_mcd->s68k_regs[5] = 0x3;\r
			Pico_mcd->cdc.DBC.B.L = Data;\r
\r
			break;\r
\r
		case 0x3: // DBCH\r
			Pico_mcd->s68k_regs[5] = 0x4;\r
			Pico_mcd->cdc.DBC.B.H = Data;\r
\r
			break;\r
\r
		case 0x4: // DACL\r
			Pico_mcd->s68k_regs[5] = 0x5;\r
			Pico_mcd->cdc.DAC.B.L = Data;\r
\r
			break;\r
\r
		case 0x5: // DACH\r
			Pico_mcd->s68k_regs[5] = 0x6;\r
			Pico_mcd->cdc.DAC.B.H = Data;\r
\r
			break;\r
\r
		case 0x6: // DTTRG\r
			if (Pico_mcd->cdc.IFCTRL & 0x02)		// Data transfer enable ?\r
			{\r
				Pico_mcd->cdc.IFSTAT &= ~0x08;		// Data transfer in progress\r
				Pico_mcd->scd.Status_CDC |= 0x08;	// Data transfer in progress\r
				Pico_mcd->s68k_regs[4] &= 0x7F;		// A data transfer start\r
\r
				cdprintf("************** Starting Data Transfer ***********");\r
				cdprintf("RS0 = %.4X  DAC = %.4X  DBC = %.4X  DMA adr = %.4X\n\n", Pico_mcd->s68k_regs[4]<<8,\r
					Pico_mcd->cdc.DAC.N, Pico_mcd->cdc.DBC.N, (Pico_mcd->s68k_regs[0xA]<<8) | Pico_mcd->s68k_regs[0xB]);\r
\r
				// tmp\r
				{\r
					int ddx = Pico_mcd->s68k_regs[4] & 7;\r
					if (ddx <  2) break; // invalid\r
					if (ddx <  4) {\r
						Pico_mcd->s68k_regs[4] |= 0x40; // Data set ready in host port\r
						break;\r
					}\r
					if (ddx == 6) break; // invalid\r
\r
					pcd_event_schedule_s68k(PCD_EVENT_DMA, Pico_mcd->cdc.DBC.N / 2);\r
				}\r
			}\r
			break;\r
\r
		case 0x7: // DTACK\r
			Pico_mcd->cdc.IFSTAT |= 0x40;			// end data transfer interrupt flag cleared\r
			break;\r
\r
		case 0x8: // WAL\r
			Pico_mcd->s68k_regs[5] = 0x9;\r
			Pico_mcd->cdc.WA.B.L = Data;\r
\r
			break;\r
\r
		case 0x9: // WAH\r
			Pico_mcd->s68k_regs[5] = 0xA;\r
			Pico_mcd->cdc.WA.B.H = Data;\r
\r
			break;\r
\r
		case 0xA: // CTRL0\r
			Pico_mcd->s68k_regs[5] = 0xB;\r
			Pico_mcd->cdc.CTRL.B.B0 = Data;\r
\r
			break;\r
\r
		case 0xB: // CTRL1\r
			Pico_mcd->s68k_regs[5] = 0xC;\r
			Pico_mcd->cdc.CTRL.B.B1 = Data;\r
\r
			break;\r
\r
		case 0xC: // PTL\r
			Pico_mcd->s68k_regs[5] = 0xD;\r
			Pico_mcd->cdc.PT.B.L = Data;\r
\r
			break;\r
\r
		case 0xD: // PTH\r
			Pico_mcd->s68k_regs[5] = 0xE;\r
			Pico_mcd->cdc.PT.B.H = Data;\r
\r
			break;\r
\r
		case 0xE: // CTRL2\r
			Pico_mcd->cdc.CTRL.B.B2 = Data;\r
			break;\r
\r
		case 0xF: // RESET\r
			CDC_Reset();\r
			break;\r
	}\r
}\r
\r
\r
static int bswapwrite(int a, unsigned short d)\r
{\r
	*(unsigned short *)(Pico_mcd->s68k_regs + a) = (d>>8)|(d<<8);\r
	return d + (d >> 8);\r
}\r
\r
PICO_INTERNAL void CDD_Export_Status(void)\r
{\r
	unsigned int csum;\r
\r
	csum  = bswapwrite( 0x38+0, Pico_mcd->cdd.Status);\r
	csum += bswapwrite( 0x38+2, Pico_mcd->cdd.Minute);\r
	csum += bswapwrite( 0x38+4, Pico_mcd->cdd.Seconde);\r
	csum += bswapwrite( 0x38+6, Pico_mcd->cdd.Frame);\r
	Pico_mcd->s68k_regs[0x38+8] = Pico_mcd->cdd.Ext;\r
	csum += Pico_mcd->cdd.Ext;\r
	Pico_mcd->s68k_regs[0x38+9] = ~csum & 0xf;\r
\r
	Pico_mcd->s68k_regs[0x37] &= 3; // CDD.Control\r
\r
	if (Pico_mcd->s68k_regs[0x33] & PCDS_IEN4)\r
	{\r
		elprintf(EL_INTS, "cdd export irq 4");\r
		SekInterruptS68k(4);\r
	}\r
\r
//	cdprintf("CDD exported status\n");\r
	cdprintf("out:  Status=%.4X, Minute=%.4X, Second=%.4X, Frame=%.4X  Checksum=%.4X",\r
		(Pico_mcd->s68k_regs[0x38+0] << 8) | Pico_mcd->s68k_regs[0x38+1],\r
		(Pico_mcd->s68k_regs[0x38+2] << 8) | Pico_mcd->s68k_regs[0x38+3],\r
		(Pico_mcd->s68k_regs[0x38+4] << 8) | Pico_mcd->s68k_regs[0x38+5],\r
		(Pico_mcd->s68k_regs[0x38+6] << 8) | Pico_mcd->s68k_regs[0x38+7],\r
		(Pico_mcd->s68k_regs[0x38+8] << 8) | Pico_mcd->s68k_regs[0x38+9]);\r
}\r
\r
\r
PICO_INTERNAL void CDD_Import_Command(void)\r
{\r
//	cdprintf("CDD importing command\n");\r
	cdprintf("in:  Command=%.4X, Minute=%.4X, Second=%.4X, Frame=%.4X  Checksum=%.4X",\r
		(Pico_mcd->s68k_regs[0x38+10+0] << 8) | Pico_mcd->s68k_regs[0x38+10+1],\r
		(Pico_mcd->s68k_regs[0x38+10+2] << 8) | Pico_mcd->s68k_regs[0x38+10+3],\r
		(Pico_mcd->s68k_regs[0x38+10+4] << 8) | Pico_mcd->s68k_regs[0x38+10+5],\r
		(Pico_mcd->s68k_regs[0x38+10+6] << 8) | Pico_mcd->s68k_regs[0x38+10+7],\r
		(Pico_mcd->s68k_regs[0x38+10+8] << 8) | Pico_mcd->s68k_regs[0x38+10+9]);\r
\r
	switch (Pico_mcd->s68k_regs[0x38+10+0])\r
	{\r
		case 0x0:	// STATUS (?)\r
			Get_Status_CDD_c0();\r
			break;\r
\r
		case 0x1:	// STOP ALL (?)\r
			Stop_CDD_c1();\r
			break;\r
\r
		case 0x2:	// GET TOC INFORMATIONS\r
			switch(Pico_mcd->s68k_regs[0x38+10+3])\r
			{\r
				case 0x0:	// get current position (MSF format)\r
					Pico_mcd->cdd.Status = (Pico_mcd->cdd.Status & 0xFF00);\r
					Get_Pos_CDD_c20();\r
					break;\r
\r
				case 0x1:	// get elapsed time of current track played/scanned (relative MSF format)\r
					Pico_mcd->cdd.Status = (Pico_mcd->cdd.Status & 0xFF00) | 1;\r
					Get_Track_Pos_CDD_c21();\r
					break;\r
\r
				case 0x2:	// get current track in RS2-RS3\r
					Pico_mcd->cdd.Status =  (Pico_mcd->cdd.Status & 0xFF00) | 2;\r
					Get_Current_Track_CDD_c22();\r
					break;\r
\r
				case 0x3:	// get total length (MSF format)\r
					Pico_mcd->cdd.Status = (Pico_mcd->cdd.Status & 0xFF00) | 3;\r
					Get_Total_Lenght_CDD_c23();\r
					break;\r
\r
				case 0x4:	// first & last track number\r
					Pico_mcd->cdd.Status = (Pico_mcd->cdd.Status & 0xFF00) | 4;\r
					Get_First_Last_Track_CDD_c24();\r
					break;\r
\r
				case 0x5:	// get track addresse (MSF format)\r
					Pico_mcd->cdd.Status = (Pico_mcd->cdd.Status & 0xFF00) | 5;\r
					Get_Track_Adr_CDD_c25();\r
					break;\r
\r
				default :	// invalid, then we return status\r
					Pico_mcd->cdd.Status = (Pico_mcd->cdd.Status & 0xFF00) | 0xF;\r
					Get_Status_CDD_c0();\r
					break;\r
			}\r
			break;\r
\r
		case 0x3:	// READ\r
			Play_CDD_c3();\r
			break;\r
\r
		case 0x4:	// SEEK\r
			Seek_CDD_c4();\r
			break;\r
\r
		case 0x6:	// PAUSE/STOP\r
			Pause_CDD_c6();\r
			break;\r
\r
		case 0x7:	// RESUME\r
			Resume_CDD_c7();\r
			break;\r
\r
		case 0x8:	// FAST FOWARD\r
			Fast_Foward_CDD_c8();\r
			break;\r
\r
		case 0x9:	// FAST REWIND\r
			Fast_Rewind_CDD_c9();\r
			break;\r
\r
		case 0xA:	// RECOVER INITIAL STATE (?)\r
			CDD_cA();\r
			break;\r
\r
		case 0xC:	// CLOSE TRAY\r
			Close_Tray_CDD_cC();\r
			break;\r
\r
		case 0xD:	// OPEN TRAY\r
			Open_Tray_CDD_cD();\r
			break;\r
\r
		default:	// UNKNOWN\r
			CDD_Def();\r
			break;\r
	}\r
}\r
\r
Commit	Line	Data
bf098bc5	1	/***********************************************************\r
bf098bc5	2	* *\r
8b99ab90	3	* This source file was taken from the Gens project *\r
bf098bc5	4	* Written by Stéphane Dallongeville *\r
bf098bc5	5	* Copyright (c) 2002 by Stéphane Dallongeville *\r
6cadc2da	6	* Modified/adapted for PicoDrive by notaz, 2007 *\r
bf098bc5	7	* *\r
bf098bc5	8	***********************************************************/\r
cc68a136	9	\r
efcba75f	10	#include "../pico_int.h"\r
cc68a136	11	\r
cc68a136	12	#define CDC_DMA_SPEED 256\r
cc68a136	13	\r
cc68a136	14	\r
	15	static void CDD_Reset(void)\r
	16	{\r
	17	// Reseting CDD\r
	18	\r
	19	memset(Pico_mcd->s68k_regs+0x34, 0, 2*2); // CDD.Fader, CDD.Control\r
	20	Pico_mcd->cdd.Status = 0;\r
	21	Pico_mcd->cdd.Minute = 0;\r
	22	Pico_mcd->cdd.Seconde = 0;\r
	23	Pico_mcd->cdd.Frame = 0;\r
	24	Pico_mcd->cdd.Ext = 0;\r
	25	\r
	26	// clear receive status and transfer command\r
	27	memset(Pico_mcd->s68k_regs+0x38, 0, 20);\r
	28	Pico_mcd->s68k_regs[0x38+9] = 0xF; // Default checksum\r
	29	}\r
	30	\r
	31	\r
	32	static void CDC_Reset(void)\r
	33	{\r
	34	// Reseting CDC\r
	35	\r
5c69a605	36	memset(Pico_mcd->cdc.Buffer, 0, sizeof(Pico_mcd->cdc.Buffer));\r
cc68a136	37	\r
	38	Pico_mcd->cdc.COMIN = 0;\r
	39	Pico_mcd->cdc.IFSTAT = 0xFF;\r
	40	Pico_mcd->cdc.DAC.N = 0;\r
	41	Pico_mcd->cdc.DBC.N = 0;\r
	42	Pico_mcd->cdc.HEAD.N = 0x01000000;\r
	43	Pico_mcd->cdc.PT.N = 0;\r
	44	Pico_mcd->cdc.WA.N = 2352 * 2;\r
	45	Pico_mcd->cdc.STAT.N = 0x00000080;\r
	46	Pico_mcd->cdc.SBOUT = 0;\r
	47	Pico_mcd->cdc.IFCTRL = 0;\r
	48	Pico_mcd->cdc.CTRL.N = 0;\r
	49	\r
75736070	50	Pico_mcd->cdc.Decode_Reg_Read = 0;\r
c459aefd	51	Pico_mcd->scd.Status_CDC &= ~0x08;\r
cc68a136	52	}\r
	53	\r
	54	\r
eff55556	55	PICO_INTERNAL void LC89510_Reset(void)\r
cc68a136	56	{\r
	57	CDD_Reset();\r
	58	CDC_Reset();\r
	59	\r
cb4a513a	60	// clear DMA_Adr & Stop_Watch\r
cb4a513a	61	memset(Pico_mcd->s68k_regs + 0xA, 0, 4);\r
cc68a136	62	}\r
cc68a136	63	\r
cc68a136	64	\r
eff55556	65	PICO_INTERNAL void Update_CDC_TRansfer(int which)\r
bf098bc5	66	{\r
0a051f55	67	unsigned int DMA_Adr, dep, length;\r
bf098bc5	68	unsigned short *dest;\r
bf098bc5	69	unsigned char *src;\r
cc68a136	70	\r
ae214f1c	71	if (1) //Pico_mcd->cdc.DBC.N <= (CDC_DMA_SPEED * 2))\r
cc68a136	72	{\r
bf098bc5	73	length = (Pico_mcd->cdc.DBC.N + 1) >> 1;\r
c459aefd	74	Pico_mcd->scd.Status_CDC &= ~0x08; // Last transfer\r
bf098bc5	75	Pico_mcd->s68k_regs[4] \|= 0x80; // End data transfer\r
	76	Pico_mcd->s68k_regs[4] &= ~0x40; // no more data ready\r
	77	Pico_mcd->cdc.IFSTAT \|= 0x08; // No more data transfer in progress\r
cc68a136	78	\r
bf098bc5	79	if (Pico_mcd->cdc.IFCTRL & 0x40) // DTEIEN = Data Trasnfer End Interrupt Enable ?\r
cc68a136	80	{\r
	81	Pico_mcd->cdc.IFSTAT &= ~0x40;\r
	82	\r
ae214f1c	83	if (Pico_mcd->s68k_regs[0x33] & PCDS_IEN5)\r
bf098bc5	84	{\r
ca61ee42	85	elprintf(EL_INTS, "cdc DTE irq 5");\r
bf098bc5	86	SekInterruptS68k(5);\r
bf098bc5	87	}\r
cc68a136	88	}\r
cc68a136	89	}\r
bf098bc5	90	else length = CDC_DMA_SPEED;\r
bf098bc5	91	\r
cc68a136	92	\r
0a051f55	93	// TODO: dst bounds checking?\r
bf098bc5	94	src = Pico_mcd->cdc.Buffer + Pico_mcd->cdc.DAC.N;\r
cb4a513a	95	DMA_Adr = (Pico_mcd->s68k_regs[0xA]<<8) \| Pico_mcd->s68k_regs[0xB];\r
cc68a136	96	\r
bf098bc5	97	if (which == 7) // WORD RAM\r
cc68a136	98	{\r
bf098bc5	99	if (Pico_mcd->s68k_regs[3] & 4)\r
cc68a136	100	{\r
fa1e5e29	101	// test: Final Fight\r
fa1e5e29	102	int bank = !(Pico_mcd->s68k_regs[3]&1);\r
cb4a513a	103	dep = ((DMA_Adr & 0x3FFF) << 3);\r
bf098bc5	104	cdprintf("CD DMA # %04x -> word_ram1M # %06x, len=%i",\r
	105	Pico_mcd->cdc.DAC.N, dep, length);\r
	106	\r
fa1e5e29	107	dest = (unsigned short *) (Pico_mcd->word_ram1M[bank] + dep);\r
bf098bc5	108	\r
0a051f55	109	memcpy16bswap(dest, src, length);\r
1cd356a3	110	\r
721cd396	111	/*{ // debug\r
fa1e5e29	112	unsigned char *b1 = Pico_mcd->word_ram1M[bank] + dep;\r
0a051f55	113	unsigned char b2 = (unsigned char )(dest+length) - 8;\r
1cd356a3	114	dprintf("%02x %02x %02x %02x .. %02x %02x %02x %02x",\r
1cd356a3	115	b1[0], b1[1], b1[4], b1[5], b2[0], b2[1], b2[4], b2[5]);\r
721cd396	116	}*/\r
cc68a136	117	}\r
bf098bc5	118	else\r
bf098bc5	119	{\r
cb4a513a	120	dep = ((DMA_Adr & 0x7FFF) << 3);\r
bf098bc5	121	cdprintf("CD DMA # %04x -> word_ram2M # %06x, len=%i",\r
bf098bc5	122	Pico_mcd->cdc.DAC.N, dep, length);\r
fa1e5e29	123	dest = (unsigned short *) (Pico_mcd->word_ram2M + dep);\r
cc68a136	124	\r
0a051f55	125	memcpy16bswap(dest, src, length);\r
1cd356a3	126	\r
721cd396	127	/*{ // debug\r
fa1e5e29	128	unsigned char *b1 = Pico_mcd->word_ram2M + dep;\r
0a051f55	129	unsigned char b2 = (unsigned char )(dest+length) - 4;\r
1cd356a3	130	dprintf("%02x %02x %02x %02x .. %02x %02x %02x %02x",\r
1cd356a3	131	b1[0], b1[1], b1[2], b1[3], b2[0], b2[1], b2[2], b2[3]);\r
721cd396	132	}*/\r
bf098bc5	133	}\r
cc68a136	134	}\r
0a051f55	135	else if (which == 4) // PCM RAM (check: popful Mail)\r
cc68a136	136	{\r
0a051f55	137	dep = (DMA_Adr & 0x03FF) << 2;\r
ca61ee42	138	cdprintf("CD DMA # %04x -> PCM[%i] # %04x, len=%i",\r
0a051f55	139	Pico_mcd->cdc.DAC.N, Pico_mcd->pcm.bank, dep, length);\r
	140	dest = (unsigned short *) (Pico_mcd->pcm_ram_b[Pico_mcd->pcm.bank] + dep);\r
	141	\r
	142	if (Pico_mcd->cdc.DAC.N & 1) /* unaligned src? */\r
	143	memcpy(dest, src, length*2);\r
	144	else memcpy16(dest, (unsigned short *) src, length);\r
bf098bc5	145	}\r
	146	else if (which == 5) // PRG RAM\r
	147	{\r
cb4a513a	148	dep = DMA_Adr << 3;\r
bf098bc5	149	dest = (unsigned short *) (Pico_mcd->prg_ram + dep);\r
	150	cdprintf("CD DMA # %04x -> prg_ram # %06x, len=%i",\r
	151	Pico_mcd->cdc.DAC.N, dep, length);\r
cc68a136	152	\r
0a051f55	153	memcpy16bswap(dest, src, length);\r
1cd356a3	154	\r
721cd396	155	/*{ // debug\r
1cd356a3	156	unsigned char *b1 = Pico_mcd->prg_ram + dep;\r
0a051f55	157	unsigned char b2 = (unsigned char )(dest+length) - 4;\r
1cd356a3	158	dprintf("%02x %02x %02x %02x .. %02x %02x %02x %02x",\r
1cd356a3	159	b1[0], b1[1], b1[2], b1[3], b2[0], b2[1], b2[2], b2[3]);\r
721cd396	160	}*/\r
cc68a136	161	}\r
cc68a136	162	\r
bf098bc5	163	length <<= 1;\r
bf098bc5	164	Pico_mcd->cdc.DAC.N = (Pico_mcd->cdc.DAC.N + length) & 0xFFFF;\r
c459aefd	165	if (Pico_mcd->scd.Status_CDC & 0x08) Pico_mcd->cdc.DBC.N -= length;\r
cc68a136	166	else Pico_mcd->cdc.DBC.N = 0;\r
1cd356a3	167	\r
	168	// update DMA_Adr\r
	169	length >>= 2;\r
	170	if (which != 4) length >>= 1;\r
	171	DMA_Adr += length;\r
	172	Pico_mcd->s68k_regs[0xA] = DMA_Adr >> 8;\r
	173	Pico_mcd->s68k_regs[0xB] = DMA_Adr;\r
cc68a136	174	}\r
cc68a136	175	\r
cc68a136	176	\r
eff55556	177	PICO_INTERNAL_ASM unsigned short Read_CDC_Host(int is_sub)\r
cc68a136	178	{\r
	179	int addr;\r
	180	\r
c459aefd	181	if (!(Pico_mcd->scd.Status_CDC & 0x08))\r
cc68a136	182	{\r
cc68a136	183	// Transfer data disabled\r
fa1e5e29	184	cdprintf("Read_CDC_Host FIXME: Transfer data disabled");\r
cc68a136	185	return 0;\r
	186	}\r
	187	\r
	188	if ((is_sub && (Pico_mcd->s68k_regs[4] & 7) != 3) \|\|\r
	189	(!is_sub && (Pico_mcd->s68k_regs[4] & 7) != 2))\r
	190	{\r
	191	// Wrong setting\r
fa1e5e29	192	cdprintf("Read_CDC_Host FIXME: Wrong setting");\r
cc68a136	193	return 0;\r
	194	}\r
	195	\r
	196	Pico_mcd->cdc.DBC.N -= 2;\r
	197	\r
	198	if (Pico_mcd->cdc.DBC.N <= 0)\r
	199	{\r
	200	Pico_mcd->cdc.DBC.N = 0;\r
c459aefd	201	Pico_mcd->scd.Status_CDC &= ~0x08; // Last transfer\r
cc68a136	202	Pico_mcd->s68k_regs[4] \|= 0x80; // End data transfer\r
	203	Pico_mcd->s68k_regs[4] &= ~0x40; // no more data ready\r
	204	Pico_mcd->cdc.IFSTAT \|= 0x08; // No more data transfer in progress\r
	205	\r
	206	if (Pico_mcd->cdc.IFCTRL & 0x40) // DTEIEN = Data Transfer End Interrupt Enable ?\r
	207	{\r
	208	Pico_mcd->cdc.IFSTAT &= ~0x40;\r
	209	\r
	210	if (Pico_mcd->s68k_regs[0x33]&(1<<5)) {\r
ca61ee42	211	elprintf(EL_INTS, "m68k: s68k irq 5");\r
cc68a136	212	SekInterruptS68k(5);\r
	213	}\r
	214	\r
c459aefd	215	cdprintf("CDC - DTE interrupt");\r
cc68a136	216	}\r
	217	}\r
	218	\r
	219	addr = Pico_mcd->cdc.DAC.N;\r
	220	Pico_mcd->cdc.DAC.N += 2;\r
c459aefd	221	\r
	222	cdprintf("Read_CDC_Host sub=%i d=%04x dac=%04x dbc=%04x", is_sub,\r
	223	(Pico_mcd->cdc.Buffer[addr]<<8) \| Pico_mcd->cdc.Buffer[addr+1], Pico_mcd->cdc.DAC.N, Pico_mcd->cdc.DBC.N);\r
	224	\r
cc68a136	225	return (Pico_mcd->cdc.Buffer[addr]<<8) \| Pico_mcd->cdc.Buffer[addr+1];\r
cc68a136	226	}\r
	227	\r
	228	\r
eff55556	229	PICO_INTERNAL void CDC_Update_Header(void)\r
cc68a136	230	{\r
	231	if (Pico_mcd->cdc.CTRL.B.B1 & 0x01) // Sub-Header wanted ?\r
	232	{\r
	233	Pico_mcd->cdc.HEAD.B.B0 = 0;\r
	234	Pico_mcd->cdc.HEAD.B.B1 = 0;\r
	235	Pico_mcd->cdc.HEAD.B.B2 = 0;\r
	236	Pico_mcd->cdc.HEAD.B.B3 = 0;\r
	237	}\r
	238	else\r
	239	{\r
	240	_msf MSF;\r
	241	\r
	242	LBA_to_MSF(Pico_mcd->scd.Cur_LBA, &MSF);\r
	243	\r
	244	Pico_mcd->cdc.HEAD.B.B0 = INT_TO_BCDB(MSF.M);\r
	245	Pico_mcd->cdc.HEAD.B.B1 = INT_TO_BCDB(MSF.S);\r
	246	Pico_mcd->cdc.HEAD.B.B2 = INT_TO_BCDB(MSF.F);\r
	247	Pico_mcd->cdc.HEAD.B.B3 = 0x01;\r
	248	}\r
	249	}\r
	250	\r
	251	\r
eff55556	252	PICO_INTERNAL unsigned char CDC_Read_Reg(void)\r
cc68a136	253	{\r
	254	unsigned char ret;\r
	255	\r
cc68a136	256	switch(Pico_mcd->s68k_regs[5] & 0xF)\r
	257	{\r
	258	case 0x0: // COMIN\r
c459aefd	259	cdprintf("CDC read reg 00 = %.2X", Pico_mcd->cdc.COMIN);\r
cc68a136	260	\r
	261	Pico_mcd->s68k_regs[5] = 0x1;\r
	262	return Pico_mcd->cdc.COMIN;\r
	263	\r
	264	case 0x1: // IFSTAT\r
c459aefd	265	cdprintf("CDC read reg 01 = %.2X", Pico_mcd->cdc.IFSTAT);\r
cc68a136	266	\r
75736070	267	Pico_mcd->cdc.Decode_Reg_Read \|= (1 << 1); // Reg 1 (decoding)\r
cc68a136	268	Pico_mcd->s68k_regs[5] = 0x2;\r
	269	return Pico_mcd->cdc.IFSTAT;\r
	270	\r
	271	case 0x2: // DBCL\r
c459aefd	272	cdprintf("CDC read reg 02 = %.2X", Pico_mcd->cdc.DBC.B.L);\r
cc68a136	273	\r
	274	Pico_mcd->s68k_regs[5] = 0x3;\r
	275	return Pico_mcd->cdc.DBC.B.L;\r
	276	\r
	277	case 0x3: // DBCH\r
c459aefd	278	cdprintf("CDC read reg 03 = %.2X", Pico_mcd->cdc.DBC.B.H);\r
cc68a136	279	\r
	280	Pico_mcd->s68k_regs[5] = 0x4;\r
	281	return Pico_mcd->cdc.DBC.B.H;\r
	282	\r
	283	case 0x4: // HEAD0\r
c459aefd	284	cdprintf("CDC read reg 04 = %.2X", Pico_mcd->cdc.HEAD.B.B0);\r
cc68a136	285	\r
75736070	286	Pico_mcd->cdc.Decode_Reg_Read \|= (1 << 4); // Reg 4 (decoding)\r
cc68a136	287	Pico_mcd->s68k_regs[5] = 0x5;\r
	288	return Pico_mcd->cdc.HEAD.B.B0;\r
	289	\r
	290	case 0x5: // HEAD1\r
c459aefd	291	cdprintf("CDC read reg 05 = %.2X", Pico_mcd->cdc.HEAD.B.B1);\r
cc68a136	292	\r
75736070	293	Pico_mcd->cdc.Decode_Reg_Read \|= (1 << 5); // Reg 5 (decoding)\r
cc68a136	294	Pico_mcd->s68k_regs[5] = 0x6;\r
	295	return Pico_mcd->cdc.HEAD.B.B1;\r
	296	\r
	297	case 0x6: // HEAD2\r
c459aefd	298	cdprintf("CDC read reg 06 = %.2X", Pico_mcd->cdc.HEAD.B.B2);\r
cc68a136	299	\r
75736070	300	Pico_mcd->cdc.Decode_Reg_Read \|= (1 << 6); // Reg 6 (decoding)\r
cc68a136	301	Pico_mcd->s68k_regs[5] = 0x7;\r
	302	return Pico_mcd->cdc.HEAD.B.B2;\r
	303	\r
	304	case 0x7: // HEAD3\r
c459aefd	305	cdprintf("CDC read reg 07 = %.2X", Pico_mcd->cdc.HEAD.B.B3);\r
cc68a136	306	\r
75736070	307	Pico_mcd->cdc.Decode_Reg_Read \|= (1 << 7); // Reg 7 (decoding)\r
cc68a136	308	Pico_mcd->s68k_regs[5] = 0x8;\r
	309	return Pico_mcd->cdc.HEAD.B.B3;\r
	310	\r
	311	case 0x8: // PTL\r
c459aefd	312	cdprintf("CDC read reg 08 = %.2X", Pico_mcd->cdc.PT.B.L);\r
cc68a136	313	\r
75736070	314	Pico_mcd->cdc.Decode_Reg_Read \|= (1 << 8); // Reg 8 (decoding)\r
cc68a136	315	Pico_mcd->s68k_regs[5] = 0x9;\r
	316	return Pico_mcd->cdc.PT.B.L;\r
	317	\r
	318	case 0x9: // PTH\r
c459aefd	319	cdprintf("CDC read reg 09 = %.2X", Pico_mcd->cdc.PT.B.H);\r
cc68a136	320	\r
75736070	321	Pico_mcd->cdc.Decode_Reg_Read \|= (1 << 9); // Reg 9 (decoding)\r
cc68a136	322	Pico_mcd->s68k_regs[5] = 0xA;\r
	323	return Pico_mcd->cdc.PT.B.H;\r
	324	\r
	325	case 0xA: // WAL\r
c459aefd	326	cdprintf("CDC read reg 10 = %.2X", Pico_mcd->cdc.WA.B.L);\r
cc68a136	327	\r
	328	Pico_mcd->s68k_regs[5] = 0xB;\r
	329	return Pico_mcd->cdc.WA.B.L;\r
	330	\r
	331	case 0xB: // WAH\r
c459aefd	332	cdprintf("CDC read reg 11 = %.2X", Pico_mcd->cdc.WA.B.H);\r
cc68a136	333	\r
	334	Pico_mcd->s68k_regs[5] = 0xC;\r
	335	return Pico_mcd->cdc.WA.B.H;\r
	336	\r
	337	case 0xC: // STAT0\r
c459aefd	338	cdprintf("CDC read reg 12 = %.2X", Pico_mcd->cdc.STAT.B.B0);\r
cc68a136	339	\r
75736070	340	Pico_mcd->cdc.Decode_Reg_Read \|= (1 << 12); // Reg 12 (decoding)\r
cc68a136	341	Pico_mcd->s68k_regs[5] = 0xD;\r
	342	return Pico_mcd->cdc.STAT.B.B0;\r
	343	\r
	344	case 0xD: // STAT1\r
c459aefd	345	cdprintf("CDC read reg 13 = %.2X", Pico_mcd->cdc.STAT.B.B1);\r
cc68a136	346	\r
75736070	347	Pico_mcd->cdc.Decode_Reg_Read \|= (1 << 13); // Reg 13 (decoding)\r
cc68a136	348	Pico_mcd->s68k_regs[5] = 0xE;\r
	349	return Pico_mcd->cdc.STAT.B.B1;\r
	350	\r
	351	case 0xE: // STAT2\r
c459aefd	352	cdprintf("CDC read reg 14 = %.2X", Pico_mcd->cdc.STAT.B.B2);\r
cc68a136	353	\r
75736070	354	Pico_mcd->cdc.Decode_Reg_Read \|= (1 << 14); // Reg 14 (decoding)\r
cc68a136	355	Pico_mcd->s68k_regs[5] = 0xF;\r
	356	return Pico_mcd->cdc.STAT.B.B2;\r
	357	\r
	358	case 0xF: // STAT3\r
c459aefd	359	cdprintf("CDC read reg 15 = %.2X", Pico_mcd->cdc.STAT.B.B3);\r
cc68a136	360	\r
	361	ret = Pico_mcd->cdc.STAT.B.B3;\r
	362	Pico_mcd->cdc.IFSTAT \|= 0x20; // decoding interrupt flag cleared\r
	363	if ((Pico_mcd->cdc.CTRL.B.B0 & 0x80) && (Pico_mcd->cdc.IFCTRL & 0x20))\r
	364	{\r
75736070	365	if ((Pico_mcd->cdc.Decode_Reg_Read & 0x73F2) == 0x73F2)\r
cc68a136	366	Pico_mcd->cdc.STAT.B.B3 = 0x80;\r
	367	}\r
	368	return ret;\r
	369	}\r
	370	\r
	371	return 0;\r
	372	}\r
	373	\r
	374	\r
eff55556	375	PICO_INTERNAL void CDC_Write_Reg(unsigned char Data)\r
cc68a136	376	{\r
c459aefd	377	cdprintf("CDC write reg%02d = %.2X", Pico_mcd->s68k_regs[5] & 0xF, Data);\r
cc68a136	378	\r
	379	switch (Pico_mcd->s68k_regs[5] & 0xF)\r
	380	{\r
	381	case 0x0: // SBOUT\r
	382	Pico_mcd->s68k_regs[5] = 0x1;\r
	383	Pico_mcd->cdc.SBOUT = Data;\r
	384	\r
	385	break;\r
	386	\r
	387	case 0x1: // IFCTRL\r
	388	Pico_mcd->s68k_regs[5] = 0x2;\r
	389	Pico_mcd->cdc.IFCTRL = Data;\r
	390	\r
	391	if ((Pico_mcd->cdc.IFCTRL & 0x02) == 0) // Stop data transfer\r
	392	{\r
	393	Pico_mcd->cdc.DBC.N = 0;\r
c459aefd	394	Pico_mcd->scd.Status_CDC &= ~0x08;\r
cc68a136	395	Pico_mcd->cdc.IFSTAT \|= 0x08; // No more data transfer in progress\r
	396	}\r
	397	break;\r
	398	\r
	399	case 0x2: // DBCL\r
	400	Pico_mcd->s68k_regs[5] = 0x3;\r
	401	Pico_mcd->cdc.DBC.B.L = Data;\r
	402	\r
	403	break;\r
	404	\r
	405	case 0x3: // DBCH\r
	406	Pico_mcd->s68k_regs[5] = 0x4;\r
	407	Pico_mcd->cdc.DBC.B.H = Data;\r
	408	\r
	409	break;\r
	410	\r
	411	case 0x4: // DACL\r
	412	Pico_mcd->s68k_regs[5] = 0x5;\r
	413	Pico_mcd->cdc.DAC.B.L = Data;\r
	414	\r
	415	break;\r
	416	\r
	417	case 0x5: // DACH\r
	418	Pico_mcd->s68k_regs[5] = 0x6;\r
	419	Pico_mcd->cdc.DAC.B.H = Data;\r
	420	\r
	421	break;\r
	422	\r
	423	case 0x6: // DTTRG\r
	424	if (Pico_mcd->cdc.IFCTRL & 0x02) // Data transfer enable ?\r
	425	{\r
	426	Pico_mcd->cdc.IFSTAT &= ~0x08; // Data transfer in progress\r
c459aefd	427	Pico_mcd->scd.Status_CDC \|= 0x08; // Data transfer in progress\r
cc68a136	428	Pico_mcd->s68k_regs[4] &= 0x7F; // A data transfer start\r
cc68a136	429	\r
c459aefd	430	cdprintf("************ Starting Data Transfer *********");\r
cc68a136	431	cdprintf("RS0 = %.4X DAC = %.4X DBC = %.4X DMA adr = %.4X\n\n", Pico_mcd->s68k_regs[4]<<8,\r
cb4a513a	432	Pico_mcd->cdc.DAC.N, Pico_mcd->cdc.DBC.N, (Pico_mcd->s68k_regs[0xA]<<8) \| Pico_mcd->s68k_regs[0xB]);\r
ae214f1c	433	\r
	434	// tmp\r
	435	{\r
	436	int ddx = Pico_mcd->s68k_regs[4] & 7;\r
	437	if (ddx < 2) break; // invalid\r
	438	if (ddx < 4) {\r
	439	Pico_mcd->s68k_regs[4] \|= 0x40; // Data set ready in host port\r
	440	break;\r
	441	}\r
	442	if (ddx == 6) break; // invalid\r
	443	\r
	444	pcd_event_schedule_s68k(PCD_EVENT_DMA, Pico_mcd->cdc.DBC.N / 2);\r
	445	}\r
cc68a136	446	}\r
	447	break;\r
	448	\r
	449	case 0x7: // DTACK\r
	450	Pico_mcd->cdc.IFSTAT \|= 0x40; // end data transfer interrupt flag cleared\r
	451	break;\r
	452	\r
	453	case 0x8: // WAL\r
	454	Pico_mcd->s68k_regs[5] = 0x9;\r
	455	Pico_mcd->cdc.WA.B.L = Data;\r
	456	\r
	457	break;\r
	458	\r
	459	case 0x9: // WAH\r
	460	Pico_mcd->s68k_regs[5] = 0xA;\r
	461	Pico_mcd->cdc.WA.B.H = Data;\r
	462	\r
	463	break;\r
	464	\r
	465	case 0xA: // CTRL0\r
	466	Pico_mcd->s68k_regs[5] = 0xB;\r
	467	Pico_mcd->cdc.CTRL.B.B0 = Data;\r
	468	\r
	469	break;\r
	470	\r
	471	case 0xB: // CTRL1\r
	472	Pico_mcd->s68k_regs[5] = 0xC;\r
	473	Pico_mcd->cdc.CTRL.B.B1 = Data;\r
	474	\r
	475	break;\r
	476	\r
	477	case 0xC: // PTL\r
	478	Pico_mcd->s68k_regs[5] = 0xD;\r
	479	Pico_mcd->cdc.PT.B.L = Data;\r
	480	\r
	481	break;\r
	482	\r
	483	case 0xD: // PTH\r
	484	Pico_mcd->s68k_regs[5] = 0xE;\r
	485	Pico_mcd->cdc.PT.B.H = Data;\r
	486	\r
	487	break;\r
	488	\r
	489	case 0xE: // CTRL2\r
	490	Pico_mcd->cdc.CTRL.B.B2 = Data;\r
	491	break;\r
	492	\r
	493	case 0xF: // RESET\r
	494	CDC_Reset();\r
	495	break;\r
	496	}\r
	497	}\r
	498	\r
	499	\r
	500	static int bswapwrite(int a, unsigned short d)\r
	501	{\r
	502	(unsigned short )(Pico_mcd->s68k_regs + a) = (d>>8)\|(d<<8);\r
	503	return d + (d >> 8);\r
	504	}\r
	505	\r
eff55556	506	PICO_INTERNAL void CDD_Export_Status(void)\r
cc68a136	507	{\r
	508	unsigned int csum;\r
	509	\r
	510	csum = bswapwrite( 0x38+0, Pico_mcd->cdd.Status);\r
	511	csum += bswapwrite( 0x38+2, Pico_mcd->cdd.Minute);\r
	512	csum += bswapwrite( 0x38+4, Pico_mcd->cdd.Seconde);\r
	513	csum += bswapwrite( 0x38+6, Pico_mcd->cdd.Frame);\r
	514	Pico_mcd->s68k_regs[0x38+8] = Pico_mcd->cdd.Ext;\r
	515	csum += Pico_mcd->cdd.Ext;\r
	516	Pico_mcd->s68k_regs[0x38+9] = ~csum & 0xf;\r
	517	\r
672ad671	518	Pico_mcd->s68k_regs[0x37] &= 3; // CDD.Control\r
cc68a136	519	\r
ae214f1c	520	if (Pico_mcd->s68k_regs[0x33] & PCDS_IEN4)\r
cc68a136	521	{\r
ca61ee42	522	elprintf(EL_INTS, "cdd export irq 4");\r
cc68a136	523	SekInterruptS68k(4);\r
	524	}\r
	525	\r
c459aefd	526	// cdprintf("CDD exported status\n");\r
c459aefd	527	cdprintf("out: Status=%.4X, Minute=%.4X, Second=%.4X, Frame=%.4X Checksum=%.4X",\r
cc68a136	528	(Pico_mcd->s68k_regs[0x38+0] << 8) \| Pico_mcd->s68k_regs[0x38+1],\r
	529	(Pico_mcd->s68k_regs[0x38+2] << 8) \| Pico_mcd->s68k_regs[0x38+3],\r
	530	(Pico_mcd->s68k_regs[0x38+4] << 8) \| Pico_mcd->s68k_regs[0x38+5],\r
	531	(Pico_mcd->s68k_regs[0x38+6] << 8) \| Pico_mcd->s68k_regs[0x38+7],\r
	532	(Pico_mcd->s68k_regs[0x38+8] << 8) \| Pico_mcd->s68k_regs[0x38+9]);\r
	533	}\r
	534	\r
	535	\r
eff55556	536	PICO_INTERNAL void CDD_Import_Command(void)\r
cc68a136	537	{\r
c459aefd	538	// cdprintf("CDD importing command\n");\r
c459aefd	539	cdprintf("in: Command=%.4X, Minute=%.4X, Second=%.4X, Frame=%.4X Checksum=%.4X",\r
cc68a136	540	(Pico_mcd->s68k_regs[0x38+10+0] << 8) \| Pico_mcd->s68k_regs[0x38+10+1],\r
	541	(Pico_mcd->s68k_regs[0x38+10+2] << 8) \| Pico_mcd->s68k_regs[0x38+10+3],\r
	542	(Pico_mcd->s68k_regs[0x38+10+4] << 8) \| Pico_mcd->s68k_regs[0x38+10+5],\r
	543	(Pico_mcd->s68k_regs[0x38+10+6] << 8) \| Pico_mcd->s68k_regs[0x38+10+7],\r
	544	(Pico_mcd->s68k_regs[0x38+10+8] << 8) \| Pico_mcd->s68k_regs[0x38+10+9]);\r
	545	\r
	546	switch (Pico_mcd->s68k_regs[0x38+10+0])\r
	547	{\r
	548	case 0x0: // STATUS (?)\r
	549	Get_Status_CDD_c0();\r
	550	break;\r
	551	\r
	552	case 0x1: // STOP ALL (?)\r
	553	Stop_CDD_c1();\r
	554	break;\r
	555	\r
	556	case 0x2: // GET TOC INFORMATIONS\r
	557	switch(Pico_mcd->s68k_regs[0x38+10+3])\r
	558	{\r
	559	case 0x0: // get current position (MSF format)\r
	560	Pico_mcd->cdd.Status = (Pico_mcd->cdd.Status & 0xFF00);\r
	561	Get_Pos_CDD_c20();\r
	562	break;\r
	563	\r
	564	case 0x1: // get elapsed time of current track played/scanned (relative MSF format)\r
	565	Pico_mcd->cdd.Status = (Pico_mcd->cdd.Status & 0xFF00) \| 1;\r
	566	Get_Track_Pos_CDD_c21();\r
	567	break;\r
	568	\r
	569	case 0x2: // get current track in RS2-RS3\r
	570	Pico_mcd->cdd.Status = (Pico_mcd->cdd.Status & 0xFF00) \| 2;\r
	571	Get_Current_Track_CDD_c22();\r
	572	break;\r
	573	\r
bf098bc5	574	case 0x3: // get total length (MSF format)\r
cc68a136	575	Pico_mcd->cdd.Status = (Pico_mcd->cdd.Status & 0xFF00) \| 3;\r
	576	Get_Total_Lenght_CDD_c23();\r
	577	break;\r
	578	\r
	579	case 0x4: // first & last track number\r
	580	Pico_mcd->cdd.Status = (Pico_mcd->cdd.Status & 0xFF00) \| 4;\r
	581	Get_First_Last_Track_CDD_c24();\r
	582	break;\r
	583	\r
	584	case 0x5: // get track addresse (MSF format)\r
	585	Pico_mcd->cdd.Status = (Pico_mcd->cdd.Status & 0xFF00) \| 5;\r
	586	Get_Track_Adr_CDD_c25();\r
	587	break;\r
	588	\r
	589	default : // invalid, then we return status\r
	590	Pico_mcd->cdd.Status = (Pico_mcd->cdd.Status & 0xFF00) \| 0xF;\r
	591	Get_Status_CDD_c0();\r
	592	break;\r
	593	}\r
	594	break;\r
	595	\r
	596	case 0x3: // READ\r
	597	Play_CDD_c3();\r
	598	break;\r
	599	\r
	600	case 0x4: // SEEK\r
	601	Seek_CDD_c4();\r
	602	break;\r
	603	\r
	604	case 0x6: // PAUSE/STOP\r
	605	Pause_CDD_c6();\r
	606	break;\r
	607	\r
	608	case 0x7: // RESUME\r
	609	Resume_CDD_c7();\r
	610	break;\r
	611	\r
	612	case 0x8: // FAST FOWARD\r
	613	Fast_Foward_CDD_c8();\r
	614	break;\r
	615	\r
	616	case 0x9: // FAST REWIND\r
	617	Fast_Rewind_CDD_c9();\r
	618	break;\r
	619	\r
	620	case 0xA: // RECOVER INITIAL STATE (?)\r
	621	CDD_cA();\r
	622	break;\r
	623	\r
	624	case 0xC: // CLOSE TRAY\r
	625	Close_Tray_CDD_cC();\r
	626	break;\r
	627	\r
	628	case 0xD: // OPEN TRAY\r
	629	Open_Tray_CDD_cD();\r
	630	break;\r
	631	\r
	632	default: // UNKNOWN\r
	633	CDD_Def();\r
	634	break;\r
	635	}\r
	636	}\r
	637	\r