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1/*\r
2 * PicoDrive - Internal Header File\r
3 * (c) Copyright Dave, 2004\r
4 * (C) notaz, 2006-2010\r
5 *\r
6 * This work is licensed under the terms of MAME license.\r
7 * See COPYING file in the top-level directory.\r
8 */\r
9\r
10#ifndef PICO_INTERNAL_INCLUDED\r
11#define PICO_INTERNAL_INCLUDED\r
12\r
13#include <stdio.h>\r
14#include <stdlib.h>\r
15#include <string.h>\r
16#include "pico.h"\r
17#include "carthw/carthw.h"\r
18\r
19//\r
20#define USE_POLL_DETECT\r
21\r
22#ifndef PICO_INTERNAL\r
23#define PICO_INTERNAL\r
24#endif\r
25#ifndef PICO_INTERNAL_ASM\r
26#define PICO_INTERNAL_ASM\r
27#endif\r
28\r
29// to select core, define EMU_C68K, EMU_M68K or EMU_F68K in your makefile or project\r
30\r
31#ifdef __cplusplus\r
32extern "C" {\r
33#endif\r
34\r
35\r
36// ----------------------- 68000 CPU -----------------------\r
37#ifdef EMU_C68K\r
38#include "../cpu/cyclone/Cyclone.h"\r
39extern struct Cyclone PicoCpuCM68k, PicoCpuCS68k;\r
40#define SekCyclesLeft PicoCpuCM68k.cycles // cycles left for this run\r
41#define SekCyclesLeftS68k PicoCpuCS68k.cycles\r
42#define SekPc (PicoCpuCM68k.pc-PicoCpuCM68k.membase)\r
43#define SekPcS68k (PicoCpuCS68k.pc-PicoCpuCS68k.membase)\r
44#define SekDar(x) (x < 8 ? PicoCpuCM68k.d[x] : PicoCpuCM68k.a[x - 8])\r
45#define SekDarS68k(x) (x < 8 ? PicoCpuCS68k.d[x] : PicoCpuCS68k.a[x - 8])\r
46#define SekSr CycloneGetSr(&PicoCpuCM68k)\r
47#define SekSrS68k CycloneGetSr(&PicoCpuCS68k)\r
48#define SekSetStop(x) { PicoCpuCM68k.state_flags&=~1; if (x) { PicoCpuCM68k.state_flags|=1; PicoCpuCM68k.cycles=0; } }\r
49#define SekSetStopS68k(x) { PicoCpuCS68k.state_flags&=~1; if (x) { PicoCpuCS68k.state_flags|=1; PicoCpuCS68k.cycles=0; } }\r
50#define SekIsStoppedM68k() (PicoCpuCM68k.state_flags&1)\r
51#define SekIsStoppedS68k() (PicoCpuCS68k.state_flags&1)\r
52#define SekShouldInterrupt() (PicoCpuCM68k.irq > (PicoCpuCM68k.srh&7))\r
53\r
54#define SekNotPolling PicoCpuCM68k.not_pol\r
55#define SekNotPollingS68k PicoCpuCS68k.not_pol\r
56\r
57#define SekInterrupt(i) PicoCpuCM68k.irq=i\r
58#define SekIrqLevel PicoCpuCM68k.irq\r
59\r
60#endif\r
61\r
62#ifdef EMU_F68K\r
63#include "../cpu/fame/fame.h"\r
64extern M68K_CONTEXT PicoCpuFM68k, PicoCpuFS68k;\r
65#define SekCyclesLeft PicoCpuFM68k.io_cycle_counter\r
66#define SekCyclesLeftS68k PicoCpuFS68k.io_cycle_counter\r
67#define SekPc fm68k_get_pc(&PicoCpuFM68k)\r
68#define SekPcS68k fm68k_get_pc(&PicoCpuFS68k)\r
69#define SekDar(x) (x < 8 ? PicoCpuFM68k.dreg[x].D : PicoCpuFM68k.areg[x - 8].D)\r
70#define SekDarS68k(x) (x < 8 ? PicoCpuFS68k.dreg[x].D : PicoCpuFS68k.areg[x - 8].D)\r
71#define SekSr PicoCpuFM68k.sr\r
72#define SekSrS68k PicoCpuFS68k.sr\r
73#define SekSetStop(x) { \\r
74 PicoCpuFM68k.execinfo &= ~FM68K_HALTED; \\r
75 if (x) { PicoCpuFM68k.execinfo |= FM68K_HALTED; PicoCpuFM68k.io_cycle_counter = 0; } \\r
76}\r
77#define SekSetStopS68k(x) { \\r
78 PicoCpuFS68k.execinfo &= ~FM68K_HALTED; \\r
79 if (x) { PicoCpuFS68k.execinfo |= FM68K_HALTED; PicoCpuFS68k.io_cycle_counter = 0; } \\r
80}\r
81#define SekIsStoppedM68k() (PicoCpuFM68k.execinfo&FM68K_HALTED)\r
82#define SekIsStoppedS68k() (PicoCpuFS68k.execinfo&FM68K_HALTED)\r
83#define SekShouldInterrupt() fm68k_would_interrupt()\r
84\r
85#define SekNotPolling PicoCpuFM68k.not_polling\r
86#define SekNotPollingS68k PicoCpuFS68k.not_polling\r
87\r
88#define SekInterrupt(irq) PicoCpuFM68k.interrupts[0]=irq\r
89#define SekIrqLevel PicoCpuFM68k.interrupts[0]\r
90\r
91#endif\r
92\r
93#ifdef EMU_M68K\r
94#include "../cpu/musashi/m68kcpu.h"\r
95extern m68ki_cpu_core PicoCpuMM68k, PicoCpuMS68k;\r
96#ifndef SekCyclesLeft\r
97#define SekCyclesLeft PicoCpuMM68k.cyc_remaining_cycles\r
98#define SekCyclesLeftS68k PicoCpuMS68k.cyc_remaining_cycles\r
99#define SekPc m68k_get_reg(&PicoCpuMM68k, M68K_REG_PC)\r
100#define SekPcS68k m68k_get_reg(&PicoCpuMS68k, M68K_REG_PC)\r
101#define SekDar(x) PicoCpuMM68k.dar[x]\r
102#define SekDarS68k(x) PicoCpuMS68k.dar[x]\r
103#define SekSr m68k_get_reg(&PicoCpuMM68k, M68K_REG_SR)\r
104#define SekSrS68k m68k_get_reg(&PicoCpuMS68k, M68K_REG_SR)\r
105#define SekSetStop(x) { \\r
106 if(x) { SET_CYCLES(0); PicoCpuMM68k.stopped=STOP_LEVEL_STOP; } \\r
107 else PicoCpuMM68k.stopped=0; \\r
108}\r
109#define SekSetStopS68k(x) { \\r
110 if(x) { SET_CYCLES(0); PicoCpuMS68k.stopped=STOP_LEVEL_STOP; } \\r
111 else PicoCpuMS68k.stopped=0; \\r
112}\r
113#define SekIsStoppedM68k() (PicoCpuMM68k.stopped==STOP_LEVEL_STOP)\r
114#define SekIsStoppedS68k() (PicoCpuMS68k.stopped==STOP_LEVEL_STOP)\r
115#define SekShouldInterrupt() (CPU_INT_LEVEL > FLAG_INT_MASK)\r
116\r
117#define SekNotPolling PicoCpuMM68k.not_polling\r
118#define SekNotPollingS68k PicoCpuMS68k.not_polling\r
119\r
120#define SekInterrupt(irq) { \\r
121 void *oldcontext = m68ki_cpu_p; \\r
122 m68k_set_context(&PicoCpuMM68k); \\r
123 m68k_set_irq(irq); \\r
124 m68k_set_context(oldcontext); \\r
125}\r
126#define SekIrqLevel (PicoCpuMM68k.int_level >> 8)\r
127\r
128#endif\r
129#endif // EMU_M68K\r
130\r
131// while running, cnt represents target of current timeslice\r
132// while not in SekRun(), it's actual cycles done\r
133// (but always use SekCyclesDone() if you need current position)\r
134// cnt may change if timeslice is ended prematurely or extended,\r
135// so we use SekCycleAim for the actual target\r
136extern unsigned int SekCycleCnt;\r
137extern unsigned int SekCycleAim;\r
138\r
139// number of cycles done (can be checked anywhere)\r
140#define SekCyclesDone() (SekCycleCnt - SekCyclesLeft)\r
141\r
142// burn cycles while not in SekRun() and while in\r
143#define SekCyclesBurn(c) SekCycleCnt += c\r
144#define SekCyclesBurnRun(c) { \\r
145 SekCyclesLeft -= c; \\r
146}\r
147\r
148// note: sometimes may extend timeslice to delay an irq\r
149#define SekEndRun(after) { \\r
150 SekCycleCnt -= SekCyclesLeft - (after); \\r
151 SekCyclesLeft = after; \\r
152}\r
153\r
154extern unsigned int SekCycleCntS68k;\r
155extern unsigned int SekCycleAimS68k;\r
156\r
157#define SekEndRunS68k(after) { \\r
158 if (SekCyclesLeftS68k > (after)) { \\r
159 SekCycleCntS68k -= SekCyclesLeftS68k - (after); \\r
160 SekCyclesLeftS68k = after; \\r
161 } \\r
162}\r
163\r
164#define SekCyclesDoneS68k() (SekCycleCntS68k - SekCyclesLeftS68k)\r
165\r
166// compare cycles, handling overflows\r
167// check if a > b\r
168#define CYCLES_GT(a, b) \\r
169 ((int)((a) - (b)) > 0)\r
170// check if a >= b\r
171#define CYCLES_GE(a, b) \\r
172 ((int)((a) - (b)) >= 0)\r
173\r
174// ----------------------- Z80 CPU -----------------------\r
175\r
176#if defined(_USE_DRZ80)\r
177#include "../cpu/DrZ80/drz80.h"\r
178\r
179extern struct DrZ80 drZ80;\r
180\r
181#define z80_run(cycles) ((cycles) - DrZ80Run(&drZ80, cycles))\r
182#define z80_run_nr(cycles) DrZ80Run(&drZ80, cycles)\r
183#define z80_int() drZ80.Z80_IRQ = 1\r
184#define z80_int() drZ80.Z80_IRQ = 1\r
185#define z80_nmi() drZ80.Z80IF |= 8\r
186\r
187#define z80_cyclesLeft drZ80.cycles\r
188#define z80_subCLeft(c) drZ80.cycles -= c\r
189#define z80_pc() (drZ80.Z80PC - drZ80.Z80PC_BASE)\r
190\r
191#elif defined(_USE_CZ80)\r
192#include "../cpu/cz80/cz80.h"\r
193\r
194#define z80_run(cycles) Cz80_Exec(&CZ80, cycles)\r
195#define z80_run_nr(cycles) Cz80_Exec(&CZ80, cycles)\r
196#define z80_int() Cz80_Set_IRQ(&CZ80, 0, HOLD_LINE)\r
197#define z80_nmi() Cz80_Set_IRQ(&CZ80, IRQ_LINE_NMI, 0)\r
198\r
199#define z80_cyclesLeft (CZ80.ICount - CZ80.ExtraCycles)\r
200#define z80_subCLeft(c) CZ80.ICount -= c\r
201#define z80_pc() Cz80_Get_Reg(&CZ80, CZ80_PC)\r
202\r
203#else\r
204\r
205#define z80_run(cycles) (cycles)\r
206#define z80_run_nr(cycles)\r
207#define z80_int()\r
208#define z80_nmi()\r
209\r
210#endif\r
211\r
212#define Z80_STATE_SIZE 0x60\r
213\r
214extern unsigned int last_z80_sync;\r
215extern int z80_cycle_cnt; /* 'done' z80 cycles before z80_run() */\r
216extern int z80_cycle_aim;\r
217extern int z80_scanline;\r
218extern int z80_scanline_cycles; /* cycles done until z80_scanline */\r
219\r
220#define z80_resetCycles() \\r
221 last_z80_sync = SekCyclesDone(); \\r
222 z80_cycle_cnt = z80_cycle_aim = z80_scanline = z80_scanline_cycles = 0;\r
223\r
224#define z80_cyclesDone() \\r
225 (z80_cycle_aim - z80_cyclesLeft)\r
226\r
227#define cycles_68k_to_z80(x) ((x)*957 >> 11)\r
228\r
229// ----------------------- SH2 CPU -----------------------\r
230\r
231#include "cpu/sh2/sh2.h"\r
232\r
233extern SH2 sh2s[2];\r
234#define msh2 sh2s[0]\r
235#define ssh2 sh2s[1]\r
236\r
237#ifndef DRC_SH2\r
238# define sh2_end_run(sh2, after_) do { \\r
239 if ((sh2)->icount > (after_)) { \\r
240 (sh2)->cycles_timeslice -= (sh2)->icount - (after_); \\r
241 (sh2)->icount = after_; \\r
242 } \\r
243} while (0)\r
244# define sh2_cycles_left(sh2) (sh2)->icount\r
245# define sh2_burn_cycles(sh2, n) (sh2)->icount -= n\r
246# define sh2_pc(sh2) (sh2)->ppc\r
247#else\r
248# define sh2_end_run(sh2, after_) do { \\r
249 int left_ = (signed int)(sh2)->sr >> 12; \\r
250 if (left_ > (after_)) { \\r
251 (sh2)->cycles_timeslice -= left_ - (after_); \\r
252 (sh2)->sr &= 0xfff; \\r
253 (sh2)->sr |= (after_) << 12; \\r
254 } \\r
255} while (0)\r
256# define sh2_cycles_left(sh2) ((signed int)(sh2)->sr >> 12)\r
257# define sh2_burn_cycles(sh2, n) (sh2)->sr -= ((n) << 12)\r
258# define sh2_pc(sh2) (sh2)->pc\r
259#endif\r
260\r
261#define sh2_cycles_done(sh2) ((int)(sh2)->cycles_timeslice - sh2_cycles_left(sh2))\r
262#define sh2_cycles_done_t(sh2) \\r
263 ((sh2)->m68krcycles_done * 3 + sh2_cycles_done(sh2))\r
264#define sh2_cycles_done_m68k(sh2) \\r
265 ((sh2)->m68krcycles_done + (sh2_cycles_done(sh2) / 3))\r
266\r
267#define sh2_reg(c, x) (c) ? ssh2.r[x] : msh2.r[x]\r
268#define sh2_gbr(c) (c) ? ssh2.gbr : msh2.gbr\r
269#define sh2_vbr(c) (c) ? ssh2.vbr : msh2.vbr\r
270#define sh2_sr(c) (((c) ? ssh2.sr : msh2.sr) & 0xfff)\r
271\r
272#define sh2_set_gbr(c, v) \\r
273 { if (c) ssh2.gbr = v; else msh2.gbr = v; }\r
274#define sh2_set_vbr(c, v) \\r
275 { if (c) ssh2.vbr = v; else msh2.vbr = v; }\r
276\r
277#define elprintf_sh2(sh2, w, f, ...) \\r
278 elprintf(w,"%csh2 "f,(sh2)->is_slave?'s':'m',##__VA_ARGS__)\r
279\r
280// ---------------------------------------------------------\r
281\r
282// main oscillator clock which controls timing\r
283#define OSC_NTSC 53693100\r
284#define OSC_PAL 53203424\r
285\r
286// PicoVideo.debug_p\r
287#define PVD_KILL_A (1 << 0)\r
288#define PVD_KILL_B (1 << 1)\r
289#define PVD_KILL_S_LO (1 << 2)\r
290#define PVD_KILL_S_HI (1 << 3)\r
291#define PVD_KILL_32X (1 << 4)\r
292#define PVD_FORCE_A (1 << 5)\r
293#define PVD_FORCE_B (1 << 6)\r
294#define PVD_FORCE_S (1 << 7)\r
295\r
296// PicoVideo.status, not part of real SR\r
297#define SR_PAL (1 << 0)\r
298#define SR_DMA (1 << 1)\r
299#define SR_HB (1 << 2)\r
300#define SR_VB (1 << 3)\r
301#define SR_ODD (1 << 4)\r
302#define SR_C (1 << 5)\r
303#define SR_SOVR (1 << 6)\r
304#define SR_F (1 << 7)\r
305#define SR_FULL (1 << 8)\r
306#define SR_EMPT (1 << 9)\r
307// not part of real SR\r
308#define PVS_ACTIVE (1 << 16)\r
309\r
310struct PicoVideo\r
311{\r
312 unsigned char reg[0x20];\r
313 unsigned int command; // 32-bit Command\r
314 unsigned char pending; // 1 if waiting for second half of 32-bit command\r
315 unsigned char type; // Command type (v/c/vsram read/write)\r
316 unsigned short addr; // Read/Write address\r
317 unsigned int status; // Status bits (SR) and extra flags\r
318 unsigned char pending_ints; // pending interrupts: ??VH????\r
319 signed char lwrite_cnt; // VDP write count during active display line\r
320 unsigned short v_counter; // V-counter\r
321 unsigned short debug; // raw debug register\r
322 unsigned char debug_p; // ... parsed: PVD_*\r
323 unsigned char addr_u; // bit16 of .addr\r
324 unsigned char hint_cnt;\r
325 unsigned char pad[0x0b];\r
326};\r
327\r
328struct PicoMisc\r
329{\r
330 unsigned char rotate;\r
331 unsigned char z80Run;\r
332 unsigned char padTHPhase[2]; // 02 phase of gamepad TH switches\r
333 unsigned short scanline; // 04 0 to 261||311\r
334 char dirtyPal; // 06 Is the palette dirty (1 - change @ this frame, 2 - some time before)\r
335 unsigned char hardware; // 07 Hardware value for country\r
336 unsigned char pal; // 08 1=PAL 0=NTSC\r
337 unsigned char sram_reg; // 09 SRAM reg. See SRR_* below\r
338 unsigned short z80_bank68k; // 0a\r
339 unsigned short pad0;\r
340 unsigned char ncart_in; // 0e !cart_in\r
341 unsigned char z80_reset; // 0f z80 reset held\r
342 unsigned char padDelay[2]; // 10 gamepad phase time outs, so we count a delay\r
343 unsigned short eeprom_addr; // EEPROM address register\r
344 unsigned char eeprom_cycle; // EEPROM cycle number\r
345 unsigned char eeprom_slave; // EEPROM slave word for X24C02 and better SRAMs\r
346 unsigned char eeprom_status;\r
347 unsigned char pad2;\r
348 unsigned short dma_xfers; // 18\r
349 unsigned char eeprom_wb[2]; // EEPROM latch/write buffer\r
350 unsigned int frame_count; // 1c for movies and idle det\r
351};\r
352\r
353struct PicoMS\r
354{\r
355 unsigned char carthw[0x10];\r
356 unsigned char io_ctl;\r
357 unsigned char nmi_state;\r
358 unsigned char pad[0x4e];\r
359};\r
360\r
361// emu state and data for the asm code\r
362struct PicoEState\r
363{\r
364 int DrawScanline;\r
365 int rendstatus;\r
366 void *DrawLineDest; // draw destination\r
367 unsigned char *HighCol;\r
368 int *HighPreSpr;\r
369 void *Pico_video;\r
370 void *Pico_vram;\r
371 int *PicoOpt;\r
372 unsigned char *Draw2FB;\r
373 unsigned short HighPal[0x100];\r
374};\r
375\r
376// some assembly stuff depend on these, do not touch!\r
377struct Pico\r
378{\r
379 unsigned char ram[0x10000]; // 0x00000 scratch ram\r
380 union { // vram is byteswapped for easier reads when drawing\r
381 unsigned short vram[0x8000]; // 0x10000\r
382 unsigned char vramb[0x4000]; // VRAM in SMS mode\r
383 };\r
384 unsigned char zram[0x2000]; // 0x20000 Z80 ram\r
385 unsigned char ioports[0x10]; // XXX: fix asm and mv\r
386 unsigned char pad[0xf0]; // unused\r
387 unsigned short cram[0x40]; // 0x22100\r
388 unsigned short vsram[0x40]; // 0x22180\r
389\r
390 unsigned char *rom; // 0x22200\r
391 unsigned int romsize; // 0x22204 (on 32bits)\r
392\r
393 struct PicoMisc m;\r
394 struct PicoVideo video;\r
395 struct PicoMS ms;\r
396 struct PicoEState est;\r
397};\r
398\r
399// sram\r
400#define SRR_MAPPED (1 << 0)\r
401#define SRR_READONLY (1 << 1)\r
402\r
403#define SRF_ENABLED (1 << 0)\r
404#define SRF_EEPROM (1 << 1)\r
405\r
406struct PicoSRAM\r
407{\r
408 unsigned char *data; // actual data\r
409 unsigned int start; // start address in 68k address space\r
410 unsigned int end;\r
411 unsigned char flags; // 0c: SRF_*\r
412 unsigned char unused2;\r
413 unsigned char changed;\r
414 unsigned char eeprom_type; // eeprom type: 0: 7bit (24C01), 2: 2 addr words (X24C02+), 3: 3 addr words\r
415 unsigned char unused3;\r
416 unsigned char eeprom_bit_cl; // bit number for cl\r
417 unsigned char eeprom_bit_in; // bit number for in\r
418 unsigned char eeprom_bit_out; // bit number for out\r
419 unsigned int size;\r
420};\r
421\r
422// MCD\r
423#define PCM_MIXBUF_LEN ((12500000 / 384) / 50 + 1)\r
424\r
425struct mcd_pcm\r
426{\r
427 unsigned char control; // reg7\r
428 unsigned char enabled; // reg8\r
429 unsigned char cur_ch;\r
430 unsigned char bank;\r
431 unsigned int update_cycles;\r
432\r
433 struct pcm_chan // 08, size 0x10\r
434 {\r
435 unsigned char regs[8];\r
436 unsigned int addr; // .08: played sample address\r
437 int pad;\r
438 } ch[8];\r
439};\r
440\r
441#define PCD_ST_S68K_RST 1\r
442\r
443struct mcd_misc\r
444{\r
445 unsigned short hint_vector;\r
446 unsigned char busreq; // not s68k_regs[1]\r
447 unsigned char s68k_pend_ints;\r
448 unsigned int state_flags; // 04\r
449 unsigned int stopwatch_base_c;\r
450 unsigned short m68k_poll_a;\r
451 unsigned short m68k_poll_cnt;\r
452 unsigned short s68k_poll_a;\r
453 unsigned short s68k_poll_cnt;\r
454 unsigned int s68k_poll_clk;\r
455 unsigned char bcram_reg; // 18: battery-backed RAM cart register\r
456 unsigned char dmna_ret_2m;\r
457 unsigned char need_sync;\r
458 unsigned char pad3;\r
459 int pad4[9];\r
460};\r
461\r
462typedef struct\r
463{\r
464 unsigned char bios[0x20000]; // 000000: 128K\r
465 union { // 020000: 512K\r
466 unsigned char prg_ram[0x80000];\r
467 unsigned char prg_ram_b[4][0x20000];\r
468 };\r
469 union { // 0a0000: 256K\r
470 struct {\r
471 unsigned char word_ram2M[0x40000];\r
472 unsigned char unused0[0x20000];\r
473 };\r
474 struct {\r
475 unsigned char unused1[0x20000];\r
476 unsigned char word_ram1M[2][0x20000];\r
477 };\r
478 };\r
479 union { // 100000: 64K\r
480 unsigned char pcm_ram[0x10000];\r
481 unsigned char pcm_ram_b[0x10][0x1000];\r
482 };\r
483 unsigned char s68k_regs[0x200]; // 110000: GA, not CPU regs\r
484 unsigned char bram[0x2000]; // 110200: 8K\r
485 struct mcd_misc m; // 112200: misc\r
486 struct mcd_pcm pcm; // 112240:\r
487 void *cdda_stream;\r
488 int cdda_type;\r
489 int pcm_mixbuf[PCM_MIXBUF_LEN * 2];\r
490 int pcm_mixpos;\r
491 char pcm_mixbuf_dirty;\r
492 char pcm_regs_dirty;\r
493} mcd_state;\r
494\r
495// XXX: this will need to be reworked for cart+cd support.\r
496#define Pico_mcd ((mcd_state *)Pico.rom)\r
497\r
498// 32X\r
499#define P32XS_FM (1<<15)\r
500#define P32XS_nCART (1<< 8)\r
501#define P32XS_REN (1<< 7)\r
502#define P32XS_nRES (1<< 1)\r
503#define P32XS_ADEN (1<< 0)\r
504#define P32XS2_ADEN (1<< 9)\r
505#define P32XS_FULL (1<< 7) // DREQ FIFO full\r
506#define P32XS_68S (1<< 2)\r
507#define P32XS_DMA (1<< 1)\r
508#define P32XS_RV (1<< 0)\r
509\r
510#define P32XV_nPAL (1<<15) // VDP\r
511#define P32XV_PRI (1<< 7)\r
512#define P32XV_Mx (3<< 0) // display mode mask\r
513\r
514#define P32XV_SFT (1<< 0)\r
515\r
516#define P32XV_VBLK (1<<15)\r
517#define P32XV_HBLK (1<<14)\r
518#define P32XV_PEN (1<<13)\r
519#define P32XV_nFEN (1<< 1)\r
520#define P32XV_FS (1<< 0)\r
521\r
522#define P32XP_RTP (1<<7) // PWM control\r
523#define P32XP_FULL (1<<15) // PWM pulse\r
524#define P32XP_EMPTY (1<<14)\r
525\r
526#define P32XF_68KCPOLL (1 << 0)\r
527#define P32XF_68KVPOLL (1 << 1)\r
528#define P32XF_Z80_32X_IO (1 << 7) // z80 does 32x io\r
529\r
530#define P32XI_VRES (1 << 14/2) // IRL/2\r
531#define P32XI_VINT (1 << 12/2)\r
532#define P32XI_HINT (1 << 10/2)\r
533#define P32XI_CMD (1 << 8/2)\r
534#define P32XI_PWM (1 << 6/2)\r
535\r
536// peripheral reg access\r
537#define PREG8(regs,offs) ((unsigned char *)regs)[offs ^ 3]\r
538\r
539#define DMAC_FIFO_LEN (4*2)\r
540#define PWM_BUFF_LEN 1024 // in one channel samples\r
541\r
542#define SH2_DRCBLK_RAM_SHIFT 1\r
543#define SH2_DRCBLK_DA_SHIFT 1\r
544\r
545#define SH2_READ_SHIFT 25\r
546#define SH2_WRITE_SHIFT 25\r
547\r
548struct Pico32x\r
549{\r
550 unsigned short regs[0x20];\r
551 unsigned short vdp_regs[0x10]; // 0x40\r
552 unsigned short sh2_regs[3]; // 0x60\r
553 unsigned char pending_fb;\r
554 unsigned char dirty_pal;\r
555 unsigned int emu_flags;\r
556 unsigned char sh2irq_mask[2];\r
557 unsigned char sh2irqi[2]; // individual\r
558 unsigned int sh2irqs; // common irqs\r
559 unsigned short dmac_fifo[DMAC_FIFO_LEN];\r
560 unsigned int pad[4];\r
561 unsigned int dmac0_fifo_ptr;\r
562 unsigned short vdp_fbcr_fake;\r
563 unsigned short pad2;\r
564 unsigned char comm_dirty_68k;\r
565 unsigned char comm_dirty_sh2;\r
566 unsigned char pwm_irq_cnt;\r
567 unsigned char pad1;\r
568 unsigned short pwm_p[2]; // pwm pos in fifo\r
569 unsigned int pwm_cycle_p; // pwm play cursor (32x cycles)\r
570 unsigned int reserved[6];\r
571};\r
572\r
573struct Pico32xMem\r
574{\r
575 unsigned char sdram[0x40000];\r
576#ifdef DRC_SH2\r
577 unsigned short drcblk_ram[1 << (18 - SH2_DRCBLK_RAM_SHIFT)];\r
578#endif\r
579 unsigned short dram[2][0x20000/2]; // AKA fb\r
580 union {\r
581 unsigned char m68k_rom[0x100];\r
582 unsigned char m68k_rom_bank[0x10000]; // M68K_BANK_SIZE\r
583 };\r
584#ifdef DRC_SH2\r
585 unsigned short drcblk_da[2][1 << (12 - SH2_DRCBLK_DA_SHIFT)];\r
586#endif\r
587 union {\r
588 unsigned char b[0x800];\r
589 unsigned short w[0x800/2];\r
590 } sh2_rom_m;\r
591 union {\r
592 unsigned char b[0x400];\r
593 unsigned short w[0x400/2];\r
594 } sh2_rom_s;\r
595 unsigned short pal[0x100];\r
596 unsigned short pal_native[0x100]; // converted to native (for renderer)\r
597 signed short pwm[2*PWM_BUFF_LEN]; // PWM buffer for current frame\r
598 signed short pwm_current[2]; // current converted samples\r
599 unsigned short pwm_fifo[2][4]; // [0] - current raw, others - fifo entries\r
600};\r
601\r
602// area.c\r
603extern void (*PicoLoadStateHook)(void);\r
604\r
605typedef struct {\r
606 int chunk;\r
607 int size;\r
608 void *ptr;\r
609} carthw_state_chunk;\r
610extern carthw_state_chunk *carthw_chunks;\r
611#define CHUNK_CARTHW 64\r
612\r
613// cart.c\r
614extern int PicoCartResize(int newsize);\r
615extern void Byteswap(void *dst, const void *src, int len);\r
616extern void (*PicoCartMemSetup)(void);\r
617extern void (*PicoCartUnloadHook)(void);\r
618\r
619// debug.c\r
620int CM_compareRun(int cyc, int is_sub);\r
621\r
622// draw.c\r
623void PicoDrawInit(void);\r
624PICO_INTERNAL void PicoFrameStart(void);\r
625void PicoDrawSync(int to, int blank_last_line);\r
626void BackFill(int reg7, int sh, struct PicoEState *est);\r
627void FinalizeLine555(int sh, int line, struct PicoEState *est);\r
628extern int (*PicoScanBegin)(unsigned int num);\r
629extern int (*PicoScanEnd)(unsigned int num);\r
630#define MAX_LINE_SPRITES 29\r
631extern unsigned char HighLnSpr[240][3 + MAX_LINE_SPRITES];\r
632extern void *DrawLineDestBase;\r
633extern int DrawLineDestIncrement;\r
634\r
635// draw2.c\r
636void PicoDraw2Init(void);\r
637PICO_INTERNAL void PicoFrameFull();\r
638\r
639// mode4.c\r
640void PicoFrameStartMode4(void);\r
641void PicoLineMode4(int line);\r
642void PicoDoHighPal555M4(void);\r
643void PicoDrawSetOutputMode4(pdso_t which);\r
644\r
645// memory.c\r
646PICO_INTERNAL void PicoMemSetup(void);\r
647unsigned int PicoRead8_io(unsigned int a);\r
648unsigned int PicoRead16_io(unsigned int a);\r
649void PicoWrite8_io(unsigned int a, unsigned int d);\r
650void PicoWrite16_io(unsigned int a, unsigned int d);\r
651\r
652// pico/memory.c\r
653PICO_INTERNAL void PicoMemSetupPico(void);\r
654\r
655// cd/cdc.c\r
656void cdc_init(void);\r
657void cdc_reset(void);\r
658int cdc_context_save(unsigned char *state);\r
659int cdc_context_load(unsigned char *state);\r
660int cdc_context_load_old(unsigned char *state);\r
661void cdc_dma_update(void);\r
662int cdc_decoder_update(unsigned char header[4]);\r
663void cdc_reg_w(unsigned char data);\r
664unsigned char cdc_reg_r(void);\r
665unsigned short cdc_host_r(void);\r
666\r
667// cd/cdd.c\r
668void cdd_reset(void);\r
669int cdd_context_save(unsigned char *state);\r
670int cdd_context_load(unsigned char *state);\r
671int cdd_context_load_old(unsigned char *state);\r
672void cdd_read_data(unsigned char *dst);\r
673void cdd_read_audio(unsigned int samples);\r
674void cdd_update(void);\r
675void cdd_process(void);\r
676\r
677// cd/cd_image.c\r
678int load_cd_image(const char *cd_img_name, int *type);\r
679\r
680// cd/gfx.c\r
681void gfx_init(void);\r
682void gfx_start(unsigned int base);\r
683void gfx_update(unsigned int cycles);\r
684int gfx_context_save(unsigned char *state);\r
685int gfx_context_load(const unsigned char *state);\r
686\r
687// cd/gfx_dma.c\r
688void DmaSlowCell(unsigned int source, unsigned int a, int len, unsigned char inc);\r
689\r
690// cd/memory.c\r
691PICO_INTERNAL void PicoMemSetupCD(void);\r
692unsigned int PicoRead8_mcd_io(unsigned int a);\r
693unsigned int PicoRead16_mcd_io(unsigned int a);\r
694void PicoWrite8_mcd_io(unsigned int a, unsigned int d);\r
695void PicoWrite16_mcd_io(unsigned int a, unsigned int d);\r
696void pcd_state_loaded_mem(void);\r
697\r
698// pico.c\r
699extern struct Pico Pico;\r
700extern struct PicoSRAM SRam;\r
701extern int PicoPadInt[2];\r
702extern int emustatus;\r
703extern void (*PicoResetHook)(void);\r
704extern void (*PicoLineHook)(void);\r
705PICO_INTERNAL int CheckDMA(void);\r
706PICO_INTERNAL void PicoDetectRegion(void);\r
707PICO_INTERNAL void PicoSyncZ80(unsigned int m68k_cycles_done);\r
708\r
709// cd/mcd.c\r
710#define PCDS_IEN1 (1<<1)\r
711#define PCDS_IEN2 (1<<2)\r
712#define PCDS_IEN3 (1<<3)\r
713#define PCDS_IEN4 (1<<4)\r
714#define PCDS_IEN5 (1<<5)\r
715#define PCDS_IEN6 (1<<6)\r
716\r
717PICO_INTERNAL void PicoInitMCD(void);\r
718PICO_INTERNAL void PicoExitMCD(void);\r
719PICO_INTERNAL void PicoPowerMCD(void);\r
720PICO_INTERNAL int PicoResetMCD(void);\r
721PICO_INTERNAL void PicoFrameMCD(void);\r
722\r
723enum pcd_event {\r
724 PCD_EVENT_CDC,\r
725 PCD_EVENT_TIMER3,\r
726 PCD_EVENT_GFX,\r
727 PCD_EVENT_DMA,\r
728 PCD_EVENT_COUNT,\r
729};\r
730extern unsigned int pcd_event_times[PCD_EVENT_COUNT];\r
731void pcd_event_schedule(unsigned int now, enum pcd_event event, int after);\r
732void pcd_event_schedule_s68k(enum pcd_event event, int after);\r
733void pcd_prepare_frame(void);\r
734unsigned int pcd_cycles_m68k_to_s68k(unsigned int c);\r
735int pcd_sync_s68k(unsigned int m68k_target, int m68k_poll_sync);\r
736void pcd_run_cpus(int m68k_cycles);\r
737void pcd_soft_reset(void);\r
738void pcd_state_loaded(void);\r
739\r
740// cd/pcm.c\r
741void pcd_pcm_sync(unsigned int to);\r
742void pcd_pcm_update(int *buffer, int length, int stereo);\r
743void pcd_pcm_write(unsigned int a, unsigned int d);\r
744unsigned int pcd_pcm_read(unsigned int a);\r
745\r
746// pico/pico.c\r
747PICO_INTERNAL void PicoInitPico(void);\r
748PICO_INTERNAL void PicoReratePico(void);\r
749\r
750// pico/xpcm.c\r
751PICO_INTERNAL void PicoPicoPCMUpdate(short *buffer, int length, int stereo);\r
752PICO_INTERNAL void PicoPicoPCMReset(void);\r
753PICO_INTERNAL void PicoPicoPCMRerate(int xpcm_rate);\r
754\r
755// sek.c\r
756PICO_INTERNAL void SekInit(void);\r
757PICO_INTERNAL int SekReset(void);\r
758PICO_INTERNAL void SekState(int *data);\r
759PICO_INTERNAL void SekSetRealTAS(int use_real);\r
760PICO_INTERNAL void SekPackCpu(unsigned char *cpu, int is_sub);\r
761PICO_INTERNAL void SekUnpackCpu(const unsigned char *cpu, int is_sub);\r
762void SekStepM68k(void);\r
763void SekInitIdleDet(void);\r
764void SekFinishIdleDet(void);\r
765#if defined(CPU_CMP_R) || defined(CPU_CMP_W)\r
766void SekTrace(int is_s68k);\r
767#else\r
768#define SekTrace(x)\r
769#endif\r
770\r
771// cd/sek.c\r
772PICO_INTERNAL void SekInitS68k(void);\r
773PICO_INTERNAL int SekResetS68k(void);\r
774PICO_INTERNAL int SekInterruptS68k(int irq);\r
775void SekInterruptClearS68k(int irq);\r
776\r
777// sound/sound.c\r
778extern short cdda_out_buffer[2*1152];\r
779extern int PsndLen_exc_cnt;\r
780extern int PsndLen_exc_add;\r
781extern int timer_a_next_oflow, timer_a_step; // in z80 cycles\r
782extern int timer_b_next_oflow, timer_b_step;\r
783\r
784void cdda_start_play(int lba_base, int lba_offset, int lb_len);\r
785\r
786void ym2612_sync_timers(int z80_cycles, int mode_old, int mode_new);\r
787void ym2612_pack_state(void);\r
788void ym2612_unpack_state(void);\r
789\r
790#define TIMER_NO_OFLOW 0x70000000\r
791// tA = 72 * (1024 - NA) / M\r
792#define TIMER_A_TICK_ZCYCLES 17203\r
793// tB = 1152 * (256 - NA) / M\r
794#define TIMER_B_TICK_ZCYCLES 262800 // 275251 broken, see Dai Makaimura\r
795\r
796#define timers_cycle() \\r
797 if (timer_a_next_oflow > 0 && timer_a_next_oflow < TIMER_NO_OFLOW) \\r
798 timer_a_next_oflow -= Pico.m.pal ? 70938*256 : 59659*256; \\r
799 if (timer_b_next_oflow > 0 && timer_b_next_oflow < TIMER_NO_OFLOW) \\r
800 timer_b_next_oflow -= Pico.m.pal ? 70938*256 : 59659*256; \\r
801 ym2612_sync_timers(0, ym2612.OPN.ST.mode, ym2612.OPN.ST.mode);\r
802\r
803#define timers_reset() \\r
804 timer_a_next_oflow = timer_b_next_oflow = TIMER_NO_OFLOW; \\r
805 timer_a_step = TIMER_A_TICK_ZCYCLES * 1024; \\r
806 timer_b_step = TIMER_B_TICK_ZCYCLES * 256;\r
807\r
808\r
809// videoport.c\r
810extern int line_base_cycles;\r
811PICO_INTERNAL_ASM void PicoVideoWrite(unsigned int a,unsigned short d);\r
812PICO_INTERNAL_ASM unsigned int PicoVideoRead(unsigned int a);\r
813unsigned char PicoVideoRead8DataH(void);\r
814unsigned char PicoVideoRead8DataL(void);\r
815unsigned char PicoVideoRead8CtlH(void);\r
816unsigned char PicoVideoRead8CtlL(void);\r
817unsigned char PicoVideoRead8HV_H(void);\r
818unsigned char PicoVideoRead8HV_L(void);\r
819extern int (*PicoDmaHook)(unsigned int source, int len, unsigned short **base, unsigned int *mask);\r
820\r
821// misc.c\r
822PICO_INTERNAL_ASM void memcpy16(unsigned short *dest, unsigned short *src, int count);\r
823PICO_INTERNAL_ASM void memcpy16bswap(unsigned short *dest, void *src, int count);\r
824PICO_INTERNAL_ASM void memcpy32(void *dest, const void *src, int count); // 32bit word count\r
825PICO_INTERNAL_ASM void memset32(void *dest, int c, int count);\r
826\r
827// eeprom.c\r
828void EEPROM_write8(unsigned int a, unsigned int d);\r
829void EEPROM_write16(unsigned int d);\r
830unsigned int EEPROM_read(void);\r
831\r
832// z80 functionality wrappers\r
833PICO_INTERNAL void z80_init(void);\r
834PICO_INTERNAL void z80_pack(void *data);\r
835PICO_INTERNAL int z80_unpack(const void *data);\r
836PICO_INTERNAL void z80_reset(void);\r
837PICO_INTERNAL void z80_exit(void);\r
838\r
839// cd/misc.c\r
840PICO_INTERNAL_ASM void wram_2M_to_1M(unsigned char *m);\r
841PICO_INTERNAL_ASM void wram_1M_to_2M(unsigned char *m);\r
842\r
843// sound/sound.c\r
844PICO_INTERNAL void PsndReset(void);\r
845PICO_INTERNAL void PsndStartFrame(void);\r
846PICO_INTERNAL void PsndDoDAC(int line_to);\r
847PICO_INTERNAL void PsndDoPSG(int line_to);\r
848PICO_INTERNAL void PsndClear(void);\r
849PICO_INTERNAL void PsndGetSamples(int y);\r
850PICO_INTERNAL void PsndGetSamplesMS(void);\r
851extern int PsndDacLine, PsndPsgLine;\r
852\r
853// sms.c\r
854#ifndef NO_SMS\r
855void PicoPowerMS(void);\r
856void PicoResetMS(void);\r
857void PicoMemSetupMS(void);\r
858void PicoStateLoadedMS(void);\r
859void PicoFrameMS(void);\r
860void PicoFrameDrawOnlyMS(void);\r
861#else\r
862#define PicoPowerMS()\r
863#define PicoResetMS()\r
864#define PicoMemSetupMS()\r
865#define PicoStateLoadedMS()\r
866#define PicoFrameMS()\r
867#define PicoFrameDrawOnlyMS()\r
868#endif\r
869\r
870// 32x/32x.c\r
871#ifndef NO_32X\r
872extern struct Pico32x Pico32x;\r
873enum p32x_event {\r
874 P32X_EVENT_PWM,\r
875 P32X_EVENT_FILLEND,\r
876 P32X_EVENT_HINT,\r
877 P32X_EVENT_COUNT,\r
878};\r
879extern unsigned int p32x_event_times[P32X_EVENT_COUNT];\r
880\r
881void Pico32xInit(void);\r
882void PicoPower32x(void);\r
883void PicoReset32x(void);\r
884void Pico32xStartup(void);\r
885void PicoUnload32x(void);\r
886void PicoFrame32x(void);\r
887void Pico32xStateLoaded(int is_early);\r
888void p32x_sync_sh2s(unsigned int m68k_target);\r
889void p32x_sync_other_sh2(SH2 *sh2, unsigned int m68k_target);\r
890void p32x_update_irls(SH2 *active_sh2, int m68k_cycles);\r
891void p32x_trigger_irq(SH2 *sh2, int m68k_cycles, unsigned int mask);\r
892void p32x_update_cmd_irq(SH2 *sh2, int m68k_cycles);\r
893void p32x_reset_sh2s(void);\r
894void p32x_event_schedule(unsigned int now, enum p32x_event event, int after);\r
895void p32x_event_schedule_sh2(SH2 *sh2, enum p32x_event event, int after);\r
896void p32x_schedule_hint(SH2 *sh2, int m68k_cycles);\r
897\r
898// 32x/memory.c\r
899struct Pico32xMem *Pico32xMem;\r
900unsigned int PicoRead8_32x(unsigned int a);\r
901unsigned int PicoRead16_32x(unsigned int a);\r
902void PicoWrite8_32x(unsigned int a, unsigned int d);\r
903void PicoWrite16_32x(unsigned int a, unsigned int d);\r
904void PicoMemSetup32x(void);\r
905void Pico32xSwapDRAM(int b);\r
906void Pico32xMemStateLoaded(void);\r
907void p32x_m68k_poll_event(unsigned int flags);\r
908void p32x_sh2_poll_event(SH2 *sh2, unsigned int flags, unsigned int m68k_cycles);\r
909\r
910// 32x/draw.c\r
911void PicoDrawSetOutFormat32x(pdso_t which, int use_32x_line_mode);\r
912void FinalizeLine32xRGB555(int sh, int line, struct PicoEState *est);\r
913void PicoDraw32xLayer(int offs, int lines, int mdbg);\r
914void PicoDraw32xLayerMdOnly(int offs, int lines);\r
915extern int (*PicoScan32xBegin)(unsigned int num);\r
916extern int (*PicoScan32xEnd)(unsigned int num);\r
917enum {\r
918 PDM32X_OFF,\r
919 PDM32X_32X_ONLY,\r
920 PDM32X_BOTH,\r
921};\r
922extern int Pico32xDrawMode;\r
923\r
924// 32x/pwm.c\r
925unsigned int p32x_pwm_read16(unsigned int a, SH2 *sh2,\r
926 unsigned int m68k_cycles);\r
927void p32x_pwm_write16(unsigned int a, unsigned int d,\r
928 SH2 *sh2, unsigned int m68k_cycles);\r
929void p32x_pwm_update(int *buf32, int length, int stereo);\r
930void p32x_pwm_ctl_changed(void);\r
931void p32x_pwm_schedule(unsigned int m68k_now);\r
932void p32x_pwm_schedule_sh2(SH2 *sh2);\r
933void p32x_pwm_sync_to_sh2(SH2 *sh2);\r
934void p32x_pwm_irq_event(unsigned int m68k_now);\r
935void p32x_pwm_state_loaded(void);\r
936\r
937// 32x/sh2soc.c\r
938void p32x_dreq0_trigger(void);\r
939void p32x_dreq1_trigger(void);\r
940void p32x_timers_recalc(void);\r
941void p32x_timers_do(unsigned int m68k_slice);\r
942void sh2_peripheral_reset(SH2 *sh2);\r
943unsigned int sh2_peripheral_read8(unsigned int a, SH2 *sh2);\r
944unsigned int sh2_peripheral_read16(unsigned int a, SH2 *sh2);\r
945unsigned int sh2_peripheral_read32(unsigned int a, SH2 *sh2);\r
946void REGPARM(3) sh2_peripheral_write8(unsigned int a, unsigned int d, SH2 *sh2);\r
947void REGPARM(3) sh2_peripheral_write16(unsigned int a, unsigned int d, SH2 *sh2);\r
948void REGPARM(3) sh2_peripheral_write32(unsigned int a, unsigned int d, SH2 *sh2);\r
949\r
950#else\r
951#define Pico32xInit()\r
952#define PicoPower32x()\r
953#define PicoReset32x()\r
954#define PicoFrame32x()\r
955#define PicoUnload32x()\r
956#define Pico32xStateLoaded()\r
957#define FinalizeLine32xRGB555 NULL\r
958#define p32x_pwm_update(...)\r
959#define p32x_timers_recalc()\r
960#endif\r
961\r
962/* avoid dependency on newer glibc */\r
963static __inline int isspace_(int c)\r
964{\r
965 return (0x09 <= c && c <= 0x0d) || c == ' ';\r
966}\r
967\r
968#ifndef ARRAY_SIZE\r
969#define ARRAY_SIZE(x) (sizeof(x) / sizeof(x[0]))\r
970#endif\r
971\r
972// emulation event logging\r
973#ifndef EL_LOGMASK\r
974# ifdef __x86_64__ // HACK\r
975# define EL_LOGMASK (EL_STATUS|EL_IDLE|EL_ANOMALY)\r
976# else\r
977# define EL_LOGMASK (EL_STATUS)\r
978# endif\r
979#endif\r
980\r
981#define EL_HVCNT 0x00000001 /* hv counter reads */\r
982#define EL_SR 0x00000002 /* SR reads */\r
983#define EL_INTS 0x00000004 /* ints and acks */\r
984#define EL_YMTIMER 0x00000008 /* ym2612 timer stuff */\r
985#define EL_INTSW 0x00000010 /* log irq switching on/off */\r
986#define EL_ASVDP 0x00000020 /* VDP accesses during active scan */\r
987#define EL_VDPDMA 0x00000040 /* VDP DMA transfers and their timing */\r
988#define EL_BUSREQ 0x00000080 /* z80 busreq r/w or reset w */\r
989#define EL_Z80BNK 0x00000100 /* z80 i/o through bank area */\r
990#define EL_SRAMIO 0x00000200 /* sram i/o */\r
991#define EL_EEPROM 0x00000400 /* eeprom debug */\r
992#define EL_UIO 0x00000800 /* unmapped i/o */\r
993#define EL_IO 0x00001000 /* all i/o */\r
994#define EL_CDPOLL 0x00002000 /* MCD: log poll detection */\r
995#define EL_SVP 0x00004000 /* SVP stuff */\r
996#define EL_PICOHW 0x00008000 /* Pico stuff */\r
997#define EL_IDLE 0x00010000 /* idle loop det. */\r
998#define EL_CDREGS 0x00020000 /* MCD: register access */\r
999#define EL_CDREG3 0x00040000 /* MCD: register 3 only */\r
1000#define EL_32X 0x00080000\r
1001#define EL_PWM 0x00100000 /* 32X PWM stuff (LOTS of output) */\r
1002#define EL_32XP 0x00200000 /* 32X peripherals */\r
1003#define EL_CD 0x00400000 /* MCD */\r
1004\r
1005#define EL_STATUS 0x40000000 /* status messages */\r
1006#define EL_ANOMALY 0x80000000 /* some unexpected conditions (during emulation) */\r
1007\r
1008#if EL_LOGMASK\r
1009#define elprintf(w,f,...) \\r
1010do { \\r
1011 if ((w) & EL_LOGMASK) \\r
1012 lprintf("%05i:%03i: " f "\n",Pico.m.frame_count,Pico.m.scanline,##__VA_ARGS__); \\r
1013} while (0)\r
1014#elif defined(_MSC_VER)\r
1015#define elprintf\r
1016#else\r
1017#define elprintf(w,f,...)\r
1018#endif\r
1019\r
1020// profiling\r
1021#ifdef PPROF\r
1022#include <platform/linux/pprof.h>\r
1023#else\r
1024#define pprof_init()\r
1025#define pprof_finish()\r
1026#define pprof_start(x)\r
1027#define pprof_end(...)\r
1028#define pprof_end_sub(...)\r
1029#endif\r
1030\r
1031#ifdef EVT_LOG\r
1032enum evt {\r
1033 EVT_FRAME_START,\r
1034 EVT_NEXT_LINE,\r
1035 EVT_RUN_START,\r
1036 EVT_RUN_END,\r
1037 EVT_POLL_START,\r
1038 EVT_POLL_END,\r
1039 EVT_CNT\r
1040};\r
1041\r
1042enum evt_cpu {\r
1043 EVT_M68K,\r
1044 EVT_S68K,\r
1045 EVT_MSH2,\r
1046 EVT_SSH2,\r
1047 EVT_CPU_CNT\r
1048};\r
1049\r
1050void pevt_log(unsigned int cycles, enum evt_cpu c, enum evt e);\r
1051void pevt_dump(void);\r
1052\r
1053#define pevt_log_m68k(e) \\r
1054 pevt_log(SekCyclesDone(), EVT_M68K, e)\r
1055#define pevt_log_m68k_o(e) \\r
1056 pevt_log(SekCyclesDone(), EVT_M68K, e)\r
1057#define pevt_log_sh2(sh2, e) \\r
1058 pevt_log(sh2_cycles_done_m68k(sh2), EVT_MSH2 + (sh2)->is_slave, e)\r
1059#define pevt_log_sh2_o(sh2, e) \\r
1060 pevt_log((sh2)->m68krcycles_done, EVT_MSH2 + (sh2)->is_slave, e)\r
1061#else\r
1062#define pevt_log(c, e)\r
1063#define pevt_log_m68k(e)\r
1064#define pevt_log_m68k_o(e)\r
1065#define pevt_log_sh2(sh2, e)\r
1066#define pevt_log_sh2_o(sh2, e)\r
1067#define pevt_dump()\r
1068#endif\r
1069\r
1070// misc\r
1071#ifdef _MSC_VER\r
1072#define cdprintf\r
1073#else\r
1074#define cdprintf(x...)\r
1075#endif\r
1076\r
1077#if defined(__GNUC__) && defined(__i386__)\r
1078#define REGPARM(x) __attribute__((regparm(x)))\r
1079#else\r
1080#define REGPARM(x)\r
1081#endif\r
1082\r
1083#ifdef __GNUC__\r
1084#define NOINLINE __attribute__((noinline))\r
1085#else\r
1086#define NOINLINE\r
1087#endif\r
1088\r
1089#ifdef __cplusplus\r
1090} // End of extern "C"\r
1091#endif\r
1092\r
1093#endif // PICO_INTERNAL_INCLUDED\r
1094\r
fast MegaDrive/MegaCD/32X emulator