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fix clean build
[picodrive.git] / pico / pico_int.h
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1// Pico Library - Internal Header File\r
2\r
3// (c) Copyright 2004 Dave, All rights reserved.\r
4// (c) Copyright 2006-2008 Grazvydas "notaz" Ignotas, all rights reserved.\r
5// Free for non-commercial use.\r
6\r
7// For commercial use, separate licencing terms must be obtained.\r
8\r
9#ifndef PICO_INTERNAL_INCLUDED\r
10#define PICO_INTERNAL_INCLUDED\r
11\r
12#include <stdio.h>\r
13#include <stdlib.h>\r
14#include <string.h>\r
15#include "pico.h"\r
16#include "carthw/carthw.h"\r
17\r
18//\r
19#define USE_POLL_DETECT\r
20\r
21#ifndef PICO_INTERNAL\r
22#define PICO_INTERNAL\r
23#endif\r
24#ifndef PICO_INTERNAL_ASM\r
25#define PICO_INTERNAL_ASM\r
26#endif\r
27\r
28// to select core, define EMU_C68K, EMU_M68K or EMU_F68K in your makefile or project\r
29\r
30#ifdef __cplusplus\r
31extern "C" {\r
32#endif\r
33\r
34\r
35// ----------------------- 68000 CPU -----------------------\r
36#ifdef EMU_C68K\r
37#include "../cpu/Cyclone/Cyclone.h"\r
38extern struct Cyclone PicoCpuCM68k, PicoCpuCS68k;\r
39#define SekCyclesLeftNoMCD PicoCpuCM68k.cycles // cycles left for this run\r
40#define SekCyclesLeft \\r
41 (((PicoAHW&1) && (PicoOpt & POPT_EN_MCD_PSYNC)) ? (SekCycleAim-SekCycleCnt) : SekCyclesLeftNoMCD)\r
42#define SekCyclesLeftS68k \\r
43 ((PicoOpt & POPT_EN_MCD_PSYNC) ? (SekCycleAimS68k-SekCycleCntS68k) : PicoCpuCS68k.cycles)\r
44#define SekEndTimeslice(after) PicoCpuCM68k.cycles=after\r
45#define SekEndTimesliceS68k(after) PicoCpuCS68k.cycles=after\r
46#define SekPc (PicoCpuCM68k.pc-PicoCpuCM68k.membase)\r
47#define SekPcS68k (PicoCpuCS68k.pc-PicoCpuCS68k.membase)\r
48#define SekSetStop(x) { PicoCpuCM68k.state_flags&=~1; if (x) { PicoCpuCM68k.state_flags|=1; PicoCpuCM68k.cycles=0; } }\r
49#define SekSetStopS68k(x) { PicoCpuCS68k.state_flags&=~1; if (x) { PicoCpuCS68k.state_flags|=1; PicoCpuCS68k.cycles=0; } }\r
50#define SekIsStoppedS68k() (PicoCpuCS68k.state_flags&1)\r
51#define SekShouldInterrupt (PicoCpuCM68k.irq > (PicoCpuCM68k.srh&7))\r
52\r
53#define SekInterrupt(i) PicoCpuCM68k.irq=i\r
54\r
55#ifdef EMU_M68K\r
56#define EMU_CORE_DEBUG\r
57#endif\r
58#endif\r
59\r
60#ifdef EMU_F68K\r
61#include "../cpu/fame/fame.h"\r
62extern M68K_CONTEXT PicoCpuFM68k, PicoCpuFS68k;\r
63#define SekCyclesLeftNoMCD PicoCpuFM68k.io_cycle_counter\r
64#define SekCyclesLeft \\r
65 (((PicoAHW&1) && (PicoOpt & POPT_EN_MCD_PSYNC)) ? (SekCycleAim-SekCycleCnt) : SekCyclesLeftNoMCD)\r
66#define SekCyclesLeftS68k \\r
67 ((PicoOpt & POPT_EN_MCD_PSYNC) ? (SekCycleAimS68k-SekCycleCntS68k) : PicoCpuFS68k.io_cycle_counter)\r
68#define SekEndTimeslice(after) PicoCpuFM68k.io_cycle_counter=after\r
69#define SekEndTimesliceS68k(after) PicoCpuFS68k.io_cycle_counter=after\r
70#define SekPc fm68k_get_pc(&PicoCpuFM68k)\r
71#define SekPcS68k fm68k_get_pc(&PicoCpuFS68k)\r
72#define SekSetStop(x) { \\r
73 PicoCpuFM68k.execinfo &= ~FM68K_HALTED; \\r
74 if (x) { PicoCpuFM68k.execinfo |= FM68K_HALTED; PicoCpuFM68k.io_cycle_counter = 0; } \\r
75}\r
76#define SekSetStopS68k(x) { \\r
77 PicoCpuFS68k.execinfo &= ~FM68K_HALTED; \\r
78 if (x) { PicoCpuFS68k.execinfo |= FM68K_HALTED; PicoCpuFS68k.io_cycle_counter = 0; } \\r
79}\r
80#define SekIsStoppedS68k() (PicoCpuFS68k.execinfo&FM68K_HALTED)\r
81#define SekShouldInterrupt fm68k_would_interrupt()\r
82\r
83#define SekInterrupt(irq) PicoCpuFM68k.interrupts[0]=irq\r
84\r
85#ifdef EMU_M68K\r
86#define EMU_CORE_DEBUG\r
87#endif\r
88#endif\r
89\r
90#ifdef EMU_M68K\r
91#include "../cpu/musashi/m68kcpu.h"\r
92extern m68ki_cpu_core PicoCpuMM68k, PicoCpuMS68k;\r
93#ifndef SekCyclesLeft\r
94#define SekCyclesLeftNoMCD PicoCpuMM68k.cyc_remaining_cycles\r
95#define SekCyclesLeft \\r
96 (((PicoAHW&1) && (PicoOpt & POPT_EN_MCD_PSYNC)) ? (SekCycleAim-SekCycleCnt) : SekCyclesLeftNoMCD)\r
97#define SekCyclesLeftS68k \\r
98 ((PicoOpt & POPT_EN_MCD_PSYNC) ? (SekCycleAimS68k-SekCycleCntS68k) : PicoCpuMS68k.cyc_remaining_cycles)\r
99#define SekEndTimeslice(after) SET_CYCLES(after)\r
100#define SekEndTimesliceS68k(after) PicoCpuMS68k.cyc_remaining_cycles=after\r
101#define SekPc m68k_get_reg(&PicoCpuMM68k, M68K_REG_PC)\r
102#define SekPcS68k m68k_get_reg(&PicoCpuMS68k, M68K_REG_PC)\r
103#define SekSetStop(x) { \\r
104 if(x) { SET_CYCLES(0); PicoCpuMM68k.stopped=STOP_LEVEL_STOP; } \\r
105 else PicoCpuMM68k.stopped=0; \\r
106}\r
107#define SekSetStopS68k(x) { \\r
108 if(x) { SET_CYCLES(0); PicoCpuMS68k.stopped=STOP_LEVEL_STOP; } \\r
109 else PicoCpuMS68k.stopped=0; \\r
110}\r
111#define SekIsStoppedS68k() (PicoCpuMS68k.stopped==STOP_LEVEL_STOP)\r
112#define SekShouldInterrupt (CPU_INT_LEVEL > FLAG_INT_MASK)\r
113\r
114#define SekInterrupt(irq) { \\r
115 void *oldcontext = m68ki_cpu_p; \\r
116 m68k_set_context(&PicoCpuMM68k); \\r
117 m68k_set_irq(irq); \\r
118 m68k_set_context(oldcontext); \\r
119}\r
120\r
121#endif\r
122#endif // EMU_M68K\r
123\r
124extern int SekCycleCnt; // cycles done in this frame\r
125extern int SekCycleAim; // cycle aim\r
126extern unsigned int SekCycleCntT; // total cycle counter, updated once per frame\r
127\r
128#define SekCyclesReset() { \\r
129 SekCycleCntT+=SekCycleAim; \\r
130 SekCycleCnt-=SekCycleAim; \\r
131 SekCycleAim=0; \\r
132}\r
133#define SekCyclesBurn(c) SekCycleCnt+=c\r
134#define SekCyclesDone() (SekCycleAim-SekCyclesLeft) // number of cycles done in this frame (can be checked anywhere)\r
135#define SekCyclesDoneT() (SekCycleCntT+SekCyclesDone()) // total nuber of cycles done for this rom\r
136\r
137#define SekEndRun(after) { \\r
138 SekCycleCnt -= SekCyclesLeft - (after); \\r
139 if (SekCycleCnt < 0) SekCycleCnt = 0; \\r
140 SekEndTimeslice(after); \\r
141}\r
142\r
143#define SekEndRunS68k(after) { \\r
144 SekCycleCntS68k -= SekCyclesLeftS68k - (after); \\r
145 if (SekCycleCntS68k < 0) SekCycleCntS68k = 0; \\r
146 SekEndTimesliceS68k(after); \\r
147}\r
148\r
149extern int SekCycleCntS68k;\r
150extern int SekCycleAimS68k;\r
151\r
152#define SekCyclesResetS68k() { \\r
153 SekCycleCntS68k-=SekCycleAimS68k; \\r
154 SekCycleAimS68k=0; \\r
155}\r
156#define SekCyclesDoneS68k() (SekCycleAimS68k-SekCyclesLeftS68k)\r
157\r
158#ifdef EMU_CORE_DEBUG\r
159extern int dbg_irq_level;\r
160#undef SekEndTimeslice\r
161#undef SekCyclesBurn\r
162#undef SekEndRun\r
163#undef SekInterrupt\r
164#define SekEndTimeslice(c)\r
165#define SekCyclesBurn(c) c\r
166#define SekEndRun(c)\r
167#define SekInterrupt(irq) dbg_irq_level=irq\r
168#endif\r
169\r
170// ----------------------- Z80 CPU -----------------------\r
171\r
172#if defined(_USE_MZ80)\r
173#include "../cpu/mz80/mz80.h"\r
174\r
175#define z80_run(cycles) { mz80GetElapsedTicks(1); mz80_run(cycles) }\r
176#define z80_run_nr(cycles) mz80_run(cycles)\r
177#define z80_int() mz80int(0)\r
178\r
179#elif defined(_USE_DRZ80)\r
180#include "../cpu/DrZ80/drz80.h"\r
181\r
182extern struct DrZ80 drZ80;\r
183\r
184#define z80_run(cycles) ((cycles) - DrZ80Run(&drZ80, cycles))\r
185#define z80_run_nr(cycles) DrZ80Run(&drZ80, cycles)\r
186#define z80_int() drZ80.Z80_IRQ = 1\r
187\r
188#define z80_cyclesLeft drZ80.cycles\r
189\r
190#elif defined(_USE_CZ80)\r
191#include "../cpu/cz80/cz80.h"\r
192\r
193#define z80_run(cycles) Cz80_Exec(&CZ80, cycles)\r
194#define z80_run_nr(cycles) Cz80_Exec(&CZ80, cycles)\r
195#define z80_int() Cz80_Set_IRQ(&CZ80, 0, HOLD_LINE)\r
196\r
197#define z80_cyclesLeft (CZ80.ICount - CZ80.ExtraCycles)\r
198\r
199#else\r
200\r
201#define z80_run(cycles) (cycles)\r
202#define z80_run_nr(cycles)\r
203#define z80_int()\r
204\r
205#endif\r
206\r
207extern int z80stopCycle; /* in 68k cycles */\r
208extern int z80_cycle_cnt; /* 'done' z80 cycles before z80_run() */\r
209extern int z80_cycle_aim;\r
210extern int z80_scanline;\r
211extern int z80_scanline_cycles; /* cycles done until z80_scanline */\r
212\r
213#define z80_resetCycles() \\r
214 z80_cycle_cnt = z80_cycle_aim = z80_scanline = z80_scanline_cycles = 0;\r
215\r
216#define z80_cyclesDone() \\r
217 (z80_cycle_aim - z80_cyclesLeft)\r
218\r
219#define cycles_68k_to_z80(x) ((x)*957 >> 11)\r
220\r
221// ---------------------------------------------------------\r
222\r
223// main oscillator clock which controls timing\r
224#define OSC_NTSC 53693100\r
225// seems to be accurate, see scans from http://www.hot.ee/tmeeco/\r
226#define OSC_PAL 53203424\r
227\r
228struct PicoVideo\r
229{\r
230 unsigned char reg[0x20];\r
231 unsigned int command; // 32-bit Command\r
232 unsigned char pending; // 1 if waiting for second half of 32-bit command\r
233 unsigned char type; // Command type (v/c/vsram read/write)\r
234 unsigned short addr; // Read/Write address\r
235 int status; // Status bits\r
236 unsigned char pending_ints; // pending interrupts: ??VH????\r
237 signed char lwrite_cnt; // VDP write count during active display line\r
238 unsigned short v_counter; // V-counter\r
239 unsigned char pad[0x10];\r
240};\r
241\r
242struct PicoMisc\r
243{\r
244 unsigned char rotate;\r
245 unsigned char z80Run;\r
246 unsigned char padTHPhase[2]; // 02 phase of gamepad TH switches\r
247 unsigned short scanline; // 04 0 to 261||311\r
248 char dirtyPal; // 06 Is the palette dirty (1 - change @ this frame, 2 - some time before)\r
249 unsigned char hardware; // 07 Hardware value for country\r
250 unsigned char pal; // 08 1=PAL 0=NTSC\r
251 unsigned char sram_reg; // SRAM mode register. bit0: allow read? bit1: deny write? bit2: EEPROM? bit4: detected? (header or by access)\r
252 unsigned short z80_bank68k; // 0a\r
253 unsigned short z80_lastaddr; // this is for Z80 faking\r
254 unsigned char z80_fakeval;\r
255 unsigned char z80_reset; // z80 reset held\r
256 unsigned char padDelay[2]; // 10 gamepad phase time outs, so we count a delay\r
257 unsigned short eeprom_addr; // EEPROM address register\r
258 unsigned char eeprom_cycle; // EEPROM SRAM cycle number\r
259 unsigned char eeprom_slave; // EEPROM slave word for X24C02 and better SRAMs\r
260 unsigned char prot_bytes[2]; // simple protection faking\r
261 unsigned short dma_xfers; // 18\r
262 unsigned char pad[2];\r
263 unsigned int frame_count; // 1c for movies and idle det\r
264};\r
265\r
266// some assembly stuff depend on these, do not touch!\r
267struct Pico\r
268{\r
269 unsigned char ram[0x10000]; // 0x00000 scratch ram\r
270 unsigned short vram[0x8000]; // 0x10000\r
271 unsigned char zram[0x2000]; // 0x20000 Z80 ram\r
272 unsigned char ioports[0x10];\r
273 unsigned int pad[0x3c]; // unused\r
274 unsigned short cram[0x40]; // 0x22100\r
275 unsigned short vsram[0x40]; // 0x22180\r
276\r
277 unsigned char *rom; // 0x22200\r
278 unsigned int romsize; // 0x22204\r
279\r
280 struct PicoMisc m;\r
281 struct PicoVideo video;\r
282};\r
283\r
284// sram\r
285struct PicoSRAM\r
286{\r
287 unsigned char *data; // actual data\r
288 unsigned int start; // start address in 68k address space\r
289 unsigned int end;\r
290 unsigned char unused1; // 0c: unused\r
291 unsigned char unused2;\r
292 unsigned char changed;\r
293 unsigned char eeprom_type; // eeprom type: 0: 7bit (24C01), 2: device with 2 addr words (X24C02+), 3: dev with 3 addr words\r
294 unsigned char eeprom_abits; // eeprom access must be odd addr for: bit0 ~ cl, bit1 ~ out\r
295 unsigned char eeprom_bit_cl; // bit number for cl\r
296 unsigned char eeprom_bit_in; // bit number for in\r
297 unsigned char eeprom_bit_out; // bit number for out\r
298};\r
299\r
300// MCD\r
301#include "cd/cd_sys.h"\r
302#include "cd/LC89510.h"\r
303#include "cd/gfx_cd.h"\r
304\r
305struct mcd_pcm\r
306{\r
307 unsigned char control; // reg7\r
308 unsigned char enabled; // reg8\r
309 unsigned char cur_ch;\r
310 unsigned char bank;\r
311 int pad1;\r
312\r
313 struct pcm_chan // 08, size 0x10\r
314 {\r
315 unsigned char regs[8];\r
316 unsigned int addr; // .08: played sample address\r
317 int pad;\r
318 } ch[8];\r
319};\r
320\r
321struct mcd_misc\r
322{\r
323 unsigned short hint_vector;\r
324 unsigned char busreq;\r
325 unsigned char s68k_pend_ints;\r
326 unsigned int state_flags; // 04: emu state: reset_pending\r
327 unsigned int counter75hz;\r
328 unsigned int pad0;\r
329 int timer_int3; // 10\r
330 unsigned int timer_stopwatch;\r
331 unsigned char bcram_reg; // 18: battery-backed RAM cart register\r
332 unsigned char pad2;\r
333 unsigned short pad3;\r
334 int pad[9];\r
335};\r
336\r
337typedef struct\r
338{\r
339 unsigned char bios[0x20000]; // 000000: 128K\r
340 union { // 020000: 512K\r
341 unsigned char prg_ram[0x80000];\r
342 unsigned char prg_ram_b[4][0x20000];\r
343 };\r
344 union { // 0a0000: 256K\r
345 struct {\r
346 unsigned char word_ram2M[0x40000];\r
347 unsigned char unused0[0x20000];\r
348 };\r
349 struct {\r
350 unsigned char unused1[0x20000];\r
351 unsigned char word_ram1M[2][0x20000];\r
352 };\r
353 };\r
354 union { // 100000: 64K\r
355 unsigned char pcm_ram[0x10000];\r
356 unsigned char pcm_ram_b[0x10][0x1000];\r
357 };\r
358 unsigned char s68k_regs[0x200]; // 110000: GA, not CPU regs\r
359 unsigned char bram[0x2000]; // 110200: 8K\r
360 struct mcd_misc m; // 112200: misc\r
361 struct mcd_pcm pcm; // 112240:\r
362 _scd_toc TOC; // not to be saved\r
363 CDD cdd;\r
364 CDC cdc;\r
365 _scd scd;\r
366 Rot_Comp rot_comp;\r
367} mcd_state;\r
368\r
369#define Pico_mcd ((mcd_state *)Pico.rom)\r
370\r
371\r
372// Area.c\r
373PICO_INTERNAL void PicoAreaPackCpu(unsigned char *cpu, int is_sub);\r
374PICO_INTERNAL void PicoAreaUnpackCpu(unsigned char *cpu, int is_sub);\r
375extern void (*PicoLoadStateHook)(void);\r
376\r
377// cd/Area.c\r
378PICO_INTERNAL int PicoCdSaveState(void *file);\r
379PICO_INTERNAL int PicoCdLoadState(void *file);\r
380\r
381typedef struct {\r
382 int chunk;\r
383 int size;\r
384 void *ptr;\r
385} carthw_state_chunk;\r
386extern carthw_state_chunk *carthw_chunks;\r
387#define CHUNK_CARTHW 64\r
388\r
389// area.c\r
390typedef size_t (arearw)(void *p, size_t _size, size_t _n, void *file);\r
391typedef size_t (areaeof)(void *file);\r
392typedef int (areaseek)(void *file, long offset, int whence);\r
393typedef int (areaclose)(void *file);\r
394extern arearw *areaRead; // external read and write function pointers for\r
395extern arearw *areaWrite; // gzip save state ability\r
396extern areaeof *areaEof;\r
397extern areaseek *areaSeek;\r
398extern areaclose *areaClose;\r
399\r
400// Cart.c\r
401extern void (*PicoCartUnloadHook)(void);\r
402\r
403// Debug.c\r
404int CM_compareRun(int cyc, int is_sub);\r
405\r
406// Draw.c\r
407PICO_INTERNAL void PicoFrameStart(void);\r
408void PicoDrawSync(int to, int blank_last_line);\r
409extern int DrawScanline;\r
410#define MAX_LINE_SPRITES 29\r
411extern unsigned char HighLnSpr[240][3 + MAX_LINE_SPRITES];\r
412\r
413// Draw2.c\r
414PICO_INTERNAL void PicoFrameFull();\r
415\r
416// Memory.c\r
417PICO_INTERNAL void PicoInitPc(unsigned int pc);\r
418PICO_INTERNAL unsigned int PicoCheckPc(unsigned int pc);\r
419PICO_INTERNAL_ASM unsigned int PicoRead32(unsigned int a);\r
420PICO_INTERNAL void PicoMemSetup(void);\r
421PICO_INTERNAL_ASM void PicoMemReset(void);\r
422PICO_INTERNAL void PicoMemResetHooks(void);\r
423PICO_INTERNAL int PadRead(int i);\r
424PICO_INTERNAL unsigned char z80_read(unsigned short a);\r
425#ifndef _USE_CZ80\r
426PICO_INTERNAL_ASM void z80_write(unsigned char data, unsigned short a);\r
427PICO_INTERNAL void z80_write16(unsigned short data, unsigned short a);\r
428PICO_INTERNAL unsigned short z80_read16(unsigned short a);\r
429#else\r
430PICO_INTERNAL_ASM void z80_write(unsigned int a, unsigned char data);\r
431#endif\r
432PICO_INTERNAL int ym2612_write_local(unsigned int a, unsigned int d, int is_from_z80);\r
433extern unsigned int (*PicoRead16Hook)(unsigned int a, int realsize);\r
434extern void (*PicoWrite8Hook) (unsigned int a,unsigned int d,int realsize);\r
435extern void (*PicoWrite16Hook)(unsigned int a,unsigned int d,int realsize);\r
436\r
437// cd/Memory.c\r
438PICO_INTERNAL void PicoMemSetupCD(void);\r
439PICO_INTERNAL_ASM void PicoMemResetCD(int r3);\r
440PICO_INTERNAL_ASM void PicoMemResetCDdecode(int r3);\r
441\r
442// Pico/Memory.c\r
443PICO_INTERNAL void PicoMemSetupPico(void);\r
444PICO_INTERNAL unsigned int ym2612_read_local_68k(void);\r
445\r
446// Pico.c\r
447extern struct Pico Pico;\r
448extern struct PicoSRAM SRam;\r
449extern int PicoPadInt[2];\r
450extern int emustatus;\r
451extern void (*PicoResetHook)(void);\r
452extern void (*PicoLineHook)(void);\r
453PICO_INTERNAL int CheckDMA(void);\r
454PICO_INTERNAL void PicoDetectRegion(void);\r
455PICO_INTERNAL void PicoSyncZ80(int m68k_cycles_done);\r
456\r
457// cd/Pico.c\r
458PICO_INTERNAL void PicoInitMCD(void);\r
459PICO_INTERNAL void PicoExitMCD(void);\r
460PICO_INTERNAL void PicoPowerMCD(void);\r
461PICO_INTERNAL int PicoResetMCD(void);\r
462PICO_INTERNAL void PicoFrameMCD(void);\r
463\r
464// Pico/Pico.c\r
465PICO_INTERNAL void PicoInitPico(void);\r
466PICO_INTERNAL void PicoReratePico(void);\r
467\r
468// Pico/xpcm.c\r
469PICO_INTERNAL void PicoPicoPCMUpdate(short *buffer, int length, int stereo);\r
470PICO_INTERNAL void PicoPicoPCMReset(void);\r
471PICO_INTERNAL void PicoPicoPCMRerate(int xpcm_rate);\r
472\r
473// Sek.c\r
474PICO_INTERNAL void SekInit(void);\r
475PICO_INTERNAL int SekReset(void);\r
476PICO_INTERNAL void SekState(int *data);\r
477PICO_INTERNAL void SekSetRealTAS(int use_real);\r
478void SekStepM68k(void);\r
479void SekInitIdleDet(void);\r
480void SekFinishIdleDet(void);\r
481\r
482// cd/Sek.c\r
483PICO_INTERNAL void SekInitS68k(void);\r
484PICO_INTERNAL int SekResetS68k(void);\r
485PICO_INTERNAL int SekInterruptS68k(int irq);\r
486\r
487// sound/sound.c\r
488PICO_INTERNAL void cdda_start_play();\r
489extern short cdda_out_buffer[2*1152];\r
490extern int PsndLen_exc_cnt;\r
491extern int PsndLen_exc_add;\r
492extern int timer_a_next_oflow, timer_a_step; // in z80 cycles\r
493extern int timer_b_next_oflow, timer_b_step;\r
494\r
495void ym2612_sync_timers(int z80_cycles, int mode_old, int mode_new);\r
496void ym2612_pack_state(void);\r
497void ym2612_unpack_state(void);\r
498\r
499#define TIMER_NO_OFLOW 0x70000000\r
500// tA = 72 * (1024 - NA) / M\r
501#define TIMER_A_TICK_ZCYCLES 17203\r
502// tB = 1152 * (256 - NA) / M\r
503#define TIMER_B_TICK_ZCYCLES 262800 // 275251 broken, see Dai Makaimura\r
504\r
505#define timers_cycle() \\r
506 if (timer_a_next_oflow > 0 && timer_a_next_oflow < TIMER_NO_OFLOW) \\r
507 timer_a_next_oflow -= Pico.m.pal ? 70938*256 : 59659*256; \\r
508 if (timer_b_next_oflow > 0 && timer_b_next_oflow < TIMER_NO_OFLOW) \\r
509 timer_b_next_oflow -= Pico.m.pal ? 70938*256 : 59659*256; \\r
510 ym2612_sync_timers(0, ym2612.OPN.ST.mode, ym2612.OPN.ST.mode);\r
511\r
512#define timers_reset() \\r
513 timer_a_next_oflow = timer_b_next_oflow = TIMER_NO_OFLOW; \\r
514 timer_a_step = TIMER_A_TICK_ZCYCLES * 1024; \\r
515 timer_b_step = TIMER_B_TICK_ZCYCLES * 256;\r
516\r
517\r
518// VideoPort.c\r
519PICO_INTERNAL_ASM void PicoVideoWrite(unsigned int a,unsigned short d);\r
520PICO_INTERNAL_ASM unsigned int PicoVideoRead(unsigned int a);\r
521PICO_INTERNAL_ASM unsigned int PicoVideoRead8(unsigned int a);\r
522extern int (*PicoDmaHook)(unsigned int source, int len, unsigned short **srcp, unsigned short **limitp);\r
523\r
524// Misc.c\r
525PICO_INTERNAL void SRAMWriteEEPROM(unsigned int d);\r
526PICO_INTERNAL void SRAMUpdPending(unsigned int a, unsigned int d);\r
527PICO_INTERNAL_ASM unsigned int SRAMReadEEPROM(void);\r
528PICO_INTERNAL_ASM void memcpy16(unsigned short *dest, unsigned short *src, int count);\r
529PICO_INTERNAL_ASM void memcpy16bswap(unsigned short *dest, void *src, int count);\r
530PICO_INTERNAL_ASM void memcpy32(int *dest, int *src, int count); // 32bit word count\r
531PICO_INTERNAL_ASM void memset32(int *dest, int c, int count);\r
532\r
533// cd/Misc.c\r
534PICO_INTERNAL_ASM void wram_2M_to_1M(unsigned char *m);\r
535PICO_INTERNAL_ASM void wram_1M_to_2M(unsigned char *m);\r
536\r
537// cd/buffering.c\r
538PICO_INTERNAL void PicoCDBufferRead(void *dest, int lba);\r
539\r
540// sound/sound.c\r
541PICO_INTERNAL void PsndReset(void);\r
542PICO_INTERNAL void PsndDoDAC(int line_to);\r
543PICO_INTERNAL void PsndClear(void);\r
544PICO_INTERNAL void PsndGetSamples(int y);\r
545// z80 functionality wrappers\r
546PICO_INTERNAL void z80_init(void);\r
547PICO_INTERNAL void z80_pack(unsigned char *data);\r
548PICO_INTERNAL void z80_unpack(unsigned char *data);\r
549PICO_INTERNAL void z80_reset(void);\r
550PICO_INTERNAL void z80_exit(void);\r
551extern int PsndDacLine;\r
552\r
553// emulation event logging\r
554#ifndef EL_LOGMASK\r
555#define EL_LOGMASK 0\r
556#endif\r
557\r
558#define EL_HVCNT 0x00000001 /* hv counter reads */\r
559#define EL_SR 0x00000002 /* SR reads */\r
560#define EL_INTS 0x00000004 /* ints and acks */\r
561#define EL_YMTIMER 0x00000008 /* ym2612 timer stuff */\r
562#define EL_INTSW 0x00000010 /* log irq switching on/off */\r
563#define EL_ASVDP 0x00000020 /* VDP accesses during active scan */\r
564#define EL_VDPDMA 0x00000040 /* VDP DMA transfers and their timing */\r
565#define EL_BUSREQ 0x00000080 /* z80 busreq r/w or reset w */\r
566#define EL_Z80BNK 0x00000100 /* z80 i/o through bank area */\r
567#define EL_SRAMIO 0x00000200 /* sram i/o */\r
568#define EL_EEPROM 0x00000400 /* eeprom debug */\r
569#define EL_UIO 0x00000800 /* unmapped i/o */\r
570#define EL_IO 0x00001000 /* all i/o */\r
571#define EL_CDPOLL 0x00002000 /* MCD: log poll detection */\r
572#define EL_SVP 0x00004000 /* SVP stuff */\r
573#define EL_PICOHW 0x00008000 /* Pico stuff */\r
574#define EL_IDLE 0x00010000 /* idle loop det. */\r
575\r
576#define EL_STATUS 0x40000000 /* status messages */\r
577#define EL_ANOMALY 0x80000000 /* some unexpected conditions (during emulation) */\r
578\r
579#if EL_LOGMASK\r
580extern void lprintf(const char *fmt, ...);\r
581#define elprintf(w,f,...) \\r
582{ \\r
583 if ((w) & EL_LOGMASK) \\r
584 lprintf("%05i:%03i: " f "\n",Pico.m.frame_count,Pico.m.scanline,##__VA_ARGS__); \\r
585}\r
586#elif defined(_MSC_VER)\r
587#define elprintf\r
588#else\r
589#define elprintf(w,f,...)\r
590#endif\r
591\r
592#ifdef _MSC_VER\r
593#define cdprintf\r
594#else\r
595#define cdprintf(x...)\r
596#endif\r
597\r
598#ifdef __cplusplus\r
599} // End of extern "C"\r
600#endif\r
601\r
602#endif // PICO_INTERNAL_INCLUDED\r
603\r
fast MegaDrive/MegaCD/32X emulator