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32x: sh2 irqs (irls), preliminary DMAC implementation
[picodrive.git] / pico / pico_int.h
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1// Pico Library - Internal Header File\r
2\r
3// (c) Copyright 2004 Dave, All rights reserved.\r
4// (c) Copyright 2006-2008 Grazvydas "notaz" Ignotas, all rights reserved.\r
5// Free for non-commercial use.\r
6\r
7// For commercial use, separate licencing terms must be obtained.\r
8\r
9#ifndef PICO_INTERNAL_INCLUDED\r
10#define PICO_INTERNAL_INCLUDED\r
11\r
12#include <stdio.h>\r
13#include <stdlib.h>\r
14#include <string.h>\r
15#include "pico.h"\r
16#include "carthw/carthw.h"\r
17\r
18//\r
19#define USE_POLL_DETECT\r
20\r
21#ifndef PICO_INTERNAL\r
22#define PICO_INTERNAL\r
23#endif\r
24#ifndef PICO_INTERNAL_ASM\r
25#define PICO_INTERNAL_ASM\r
26#endif\r
27\r
28// to select core, define EMU_C68K, EMU_M68K or EMU_F68K in your makefile or project\r
29\r
30#ifdef __cplusplus\r
31extern "C" {\r
32#endif\r
33\r
34\r
35// ----------------------- 68000 CPU -----------------------\r
36#ifdef EMU_C68K\r
37#include "../cpu/Cyclone/Cyclone.h"\r
38extern struct Cyclone PicoCpuCM68k, PicoCpuCS68k;\r
39#define SekCyclesLeftNoMCD PicoCpuCM68k.cycles // cycles left for this run\r
40#define SekCyclesLeft \\r
41 (((PicoAHW&1) && (PicoOpt & POPT_EN_MCD_PSYNC)) ? (SekCycleAim-SekCycleCnt) : SekCyclesLeftNoMCD)\r
42#define SekCyclesLeftS68k \\r
43 ((PicoOpt & POPT_EN_MCD_PSYNC) ? (SekCycleAimS68k-SekCycleCntS68k) : PicoCpuCS68k.cycles)\r
44#define SekEndTimeslice(after) PicoCpuCM68k.cycles=after\r
45#define SekEndTimesliceS68k(after) PicoCpuCS68k.cycles=after\r
46#define SekPc (PicoCpuCM68k.pc-PicoCpuCM68k.membase)\r
47#define SekPcS68k (PicoCpuCS68k.pc-PicoCpuCS68k.membase)\r
48#define SekSetStop(x) { PicoCpuCM68k.state_flags&=~1; if (x) { PicoCpuCM68k.state_flags|=1; PicoCpuCM68k.cycles=0; } }\r
49#define SekSetStopS68k(x) { PicoCpuCS68k.state_flags&=~1; if (x) { PicoCpuCS68k.state_flags|=1; PicoCpuCS68k.cycles=0; } }\r
50#define SekIsStoppedS68k() (PicoCpuCS68k.state_flags&1)\r
51#define SekShouldInterrupt (PicoCpuCM68k.irq > (PicoCpuCM68k.srh&7))\r
52\r
53#define SekInterrupt(i) PicoCpuCM68k.irq=i\r
54\r
55#ifdef EMU_M68K\r
56#define EMU_CORE_DEBUG\r
57#endif\r
58#endif\r
59\r
60#ifdef EMU_F68K\r
61#include "../cpu/fame/fame.h"\r
62extern M68K_CONTEXT PicoCpuFM68k, PicoCpuFS68k;\r
63#define SekCyclesLeftNoMCD PicoCpuFM68k.io_cycle_counter\r
64#define SekCyclesLeft \\r
65 (((PicoAHW&1) && (PicoOpt & POPT_EN_MCD_PSYNC)) ? (SekCycleAim-SekCycleCnt) : SekCyclesLeftNoMCD)\r
66#define SekCyclesLeftS68k \\r
67 ((PicoOpt & POPT_EN_MCD_PSYNC) ? (SekCycleAimS68k-SekCycleCntS68k) : PicoCpuFS68k.io_cycle_counter)\r
68#define SekEndTimeslice(after) PicoCpuFM68k.io_cycle_counter=after\r
69#define SekEndTimesliceS68k(after) PicoCpuFS68k.io_cycle_counter=after\r
70#define SekPc fm68k_get_pc(&PicoCpuFM68k)\r
71#define SekPcS68k fm68k_get_pc(&PicoCpuFS68k)\r
72#define SekSetStop(x) { \\r
73 PicoCpuFM68k.execinfo &= ~FM68K_HALTED; \\r
74 if (x) { PicoCpuFM68k.execinfo |= FM68K_HALTED; PicoCpuFM68k.io_cycle_counter = 0; } \\r
75}\r
76#define SekSetStopS68k(x) { \\r
77 PicoCpuFS68k.execinfo &= ~FM68K_HALTED; \\r
78 if (x) { PicoCpuFS68k.execinfo |= FM68K_HALTED; PicoCpuFS68k.io_cycle_counter = 0; } \\r
79}\r
80#define SekIsStoppedS68k() (PicoCpuFS68k.execinfo&FM68K_HALTED)\r
81#define SekShouldInterrupt fm68k_would_interrupt()\r
82\r
83#define SekInterrupt(irq) PicoCpuFM68k.interrupts[0]=irq\r
84\r
85#ifdef EMU_M68K\r
86#define EMU_CORE_DEBUG\r
87#endif\r
88#endif\r
89\r
90#ifdef EMU_M68K\r
91#include "../cpu/musashi/m68kcpu.h"\r
92extern m68ki_cpu_core PicoCpuMM68k, PicoCpuMS68k;\r
93#ifndef SekCyclesLeft\r
94#define SekCyclesLeftNoMCD PicoCpuMM68k.cyc_remaining_cycles\r
95#define SekCyclesLeft \\r
96 (((PicoAHW&1) && (PicoOpt & POPT_EN_MCD_PSYNC)) ? (SekCycleAim-SekCycleCnt) : SekCyclesLeftNoMCD)\r
97#define SekCyclesLeftS68k \\r
98 ((PicoOpt & POPT_EN_MCD_PSYNC) ? (SekCycleAimS68k-SekCycleCntS68k) : PicoCpuMS68k.cyc_remaining_cycles)\r
99#define SekEndTimeslice(after) SET_CYCLES(after)\r
100#define SekEndTimesliceS68k(after) PicoCpuMS68k.cyc_remaining_cycles=after\r
101#define SekPc m68k_get_reg(&PicoCpuMM68k, M68K_REG_PC)\r
102#define SekPcS68k m68k_get_reg(&PicoCpuMS68k, M68K_REG_PC)\r
103#define SekSetStop(x) { \\r
104 if(x) { SET_CYCLES(0); PicoCpuMM68k.stopped=STOP_LEVEL_STOP; } \\r
105 else PicoCpuMM68k.stopped=0; \\r
106}\r
107#define SekSetStopS68k(x) { \\r
108 if(x) { SET_CYCLES(0); PicoCpuMS68k.stopped=STOP_LEVEL_STOP; } \\r
109 else PicoCpuMS68k.stopped=0; \\r
110}\r
111#define SekIsStoppedS68k() (PicoCpuMS68k.stopped==STOP_LEVEL_STOP)\r
112#define SekShouldInterrupt (CPU_INT_LEVEL > FLAG_INT_MASK)\r
113\r
114#define SekInterrupt(irq) { \\r
115 void *oldcontext = m68ki_cpu_p; \\r
116 m68k_set_context(&PicoCpuMM68k); \\r
117 m68k_set_irq(irq); \\r
118 m68k_set_context(oldcontext); \\r
119}\r
120\r
121#endif\r
122#endif // EMU_M68K\r
123\r
124extern int SekCycleCnt; // cycles done in this frame\r
125extern int SekCycleAim; // cycle aim\r
126extern unsigned int SekCycleCntT; // total cycle counter, updated once per frame\r
127\r
128#define SekCyclesReset() { \\r
129 SekCycleCntT+=SekCycleAim; \\r
130 SekCycleCnt-=SekCycleAim; \\r
131 SekCycleAim=0; \\r
132}\r
133#define SekCyclesBurn(c) SekCycleCnt+=c\r
134#define SekCyclesDone() (SekCycleAim-SekCyclesLeft) // number of cycles done in this frame (can be checked anywhere)\r
135#define SekCyclesDoneT() (SekCycleCntT+SekCyclesDone()) // total nuber of cycles done for this rom\r
136\r
137#define SekEndRun(after) { \\r
138 SekCycleCnt -= SekCyclesLeft - (after); \\r
139 if (SekCycleCnt < 0) SekCycleCnt = 0; \\r
140 SekEndTimeslice(after); \\r
141}\r
142\r
143#define SekEndRunS68k(after) { \\r
144 SekCycleCntS68k -= SekCyclesLeftS68k - (after); \\r
145 if (SekCycleCntS68k < 0) SekCycleCntS68k = 0; \\r
146 SekEndTimesliceS68k(after); \\r
147}\r
148\r
149extern int SekCycleCntS68k;\r
150extern int SekCycleAimS68k;\r
151\r
152#define SekCyclesResetS68k() { \\r
153 SekCycleCntS68k-=SekCycleAimS68k; \\r
154 SekCycleAimS68k=0; \\r
155}\r
156#define SekCyclesDoneS68k() (SekCycleAimS68k-SekCyclesLeftS68k)\r
157\r
158#ifdef EMU_CORE_DEBUG\r
159extern int dbg_irq_level;\r
160#undef SekEndTimeslice\r
161#undef SekCyclesBurn\r
162#undef SekEndRun\r
163#undef SekInterrupt\r
164#define SekEndTimeslice(c)\r
165#define SekCyclesBurn(c) c\r
166#define SekEndRun(c)\r
167#define SekInterrupt(irq) dbg_irq_level=irq\r
168#endif\r
169\r
170// ----------------------- Z80 CPU -----------------------\r
171\r
172#if defined(_USE_MZ80)\r
173#include "../cpu/mz80/mz80.h"\r
174\r
175#define z80_run(cycles) { mz80GetElapsedTicks(1); mz80_run(cycles) }\r
176#define z80_run_nr(cycles) mz80_run(cycles)\r
177#define z80_int() mz80int(0)\r
178\r
179#elif defined(_USE_DRZ80)\r
180#include "../cpu/DrZ80/drz80.h"\r
181\r
182extern struct DrZ80 drZ80;\r
183\r
184#define z80_run(cycles) ((cycles) - DrZ80Run(&drZ80, cycles))\r
185#define z80_run_nr(cycles) DrZ80Run(&drZ80, cycles)\r
186#define z80_int() drZ80.Z80_IRQ = 1\r
187\r
188#define z80_cyclesLeft drZ80.cycles\r
189#define z80_pc() (drZ80.Z80PC - drZ80.Z80PC_BASE)\r
190\r
191#elif defined(_USE_CZ80)\r
192#include "../cpu/cz80/cz80.h"\r
193\r
194#define z80_run(cycles) Cz80_Exec(&CZ80, cycles)\r
195#define z80_run_nr(cycles) Cz80_Exec(&CZ80, cycles)\r
196#define z80_int() Cz80_Set_IRQ(&CZ80, 0, HOLD_LINE)\r
197\r
198#define z80_cyclesLeft (CZ80.ICount - CZ80.ExtraCycles)\r
199#define z80_pc() Cz80_Get_Reg(&CZ80, CZ80_PC)\r
200\r
201#else\r
202\r
203#define z80_run(cycles) (cycles)\r
204#define z80_run_nr(cycles)\r
205#define z80_int()\r
206\r
207#endif\r
208\r
209extern int z80stopCycle; /* in 68k cycles */\r
210extern int z80_cycle_cnt; /* 'done' z80 cycles before z80_run() */\r
211extern int z80_cycle_aim;\r
212extern int z80_scanline;\r
213extern int z80_scanline_cycles; /* cycles done until z80_scanline */\r
214\r
215#define z80_resetCycles() \\r
216 z80_cycle_cnt = z80_cycle_aim = z80_scanline = z80_scanline_cycles = 0;\r
217\r
218#define z80_cyclesDone() \\r
219 (z80_cycle_aim - z80_cyclesLeft)\r
220\r
221#define cycles_68k_to_z80(x) ((x)*957 >> 11)\r
222\r
223#define Z80_MEM_SHIFT 13\r
224extern unsigned long z80_read_map [0x10000 >> Z80_MEM_SHIFT];\r
225extern unsigned long z80_write_map[0x10000 >> Z80_MEM_SHIFT];\r
226typedef unsigned char (z80_read_f)(unsigned short a);\r
227typedef void (z80_write_f)(unsigned int a, unsigned char data);\r
228\r
229// ----------------------- SH2 CPU -----------------------\r
230\r
231#include "cpu/sh2mame/sh2.h"\r
232\r
233SH2 msh2, ssh2;\r
234#define ash2_pc() msh2.ppc\r
235#define ash2_end_run(after) sh2_icount = after\r
236\r
237#define sh2_pc(c) (c) ? ssh2.ppc : msh2.ppc\r
238#define sh2_reg(c, x) (c) ? ssh2.r[x] : msh2.r[x]\r
239#define sh2_gbr(c) (c) ? ssh2.gbr : msh2.gbr\r
240#define sh2_vbr(c) (c) ? ssh2.vbr : msh2.vbr\r
241#define sh2_sr(c) (c) ? ssh2.sr : msh2.sr\r
242\r
243// ---------------------------------------------------------\r
244\r
245// main oscillator clock which controls timing\r
246#define OSC_NTSC 53693100\r
247#define OSC_PAL 53203424\r
248\r
249struct PicoVideo\r
250{\r
251 unsigned char reg[0x20];\r
252 unsigned int command; // 32-bit Command\r
253 unsigned char pending; // 1 if waiting for second half of 32-bit command\r
254 unsigned char type; // Command type (v/c/vsram read/write)\r
255 unsigned short addr; // Read/Write address\r
256 int status; // Status bits\r
257 unsigned char pending_ints; // pending interrupts: ??VH????\r
258 signed char lwrite_cnt; // VDP write count during active display line\r
259 unsigned short v_counter; // V-counter\r
260 unsigned char pad[0x10];\r
261};\r
262\r
263struct PicoMisc\r
264{\r
265 unsigned char rotate;\r
266 unsigned char z80Run;\r
267 unsigned char padTHPhase[2]; // 02 phase of gamepad TH switches\r
268 unsigned short scanline; // 04 0 to 261||311\r
269 char dirtyPal; // 06 Is the palette dirty (1 - change @ this frame, 2 - some time before)\r
270 unsigned char hardware; // 07 Hardware value for country\r
271 unsigned char pal; // 08 1=PAL 0=NTSC\r
272 unsigned char sram_reg; // 09 SRAM reg. See SRR_* below\r
273 unsigned short z80_bank68k; // 0a\r
274 unsigned short pad0;\r
275 unsigned char pad1;\r
276 unsigned char z80_reset; // 0f z80 reset held\r
277 unsigned char padDelay[2]; // 10 gamepad phase time outs, so we count a delay\r
278 unsigned short eeprom_addr; // EEPROM address register\r
279 unsigned char eeprom_cycle; // EEPROM cycle number\r
280 unsigned char eeprom_slave; // EEPROM slave word for X24C02 and better SRAMs\r
281 unsigned char eeprom_status;\r
282 unsigned char pad2;\r
283 unsigned short dma_xfers; // 18\r
284 unsigned char eeprom_wb[2]; // EEPROM latch/write buffer\r
285 unsigned int frame_count; // 1c for movies and idle det\r
286};\r
287\r
288// some assembly stuff depend on these, do not touch!\r
289struct Pico\r
290{\r
291 unsigned char ram[0x10000]; // 0x00000 scratch ram\r
292 union { // vram is byteswapped for easier reads when drawing\r
293 unsigned short vram[0x8000]; // 0x10000\r
294 unsigned char vramb[0x4000]; // VRAM in SMS mode\r
295 };\r
296 unsigned char zram[0x2000]; // 0x20000 Z80 ram\r
297 unsigned char ioports[0x10];\r
298 unsigned char sms_io_ctl;\r
299 unsigned char pad[0xef]; // unused\r
300 unsigned short cram[0x40]; // 0x22100\r
301 unsigned short vsram[0x40]; // 0x22180\r
302\r
303 unsigned char *rom; // 0x22200\r
304 unsigned int romsize; // 0x22204\r
305\r
306 struct PicoMisc m;\r
307 struct PicoVideo video;\r
308};\r
309\r
310// sram\r
311#define SRR_MAPPED (1 << 0)\r
312#define SRR_READONLY (1 << 1)\r
313\r
314#define SRF_ENABLED (1 << 0)\r
315#define SRF_EEPROM (1 << 1)\r
316\r
317struct PicoSRAM\r
318{\r
319 unsigned char *data; // actual data\r
320 unsigned int start; // start address in 68k address space\r
321 unsigned int end;\r
322 unsigned char flags; // 0c: SRF_*\r
323 unsigned char unused2;\r
324 unsigned char changed;\r
325 unsigned char eeprom_type; // eeprom type: 0: 7bit (24C01), 2: 2 addr words (X24C02+), 3: 3 addr words\r
326 unsigned char unused3;\r
327 unsigned char eeprom_bit_cl; // bit number for cl\r
328 unsigned char eeprom_bit_in; // bit number for in\r
329 unsigned char eeprom_bit_out; // bit number for out\r
330 unsigned int size;\r
331};\r
332\r
333// MCD\r
334#include "cd/cd_sys.h"\r
335#include "cd/LC89510.h"\r
336#include "cd/gfx_cd.h"\r
337\r
338struct mcd_pcm\r
339{\r
340 unsigned char control; // reg7\r
341 unsigned char enabled; // reg8\r
342 unsigned char cur_ch;\r
343 unsigned char bank;\r
344 int pad1;\r
345\r
346 struct pcm_chan // 08, size 0x10\r
347 {\r
348 unsigned char regs[8];\r
349 unsigned int addr; // .08: played sample address\r
350 int pad;\r
351 } ch[8];\r
352};\r
353\r
354struct mcd_misc\r
355{\r
356 unsigned short hint_vector;\r
357 unsigned char busreq;\r
358 unsigned char s68k_pend_ints;\r
359 unsigned int state_flags; // 04: emu state: reset_pending\r
360 unsigned int counter75hz;\r
361 unsigned int pad0;\r
362 int timer_int3; // 10\r
363 unsigned int timer_stopwatch;\r
364 unsigned char bcram_reg; // 18: battery-backed RAM cart register\r
365 unsigned char pad2;\r
366 unsigned short pad3;\r
367 int pad[9];\r
368};\r
369\r
370typedef struct\r
371{\r
372 unsigned char bios[0x20000]; // 000000: 128K\r
373 union { // 020000: 512K\r
374 unsigned char prg_ram[0x80000];\r
375 unsigned char prg_ram_b[4][0x20000];\r
376 };\r
377 union { // 0a0000: 256K\r
378 struct {\r
379 unsigned char word_ram2M[0x40000];\r
380 unsigned char unused0[0x20000];\r
381 };\r
382 struct {\r
383 unsigned char unused1[0x20000];\r
384 unsigned char word_ram1M[2][0x20000];\r
385 };\r
386 };\r
387 union { // 100000: 64K\r
388 unsigned char pcm_ram[0x10000];\r
389 unsigned char pcm_ram_b[0x10][0x1000];\r
390 };\r
391 unsigned char s68k_regs[0x200]; // 110000: GA, not CPU regs\r
392 unsigned char bram[0x2000]; // 110200: 8K\r
393 struct mcd_misc m; // 112200: misc\r
394 struct mcd_pcm pcm; // 112240:\r
395 _scd_toc TOC; // not to be saved\r
396 CDD cdd;\r
397 CDC cdc;\r
398 _scd scd;\r
399 Rot_Comp rot_comp;\r
400} mcd_state;\r
401\r
402// XXX: this will need to be reworked for cart+cd support.\r
403#define Pico_mcd ((mcd_state *)Pico.rom)\r
404\r
405// 32X\r
406#define P32XS_FM (1<<15)\r
407#define P32XS2_ADEN (1<< 9)\r
408#define P32XS_FULL (1<< 7)\r
409#define P32XS_68S (1<< 2)\r
410#define P32XS_RV (1<< 0)\r
411\r
412#define P32XV_nPAL (1<<15)\r
413#define P32XV_PRI (1<< 7)\r
414#define P32XV_Mx (3<< 0) // display mode mask\r
415\r
416#define P32XV_VBLK (1<<15)\r
417#define P32XV_HBLK (1<<14)\r
418#define P32XV_PEN (1<<13)\r
419#define P32XV_nFEN (1<< 1)\r
420#define P32XV_FS (1<< 0)\r
421\r
422#define P32XF_68KPOLL (1 << 0)\r
423#define P32XF_MSH2POLL (1 << 1)\r
424#define P32XF_SSH2POLL (1 << 2)\r
425#define P32XF_68KVPOLL (1 << 3)\r
426#define P32XF_MSH2VPOLL (1 << 4)\r
427#define P32XF_SSH2VPOLL (1 << 5)\r
428\r
429#define P32XI_VRES (1 << 14/2) // IRL/2\r
430#define P32XI_VINT (1 << 12/2)\r
431#define P32XI_HINT (1 << 10/2)\r
432#define P32XI_CMD (1 << 8/2)\r
433#define P32XI_PWM (1 << 6/2)\r
434\r
435// real one is 4*2, but we use more because we don't lockstep\r
436#define DMAC_FIFO_LEN (4*4)\r
437\r
438struct Pico32x\r
439{\r
440 unsigned short regs[0x20];\r
441 unsigned short vdp_regs[0x10];\r
442 unsigned char pending_fb;\r
443 unsigned char dirty_pal;\r
444 unsigned char pad[2];\r
445 unsigned int emu_flags;\r
446 unsigned char sh2irq_mask[2];\r
447 unsigned char sh2irqi[2]; // individual\r
448 unsigned int sh2irqs; // common irqs\r
449 unsigned short dmac_fifo[DMAC_FIFO_LEN];\r
450 unsigned int dmac_ptr;\r
451};\r
452\r
453struct Pico32xMem\r
454{\r
455 unsigned char sdram[0x40000];\r
456 unsigned short dram[2][0x20000/2]; // AKA fb\r
457 unsigned char m68k_rom[0x10000]; // 0x100; using M68K_BANK_SIZE\r
458 unsigned char sh2_rom_m[0x800];\r
459 unsigned char sh2_rom_s[0x400];\r
460 unsigned short pal[0x100];\r
461 unsigned short pal_native[0x100]; // converted to native (for renderer)\r
462 unsigned int sh2_peri_regs[2][0x200/4]; // periphereal regs of SH2s\r
463};\r
464\r
465// area.c\r
466PICO_INTERNAL void PicoAreaPackCpu(unsigned char *cpu, int is_sub);\r
467PICO_INTERNAL void PicoAreaUnpackCpu(unsigned char *cpu, int is_sub);\r
468extern void (*PicoLoadStateHook)(void);\r
469\r
470// cd/area.c\r
471PICO_INTERNAL int PicoCdSaveState(void *file);\r
472PICO_INTERNAL int PicoCdLoadState(void *file);\r
473\r
474typedef struct {\r
475 int chunk;\r
476 int size;\r
477 void *ptr;\r
478} carthw_state_chunk;\r
479extern carthw_state_chunk *carthw_chunks;\r
480#define CHUNK_CARTHW 64\r
481\r
482// area.c\r
483typedef size_t (arearw)(void *p, size_t _size, size_t _n, void *file);\r
484typedef size_t (areaeof)(void *file);\r
485typedef int (areaseek)(void *file, long offset, int whence);\r
486typedef int (areaclose)(void *file);\r
487extern arearw *areaRead; // external read and write function pointers for\r
488extern arearw *areaWrite; // gzip save state ability\r
489extern areaeof *areaEof;\r
490extern areaseek *areaSeek;\r
491extern areaclose *areaClose;\r
492\r
493// cart.c\r
494extern void (*PicoCartMemSetup)(void);\r
495extern void (*PicoCartUnloadHook)(void);\r
496\r
497// debug.c\r
498int CM_compareRun(int cyc, int is_sub);\r
499\r
500// draw.c\r
501PICO_INTERNAL void PicoFrameStart(void);\r
502void PicoDrawSync(int to, int blank_last_line);\r
503void BackFill(int reg7, int sh);\r
504void FinalizeLineRGB555(int sh, int line);\r
505extern int DrawScanline;\r
506#define MAX_LINE_SPRITES 29\r
507extern unsigned char HighLnSpr[240][3 + MAX_LINE_SPRITES];\r
508\r
509// draw2.c\r
510PICO_INTERNAL void PicoFrameFull();\r
511\r
512// mode4.c\r
513void PicoFrameStartMode4(void);\r
514void PicoLineMode4(int line);\r
515void PicoDoHighPal555M4(void);\r
516void PicoDrawSetColorFormatMode4(int which);\r
517\r
518// memory.c\r
519PICO_INTERNAL void PicoMemSetup(void);\r
520unsigned int PicoRead8_io(unsigned int a);\r
521unsigned int PicoRead16_io(unsigned int a);\r
522void PicoWrite8_io(unsigned int a, unsigned int d);\r
523void PicoWrite16_io(unsigned int a, unsigned int d);\r
524\r
525// pico/memory.c\r
526PICO_INTERNAL void PicoMemSetupPico(void);\r
527\r
528// cd/memory.c\r
529PICO_INTERNAL void PicoMemSetupCD(void);\r
530void PicoMemStateLoaded(void);\r
531\r
532// pico.c\r
533extern struct Pico Pico;\r
534extern struct PicoSRAM SRam;\r
535extern int PicoPadInt[2];\r
536extern int emustatus;\r
537extern void (*PicoResetHook)(void);\r
538extern void (*PicoLineHook)(void);\r
539PICO_INTERNAL int CheckDMA(void);\r
540PICO_INTERNAL void PicoDetectRegion(void);\r
541PICO_INTERNAL void PicoSyncZ80(int m68k_cycles_done);\r
542\r
543// cd/pico.c\r
544PICO_INTERNAL void PicoInitMCD(void);\r
545PICO_INTERNAL void PicoExitMCD(void);\r
546PICO_INTERNAL void PicoPowerMCD(void);\r
547PICO_INTERNAL int PicoResetMCD(void);\r
548PICO_INTERNAL void PicoFrameMCD(void);\r
549\r
550// pico/pico.c\r
551PICO_INTERNAL void PicoInitPico(void);\r
552PICO_INTERNAL void PicoReratePico(void);\r
553\r
554// pico/xpcm.c\r
555PICO_INTERNAL void PicoPicoPCMUpdate(short *buffer, int length, int stereo);\r
556PICO_INTERNAL void PicoPicoPCMReset(void);\r
557PICO_INTERNAL void PicoPicoPCMRerate(int xpcm_rate);\r
558\r
559// sek.c\r
560PICO_INTERNAL void SekInit(void);\r
561PICO_INTERNAL int SekReset(void);\r
562PICO_INTERNAL void SekState(int *data);\r
563PICO_INTERNAL void SekSetRealTAS(int use_real);\r
564void SekStepM68k(void);\r
565void SekInitIdleDet(void);\r
566void SekFinishIdleDet(void);\r
567\r
568// cd/sek.c\r
569PICO_INTERNAL void SekInitS68k(void);\r
570PICO_INTERNAL int SekResetS68k(void);\r
571PICO_INTERNAL int SekInterruptS68k(int irq);\r
572\r
573// sound/sound.c\r
574PICO_INTERNAL void cdda_start_play();\r
575extern short cdda_out_buffer[2*1152];\r
576extern int PsndLen_exc_cnt;\r
577extern int PsndLen_exc_add;\r
578extern int timer_a_next_oflow, timer_a_step; // in z80 cycles\r
579extern int timer_b_next_oflow, timer_b_step;\r
580\r
581void ym2612_sync_timers(int z80_cycles, int mode_old, int mode_new);\r
582void ym2612_pack_state(void);\r
583void ym2612_unpack_state(void);\r
584\r
585#define TIMER_NO_OFLOW 0x70000000\r
586// tA = 72 * (1024 - NA) / M\r
587#define TIMER_A_TICK_ZCYCLES 17203\r
588// tB = 1152 * (256 - NA) / M\r
589#define TIMER_B_TICK_ZCYCLES 262800 // 275251 broken, see Dai Makaimura\r
590\r
591#define timers_cycle() \\r
592 if (timer_a_next_oflow > 0 && timer_a_next_oflow < TIMER_NO_OFLOW) \\r
593 timer_a_next_oflow -= Pico.m.pal ? 70938*256 : 59659*256; \\r
594 if (timer_b_next_oflow > 0 && timer_b_next_oflow < TIMER_NO_OFLOW) \\r
595 timer_b_next_oflow -= Pico.m.pal ? 70938*256 : 59659*256; \\r
596 ym2612_sync_timers(0, ym2612.OPN.ST.mode, ym2612.OPN.ST.mode);\r
597\r
598#define timers_reset() \\r
599 timer_a_next_oflow = timer_b_next_oflow = TIMER_NO_OFLOW; \\r
600 timer_a_step = TIMER_A_TICK_ZCYCLES * 1024; \\r
601 timer_b_step = TIMER_B_TICK_ZCYCLES * 256;\r
602\r
603\r
604// videoport.c\r
605PICO_INTERNAL_ASM void PicoVideoWrite(unsigned int a,unsigned short d);\r
606PICO_INTERNAL_ASM unsigned int PicoVideoRead(unsigned int a);\r
607PICO_INTERNAL_ASM unsigned int PicoVideoRead8(unsigned int a);\r
608extern int (*PicoDmaHook)(unsigned int source, int len, unsigned short **srcp, unsigned short **limitp);\r
609\r
610// misc.c\r
611PICO_INTERNAL_ASM void memcpy16(unsigned short *dest, unsigned short *src, int count);\r
612PICO_INTERNAL_ASM void memcpy16bswap(unsigned short *dest, void *src, int count);\r
613PICO_INTERNAL_ASM void memcpy32(int *dest, int *src, int count); // 32bit word count\r
614PICO_INTERNAL_ASM void memset32(int *dest, int c, int count);\r
615\r
616// eeprom.c\r
617void EEPROM_write8(unsigned int a, unsigned int d);\r
618void EEPROM_write16(unsigned int d);\r
619unsigned int EEPROM_read(void);\r
620\r
621// z80 functionality wrappers\r
622PICO_INTERNAL void z80_init(void);\r
623PICO_INTERNAL void z80_pack(unsigned char *data);\r
624PICO_INTERNAL void z80_unpack(unsigned char *data);\r
625PICO_INTERNAL void z80_reset(void);\r
626PICO_INTERNAL void z80_exit(void);\r
627\r
628// cd/misc.c\r
629PICO_INTERNAL_ASM void wram_2M_to_1M(unsigned char *m);\r
630PICO_INTERNAL_ASM void wram_1M_to_2M(unsigned char *m);\r
631\r
632// cd/buffering.c\r
633PICO_INTERNAL void PicoCDBufferRead(void *dest, int lba);\r
634\r
635// sound/sound.c\r
636PICO_INTERNAL void PsndReset(void);\r
637PICO_INTERNAL void PsndDoDAC(int line_to);\r
638PICO_INTERNAL void PsndClear(void);\r
639PICO_INTERNAL void PsndGetSamples(int y);\r
640PICO_INTERNAL void PsndGetSamplesMS(void);\r
641extern int PsndDacLine;\r
642\r
643// sms.c\r
644void PicoPowerMS(void);\r
645void PicoResetMS(void);\r
646void PicoMemSetupMS(void);\r
647void PicoFrameMS(void);\r
648void PicoFrameDrawOnlyMS(void);\r
649\r
650// 32x/32x.c\r
651extern struct Pico32x Pico32x;\r
652void Pico32xInit(void);\r
653void PicoPower32x(void);\r
654void PicoReset32x(void);\r
655void Pico32xStartup(void);\r
656void PicoUnload32x(void);\r
657void PicoFrame32x(void);\r
658void p32x_update_irls(void);\r
659\r
660// 32x/memory.c\r
661struct Pico32xMem *Pico32xMem;\r
662unsigned int PicoRead8_32x(unsigned int a);\r
663unsigned int PicoRead16_32x(unsigned int a);\r
664void PicoWrite8_32x(unsigned int a, unsigned int d);\r
665void PicoWrite16_32x(unsigned int a, unsigned int d);\r
666void PicoMemSetup32x(void);\r
667void Pico32xSwapDRAM(int b);\r
668void p32x_poll_event(int is_vdp);\r
669\r
670// 32x/draw.c\r
671void FinalizeLine32xRGB555(int sh, int line);\r
672\r
673/* avoid dependency on newer glibc */\r
674static __inline int isspace_(int c)\r
675{\r
676 return (0x09 <= c && c <= 0x0d) || c == ' ';\r
677}\r
678\r
679// emulation event logging\r
680#ifndef EL_LOGMASK\r
681#define EL_LOGMASK 0\r
682#endif\r
683\r
684#define EL_HVCNT 0x00000001 /* hv counter reads */\r
685#define EL_SR 0x00000002 /* SR reads */\r
686#define EL_INTS 0x00000004 /* ints and acks */\r
687#define EL_YMTIMER 0x00000008 /* ym2612 timer stuff */\r
688#define EL_INTSW 0x00000010 /* log irq switching on/off */\r
689#define EL_ASVDP 0x00000020 /* VDP accesses during active scan */\r
690#define EL_VDPDMA 0x00000040 /* VDP DMA transfers and their timing */\r
691#define EL_BUSREQ 0x00000080 /* z80 busreq r/w or reset w */\r
692#define EL_Z80BNK 0x00000100 /* z80 i/o through bank area */\r
693#define EL_SRAMIO 0x00000200 /* sram i/o */\r
694#define EL_EEPROM 0x00000400 /* eeprom debug */\r
695#define EL_UIO 0x00000800 /* unmapped i/o */\r
696#define EL_IO 0x00001000 /* all i/o */\r
697#define EL_CDPOLL 0x00002000 /* MCD: log poll detection */\r
698#define EL_SVP 0x00004000 /* SVP stuff */\r
699#define EL_PICOHW 0x00008000 /* Pico stuff */\r
700#define EL_IDLE 0x00010000 /* idle loop det. */\r
701#define EL_CDREGS 0x00020000 /* MCD: register access */\r
702#define EL_CDREG3 0x00040000 /* MCD: register 3 only */\r
703#define EL_32X 0x00080000\r
704\r
705#define EL_STATUS 0x40000000 /* status messages */\r
706#define EL_ANOMALY 0x80000000 /* some unexpected conditions (during emulation) */\r
707\r
708#if EL_LOGMASK\r
709extern void lprintf(const char *fmt, ...);\r
710#define elprintf(w,f,...) \\r
711{ \\r
712 if ((w) & EL_LOGMASK) \\r
713 lprintf("%05i:%03i: " f "\n",Pico.m.frame_count,Pico.m.scanline,##__VA_ARGS__); \\r
714}\r
715#elif defined(_MSC_VER)\r
716#define elprintf\r
717#else\r
718#define elprintf(w,f,...)\r
719#endif\r
720\r
721#ifdef _MSC_VER\r
722#define cdprintf\r
723#else\r
724#define cdprintf(x...)\r
725#endif\r
726\r
727#if defined(__GNUC__) && __GNUC__ >= 4 && __GNUC_MINOR__ >= 3\r
728#define MEMH_FUNC __attribute__((aligned(4)))\r
729#else\r
730#define MEMH_FUNC\r
731#endif\r
732\r
733#ifdef __GNUC__\r
734#define NOINLINE __attribute__((noinline))\r
735#else\r
736#define NOINLINE\r
737#endif\r
738\r
739#ifdef __cplusplus\r
740} // End of extern "C"\r
741#endif\r
742\r
743#endif // PICO_INTERNAL_INCLUDED\r
744\r
fast MegaDrive/MegaCD/32X emulator