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drZ80 separation finished, related bugs fixed
[picodrive.git] / pico / pico_int.h
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1// Pico Library - Internal Header File\r
2\r
3// (c) Copyright 2004 Dave, All rights reserved.\r
4// (c) Copyright 2006-2008 Grazvydas "notaz" Ignotas, all rights reserved.\r
5// Free for non-commercial use.\r
6\r
7// For commercial use, separate licencing terms must be obtained.\r
8\r
9#ifndef PICO_INTERNAL_INCLUDED\r
10#define PICO_INTERNAL_INCLUDED\r
11\r
12#include <stdio.h>\r
13#include <stdlib.h>\r
14#include <string.h>\r
15#include "pico.h"\r
16#include "carthw/carthw.h"\r
17\r
18//\r
19#define USE_POLL_DETECT\r
20\r
21#ifndef PICO_INTERNAL\r
22#define PICO_INTERNAL\r
23#endif\r
24#ifndef PICO_INTERNAL_ASM\r
25#define PICO_INTERNAL_ASM\r
26#endif\r
27\r
28// to select core, define EMU_C68K, EMU_M68K or EMU_F68K in your makefile or project\r
29\r
30#ifdef __cplusplus\r
31extern "C" {\r
32#endif\r
33\r
34\r
35// ----------------------- 68000 CPU -----------------------\r
36#ifdef EMU_C68K\r
37#include "../cpu/Cyclone/Cyclone.h"\r
38extern struct Cyclone PicoCpuCM68k, PicoCpuCS68k;\r
39#define SekCyclesLeftNoMCD PicoCpuCM68k.cycles // cycles left for this run\r
40#define SekCyclesLeft \\r
41 (((PicoAHW&1) && (PicoOpt & POPT_EN_MCD_PSYNC)) ? (SekCycleAim-SekCycleCnt) : SekCyclesLeftNoMCD)\r
42#define SekCyclesLeftS68k \\r
43 ((PicoOpt & POPT_EN_MCD_PSYNC) ? (SekCycleAimS68k-SekCycleCntS68k) : PicoCpuCS68k.cycles)\r
44#define SekEndTimeslice(after) PicoCpuCM68k.cycles=after\r
45#define SekEndTimesliceS68k(after) PicoCpuCS68k.cycles=after\r
46#define SekPc (PicoCpuCM68k.pc-PicoCpuCM68k.membase)\r
47#define SekPcS68k (PicoCpuCS68k.pc-PicoCpuCS68k.membase)\r
48#define SekSetStop(x) { PicoCpuCM68k.state_flags&=~1; if (x) { PicoCpuCM68k.state_flags|=1; PicoCpuCM68k.cycles=0; } }\r
49#define SekSetStopS68k(x) { PicoCpuCS68k.state_flags&=~1; if (x) { PicoCpuCS68k.state_flags|=1; PicoCpuCS68k.cycles=0; } }\r
50#define SekIsStoppedS68k() (PicoCpuCS68k.state_flags&1)\r
51#define SekShouldInterrupt (PicoCpuCM68k.irq > (PicoCpuCM68k.srh&7))\r
52\r
53#define SekInterrupt(i) PicoCpuCM68k.irq=i\r
54\r
55#ifdef EMU_M68K\r
56#define EMU_CORE_DEBUG\r
57#endif\r
58#endif\r
59\r
60#ifdef EMU_F68K\r
61#include "../cpu/fame/fame.h"\r
62extern M68K_CONTEXT PicoCpuFM68k, PicoCpuFS68k;\r
63#define SekCyclesLeftNoMCD PicoCpuFM68k.io_cycle_counter\r
64#define SekCyclesLeft \\r
65 (((PicoAHW&1) && (PicoOpt & POPT_EN_MCD_PSYNC)) ? (SekCycleAim-SekCycleCnt) : SekCyclesLeftNoMCD)\r
66#define SekCyclesLeftS68k \\r
67 ((PicoOpt & POPT_EN_MCD_PSYNC) ? (SekCycleAimS68k-SekCycleCntS68k) : PicoCpuFS68k.io_cycle_counter)\r
68#define SekEndTimeslice(after) PicoCpuFM68k.io_cycle_counter=after\r
69#define SekEndTimesliceS68k(after) PicoCpuFS68k.io_cycle_counter=after\r
70#define SekPc fm68k_get_pc(&PicoCpuFM68k)\r
71#define SekPcS68k fm68k_get_pc(&PicoCpuFS68k)\r
72#define SekSetStop(x) { \\r
73 PicoCpuFM68k.execinfo &= ~FM68K_HALTED; \\r
74 if (x) { PicoCpuFM68k.execinfo |= FM68K_HALTED; PicoCpuFM68k.io_cycle_counter = 0; } \\r
75}\r
76#define SekSetStopS68k(x) { \\r
77 PicoCpuFS68k.execinfo &= ~FM68K_HALTED; \\r
78 if (x) { PicoCpuFS68k.execinfo |= FM68K_HALTED; PicoCpuFS68k.io_cycle_counter = 0; } \\r
79}\r
80#define SekIsStoppedS68k() (PicoCpuFS68k.execinfo&FM68K_HALTED)\r
81#define SekShouldInterrupt fm68k_would_interrupt()\r
82\r
83#define SekInterrupt(irq) PicoCpuFM68k.interrupts[0]=irq\r
84\r
85#ifdef EMU_M68K\r
86#define EMU_CORE_DEBUG\r
87#endif\r
88#endif\r
89\r
90#ifdef EMU_M68K\r
91#include "../cpu/musashi/m68kcpu.h"\r
92extern m68ki_cpu_core PicoCpuMM68k, PicoCpuMS68k;\r
93#ifndef SekCyclesLeft\r
94#define SekCyclesLeftNoMCD PicoCpuMM68k.cyc_remaining_cycles\r
95#define SekCyclesLeft \\r
96 (((PicoAHW&1) && (PicoOpt & POPT_EN_MCD_PSYNC)) ? (SekCycleAim-SekCycleCnt) : SekCyclesLeftNoMCD)\r
97#define SekCyclesLeftS68k \\r
98 ((PicoOpt & POPT_EN_MCD_PSYNC) ? (SekCycleAimS68k-SekCycleCntS68k) : PicoCpuMS68k.cyc_remaining_cycles)\r
99#define SekEndTimeslice(after) SET_CYCLES(after)\r
100#define SekEndTimesliceS68k(after) PicoCpuMS68k.cyc_remaining_cycles=after\r
101#define SekPc m68k_get_reg(&PicoCpuMM68k, M68K_REG_PC)\r
102#define SekPcS68k m68k_get_reg(&PicoCpuMS68k, M68K_REG_PC)\r
103#define SekSetStop(x) { \\r
104 if(x) { SET_CYCLES(0); PicoCpuMM68k.stopped=STOP_LEVEL_STOP; } \\r
105 else PicoCpuMM68k.stopped=0; \\r
106}\r
107#define SekSetStopS68k(x) { \\r
108 if(x) { SET_CYCLES(0); PicoCpuMS68k.stopped=STOP_LEVEL_STOP; } \\r
109 else PicoCpuMS68k.stopped=0; \\r
110}\r
111#define SekIsStoppedS68k() (PicoCpuMS68k.stopped==STOP_LEVEL_STOP)\r
112#define SekShouldInterrupt (CPU_INT_LEVEL > FLAG_INT_MASK)\r
113\r
114#define SekInterrupt(irq) { \\r
115 void *oldcontext = m68ki_cpu_p; \\r
116 m68k_set_context(&PicoCpuMM68k); \\r
117 m68k_set_irq(irq); \\r
118 m68k_set_context(oldcontext); \\r
119}\r
120\r
121#endif\r
122#endif // EMU_M68K\r
123\r
124extern int SekCycleCnt; // cycles done in this frame\r
125extern int SekCycleAim; // cycle aim\r
126extern unsigned int SekCycleCntT; // total cycle counter, updated once per frame\r
127\r
128#define SekCyclesReset() { \\r
129 SekCycleCntT+=SekCycleAim; \\r
130 SekCycleCnt-=SekCycleAim; \\r
131 SekCycleAim=0; \\r
132}\r
133#define SekCyclesBurn(c) SekCycleCnt+=c\r
134#define SekCyclesDone() (SekCycleAim-SekCyclesLeft) // number of cycles done in this frame (can be checked anywhere)\r
135#define SekCyclesDoneT() (SekCycleCntT+SekCyclesDone()) // total nuber of cycles done for this rom\r
136\r
137#define SekEndRun(after) { \\r
138 SekCycleCnt -= SekCyclesLeft - (after); \\r
139 if (SekCycleCnt < 0) SekCycleCnt = 0; \\r
140 SekEndTimeslice(after); \\r
141}\r
142\r
143#define SekEndRunS68k(after) { \\r
144 SekCycleCntS68k -= SekCyclesLeftS68k - (after); \\r
145 if (SekCycleCntS68k < 0) SekCycleCntS68k = 0; \\r
146 SekEndTimesliceS68k(after); \\r
147}\r
148\r
149extern int SekCycleCntS68k;\r
150extern int SekCycleAimS68k;\r
151\r
152#define SekCyclesResetS68k() { \\r
153 SekCycleCntS68k-=SekCycleAimS68k; \\r
154 SekCycleAimS68k=0; \\r
155}\r
156#define SekCyclesDoneS68k() (SekCycleAimS68k-SekCyclesLeftS68k)\r
157\r
158#ifdef EMU_CORE_DEBUG\r
159extern int dbg_irq_level;\r
160#undef SekEndTimeslice\r
161#undef SekCyclesBurn\r
162#undef SekEndRun\r
163#undef SekInterrupt\r
164#define SekEndTimeslice(c)\r
165#define SekCyclesBurn(c) c\r
166#define SekEndRun(c)\r
167#define SekInterrupt(irq) dbg_irq_level=irq\r
168#endif\r
169\r
170// ----------------------- Z80 CPU -----------------------\r
171\r
172#if defined(_USE_MZ80)\r
173#include "../cpu/mz80/mz80.h"\r
174\r
175#define z80_run(cycles) { mz80GetElapsedTicks(1); mz80_run(cycles) }\r
176#define z80_run_nr(cycles) mz80_run(cycles)\r
177#define z80_int() mz80int(0)\r
178\r
179#elif defined(_USE_DRZ80)\r
180#include "../cpu/DrZ80/drz80.h"\r
181\r
182extern struct DrZ80 drZ80;\r
183\r
184#define z80_run(cycles) ((cycles) - DrZ80Run(&drZ80, cycles))\r
185#define z80_run_nr(cycles) DrZ80Run(&drZ80, cycles)\r
186#define z80_int() drZ80.Z80_IRQ = 1\r
187\r
188#define z80_cyclesLeft drZ80.cycles\r
189\r
190#elif defined(_USE_CZ80)\r
191#include "../cpu/cz80/cz80.h"\r
192\r
193#define z80_run(cycles) Cz80_Exec(&CZ80, cycles)\r
194#define z80_run_nr(cycles) Cz80_Exec(&CZ80, cycles)\r
195#define z80_int() Cz80_Set_IRQ(&CZ80, 0, HOLD_LINE)\r
196\r
197#define z80_cyclesLeft (CZ80.ICount - CZ80.ExtraCycles)\r
198\r
199#else\r
200\r
201#define z80_run(cycles) (cycles)\r
202#define z80_run_nr(cycles)\r
203#define z80_int()\r
204\r
205#endif\r
206\r
207extern int z80stopCycle; /* in 68k cycles */\r
208extern int z80_cycle_cnt; /* 'done' z80 cycles before z80_run() */\r
209extern int z80_cycle_aim;\r
210extern int z80_scanline;\r
211extern int z80_scanline_cycles; /* cycles done until z80_scanline */\r
212\r
213#define z80_resetCycles() \\r
214 z80_cycle_cnt = z80_cycle_aim = z80_scanline = z80_scanline_cycles = 0;\r
215\r
216#define z80_cyclesDone() \\r
217 (z80_cycle_aim - z80_cyclesLeft)\r
218\r
219#define cycles_68k_to_z80(x) ((x)*957 >> 11)\r
220\r
221#define Z80_MEM_SHIFT 13\r
222extern unsigned long z80_read_map [0x10000 >> Z80_MEM_SHIFT];\r
223extern unsigned long z80_write_map[0x10000 >> Z80_MEM_SHIFT];\r
224typedef unsigned char (z80_read_f)(unsigned short a);\r
225typedef void (z80_write_f)(unsigned int a, unsigned char data);\r
226\r
227// ---------------------------------------------------------\r
228\r
229// main oscillator clock which controls timing\r
230#define OSC_NTSC 53693100\r
231#define OSC_PAL 53203424\r
232\r
233struct PicoVideo\r
234{\r
235 unsigned char reg[0x20];\r
236 unsigned int command; // 32-bit Command\r
237 unsigned char pending; // 1 if waiting for second half of 32-bit command\r
238 unsigned char type; // Command type (v/c/vsram read/write)\r
239 unsigned short addr; // Read/Write address\r
240 int status; // Status bits\r
241 unsigned char pending_ints; // pending interrupts: ??VH????\r
242 signed char lwrite_cnt; // VDP write count during active display line\r
243 unsigned short v_counter; // V-counter\r
244 unsigned char pad[0x10];\r
245};\r
246\r
247struct PicoMisc\r
248{\r
249 unsigned char rotate;\r
250 unsigned char z80Run;\r
251 unsigned char padTHPhase[2]; // 02 phase of gamepad TH switches\r
252 unsigned short scanline; // 04 0 to 261||311\r
253 char dirtyPal; // 06 Is the palette dirty (1 - change @ this frame, 2 - some time before)\r
254 unsigned char hardware; // 07 Hardware value for country\r
255 unsigned char pal; // 08 1=PAL 0=NTSC\r
256 unsigned char sram_reg; // SRAM mode register. bit0: allow read? bit1: deny write? bit2: EEPROM? bit4: detected? (header or by access)\r
257 unsigned short z80_bank68k; // 0a\r
258 unsigned short z80_lastaddr; // this is for Z80 faking\r
259 unsigned char z80_fakeval;\r
260 unsigned char z80_reset; // z80 reset held\r
261 unsigned char padDelay[2]; // 10 gamepad phase time outs, so we count a delay\r
262 unsigned short eeprom_addr; // EEPROM address register\r
263 unsigned char eeprom_cycle; // EEPROM SRAM cycle number\r
264 unsigned char eeprom_slave; // EEPROM slave word for X24C02 and better SRAMs\r
265 unsigned char prot_bytes[2]; // simple protection faking\r
266 unsigned short dma_xfers; // 18\r
267 unsigned char pad[2];\r
268 unsigned int frame_count; // 1c for movies and idle det\r
269};\r
270\r
271// some assembly stuff depend on these, do not touch!\r
272struct Pico\r
273{\r
274 unsigned char ram[0x10000]; // 0x00000 scratch ram\r
275 unsigned short vram[0x8000]; // 0x10000\r
276 unsigned char zram[0x2000]; // 0x20000 Z80 ram\r
277 unsigned char ioports[0x10];\r
278 unsigned int pad[0x3c]; // unused\r
279 unsigned short cram[0x40]; // 0x22100\r
280 unsigned short vsram[0x40]; // 0x22180\r
281\r
282 unsigned char *rom; // 0x22200\r
283 unsigned int romsize; // 0x22204\r
284\r
285 struct PicoMisc m;\r
286 struct PicoVideo video;\r
287};\r
288\r
289// sram\r
290struct PicoSRAM\r
291{\r
292 unsigned char *data; // actual data\r
293 unsigned int start; // start address in 68k address space\r
294 unsigned int end;\r
295 unsigned char unused1; // 0c: unused\r
296 unsigned char unused2;\r
297 unsigned char changed;\r
298 unsigned char eeprom_type; // eeprom type: 0: 7bit (24C01), 2: device with 2 addr words (X24C02+), 3: dev with 3 addr words\r
299 unsigned char eeprom_abits; // eeprom access must be odd addr for: bit0 ~ cl, bit1 ~ out\r
300 unsigned char eeprom_bit_cl; // bit number for cl\r
301 unsigned char eeprom_bit_in; // bit number for in\r
302 unsigned char eeprom_bit_out; // bit number for out\r
303};\r
304\r
305// MCD\r
306#include "cd/cd_sys.h"\r
307#include "cd/LC89510.h"\r
308#include "cd/gfx_cd.h"\r
309\r
310struct mcd_pcm\r
311{\r
312 unsigned char control; // reg7\r
313 unsigned char enabled; // reg8\r
314 unsigned char cur_ch;\r
315 unsigned char bank;\r
316 int pad1;\r
317\r
318 struct pcm_chan // 08, size 0x10\r
319 {\r
320 unsigned char regs[8];\r
321 unsigned int addr; // .08: played sample address\r
322 int pad;\r
323 } ch[8];\r
324};\r
325\r
326struct mcd_misc\r
327{\r
328 unsigned short hint_vector;\r
329 unsigned char busreq;\r
330 unsigned char s68k_pend_ints;\r
331 unsigned int state_flags; // 04: emu state: reset_pending\r
332 unsigned int counter75hz;\r
333 unsigned int pad0;\r
334 int timer_int3; // 10\r
335 unsigned int timer_stopwatch;\r
336 unsigned char bcram_reg; // 18: battery-backed RAM cart register\r
337 unsigned char pad2;\r
338 unsigned short pad3;\r
339 int pad[9];\r
340};\r
341\r
342typedef struct\r
343{\r
344 unsigned char bios[0x20000]; // 000000: 128K\r
345 union { // 020000: 512K\r
346 unsigned char prg_ram[0x80000];\r
347 unsigned char prg_ram_b[4][0x20000];\r
348 };\r
349 union { // 0a0000: 256K\r
350 struct {\r
351 unsigned char word_ram2M[0x40000];\r
352 unsigned char unused0[0x20000];\r
353 };\r
354 struct {\r
355 unsigned char unused1[0x20000];\r
356 unsigned char word_ram1M[2][0x20000];\r
357 };\r
358 };\r
359 union { // 100000: 64K\r
360 unsigned char pcm_ram[0x10000];\r
361 unsigned char pcm_ram_b[0x10][0x1000];\r
362 };\r
363 unsigned char s68k_regs[0x200]; // 110000: GA, not CPU regs\r
364 unsigned char bram[0x2000]; // 110200: 8K\r
365 struct mcd_misc m; // 112200: misc\r
366 struct mcd_pcm pcm; // 112240:\r
367 _scd_toc TOC; // not to be saved\r
368 CDD cdd;\r
369 CDC cdc;\r
370 _scd scd;\r
371 Rot_Comp rot_comp;\r
372} mcd_state;\r
373\r
374#define Pico_mcd ((mcd_state *)Pico.rom)\r
375\r
376\r
377// area.c\r
378PICO_INTERNAL void PicoAreaPackCpu(unsigned char *cpu, int is_sub);\r
379PICO_INTERNAL void PicoAreaUnpackCpu(unsigned char *cpu, int is_sub);\r
380extern void (*PicoLoadStateHook)(void);\r
381\r
382// cd/area.c\r
383PICO_INTERNAL int PicoCdSaveState(void *file);\r
384PICO_INTERNAL int PicoCdLoadState(void *file);\r
385\r
386typedef struct {\r
387 int chunk;\r
388 int size;\r
389 void *ptr;\r
390} carthw_state_chunk;\r
391extern carthw_state_chunk *carthw_chunks;\r
392#define CHUNK_CARTHW 64\r
393\r
394// area.c\r
395typedef size_t (arearw)(void *p, size_t _size, size_t _n, void *file);\r
396typedef size_t (areaeof)(void *file);\r
397typedef int (areaseek)(void *file, long offset, int whence);\r
398typedef int (areaclose)(void *file);\r
399extern arearw *areaRead; // external read and write function pointers for\r
400extern arearw *areaWrite; // gzip save state ability\r
401extern areaeof *areaEof;\r
402extern areaseek *areaSeek;\r
403extern areaclose *areaClose;\r
404\r
405// cart.c\r
406extern void (*PicoCartUnloadHook)(void);\r
407\r
408// debug.c\r
409int CM_compareRun(int cyc, int is_sub);\r
410\r
411// draw.c\r
412PICO_INTERNAL void PicoFrameStart(void);\r
413void PicoDrawSync(int to, int blank_last_line);\r
414extern int DrawScanline;\r
415#define MAX_LINE_SPRITES 29\r
416extern unsigned char HighLnSpr[240][3 + MAX_LINE_SPRITES];\r
417\r
418// draw2.c\r
419PICO_INTERNAL void PicoFrameFull();\r
420\r
421// memory.c\r
422PICO_INTERNAL void PicoInitPc(unsigned int pc);\r
423PICO_INTERNAL unsigned int PicoCheckPc(unsigned int pc);\r
424PICO_INTERNAL_ASM unsigned int PicoRead32(unsigned int a);\r
425PICO_INTERNAL void PicoMemSetup(void);\r
426PICO_INTERNAL_ASM void PicoMemReset(void);\r
427PICO_INTERNAL void PicoMemResetHooks(void);\r
428PICO_INTERNAL int PadRead(int i);\r
429PICO_INTERNAL int ym2612_write_local(unsigned int a, unsigned int d, int is_from_z80);\r
430void z80_mem_setup(void);\r
431extern unsigned int (*PicoRead16Hook)(unsigned int a, int realsize);\r
432extern void (*PicoWrite8Hook) (unsigned int a,unsigned int d,int realsize);\r
433extern void (*PicoWrite16Hook)(unsigned int a,unsigned int d,int realsize);\r
434\r
435// cd/memory.c\r
436PICO_INTERNAL void PicoMemSetupCD(void);\r
437PICO_INTERNAL_ASM void PicoMemResetCD(int r3);\r
438PICO_INTERNAL_ASM void PicoMemResetCDdecode(int r3);\r
439\r
440// pico/memory.c\r
441PICO_INTERNAL void PicoMemSetupPico(void);\r
442PICO_INTERNAL unsigned int ym2612_read_local_68k(void);\r
443\r
444// pico.c\r
445extern struct Pico Pico;\r
446extern struct PicoSRAM SRam;\r
447extern int PicoPadInt[2];\r
448extern int emustatus;\r
449extern void (*PicoResetHook)(void);\r
450extern void (*PicoLineHook)(void);\r
451PICO_INTERNAL int CheckDMA(void);\r
452PICO_INTERNAL void PicoDetectRegion(void);\r
453PICO_INTERNAL void PicoSyncZ80(int m68k_cycles_done);\r
454\r
455// cd/pico.c\r
456PICO_INTERNAL void PicoInitMCD(void);\r
457PICO_INTERNAL void PicoExitMCD(void);\r
458PICO_INTERNAL void PicoPowerMCD(void);\r
459PICO_INTERNAL int PicoResetMCD(void);\r
460PICO_INTERNAL void PicoFrameMCD(void);\r
461\r
462// pico/pico.c\r
463PICO_INTERNAL void PicoInitPico(void);\r
464PICO_INTERNAL void PicoReratePico(void);\r
465\r
466// pico/xpcm.c\r
467PICO_INTERNAL void PicoPicoPCMUpdate(short *buffer, int length, int stereo);\r
468PICO_INTERNAL void PicoPicoPCMReset(void);\r
469PICO_INTERNAL void PicoPicoPCMRerate(int xpcm_rate);\r
470\r
471// sek.c\r
472PICO_INTERNAL void SekInit(void);\r
473PICO_INTERNAL int SekReset(void);\r
474PICO_INTERNAL void SekState(int *data);\r
475PICO_INTERNAL void SekSetRealTAS(int use_real);\r
476void SekStepM68k(void);\r
477void SekInitIdleDet(void);\r
478void SekFinishIdleDet(void);\r
479\r
480// cd/sek.c\r
481PICO_INTERNAL void SekInitS68k(void);\r
482PICO_INTERNAL int SekResetS68k(void);\r
483PICO_INTERNAL int SekInterruptS68k(int irq);\r
484\r
485// sound/sound.c\r
486PICO_INTERNAL void cdda_start_play();\r
487extern short cdda_out_buffer[2*1152];\r
488extern int PsndLen_exc_cnt;\r
489extern int PsndLen_exc_add;\r
490extern int timer_a_next_oflow, timer_a_step; // in z80 cycles\r
491extern int timer_b_next_oflow, timer_b_step;\r
492\r
493void ym2612_sync_timers(int z80_cycles, int mode_old, int mode_new);\r
494void ym2612_pack_state(void);\r
495void ym2612_unpack_state(void);\r
496\r
497#define TIMER_NO_OFLOW 0x70000000\r
498// tA = 72 * (1024 - NA) / M\r
499#define TIMER_A_TICK_ZCYCLES 17203\r
500// tB = 1152 * (256 - NA) / M\r
501#define TIMER_B_TICK_ZCYCLES 262800 // 275251 broken, see Dai Makaimura\r
502\r
503#define timers_cycle() \\r
504 if (timer_a_next_oflow > 0 && timer_a_next_oflow < TIMER_NO_OFLOW) \\r
505 timer_a_next_oflow -= Pico.m.pal ? 70938*256 : 59659*256; \\r
506 if (timer_b_next_oflow > 0 && timer_b_next_oflow < TIMER_NO_OFLOW) \\r
507 timer_b_next_oflow -= Pico.m.pal ? 70938*256 : 59659*256; \\r
508 ym2612_sync_timers(0, ym2612.OPN.ST.mode, ym2612.OPN.ST.mode);\r
509\r
510#define timers_reset() \\r
511 timer_a_next_oflow = timer_b_next_oflow = TIMER_NO_OFLOW; \\r
512 timer_a_step = TIMER_A_TICK_ZCYCLES * 1024; \\r
513 timer_b_step = TIMER_B_TICK_ZCYCLES * 256;\r
514\r
515\r
516// videoport.c\r
517PICO_INTERNAL_ASM void PicoVideoWrite(unsigned int a,unsigned short d);\r
518PICO_INTERNAL_ASM unsigned int PicoVideoRead(unsigned int a);\r
519PICO_INTERNAL_ASM unsigned int PicoVideoRead8(unsigned int a);\r
520extern int (*PicoDmaHook)(unsigned int source, int len, unsigned short **srcp, unsigned short **limitp);\r
521\r
522// misc.c\r
523PICO_INTERNAL void SRAMWriteEEPROM(unsigned int d);\r
524PICO_INTERNAL void SRAMUpdPending(unsigned int a, unsigned int d);\r
525PICO_INTERNAL_ASM unsigned int SRAMReadEEPROM(void);\r
526PICO_INTERNAL_ASM void memcpy16(unsigned short *dest, unsigned short *src, int count);\r
527PICO_INTERNAL_ASM void memcpy16bswap(unsigned short *dest, void *src, int count);\r
528PICO_INTERNAL_ASM void memcpy32(int *dest, int *src, int count); // 32bit word count\r
529PICO_INTERNAL_ASM void memset32(int *dest, int c, int count);\r
530\r
531// z80 functionality wrappers\r
532PICO_INTERNAL void z80_init(void);\r
533PICO_INTERNAL void z80_pack(unsigned char *data);\r
534PICO_INTERNAL void z80_unpack(unsigned char *data);\r
535PICO_INTERNAL void z80_reset(void);\r
536PICO_INTERNAL void z80_exit(void);\r
537void z80_map_set(unsigned long *map, int start_addr,\r
538 int end_addr, void *func_or_mh, int is_func);\r
539\r
540// cd/misc.c\r
541PICO_INTERNAL_ASM void wram_2M_to_1M(unsigned char *m);\r
542PICO_INTERNAL_ASM void wram_1M_to_2M(unsigned char *m);\r
543\r
544// cd/buffering.c\r
545PICO_INTERNAL void PicoCDBufferRead(void *dest, int lba);\r
546\r
547// sound/sound.c\r
548PICO_INTERNAL void PsndReset(void);\r
549PICO_INTERNAL void PsndDoDAC(int line_to);\r
550PICO_INTERNAL void PsndClear(void);\r
551PICO_INTERNAL void PsndGetSamples(int y);\r
552extern int PsndDacLine;\r
553\r
554// emulation event logging\r
555#ifndef EL_LOGMASK\r
556#define EL_LOGMASK 0\r
557#endif\r
558\r
559#define EL_HVCNT 0x00000001 /* hv counter reads */\r
560#define EL_SR 0x00000002 /* SR reads */\r
561#define EL_INTS 0x00000004 /* ints and acks */\r
562#define EL_YMTIMER 0x00000008 /* ym2612 timer stuff */\r
563#define EL_INTSW 0x00000010 /* log irq switching on/off */\r
564#define EL_ASVDP 0x00000020 /* VDP accesses during active scan */\r
565#define EL_VDPDMA 0x00000040 /* VDP DMA transfers and their timing */\r
566#define EL_BUSREQ 0x00000080 /* z80 busreq r/w or reset w */\r
567#define EL_Z80BNK 0x00000100 /* z80 i/o through bank area */\r
568#define EL_SRAMIO 0x00000200 /* sram i/o */\r
569#define EL_EEPROM 0x00000400 /* eeprom debug */\r
570#define EL_UIO 0x00000800 /* unmapped i/o */\r
571#define EL_IO 0x00001000 /* all i/o */\r
572#define EL_CDPOLL 0x00002000 /* MCD: log poll detection */\r
573#define EL_SVP 0x00004000 /* SVP stuff */\r
574#define EL_PICOHW 0x00008000 /* Pico stuff */\r
575#define EL_IDLE 0x00010000 /* idle loop det. */\r
576\r
577#define EL_STATUS 0x40000000 /* status messages */\r
578#define EL_ANOMALY 0x80000000 /* some unexpected conditions (during emulation) */\r
579\r
580#if EL_LOGMASK\r
581extern void lprintf(const char *fmt, ...);\r
582#define elprintf(w,f,...) \\r
583{ \\r
584 if ((w) & EL_LOGMASK) \\r
585 lprintf("%05i:%03i: " f "\n",Pico.m.frame_count,Pico.m.scanline,##__VA_ARGS__); \\r
586}\r
587#elif defined(_MSC_VER)\r
588#define elprintf\r
589#else\r
590#define elprintf(w,f,...)\r
591#endif\r
592\r
593#ifdef _MSC_VER\r
594#define cdprintf\r
595#else\r
596#define cdprintf(x...)\r
597#endif\r
598\r
599#if defined(__GNUC__) && !defined(ARM)\r
600#define MEMH_FUNC __attribute__((aligned(4)))\r
601#else\r
602#define MEMH_FUNC\r
603#endif\r
604\r
605#ifdef __cplusplus\r
606} // End of extern "C"\r
607#endif\r
608\r
609#endif // PICO_INTERNAL_INCLUDED\r
610\r
fast MegaDrive/MegaCD/32X emulator