| | 1 | /*\r |
| | 2 | * PicoDrive - Internal Header File\r |
| | 3 | * (c) Copyright Dave, 2004\r |
| | 4 | * (C) notaz, 2006-2010\r |
| | 5 | *\r |
| | 6 | * This work is licensed under the terms of MAME license.\r |
| | 7 | * See COPYING file in the top-level directory.\r |
| | 8 | */\r |
| | 9 | \r |
| | 10 | #ifndef PICO_INTERNAL_INCLUDED\r |
| | 11 | #define PICO_INTERNAL_INCLUDED\r |
| | 12 | \r |
| | 13 | #include <stdio.h>\r |
| | 14 | #include <stdlib.h>\r |
| | 15 | #include <string.h>\r |
| | 16 | #include "pico.h"\r |
| | 17 | #include "carthw/carthw.h"\r |
| | 18 | \r |
| | 19 | //\r |
| | 20 | #define USE_POLL_DETECT\r |
| | 21 | \r |
| | 22 | #ifndef PICO_INTERNAL\r |
| | 23 | #define PICO_INTERNAL\r |
| | 24 | #endif\r |
| | 25 | #ifndef PICO_INTERNAL_ASM\r |
| | 26 | #define PICO_INTERNAL_ASM\r |
| | 27 | #endif\r |
| | 28 | \r |
| | 29 | // to select core, define EMU_C68K, EMU_M68K or EMU_F68K in your makefile or project\r |
| | 30 | \r |
| | 31 | #ifdef __cplusplus\r |
| | 32 | extern "C" {\r |
| | 33 | #endif\r |
| | 34 | \r |
| | 35 | \r |
| | 36 | // ----------------------- 68000 CPU -----------------------\r |
| | 37 | #ifdef EMU_C68K\r |
| | 38 | #include "../cpu/cyclone/Cyclone.h"\r |
| | 39 | extern struct Cyclone PicoCpuCM68k, PicoCpuCS68k;\r |
| | 40 | #define SekCyclesLeftNoMCD PicoCpuCM68k.cycles // cycles left for this run\r |
| | 41 | #define SekCyclesLeft \\r |
| | 42 | (((PicoAHW&1) && (PicoOpt & POPT_EN_MCD_PSYNC)) ? (SekCycleAim-SekCycleCnt) : SekCyclesLeftNoMCD)\r |
| | 43 | #define SekCyclesLeftS68k \\r |
| | 44 | ((PicoOpt & POPT_EN_MCD_PSYNC) ? (SekCycleAimS68k-SekCycleCntS68k) : PicoCpuCS68k.cycles)\r |
| | 45 | #define SekEndTimeslice(after) PicoCpuCM68k.cycles=after\r |
| | 46 | #define SekEndTimesliceS68k(after) PicoCpuCS68k.cycles=after\r |
| | 47 | #define SekPc (PicoCpuCM68k.pc-PicoCpuCM68k.membase)\r |
| | 48 | #define SekPcS68k (PicoCpuCS68k.pc-PicoCpuCS68k.membase)\r |
| | 49 | #define SekDar(x) (x < 8 ? PicoCpuCM68k.d[x] : PicoCpuCM68k.a[x - 8])\r |
| | 50 | #define SekSr CycloneGetSr(&PicoCpuCM68k)\r |
| | 51 | #define SekSetStop(x) { PicoCpuCM68k.state_flags&=~1; if (x) { PicoCpuCM68k.state_flags|=1; PicoCpuCM68k.cycles=0; } }\r |
| | 52 | #define SekSetStopS68k(x) { PicoCpuCS68k.state_flags&=~1; if (x) { PicoCpuCS68k.state_flags|=1; PicoCpuCS68k.cycles=0; } }\r |
| | 53 | #define SekIsStoppedM68k() (PicoCpuCM68k.state_flags&1)\r |
| | 54 | #define SekIsStoppedS68k() (PicoCpuCS68k.state_flags&1)\r |
| | 55 | #define SekShouldInterrupt (PicoCpuCM68k.irq > (PicoCpuCM68k.srh&7))\r |
| | 56 | \r |
| | 57 | #define SekInterrupt(i) PicoCpuCM68k.irq=i\r |
| | 58 | #define SekIrqLevel PicoCpuCM68k.irq\r |
| | 59 | \r |
| | 60 | #ifdef EMU_M68K\r |
| | 61 | #define EMU_CORE_DEBUG\r |
| | 62 | #endif\r |
| | 63 | #endif\r |
| | 64 | \r |
| | 65 | #ifdef EMU_F68K\r |
| | 66 | #include "../cpu/fame/fame.h"\r |
| | 67 | extern M68K_CONTEXT PicoCpuFM68k, PicoCpuFS68k;\r |
| | 68 | #define SekCyclesLeftNoMCD PicoCpuFM68k.io_cycle_counter\r |
| | 69 | #define SekCyclesLeft \\r |
| | 70 | (((PicoAHW&1) && (PicoOpt & POPT_EN_MCD_PSYNC)) ? (SekCycleAim-SekCycleCnt) : SekCyclesLeftNoMCD)\r |
| | 71 | #define SekCyclesLeftS68k \\r |
| | 72 | ((PicoOpt & POPT_EN_MCD_PSYNC) ? (SekCycleAimS68k-SekCycleCntS68k) : PicoCpuFS68k.io_cycle_counter)\r |
| | 73 | #define SekEndTimeslice(after) PicoCpuFM68k.io_cycle_counter=after\r |
| | 74 | #define SekEndTimesliceS68k(after) PicoCpuFS68k.io_cycle_counter=after\r |
| | 75 | #define SekPc fm68k_get_pc(&PicoCpuFM68k)\r |
| | 76 | #define SekPcS68k fm68k_get_pc(&PicoCpuFS68k)\r |
| | 77 | #define SekDar(x) (x < 8 ? PicoCpuFM68k.dreg[x].D : PicoCpuFM68k.areg[x - 8].D)\r |
| | 78 | #define SekSr PicoCpuFM68k.sr\r |
| | 79 | #define SekSetStop(x) { \\r |
| | 80 | PicoCpuFM68k.execinfo &= ~FM68K_HALTED; \\r |
| | 81 | if (x) { PicoCpuFM68k.execinfo |= FM68K_HALTED; PicoCpuFM68k.io_cycle_counter = 0; } \\r |
| | 82 | }\r |
| | 83 | #define SekSetStopS68k(x) { \\r |
| | 84 | PicoCpuFS68k.execinfo &= ~FM68K_HALTED; \\r |
| | 85 | if (x) { PicoCpuFS68k.execinfo |= FM68K_HALTED; PicoCpuFS68k.io_cycle_counter = 0; } \\r |
| | 86 | }\r |
| | 87 | #define SekIsStoppedM68k() (PicoCpuFM68k.execinfo&FM68K_HALTED)\r |
| | 88 | #define SekIsStoppedS68k() (PicoCpuFS68k.execinfo&FM68K_HALTED)\r |
| | 89 | #define SekShouldInterrupt fm68k_would_interrupt()\r |
| | 90 | \r |
| | 91 | #define SekInterrupt(irq) PicoCpuFM68k.interrupts[0]=irq\r |
| | 92 | #define SekIrqLevel PicoCpuFM68k.interrupts[0]\r |
| | 93 | \r |
| | 94 | #ifdef EMU_M68K\r |
| | 95 | #define EMU_CORE_DEBUG\r |
| | 96 | #endif\r |
| | 97 | #endif\r |
| | 98 | \r |
| | 99 | #ifdef EMU_M68K\r |
| | 100 | #include "../cpu/musashi/m68kcpu.h"\r |
| | 101 | extern m68ki_cpu_core PicoCpuMM68k, PicoCpuMS68k;\r |
| | 102 | #ifndef SekCyclesLeft\r |
| | 103 | #define SekCyclesLeftNoMCD PicoCpuMM68k.cyc_remaining_cycles\r |
| | 104 | #define SekCyclesLeft \\r |
| | 105 | (((PicoAHW&1) && (PicoOpt & POPT_EN_MCD_PSYNC)) ? (SekCycleAim-SekCycleCnt) : SekCyclesLeftNoMCD)\r |
| | 106 | #define SekCyclesLeftS68k \\r |
| | 107 | ((PicoOpt & POPT_EN_MCD_PSYNC) ? (SekCycleAimS68k-SekCycleCntS68k) : PicoCpuMS68k.cyc_remaining_cycles)\r |
| | 108 | #define SekEndTimeslice(after) SET_CYCLES(after)\r |
| | 109 | #define SekEndTimesliceS68k(after) PicoCpuMS68k.cyc_remaining_cycles=after\r |
| | 110 | #define SekPc m68k_get_reg(&PicoCpuMM68k, M68K_REG_PC)\r |
| | 111 | #define SekPcS68k m68k_get_reg(&PicoCpuMS68k, M68K_REG_PC)\r |
| | 112 | #define SekDar(x) PicoCpuMM68k.dar[x]\r |
| | 113 | #define SekSr m68k_get_reg(&PicoCpuMM68k, M68K_REG_SR)\r |
| | 114 | #define SekSetStop(x) { \\r |
| | 115 | if(x) { SET_CYCLES(0); PicoCpuMM68k.stopped=STOP_LEVEL_STOP; } \\r |
| | 116 | else PicoCpuMM68k.stopped=0; \\r |
| | 117 | }\r |
| | 118 | #define SekSetStopS68k(x) { \\r |
| | 119 | if(x) { SET_CYCLES(0); PicoCpuMS68k.stopped=STOP_LEVEL_STOP; } \\r |
| | 120 | else PicoCpuMS68k.stopped=0; \\r |
| | 121 | }\r |
| | 122 | #define SekIsStoppedM68k() (PicoCpuMM68k.stopped==STOP_LEVEL_STOP)\r |
| | 123 | #define SekIsStoppedS68k() (PicoCpuMS68k.stopped==STOP_LEVEL_STOP)\r |
| | 124 | #define SekShouldInterrupt (CPU_INT_LEVEL > FLAG_INT_MASK)\r |
| | 125 | \r |
| | 126 | #define SekInterrupt(irq) { \\r |
| | 127 | void *oldcontext = m68ki_cpu_p; \\r |
| | 128 | m68k_set_context(&PicoCpuMM68k); \\r |
| | 129 | m68k_set_irq(irq); \\r |
| | 130 | m68k_set_context(oldcontext); \\r |
| | 131 | }\r |
| | 132 | #define SekIrqLevel (PicoCpuMM68k.int_level >> 8)\r |
| | 133 | \r |
| | 134 | #endif\r |
| | 135 | #endif // EMU_M68K\r |
| | 136 | \r |
| | 137 | extern int SekCycleCnt; // cycles done in this frame\r |
| | 138 | extern int SekCycleAim; // cycle aim\r |
| | 139 | extern unsigned int SekCycleCntT; // total cycle counter, updated once per frame\r |
| | 140 | \r |
| | 141 | #define SekCyclesReset() { \\r |
| | 142 | SekCycleCntT+=SekCycleAim; \\r |
| | 143 | SekCycleCnt-=SekCycleAim; \\r |
| | 144 | SekCycleAim=0; \\r |
| | 145 | }\r |
| | 146 | #define SekCyclesBurn(c) SekCycleCnt+=c\r |
| | 147 | #define SekCyclesDone() (SekCycleAim-SekCyclesLeft) // number of cycles done in this frame (can be checked anywhere)\r |
| | 148 | #define SekCyclesDoneT() (SekCycleCntT+SekCyclesDone()) // total nuber of cycles done for this rom\r |
| | 149 | #define SekCyclesDoneT2() (SekCycleCntT + SekCycleCnt) // same as above but not from memhandlers\r |
| | 150 | \r |
| | 151 | #define SekEndRun(after) { \\r |
| | 152 | SekCycleCnt -= SekCyclesLeft - (after); \\r |
| | 153 | if (SekCycleCnt < 0) SekCycleCnt = 0; \\r |
| | 154 | SekEndTimeslice(after); \\r |
| | 155 | }\r |
| | 156 | \r |
| | 157 | #define SekEndRunS68k(after) { \\r |
| | 158 | SekCycleCntS68k -= SekCyclesLeftS68k - (after); \\r |
| | 159 | if (SekCycleCntS68k < 0) SekCycleCntS68k = 0; \\r |
| | 160 | SekEndTimesliceS68k(after); \\r |
| | 161 | }\r |
| | 162 | \r |
| | 163 | extern int SekCycleCntS68k;\r |
| | 164 | extern int SekCycleAimS68k;\r |
| | 165 | \r |
| | 166 | #define SekCyclesResetS68k() { \\r |
| | 167 | SekCycleCntS68k-=SekCycleAimS68k; \\r |
| | 168 | SekCycleAimS68k=0; \\r |
| | 169 | }\r |
| | 170 | #define SekCyclesDoneS68k() (SekCycleAimS68k-SekCyclesLeftS68k)\r |
| | 171 | \r |
| | 172 | #ifdef EMU_CORE_DEBUG\r |
| | 173 | extern int dbg_irq_level;\r |
| | 174 | #undef SekEndTimeslice\r |
| | 175 | #undef SekCyclesBurn\r |
| | 176 | #undef SekEndRun\r |
| | 177 | #undef SekInterrupt\r |
| | 178 | #define SekEndTimeslice(c)\r |
| | 179 | #define SekCyclesBurn(c) c\r |
| | 180 | #define SekEndRun(c)\r |
| | 181 | #define SekInterrupt(irq) dbg_irq_level=irq\r |
| | 182 | #endif\r |
| | 183 | \r |
| | 184 | // ----------------------- Z80 CPU -----------------------\r |
| | 185 | \r |
| | 186 | #if defined(_USE_DRZ80)\r |
| | 187 | #include "../cpu/DrZ80/drz80.h"\r |
| | 188 | \r |
| | 189 | extern struct DrZ80 drZ80;\r |
| | 190 | \r |
| | 191 | #define z80_run(cycles) ((cycles) - DrZ80Run(&drZ80, cycles))\r |
| | 192 | #define z80_run_nr(cycles) DrZ80Run(&drZ80, cycles)\r |
| | 193 | #define z80_int() drZ80.Z80_IRQ = 1\r |
| | 194 | \r |
| | 195 | #define z80_cyclesLeft drZ80.cycles\r |
| | 196 | #define z80_pc() (drZ80.Z80PC - drZ80.Z80PC_BASE)\r |
| | 197 | \r |
| | 198 | #elif defined(_USE_CZ80)\r |
| | 199 | #include "../cpu/cz80/cz80.h"\r |
| | 200 | \r |
| | 201 | #define z80_run(cycles) Cz80_Exec(&CZ80, cycles)\r |
| | 202 | #define z80_run_nr(cycles) Cz80_Exec(&CZ80, cycles)\r |
| | 203 | #define z80_int() Cz80_Set_IRQ(&CZ80, 0, HOLD_LINE)\r |
| | 204 | \r |
| | 205 | #define z80_cyclesLeft (CZ80.ICount - CZ80.ExtraCycles)\r |
| | 206 | #define z80_pc() Cz80_Get_Reg(&CZ80, CZ80_PC)\r |
| | 207 | \r |
| | 208 | #else\r |
| | 209 | \r |
| | 210 | #define z80_run(cycles) (cycles)\r |
| | 211 | #define z80_run_nr(cycles)\r |
| | 212 | #define z80_int()\r |
| | 213 | \r |
| | 214 | #endif\r |
| | 215 | \r |
| | 216 | #define Z80_STATE_SIZE 0x60\r |
| | 217 | \r |
| | 218 | extern int z80stopCycle; /* in 68k cycles */\r |
| | 219 | extern int z80_cycle_cnt; /* 'done' z80 cycles before z80_run() */\r |
| | 220 | extern int z80_cycle_aim;\r |
| | 221 | extern int z80_scanline;\r |
| | 222 | extern int z80_scanline_cycles; /* cycles done until z80_scanline */\r |
| | 223 | \r |
| | 224 | #define z80_resetCycles() \\r |
| | 225 | z80_cycle_cnt = z80_cycle_aim = z80_scanline = z80_scanline_cycles = 0;\r |
| | 226 | \r |
| | 227 | #define z80_cyclesDone() \\r |
| | 228 | (z80_cycle_aim - z80_cyclesLeft)\r |
| | 229 | \r |
| | 230 | #define cycles_68k_to_z80(x) ((x)*957 >> 11)\r |
| | 231 | \r |
| | 232 | // ----------------------- SH2 CPU -----------------------\r |
| | 233 | \r |
| | 234 | #include "cpu/sh2/sh2.h"\r |
| | 235 | \r |
| | 236 | extern SH2 sh2s[2];\r |
| | 237 | #define msh2 sh2s[0]\r |
| | 238 | #define ssh2 sh2s[1]\r |
| | 239 | \r |
| | 240 | #ifndef DRC_SH2\r |
| | 241 | # define sh2_end_run(sh2, after_) do { \\r |
| | 242 | if ((sh2)->icount > (after_)) { \\r |
| | 243 | (sh2)->cycles_timeslice -= (sh2)->icount; \\r |
| | 244 | (sh2)->icount = after_; \\r |
| | 245 | } \\r |
| | 246 | } while (0)\r |
| | 247 | # define sh2_cycles_left(sh2) (sh2)->icount\r |
| | 248 | # define sh2_pc(c) (c) ? ssh2.ppc : msh2.ppc\r |
| | 249 | #else\r |
| | 250 | # define sh2_end_run(sh2, after_) do { \\r |
| | 251 | int left_ = (signed int)(sh2)->sr >> 12; \\r |
| | 252 | if (left_ > (after_)) { \\r |
| | 253 | (sh2)->cycles_timeslice -= left_; \\r |
| | 254 | (sh2)->sr &= 0xfff; \\r |
| | 255 | (sh2)->sr |= (after_) << 12; \\r |
| | 256 | } \\r |
| | 257 | } while (0)\r |
| | 258 | # define sh2_cycles_left(sh2) ((signed int)(sh2)->sr >> 12)\r |
| | 259 | # define sh2_pc(c) (c) ? ssh2.pc : msh2.pc\r |
| | 260 | #endif\r |
| | 261 | \r |
| | 262 | #define sh2_cycles_done(sh2) ((int)(sh2)->cycles_timeslice - sh2_cycles_left(sh2))\r |
| | 263 | #define sh2_cycles_done_t(sh2) \\r |
| | 264 | ((sh2)->m68krcycles_done * 3 + sh2_cycles_done(sh2))\r |
| | 265 | #define sh2_cycles_done_m68k(sh2) \\r |
| | 266 | ((sh2)->m68krcycles_done + (sh2_cycles_done(sh2) / 3))\r |
| | 267 | \r |
| | 268 | #define sh2_reg(c, x) (c) ? ssh2.r[x] : msh2.r[x]\r |
| | 269 | #define sh2_gbr(c) (c) ? ssh2.gbr : msh2.gbr\r |
| | 270 | #define sh2_vbr(c) (c) ? ssh2.vbr : msh2.vbr\r |
| | 271 | #define sh2_sr(c) (((c) ? ssh2.sr : msh2.sr) & 0xfff)\r |
| | 272 | \r |
| | 273 | #define sh2_set_gbr(c, v) \\r |
| | 274 | { if (c) ssh2.gbr = v; else msh2.gbr = v; }\r |
| | 275 | #define sh2_set_vbr(c, v) \\r |
| | 276 | { if (c) ssh2.vbr = v; else msh2.vbr = v; }\r |
| | 277 | \r |
| | 278 | // ---------------------------------------------------------\r |
| | 279 | \r |
| | 280 | // main oscillator clock which controls timing\r |
| | 281 | #define OSC_NTSC 53693100\r |
| | 282 | #define OSC_PAL 53203424\r |
| | 283 | \r |
| | 284 | struct PicoVideo\r |
| | 285 | {\r |
| | 286 | unsigned char reg[0x20];\r |
| | 287 | unsigned int command; // 32-bit Command\r |
| | 288 | unsigned char pending; // 1 if waiting for second half of 32-bit command\r |
| | 289 | unsigned char type; // Command type (v/c/vsram read/write)\r |
| | 290 | unsigned short addr; // Read/Write address\r |
| | 291 | int status; // Status bits\r |
| | 292 | unsigned char pending_ints; // pending interrupts: ??VH????\r |
| | 293 | signed char lwrite_cnt; // VDP write count during active display line\r |
| | 294 | unsigned short v_counter; // V-counter\r |
| | 295 | unsigned char pad[0x10];\r |
| | 296 | };\r |
| | 297 | \r |
| | 298 | struct PicoMisc\r |
| | 299 | {\r |
| | 300 | unsigned char rotate;\r |
| | 301 | unsigned char z80Run;\r |
| | 302 | unsigned char padTHPhase[2]; // 02 phase of gamepad TH switches\r |
| | 303 | unsigned short scanline; // 04 0 to 261||311\r |
| | 304 | char dirtyPal; // 06 Is the palette dirty (1 - change @ this frame, 2 - some time before)\r |
| | 305 | unsigned char hardware; // 07 Hardware value for country\r |
| | 306 | unsigned char pal; // 08 1=PAL 0=NTSC\r |
| | 307 | unsigned char sram_reg; // 09 SRAM reg. See SRR_* below\r |
| | 308 | unsigned short z80_bank68k; // 0a\r |
| | 309 | unsigned short pad0;\r |
| | 310 | unsigned char pad1;\r |
| | 311 | unsigned char z80_reset; // 0f z80 reset held\r |
| | 312 | unsigned char padDelay[2]; // 10 gamepad phase time outs, so we count a delay\r |
| | 313 | unsigned short eeprom_addr; // EEPROM address register\r |
| | 314 | unsigned char eeprom_cycle; // EEPROM cycle number\r |
| | 315 | unsigned char eeprom_slave; // EEPROM slave word for X24C02 and better SRAMs\r |
| | 316 | unsigned char eeprom_status;\r |
| | 317 | unsigned char pad2;\r |
| | 318 | unsigned short dma_xfers; // 18\r |
| | 319 | unsigned char eeprom_wb[2]; // EEPROM latch/write buffer\r |
| | 320 | unsigned int frame_count; // 1c for movies and idle det\r |
| | 321 | };\r |
| | 322 | \r |
| | 323 | struct PicoMS\r |
| | 324 | {\r |
| | 325 | unsigned char carthw[0x10];\r |
| | 326 | unsigned char io_ctl;\r |
| | 327 | unsigned char pad[0x4f];\r |
| | 328 | };\r |
| | 329 | \r |
| | 330 | // some assembly stuff depend on these, do not touch!\r |
| | 331 | struct Pico\r |
| | 332 | {\r |
| | 333 | unsigned char ram[0x10000]; // 0x00000 scratch ram\r |
| | 334 | union { // vram is byteswapped for easier reads when drawing\r |
| | 335 | unsigned short vram[0x8000]; // 0x10000\r |
| | 336 | unsigned char vramb[0x4000]; // VRAM in SMS mode\r |
| | 337 | };\r |
| | 338 | unsigned char zram[0x2000]; // 0x20000 Z80 ram\r |
| | 339 | unsigned char ioports[0x10]; // XXX: fix asm and mv\r |
| | 340 | unsigned char pad[0xf0]; // unused\r |
| | 341 | unsigned short cram[0x40]; // 0x22100\r |
| | 342 | unsigned short vsram[0x40]; // 0x22180\r |
| | 343 | \r |
| | 344 | unsigned char *rom; // 0x22200\r |
| | 345 | unsigned int romsize; // 0x22204\r |
| | 346 | \r |
| | 347 | struct PicoMisc m;\r |
| | 348 | struct PicoVideo video;\r |
| | 349 | struct PicoMS ms;\r |
| | 350 | };\r |
| | 351 | \r |
| | 352 | // sram\r |
| | 353 | #define SRR_MAPPED (1 << 0)\r |
| | 354 | #define SRR_READONLY (1 << 1)\r |
| | 355 | \r |
| | 356 | #define SRF_ENABLED (1 << 0)\r |
| | 357 | #define SRF_EEPROM (1 << 1)\r |
| | 358 | \r |
| | 359 | struct PicoSRAM\r |
| | 360 | {\r |
| | 361 | unsigned char *data; // actual data\r |
| | 362 | unsigned int start; // start address in 68k address space\r |
| | 363 | unsigned int end;\r |
| | 364 | unsigned char flags; // 0c: SRF_*\r |
| | 365 | unsigned char unused2;\r |
| | 366 | unsigned char changed;\r |
| | 367 | unsigned char eeprom_type; // eeprom type: 0: 7bit (24C01), 2: 2 addr words (X24C02+), 3: 3 addr words\r |
| | 368 | unsigned char unused3;\r |
| | 369 | unsigned char eeprom_bit_cl; // bit number for cl\r |
| | 370 | unsigned char eeprom_bit_in; // bit number for in\r |
| | 371 | unsigned char eeprom_bit_out; // bit number for out\r |
| | 372 | unsigned int size;\r |
| | 373 | };\r |
| | 374 | \r |
| | 375 | // MCD\r |
| | 376 | #include "cd/cd_sys.h"\r |
| | 377 | #include "cd/LC89510.h"\r |
| | 378 | #include "cd/gfx_cd.h"\r |
| | 379 | \r |
| | 380 | struct mcd_pcm\r |
| | 381 | {\r |
| | 382 | unsigned char control; // reg7\r |
| | 383 | unsigned char enabled; // reg8\r |
| | 384 | unsigned char cur_ch;\r |
| | 385 | unsigned char bank;\r |
| | 386 | int pad1;\r |
| | 387 | \r |
| | 388 | struct pcm_chan // 08, size 0x10\r |
| | 389 | {\r |
| | 390 | unsigned char regs[8];\r |
| | 391 | unsigned int addr; // .08: played sample address\r |
| | 392 | int pad;\r |
| | 393 | } ch[8];\r |
| | 394 | };\r |
| | 395 | \r |
| | 396 | struct mcd_misc\r |
| | 397 | {\r |
| | 398 | unsigned short hint_vector;\r |
| | 399 | unsigned char busreq;\r |
| | 400 | unsigned char s68k_pend_ints;\r |
| | 401 | unsigned int state_flags; // 04: emu state: reset_pending\r |
| | 402 | unsigned int counter75hz;\r |
| | 403 | unsigned int pad0;\r |
| | 404 | int timer_int3; // 10\r |
| | 405 | unsigned int timer_stopwatch;\r |
| | 406 | unsigned char bcram_reg; // 18: battery-backed RAM cart register\r |
| | 407 | unsigned char pad2;\r |
| | 408 | unsigned short pad3;\r |
| | 409 | int pad[9];\r |
| | 410 | };\r |
| | 411 | \r |
| | 412 | typedef struct\r |
| | 413 | {\r |
| | 414 | unsigned char bios[0x20000]; // 000000: 128K\r |
| | 415 | union { // 020000: 512K\r |
| | 416 | unsigned char prg_ram[0x80000];\r |
| | 417 | unsigned char prg_ram_b[4][0x20000];\r |
| | 418 | };\r |
| | 419 | union { // 0a0000: 256K\r |
| | 420 | struct {\r |
| | 421 | unsigned char word_ram2M[0x40000];\r |
| | 422 | unsigned char unused0[0x20000];\r |
| | 423 | };\r |
| | 424 | struct {\r |
| | 425 | unsigned char unused1[0x20000];\r |
| | 426 | unsigned char word_ram1M[2][0x20000];\r |
| | 427 | };\r |
| | 428 | };\r |
| | 429 | union { // 100000: 64K\r |
| | 430 | unsigned char pcm_ram[0x10000];\r |
| | 431 | unsigned char pcm_ram_b[0x10][0x1000];\r |
| | 432 | };\r |
| | 433 | unsigned char s68k_regs[0x200]; // 110000: GA, not CPU regs\r |
| | 434 | unsigned char bram[0x2000]; // 110200: 8K\r |
| | 435 | struct mcd_misc m; // 112200: misc\r |
| | 436 | struct mcd_pcm pcm; // 112240:\r |
| | 437 | _scd_toc TOC; // not to be saved\r |
| | 438 | CDD cdd;\r |
| | 439 | CDC cdc;\r |
| | 440 | _scd scd;\r |
| | 441 | Rot_Comp rot_comp;\r |
| | 442 | } mcd_state;\r |
| | 443 | \r |
| | 444 | // XXX: this will need to be reworked for cart+cd support.\r |
| | 445 | #define Pico_mcd ((mcd_state *)Pico.rom)\r |
| | 446 | \r |
| | 447 | // 32X\r |
| | 448 | #define P32XS_FM (1<<15)\r |
| | 449 | #define P32XS_REN (1<< 7)\r |
| | 450 | #define P32XS_nRES (1<< 1)\r |
| | 451 | #define P32XS_ADEN (1<< 0)\r |
| | 452 | #define P32XS2_ADEN (1<< 9)\r |
| | 453 | #define P32XS_FULL (1<< 7) // DREQ FIFO full\r |
| | 454 | #define P32XS_68S (1<< 2)\r |
| | 455 | #define P32XS_DMA (1<< 1)\r |
| | 456 | #define P32XS_RV (1<< 0)\r |
| | 457 | \r |
| | 458 | #define P32XV_nPAL (1<<15) // VDP\r |
| | 459 | #define P32XV_PRI (1<< 7)\r |
| | 460 | #define P32XV_Mx (3<< 0) // display mode mask\r |
| | 461 | \r |
| | 462 | #define P32XV_SFT (1<< 0)\r |
| | 463 | \r |
| | 464 | #define P32XV_VBLK (1<<15)\r |
| | 465 | #define P32XV_HBLK (1<<14)\r |
| | 466 | #define P32XV_PEN (1<<13)\r |
| | 467 | #define P32XV_nFEN (1<< 1)\r |
| | 468 | #define P32XV_FS (1<< 0)\r |
| | 469 | \r |
| | 470 | #define P32XP_RTP (1<<7) // PWM control\r |
| | 471 | #define P32XP_FULL (1<<15) // PWM pulse\r |
| | 472 | #define P32XP_EMPTY (1<<14)\r |
| | 473 | \r |
| | 474 | #define P32XF_68KCPOLL (1 << 0)\r |
| | 475 | #define P32XF_68KVPOLL (1 << 1)\r |
| | 476 | \r |
| | 477 | #define P32XI_VRES (1 << 14/2) // IRL/2\r |
| | 478 | #define P32XI_VINT (1 << 12/2)\r |
| | 479 | #define P32XI_HINT (1 << 10/2)\r |
| | 480 | #define P32XI_CMD (1 << 8/2)\r |
| | 481 | #define P32XI_PWM (1 << 6/2)\r |
| | 482 | \r |
| | 483 | // peripheral reg access\r |
| | 484 | #define PREG8(regs,offs) ((unsigned char *)regs)[offs ^ 3]\r |
| | 485 | \r |
| | 486 | // real one is 4*2, but we use more because we don't lockstep\r |
| | 487 | #define DMAC_FIFO_LEN (4*4)\r |
| | 488 | #define PWM_BUFF_LEN 1024 // in one channel samples\r |
| | 489 | \r |
| | 490 | #define SH2_DRCBLK_RAM_SHIFT 1\r |
| | 491 | #define SH2_DRCBLK_DA_SHIFT 1\r |
| | 492 | \r |
| | 493 | #define SH2_WRITE_SHIFT 25\r |
| | 494 | \r |
| | 495 | struct Pico32x\r |
| | 496 | {\r |
| | 497 | unsigned short regs[0x20];\r |
| | 498 | unsigned short vdp_regs[0x10]; // 0x40\r |
| | 499 | unsigned short sh2_regs[3]; // 0x60\r |
| | 500 | unsigned char pending_fb;\r |
| | 501 | unsigned char dirty_pal;\r |
| | 502 | unsigned int emu_flags;\r |
| | 503 | unsigned char sh2irq_mask[2];\r |
| | 504 | unsigned char sh2irqi[2]; // individual\r |
| | 505 | unsigned int sh2irqs; // common irqs\r |
| | 506 | unsigned short dmac_fifo[DMAC_FIFO_LEN];\r |
| | 507 | unsigned int dmac0_fifo_ptr;\r |
| | 508 | unsigned int pad;\r |
| | 509 | unsigned char comm_dirty_68k;\r |
| | 510 | unsigned char comm_dirty_sh2;\r |
| | 511 | unsigned char pwm_irq_cnt;\r |
| | 512 | unsigned char pad1;\r |
| | 513 | unsigned short pwm_p[2]; // pwm pos in fifo\r |
| | 514 | unsigned int pwm_cycle_p; // pwm play cursor (32x cycles)\r |
| | 515 | unsigned int reserved[6];\r |
| | 516 | };\r |
| | 517 | \r |
| | 518 | struct Pico32xMem\r |
| | 519 | {\r |
| | 520 | unsigned char sdram[0x40000];\r |
| | 521 | #ifdef DRC_SH2\r |
| | 522 | unsigned short drcblk_ram[1 << (18 - SH2_DRCBLK_RAM_SHIFT)];\r |
| | 523 | #endif\r |
| | 524 | unsigned short dram[2][0x20000/2]; // AKA fb\r |
| | 525 | union {\r |
| | 526 | unsigned char m68k_rom[0x100];\r |
| | 527 | unsigned char m68k_rom_bank[0x10000]; // M68K_BANK_SIZE\r |
| | 528 | };\r |
| | 529 | unsigned char data_array[2][0x1000]; // cache in SH2s (can be used as RAM)\r |
| | 530 | #ifdef DRC_SH2\r |
| | 531 | unsigned short drcblk_da[2][1 << (12 - SH2_DRCBLK_DA_SHIFT)];\r |
| | 532 | #endif\r |
| | 533 | unsigned char sh2_rom_m[0x800];\r |
| | 534 | unsigned char sh2_rom_s[0x400];\r |
| | 535 | unsigned short pal[0x100];\r |
| | 536 | unsigned short pal_native[0x100]; // converted to native (for renderer)\r |
| | 537 | unsigned int sh2_peri_regs[2][0x200/4]; // periphereal regs of SH2s\r |
| | 538 | signed short pwm[2*PWM_BUFF_LEN]; // PWM buffer for current frame\r |
| | 539 | signed short pwm_fifo[2][4]; // [0] - current, others - fifo entries\r |
| | 540 | };\r |
| | 541 | \r |
| | 542 | // area.c\r |
| | 543 | extern void (*PicoLoadStateHook)(void);\r |
| | 544 | \r |
| | 545 | typedef struct {\r |
| | 546 | int chunk;\r |
| | 547 | int size;\r |
| | 548 | void *ptr;\r |
| | 549 | } carthw_state_chunk;\r |
| | 550 | extern carthw_state_chunk *carthw_chunks;\r |
| | 551 | #define CHUNK_CARTHW 64\r |
| | 552 | \r |
| | 553 | // cart.c\r |
| | 554 | extern int PicoCartResize(int newsize);\r |
| | 555 | extern void Byteswap(void *dst, const void *src, int len);\r |
| | 556 | extern void (*PicoCartMemSetup)(void);\r |
| | 557 | extern void (*PicoCartUnloadHook)(void);\r |
| | 558 | \r |
| | 559 | // debug.c\r |
| | 560 | int CM_compareRun(int cyc, int is_sub);\r |
| | 561 | \r |
| | 562 | // draw.c\r |
| | 563 | PICO_INTERNAL void PicoFrameStart(void);\r |
| | 564 | void PicoDrawSync(int to, int blank_last_line);\r |
| | 565 | void BackFill(int reg7, int sh);\r |
| | 566 | void FinalizeLine555(int sh, int line);\r |
| | 567 | extern int (*PicoScanBegin)(unsigned int num);\r |
| | 568 | extern int (*PicoScanEnd)(unsigned int num);\r |
| | 569 | extern int DrawScanline;\r |
| | 570 | #define MAX_LINE_SPRITES 29\r |
| | 571 | extern unsigned char HighLnSpr[240][3 + MAX_LINE_SPRITES];\r |
| | 572 | extern void *DrawLineDestBase;\r |
| | 573 | extern int DrawLineDestIncrement;\r |
| | 574 | \r |
| | 575 | // draw2.c\r |
| | 576 | PICO_INTERNAL void PicoFrameFull();\r |
| | 577 | \r |
| | 578 | // mode4.c\r |
| | 579 | void PicoFrameStartMode4(void);\r |
| | 580 | void PicoLineMode4(int line);\r |
| | 581 | void PicoDoHighPal555M4(void);\r |
| | 582 | void PicoDrawSetOutputMode4(pdso_t which);\r |
| | 583 | \r |
| | 584 | // memory.c\r |
| | 585 | PICO_INTERNAL void PicoMemSetup(void);\r |
| | 586 | unsigned int PicoRead8_io(unsigned int a);\r |
| | 587 | unsigned int PicoRead16_io(unsigned int a);\r |
| | 588 | void PicoWrite8_io(unsigned int a, unsigned int d);\r |
| | 589 | void PicoWrite16_io(unsigned int a, unsigned int d);\r |
| | 590 | void p32x_dreq1_trigger(void);\r |
| | 591 | \r |
| | 592 | // pico/memory.c\r |
| | 593 | PICO_INTERNAL void PicoMemSetupPico(void);\r |
| | 594 | \r |
| | 595 | // cd/memory.c\r |
| | 596 | PICO_INTERNAL void PicoMemSetupCD(void);\r |
| | 597 | void PicoMemStateLoaded(void);\r |
| | 598 | \r |
| | 599 | // pico.c\r |
| | 600 | extern struct Pico Pico;\r |
| | 601 | extern struct PicoSRAM SRam;\r |
| | 602 | extern int PicoPadInt[2];\r |
| | 603 | extern int emustatus;\r |
| | 604 | extern int scanlines_total;\r |
| | 605 | extern void (*PicoResetHook)(void);\r |
| | 606 | extern void (*PicoLineHook)(void);\r |
| | 607 | PICO_INTERNAL int CheckDMA(void);\r |
| | 608 | PICO_INTERNAL void PicoDetectRegion(void);\r |
| | 609 | PICO_INTERNAL void PicoSyncZ80(int m68k_cycles_done);\r |
| | 610 | \r |
| | 611 | // cd/pico.c\r |
| | 612 | PICO_INTERNAL void PicoInitMCD(void);\r |
| | 613 | PICO_INTERNAL void PicoExitMCD(void);\r |
| | 614 | PICO_INTERNAL void PicoPowerMCD(void);\r |
| | 615 | PICO_INTERNAL int PicoResetMCD(void);\r |
| | 616 | PICO_INTERNAL void PicoFrameMCD(void);\r |
| | 617 | \r |
| | 618 | // pico/pico.c\r |
| | 619 | PICO_INTERNAL void PicoInitPico(void);\r |
| | 620 | PICO_INTERNAL void PicoReratePico(void);\r |
| | 621 | \r |
| | 622 | // pico/xpcm.c\r |
| | 623 | PICO_INTERNAL void PicoPicoPCMUpdate(short *buffer, int length, int stereo);\r |
| | 624 | PICO_INTERNAL void PicoPicoPCMReset(void);\r |
| | 625 | PICO_INTERNAL void PicoPicoPCMRerate(int xpcm_rate);\r |
| | 626 | \r |
| | 627 | // sek.c\r |
| | 628 | PICO_INTERNAL void SekInit(void);\r |
| | 629 | PICO_INTERNAL int SekReset(void);\r |
| | 630 | PICO_INTERNAL void SekState(int *data);\r |
| | 631 | PICO_INTERNAL void SekSetRealTAS(int use_real);\r |
| | 632 | PICO_INTERNAL void SekPackCpu(unsigned char *cpu, int is_sub);\r |
| | 633 | PICO_INTERNAL void SekUnpackCpu(const unsigned char *cpu, int is_sub);\r |
| | 634 | void SekStepM68k(void);\r |
| | 635 | void SekInitIdleDet(void);\r |
| | 636 | void SekFinishIdleDet(void);\r |
| | 637 | \r |
| | 638 | // cd/sek.c\r |
| | 639 | PICO_INTERNAL void SekInitS68k(void);\r |
| | 640 | PICO_INTERNAL int SekResetS68k(void);\r |
| | 641 | PICO_INTERNAL int SekInterruptS68k(int irq);\r |
| | 642 | \r |
| | 643 | // sound/sound.c\r |
| | 644 | PICO_INTERNAL void cdda_start_play();\r |
| | 645 | extern short cdda_out_buffer[2*1152];\r |
| | 646 | extern int PsndLen_exc_cnt;\r |
| | 647 | extern int PsndLen_exc_add;\r |
| | 648 | extern int timer_a_next_oflow, timer_a_step; // in z80 cycles\r |
| | 649 | extern int timer_b_next_oflow, timer_b_step;\r |
| | 650 | \r |
| | 651 | void ym2612_sync_timers(int z80_cycles, int mode_old, int mode_new);\r |
| | 652 | void ym2612_pack_state(void);\r |
| | 653 | void ym2612_unpack_state(void);\r |
| | 654 | \r |
| | 655 | #define TIMER_NO_OFLOW 0x70000000\r |
| | 656 | // tA = 72 * (1024 - NA) / M\r |
| | 657 | #define TIMER_A_TICK_ZCYCLES 17203\r |
| | 658 | // tB = 1152 * (256 - NA) / M\r |
| | 659 | #define TIMER_B_TICK_ZCYCLES 262800 // 275251 broken, see Dai Makaimura\r |
| | 660 | \r |
| | 661 | #define timers_cycle() \\r |
| | 662 | if (timer_a_next_oflow > 0 && timer_a_next_oflow < TIMER_NO_OFLOW) \\r |
| | 663 | timer_a_next_oflow -= Pico.m.pal ? 70938*256 : 59659*256; \\r |
| | 664 | if (timer_b_next_oflow > 0 && timer_b_next_oflow < TIMER_NO_OFLOW) \\r |
| | 665 | timer_b_next_oflow -= Pico.m.pal ? 70938*256 : 59659*256; \\r |
| | 666 | ym2612_sync_timers(0, ym2612.OPN.ST.mode, ym2612.OPN.ST.mode);\r |
| | 667 | \r |
| | 668 | #define timers_reset() \\r |
| | 669 | timer_a_next_oflow = timer_b_next_oflow = TIMER_NO_OFLOW; \\r |
| | 670 | timer_a_step = TIMER_A_TICK_ZCYCLES * 1024; \\r |
| | 671 | timer_b_step = TIMER_B_TICK_ZCYCLES * 256;\r |
| | 672 | \r |
| | 673 | \r |
| | 674 | // videoport.c\r |
| | 675 | PICO_INTERNAL_ASM void PicoVideoWrite(unsigned int a,unsigned short d);\r |
| | 676 | PICO_INTERNAL_ASM unsigned int PicoVideoRead(unsigned int a);\r |
| | 677 | PICO_INTERNAL_ASM unsigned int PicoVideoRead8(unsigned int a);\r |
| | 678 | extern int (*PicoDmaHook)(unsigned int source, int len, unsigned short **srcp, unsigned short **limitp);\r |
| | 679 | \r |
| | 680 | // misc.c\r |
| | 681 | PICO_INTERNAL_ASM void memcpy16(unsigned short *dest, unsigned short *src, int count);\r |
| | 682 | PICO_INTERNAL_ASM void memcpy16bswap(unsigned short *dest, void *src, int count);\r |
| | 683 | PICO_INTERNAL_ASM void memcpy32(int *dest, int *src, int count); // 32bit word count\r |
| | 684 | PICO_INTERNAL_ASM void memset32(int *dest, int c, int count);\r |
| | 685 | \r |
| | 686 | // eeprom.c\r |
| | 687 | void EEPROM_write8(unsigned int a, unsigned int d);\r |
| | 688 | void EEPROM_write16(unsigned int d);\r |
| | 689 | unsigned int EEPROM_read(void);\r |
| | 690 | \r |
| | 691 | // z80 functionality wrappers\r |
| | 692 | PICO_INTERNAL void z80_init(void);\r |
| | 693 | PICO_INTERNAL void z80_pack(void *data);\r |
| | 694 | PICO_INTERNAL int z80_unpack(const void *data);\r |
| | 695 | PICO_INTERNAL void z80_reset(void);\r |
| | 696 | PICO_INTERNAL void z80_exit(void);\r |
| | 697 | \r |
| | 698 | // cd/misc.c\r |
| | 699 | PICO_INTERNAL_ASM void wram_2M_to_1M(unsigned char *m);\r |
| | 700 | PICO_INTERNAL_ASM void wram_1M_to_2M(unsigned char *m);\r |
| | 701 | \r |
| | 702 | // cd/buffering.c\r |
| | 703 | PICO_INTERNAL void PicoCDBufferRead(void *dest, int lba);\r |
| | 704 | \r |
| | 705 | // sound/sound.c\r |
| | 706 | PICO_INTERNAL void PsndReset(void);\r |
| | 707 | PICO_INTERNAL void PsndDoDAC(int line_to);\r |
| | 708 | PICO_INTERNAL void PsndClear(void);\r |
| | 709 | PICO_INTERNAL void PsndGetSamples(int y);\r |
| | 710 | PICO_INTERNAL void PsndGetSamplesMS(void);\r |
| | 711 | extern int PsndDacLine;\r |
| | 712 | \r |
| | 713 | // sms.c\r |
| | 714 | #ifndef NO_SMS\r |
| | 715 | void PicoPowerMS(void);\r |
| | 716 | void PicoResetMS(void);\r |
| | 717 | void PicoMemSetupMS(void);\r |
| | 718 | void PicoStateLoadedMS(void);\r |
| | 719 | void PicoFrameMS(void);\r |
| | 720 | void PicoFrameDrawOnlyMS(void);\r |
| | 721 | #else\r |
| | 722 | #define PicoPowerMS()\r |
| | 723 | #define PicoResetMS()\r |
| | 724 | #define PicoMemSetupMS()\r |
| | 725 | #define PicoStateLoadedMS()\r |
| | 726 | #define PicoFrameMS()\r |
| | 727 | #define PicoFrameDrawOnlyMS()\r |
| | 728 | #endif\r |
| | 729 | \r |
| | 730 | // 32x/32x.c\r |
| | 731 | #ifndef NO_32X\r |
| | 732 | extern struct Pico32x Pico32x;\r |
| | 733 | enum p32x_event {\r |
| | 734 | P32X_EVENT_PWM,\r |
| | 735 | P32X_EVENT_FILLEND,\r |
| | 736 | P32X_EVENT_COUNT,\r |
| | 737 | };\r |
| | 738 | extern unsigned int event_times[P32X_EVENT_COUNT];\r |
| | 739 | \r |
| | 740 | void Pico32xInit(void);\r |
| | 741 | void PicoPower32x(void);\r |
| | 742 | void PicoReset32x(void);\r |
| | 743 | void Pico32xStartup(void);\r |
| | 744 | void PicoUnload32x(void);\r |
| | 745 | void PicoFrame32x(void);\r |
| | 746 | void Pico32xStateLoaded(int is_early);\r |
| | 747 | void p32x_sync_sh2s(unsigned int m68k_target);\r |
| | 748 | void p32x_sync_other_sh2(SH2 *sh2, unsigned int m68k_target);\r |
| | 749 | void p32x_update_irls(SH2 *active_sh2);\r |
| | 750 | void p32x_reset_sh2s(void);\r |
| | 751 | void p32x_event_schedule(unsigned int now, enum p32x_event event, int after);\r |
| | 752 | void p32x_event_schedule_sh2(SH2 *sh2, enum p32x_event event, int after);\r |
| | 753 | \r |
| | 754 | // 32x/memory.c\r |
| | 755 | struct Pico32xMem *Pico32xMem;\r |
| | 756 | unsigned int PicoRead8_32x(unsigned int a);\r |
| | 757 | unsigned int PicoRead16_32x(unsigned int a);\r |
| | 758 | void PicoWrite8_32x(unsigned int a, unsigned int d);\r |
| | 759 | void PicoWrite16_32x(unsigned int a, unsigned int d);\r |
| | 760 | void PicoMemSetup32x(void);\r |
| | 761 | void Pico32xSwapDRAM(int b);\r |
| | 762 | void Pico32xMemStateLoaded(void);\r |
| | 763 | void p32x_m68k_poll_event(unsigned int flags);\r |
| | 764 | void p32x_sh2_poll_event(SH2 *sh2, unsigned int flags, unsigned int m68k_cycles);\r |
| | 765 | \r |
| | 766 | // 32x/draw.c\r |
| | 767 | void PicoDrawSetOutFormat32x(pdso_t which, int use_32x_line_mode);\r |
| | 768 | void FinalizeLine32xRGB555(int sh, int line);\r |
| | 769 | void PicoDraw32xLayer(int offs, int lines, int mdbg);\r |
| | 770 | void PicoDraw32xLayerMdOnly(int offs, int lines);\r |
| | 771 | extern int (*PicoScan32xBegin)(unsigned int num);\r |
| | 772 | extern int (*PicoScan32xEnd)(unsigned int num);\r |
| | 773 | enum {\r |
| | 774 | PDM32X_OFF,\r |
| | 775 | PDM32X_32X_ONLY,\r |
| | 776 | PDM32X_BOTH,\r |
| | 777 | };\r |
| | 778 | extern int Pico32xDrawMode;\r |
| | 779 | \r |
| | 780 | // 32x/pwm.c\r |
| | 781 | unsigned int p32x_pwm_read16(unsigned int a, unsigned int cycles);\r |
| | 782 | void p32x_pwm_write16(unsigned int a, unsigned int d, unsigned int cycles);\r |
| | 783 | void p32x_pwm_update(int *buf32, int length, int stereo);\r |
| | 784 | void p32x_timers_do(unsigned int m68k_now, unsigned int m68k_slice);\r |
| | 785 | void p32x_timers_recalc(void);\r |
| | 786 | void p32x_pwm_schedule(unsigned int m68k_now);\r |
| | 787 | void p32x_pwm_schedule_sh2(SH2 *sh2);\r |
| | 788 | void p32x_pwm_irq_event(unsigned int m68k_now);\r |
| | 789 | void p32x_pwm_state_loaded(void);\r |
| | 790 | #else\r |
| | 791 | #define Pico32xInit()\r |
| | 792 | #define PicoPower32x()\r |
| | 793 | #define PicoReset32x()\r |
| | 794 | #define PicoFrame32x()\r |
| | 795 | #define PicoUnload32x()\r |
| | 796 | #define Pico32xStateLoaded()\r |
| | 797 | #define FinalizeLine32xRGB555 NULL\r |
| | 798 | #define p32x_pwm_update(...)\r |
| | 799 | #define p32x_timers_recalc()\r |
| | 800 | #endif\r |
| | 801 | \r |
| | 802 | /* avoid dependency on newer glibc */\r |
| | 803 | static __inline int isspace_(int c)\r |
| | 804 | {\r |
| | 805 | return (0x09 <= c && c <= 0x0d) || c == ' ';\r |
| | 806 | }\r |
| | 807 | \r |
| | 808 | #ifndef ARRAY_SIZE\r |
| | 809 | #define ARRAY_SIZE(x) (sizeof(x) / sizeof(x[0]))\r |
| | 810 | #endif\r |
| | 811 | \r |
| | 812 | // emulation event logging\r |
| | 813 | #ifndef EL_LOGMASK\r |
| | 814 | # ifdef __x86_64__ // HACK\r |
| | 815 | # define EL_LOGMASK (EL_STATUS|EL_IDLE|EL_ANOMALY)\r |
| | 816 | # else\r |
| | 817 | # define EL_LOGMASK (EL_STATUS)\r |
| | 818 | # endif\r |
| | 819 | #endif\r |
| | 820 | \r |
| | 821 | #define EL_HVCNT 0x00000001 /* hv counter reads */\r |
| | 822 | #define EL_SR 0x00000002 /* SR reads */\r |
| | 823 | #define EL_INTS 0x00000004 /* ints and acks */\r |
| | 824 | #define EL_YMTIMER 0x00000008 /* ym2612 timer stuff */\r |
| | 825 | #define EL_INTSW 0x00000010 /* log irq switching on/off */\r |
| | 826 | #define EL_ASVDP 0x00000020 /* VDP accesses during active scan */\r |
| | 827 | #define EL_VDPDMA 0x00000040 /* VDP DMA transfers and their timing */\r |
| | 828 | #define EL_BUSREQ 0x00000080 /* z80 busreq r/w or reset w */\r |
| | 829 | #define EL_Z80BNK 0x00000100 /* z80 i/o through bank area */\r |
| | 830 | #define EL_SRAMIO 0x00000200 /* sram i/o */\r |
| | 831 | #define EL_EEPROM 0x00000400 /* eeprom debug */\r |
| | 832 | #define EL_UIO 0x00000800 /* unmapped i/o */\r |
| | 833 | #define EL_IO 0x00001000 /* all i/o */\r |
| | 834 | #define EL_CDPOLL 0x00002000 /* MCD: log poll detection */\r |
| | 835 | #define EL_SVP 0x00004000 /* SVP stuff */\r |
| | 836 | #define EL_PICOHW 0x00008000 /* Pico stuff */\r |
| | 837 | #define EL_IDLE 0x00010000 /* idle loop det. */\r |
| | 838 | #define EL_CDREGS 0x00020000 /* MCD: register access */\r |
| | 839 | #define EL_CDREG3 0x00040000 /* MCD: register 3 only */\r |
| | 840 | #define EL_32X 0x00080000\r |
| | 841 | #define EL_PWM 0x00100000 /* 32X PWM stuff (LOTS of output) */\r |
| | 842 | \r |
| | 843 | #define EL_STATUS 0x40000000 /* status messages */\r |
| | 844 | #define EL_ANOMALY 0x80000000 /* some unexpected conditions (during emulation) */\r |
| | 845 | \r |
| | 846 | #if EL_LOGMASK\r |
| | 847 | #define elprintf(w,f,...) \\r |
| | 848 | do { \\r |
| | 849 | if ((w) & EL_LOGMASK) \\r |
| | 850 | lprintf("%05i:%03i: " f "\n",Pico.m.frame_count,Pico.m.scanline,##__VA_ARGS__); \\r |
| | 851 | } while (0)\r |
| | 852 | #elif defined(_MSC_VER)\r |
| | 853 | #define elprintf\r |
| | 854 | #else\r |
| | 855 | #define elprintf(w,f,...)\r |
| | 856 | #endif\r |
| | 857 | \r |
| | 858 | // profiling\r |
| | 859 | #ifdef PPROF\r |
| | 860 | #include <platform/linux/pprof.h>\r |
| | 861 | #else\r |
| | 862 | #define pprof_init()\r |
| | 863 | #define pprof_finish()\r |
| | 864 | #define pprof_start(x)\r |
| | 865 | #define pprof_end(...)\r |
| | 866 | #define pprof_end_sub(...)\r |
| | 867 | #endif\r |
| | 868 | \r |
| | 869 | #ifdef EVT_LOG\r |
| | 870 | enum evt {\r |
| | 871 | EVT_FRAME_START,\r |
| | 872 | EVT_NEXT_LINE,\r |
| | 873 | EVT_RUN_START,\r |
| | 874 | EVT_RUN_END,\r |
| | 875 | EVT_POLL_START,\r |
| | 876 | EVT_POLL_END,\r |
| | 877 | EVT_CNT\r |
| | 878 | };\r |
| | 879 | \r |
| | 880 | enum evt_cpu {\r |
| | 881 | EVT_M68K,\r |
| | 882 | EVT_S68K,\r |
| | 883 | EVT_MSH2,\r |
| | 884 | EVT_SSH2,\r |
| | 885 | EVT_CPU_CNT\r |
| | 886 | };\r |
| | 887 | \r |
| | 888 | void pevt_log(unsigned int cycles, enum evt_cpu c, enum evt e);\r |
| | 889 | void pevt_dump(void);\r |
| | 890 | \r |
| | 891 | #define pevt_log_m68k(e) \\r |
| | 892 | pevt_log(SekCyclesDoneT(), EVT_M68K, e)\r |
| | 893 | #define pevt_log_m68k_o(e) \\r |
| | 894 | pevt_log(SekCyclesDoneT2(), EVT_M68K, e)\r |
| | 895 | #define pevt_log_sh2(sh2, e) \\r |
| | 896 | pevt_log(sh2_cycles_done_m68k(sh2), EVT_MSH2 + (sh2)->is_slave, e)\r |
| | 897 | #define pevt_log_sh2_o(sh2, e) \\r |
| | 898 | pevt_log((sh2)->m68krcycles_done, EVT_MSH2 + (sh2)->is_slave, e)\r |
| | 899 | #else\r |
| | 900 | #define pevt_log(c, e)\r |
| | 901 | #define pevt_log_m68k(e)\r |
| | 902 | #define pevt_log_m68k_o(e)\r |
| | 903 | #define pevt_log_sh2(sh2, e)\r |
| | 904 | #define pevt_log_sh2_o(sh2, e)\r |
| | 905 | #define pevt_dump()\r |
| | 906 | #endif\r |
| | 907 | \r |
| | 908 | // misc\r |
| | 909 | #ifdef _MSC_VER\r |
| | 910 | #define cdprintf\r |
| | 911 | #else\r |
| | 912 | #define cdprintf(x...)\r |
| | 913 | #endif\r |
| | 914 | \r |
| | 915 | #ifdef __i386__\r |
| | 916 | #define REGPARM(x) __attribute__((regparm(x)))\r |
| | 917 | #else\r |
| | 918 | #define REGPARM(x)\r |
| | 919 | #endif\r |
| | 920 | \r |
| | 921 | #ifdef __GNUC__\r |
| | 922 | #define NOINLINE __attribute__((noinline))\r |
| | 923 | #else\r |
| | 924 | #define NOINLINE\r |
| | 925 | #endif\r |
| | 926 | \r |
| | 927 | #ifdef __cplusplus\r |
| | 928 | } // End of extern "C"\r |
| | 929 | #endif\r |
| | 930 | \r |
| | 931 | #endif // PICO_INTERNAL_INCLUDED\r |
| | 932 | \r |
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