bump libpicofe
[picodrive.git] / pico / pico_int.h
... / ...
CommitLineData
1/*\r
2 * PicoDrive - Internal Header File\r
3 * (c) Copyright Dave, 2004\r
4 * (C) notaz, 2006-2010\r
5 *\r
6 * This work is licensed under the terms of MAME license.\r
7 * See COPYING file in the top-level directory.\r
8 */\r
9\r
10#ifndef PICO_INTERNAL_INCLUDED\r
11#define PICO_INTERNAL_INCLUDED\r
12\r
13#include <stdio.h>\r
14#include <stdlib.h>\r
15#include <string.h>\r
16#include "pico.h"\r
17#include "carthw/carthw.h"\r
18\r
19//\r
20#define USE_POLL_DETECT\r
21\r
22#ifndef PICO_INTERNAL\r
23#define PICO_INTERNAL\r
24#endif\r
25#ifndef PICO_INTERNAL_ASM\r
26#define PICO_INTERNAL_ASM\r
27#endif\r
28\r
29// to select core, define EMU_C68K, EMU_M68K or EMU_F68K in your makefile or project\r
30\r
31#ifdef __cplusplus\r
32extern "C" {\r
33#endif\r
34\r
35\r
36// ----------------------- 68000 CPU -----------------------\r
37#ifdef EMU_C68K\r
38#include "../cpu/cyclone/Cyclone.h"\r
39extern struct Cyclone PicoCpuCM68k, PicoCpuCS68k;\r
40#define SekCyclesLeftNoMCD PicoCpuCM68k.cycles // cycles left for this run\r
41#define SekCyclesLeft \\r
42 (((PicoAHW&1) && (PicoOpt & POPT_EN_MCD_PSYNC)) ? (SekCycleAim-SekCycleCnt) : SekCyclesLeftNoMCD)\r
43#define SekCyclesLeftS68k \\r
44 ((PicoOpt & POPT_EN_MCD_PSYNC) ? (SekCycleAimS68k-SekCycleCntS68k) : PicoCpuCS68k.cycles)\r
45#define SekEndTimeslice(after) PicoCpuCM68k.cycles=after\r
46#define SekEndTimesliceS68k(after) PicoCpuCS68k.cycles=after\r
47#define SekPc (PicoCpuCM68k.pc-PicoCpuCM68k.membase)\r
48#define SekPcS68k (PicoCpuCS68k.pc-PicoCpuCS68k.membase)\r
49#define SekDar(x) (x < 8 ? PicoCpuCM68k.d[x] : PicoCpuCM68k.a[x - 8])\r
50#define SekDarS68k(x) (x < 8 ? PicoCpuCS68k.d[x] : PicoCpuCS68k.a[x - 8])\r
51#define SekSr CycloneGetSr(&PicoCpuCM68k)\r
52#define SekSrS68k CycloneGetSr(&PicoCpuCS68k)\r
53#define SekSetStop(x) { PicoCpuCM68k.state_flags&=~1; if (x) { PicoCpuCM68k.state_flags|=1; PicoCpuCM68k.cycles=0; } }\r
54#define SekSetStopS68k(x) { PicoCpuCS68k.state_flags&=~1; if (x) { PicoCpuCS68k.state_flags|=1; PicoCpuCS68k.cycles=0; } }\r
55#define SekIsStoppedM68k() (PicoCpuCM68k.state_flags&1)\r
56#define SekIsStoppedS68k() (PicoCpuCS68k.state_flags&1)\r
57#define SekShouldInterrupt (PicoCpuCM68k.irq > (PicoCpuCM68k.srh&7))\r
58\r
59#define SekInterrupt(i) PicoCpuCM68k.irq=i\r
60#define SekIrqLevel PicoCpuCM68k.irq\r
61\r
62#ifdef EMU_M68K\r
63#define EMU_CORE_DEBUG\r
64#endif\r
65#endif\r
66\r
67#ifdef EMU_F68K\r
68#include "../cpu/fame/fame.h"\r
69extern M68K_CONTEXT PicoCpuFM68k, PicoCpuFS68k;\r
70#define SekCyclesLeftNoMCD PicoCpuFM68k.io_cycle_counter\r
71#define SekCyclesLeft \\r
72 (((PicoAHW&1) && (PicoOpt & POPT_EN_MCD_PSYNC)) ? (SekCycleAim-SekCycleCnt) : SekCyclesLeftNoMCD)\r
73#define SekCyclesLeftS68k \\r
74 ((PicoOpt & POPT_EN_MCD_PSYNC) ? (SekCycleAimS68k-SekCycleCntS68k) : PicoCpuFS68k.io_cycle_counter)\r
75#define SekEndTimeslice(after) PicoCpuFM68k.io_cycle_counter=after\r
76#define SekEndTimesliceS68k(after) PicoCpuFS68k.io_cycle_counter=after\r
77#define SekPc fm68k_get_pc(&PicoCpuFM68k)\r
78#define SekPcS68k fm68k_get_pc(&PicoCpuFS68k)\r
79#define SekDar(x) (x < 8 ? PicoCpuFM68k.dreg[x].D : PicoCpuFM68k.areg[x - 8].D)\r
80#define SekDarS68k(x) (x < 8 ? PicoCpuFS68k.dreg[x].D : PicoCpuFS68k.areg[x - 8].D)\r
81#define SekSr PicoCpuFM68k.sr\r
82#define SekSrS68k PicoCpuFS68k.sr\r
83#define SekSetStop(x) { \\r
84 PicoCpuFM68k.execinfo &= ~FM68K_HALTED; \\r
85 if (x) { PicoCpuFM68k.execinfo |= FM68K_HALTED; PicoCpuFM68k.io_cycle_counter = 0; } \\r
86}\r
87#define SekSetStopS68k(x) { \\r
88 PicoCpuFS68k.execinfo &= ~FM68K_HALTED; \\r
89 if (x) { PicoCpuFS68k.execinfo |= FM68K_HALTED; PicoCpuFS68k.io_cycle_counter = 0; } \\r
90}\r
91#define SekIsStoppedM68k() (PicoCpuFM68k.execinfo&FM68K_HALTED)\r
92#define SekIsStoppedS68k() (PicoCpuFS68k.execinfo&FM68K_HALTED)\r
93#define SekShouldInterrupt fm68k_would_interrupt()\r
94\r
95#define SekInterrupt(irq) PicoCpuFM68k.interrupts[0]=irq\r
96#define SekIrqLevel PicoCpuFM68k.interrupts[0]\r
97\r
98#ifdef EMU_M68K\r
99#define EMU_CORE_DEBUG\r
100#endif\r
101#endif\r
102\r
103#ifdef EMU_M68K\r
104#include "../cpu/musashi/m68kcpu.h"\r
105extern m68ki_cpu_core PicoCpuMM68k, PicoCpuMS68k;\r
106#ifndef SekCyclesLeft\r
107#define SekCyclesLeftNoMCD PicoCpuMM68k.cyc_remaining_cycles\r
108#define SekCyclesLeft \\r
109 (((PicoAHW&1) && (PicoOpt & POPT_EN_MCD_PSYNC)) ? (SekCycleAim-SekCycleCnt) : SekCyclesLeftNoMCD)\r
110#define SekCyclesLeftS68k \\r
111 ((PicoOpt & POPT_EN_MCD_PSYNC) ? (SekCycleAimS68k-SekCycleCntS68k) : PicoCpuMS68k.cyc_remaining_cycles)\r
112#define SekEndTimeslice(after) SET_CYCLES(after)\r
113#define SekEndTimesliceS68k(after) PicoCpuMS68k.cyc_remaining_cycles=after\r
114#define SekPc m68k_get_reg(&PicoCpuMM68k, M68K_REG_PC)\r
115#define SekPcS68k m68k_get_reg(&PicoCpuMS68k, M68K_REG_PC)\r
116#define SekDar(x) PicoCpuMM68k.dar[x]\r
117#define SekDarS68k(x) PicoCpuMS68k.dar[x]\r
118#define SekSr m68k_get_reg(&PicoCpuMM68k, M68K_REG_SR)\r
119#define SekSrS68k m68k_get_reg(&PicoCpuMS68k, M68K_REG_SR)\r
120#define SekSetStop(x) { \\r
121 if(x) { SET_CYCLES(0); PicoCpuMM68k.stopped=STOP_LEVEL_STOP; } \\r
122 else PicoCpuMM68k.stopped=0; \\r
123}\r
124#define SekSetStopS68k(x) { \\r
125 if(x) { SET_CYCLES(0); PicoCpuMS68k.stopped=STOP_LEVEL_STOP; } \\r
126 else PicoCpuMS68k.stopped=0; \\r
127}\r
128#define SekIsStoppedM68k() (PicoCpuMM68k.stopped==STOP_LEVEL_STOP)\r
129#define SekIsStoppedS68k() (PicoCpuMS68k.stopped==STOP_LEVEL_STOP)\r
130#define SekShouldInterrupt (CPU_INT_LEVEL > FLAG_INT_MASK)\r
131\r
132#define SekInterrupt(irq) { \\r
133 void *oldcontext = m68ki_cpu_p; \\r
134 m68k_set_context(&PicoCpuMM68k); \\r
135 m68k_set_irq(irq); \\r
136 m68k_set_context(oldcontext); \\r
137}\r
138#define SekIrqLevel (PicoCpuMM68k.int_level >> 8)\r
139\r
140#endif\r
141#endif // EMU_M68K\r
142\r
143extern int SekCycleCnt; // cycles done in this frame\r
144extern int SekCycleAim; // cycle aim\r
145extern unsigned int SekCycleCntT; // total cycle counter, updated once per frame\r
146\r
147#define SekCyclesReset() { \\r
148 SekCycleCntT+=SekCycleAim; \\r
149 SekCycleCnt-=SekCycleAim; \\r
150 SekCycleAim=0; \\r
151}\r
152#define SekCyclesBurn(c) SekCycleCnt+=c\r
153#define SekCyclesDone() (SekCycleAim-SekCyclesLeft) // number of cycles done in this frame (can be checked anywhere)\r
154#define SekCyclesDoneT() (SekCycleCntT+SekCyclesDone()) // total nuber of cycles done for this rom\r
155#define SekCyclesDoneT2() (SekCycleCntT + SekCycleCnt) // same as above but not from memhandlers\r
156\r
157#define SekEndRun(after) { \\r
158 SekCycleCnt -= SekCyclesLeft - (after); \\r
159 if (SekCycleCnt < 0) SekCycleCnt = 0; \\r
160 SekEndTimeslice(after); \\r
161}\r
162\r
163#define SekEndRunS68k(after) { \\r
164 SekCycleCntS68k -= SekCyclesLeftS68k - (after); \\r
165 if (SekCycleCntS68k < 0) SekCycleCntS68k = 0; \\r
166 SekEndTimesliceS68k(after); \\r
167}\r
168\r
169extern int SekCycleCntS68k;\r
170extern int SekCycleAimS68k;\r
171\r
172#define SekCyclesResetS68k() { \\r
173 SekCycleCntS68k-=SekCycleAimS68k; \\r
174 SekCycleAimS68k=0; \\r
175}\r
176#define SekCyclesDoneS68k() (SekCycleAimS68k-SekCyclesLeftS68k)\r
177\r
178#ifdef EMU_CORE_DEBUG\r
179extern int dbg_irq_level;\r
180#undef SekEndTimeslice\r
181#undef SekCyclesBurn\r
182#undef SekEndRun\r
183#undef SekInterrupt\r
184#define SekEndTimeslice(c)\r
185#define SekCyclesBurn(c) c\r
186#define SekEndRun(c)\r
187#define SekInterrupt(irq) dbg_irq_level=irq\r
188#endif\r
189\r
190// ----------------------- Z80 CPU -----------------------\r
191\r
192#if defined(_USE_DRZ80)\r
193#include "../cpu/DrZ80/drz80.h"\r
194\r
195extern struct DrZ80 drZ80;\r
196\r
197#define z80_run(cycles) ((cycles) - DrZ80Run(&drZ80, cycles))\r
198#define z80_run_nr(cycles) DrZ80Run(&drZ80, cycles)\r
199#define z80_int() drZ80.Z80_IRQ = 1\r
200\r
201#define z80_cyclesLeft drZ80.cycles\r
202#define z80_pc() (drZ80.Z80PC - drZ80.Z80PC_BASE)\r
203\r
204#elif defined(_USE_CZ80)\r
205#include "../cpu/cz80/cz80.h"\r
206\r
207#define z80_run(cycles) Cz80_Exec(&CZ80, cycles)\r
208#define z80_run_nr(cycles) Cz80_Exec(&CZ80, cycles)\r
209#define z80_int() Cz80_Set_IRQ(&CZ80, 0, HOLD_LINE)\r
210\r
211#define z80_cyclesLeft (CZ80.ICount - CZ80.ExtraCycles)\r
212#define z80_pc() Cz80_Get_Reg(&CZ80, CZ80_PC)\r
213\r
214#else\r
215\r
216#define z80_run(cycles) (cycles)\r
217#define z80_run_nr(cycles)\r
218#define z80_int()\r
219\r
220#endif\r
221\r
222#define Z80_STATE_SIZE 0x60\r
223\r
224extern int z80stopCycle; /* in 68k cycles */\r
225extern int z80_cycle_cnt; /* 'done' z80 cycles before z80_run() */\r
226extern int z80_cycle_aim;\r
227extern int z80_scanline;\r
228extern int z80_scanline_cycles; /* cycles done until z80_scanline */\r
229\r
230#define z80_resetCycles() \\r
231 z80_cycle_cnt = z80_cycle_aim = z80_scanline = z80_scanline_cycles = 0;\r
232\r
233#define z80_cyclesDone() \\r
234 (z80_cycle_aim - z80_cyclesLeft)\r
235\r
236#define cycles_68k_to_z80(x) ((x)*957 >> 11)\r
237\r
238// ----------------------- SH2 CPU -----------------------\r
239\r
240#include "cpu/sh2/sh2.h"\r
241\r
242extern SH2 sh2s[2];\r
243#define msh2 sh2s[0]\r
244#define ssh2 sh2s[1]\r
245\r
246#ifndef DRC_SH2\r
247# define sh2_end_run(sh2, after_) do { \\r
248 if ((sh2)->icount > (after_)) { \\r
249 (sh2)->cycles_timeslice -= (sh2)->icount - (after_); \\r
250 (sh2)->icount = after_; \\r
251 } \\r
252} while (0)\r
253# define sh2_cycles_left(sh2) (sh2)->icount\r
254# define sh2_pc(sh2) (sh2)->ppc\r
255#else\r
256# define sh2_end_run(sh2, after_) do { \\r
257 int left_ = (signed int)(sh2)->sr >> 12; \\r
258 if (left_ > (after_)) { \\r
259 (sh2)->cycles_timeslice -= left_ - (after_); \\r
260 (sh2)->sr &= 0xfff; \\r
261 (sh2)->sr |= (after_) << 12; \\r
262 } \\r
263} while (0)\r
264# define sh2_cycles_left(sh2) ((signed int)(sh2)->sr >> 12)\r
265# define sh2_pc(sh2) (sh2)->pc\r
266#endif\r
267\r
268#define sh2_cycles_done(sh2) ((int)(sh2)->cycles_timeslice - sh2_cycles_left(sh2))\r
269#define sh2_cycles_done_t(sh2) \\r
270 ((sh2)->m68krcycles_done * 3 + sh2_cycles_done(sh2))\r
271#define sh2_cycles_done_m68k(sh2) \\r
272 ((sh2)->m68krcycles_done + (sh2_cycles_done(sh2) / 3))\r
273\r
274#define sh2_reg(c, x) (c) ? ssh2.r[x] : msh2.r[x]\r
275#define sh2_gbr(c) (c) ? ssh2.gbr : msh2.gbr\r
276#define sh2_vbr(c) (c) ? ssh2.vbr : msh2.vbr\r
277#define sh2_sr(c) (((c) ? ssh2.sr : msh2.sr) & 0xfff)\r
278\r
279#define sh2_set_gbr(c, v) \\r
280 { if (c) ssh2.gbr = v; else msh2.gbr = v; }\r
281#define sh2_set_vbr(c, v) \\r
282 { if (c) ssh2.vbr = v; else msh2.vbr = v; }\r
283\r
284// ---------------------------------------------------------\r
285\r
286// main oscillator clock which controls timing\r
287#define OSC_NTSC 53693100\r
288#define OSC_PAL 53203424\r
289\r
290struct PicoVideo\r
291{\r
292 unsigned char reg[0x20];\r
293 unsigned int command; // 32-bit Command\r
294 unsigned char pending; // 1 if waiting for second half of 32-bit command\r
295 unsigned char type; // Command type (v/c/vsram read/write)\r
296 unsigned short addr; // Read/Write address\r
297 int status; // Status bits\r
298 unsigned char pending_ints; // pending interrupts: ??VH????\r
299 signed char lwrite_cnt; // VDP write count during active display line\r
300 unsigned short v_counter; // V-counter\r
301 unsigned char pad[0x10];\r
302};\r
303\r
304struct PicoMisc\r
305{\r
306 unsigned char rotate;\r
307 unsigned char z80Run;\r
308 unsigned char padTHPhase[2]; // 02 phase of gamepad TH switches\r
309 unsigned short scanline; // 04 0 to 261||311\r
310 char dirtyPal; // 06 Is the palette dirty (1 - change @ this frame, 2 - some time before)\r
311 unsigned char hardware; // 07 Hardware value for country\r
312 unsigned char pal; // 08 1=PAL 0=NTSC\r
313 unsigned char sram_reg; // 09 SRAM reg. See SRR_* below\r
314 unsigned short z80_bank68k; // 0a\r
315 unsigned short pad0;\r
316 unsigned char pad1;\r
317 unsigned char z80_reset; // 0f z80 reset held\r
318 unsigned char padDelay[2]; // 10 gamepad phase time outs, so we count a delay\r
319 unsigned short eeprom_addr; // EEPROM address register\r
320 unsigned char eeprom_cycle; // EEPROM cycle number\r
321 unsigned char eeprom_slave; // EEPROM slave word for X24C02 and better SRAMs\r
322 unsigned char eeprom_status;\r
323 unsigned char pad2;\r
324 unsigned short dma_xfers; // 18\r
325 unsigned char eeprom_wb[2]; // EEPROM latch/write buffer\r
326 unsigned int frame_count; // 1c for movies and idle det\r
327};\r
328\r
329struct PicoMS\r
330{\r
331 unsigned char carthw[0x10];\r
332 unsigned char io_ctl;\r
333 unsigned char pad[0x4f];\r
334};\r
335\r
336// some assembly stuff depend on these, do not touch!\r
337struct Pico\r
338{\r
339 unsigned char ram[0x10000]; // 0x00000 scratch ram\r
340 union { // vram is byteswapped for easier reads when drawing\r
341 unsigned short vram[0x8000]; // 0x10000\r
342 unsigned char vramb[0x4000]; // VRAM in SMS mode\r
343 };\r
344 unsigned char zram[0x2000]; // 0x20000 Z80 ram\r
345 unsigned char ioports[0x10]; // XXX: fix asm and mv\r
346 unsigned char pad[0xf0]; // unused\r
347 unsigned short cram[0x40]; // 0x22100\r
348 unsigned short vsram[0x40]; // 0x22180\r
349\r
350 unsigned char *rom; // 0x22200\r
351 unsigned int romsize; // 0x22204\r
352\r
353 struct PicoMisc m;\r
354 struct PicoVideo video;\r
355 struct PicoMS ms;\r
356};\r
357\r
358// sram\r
359#define SRR_MAPPED (1 << 0)\r
360#define SRR_READONLY (1 << 1)\r
361\r
362#define SRF_ENABLED (1 << 0)\r
363#define SRF_EEPROM (1 << 1)\r
364\r
365struct PicoSRAM\r
366{\r
367 unsigned char *data; // actual data\r
368 unsigned int start; // start address in 68k address space\r
369 unsigned int end;\r
370 unsigned char flags; // 0c: SRF_*\r
371 unsigned char unused2;\r
372 unsigned char changed;\r
373 unsigned char eeprom_type; // eeprom type: 0: 7bit (24C01), 2: 2 addr words (X24C02+), 3: 3 addr words\r
374 unsigned char unused3;\r
375 unsigned char eeprom_bit_cl; // bit number for cl\r
376 unsigned char eeprom_bit_in; // bit number for in\r
377 unsigned char eeprom_bit_out; // bit number for out\r
378 unsigned int size;\r
379};\r
380\r
381// MCD\r
382#include "cd/cd_sys.h"\r
383#include "cd/LC89510.h"\r
384#include "cd/gfx_cd.h"\r
385\r
386struct mcd_pcm\r
387{\r
388 unsigned char control; // reg7\r
389 unsigned char enabled; // reg8\r
390 unsigned char cur_ch;\r
391 unsigned char bank;\r
392 int pad1;\r
393\r
394 struct pcm_chan // 08, size 0x10\r
395 {\r
396 unsigned char regs[8];\r
397 unsigned int addr; // .08: played sample address\r
398 int pad;\r
399 } ch[8];\r
400};\r
401\r
402struct mcd_misc\r
403{\r
404 unsigned short hint_vector;\r
405 unsigned char busreq;\r
406 unsigned char s68k_pend_ints;\r
407 unsigned int state_flags; // 04: emu state: reset_pending\r
408 unsigned int counter75hz;\r
409 unsigned int pad0;\r
410 int timer_int3; // 10\r
411 unsigned int timer_stopwatch;\r
412 unsigned char bcram_reg; // 18: battery-backed RAM cart register\r
413 unsigned char pad2;\r
414 unsigned short pad3;\r
415 int pad[9];\r
416};\r
417\r
418typedef struct\r
419{\r
420 unsigned char bios[0x20000]; // 000000: 128K\r
421 union { // 020000: 512K\r
422 unsigned char prg_ram[0x80000];\r
423 unsigned char prg_ram_b[4][0x20000];\r
424 };\r
425 union { // 0a0000: 256K\r
426 struct {\r
427 unsigned char word_ram2M[0x40000];\r
428 unsigned char unused0[0x20000];\r
429 };\r
430 struct {\r
431 unsigned char unused1[0x20000];\r
432 unsigned char word_ram1M[2][0x20000];\r
433 };\r
434 };\r
435 union { // 100000: 64K\r
436 unsigned char pcm_ram[0x10000];\r
437 unsigned char pcm_ram_b[0x10][0x1000];\r
438 };\r
439 unsigned char s68k_regs[0x200]; // 110000: GA, not CPU regs\r
440 unsigned char bram[0x2000]; // 110200: 8K\r
441 struct mcd_misc m; // 112200: misc\r
442 struct mcd_pcm pcm; // 112240:\r
443 _scd_toc TOC; // not to be saved\r
444 CDD cdd;\r
445 CDC cdc;\r
446 _scd scd;\r
447 Rot_Comp rot_comp;\r
448} mcd_state;\r
449\r
450// XXX: this will need to be reworked for cart+cd support.\r
451#define Pico_mcd ((mcd_state *)Pico.rom)\r
452\r
453// 32X\r
454#define P32XS_FM (1<<15)\r
455#define P32XS_REN (1<< 7)\r
456#define P32XS_nRES (1<< 1)\r
457#define P32XS_ADEN (1<< 0)\r
458#define P32XS2_ADEN (1<< 9)\r
459#define P32XS_FULL (1<< 7) // DREQ FIFO full\r
460#define P32XS_68S (1<< 2)\r
461#define P32XS_DMA (1<< 1)\r
462#define P32XS_RV (1<< 0)\r
463\r
464#define P32XV_nPAL (1<<15) // VDP\r
465#define P32XV_PRI (1<< 7)\r
466#define P32XV_Mx (3<< 0) // display mode mask\r
467\r
468#define P32XV_SFT (1<< 0)\r
469\r
470#define P32XV_VBLK (1<<15)\r
471#define P32XV_HBLK (1<<14)\r
472#define P32XV_PEN (1<<13)\r
473#define P32XV_nFEN (1<< 1)\r
474#define P32XV_FS (1<< 0)\r
475\r
476#define P32XP_RTP (1<<7) // PWM control\r
477#define P32XP_FULL (1<<15) // PWM pulse\r
478#define P32XP_EMPTY (1<<14)\r
479\r
480#define P32XF_68KCPOLL (1 << 0)\r
481#define P32XF_68KVPOLL (1 << 1)\r
482\r
483#define P32XI_VRES (1 << 14/2) // IRL/2\r
484#define P32XI_VINT (1 << 12/2)\r
485#define P32XI_HINT (1 << 10/2)\r
486#define P32XI_CMD (1 << 8/2)\r
487#define P32XI_PWM (1 << 6/2)\r
488\r
489// peripheral reg access\r
490#define PREG8(regs,offs) ((unsigned char *)regs)[offs ^ 3]\r
491\r
492// real one is 4*2, but we use more because we don't lockstep\r
493#define DMAC_FIFO_LEN (4*4)\r
494#define PWM_BUFF_LEN 1024 // in one channel samples\r
495\r
496#define SH2_DRCBLK_RAM_SHIFT 1\r
497#define SH2_DRCBLK_DA_SHIFT 1\r
498\r
499#define SH2_READ_SHIFT 25\r
500#define SH2_WRITE_SHIFT 25\r
501\r
502struct Pico32x\r
503{\r
504 unsigned short regs[0x20];\r
505 unsigned short vdp_regs[0x10]; // 0x40\r
506 unsigned short sh2_regs[3]; // 0x60\r
507 unsigned char pending_fb;\r
508 unsigned char dirty_pal;\r
509 unsigned int emu_flags;\r
510 unsigned char sh2irq_mask[2];\r
511 unsigned char sh2irqi[2]; // individual\r
512 unsigned int sh2irqs; // common irqs\r
513 unsigned short dmac_fifo[DMAC_FIFO_LEN];\r
514 unsigned int dmac0_fifo_ptr;\r
515 unsigned int pad;\r
516 unsigned char comm_dirty_68k;\r
517 unsigned char comm_dirty_sh2;\r
518 unsigned char pwm_irq_cnt;\r
519 unsigned char pad1;\r
520 unsigned short pwm_p[2]; // pwm pos in fifo\r
521 unsigned int pwm_cycle_p; // pwm play cursor (32x cycles)\r
522 unsigned int reserved[6];\r
523};\r
524\r
525struct Pico32xMem\r
526{\r
527 unsigned char sdram[0x40000];\r
528#ifdef DRC_SH2\r
529 unsigned short drcblk_ram[1 << (18 - SH2_DRCBLK_RAM_SHIFT)];\r
530#endif\r
531 unsigned short dram[2][0x20000/2]; // AKA fb\r
532 union {\r
533 unsigned char m68k_rom[0x100];\r
534 unsigned char m68k_rom_bank[0x10000]; // M68K_BANK_SIZE\r
535 };\r
536#ifdef DRC_SH2\r
537 unsigned short drcblk_da[2][1 << (12 - SH2_DRCBLK_DA_SHIFT)];\r
538#endif\r
539 unsigned char sh2_rom_m[0x800];\r
540 unsigned char sh2_rom_s[0x400];\r
541 unsigned short pal[0x100];\r
542 unsigned short pal_native[0x100]; // converted to native (for renderer)\r
543 signed short pwm[2*PWM_BUFF_LEN]; // PWM buffer for current frame\r
544 signed short pwm_fifo[2][4]; // [0] - current, others - fifo entries\r
545};\r
546\r
547// area.c\r
548extern void (*PicoLoadStateHook)(void);\r
549\r
550typedef struct {\r
551 int chunk;\r
552 int size;\r
553 void *ptr;\r
554} carthw_state_chunk;\r
555extern carthw_state_chunk *carthw_chunks;\r
556#define CHUNK_CARTHW 64\r
557\r
558// cart.c\r
559extern int PicoCartResize(int newsize);\r
560extern void Byteswap(void *dst, const void *src, int len);\r
561extern void (*PicoCartMemSetup)(void);\r
562extern void (*PicoCartUnloadHook)(void);\r
563\r
564// debug.c\r
565int CM_compareRun(int cyc, int is_sub);\r
566\r
567// draw.c\r
568PICO_INTERNAL void PicoFrameStart(void);\r
569void PicoDrawSync(int to, int blank_last_line);\r
570void BackFill(int reg7, int sh);\r
571void FinalizeLine555(int sh, int line);\r
572extern int (*PicoScanBegin)(unsigned int num);\r
573extern int (*PicoScanEnd)(unsigned int num);\r
574extern int DrawScanline;\r
575#define MAX_LINE_SPRITES 29\r
576extern unsigned char HighLnSpr[240][3 + MAX_LINE_SPRITES];\r
577extern void *DrawLineDestBase;\r
578extern int DrawLineDestIncrement;\r
579\r
580// draw2.c\r
581PICO_INTERNAL void PicoFrameFull();\r
582\r
583// mode4.c\r
584void PicoFrameStartMode4(void);\r
585void PicoLineMode4(int line);\r
586void PicoDoHighPal555M4(void);\r
587void PicoDrawSetOutputMode4(pdso_t which);\r
588\r
589// memory.c\r
590PICO_INTERNAL void PicoMemSetup(void);\r
591unsigned int PicoRead8_io(unsigned int a);\r
592unsigned int PicoRead16_io(unsigned int a);\r
593void PicoWrite8_io(unsigned int a, unsigned int d);\r
594void PicoWrite16_io(unsigned int a, unsigned int d);\r
595void p32x_dreq1_trigger(void);\r
596\r
597// pico/memory.c\r
598PICO_INTERNAL void PicoMemSetupPico(void);\r
599\r
600// cd/memory.c\r
601PICO_INTERNAL void PicoMemSetupCD(void);\r
602void PicoMemStateLoaded(void);\r
603\r
604// pico.c\r
605extern struct Pico Pico;\r
606extern struct PicoSRAM SRam;\r
607extern int PicoPadInt[2];\r
608extern int emustatus;\r
609extern int scanlines_total;\r
610extern void (*PicoResetHook)(void);\r
611extern void (*PicoLineHook)(void);\r
612PICO_INTERNAL int CheckDMA(void);\r
613PICO_INTERNAL void PicoDetectRegion(void);\r
614PICO_INTERNAL void PicoSyncZ80(int m68k_cycles_done);\r
615\r
616// cd/pico.c\r
617PICO_INTERNAL void PicoInitMCD(void);\r
618PICO_INTERNAL void PicoExitMCD(void);\r
619PICO_INTERNAL void PicoPowerMCD(void);\r
620PICO_INTERNAL int PicoResetMCD(void);\r
621PICO_INTERNAL void PicoFrameMCD(void);\r
622\r
623// pico/pico.c\r
624PICO_INTERNAL void PicoInitPico(void);\r
625PICO_INTERNAL void PicoReratePico(void);\r
626\r
627// pico/xpcm.c\r
628PICO_INTERNAL void PicoPicoPCMUpdate(short *buffer, int length, int stereo);\r
629PICO_INTERNAL void PicoPicoPCMReset(void);\r
630PICO_INTERNAL void PicoPicoPCMRerate(int xpcm_rate);\r
631\r
632// sek.c\r
633PICO_INTERNAL void SekInit(void);\r
634PICO_INTERNAL int SekReset(void);\r
635PICO_INTERNAL void SekState(int *data);\r
636PICO_INTERNAL void SekSetRealTAS(int use_real);\r
637PICO_INTERNAL void SekPackCpu(unsigned char *cpu, int is_sub);\r
638PICO_INTERNAL void SekUnpackCpu(const unsigned char *cpu, int is_sub);\r
639void SekStepM68k(void);\r
640void SekInitIdleDet(void);\r
641void SekFinishIdleDet(void);\r
642#if defined(CPU_CMP_R) || defined(CPU_CMP_W)\r
643void SekTrace(int is_s68k);\r
644#else\r
645#define SekTrace(x)\r
646#endif\r
647\r
648// cd/sek.c\r
649PICO_INTERNAL void SekInitS68k(void);\r
650PICO_INTERNAL int SekResetS68k(void);\r
651PICO_INTERNAL int SekInterruptS68k(int irq);\r
652\r
653// sound/sound.c\r
654PICO_INTERNAL void cdda_start_play();\r
655extern short cdda_out_buffer[2*1152];\r
656extern int PsndLen_exc_cnt;\r
657extern int PsndLen_exc_add;\r
658extern int timer_a_next_oflow, timer_a_step; // in z80 cycles\r
659extern int timer_b_next_oflow, timer_b_step;\r
660\r
661void ym2612_sync_timers(int z80_cycles, int mode_old, int mode_new);\r
662void ym2612_pack_state(void);\r
663void ym2612_unpack_state(void);\r
664\r
665#define TIMER_NO_OFLOW 0x70000000\r
666// tA = 72 * (1024 - NA) / M\r
667#define TIMER_A_TICK_ZCYCLES 17203\r
668// tB = 1152 * (256 - NA) / M\r
669#define TIMER_B_TICK_ZCYCLES 262800 // 275251 broken, see Dai Makaimura\r
670\r
671#define timers_cycle() \\r
672 if (timer_a_next_oflow > 0 && timer_a_next_oflow < TIMER_NO_OFLOW) \\r
673 timer_a_next_oflow -= Pico.m.pal ? 70938*256 : 59659*256; \\r
674 if (timer_b_next_oflow > 0 && timer_b_next_oflow < TIMER_NO_OFLOW) \\r
675 timer_b_next_oflow -= Pico.m.pal ? 70938*256 : 59659*256; \\r
676 ym2612_sync_timers(0, ym2612.OPN.ST.mode, ym2612.OPN.ST.mode);\r
677\r
678#define timers_reset() \\r
679 timer_a_next_oflow = timer_b_next_oflow = TIMER_NO_OFLOW; \\r
680 timer_a_step = TIMER_A_TICK_ZCYCLES * 1024; \\r
681 timer_b_step = TIMER_B_TICK_ZCYCLES * 256;\r
682\r
683\r
684// videoport.c\r
685PICO_INTERNAL_ASM void PicoVideoWrite(unsigned int a,unsigned short d);\r
686PICO_INTERNAL_ASM unsigned int PicoVideoRead(unsigned int a);\r
687PICO_INTERNAL_ASM unsigned int PicoVideoRead8(unsigned int a);\r
688extern int (*PicoDmaHook)(unsigned int source, int len, unsigned short **srcp, unsigned short **limitp);\r
689\r
690// misc.c\r
691PICO_INTERNAL_ASM void memcpy16(unsigned short *dest, unsigned short *src, int count);\r
692PICO_INTERNAL_ASM void memcpy16bswap(unsigned short *dest, void *src, int count);\r
693PICO_INTERNAL_ASM void memcpy32(int *dest, int *src, int count); // 32bit word count\r
694PICO_INTERNAL_ASM void memset32(int *dest, int c, int count);\r
695\r
696// eeprom.c\r
697void EEPROM_write8(unsigned int a, unsigned int d);\r
698void EEPROM_write16(unsigned int d);\r
699unsigned int EEPROM_read(void);\r
700\r
701// z80 functionality wrappers\r
702PICO_INTERNAL void z80_init(void);\r
703PICO_INTERNAL void z80_pack(void *data);\r
704PICO_INTERNAL int z80_unpack(const void *data);\r
705PICO_INTERNAL void z80_reset(void);\r
706PICO_INTERNAL void z80_exit(void);\r
707\r
708// cd/misc.c\r
709PICO_INTERNAL_ASM void wram_2M_to_1M(unsigned char *m);\r
710PICO_INTERNAL_ASM void wram_1M_to_2M(unsigned char *m);\r
711\r
712// cd/buffering.c\r
713PICO_INTERNAL void PicoCDBufferRead(void *dest, int lba);\r
714\r
715// sound/sound.c\r
716PICO_INTERNAL void PsndReset(void);\r
717PICO_INTERNAL void PsndDoDAC(int line_to);\r
718PICO_INTERNAL void PsndClear(void);\r
719PICO_INTERNAL void PsndGetSamples(int y);\r
720PICO_INTERNAL void PsndGetSamplesMS(void);\r
721extern int PsndDacLine;\r
722\r
723// sms.c\r
724#ifndef NO_SMS\r
725void PicoPowerMS(void);\r
726void PicoResetMS(void);\r
727void PicoMemSetupMS(void);\r
728void PicoStateLoadedMS(void);\r
729void PicoFrameMS(void);\r
730void PicoFrameDrawOnlyMS(void);\r
731#else\r
732#define PicoPowerMS()\r
733#define PicoResetMS()\r
734#define PicoMemSetupMS()\r
735#define PicoStateLoadedMS()\r
736#define PicoFrameMS()\r
737#define PicoFrameDrawOnlyMS()\r
738#endif\r
739\r
740// 32x/32x.c\r
741#ifndef NO_32X\r
742extern struct Pico32x Pico32x;\r
743enum p32x_event {\r
744 P32X_EVENT_PWM,\r
745 P32X_EVENT_FILLEND,\r
746 P32X_EVENT_COUNT,\r
747};\r
748extern unsigned int event_times[P32X_EVENT_COUNT];\r
749\r
750void Pico32xInit(void);\r
751void PicoPower32x(void);\r
752void PicoReset32x(void);\r
753void Pico32xStartup(void);\r
754void PicoUnload32x(void);\r
755void PicoFrame32x(void);\r
756void Pico32xStateLoaded(int is_early);\r
757void p32x_sync_sh2s(unsigned int m68k_target);\r
758void p32x_sync_other_sh2(SH2 *sh2, unsigned int m68k_target);\r
759void p32x_update_irls(SH2 *active_sh2, int m68k_cycles);\r
760void p32x_reset_sh2s(void);\r
761void p32x_event_schedule(unsigned int now, enum p32x_event event, int after);\r
762void p32x_event_schedule_sh2(SH2 *sh2, enum p32x_event event, int after);\r
763\r
764// 32x/memory.c\r
765struct Pico32xMem *Pico32xMem;\r
766unsigned int PicoRead8_32x(unsigned int a);\r
767unsigned int PicoRead16_32x(unsigned int a);\r
768void PicoWrite8_32x(unsigned int a, unsigned int d);\r
769void PicoWrite16_32x(unsigned int a, unsigned int d);\r
770void PicoMemSetup32x(void);\r
771void Pico32xSwapDRAM(int b);\r
772void Pico32xMemStateLoaded(void);\r
773void p32x_m68k_poll_event(unsigned int flags);\r
774void p32x_sh2_poll_event(SH2 *sh2, unsigned int flags, unsigned int m68k_cycles);\r
775\r
776// 32x/draw.c\r
777void PicoDrawSetOutFormat32x(pdso_t which, int use_32x_line_mode);\r
778void FinalizeLine32xRGB555(int sh, int line);\r
779void PicoDraw32xLayer(int offs, int lines, int mdbg);\r
780void PicoDraw32xLayerMdOnly(int offs, int lines);\r
781extern int (*PicoScan32xBegin)(unsigned int num);\r
782extern int (*PicoScan32xEnd)(unsigned int num);\r
783enum {\r
784 PDM32X_OFF,\r
785 PDM32X_32X_ONLY,\r
786 PDM32X_BOTH,\r
787};\r
788extern int Pico32xDrawMode;\r
789\r
790// 32x/pwm.c\r
791unsigned int p32x_pwm_read16(unsigned int a, SH2 *sh2,\r
792 unsigned int m68k_cycles);\r
793void p32x_pwm_write16(unsigned int a, unsigned int d,\r
794 SH2 *sh2, unsigned int m68k_cycles);\r
795void p32x_pwm_update(int *buf32, int length, int stereo);\r
796void p32x_pwm_ctl_changed(void);\r
797void p32x_pwm_schedule(unsigned int m68k_now);\r
798void p32x_pwm_schedule_sh2(SH2 *sh2);\r
799void p32x_pwm_irq_event(unsigned int m68k_now);\r
800void p32x_pwm_state_loaded(void);\r
801\r
802// 32x/sh2soc.c\r
803void p32x_dreq0_trigger(void);\r
804void p32x_dreq1_trigger(void);\r
805void p32x_timers_recalc(void);\r
806void p32x_timers_do(unsigned int m68k_slice);\r
807unsigned int sh2_peripheral_read8(unsigned int a, SH2 *sh2);\r
808unsigned int sh2_peripheral_read16(unsigned int a, SH2 *sh2);\r
809unsigned int sh2_peripheral_read32(unsigned int a, SH2 *sh2);\r
810void sh2_peripheral_write8(unsigned int a, unsigned int d, SH2 *sh2);\r
811void sh2_peripheral_write16(unsigned int a, unsigned int d, SH2 *sh2);\r
812void sh2_peripheral_write32(unsigned int a, unsigned int d, SH2 *sh2);\r
813\r
814#else\r
815#define Pico32xInit()\r
816#define PicoPower32x()\r
817#define PicoReset32x()\r
818#define PicoFrame32x()\r
819#define PicoUnload32x()\r
820#define Pico32xStateLoaded()\r
821#define FinalizeLine32xRGB555 NULL\r
822#define p32x_pwm_update(...)\r
823#define p32x_timers_recalc()\r
824#endif\r
825\r
826/* avoid dependency on newer glibc */\r
827static __inline int isspace_(int c)\r
828{\r
829 return (0x09 <= c && c <= 0x0d) || c == ' ';\r
830}\r
831\r
832#ifndef ARRAY_SIZE\r
833#define ARRAY_SIZE(x) (sizeof(x) / sizeof(x[0]))\r
834#endif\r
835\r
836// emulation event logging\r
837#ifndef EL_LOGMASK\r
838# ifdef __x86_64__ // HACK\r
839# define EL_LOGMASK (EL_STATUS|EL_IDLE|EL_ANOMALY)\r
840# else\r
841# define EL_LOGMASK (EL_STATUS)\r
842# endif\r
843#endif\r
844\r
845#define EL_HVCNT 0x00000001 /* hv counter reads */\r
846#define EL_SR 0x00000002 /* SR reads */\r
847#define EL_INTS 0x00000004 /* ints and acks */\r
848#define EL_YMTIMER 0x00000008 /* ym2612 timer stuff */\r
849#define EL_INTSW 0x00000010 /* log irq switching on/off */\r
850#define EL_ASVDP 0x00000020 /* VDP accesses during active scan */\r
851#define EL_VDPDMA 0x00000040 /* VDP DMA transfers and their timing */\r
852#define EL_BUSREQ 0x00000080 /* z80 busreq r/w or reset w */\r
853#define EL_Z80BNK 0x00000100 /* z80 i/o through bank area */\r
854#define EL_SRAMIO 0x00000200 /* sram i/o */\r
855#define EL_EEPROM 0x00000400 /* eeprom debug */\r
856#define EL_UIO 0x00000800 /* unmapped i/o */\r
857#define EL_IO 0x00001000 /* all i/o */\r
858#define EL_CDPOLL 0x00002000 /* MCD: log poll detection */\r
859#define EL_SVP 0x00004000 /* SVP stuff */\r
860#define EL_PICOHW 0x00008000 /* Pico stuff */\r
861#define EL_IDLE 0x00010000 /* idle loop det. */\r
862#define EL_CDREGS 0x00020000 /* MCD: register access */\r
863#define EL_CDREG3 0x00040000 /* MCD: register 3 only */\r
864#define EL_32X 0x00080000\r
865#define EL_PWM 0x00100000 /* 32X PWM stuff (LOTS of output) */\r
866#define EL_32XP 0x00200000 /* 32X peripherals */\r
867\r
868#define EL_STATUS 0x40000000 /* status messages */\r
869#define EL_ANOMALY 0x80000000 /* some unexpected conditions (during emulation) */\r
870\r
871#if EL_LOGMASK\r
872#define elprintf(w,f,...) \\r
873do { \\r
874 if ((w) & EL_LOGMASK) \\r
875 lprintf("%05i:%03i: " f "\n",Pico.m.frame_count,Pico.m.scanline,##__VA_ARGS__); \\r
876} while (0)\r
877#elif defined(_MSC_VER)\r
878#define elprintf\r
879#else\r
880#define elprintf(w,f,...)\r
881#endif\r
882\r
883// profiling\r
884#ifdef PPROF\r
885#include <platform/linux/pprof.h>\r
886#else\r
887#define pprof_init()\r
888#define pprof_finish()\r
889#define pprof_start(x)\r
890#define pprof_end(...)\r
891#define pprof_end_sub(...)\r
892#endif\r
893\r
894#ifdef EVT_LOG\r
895enum evt {\r
896 EVT_FRAME_START,\r
897 EVT_NEXT_LINE,\r
898 EVT_RUN_START,\r
899 EVT_RUN_END,\r
900 EVT_POLL_START,\r
901 EVT_POLL_END,\r
902 EVT_CNT\r
903};\r
904\r
905enum evt_cpu {\r
906 EVT_M68K,\r
907 EVT_S68K,\r
908 EVT_MSH2,\r
909 EVT_SSH2,\r
910 EVT_CPU_CNT\r
911};\r
912\r
913void pevt_log(unsigned int cycles, enum evt_cpu c, enum evt e);\r
914void pevt_dump(void);\r
915\r
916#define pevt_log_m68k(e) \\r
917 pevt_log(SekCyclesDoneT(), EVT_M68K, e)\r
918#define pevt_log_m68k_o(e) \\r
919 pevt_log(SekCyclesDoneT2(), EVT_M68K, e)\r
920#define pevt_log_sh2(sh2, e) \\r
921 pevt_log(sh2_cycles_done_m68k(sh2), EVT_MSH2 + (sh2)->is_slave, e)\r
922#define pevt_log_sh2_o(sh2, e) \\r
923 pevt_log((sh2)->m68krcycles_done, EVT_MSH2 + (sh2)->is_slave, e)\r
924#else\r
925#define pevt_log(c, e)\r
926#define pevt_log_m68k(e)\r
927#define pevt_log_m68k_o(e)\r
928#define pevt_log_sh2(sh2, e)\r
929#define pevt_log_sh2_o(sh2, e)\r
930#define pevt_dump()\r
931#endif\r
932\r
933// misc\r
934#ifdef _MSC_VER\r
935#define cdprintf\r
936#else\r
937#define cdprintf(x...)\r
938#endif\r
939\r
940#ifdef __i386__\r
941#define REGPARM(x) __attribute__((regparm(x)))\r
942#else\r
943#define REGPARM(x)\r
944#endif\r
945\r
946#ifdef __GNUC__\r
947#define NOINLINE __attribute__((noinline))\r
948#else\r
949#define NOINLINE\r
950#endif\r
951\r
952#ifdef __cplusplus\r
953} // End of extern "C"\r
954#endif\r
955\r
956#endif // PICO_INTERNAL_INCLUDED\r
957\r