Pico/carthw/svp/compiler.c

   1 // SSP1601 to ARM recompiler
   2
   3 // (c) Copyright 2008, Grazvydas "notaz" Ignotas
   4 // Free for non-commercial use.
   5
   6 #include "../../PicoInt.h"
   7 #include "compiler.h"
   8
   9 #define u32 unsigned int
  10
  11 static u32 *tcache_ptr = NULL;
  12
  13 static int nblocks = 0;
  14 static int n_in_ops = 0;
  15
  16 extern ssp1601_t *ssp;
  17
  18 #define rPC    ssp->gr[SSP_PC].h
  19 #define rPMC   ssp->gr[SSP_PMC]
  20
  21 #define SSP_FLAG_Z (1<<0xd)
  22 #define SSP_FLAG_N (1<<0xf)
  23
  24 #ifndef ARM
  25 #define DUMP_BLOCK 0x0c9a
  26 u32 tcache[SSP_TCACHE_SIZE/4];
  27 u32 *ssp_block_table[0x5090/2];
  28 u32 *ssp_block_table_iram[15][0x800/2];
  29 char ssp_align[SSP_BLOCKTAB_ALIGN_SIZE];
  30 void ssp_drc_next(void){}
  31 void ssp_drc_next_patch(void){}
  32 void ssp_drc_end(void){}
  33 #endif
  34
  35 #include "gen_arm.c"
  36
  37 // -----------------------------------------------------
  38
  39 static int get_inc(int mode)
  40 {
  41         int inc = (mode >> 11) & 7;
  42         if (inc != 0) {
  43                 if (inc != 7) inc--;
  44                 inc = 1 << inc; // 0 1 2 4 8 16 32 128
  45                 if (mode & 0x8000) inc = -inc; // decrement mode
  46         }
  47         return inc;
  48 }
  49
  50 u32 ssp_pm_read(int reg)
  51 {
  52         u32 d = 0, mode;
  53
  54         if (ssp->emu_status & SSP_PMC_SET)
  55         {
  56                 ssp->pmac_read[reg] = rPMC.v;
  57                 ssp->emu_status &= ~SSP_PMC_SET;
  58                 return 0;
  59         }
  60
  61         // just in case
  62         ssp->emu_status &= ~SSP_PMC_HAVE_ADDR;
  63
  64         mode = ssp->pmac_read[reg]>>16;
  65         if      ((mode & 0xfff0) == 0x0800) // ROM
  66         {
  67                 d = ((unsigned short *)Pico.rom)[ssp->pmac_read[reg]&0xfffff];
  68                 ssp->pmac_read[reg] += 1;
  69         }
  70         else if ((mode & 0x47ff) == 0x0018) // DRAM
  71         {
  72                 unsigned short *dram = (unsigned short *)svp->dram;
  73                 int inc = get_inc(mode);
  74                 d = dram[ssp->pmac_read[reg]&0xffff];
  75                 ssp->pmac_read[reg] += inc;
  76         }
  77
  78         // PMC value corresponds to last PMR accessed
  79         rPMC.v = ssp->pmac_read[reg];
  80
  81         return d;
  82 }
  83
  84 #define overwrite_write(dst, d) \
  85 { \
  86         if (d & 0xf000) { dst &= ~0xf000; dst |= d & 0xf000; } \
  87         if (d & 0x0f00) { dst &= ~0x0f00; dst |= d & 0x0f00; } \
  88         if (d & 0x00f0) { dst &= ~0x00f0; dst |= d & 0x00f0; } \
  89         if (d & 0x000f) { dst &= ~0x000f; dst |= d & 0x000f; } \
  90 }
  91
  92 void ssp_pm_write(u32 d, int reg)
  93 {
  94         unsigned short *dram;
  95         int mode, addr;
  96
  97         if (ssp->emu_status & SSP_PMC_SET)
  98         {
  99                 ssp->pmac_write[reg] = rPMC.v;
 100                 ssp->emu_status &= ~SSP_PMC_SET;
 101                 return;
 102         }
 103
 104         // just in case
 105         ssp->emu_status &= ~SSP_PMC_HAVE_ADDR;
 106
 107         dram = (unsigned short *)svp->dram;
 108         mode = ssp->pmac_write[reg]>>16;
 109         addr = ssp->pmac_write[reg]&0xffff;
 110         if      ((mode & 0x43ff) == 0x0018) // DRAM
 111         {
 112                 int inc = get_inc(mode);
 113                 if (mode & 0x0400) {
 114                        overwrite_write(dram[addr], d);
 115                 } else dram[addr] = d;
 116                 ssp->pmac_write[reg] += inc;
 117         }
 118         else if ((mode & 0xfbff) == 0x4018) // DRAM, cell inc
 119         {
 120                 if (mode & 0x0400) {
 121                        overwrite_write(dram[addr], d);
 122                 } else dram[addr] = d;
 123                 ssp->pmac_write[reg] += (addr&1) ? 0x1f : 1;
 124         }
 125         else if ((mode & 0x47ff) == 0x001c) // IRAM
 126         {
 127                 int inc = get_inc(mode);
 128                 ((unsigned short *)svp->iram_rom)[addr&0x3ff] = d;
 129                 ssp->pmac_write[reg] += inc;
 130                 ssp->drc.iram_dirty = 1;
 131         }
 132
 133         rPMC.v = ssp->pmac_write[reg];
 134 }
 135
 136
 137 // -----------------------------------------------------
 138
 139 // 14 IRAM blocks
 140 static unsigned char iram_context_map[] =
 141 {
 142          0, 0, 0, 0, 1, 0, 0, 0, // 04
 143          0, 0, 0, 0, 0, 0, 2, 0, // 0e
 144          0, 0, 0, 0, 0, 3, 0, 4, // 15 17
 145          5, 0, 0, 6, 0, 7, 0, 0, // 18 1b 1d
 146          8, 9, 0, 0, 0,10, 0, 0, // 20 21 25
 147          0, 0, 0, 0, 0, 0, 0, 0,
 148          0, 0,11, 0, 0,12, 0, 0, // 32 35
 149         13,14, 0, 0, 0, 0, 0, 0  // 38 39
 150 };
 151
 152 int ssp_get_iram_context(void)
 153 {
 154         unsigned char *ir = (unsigned char *)svp->iram_rom;
 155         int val1, val = ir[0x083^1] + ir[0x4FA^1] + ir[0x5F7^1] + ir[0x47B^1];
 156         val1 = iram_context_map[(val>>1)&0x3f];
 157
 158         if (val1 == 0) {
 159                 elprintf(EL_ANOMALY, "svp: iram ctx val: %02x PC=%04x\n", (val>>1)&0x3f, rPC);
 160                 //debug_dump2file(name, svp->iram_rom, 0x800);
 161                 //exit(1);
 162         }
 163         return val1;
 164 }
 165
 166 // -----------------------------------------------------
 167
 168 /* regs with known values */
 169 static struct
 170 {
 171         ssp_reg_t gr[8];
 172         unsigned char r[8];
 173         unsigned int pmac_read[5];
 174         unsigned int pmac_write[5];
 175         ssp_reg_t pmc;
 176         unsigned int emu_status;
 177 } known_regs;
 178
 179 #define KRREG_X     (1 << SSP_X)
 180 #define KRREG_Y     (1 << SSP_Y)
 181 #define KRREG_A     (1 << SSP_A)        /* AH only */
 182 #define KRREG_ST    (1 << SSP_ST)
 183 #define KRREG_STACK (1 << SSP_STACK)
 184 #define KRREG_PC    (1 << SSP_PC)
 185 #define KRREG_P     (1 << SSP_P)
 186 #define KRREG_PR0   (1 << 8)
 187 #define KRREG_PR4   (1 << 12)
 188 #define KRREG_AL    (1 << 16)
 189 #define KRREG_PMCM  (1 << 18)           /* only mode word of PMC */
 190 #define KRREG_PMC   (1 << 19)
 191 #define KRREG_PM0R  (1 << 20)
 192 #define KRREG_PM1R  (1 << 21)
 193 #define KRREG_PM2R  (1 << 22)
 194 #define KRREG_PM3R  (1 << 23)
 195 #define KRREG_PM4R  (1 << 24)
 196 #define KRREG_PM0W  (1 << 25)
 197 #define KRREG_PM1W  (1 << 26)
 198 #define KRREG_PM2W  (1 << 27)
 199 #define KRREG_PM3W  (1 << 28)
 200 #define KRREG_PM4W  (1 << 29)
 201
 202 /* bitfield of known register values */
 203 static u32 known_regb = 0;
 204
 205 /* known vals, which need to be flushed
 206  * (only ST, P, r0-r7, PMCx, PMxR, PMxW)
 207  * ST means flags are being held in ARM PSR
 208  * P means that it needs to be recalculated
 209  */
 210 static u32 dirty_regb = 0;
 211
 212 /* known values of host regs.
 213  * -1            - unknown
 214  * 000000-00ffff - 16bit value
 215  * 100000-10ffff - base reg (r7) + 16bit val
 216  * 0r0000        - means reg (low) eq gr[r].h, r != AL
 217  */
 218 static int hostreg_r[4];
 219
 220 static void hostreg_clear(void)
 221 {
 222         int i;
 223         for (i = 0; i < 4; i++)
 224                 hostreg_r[i] = -1;
 225 }
 226
 227 static void hostreg_sspreg_changed(int sspreg)
 228 {
 229         int i;
 230         for (i = 0; i < 4; i++)
 231                 if (hostreg_r[i] == (sspreg<<16)) hostreg_r[i] = -1;
 232 }
 233
 234
 235 #define PROGRAM(x)   ((unsigned short *)svp->iram_rom)[x]
 236 #define PROGRAM_P(x) ((unsigned short *)svp->iram_rom + (x))
 237
 238 void tr_unhandled(void)
 239 {
 240         //FILE *f = fopen("tcache.bin", "wb");
 241         //fwrite(tcache, 1, (tcache_ptr - tcache)*4, f);
 242         //fclose(f);
 243         elprintf(EL_ANOMALY, "unhandled @ %04x\n", known_regs.gr[SSP_PC].h<<1);
 244         //exit(1);
 245 }
 246
 247 /* update P, if needed. Trashes r0 */
 248 static void tr_flush_dirty_P(void)
 249 {
 250         // TODO: const regs
 251         if (!(dirty_regb & KRREG_P)) return;
 252         EOP_MOV_REG_ASR(10, 4, 16);             // mov  r10, r4, asr #16
 253         EOP_MOV_REG_LSL( 0, 4, 16);             // mov  r0,  r4, lsl #16
 254         EOP_MOV_REG_ASR( 0, 0, 15);             // mov  r0,  r0, asr #15
 255         EOP_MUL(10, 0, 10);                     // mul  r10, r0, r10
 256         dirty_regb &= ~KRREG_P;
 257         hostreg_r[0] = -1;
 258 }
 259
 260 /* write dirty pr to host reg. Nothing is trashed */
 261 static void tr_flush_dirty_pr(int r)
 262 {
 263         int ror = 0, reg;
 264
 265         if (!(dirty_regb & (1 << (r+8)))) return;
 266
 267         switch (r&3) {
 268                 case 0: ror =    0; break;
 269                 case 1: ror = 24/2; break;
 270                 case 2: ror = 16/2; break;
 271         }
 272         reg = (r < 4) ? 8 : 9;
 273         EOP_BIC_IMM(reg,reg,ror,0xff);
 274         if (known_regs.r[r] != 0)
 275                 EOP_ORR_IMM(reg,reg,ror,known_regs.r[r]);
 276         dirty_regb &= ~(1 << (r+8));
 277 }
 278
 279 /* write all dirty pr0-pr7 to host regs. Nothing is trashed */
 280 static void tr_flush_dirty_prs(void)
 281 {
 282         int i, ror = 0, reg;
 283         int dirty = dirty_regb >> 8;
 284         if ((dirty&7) == 7) {
 285                 emit_mov_const(A_COND_AL, 8, known_regs.r[0]|(known_regs.r[1]<<8)|(known_regs.r[2]<<16));
 286                 dirty &= ~7;
 287         }
 288         if ((dirty&0x70) == 0x70) {
 289                 emit_mov_const(A_COND_AL, 9, known_regs.r[4]|(known_regs.r[5]<<8)|(known_regs.r[6]<<16));
 290                 dirty &= ~0x70;
 291         }
 292         /* r0-r7 */
 293         for (i = 0; dirty && i < 8; i++, dirty >>= 1)
 294         {
 295                 if (!(dirty&1)) continue;
 296                 switch (i&3) {
 297                         case 0: ror =    0; break;
 298                         case 1: ror = 24/2; break;
 299                         case 2: ror = 16/2; break;
 300                 }
 301                 reg = (i < 4) ? 8 : 9;
 302                 EOP_BIC_IMM(reg,reg,ror,0xff);
 303                 if (known_regs.r[i] != 0)
 304                         EOP_ORR_IMM(reg,reg,ror,known_regs.r[i]);
 305         }
 306         dirty_regb &= ~0xff00;
 307 }
 308
 309 /* write dirty pr and "forget" it. Nothing is trashed. */
 310 static void tr_release_pr(int r)
 311 {
 312         tr_flush_dirty_pr(r);
 313         known_regb &= ~(1 << (r+8));
 314 }
 315
 316 /* fush ARM PSR to r6. Trashes r1 */
 317 static void tr_flush_dirty_ST(void)
 318 {
 319         if (!(dirty_regb & KRREG_ST)) return;
 320         EOP_BIC_IMM(6,6,0,0x0f);
 321         EOP_MRS(1);
 322         EOP_ORR_REG_LSR(6,6,1,28);
 323         dirty_regb &= ~KRREG_ST;
 324         hostreg_r[1] = -1;
 325 }
 326
 327 /* inverse of above. Trashes r1 */
 328 static void tr_make_dirty_ST(void)
 329 {
 330         if (dirty_regb & KRREG_ST) return;
 331         if (known_regb & KRREG_ST) {
 332                 int flags = 0;
 333                 if (known_regs.gr[SSP_ST].h & SSP_FLAG_N) flags |= 8;
 334                 if (known_regs.gr[SSP_ST].h & SSP_FLAG_Z) flags |= 4;
 335                 EOP_MSR_IMM(4/2, flags);
 336         } else {
 337                 EOP_MOV_REG_LSL(1, 6, 28);
 338                 EOP_MSR_REG(1);
 339                 hostreg_r[1] = -1;
 340         }
 341         dirty_regb |= KRREG_ST;
 342 }
 343
 344 /* load 16bit val into host reg r0-r3. Nothing is trashed */
 345 static void tr_mov16(int r, int val)
 346 {
 347         if (hostreg_r[r] != val) {
 348                 emit_mov_const(A_COND_AL, r, val);
 349                 hostreg_r[r] = val;
 350         }
 351 }
 352
 353 static void tr_mov16_cond(int cond, int r, int val)
 354 {
 355         emit_mov_const(cond, r, val);
 356         hostreg_r[r] = -1;
 357 }
 358
 359 /* trashes r1 */
 360 static void tr_flush_dirty_pmcrs(void)
 361 {
 362         u32 i, val = (u32)-1;
 363         if (!(dirty_regb & 0x3ff80000)) return;
 364
 365         if (dirty_regb & KRREG_PMC) {
 366                 val = known_regs.pmc.v;
 367                 emit_mov_const(A_COND_AL, 1, val);
 368                 EOP_STR_IMM(1,7,0x400+SSP_PMC*4);
 369
 370                 if (known_regs.emu_status & (SSP_PMC_SET|SSP_PMC_HAVE_ADDR)) {
 371                         elprintf(EL_ANOMALY, "!! SSP_PMC_SET|SSP_PMC_HAVE_ADDR set on flush\n");
 372                         tr_unhandled();
 373                 }
 374         }
 375         for (i = 0; i < 5; i++)
 376         {
 377                 if (dirty_regb & (1 << (20+i))) {
 378                         if (val != known_regs.pmac_read[i]) {
 379                                 val = known_regs.pmac_read[i];
 380                                 emit_mov_const(A_COND_AL, 1, val);
 381                         }
 382                         EOP_STR_IMM(1,7,0x454+i*4); // pmac_read
 383                 }
 384                 if (dirty_regb & (1 << (25+i))) {
 385                         if (val != known_regs.pmac_write[i]) {
 386                                 val = known_regs.pmac_write[i];
 387                                 emit_mov_const(A_COND_AL, 1, val);
 388                         }
 389                         EOP_STR_IMM(1,7,0x46c+i*4); // pmac_write
 390                 }
 391         }
 392         dirty_regb &= ~0x3ff80000;
 393         hostreg_r[1] = -1;
 394 }
 395
 396 /* read bank word to r0 (upper bits zero). Thrashes r1. */
 397 static void tr_bank_read(int addr) /* word addr 0-0x1ff */
 398 {
 399         int breg = 7;
 400         if (addr > 0x7f) {
 401                 if (hostreg_r[1] != (0x100000|((addr&0x180)<<1))) {
 402                         EOP_ADD_IMM(1,7,30/2,(addr&0x180)>>1);  // add  r1, r7, ((op&0x180)<<1)
 403                         hostreg_r[1] = 0x100000|((addr&0x180)<<1);
 404                 }
 405                 breg = 1;
 406         }
 407         EOP_LDRH_IMM(0,breg,(addr&0x7f)<<1);    // ldrh r0, [r1, (op&0x7f)<<1]
 408         hostreg_r[0] = -1;
 409 }
 410
 411 /* write r0 to bank. Trashes r1. */
 412 static void tr_bank_write(int addr)
 413 {
 414         int breg = 7;
 415         if (addr > 0x7f) {
 416                 if (hostreg_r[1] != (0x100000|((addr&0x180)<<1))) {
 417                         EOP_ADD_IMM(1,7,30/2,(addr&0x180)>>1);  // add  r1, r7, ((op&0x180)<<1)
 418                         hostreg_r[1] = 0x100000|((addr&0x180)<<1);
 419                 }
 420                 breg = 1;
 421         }
 422         EOP_STRH_IMM(0,breg,(addr&0x7f)<<1);            // strh r0, [r1, (op&0x7f)<<1]
 423 }
 424
 425 /* handle RAM bank pointer modifiers. if need_modulo, trash r1-r3, else nothing */
 426 static void tr_ptrr_mod(int r, int mod, int need_modulo, int count)
 427 {
 428         int modulo_shift = -1;  /* unknown */
 429
 430         if (mod == 0) return;
 431
 432         if (!need_modulo || mod == 1) // +!
 433                 modulo_shift = 8;
 434         else if (need_modulo && (known_regb & KRREG_ST)) {
 435                 modulo_shift = known_regs.gr[SSP_ST].h & 7;
 436                 if (modulo_shift == 0) modulo_shift = 8;
 437         }
 438
 439         if (modulo_shift == -1)
 440         {
 441                 int reg = (r < 4) ? 8 : 9;
 442                 tr_release_pr(r);
 443                 if (dirty_regb & KRREG_ST) {
 444                         // avoid flushing ARM flags
 445                         EOP_AND_IMM(1, 6, 0, 0x70);
 446                         EOP_SUB_IMM(1, 1, 0, 0x10);
 447                         EOP_AND_IMM(1, 1, 0, 0x70);
 448                         EOP_ADD_IMM(1, 1, 0, 0x10);
 449                 } else {
 450                         EOP_C_DOP_IMM(A_COND_AL,A_OP_AND,1,6,1,0,0x70); // ands  r1, r6, #0x70
 451                         EOP_C_DOP_IMM(A_COND_EQ,A_OP_MOV,0,0,1,0,0x80); // moveq r1, #0x80
 452                 }
 453                 EOP_MOV_REG_LSR(1, 1, 4);               // mov r1, r1, lsr #4
 454                 EOP_RSB_IMM(2, 1, 0, 8);                // rsb r1, r1, #8
 455                 EOP_MOV_IMM(3, 8/2, count);             // mov r3, #0x01000000
 456                 if (r&3)
 457                         EOP_ADD_IMM(1, 1, 0, (r&3)*8);  // add r1, r1, #(r&3)*8
 458                 EOP_MOV_REG2_ROR(reg,reg,1);            // mov reg, reg, ror r1
 459                 if (mod == 2)
 460                      EOP_SUB_REG2_LSL(reg,reg,3,2);     // sub reg, reg, #0x01000000 << r2
 461                 else EOP_ADD_REG2_LSL(reg,reg,3,2);
 462                 EOP_RSB_IMM(1, 1, 0, 32);               // rsb r1, r1, #32
 463                 EOP_MOV_REG2_ROR(reg,reg,1);            // mov reg, reg, ror r1
 464                 hostreg_r[1] = hostreg_r[2] = hostreg_r[3] = -1;
 465         }
 466         else if (known_regb & (1 << (r + 8)))
 467         {
 468                 int modulo = (1 << modulo_shift) - 1;
 469                 if (mod == 2)
 470                      known_regs.r[r] = (known_regs.r[r] & ~modulo) | ((known_regs.r[r] - count) & modulo);
 471                 else known_regs.r[r] = (known_regs.r[r] & ~modulo) | ((known_regs.r[r] + count) & modulo);
 472         }
 473         else
 474         {
 475                 int reg = (r < 4) ? 8 : 9;
 476                 int ror = ((r&3) + 1)*8 - (8 - modulo_shift);
 477                 EOP_MOV_REG_ROR(reg,reg,ror);
 478                 // {add|sub} reg, reg, #1<<shift
 479                 EOP_C_DOP_IMM(A_COND_AL,(mod==2)?A_OP_SUB:A_OP_ADD,0,reg,reg, 8/2, count << (8 - modulo_shift));
 480                 EOP_MOV_REG_ROR(reg,reg,32-ror);
 481         }
 482 }
 483
 484 /* handle writes r0 to (rX). Trashes r1.
 485  * fortunately we can ignore modulo increment modes for writes. */
 486 static void tr_rX_write(int op)
 487 {
 488         if ((op&3) == 3)
 489         {
 490                 int mod = (op>>2) & 3; // direct addressing
 491                 tr_bank_write((op & 0x100) + mod);
 492         }
 493         else
 494         {
 495                 int r = (op&3) | ((op>>6)&4);
 496                 if (known_regb & (1 << (r + 8))) {
 497                         tr_bank_write((op&0x100) | known_regs.r[r]);
 498                 } else {
 499                         int reg = (r < 4) ? 8 : 9;
 500                         int ror = ((4 - (r&3))*8) & 0x1f;
 501                         EOP_AND_IMM(1,reg,ror/2,0xff);                  // and r1, r{7,8}, <mask>
 502                         if (r >= 4)
 503                                 EOP_ORR_IMM(1,1,((ror-8)&0x1f)/2,1);            // orr r1, r1, 1<<shift
 504                         if (r&3) EOP_ADD_REG_LSR(1,7,1, (r&3)*8-1);     // add r1, r7, r1, lsr #lsr
 505                         else     EOP_ADD_REG_LSL(1,7,1,1);
 506                         EOP_STRH_SIMPLE(0,1);                           // strh r0, [r1]
 507                         hostreg_r[1] = -1;
 508                 }
 509                 tr_ptrr_mod(r, (op>>2) & 3, 0, 1);
 510         }
 511 }
 512
 513 /* read (rX) to r0. Trashes r1-r3. */
 514 static void tr_rX_read(int r, int mod)
 515 {
 516         if ((r&3) == 3)
 517         {
 518                 tr_bank_read(((r << 6) & 0x100) + mod); // direct addressing
 519         }
 520         else
 521         {
 522                 if (known_regb & (1 << (r + 8))) {
 523                         tr_bank_read(((r << 6) & 0x100) | known_regs.r[r]);
 524                 } else {
 525                         int reg = (r < 4) ? 8 : 9;
 526                         int ror = ((4 - (r&3))*8) & 0x1f;
 527                         EOP_AND_IMM(1,reg,ror/2,0xff);                  // and r1, r{7,8}, <mask>
 528                         if (r >= 4)
 529                                 EOP_ORR_IMM(1,1,((ror-8)&0x1f)/2,1);            // orr r1, r1, 1<<shift
 530                         if (r&3) EOP_ADD_REG_LSR(1,7,1, (r&3)*8-1);     // add r1, r7, r1, lsr #lsr
 531                         else     EOP_ADD_REG_LSL(1,7,1,1);
 532                         EOP_LDRH_SIMPLE(0,1);                           // ldrh r0, [r1]
 533                         hostreg_r[0] = hostreg_r[1] = -1;
 534                 }
 535                 tr_ptrr_mod(r, mod, 1, 1);
 536         }
 537 }
 538
 539 /* read ((rX)) to r0. Trashes r1,r2. */
 540 static void tr_rX_read2(int op)
 541 {
 542         int r = (op&3) | ((op>>6)&4); // src
 543
 544         if ((r&3) == 3) {
 545                 tr_bank_read((op&0x100) | ((op>>2)&3));
 546         } else if (known_regb & (1 << (r+8))) {
 547                 tr_bank_read((op&0x100) | known_regs.r[r]);
 548         } else {
 549                 int reg = (r < 4) ? 8 : 9;
 550                 int ror = ((4 - (r&3))*8) & 0x1f;
 551                 EOP_AND_IMM(1,reg,ror/2,0xff);                  // and r1, r{7,8}, <mask>
 552                 if (r >= 4)
 553                         EOP_ORR_IMM(1,1,((ror-8)&0x1f)/2,1);            // orr r1, r1, 1<<shift
 554                 if (r&3) EOP_ADD_REG_LSR(1,7,1, (r&3)*8-1);     // add r1, r7, r1, lsr #lsr
 555                 else     EOP_ADD_REG_LSL(1,7,1,1);
 556                 EOP_LDRH_SIMPLE(0,1);                           // ldrh r0, [r1]
 557         }
 558         EOP_LDR_IMM(2,7,0x48c);                                 // ptr_iram_rom
 559         EOP_ADD_REG_LSL(2,2,0,1);                               // add  r2, r2, r0, lsl #1
 560         EOP_ADD_IMM(0,0,0,1);                                   // add  r0, r0, #1
 561         if ((r&3) == 3) {
 562                 tr_bank_write((op&0x100) | ((op>>2)&3));
 563         } else if (known_regb & (1 << (r+8))) {
 564                 tr_bank_write((op&0x100) | known_regs.r[r]);
 565         } else {
 566                 EOP_STRH_SIMPLE(0,1);                           // strh r0, [r1]
 567                 hostreg_r[1] = -1;
 568         }
 569         EOP_LDRH_SIMPLE(0,2);                                   // ldrh r0, [r2]
 570         hostreg_r[0] = hostreg_r[2] = -1;
 571 }
 572
 573 // check if AL is going to be used later in block
 574 static int tr_predict_al_need(void)
 575 {
 576         int tmpv, tmpv2, op, pc = known_regs.gr[SSP_PC].h;
 577
 578         while (1)
 579         {
 580                 op = PROGRAM(pc);
 581                 switch (op >> 9)
 582                 {
 583                         // ld d, s
 584                         case 0x00:
 585                                 tmpv2 = (op >> 4) & 0xf; // dst
 586                                 tmpv  = op & 0xf; // src
 587                                 if ((tmpv2 == SSP_A && tmpv == SSP_P) || tmpv2 == SSP_AL) // ld A, P; ld AL, *
 588                                         return 0;
 589                                 break;
 590
 591                         // ld (ri), s
 592                         case 0x02:
 593                         // ld ri, s
 594                         case 0x0a:
 595                         // OP a, s
 596                         case 0x10: case 0x30: case 0x40: case 0x60: case 0x70:
 597                                 tmpv  = op & 0xf; // src
 598                                 if (tmpv == SSP_AL) // OP *, AL
 599                                         return 1;
 600                                 break;
 601
 602                         case 0x04:
 603                         case 0x06:
 604                         case 0x14:
 605                         case 0x34:
 606                         case 0x44:
 607                         case 0x64:
 608                         case 0x74: pc++; break;
 609
 610                         // call cond, addr
 611                         case 0x24:
 612                         // bra cond, addr
 613                         case 0x26:
 614                         // mod cond, op
 615                         case 0x48:
 616                         // mpys?
 617                         case 0x1b:
 618                         // mpya (rj), (ri), b
 619                         case 0x4b: return 1;
 620
 621                         // mld (rj), (ri), b
 622                         case 0x5b: return 0; // cleared anyway
 623
 624                         // and A, *
 625                         case 0x50:
 626                                 tmpv  = op & 0xf; // src
 627                                 if (tmpv == SSP_AL) return 1;
 628                         case 0x51: case 0x53: case 0x54: case 0x55: case 0x59: case 0x5c:
 629                                 return 0;
 630                 }
 631                 pc++;
 632         }
 633 }
 634
 635
 636 /* get ARM cond which would mean that SSP cond is satisfied. No trash. */
 637 static int tr_cond_check(int op)
 638 {
 639         int f = (op & 0x100) >> 8;
 640         switch (op&0xf0) {
 641                 case 0x00: return A_COND_AL;    /* always true */
 642                 case 0x50:                      /* Z matches f(?) bit */
 643                         if (dirty_regb & KRREG_ST) return f ? A_COND_EQ : A_COND_NE;
 644                         EOP_TST_IMM(6, 0, 4);
 645                         return f ? A_COND_NE : A_COND_EQ;
 646                 case 0x70:                      /* N matches f(?) bit */
 647                         if (dirty_regb & KRREG_ST) return f ? A_COND_MI : A_COND_PL;
 648                         EOP_TST_IMM(6, 0, 8);
 649                         return f ? A_COND_NE : A_COND_EQ;
 650                 default:
 651                         elprintf(EL_ANOMALY, "unimplemented cond?\n");
 652                         tr_unhandled();
 653                         return 0;
 654         }
 655 }
 656
 657 static int tr_neg_cond(int cond)
 658 {
 659         switch (cond) {
 660                 case A_COND_AL: elprintf(EL_ANOMALY, "neg for AL?\n"); exit(1);
 661                 case A_COND_EQ: return A_COND_NE;
 662                 case A_COND_NE: return A_COND_EQ;
 663                 case A_COND_MI: return A_COND_PL;
 664                 case A_COND_PL: return A_COND_MI;
 665                 default:        elprintf(EL_ANOMALY, "bad cond for neg\n"); exit(1);
 666         }
 667         return 0;
 668 }
 669
 670 static int tr_aop_ssp2arm(int op)
 671 {
 672         switch (op) {
 673                 case 1: return A_OP_SUB;
 674                 case 3: return A_OP_CMP;
 675                 case 4: return A_OP_ADD;
 676                 case 5: return A_OP_AND;
 677                 case 6: return A_OP_ORR;
 678                 case 7: return A_OP_EOR;
 679         }
 680
 681         tr_unhandled();
 682         return 0;
 683 }
 684
 685 // -----------------------------------------------------
 686
 687 //@ r4:  XXYY
 688 //@ r5:  A
 689 //@ r6:  STACK and emu flags
 690 //@ r7:  SSP context
 691 //@ r10: P
 692
 693 // read general reg to r0. Trashes r1
 694 static void tr_GR0_to_r0(int op)
 695 {
 696         tr_mov16(0, 0xffff);
 697 }
 698
 699 static void tr_X_to_r0(int op)
 700 {
 701         if (hostreg_r[0] != (SSP_X<<16)) {
 702                 EOP_MOV_REG_LSR(0, 4, 16);      // mov  r0, r4, lsr #16
 703                 hostreg_r[0] = SSP_X<<16;
 704         }
 705 }
 706
 707 static void tr_Y_to_r0(int op)
 708 {
 709         if (hostreg_r[0] != (SSP_Y<<16)) {
 710                 EOP_MOV_REG_SIMPLE(0, 4);       // mov  r0, r4
 711                 hostreg_r[0] = SSP_Y<<16;
 712         }
 713 }
 714
 715 static void tr_A_to_r0(int op)
 716 {
 717         if (hostreg_r[0] != (SSP_A<<16)) {
 718                 EOP_MOV_REG_LSR(0, 5, 16);      // mov  r0, r5, lsr #16  @ AH
 719                 hostreg_r[0] = SSP_A<<16;
 720         }
 721 }
 722
 723 static void tr_ST_to_r0(int op)
 724 {
 725         // VR doesn't need much accuracy here..
 726         EOP_MOV_REG_LSR(0, 6, 4);               // mov  r0, r6, lsr #4
 727         EOP_AND_IMM(0, 0, 0, 0x67);             // and  r0, r0, #0x67
 728         hostreg_r[0] = -1;
 729 }
 730
 731 static void tr_STACK_to_r0(int op)
 732 {
 733         // 448
 734         EOP_SUB_IMM(6, 6,  8/2, 0x20);          // sub  r6, r6, #1<<29
 735         EOP_ADD_IMM(1, 7, 24/2, 0x04);          // add  r1, r7, 0x400
 736         EOP_ADD_IMM(1, 1, 0, 0x48);             // add  r1, r1, 0x048
 737         EOP_ADD_REG_LSR(1, 1, 6, 28);           // add  r1, r1, r6, lsr #28
 738         EOP_LDRH_SIMPLE(0, 1);                  // ldrh r0, [r1]
 739         hostreg_r[0] = hostreg_r[1] = -1;
 740 }
 741
 742 static void tr_PC_to_r0(int op)
 743 {
 744         tr_mov16(0, known_regs.gr[SSP_PC].h);
 745 }
 746
 747 static void tr_P_to_r0(int op)
 748 {
 749         tr_flush_dirty_P();
 750         EOP_MOV_REG_LSR(0, 10, 16);             // mov  r0, r10, lsr #16
 751         hostreg_r[0] = -1;
 752 }
 753
 754 static void tr_AL_to_r0(int op)
 755 {
 756         if (op == 0x000f) {
 757                 if (known_regb & KRREG_PMC) {
 758                         known_regs.emu_status &= ~(SSP_PMC_SET|SSP_PMC_HAVE_ADDR);
 759                 } else {
 760                         EOP_LDR_IMM(0,7,0x484);                 // ldr r1, [r7, #0x484] // emu_status
 761                         EOP_BIC_IMM(0,0,0,SSP_PMC_SET|SSP_PMC_HAVE_ADDR);
 762                         EOP_STR_IMM(0,7,0x484);
 763                 }
 764         }
 765
 766         if (hostreg_r[0] != (SSP_AL<<16)) {
 767                 EOP_MOV_REG_SIMPLE(0, 5);       // mov  r0, r5
 768                 hostreg_r[0] = SSP_AL<<16;
 769         }
 770 }
 771
 772 static void tr_PMX_to_r0(int reg)
 773 {
 774         if ((known_regb & KRREG_PMC) && (known_regs.emu_status & SSP_PMC_SET))
 775         {
 776                 known_regs.pmac_read[reg] = known_regs.pmc.v;
 777                 known_regs.emu_status &= ~SSP_PMC_SET;
 778                 known_regb |= 1 << (20+reg);
 779                 dirty_regb |= 1 << (20+reg);
 780                 return;
 781         }
 782
 783         if ((known_regb & KRREG_PMC) && (known_regb & (1 << (20+reg))))
 784         {
 785                 u32 pmcv = known_regs.pmac_read[reg];
 786                 int mode = pmcv>>16;
 787                 known_regs.emu_status &= ~SSP_PMC_HAVE_ADDR;
 788
 789                 if      ((mode & 0xfff0) == 0x0800)
 790                 {
 791                         EOP_LDR_IMM(1,7,0x488);         // rom_ptr
 792                         emit_mov_const(A_COND_AL, 0, (pmcv&0xfffff)<<1);
 793                         EOP_LDRH_REG(0,1,0);            // ldrh r0, [r1, r0]
 794                         known_regs.pmac_read[reg] += 1;
 795                 }
 796                 else if ((mode & 0x47ff) == 0x0018) // DRAM
 797                 {
 798                         int inc = get_inc(mode);
 799                         EOP_LDR_IMM(1,7,0x490);         // dram_ptr
 800                         emit_mov_const(A_COND_AL, 0, (pmcv&0xffff)<<1);
 801                         EOP_LDRH_REG(0,1,0);            // ldrh r0, [r1, r0]
 802                         if (reg == 4 && (pmcv == 0x187f03 || pmcv == 0x187f04)) // wait loop detection
 803                         {
 804                                 int flag = (pmcv == 0x187f03) ? SSP_WAIT_30FE06 : SSP_WAIT_30FE08;
 805                                 tr_flush_dirty_ST();
 806                                 EOP_LDR_IMM(1,7,0x484);                 // ldr r1, [r7, #0x484] // emu_status
 807                                 EOP_TST_REG_SIMPLE(0,0);
 808                                 EOP_C_DOP_IMM(A_COND_EQ,A_OP_SUB,0,11,11,22/2,1);       // subeq r11, r11, #1024
 809                                 EOP_C_DOP_IMM(A_COND_EQ,A_OP_ORR,0, 1, 1,24/2,flag>>8); // orreq r1, r1, #SSP_WAIT_30FE08
 810                                 EOP_STR_IMM(1,7,0x484);                 // str r1, [r7, #0x484] // emu_status
 811                         }
 812                         known_regs.pmac_read[reg] += inc;
 813                 }
 814                 else
 815                 {
 816                         tr_unhandled();
 817                 }
 818                 known_regs.pmc.v = known_regs.pmac_read[reg];
 819                 //known_regb |= KRREG_PMC;
 820                 dirty_regb |= KRREG_PMC;
 821                 dirty_regb |= 1 << (20+reg);
 822                 hostreg_r[0] = hostreg_r[1] = -1;
 823                 return;
 824         }
 825
 826         known_regb &= ~KRREG_PMC;
 827         dirty_regb &= ~KRREG_PMC;
 828         known_regb &= ~(1 << (20+reg));
 829         dirty_regb &= ~(1 << (20+reg));
 830
 831         // call the C code to handle this
 832         tr_flush_dirty_ST();
 833         //tr_flush_dirty_pmcrs();
 834         tr_mov16(0, reg);
 835         emit_call(A_COND_AL, ssp_pm_read);
 836         hostreg_clear();
 837 }
 838
 839 static void tr_PM0_to_r0(int op)
 840 {
 841         tr_PMX_to_r0(0);
 842 }
 843
 844 static void tr_PM1_to_r0(int op)
 845 {
 846         tr_PMX_to_r0(1);
 847 }
 848
 849 static void tr_PM2_to_r0(int op)
 850 {
 851         tr_PMX_to_r0(2);
 852 }
 853
 854 static void tr_XST_to_r0(int op)
 855 {
 856         EOP_ADD_IMM(0, 7, 24/2, 4);     // add r0, r7, #0x400
 857         EOP_LDRH_IMM(0, 0, SSP_XST*4+2);
 858 }
 859
 860 static void tr_PM4_to_r0(int op)
 861 {
 862         tr_PMX_to_r0(4);
 863 }
 864
 865 static void tr_PMC_to_r0(int op)
 866 {
 867         if (known_regb & KRREG_PMC)
 868         {
 869                 if (known_regs.emu_status & SSP_PMC_HAVE_ADDR) {
 870                         known_regs.emu_status |= SSP_PMC_SET;
 871                         known_regs.emu_status &= ~SSP_PMC_HAVE_ADDR;
 872                         // do nothing - this is handled elsewhere
 873                 } else {
 874                         tr_mov16(0, known_regs.pmc.l);
 875                         known_regs.emu_status |= SSP_PMC_HAVE_ADDR;
 876                 }
 877         }
 878         else
 879         {
 880                 EOP_LDR_IMM(1,7,0x484);                 // ldr r1, [r7, #0x484] // emu_status
 881                 tr_flush_dirty_ST();
 882                 if (op != 0x000e)
 883                         EOP_LDR_IMM(0, 7, 0x400+SSP_PMC*4);
 884                 EOP_TST_IMM(1, 0, SSP_PMC_HAVE_ADDR);
 885                 EOP_C_DOP_IMM(A_COND_EQ,A_OP_ORR,0, 1, 1, 0, SSP_PMC_HAVE_ADDR); // orreq r1, r1, #..
 886                 EOP_C_DOP_IMM(A_COND_NE,A_OP_BIC,0, 1, 1, 0, SSP_PMC_HAVE_ADDR); // bicne r1, r1, #..
 887                 EOP_C_DOP_IMM(A_COND_NE,A_OP_ORR,0, 1, 1, 0, SSP_PMC_SET);       // orrne r1, r1, #..
 888                 EOP_STR_IMM(1,7,0x484);
 889                 hostreg_r[0] = hostreg_r[1] = -1;
 890         }
 891 }
 892
 893
 894 typedef void (tr_read_func)(int op);
 895
 896 static tr_read_func *tr_read_funcs[16] =
 897 {
 898         tr_GR0_to_r0,
 899         tr_X_to_r0,
 900         tr_Y_to_r0,
 901         tr_A_to_r0,
 902         tr_ST_to_r0,
 903         tr_STACK_to_r0,
 904         tr_PC_to_r0,
 905         tr_P_to_r0,
 906         tr_PM0_to_r0,
 907         tr_PM1_to_r0,
 908         tr_PM2_to_r0,
 909         tr_XST_to_r0,
 910         tr_PM4_to_r0,
 911         (tr_read_func *)tr_unhandled,
 912         tr_PMC_to_r0,
 913         tr_AL_to_r0
 914 };
 915
 916
 917 // write r0 to general reg handlers. Trashes r1
 918 #define TR_WRITE_R0_TO_REG(reg) \
 919 { \
 920         hostreg_sspreg_changed(reg); \
 921         hostreg_r[0] = (reg)<<16; \
 922         if (const_val != -1) { \
 923                 known_regs.gr[reg].h = const_val; \
 924                 known_regb |= 1 << (reg); \
 925         } else { \
 926                 known_regb &= ~(1 << (reg)); \
 927         } \
 928 }
 929
 930 static void tr_r0_to_GR0(int const_val)
 931 {
 932         // do nothing
 933 }
 934
 935 static void tr_r0_to_X(int const_val)
 936 {
 937         EOP_MOV_REG_LSL(4, 4, 16);              // mov  r4, r4, lsl #16
 938         EOP_MOV_REG_LSR(4, 4, 16);              // mov  r4, r4, lsr #16
 939         EOP_ORR_REG_LSL(4, 4, 0, 16);           // orr  r4, r4, r0, lsl #16
 940         dirty_regb |= KRREG_P;                  // touching X or Y makes P dirty.
 941         TR_WRITE_R0_TO_REG(SSP_X);
 942 }
 943
 944 static void tr_r0_to_Y(int const_val)
 945 {
 946         EOP_MOV_REG_LSR(4, 4, 16);              // mov  r4, r4, lsr #16
 947         EOP_ORR_REG_LSL(4, 4, 0, 16);           // orr  r4, r4, r0, lsl #16
 948         EOP_MOV_REG_ROR(4, 4, 16);              // mov  r4, r4, ror #16
 949         dirty_regb |= KRREG_P;
 950         TR_WRITE_R0_TO_REG(SSP_Y);
 951 }
 952
 953 static void tr_r0_to_A(int const_val)
 954 {
 955         if (tr_predict_al_need()) {
 956                 EOP_MOV_REG_LSL(5, 5, 16);      // mov  r5, r5, lsl #16
 957                 EOP_MOV_REG_LSR(5, 5, 16);      // mov  r5, r5, lsr #16  @ AL
 958                 EOP_ORR_REG_LSL(5, 5, 0, 16);   // orr  r5, r5, r0, lsl #16
 959         }
 960         else
 961                 EOP_MOV_REG_LSL(5, 0, 16);
 962         TR_WRITE_R0_TO_REG(SSP_A);
 963 }
 964
 965 static void tr_r0_to_ST(int const_val)
 966 {
 967         // VR doesn't need much accuracy here..
 968         EOP_AND_IMM(1, 0,   0, 0x67);           // and   r1, r0, #0x67
 969         EOP_AND_IMM(6, 6, 8/2, 0xe0);           // and   r6, r6, #7<<29     @ preserve STACK
 970         EOP_ORR_REG_LSL(6, 6, 1, 4);            // orr   r6, r6, r1, lsl #4
 971         TR_WRITE_R0_TO_REG(SSP_ST);
 972         hostreg_r[1] = -1;
 973         dirty_regb &= ~KRREG_ST;
 974 }
 975
 976 static void tr_r0_to_STACK(int const_val)
 977 {
 978         // 448
 979         EOP_ADD_IMM(1, 7, 24/2, 0x04);          // add  r1, r7, 0x400
 980         EOP_ADD_IMM(1, 1, 0, 0x48);             // add  r1, r1, 0x048
 981         EOP_ADD_REG_LSR(1, 1, 6, 28);           // add  r1, r1, r6, lsr #28
 982         EOP_STRH_SIMPLE(0, 1);                  // strh r0, [r1]
 983         EOP_ADD_IMM(6, 6,  8/2, 0x20);          // add  r6, r6, #1<<29
 984         hostreg_r[1] = -1;
 985 }
 986
 987 static void tr_r0_to_PC(int const_val)
 988 {
 989 /*
 990  * do nothing - dispatcher will take care of this
 991         EOP_MOV_REG_LSL(1, 0, 16);              // mov  r1, r0, lsl #16
 992         EOP_STR_IMM(1,7,0x400+6*4);             // str  r1, [r7, #(0x400+6*8)]
 993         hostreg_r[1] = -1;
 994 */
 995 }
 996
 997 static void tr_r0_to_AL(int const_val)
 998 {
 999         EOP_MOV_REG_LSR(5, 5, 16);              // mov  r5, r5, lsr #16
1000         EOP_ORR_REG_LSL(5, 5, 0, 16);           // orr  r5, r5, r0, lsl #16
1001         EOP_MOV_REG_ROR(5, 5, 16);              // mov  r5, r5, ror #16
1002         hostreg_sspreg_changed(SSP_AL);
1003         if (const_val != -1) {
1004                 known_regs.gr[SSP_A].l = const_val;
1005                 known_regb |= 1 << SSP_AL;
1006         } else
1007                 known_regb &= ~(1 << SSP_AL);
1008 }
1009
1010 static void tr_r0_to_PMX(int reg)
1011 {
1012         if ((known_regb & KRREG_PMC) && (known_regs.emu_status & SSP_PMC_SET))
1013         {
1014                 known_regs.pmac_write[reg] = known_regs.pmc.v;
1015                 known_regs.emu_status &= ~SSP_PMC_SET;
1016                 known_regb |= 1 << (25+reg);
1017                 dirty_regb |= 1 << (25+reg);
1018                 return;
1019         }
1020
1021         if ((known_regb & KRREG_PMC) && (known_regb & (1 << (25+reg))))
1022         {
1023                 int mode, addr;
1024
1025                 known_regs.emu_status &= ~SSP_PMC_HAVE_ADDR;
1026
1027                 mode = known_regs.pmac_write[reg]>>16;
1028                 addr = known_regs.pmac_write[reg]&0xffff;
1029                 if      ((mode & 0x43ff) == 0x0018) // DRAM
1030                 {
1031                         int inc = get_inc(mode);
1032                         if (mode & 0x0400) tr_unhandled();
1033                         EOP_LDR_IMM(1,7,0x490);         // dram_ptr
1034                         emit_mov_const(A_COND_AL, 2, addr<<1);
1035                         EOP_STRH_REG(0,1,2);            // strh r0, [r1, r2]
1036                         known_regs.pmac_write[reg] += inc;
1037                 }
1038                 else if ((mode & 0xfbff) == 0x4018) // DRAM, cell inc
1039                 {
1040                         if (mode & 0x0400) tr_unhandled();
1041                         EOP_LDR_IMM(1,7,0x490);         // dram_ptr
1042                         emit_mov_const(A_COND_AL, 2, addr<<1);
1043                         EOP_STRH_REG(0,1,2);            // strh r0, [r1, r2]
1044                         known_regs.pmac_write[reg] += (addr&1) ? 31 : 1;
1045                 }
1046                 else if ((mode & 0x47ff) == 0x001c) // IRAM
1047                 {
1048                         int inc = get_inc(mode);
1049                         EOP_LDR_IMM(1,7,0x48c);         // iram_ptr
1050                         emit_mov_const(A_COND_AL, 2, (addr&0x3ff)<<1);
1051                         EOP_STRH_REG(0,1,2);            // strh r0, [r1, r2]
1052                         EOP_MOV_IMM(1,0,1);
1053                         EOP_STR_IMM(1,7,0x494);         // iram_dirty
1054                         known_regs.pmac_write[reg] += inc;
1055                 }
1056                 else
1057                         tr_unhandled();
1058
1059                 known_regs.pmc.v = known_regs.pmac_write[reg];
1060                 //known_regb |= KRREG_PMC;
1061                 dirty_regb |= KRREG_PMC;
1062                 dirty_regb |= 1 << (25+reg);
1063                 hostreg_r[1] = hostreg_r[2] = -1;
1064                 return;
1065         }
1066
1067         known_regb &= ~KRREG_PMC;
1068         dirty_regb &= ~KRREG_PMC;
1069         known_regb &= ~(1 << (25+reg));
1070         dirty_regb &= ~(1 << (25+reg));
1071
1072         // call the C code to handle this
1073         tr_flush_dirty_ST();
1074         //tr_flush_dirty_pmcrs();
1075         tr_mov16(1, reg);
1076         emit_call(A_COND_AL, ssp_pm_write);
1077         hostreg_clear();
1078 }
1079
1080 static void tr_r0_to_PM0(int const_val)
1081 {
1082         tr_r0_to_PMX(0);
1083 }
1084
1085 static void tr_r0_to_PM1(int const_val)
1086 {
1087         tr_r0_to_PMX(1);
1088 }
1089
1090 static void tr_r0_to_PM2(int const_val)
1091 {
1092         tr_r0_to_PMX(2);
1093 }
1094
1095 static void tr_r0_to_PM4(int const_val)
1096 {
1097         tr_r0_to_PMX(4);
1098 }
1099
1100 static void tr_r0_to_PMC(int const_val)
1101 {
1102         if ((known_regb & KRREG_PMC) && const_val != -1)
1103         {
1104                 if (known_regs.emu_status & SSP_PMC_HAVE_ADDR) {
1105                         known_regs.emu_status |= SSP_PMC_SET;
1106                         known_regs.emu_status &= ~SSP_PMC_HAVE_ADDR;
1107                         known_regs.pmc.h = const_val;
1108                 } else {
1109                         known_regs.emu_status |= SSP_PMC_HAVE_ADDR;
1110                         known_regs.pmc.l = const_val;
1111                 }
1112         }
1113         else
1114         {
1115                 tr_flush_dirty_ST();
1116                 if (known_regb & KRREG_PMC) {
1117                         emit_mov_const(A_COND_AL, 1, known_regs.pmc.v);
1118                         EOP_STR_IMM(1,7,0x400+SSP_PMC*4);
1119                         known_regb &= ~KRREG_PMC;
1120                         dirty_regb &= ~KRREG_PMC;
1121                 }
1122                 EOP_LDR_IMM(1,7,0x484);                 // ldr r1, [r7, #0x484] // emu_status
1123                 EOP_ADD_IMM(2,7,24/2,4);                // add r2, r7, #0x400
1124                 EOP_TST_IMM(1, 0, SSP_PMC_HAVE_ADDR);
1125                 EOP_C_AM3_IMM(A_COND_EQ,1,0,2,0,0,1,SSP_PMC*4);         // strxx r0, [r2, #SSP_PMC]
1126                 EOP_C_AM3_IMM(A_COND_NE,1,0,2,0,0,1,SSP_PMC*4+2);
1127                 EOP_C_DOP_IMM(A_COND_EQ,A_OP_ORR,0, 1, 1, 0, SSP_PMC_HAVE_ADDR); // orreq r1, r1, #..
1128                 EOP_C_DOP_IMM(A_COND_NE,A_OP_BIC,0, 1, 1, 0, SSP_PMC_HAVE_ADDR); // bicne r1, r1, #..
1129                 EOP_C_DOP_IMM(A_COND_NE,A_OP_ORR,0, 1, 1, 0, SSP_PMC_SET);       // orrne r1, r1, #..
1130                 EOP_STR_IMM(1,7,0x484);
1131                 hostreg_r[1] = hostreg_r[2] = -1;
1132         }
1133 }
1134
1135 typedef void (tr_write_func)(int const_val);
1136
1137 static tr_write_func *tr_write_funcs[16] =
1138 {
1139         tr_r0_to_GR0,
1140         tr_r0_to_X,
1141         tr_r0_to_Y,
1142         tr_r0_to_A,
1143         tr_r0_to_ST,
1144         tr_r0_to_STACK,
1145         tr_r0_to_PC,
1146         (tr_write_func *)tr_unhandled,
1147         tr_r0_to_PM0,
1148         tr_r0_to_PM1,
1149         tr_r0_to_PM2,
1150         (tr_write_func *)tr_unhandled,
1151         tr_r0_to_PM4,
1152         (tr_write_func *)tr_unhandled,
1153         tr_r0_to_PMC,
1154         tr_r0_to_AL
1155 };
1156
1157 static void tr_mac_load_XY(int op)
1158 {
1159         tr_rX_read(op&3, (op>>2)&3); // X
1160         EOP_MOV_REG_LSL(4, 0, 16);
1161         tr_rX_read(((op>>4)&3)|4, (op>>6)&3); // Y
1162         EOP_ORR_REG_SIMPLE(4, 0);
1163         dirty_regb |= KRREG_P;
1164         hostreg_sspreg_changed(SSP_X);
1165         hostreg_sspreg_changed(SSP_Y);
1166         known_regb &= ~KRREG_X;
1167         known_regb &= ~KRREG_Y;
1168 }
1169
1170 // -----------------------------------------------------
1171
1172 static int tr_detect_set_pm(unsigned int op, int *pc, int imm)
1173 {
1174         u32 pmcv, tmpv;
1175         if (!((op&0xfef0) == 0x08e0 && (PROGRAM(*pc)&0xfef0) == 0x08e0)) return 0;
1176
1177         // programming PMC:
1178         // ldi PMC, imm1
1179         // ldi PMC, imm2
1180         (*pc)++;
1181         pmcv = imm | (PROGRAM((*pc)++) << 16);
1182         known_regs.pmc.v = pmcv;
1183         known_regb |= KRREG_PMC;
1184         dirty_regb |= KRREG_PMC;
1185         known_regs.emu_status |= SSP_PMC_SET;
1186         n_in_ops++;
1187
1188         // check for possible reg programming
1189         tmpv = PROGRAM(*pc);
1190         if ((tmpv & 0xfff8) == 0x08 || (tmpv & 0xff8f) == 0x80)
1191         {
1192                 int is_write = (tmpv & 0xff8f) == 0x80;
1193                 int reg = is_write ? ((tmpv>>4)&0x7) : (tmpv&0x7);
1194                 if (reg > 4) tr_unhandled();
1195                 if ((tmpv & 0x0f) != 0 && (tmpv & 0xf0) != 0) tr_unhandled();
1196                 known_regs.pmac_read[is_write ? reg + 5 : reg] = pmcv;
1197                 known_regb |= is_write ? (1 << (reg+25)) : (1 << (reg+20));
1198                 dirty_regb |= is_write ? (1 << (reg+25)) : (1 << (reg+20));
1199                 known_regs.emu_status &= ~SSP_PMC_SET;
1200                 (*pc)++;
1201                 n_in_ops++;
1202                 return 5;
1203         }
1204
1205         tr_unhandled();
1206         return 4;
1207 }
1208
1209 static const short pm0_block_seq[] = { 0x0880, 0, 0x0880, 0, 0x0840, 0x60 };
1210
1211 static int tr_detect_pm0_block(unsigned int op, int *pc, int imm)
1212 {
1213         // ldi ST, 0
1214         // ldi PM0, 0
1215         // ldi PM0, 0
1216         // ldi ST, 60h
1217         unsigned short *pp;
1218         if (op != 0x0840 || imm != 0) return 0;
1219         pp = PROGRAM_P(*pc);
1220         if (memcmp(pp, pm0_block_seq, sizeof(pm0_block_seq)) != 0) return 0;
1221
1222         EOP_AND_IMM(6, 6, 8/2, 0xe0);           // and   r6, r6, #7<<29     @ preserve STACK
1223         EOP_ORR_IMM(6, 6, 24/2, 6);             // orr   r6, r6, 0x600
1224         hostreg_sspreg_changed(SSP_ST);
1225         known_regs.gr[SSP_ST].h = 0x60;
1226         known_regb |= 1 << SSP_ST;
1227         dirty_regb &= ~KRREG_ST;
1228         (*pc) += 3*2;
1229         n_in_ops += 3;
1230         return 4*2;
1231 }
1232
1233 static int tr_detect_rotate(unsigned int op, int *pc, int imm)
1234 {
1235         // @ 3DA2 and 426A
1236         // ld PMC, (r3|00)
1237         // ld (r3|00), PMC
1238         // ld -, AL
1239         if (op != 0x02e3 || PROGRAM(*pc) != 0x04e3 || PROGRAM(*pc + 1) != 0x000f) return 0;
1240
1241         tr_bank_read(0);
1242         EOP_MOV_REG_LSL(0, 0, 4);
1243         EOP_ORR_REG_LSR(0, 0, 0, 16);
1244         tr_bank_write(0);
1245         (*pc) += 2;
1246         n_in_ops += 2;
1247         return 3;
1248 }
1249
1250 // -----------------------------------------------------
1251
1252 static int translate_op(unsigned int op, int *pc, int imm, int *end_cond, int *jump_pc)
1253 {
1254         u32 tmpv, tmpv2, tmpv3;
1255         int ret = 0;
1256         known_regs.gr[SSP_PC].h = *pc;
1257
1258         switch (op >> 9)
1259         {
1260                 // ld d, s
1261                 case 0x00:
1262                         if (op == 0) { ret++; break; } // nop
1263                         tmpv  = op & 0xf; // src
1264                         tmpv2 = (op >> 4) & 0xf; // dst
1265                         if (tmpv2 == SSP_A && tmpv == SSP_P) { // ld A, P
1266                                 tr_flush_dirty_P();
1267                                 EOP_MOV_REG_SIMPLE(5, 10);
1268                                 hostreg_sspreg_changed(SSP_A);
1269                                 known_regb &= ~(KRREG_A|KRREG_AL);
1270                                 ret++; break;
1271                         }
1272                         tr_read_funcs[tmpv](op);
1273                         tr_write_funcs[tmpv2]((known_regb & (1 << tmpv)) ? known_regs.gr[tmpv].h : -1);
1274                         if (tmpv2 == SSP_PC) {
1275                                 ret |= 0x10000;
1276                                 *end_cond = -A_COND_AL;
1277                         }
1278                         ret++; break;
1279
1280                 // ld d, (ri)
1281                 case 0x01: {
1282                         int r = (op&3) | ((op>>6)&4);
1283                         int mod = (op>>2)&3;
1284                         tmpv = (op >> 4) & 0xf; // dst
1285                         ret = tr_detect_rotate(op, pc, imm);
1286                         if (ret > 0) break;
1287                         if (tmpv != 0)
1288                                 tr_rX_read(r, mod);
1289                         else {
1290                                 int cnt = 1;
1291                                 while (PROGRAM(*pc) == op) {
1292                                         (*pc)++; cnt++; ret++;
1293                                         n_in_ops++;
1294                                 }
1295                                 tr_ptrr_mod(r, mod, 1, cnt); // skip
1296                         }
1297                         tr_write_funcs[tmpv](-1);
1298                         if (tmpv == SSP_PC) {
1299                                 ret |= 0x10000;
1300                                 *end_cond = -A_COND_AL;
1301                         }
1302                         ret++; break;
1303                 }
1304
1305                 // ld (ri), s
1306                 case 0x02:
1307                         tmpv = (op >> 4) & 0xf; // src
1308                         tr_read_funcs[tmpv](op);
1309                         tr_rX_write(op);
1310                         ret++; break;
1311
1312                 // ld a, adr
1313                 case 0x03:
1314                         tr_bank_read(op&0x1ff);
1315                         tr_r0_to_A(-1);
1316                         ret++; break;
1317
1318                 // ldi d, imm
1319                 case 0x04:
1320                         tmpv = (op & 0xf0) >> 4; // dst
1321                         ret = tr_detect_pm0_block(op, pc, imm);
1322                         if (ret > 0) break;
1323                         ret = tr_detect_set_pm(op, pc, imm);
1324                         if (ret > 0) break;
1325                         tr_mov16(0, imm);
1326                         tr_write_funcs[tmpv](imm);
1327                         if (tmpv == SSP_PC) {
1328                                 ret |= 0x10000;
1329                                 *jump_pc = imm;
1330                         }
1331                         ret += 2; break;
1332
1333                 // ld d, ((ri))
1334                 case 0x05:
1335                         tmpv2 = (op >> 4) & 0xf;  // dst
1336                         tr_rX_read2(op);
1337                         tr_write_funcs[tmpv2](-1);
1338                         if (tmpv2 == SSP_PC) {
1339                                 ret |= 0x10000;
1340                                 *end_cond = -A_COND_AL;
1341                         }
1342                         ret += 3; break;
1343
1344                 // ldi (ri), imm
1345                 case 0x06:
1346                         tr_mov16(0, imm);
1347                         tr_rX_write(op);
1348                         ret += 2; break;
1349
1350                 // ld adr, a
1351                 case 0x07:
1352                         tr_A_to_r0(op);
1353                         tr_bank_write(op&0x1ff);
1354                         ret++; break;
1355
1356                 // ld d, ri
1357                 case 0x09: {
1358                         int r;
1359                         r = (op&3) | ((op>>6)&4); // src
1360                         tmpv2 = (op >> 4) & 0xf;  // dst
1361                         if ((r&3) == 3) tr_unhandled();
1362
1363                         if (known_regb & (1 << (r+8))) {
1364                                 tr_mov16(0, known_regs.r[r]);
1365                                 tr_write_funcs[tmpv2](known_regs.r[r]);
1366                         } else {
1367                                 int reg = (r < 4) ? 8 : 9;
1368                                 if (r&3) EOP_MOV_REG_LSR(0, reg, (r&3)*8);      // mov r0, r{7,8}, lsr #lsr
1369                                 EOP_AND_IMM(0, (r&3)?0:reg, 0, 0xff);           // and r0, r{7,8}, <mask>
1370                                 hostreg_r[0] = -1;
1371                                 tr_write_funcs[tmpv2](-1);
1372                         }
1373                         ret++; break;
1374                 }
1375
1376                 // ld ri, s
1377                 case 0x0a: {
1378                         int r;
1379                         r = (op&3) | ((op>>6)&4); // dst
1380                         tmpv = (op >> 4) & 0xf;   // src
1381                         if ((r&3) == 3) tr_unhandled();
1382
1383                         if (known_regb & (1 << tmpv)) {
1384                                 known_regs.r[r] = known_regs.gr[tmpv].h;
1385                                 known_regb |= 1 << (r + 8);
1386                                 dirty_regb |= 1 << (r + 8);
1387                         } else {
1388                                 int reg = (r < 4) ? 8 : 9;
1389                                 int ror = ((4 - (r&3))*8) & 0x1f;
1390                                 tr_read_funcs[tmpv](op);
1391                                 EOP_BIC_IMM(reg, reg, ror/2, 0xff);             // bic r{7,8}, r{7,8}, <mask>
1392                                 EOP_AND_IMM(0, 0, 0, 0xff);                     // and r0, r0, 0xff
1393                                 EOP_ORR_REG_LSL(reg, reg, 0, (r&3)*8);          // orr r{7,8}, r{7,8}, r0, lsl #lsl
1394                                 hostreg_r[0] = -1;
1395                                 known_regb &= ~(1 << (r+8));
1396                                 dirty_regb &= ~(1 << (r+8));
1397                         }
1398                         ret++; break;
1399                 }
1400
1401                 // ldi ri, simm
1402                 case 0x0c: case 0x0d: case 0x0e: case 0x0f:
1403                         tmpv = (op>>8)&7;
1404                         known_regs.r[tmpv] = op;
1405                         known_regb |= 1 << (tmpv + 8);
1406                         dirty_regb |= 1 << (tmpv + 8);
1407                         ret++; break;
1408
1409                 // call cond, addr
1410                 case 0x24: {
1411                         u32 *jump_op = NULL;
1412                         tmpv = tr_cond_check(op);
1413                         if (tmpv != A_COND_AL) {
1414                                 jump_op = tcache_ptr;
1415                                 EOP_MOV_IMM(0, 0, 0); // placeholder for branch
1416                         }
1417                         tr_mov16(0, *pc);
1418                         tr_r0_to_STACK(*pc);
1419                         if (tmpv != A_COND_AL) {
1420                                 u32 *real_ptr = tcache_ptr;
1421                                 tcache_ptr = jump_op;
1422                                 EOP_C_B(tr_neg_cond(tmpv),0,real_ptr - jump_op - 2);
1423                                 tcache_ptr = real_ptr;
1424                         }
1425                         tr_mov16_cond(tmpv, 0, imm);
1426                         if (tmpv != A_COND_AL)
1427                                 tr_mov16_cond(tr_neg_cond(tmpv), 0, *pc);
1428                         tr_r0_to_PC(tmpv == A_COND_AL ? imm : -1);
1429                         ret |= 0x10000;
1430                         *end_cond = tmpv;
1431                         *jump_pc = imm;
1432                         ret += 2; break;
1433                 }
1434
1435                 // ld d, (a)
1436                 case 0x25:
1437                         tmpv2 = (op >> 4) & 0xf;  // dst
1438                         tr_A_to_r0(op);
1439                         EOP_LDR_IMM(1,7,0x48c);                                 // ptr_iram_rom
1440                         EOP_ADD_REG_LSL(0,1,0,1);                               // add  r0, r1, r0, lsl #1
1441                         EOP_LDRH_SIMPLE(0,0);                                   // ldrh r0, [r0]
1442                         hostreg_r[0] = hostreg_r[1] = -1;
1443                         tr_write_funcs[tmpv2](-1);
1444                         if (tmpv2 == SSP_PC) {
1445                                 ret |= 0x10000;
1446                                 *end_cond = -A_COND_AL;
1447                         }
1448                         ret += 3; break;
1449
1450                 // bra cond, addr
1451                 case 0x26:
1452                         tmpv = tr_cond_check(op);
1453                         tr_mov16_cond(tmpv, 0, imm);
1454                         if (tmpv != A_COND_AL)
1455                                 tr_mov16_cond(tr_neg_cond(tmpv), 0, *pc);
1456                         tr_r0_to_PC(tmpv == A_COND_AL ? imm : -1);
1457                         ret |= 0x10000;
1458                         *end_cond = tmpv;
1459                         *jump_pc = imm;
1460                         ret += 2; break;
1461
1462                 // mod cond, op
1463                 case 0x48: {
1464                         // check for repeats of this op
1465                         tmpv = 1; // count
1466                         while (PROGRAM(*pc) == op && (op & 7) != 6) {
1467                                 (*pc)++; tmpv++;
1468                                 n_in_ops++;
1469                         }
1470                         if ((op&0xf0) != 0) // !always
1471                                 tr_make_dirty_ST();
1472
1473                         tmpv2 = tr_cond_check(op);
1474                         switch (op & 7) {
1475                                 case 2: EOP_C_DOP_REG_XIMM(tmpv2,A_OP_MOV,1,0,5,tmpv,A_AM1_ASR,5); break; // shr (arithmetic)
1476                                 case 3: EOP_C_DOP_REG_XIMM(tmpv2,A_OP_MOV,1,0,5,tmpv,A_AM1_LSL,5); break; // shl
1477                                 case 6: EOP_C_DOP_IMM(tmpv2,A_OP_RSB,1,5,5,0,0); break; // neg
1478                                 case 7: EOP_C_DOP_REG_XIMM(tmpv2,A_OP_EOR,0,5,1,31,A_AM1_ASR,5); // eor  r1, r5, r5, asr #31
1479                                         EOP_C_DOP_REG_XIMM(tmpv2,A_OP_ADD,1,1,5,31,A_AM1_LSR,5); // adds r5, r1, r5, lsr #31
1480                                         hostreg_r[1] = -1; break; // abs
1481                                 default: tr_unhandled();
1482                         }
1483
1484                         hostreg_sspreg_changed(SSP_A);
1485                         dirty_regb |=  KRREG_ST;
1486                         known_regb &= ~KRREG_ST;
1487                         known_regb &= ~(KRREG_A|KRREG_AL);
1488                         ret += tmpv; break;
1489                 }
1490
1491                 // mpys?
1492                 case 0x1b:
1493                         tr_flush_dirty_P();
1494                         tr_mac_load_XY(op);
1495                         tr_make_dirty_ST();
1496                         EOP_C_DOP_REG_XIMM(A_COND_AL,A_OP_SUB,1,5,5,0,A_AM1_LSL,10); // subs r5, r5, r10
1497                         hostreg_sspreg_changed(SSP_A);
1498                         known_regb &= ~(KRREG_A|KRREG_AL);
1499                         dirty_regb |= KRREG_ST;
1500                         ret++; break;
1501
1502                 // mpya (rj), (ri), b
1503                 case 0x4b:
1504                         tr_flush_dirty_P();
1505                         tr_mac_load_XY(op);
1506                         tr_make_dirty_ST();
1507                         EOP_C_DOP_REG_XIMM(A_COND_AL,A_OP_ADD,1,5,5,0,A_AM1_LSL,10); // adds r5, r5, r10
1508                         hostreg_sspreg_changed(SSP_A);
1509                         known_regb &= ~(KRREG_A|KRREG_AL);
1510                         dirty_regb |= KRREG_ST;
1511                         ret++; break;
1512
1513                 // mld (rj), (ri), b
1514                 case 0x5b:
1515                         EOP_C_DOP_IMM(A_COND_AL,A_OP_MOV,1,0,5,0,0); // movs r5, #0
1516                         hostreg_sspreg_changed(SSP_A);
1517                         known_regs.gr[SSP_A].v = 0;
1518                         known_regb |= (KRREG_A|KRREG_AL);
1519                         dirty_regb |= KRREG_ST;
1520                         tr_mac_load_XY(op);
1521                         ret++; break;
1522
1523                 // OP a, s
1524                 case 0x10:
1525                 case 0x30:
1526                 case 0x40:
1527                 case 0x50:
1528                 case 0x60:
1529                 case 0x70:
1530                         tmpv = op & 0xf; // src
1531                         tmpv2 = tr_aop_ssp2arm(op>>13); // op
1532                         tmpv3 = (tmpv2 == A_OP_CMP) ? 0 : 5;
1533                         if (tmpv == SSP_P) {
1534                                 tr_flush_dirty_P();
1535                                 EOP_C_DOP_REG_XIMM(A_COND_AL,tmpv2,1,5,tmpv3, 0,A_AM1_LSL,10); // OPs r5, r5, r10
1536                         } else if (tmpv == SSP_A) {
1537                                 EOP_C_DOP_REG_XIMM(A_COND_AL,tmpv2,1,5,tmpv3, 0,A_AM1_LSL, 5); // OPs r5, r5, r5
1538                         } else {
1539                                 tr_read_funcs[tmpv](op);
1540                                 EOP_C_DOP_REG_XIMM(A_COND_AL,tmpv2,1,5,tmpv3,16,A_AM1_LSL, 0); // OPs r5, r5, r0, lsl #16
1541                         }
1542                         hostreg_sspreg_changed(SSP_A);
1543                         known_regb &= ~(KRREG_A|KRREG_AL|KRREG_ST);
1544                         dirty_regb |= KRREG_ST;
1545                         ret++; break;
1546
1547                 // OP a, (ri)
1548                 case 0x11:
1549                 case 0x31:
1550                 case 0x41:
1551                 case 0x51:
1552                 case 0x61:
1553                 case 0x71:
1554                         tmpv2 = tr_aop_ssp2arm(op>>13); // op
1555                         tmpv3 = (tmpv2 == A_OP_CMP) ? 0 : 5;
1556                         tr_rX_read((op&3)|((op>>6)&4), (op>>2)&3);
1557                         EOP_C_DOP_REG_XIMM(A_COND_AL,tmpv2,1,5,tmpv3,16,A_AM1_LSL,0);   // OPs r5, r5, r0, lsl #16
1558                         hostreg_sspreg_changed(SSP_A);
1559                         known_regb &= ~(KRREG_A|KRREG_AL|KRREG_ST);
1560                         dirty_regb |= KRREG_ST;
1561                         ret++; break;
1562
1563                 // OP a, adr
1564                 case 0x13:
1565                 case 0x33:
1566                 case 0x43:
1567                 case 0x53:
1568                 case 0x63:
1569                 case 0x73:
1570                         tmpv2 = tr_aop_ssp2arm(op>>13); // op
1571                         tmpv3 = (tmpv2 == A_OP_CMP) ? 0 : 5;
1572                         tr_bank_read(op&0x1ff);
1573                         EOP_C_DOP_REG_XIMM(A_COND_AL,tmpv2,1,5,tmpv3,16,A_AM1_LSL,0);   // OPs r5, r5, r0, lsl #16
1574                         hostreg_sspreg_changed(SSP_A);
1575                         known_regb &= ~(KRREG_A|KRREG_AL|KRREG_ST);
1576                         dirty_regb |= KRREG_ST;
1577                         ret++; break;
1578
1579                 // OP a, imm
1580                 case 0x14:
1581                 case 0x34:
1582                 case 0x44:
1583                 case 0x54:
1584                 case 0x64:
1585                 case 0x74:
1586                         tmpv = (op & 0xf0) >> 4;
1587                         tmpv2 = tr_aop_ssp2arm(op>>13); // op
1588                         tmpv3 = (tmpv2 == A_OP_CMP) ? 0 : 5;
1589                         tr_mov16(0, imm);
1590                         EOP_C_DOP_REG_XIMM(A_COND_AL,tmpv2,1,5,tmpv3,16,A_AM1_LSL,0);   // OPs r5, r5, r0, lsl #16
1591                         hostreg_sspreg_changed(SSP_A);
1592                         known_regb &= ~(KRREG_A|KRREG_AL|KRREG_ST);
1593                         dirty_regb |= KRREG_ST;
1594                         ret += 2; break;
1595
1596                 // OP a, ((ri))
1597                 case 0x15:
1598                 case 0x35:
1599                 case 0x45:
1600                 case 0x55:
1601                 case 0x65:
1602                 case 0x75:
1603                         tmpv2 = tr_aop_ssp2arm(op>>13); // op
1604                         tmpv3 = (tmpv2 == A_OP_CMP) ? 0 : 5;
1605                         tr_rX_read2(op);
1606                         EOP_C_DOP_REG_XIMM(A_COND_AL,tmpv2,1,5,tmpv3,16,A_AM1_LSL,0);   // OPs r5, r5, r0, lsl #16
1607                         hostreg_sspreg_changed(SSP_A);
1608                         known_regb &= ~(KRREG_A|KRREG_AL|KRREG_ST);
1609                         dirty_regb |= KRREG_ST;
1610                         ret += 3; break;
1611
1612                 // OP a, ri
1613                 case 0x19:
1614                 case 0x39:
1615                 case 0x49:
1616                 case 0x59:
1617                 case 0x69:
1618                 case 0x79: {
1619                         int r;
1620                         tmpv2 = tr_aop_ssp2arm(op>>13); // op
1621                         tmpv3 = (tmpv2 == A_OP_CMP) ? 0 : 5;
1622                         r = (op&3) | ((op>>6)&4); // src
1623                         if ((r&3) == 3) tr_unhandled();
1624
1625                         if (known_regb & (1 << (r+8))) {
1626                                 EOP_C_DOP_IMM(A_COND_AL,tmpv2,1,5,tmpv3,16/2,known_regs.r[r]);  // OPs r5, r5, #val<<16
1627                         } else {
1628                                 int reg = (r < 4) ? 8 : 9;
1629                                 if (r&3) EOP_MOV_REG_LSR(0, reg, (r&3)*8);      // mov r0, r{7,8}, lsr #lsr
1630                                 EOP_AND_IMM(0, (r&3)?0:reg, 0, 0xff);           // and r0, r{7,8}, <mask>
1631                                 EOP_C_DOP_REG_XIMM(A_COND_AL,tmpv2,1,5,tmpv3,16,A_AM1_LSL,0);   // OPs r5, r5, r0, lsl #16
1632                                 hostreg_r[0] = -1;
1633                         }
1634                         hostreg_sspreg_changed(SSP_A);
1635                         known_regb &= ~(KRREG_A|KRREG_AL|KRREG_ST);
1636                         dirty_regb |= KRREG_ST;
1637                         ret++; break;
1638                 }
1639
1640                 // OP simm
1641                 case 0x1c:
1642                 case 0x3c:
1643                 case 0x4c:
1644                 case 0x5c:
1645                 case 0x6c:
1646                 case 0x7c:
1647                         tmpv2 = tr_aop_ssp2arm(op>>13); // op
1648                         tmpv3 = (tmpv2 == A_OP_CMP) ? 0 : 5;
1649                         EOP_C_DOP_IMM(A_COND_AL,tmpv2,1,5,tmpv3,16/2,op & 0xff);        // OPs r5, r5, #val<<16
1650                         hostreg_sspreg_changed(SSP_A);
1651                         known_regb &= ~(KRREG_A|KRREG_AL|KRREG_ST);
1652                         dirty_regb |= KRREG_ST;
1653                         ret++; break;
1654         }
1655
1656         n_in_ops++;
1657
1658         return ret;
1659 }
1660
1661 static void emit_block_prologue(void)
1662 {
1663         // check if there are enough cycles..
1664         // note: r0 must contain PC of current block
1665         EOP_CMP_IMM(11,0,0);                    // cmp r11, #0
1666         emit_jump(A_COND_LE, ssp_drc_end);
1667 }
1668
1669 /* cond:
1670  * >0: direct (un)conditional jump
1671  * <0: indirect jump
1672  */
1673 static void emit_block_epilogue(int cycles, int cond, int pc, int end_pc)
1674 {
1675         if (cycles > 0xff) { elprintf(EL_ANOMALY, "large cycle count: %i\n", cycles); cycles = 0xff; }
1676         EOP_SUB_IMM(11,11,0,cycles);            // sub r11, r11, #cycles
1677
1678         if (cond < 0 || (end_pc >= 0x400 && pc < 0x400)) {
1679                 // indirect jump, or rom -> iram jump, must use dispatcher
1680                 emit_jump(A_COND_AL, ssp_drc_next);
1681         }
1682         else if (cond == A_COND_AL) {
1683                 u32 *target = (pc < 0x400) ? ssp_block_table_iram[ssp->drc.iram_context][pc] : ssp_block_table[pc];
1684                 if (target != NULL)
1685                         emit_jump(A_COND_AL, target);
1686                 else {
1687                         int ops = emit_jump(A_COND_AL, ssp_drc_next);
1688                         // cause the next block to be emitted over jump instruction
1689                         tcache_ptr -= ops;
1690                 }
1691         }
1692         else {
1693                 u32 *target1 = (pc     < 0x400) ? ssp_block_table_iram[ssp->drc.iram_context][pc] : ssp_block_table[pc];
1694                 u32 *target2 = (end_pc < 0x400) ? ssp_block_table_iram[ssp->drc.iram_context][end_pc] : ssp_block_table[end_pc];
1695                 if (target1 != NULL)
1696                      emit_jump(cond, target1);
1697                 if (target2 != NULL)
1698                      emit_jump(tr_neg_cond(cond), target2); // neg_cond, to be able to swap jumps if needed
1699 #ifndef __EPOC32__
1700                 // emit patchable branches
1701                 if (target1 == NULL)
1702                         emit_call(cond, ssp_drc_next_patch);
1703                 if (target2 == NULL)
1704                         emit_call(tr_neg_cond(cond), ssp_drc_next_patch);
1705 #else
1706                 // won't patch indirect jumps
1707                 if (target1 == NULL || target2 == NULL)
1708                         emit_jump(A_COND_AL, ssp_drc_next);
1709 #endif
1710         }
1711 }
1712
1713 void *ssp_translate_block(int pc)
1714 {
1715         unsigned int op, op1, imm, ccount = 0;
1716         unsigned int *block_start;
1717         int ret, end_cond = A_COND_AL, jump_pc = -1;
1718
1719         //printf("translate %04x -> %04x\n", pc<<1, (tcache_ptr-tcache)<<2);
1720
1721         block_start = tcache_ptr;
1722         known_regb = 0;
1723         dirty_regb = KRREG_P;
1724         known_regs.emu_status = 0;
1725         hostreg_clear();
1726
1727         emit_block_prologue();
1728
1729         for (; ccount < 100;)
1730         {
1731                 op = PROGRAM(pc++);
1732                 op1 = op >> 9;
1733                 imm = (u32)-1;
1734
1735                 if ((op1 & 0xf) == 4 || (op1 & 0xf) == 6)
1736                         imm = PROGRAM(pc++); // immediate
1737
1738                 ret = translate_op(op, &pc, imm, &end_cond, &jump_pc);
1739                 if (ret <= 0)
1740                 {
1741                         elprintf(EL_ANOMALY, "NULL func! op=%08x (%02x)\n", op, op1);
1742                         //exit(1);
1743                 }
1744
1745                 ccount += ret & 0xffff;
1746                 if (ret & 0x10000) break;
1747         }
1748
1749         if (ccount >= 100) {
1750                 end_cond = A_COND_AL;
1751                 jump_pc = pc;
1752                 emit_mov_const(A_COND_AL, 0, pc);
1753         }
1754
1755         tr_flush_dirty_prs();
1756         tr_flush_dirty_ST();
1757         tr_flush_dirty_pmcrs();
1758         emit_block_epilogue(ccount, end_cond, jump_pc, pc);
1759
1760         if (tcache_ptr - tcache > SSP_TCACHE_SIZE/4) {
1761                 elprintf(EL_ANOMALY|EL_STATUS|EL_SVP, "tcache overflow!\n");
1762                 fflush(stdout);
1763                 exit(1);
1764         }
1765
1766         // stats
1767         nblocks++;
1768         //printf("%i blocks, %i bytes, k=%.3f\n", nblocks, (tcache_ptr - tcache)*4,
1769         //      (double)(tcache_ptr - tcache) / (double)n_in_ops);
1770
1771 #ifdef DUMP_BLOCK
1772         {
1773                 FILE *f = fopen("tcache.bin", "wb");
1774                 fwrite(tcache, 1, (tcache_ptr - tcache)*4, f);
1775                 fclose(f);
1776         }
1777         printf("dumped tcache.bin\n");
1778         exit(0);
1779 #endif
1780
1781         handle_caches();
1782
1783         return block_start;
1784 }
1785
1786
1787
1788 // -----------------------------------------------------
1789
1790 static void ssp1601_state_load(void)
1791 {
1792         ssp->drc.iram_dirty = 1;
1793         ssp->drc.iram_context = 0;
1794 }
1795
1796 int ssp1601_dyn_startup(void)
1797 {
1798         memset(tcache, 0, SSP_TCACHE_SIZE);
1799         memset(ssp_block_table, 0, sizeof(ssp_block_table));
1800         memset(ssp_block_table_iram, 0, sizeof(ssp_block_table_iram));
1801         tcache_ptr = tcache;
1802
1803         PicoLoadStateHook = ssp1601_state_load;
1804
1805         n_in_ops = 0;
1806 #ifdef ARM
1807         // hle'd blocks
1808         ssp_block_table[0x800/2] = (void *) ssp_hle_800;
1809         ssp_block_table[0x902/2] = (void *) ssp_hle_902;
1810         ssp_block_table_iram[ 7][0x030/2] = (void *) ssp_hle_07_030;
1811         ssp_block_table_iram[ 7][0x036/2] = (void *) ssp_hle_07_036;
1812         ssp_block_table_iram[ 7][0x6d6/2] = (void *) ssp_hle_07_6d6;
1813         ssp_block_table_iram[11][0x12c/2] = (void *) ssp_hle_11_12c;
1814         ssp_block_table_iram[11][0x384/2] = (void *) ssp_hle_11_384;
1815         ssp_block_table_iram[11][0x38a/2] = (void *) ssp_hle_11_38a;
1816 #endif
1817
1818         return 0;
1819 }
1820
1821
1822 void ssp1601_dyn_reset(ssp1601_t *ssp)
1823 {
1824         ssp1601_reset(ssp);
1825         ssp->drc.iram_dirty = 1;
1826         ssp->drc.iram_context = 0;
1827         // must do this here because ssp is not available @ startup()
1828         ssp->drc.ptr_rom = (u32) Pico.rom;
1829         ssp->drc.ptr_iram_rom = (u32) svp->iram_rom;
1830         ssp->drc.ptr_dram = (u32) svp->dram;
1831         ssp->drc.ptr_btable = (u32) ssp_block_table;
1832         ssp->drc.ptr_btable_iram = (u32) ssp_block_table_iram;
1833
1834         // prevent new versions of IRAM from appearing
1835         memset(svp->iram_rom, 0, 0x800);
1836 }
1837
1838
1839 void ssp1601_dyn_run(int cycles)
1840 {
1841         if (ssp->emu_status & SSP_WAIT_MASK) return;
1842
1843 #ifdef DUMP_BLOCK
1844         ssp_translate_block(DUMP_BLOCK >> 1);
1845 #endif
1846 #ifdef ARM
1847         ssp_drc_entry(cycles);
1848 #endif
1849 }
1850