1 // This is part of Pico Library
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3 // (c) Copyright 2004 Dave, All rights reserved.
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4 // (c) Copyright 2006 notaz, All rights reserved.
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5 // Free for non-commercial use.
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7 // For commercial use, separate licencing terms must be obtained.
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9 // A68K no longer supported here
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11 //#define __debug_io
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13 #include "../PicoInt.h"
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15 #include "../sound/sound.h"
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16 #include "../sound/ym2612.h"
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17 #include "../sound/sn76496.h"
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21 typedef unsigned char u8;
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22 typedef unsigned short u16;
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23 typedef unsigned int u32;
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25 //#define __debug_io
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26 //#define __debug_io2
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27 #define rdprintf dprintf
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28 //#define rdprintf(...)
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30 // -----------------------------------------------------------------
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32 // extern m68ki_cpu_core m68ki_cpu;
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34 extern int counter75hz;
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37 static u32 m68k_reg_read16(u32 a)
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41 // dprintf("m68k_regs r%2i: [%02x] @%06x", realsize&~1, a+(realsize&1), SekPc);
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45 d = ((Pico_mcd->s68k_regs[0x33]<<13)&0x8000) | Pico_mcd->m.busreq; // here IFL2 is always 0, just like in Gens
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48 d = (Pico_mcd->s68k_regs[a]<<8) | (Pico_mcd->s68k_regs[a+1]&0xc7);
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49 dprintf("m68k_regs r3: %02x @%06x", (u8)d, SekPc);
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52 d = Pico_mcd->s68k_regs[4]<<8;
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55 d = Pico_mcd->m.hint_vector;
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58 d = Read_CDC_Host(0);
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61 dprintf("m68k reserved read");
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64 dprintf("m68k stopwatch read");
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69 // comm flag/cmd/status (0xE-0x2F)
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70 d = (Pico_mcd->s68k_regs[a]<<8) | Pico_mcd->s68k_regs[a+1];
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74 dprintf("m68k_regs invalid read @ %02x", a);
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78 // dprintf("ret = %04x", d);
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82 static void m68k_reg_write8(u32 a, u32 d)
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85 // dprintf("m68k_regs w%2i: [%02x] %02x @%06x", realsize, a, d, SekPc);
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90 if ((d&1) && (Pico_mcd->s68k_regs[0x33]&(1<<2))) { dprintf("m68k: s68k irq 2"); SekInterruptS68k(2); }
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94 if (!(d&1)) PicoMCD |= 2; // reset pending, needed to be sure we fetch the right vectors on reset
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95 if ( (Pico_mcd->m.busreq&1) != (d&1)) dprintf("m68k: s68k reset %i", !(d&1));
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96 if ( (Pico_mcd->m.busreq&2) != (d&2)) dprintf("m68k: s68k brq %i", (d&2)>>1);
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97 if ((PicoMCD&2) && (d&3)==1) {
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98 SekResetS68k(); // S68k comes out of RESET or BRQ state
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100 dprintf("m68k: resetting s68k, cycles=%i", SekCyclesLeft);
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102 Pico_mcd->m.busreq = d;
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105 Pico_mcd->s68k_regs[2] = d; // really use s68k side register
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108 dprintf("m68k_regs w3: %02x @%06x", (u8)d, SekPc);
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110 if ((Pico_mcd->s68k_regs[3]>>6) != ((d>>6)&3))
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111 dprintf("m68k: prg bank: %i -> %i", (Pico_mcd->s68k_regs[a]>>6), ((d>>6)&3));
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112 //if ((Pico_mcd->s68k_regs[3]&4) != (d&4)) dprintf("m68k: ram mode %i mbit", (d&4) ? 1 : 2);
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113 //if ((Pico_mcd->s68k_regs[3]&2) != (d&2)) dprintf("m68k: %s", (d&4) ? ((d&2) ? "word swap req" : "noop?") :
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114 // ((d&2) ? "word ram to s68k" : "word ram to m68k"));
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115 d |= Pico_mcd->s68k_regs[3]&0x1d;
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116 if (!(d & 4) && (d & 2)) d &= ~1; // return word RAM to s68k in 2M mode
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117 Pico_mcd->s68k_regs[3] = d; // really use s68k side register
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120 *((char *)&Pico_mcd->m.hint_vector+1) = d;
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123 *(char *)&Pico_mcd->m.hint_vector = d;
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126 //dprintf("m68k: comm flag: %02x", d);
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128 //dprintf("s68k @ %06x", SekPcS68k);
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130 Pico_mcd->s68k_regs[0xe] = d;
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134 if ((a&0xf0) == 0x10) {
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135 Pico_mcd->s68k_regs[a] = d;
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139 dprintf("m68k: invalid write? [%02x] %02x", a, d);
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144 static u32 s68k_reg_read16(u32 a)
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148 // dprintf("s68k_regs r%2i: [%02x] @ %06x", realsize&~1, a+(realsize&1), SekPcS68k);
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152 d = ((Pico_mcd->s68k_regs[0]&3)<<8) | 1; // ver = 0, not in reset state
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155 d = (Pico_mcd->s68k_regs[a]<<8) | (Pico_mcd->s68k_regs[a+1]&0x1f);
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156 dprintf("s68k_regs r3: %02x @%06x", (u8)d, SekPc);
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159 d = CDC_Read_Reg();
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162 d = Read_CDC_Host(1); // Gens returns 0 here on byte reads
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165 dprintf("s68k stopwatch read");
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167 case 0x34: // fader
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168 d = 0; // no busy bit
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172 d = (Pico_mcd->s68k_regs[a]<<8) | Pico_mcd->s68k_regs[a+1];
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176 // dprintf("ret = %04x", d);
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181 static void s68k_reg_write8(u32 a, u32 d)
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183 //dprintf("s68k_regs w%2i: [%02x] %02x @ %06x", realsize, a, d, SekPcS68k);
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185 // TODO: review against Gens
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188 return; // only m68k can change WP
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190 dprintf("s68k_regs w3: %02x @%06x", (u8)d, SekPc);
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193 d |= Pico_mcd->s68k_regs[3]&0xc2;
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194 if ((d ^ Pico_mcd->s68k_regs[3]) & 5) d &= ~2; // in case of mode or bank change we clear DMNA (m68k req) bit
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196 d |= Pico_mcd->s68k_regs[3]&0xc3;
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197 if (d&1) d &= ~2; // return word RAM to m68k in 2M mode
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201 dprintf("s68k CDC dest: %x", d&7);
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202 Pico_mcd->s68k_regs[4] = (Pico_mcd->s68k_regs[4]&0xC0) | (d&7); // CDC mode
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205 //dprintf("s68k CDC reg addr: %x", d&0xf);
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211 dprintf("s68k set CDC dma addr");
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213 case 0x33: // IRQ mask
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214 dprintf("s68k irq mask: %02x", d);
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215 if ((d&(1<<4)) && (Pico_mcd->s68k_regs[0x37]&4) && !(Pico_mcd->s68k_regs[0x33]&(1<<4))) {
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216 CDD_Export_Status();
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217 // counter75hz = 0; // ???
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220 case 0x34: // fader
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221 Pico_mcd->s68k_regs[a] = (u8) d & 0x7f;
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224 return; // d/m bit is unsetable
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226 u32 d_old = Pico_mcd->s68k_regs[0x37];
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227 Pico_mcd->s68k_regs[0x37] = d&7;
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228 if ((d&4) && !(d_old&4)) {
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229 CDD_Export_Status();
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230 // counter75hz = 0; // ???
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235 Pico_mcd->s68k_regs[a] = (u8) d;
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236 CDD_Import_Command();
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240 if ((a&0x1f0) == 0x10 || a == 0x0e || (a >= 0x38 && a < 0x42))
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242 dprintf("m68k: invalid write @ %02x?", a);
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246 Pico_mcd->s68k_regs[a] = (u8) d;
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253 static int PadRead(int i)
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255 int pad=0,value=0,TH;
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256 pad=~PicoPad[i]; // Get inverse of pad MXYZ SACB RLDU
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257 TH=Pico.ioports[i+1]&0x40;
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259 if(PicoOpt & 0x20) { // 6 button gamepad enabled
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260 int phase = Pico.m.padTHPhase[i];
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262 if(phase == 2 && !TH) {
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263 value=(pad&0xc0)>>2; // ?0SA 0000
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265 } else if(phase == 3 && TH) {
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266 value=(pad&0x30)|((pad>>8)&0xf); // ?1CB MXYZ
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268 } else if(phase == 3 && !TH) {
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269 value=((pad&0xc0)>>2)|0x0f; // ?0SA 1111
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274 if(TH) value=(pad&0x3f); // ?1CB RLDU
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275 else value=((pad&0xc0)>>2)|(pad&3); // ?0SA 00DU
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279 // orr the bits, which are set as output
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280 value |= Pico.ioports[i+1]&Pico.ioports[i+4];
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282 return value; // will mirror later
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285 static u8 z80Read8(u32 a)
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287 if(Pico.m.z80Run&1) return 0;
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292 // Z80 disabled, do some faking
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293 static u8 zerosent = 0;
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294 if(a == Pico.m.z80_lastaddr) { // probably polling something
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295 u8 d = Pico.m.z80_fakeval;
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296 if((d & 0xf) == 0xf && !zerosent) {
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297 d = 0; zerosent = 1;
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299 Pico.m.z80_fakeval++;
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304 Pico.m.z80_fakeval = 0;
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308 Pico.m.z80_lastaddr = (u16) a;
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309 return Pico.zram[a];
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313 // for nonstandard reads
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314 static u32 UnusualRead16(u32 a, int realsize)
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318 dprintf("unusual r%i: %06x @%06x", realsize&~1, (a&0xfffffe)+(realsize&1), SekPc);
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321 dprintf("ret = %04x", d);
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325 static u32 OtherRead16(u32 a, int realsize)
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329 if ((a&0xff0000)==0xa00000) {
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330 if ((a&0x4000)==0x0000) { d=z80Read8(a); d|=d<<8; goto end; } // Z80 ram (not byteswaped)
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331 if ((a&0x6000)==0x4000) { if(PicoOpt&1) d=YM2612Read(); else d=Pico.m.rotate++&3; goto end; } // 0x4000-0x5fff, Fudge if disabled
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332 d=0xffff; goto end;
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334 if ((a&0xffffe0)==0xa10000) { // I/O ports
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337 case 0: d=Pico.m.hardware; break; // Hardware value (Version register)
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338 case 1: d=PadRead(0); d|=Pico.ioports[1]&0x80; break;
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339 case 2: d=PadRead(1); d|=Pico.ioports[2]&0x80; break;
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340 default: d=Pico.ioports[a]; break; // IO ports can be used as RAM
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345 // |=0x80 for Shadow of the Beast & Super Offroad; rotate fakes next fetched instruction for Time Killers
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346 if (a==0xa11100) { d=((Pico.m.z80Run&1)<<8)|0x8000|Pico.m.rotate++; goto end; }
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348 if ((a&0xe700e0)==0xc00000) { d=PicoVideoRead(a); goto end; }
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350 if ((a&0xffffc0)==0xa12000) {
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351 d=m68k_reg_read16(a);
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355 d = UnusualRead16(a, realsize);
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361 //extern UINT32 mz80GetRegisterValue(void *, UINT32);
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363 static void OtherWrite8(u32 a,u32 d,int realsize)
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365 if ((a&0xe700f9)==0xc00011||(a&0xff7ff9)==0xa07f11) { if(PicoOpt&2) SN76496Write(d); return; } // PSG Sound
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366 if ((a&0xff4000)==0xa00000) { if(!(Pico.m.z80Run&1)) Pico.zram[a&0x1fff]=(u8)d; return; } // Z80 ram
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367 if ((a&0xff6000)==0xa04000) { if(PicoOpt&1) emustatus|=YM2612Write(a&3, d); return; } // FM Sound
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368 if ((a&0xffffe0)==0xa10000) { // I/O ports
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370 // 6 button gamepad: if TH went from 0 to 1, gamepad changes state
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373 Pico.m.padDelay[0] = 0;
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374 if(!(Pico.ioports[1]&0x40) && (d&0x40)) Pico.m.padTHPhase[0]++;
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377 Pico.m.padDelay[1] = 0;
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378 if(!(Pico.ioports[2]&0x40) && (d&0x40)) Pico.m.padTHPhase[1]++;
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381 Pico.ioports[a]=(u8)d; // IO ports can be used as RAM
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385 extern int z80startCycle, z80stopCycle;
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386 //int lineCycles=(488-SekCyclesLeft)&0x1ff;
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389 // hack: detect a nasty situation where Z80 was enabled and disabled in the same 68k timeslice (Golden Axe III)
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390 if((PicoOpt&4) && Pico.m.z80Run==1) z80_run(20);
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391 z80stopCycle = SekCyclesDone();
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392 //z80ExtraCycles += (lineCycles>>1)-(lineCycles>>5); // only meaningful in PicoFrameHints()
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394 z80startCycle = SekCyclesDone();
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395 //if(Pico.m.scanline != -1)
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396 //z80ExtraCycles -= (lineCycles>>1)-(lineCycles>>5)+16;
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398 //dprintf("set_zrun: %i [%i|%i] zPC=%04x @%06x", d, Pico.m.scanline, SekCyclesDone(), mz80GetRegisterValue(NULL, 0), SekPc);
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399 Pico.m.z80Run=(u8)d; return;
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401 if (a==0xa11200) { if(!(d&1)) z80_reset(); return; }
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403 if ((a&0xff7f00)==0xa06000) // Z80 BANK register
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405 Pico.m.z80_bank68k>>=1;
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406 Pico.m.z80_bank68k|=(d&1)<<8;
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407 Pico.m.z80_bank68k&=0x1ff; // 9 bits and filled in the new top one
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411 if ((a&0xe700e0)==0xc00000) { PicoVideoWrite(a,(u16)(d|(d<<8))); return; } // Byte access gets mirrored
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413 if ((a&0xffffc0)==0xa12000) { m68k_reg_write8(a, d); return; }
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415 dprintf("strange w%i: %06x, %08x @%06x", realsize, a&0xffffff, d, SekPc);
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418 static void OtherWrite16(u32 a,u32 d)
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420 if ((a&0xe700e0)==0xc00000) { PicoVideoWrite(a,(u16)d); return; }
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421 if ((a&0xff4000)==0xa00000) { if(!(Pico.m.z80Run&1)) Pico.zram[a&0x1fff]=(u8)(d>>8); return; } // Z80 ram (MSB only)
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423 if ((a&0xffffe0)==0xa10000) { // I/O ports
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425 // 6 button gamepad: if TH went from 0 to 1, gamepad changes state
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428 Pico.m.padDelay[0] = 0;
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429 if(!(Pico.ioports[1]&0x40) && (d&0x40)) Pico.m.padTHPhase[0]++;
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432 Pico.m.padDelay[1] = 0;
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433 if(!(Pico.ioports[2]&0x40) && (d&0x40)) Pico.m.padTHPhase[1]++;
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436 Pico.ioports[a]=(u8)d; // IO ports can be used as RAM
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439 if (a==0xa11100) { OtherWrite8(a, d>>8, 16); return; }
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440 if (a==0xa11200) { if(!(d&0x100)) z80_reset(); return; }
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442 OtherWrite8(a, d>>8, 16);
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443 OtherWrite8(a+1,d&0xff, 16);
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446 // -----------------------------------------------------------------
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447 // Read Rom and read Ram
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449 u8 PicoReadM68k8(u32 a)
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453 if ((a&0xe00000)==0xe00000) { d = *(u8 *)(Pico.ram+((a^1)&0xffff)); goto end; } // Ram
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457 if (a < 0x20000) { d = *(u8 *)(Pico_mcd->bios+(a^1)); goto end; } // bios
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460 if ((a&0xfe0000)==0x020000) {
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461 u8 *prg_bank = Pico_mcd->prg_ram_b[Pico_mcd->s68k_regs[3]>>6];
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462 d = *(prg_bank+((a^1)&0x1ffff));
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467 if ((a&0xfc0000)==0x200000) {
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468 dprintf("m68k_wram r8: [%06x] @%06x", a, SekPc);
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469 if (Pico_mcd->s68k_regs[3]&4) { // 1M mode?
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470 if (a >= 0x220000) {
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473 a=((a&0x1fffe)<<1)|(a&1);
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474 if (Pico_mcd->s68k_regs[3]&1) a+=2;
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475 d = Pico_mcd->word_ram[a^1];
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478 // allow access in any mode, like Gens does
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479 d = Pico_mcd->word_ram[(a^1)&0x3ffff];
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481 dprintf("ret = %02x", (u8)d);
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485 if ((a&0xff4000)==0xa00000) { d=z80Read8(a); goto end; } // Z80 Ram
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487 if ((a&0xffffc0)==0xa12000)
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488 rdprintf("m68k_regs r8: [%02x] @%06x", a&0x3f, SekPc);
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490 d=OtherRead16(a&~1, 8|(a&1)); if ((a&1)==0) d>>=8;
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492 if ((a&0xffffc0)==0xa12000)
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493 rdprintf("ret = %02x", (u8)d);
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498 dprintf("r8 : %06x, %02x @%06x", a&0xffffff, (u8)d, SekPc);
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504 u16 PicoReadM68k16(u32 a)
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508 if ((a&0xe00000)==0xe00000) { d=*(u16 *)(Pico.ram+(a&0xfffe)); goto end; } // Ram
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512 if (a < 0x20000) { d = *(u16 *)(Pico_mcd->bios+a); goto end; } // bios
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515 if ((a&0xfe0000)==0x020000) {
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516 u8 *prg_bank = Pico_mcd->prg_ram_b[Pico_mcd->s68k_regs[3]>>6];
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517 d = *(u16 *)(prg_bank+(a&0x1fffe));
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522 if ((a&0xfc0000)==0x200000) {
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523 dprintf("m68k_wram r16: [%06x] @%06x", a, SekPc);
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524 if (Pico_mcd->s68k_regs[3]&4) { // 1M mode?
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525 if (a >= 0x220000) {
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528 a=((a&0x1fffe)<<1);
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529 if (Pico_mcd->s68k_regs[3]&1) a+=2;
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530 d = *(u16 *)(Pico_mcd->word_ram+a);
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533 // allow access in any mode, like Gens does
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534 d = *(u16 *)(Pico_mcd->word_ram+(a&0x3fffe));
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536 dprintf("ret = %04x", d);
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540 if ((a&0xffffc0)==0xa12000)
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541 rdprintf("m68k_regs r16: [%02x] @%06x", a&0x3f, SekPc);
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543 d = (u16)OtherRead16(a, 16);
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545 if ((a&0xffffc0)==0xa12000)
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546 rdprintf("ret = %04x", d);
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551 dprintf("r16: %06x, %04x @%06x", a&0xffffff, d, SekPc);
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557 u32 PicoReadM68k32(u32 a)
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561 if ((a&0xe00000)==0xe00000) { u16 *pm=(u16 *)(Pico.ram+(a&0xfffe)); d = (pm[0]<<16)|pm[1]; goto end; } // Ram
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565 if (a < 0x20000) { u16 *pm=(u16 *)(Pico_mcd->bios+a); d = (pm[0]<<16)|pm[1]; goto end; } // bios
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568 if ((a&0xfe0000)==0x020000) {
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569 u8 *prg_bank = Pico_mcd->prg_ram_b[Pico_mcd->s68k_regs[3]>>6];
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570 u16 *pm=(u16 *)(prg_bank+(a&0x1fffe));
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571 d = (pm[0]<<16)|pm[1];
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576 if ((a&0xfc0000)==0x200000) {
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577 dprintf("m68k_wram r32: [%06x] @%06x", a, SekPc);
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578 if (Pico_mcd->s68k_regs[3]&4) { // 1M mode?
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579 if (a >= 0x220000) {
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582 a=((a&0x1fffe)<<1);
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583 if (Pico_mcd->s68k_regs[3]&1) a+=2;
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584 d = *(u16 *)(Pico_mcd->word_ram+a) << 16;
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585 d |= *(u16 *)(Pico_mcd->word_ram+a+4);
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588 // allow access in any mode, like Gens does
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589 u16 *pm=(u16 *)(Pico_mcd->word_ram+(a&0x3fffe)); d = (pm[0]<<16)|pm[1];
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591 dprintf("ret = %08x", d);
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595 if ((a&0xffffc0)==0xa12000)
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596 rdprintf("m68k_regs r32: [%02x] @%06x", a&0x3f, SekPc);
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598 d = (OtherRead16(a, 32)<<16)|OtherRead16(a+2, 32);
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600 if ((a&0xffffc0)==0xa12000)
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601 rdprintf("ret = %08x", d);
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605 dprintf("r32: %06x, %08x @%06x", a&0xffffff, d, SekPc);
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611 // -----------------------------------------------------------------
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614 void PicoWriteM68k8(u32 a,u8 d)
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617 dprintf("w8 : %06x, %02x @%06x", a&0xffffff, d, SekPc);
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619 //if ((a&0xe0ffff)==0xe0a9ba+0x69c)
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620 // dprintf("w8 : %06x, %02x @%06x", a&0xffffff, d, SekPc);
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623 if ((a&0xe00000)==0xe00000) { // Ram
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624 *(u8 *)(Pico.ram+((a^1)&0xffff)) = d;
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631 if ((a&0xfe0000)==0x020000) {
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632 u8 *prg_bank = Pico_mcd->prg_ram_b[Pico_mcd->s68k_regs[3]>>6];
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633 *(u8 *)(prg_bank+((a^1)&0x1ffff))=d;
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638 if ((a&0xfc0000)==0x200000) {
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639 dprintf("m68k_wram w8: [%06x] %02x @%06x", a, d, SekPc);
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640 if (Pico_mcd->s68k_regs[3]&4) { // 1M mode?
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641 if (a >= 0x220000) {
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644 a=((a&0x1fffe)<<1)|(a&1);
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645 if (Pico_mcd->s68k_regs[3]&1) a+=2;
\r
646 *(u8 *)(Pico_mcd->word_ram+(a^1))=d;
\r
649 // allow access in any mode, like Gens does
\r
650 *(u8 *)(Pico_mcd->word_ram+((a^1)&0x3ffff))=d;
\r
655 if ((a&0xffffc0)==0xa12000)
\r
656 rdprintf("m68k_regs w8: [%02x] %02x @%06x", a&0x3f, d, SekPc);
\r
658 OtherWrite8(a,d,8);
\r
662 void PicoWriteM68k16(u32 a,u16 d)
\r
665 dprintf("w16: %06x, %04x", a&0xffffff, d);
\r
667 // dprintf("w16: %06x, %04x @%06x", a&0xffffff, d, SekPc);
\r
669 if ((a&0xe00000)==0xe00000) { // Ram
\r
670 *(u16 *)(Pico.ram+(a&0xfffe))=d;
\r
677 if ((a&0xfe0000)==0x020000) {
\r
678 u8 *prg_bank = Pico_mcd->prg_ram_b[Pico_mcd->s68k_regs[3]>>6];
\r
679 *(u16 *)(prg_bank+(a&0x1fffe))=d;
\r
684 if ((a&0xfc0000)==0x200000) {
\r
685 dprintf("m68k_wram w16: [%06x] %04x @%06x", a, d, SekPc);
\r
686 if (Pico_mcd->s68k_regs[3]&4) { // 1M mode?
\r
687 if (a >= 0x220000) {
\r
690 a=((a&0x1fffe)<<1);
\r
691 if (Pico_mcd->s68k_regs[3]&1) a+=2;
\r
692 *(u16 *)(Pico_mcd->word_ram+a)=d;
\r
695 // allow access in any mode, like Gens does
\r
696 *(u16 *)(Pico_mcd->word_ram+(a&0x3fffe))=d;
\r
701 if ((a&0xffffc0)==0xa12000)
\r
702 rdprintf("m68k_regs w16: [%02x] %04x @%06x", a&0x3f, d, SekPc);
\r
708 void PicoWriteM68k32(u32 a,u32 d)
\r
711 dprintf("w32: %06x, %08x", a&0xffffff, d);
\r
714 if ((a&0xe00000)==0xe00000)
\r
717 u16 *pm=(u16 *)(Pico.ram+(a&0xfffe));
\r
718 pm[0]=(u16)(d>>16); pm[1]=(u16)d;
\r
725 if ((a&0xfe0000)==0x020000) {
\r
726 u8 *prg_bank = Pico_mcd->prg_ram_b[Pico_mcd->s68k_regs[3]>>6];
\r
727 u16 *pm=(u16 *)(prg_bank+(a&0x1fffe));
\r
728 pm[0]=(u16)(d>>16); pm[1]=(u16)d;
\r
733 if ((a&0xfc0000)==0x200000) {
\r
734 if (d != 0) // don't log clears
\r
735 dprintf("m68k_wram w32: [%06x] %08x @%06x", a, d, SekPc);
\r
736 if (Pico_mcd->s68k_regs[3]&4) { // 1M mode?
\r
737 if (a >= 0x220000) {
\r
740 a=((a&0x1fffe)<<1);
\r
741 if (Pico_mcd->s68k_regs[3]&1) a+=2;
\r
742 *(u16 *)(Pico_mcd->word_ram+a) = d>>16;
\r
743 *(u16 *)(Pico_mcd->word_ram+a+4) = d;
\r
746 // allow access in any mode, like Gens does
\r
747 u16 *pm=(u16 *)(Pico_mcd->word_ram+(a&0x3fffe));
\r
748 pm[0]=(u16)(d>>16); pm[1]=(u16)d;
\r
753 if ((a&0xffffc0)==0xa12000)
\r
754 rdprintf("m68k_regs w32: [%02x] %08x @%06x", a&0x3f, d, SekPc);
\r
757 if ((a&0x3f) == 0x1c && SekPc == 0xffff05ba)
\r
761 unsigned short *ram = (unsigned short *) Pico.ram;
\r
762 // unswap and dump RAM
\r
763 for (i = 0; i < 0x10000/2; i++)
\r
764 ram[i] = (ram[i]>>8) | (ram[i]<<8);
\r
765 ff = fopen("ram.bin", "wb");
\r
766 fwrite(ram, 1, 0x10000, ff);
\r
772 OtherWrite16(a, (u16)(d>>16));
\r
773 OtherWrite16(a+2,(u16)d);
\r
777 // -----------------------------------------------------------------
\r
780 u8 PicoReadS68k8(u32 a)
\r
788 d = *(Pico_mcd->prg_ram+(a^1));
\r
793 if ((a&0xfffe00) == 0xff8000) {
\r
795 rdprintf("s68k_regs r8: [%02x] @ %06x", a, SekPcS68k);
\r
796 if (a >= 0x50 && a < 0x68)
\r
797 d = gfx_cd_read(a&~1);
\r
798 else d = s68k_reg_read16(a&~1);
\r
799 if ((a&1)==0) d>>=8;
\r
800 rdprintf("ret = %02x", (u8)d);
\r
804 // word RAM (2M area)
\r
805 if ((a&0xfc0000)==0x080000) { // 080000-0bffff
\r
806 dprintf("s68k_wram2M r8: [%06x] @%06x", a, SekPc);
\r
807 if (Pico_mcd->s68k_regs[3]&4) { // 1M mode?
\r
809 dprintf("(decode)");
\r
811 // allow access in any mode, like Gens does
\r
812 d = Pico_mcd->word_ram[(a^1)&0x3ffff];
\r
814 dprintf("ret = %02x", (u8)d);
\r
818 // word RAM (1M area)
\r
819 if ((a&0xfe0000)==0x0c0000 && (Pico_mcd->s68k_regs[3]&4)) { // 0c0000-0dffff
\r
820 dprintf("s68k_wram1M r8: [%06x] @%06x", a, SekPc);
\r
821 a=((a&0x1fffe)<<1)|(a&1);
\r
822 if (!(Pico_mcd->s68k_regs[3]&1)) a+=2;
\r
823 d = Pico_mcd->word_ram[a^1];
\r
824 dprintf("ret = %02x", (u8)d);
\r
829 if ((a&0xff0000)==0xfe0000) {
\r
830 d = Pico_mcd->bram[(a>>1)&0x1fff];
\r
834 dprintf("s68k r8 : %06x, %02x @%06x", a&0xffffff, (u8)d, SekPcS68k);
\r
839 dprintf("s68k r8 : %06x, %02x @%06x", a&0xffffff, (u8)d, SekPcS68k);
\r
845 u16 PicoReadS68k16(u32 a)
\r
853 d = *(u16 *)(Pico_mcd->prg_ram+a);
\r
858 if ((a&0xfffe00) == 0xff8000) {
\r
860 rdprintf("s68k_regs r16: [%02x] @ %06x", a, SekPcS68k);
\r
861 if (a >= 0x50 && a < 0x68)
\r
862 d = gfx_cd_read(a);
\r
863 else d = s68k_reg_read16(a);
\r
864 rdprintf("ret = %04x", d);
\r
868 // word RAM (2M area)
\r
869 if ((a&0xfc0000)==0x080000) { // 080000-0bffff
\r
870 dprintf("s68k_wram2M r16: [%06x] @%06x", a, SekPc);
\r
871 if (Pico_mcd->s68k_regs[3]&4) { // 1M mode?
\r
873 dprintf("(decode)");
\r
875 // allow access in any mode, like Gens does
\r
876 d = *(u16 *)(Pico_mcd->word_ram+(a&0x3fffe));
\r
878 dprintf("ret = %04x", d);
\r
882 // word RAM (1M area)
\r
883 if ((a&0xfe0000)==0x0c0000 && (Pico_mcd->s68k_regs[3]&4)) { // 0c0000-0dffff
\r
884 dprintf("s68k_wram1M r16: [%06x] @%06x", a, SekPc);
\r
885 a=((a&0x1fffe)<<1);
\r
886 if (!(Pico_mcd->s68k_regs[3]&1)) a+=2;
\r
887 d = *(u16 *)(Pico_mcd->word_ram+a);
\r
888 dprintf("ret = %04x", d);
\r
893 if ((a&0xff0000)==0xfe0000) {
\r
894 dprintf("s68k_bram r16: [%06x] @%06x", a, SekPc);
\r
896 d = Pico_mcd->bram[a++]; // Gens does little endian here, an so do we..
\r
897 d|= Pico_mcd->bram[a++] << 8;
\r
898 dprintf("ret = %04x", d);
\r
902 dprintf("s68k r16: %06x, %04x @%06x", a&0xffffff, d, SekPcS68k);
\r
907 dprintf("s68k r16: %06x, %04x @%06x", a&0xffffff, d, SekPcS68k);
\r
913 u32 PicoReadS68k32(u32 a)
\r
921 u16 *pm=(u16 *)(Pico_mcd->prg_ram+a);
\r
922 d = (pm[0]<<16)|pm[1];
\r
927 if ((a&0xfffe00) == 0xff8000) {
\r
929 rdprintf("s68k_regs r32: [%02x] @ %06x", a, SekPcS68k);
\r
930 if (a >= 0x50 && a < 0x68)
\r
931 d = (gfx_cd_read(a)<<16)|gfx_cd_read(a+2);
\r
932 else d = (s68k_reg_read16(a)<<16)|s68k_reg_read16(a+2);
\r
933 rdprintf("ret = %08x", d);
\r
937 // word RAM (2M area)
\r
938 if ((a&0xfc0000)==0x080000) { // 080000-0bffff
\r
939 dprintf("s68k_wram2M r32: [%06x] @%06x", a, SekPc);
\r
940 if (Pico_mcd->s68k_regs[3]&4) { // 1M mode?
\r
942 dprintf("(decode)");
\r
944 // allow access in any mode, like Gens does
\r
945 u16 *pm=(u16 *)(Pico_mcd->word_ram+(a&0x3fffe)); d = (pm[0]<<16)|pm[1];
\r
947 dprintf("ret = %08x", d);
\r
951 // word RAM (1M area)
\r
952 if ((a&0xfe0000)==0x0c0000 && (Pico_mcd->s68k_regs[3]&4)) { // 0c0000-0dffff
\r
953 dprintf("s68k_wram1M r32: [%06x] @%06x", a, SekPc);
\r
954 a=((a&0x1fffe)<<1);
\r
955 if (!(Pico_mcd->s68k_regs[3]&1)) a+=2;
\r
956 d = *(u16 *)(Pico_mcd->word_ram+a) << 16;
\r
957 d |= *(u16 *)(Pico_mcd->word_ram+a+4);
\r
958 dprintf("ret = %08x", d);
\r
963 if ((a&0xff0000)==0xfe0000) {
\r
964 dprintf("s68k_bram r32: [%06x] @%06x", a, SekPc);
\r
966 d = Pico_mcd->bram[a++] << 16; // middle endian? TODO: verify against Fusion..
\r
967 d|= Pico_mcd->bram[a++] << 24;
\r
968 d|= Pico_mcd->bram[a++];
\r
969 d|= Pico_mcd->bram[a++] << 8;
\r
970 dprintf("ret = %08x", d);
\r
974 dprintf("s68k r32: %06x, %08x @%06x", a&0xffffff, d, SekPcS68k);
\r
979 dprintf("s68k r32: %06x, %08x @%06x", a&0xffffff, d, SekPcS68k);
\r
985 // -----------------------------------------------------------------
\r
987 void PicoWriteS68k8(u32 a,u8 d)
\r
990 dprintf("s68k w8 : %06x, %02x @%06x", a&0xffffff, d, SekPcS68k);
\r
997 u8 *pm=(u8 *)(Pico_mcd->prg_ram+(a^1));
\r
1002 if (a != 0xff0011 && (a&0xff8000) == 0xff0000) // PCM hack
\r
1006 if ((a&0xfffe00) == 0xff8000) {
\r
1008 rdprintf("s68k_regs w8: [%02x] %02x @ %06x", a, d, SekPcS68k);
\r
1009 if (a >= 0x50 && a < 0x68)
\r
1010 gfx_cd_write(a&~1, (d<<8)|d);
\r
1011 else s68k_reg_write8(a,d);
\r
1015 // word RAM (2M area)
\r
1016 if ((a&0xfc0000)==0x080000) { // 080000-0bffff
\r
1017 dprintf("s68k_wram2M w8: [%06x] %02x @%06x", a, d, SekPc);
\r
1018 if (Pico_mcd->s68k_regs[3]&4) { // 1M mode?
\r
1020 dprintf("(decode)");
\r
1022 // allow access in any mode, like Gens does
\r
1023 *(u8 *)(Pico_mcd->word_ram+((a^1)&0x3ffff))=d;
\r
1028 // word RAM (1M area)
\r
1029 if ((a&0xfe0000)==0x0c0000 && (Pico_mcd->s68k_regs[3]&4)) { // 0c0000-0dffff
\r
1031 dprintf("s68k_wram1M w8: [%06x] %02x @%06x", a, d, SekPc);
\r
1032 a=((a&0x1fffe)<<1)|(a&1);
\r
1033 if (!(Pico_mcd->s68k_regs[3]&1)) a+=2;
\r
1034 *(u8 *)(Pico_mcd->word_ram+(a^1))=d;
\r
1039 if ((a&0xff0000)==0xfe0000) {
\r
1040 Pico_mcd->bram[(a>>1)&0x1fff] = d;
\r
1045 dprintf("s68k w8 : %06x, %02x @%06x", a&0xffffff, d, SekPcS68k);
\r
1049 void PicoWriteS68k16(u32 a,u16 d)
\r
1051 #ifdef __debug_io2
\r
1052 dprintf("s68k w16: %06x, %04x @%06x", a&0xffffff, d, SekPcS68k);
\r
1058 if (a < 0x80000) {
\r
1059 *(u16 *)(Pico_mcd->prg_ram+a)=d;
\r
1064 if ((a&0xfffe00) == 0xff8000) {
\r
1066 rdprintf("s68k_regs w16: [%02x] %04x @ %06x", a, d, SekPcS68k);
\r
1067 if (a >= 0x50 && a < 0x68)
\r
1068 gfx_cd_write(a, d);
\r
1070 s68k_reg_write8(a, d>>8);
\r
1071 s68k_reg_write8(a+1,d&0xff);
\r
1076 // word RAM (2M area)
\r
1077 if ((a&0xfc0000)==0x080000) { // 080000-0bffff
\r
1078 dprintf("s68k_wram2M w16: [%06x] %04x @%06x", a, d, SekPc);
\r
1079 if (Pico_mcd->s68k_regs[3]&4) { // 1M mode?
\r
1081 dprintf("(decode)");
\r
1083 // allow access in any mode, like Gens does
\r
1084 *(u16 *)(Pico_mcd->word_ram+(a&0x3fffe))=d;
\r
1089 // word RAM (1M area)
\r
1090 if ((a&0xfe0000)==0x0c0000 && (Pico_mcd->s68k_regs[3]&4)) { // 0c0000-0dffff
\r
1092 dprintf("s68k_wram1M w16: [%06x] %04x @%06x", a, d, SekPc);
\r
1093 a=((a&0x1fffe)<<1);
\r
1094 if (!(Pico_mcd->s68k_regs[3]&1)) a+=2;
\r
1095 *(u16 *)(Pico_mcd->word_ram+a)=d;
\r
1100 if ((a&0xff0000)==0xfe0000) {
\r
1101 dprintf("s68k_bram w16: [%06x] %04x @%06x", a, d, SekPc);
\r
1102 a = (a>>1)&0x1fff;
\r
1103 Pico_mcd->bram[a++] = d; // Gens does little endian here, an so do we..
\r
1104 Pico_mcd->bram[a++] = d >> 8;
\r
1109 dprintf("s68k w16: %06x, %04x @%06x", a&0xffffff, d, SekPcS68k);
\r
1113 void PicoWriteS68k32(u32 a,u32 d)
\r
1115 #ifdef __debug_io2
\r
1116 dprintf("s68k w32: %06x, %08x @%06x", a&0xffffff, d, SekPcS68k);
\r
1122 if (a < 0x80000) {
\r
1123 u16 *pm=(u16 *)(Pico_mcd->prg_ram+a);
\r
1124 pm[0]=(u16)(d>>16); pm[1]=(u16)d;
\r
1129 if ((a&0xfffe00) == 0xff8000) {
\r
1131 rdprintf("s68k_regs w32: [%02x] %08x @ %06x", a, d, SekPcS68k);
\r
1132 if (a >= 0x50 && a < 0x68) {
\r
1133 gfx_cd_write(a, d>>16);
\r
1134 gfx_cd_write(a+2, d&0xffff);
\r
1136 s68k_reg_write8(a, d>>24);
\r
1137 s68k_reg_write8(a+1,(d>>16)&0xff);
\r
1138 s68k_reg_write8(a+2,(d>>8) &0xff);
\r
1139 s68k_reg_write8(a+3, d &0xff);
\r
1144 // word RAM (2M area)
\r
1145 if ((a&0xfc0000)==0x080000) { // 080000-0bffff
\r
1146 dprintf("s68k_wram2M w32: [%06x] %08x @%06x", a, d, SekPc);
\r
1147 if (Pico_mcd->s68k_regs[3]&4) { // 1M mode?
\r
1149 dprintf("(decode)");
\r
1151 // allow access in any mode, like Gens does
\r
1152 u16 *pm=(u16 *)(Pico_mcd->word_ram+(a&0x3fffe));
\r
1153 pm[0]=(u16)(d>>16); pm[1]=(u16)d;
\r
1158 // word RAM (1M area)
\r
1159 if ((a&0xfe0000)==0x0c0000 && (Pico_mcd->s68k_regs[3]&4)) { // 0c0000-0dffff
\r
1161 dprintf("s68k_wram1M w32: [%06x] %08x @%06x", a, d, SekPc);
\r
1162 a=((a&0x1fffe)<<1);
\r
1163 if (!(Pico_mcd->s68k_regs[3]&1)) a+=2;
\r
1164 *(u16 *)(Pico_mcd->word_ram+a) = d>>16;
\r
1165 *(u16 *)(Pico_mcd->word_ram+a+4) = d;
\r
1170 if ((a&0xff0000)==0xfe0000) {
\r
1171 dprintf("s68k_bram w32: [%06x] %08x @%06x", a, d, SekPc);
\r
1172 a = (a>>1)&0x1fff;
\r
1173 Pico_mcd->bram[a++] = d >> 16; // middle endian? verify?
\r
1174 Pico_mcd->bram[a++] = d >> 24;
\r
1175 Pico_mcd->bram[a++] = d;
\r
1176 Pico_mcd->bram[a++] = d >> 8;
\r
1181 dprintf("s68k w32: %06x, %08x @%06x", a&0xffffff, d, SekPcS68k);
\r
1186 // -----------------------------------------------------------------
\r
1189 unsigned char PicoReadCD8w (unsigned int a) {
\r
1190 return m68ki_cpu_p == &PicoS68kCPU ? PicoReadS68k8(a) : PicoReadM68k8(a);
\r
1192 unsigned short PicoReadCD16w(unsigned int a) {
\r
1193 return m68ki_cpu_p == &PicoS68kCPU ? PicoReadS68k16(a) : PicoReadM68k16(a);
\r
1195 unsigned int PicoReadCD32w(unsigned int a) {
\r
1196 return m68ki_cpu_p == &PicoS68kCPU ? PicoReadS68k32(a) : PicoReadM68k32(a);
\r
1198 void PicoWriteCD8w (unsigned int a, unsigned char d) {
\r
1199 if (m68ki_cpu_p == &PicoS68kCPU) PicoWriteS68k8(a, d); else PicoWriteM68k8(a, d);
\r
1201 void PicoWriteCD16w(unsigned int a, unsigned short d) {
\r
1202 if (m68ki_cpu_p == &PicoS68kCPU) PicoWriteS68k16(a, d); else PicoWriteM68k16(a, d);
\r
1204 void PicoWriteCD32w(unsigned int a, unsigned int d) {
\r
1205 if (m68ki_cpu_p == &PicoS68kCPU) PicoWriteS68k32(a, d); else PicoWriteM68k32(a, d);
\r
1208 // these are allowed to access RAM
\r
1209 unsigned int m68k_read_pcrelative_CD8 (unsigned int a) {
\r
1211 if(m68ki_cpu_p == &PicoS68kCPU) {
\r
1212 if (a < 0x80000) return *(u8 *)(Pico_mcd->prg_ram+(a^1)); // PRG Ram
\r
1213 else dprintf("s68k read_pcrel8 @ %06x", a);
\r
1215 if(a<Pico.romsize) return *(u8 *)(Pico.rom+(a^1)); // Rom
\r
1216 if((a&0xe00000)==0xe00000) return *(u8 *)(Pico.ram+((a^1)&0xffff)); // Ram
\r
1218 return 0;//(u8) lastread_d;
\r
1220 unsigned int m68k_read_pcrelative_CD16(unsigned int a) {
\r
1222 if(m68ki_cpu_p == &PicoS68kCPU) {
\r
1223 if (a < 0x80000) return *(u16 *)(Pico_mcd->prg_ram+(a&~1)); // PRG Ram
\r
1224 else dprintf("s68k read_pcrel16 @ %06x", a);
\r
1226 if(a<Pico.romsize) return *(u16 *)(Pico.rom+(a&~1)); // Rom
\r
1227 if((a&0xe00000)==0xe00000) return *(u16 *)(Pico.ram+(a&0xfffe)); // Ram
\r
1229 return 0;//(u16) lastread_d;
\r
1231 unsigned int m68k_read_pcrelative_CD32(unsigned int a) {
\r
1233 if(m68ki_cpu_p == &PicoS68kCPU) {
\r
1234 if (a < 0x80000) { u16 *pm=(u16 *)(Pico_mcd->prg_ram+(a&~1)); return (pm[0]<<16)|pm[1]; } // PRG Ram
\r
1235 else dprintf("s68k read_pcrel32 @ %06x", a);
\r
1237 if(a<Pico.romsize) { u16 *pm=(u16 *)(Pico.rom+(a&~1)); return (pm[0]<<16)|pm[1]; }
\r
1238 if((a&0xe00000)==0xe00000) { u16 *pm=(u16 *)(Pico.ram+(a&0xfffe)); return (pm[0]<<16)|pm[1]; } // Ram
\r
1240 return 0; //lastread_d;
\r
1242 #endif // EMU_M68K
\r