cpu/drc/emit_arm.c

   1 // Basic macros to emit ARM instructions and some utils
   2
   3 // (c) Copyright 2008-2009, Grazvydas "notaz" Ignotas
   4 // Free for non-commercial use.
   5
   6 #define CONTEXT_REG 7
   7
   8 // XXX: tcache_ptr type for SVP and SH2 compilers differs..
   9 #define EMIT_PTR(ptr, x) \
  10         do { \
  11                 *(u32 *)ptr = x; \
  12                 ptr = (void *)((u8 *)ptr + sizeof(u32)); \
  13                 COUNT_OP; \
  14         } while (0)
  15
  16 #define EMIT(x) EMIT_PTR(tcache_ptr, x)
  17
  18 #define A_R4M  (1 << 4)
  19 #define A_R5M  (1 << 5)
  20 #define A_R6M  (1 << 6)
  21 #define A_R7M  (1 << 7)
  22 #define A_R8M  (1 << 8)
  23 #define A_R9M  (1 << 9)
  24 #define A_R10M (1 << 10)
  25 #define A_R11M (1 << 11)
  26 #define A_R14M (1 << 14)
  27
  28 #define A_COND_AL 0xe
  29 #define A_COND_EQ 0x0
  30 #define A_COND_NE 0x1
  31 #define A_COND_HS 0x2
  32 #define A_COND_LO 0x3
  33 #define A_COND_MI 0x4
  34 #define A_COND_PL 0x5
  35 #define A_COND_VS 0x6
  36 #define A_COND_VC 0x7
  37 #define A_COND_HI 0x8
  38 #define A_COND_LS 0x9
  39 #define A_COND_GE 0xa
  40 #define A_COND_LT 0xb
  41 #define A_COND_GT 0xc
  42 #define A_COND_LE 0xd
  43
  44 /* unified conditions */
  45 #define DCOND_EQ A_COND_EQ
  46 #define DCOND_NE A_COND_NE
  47 #define DCOND_MI A_COND_MI
  48 #define DCOND_PL A_COND_PL
  49 #define DCOND_HI A_COND_HI
  50 #define DCOND_HS A_COND_HS
  51 #define DCOND_LO A_COND_LO
  52 #define DCOND_GE A_COND_GE
  53 #define DCOND_GT A_COND_GT
  54 #define DCOND_LT A_COND_LT
  55 #define DCOND_LS A_COND_LS
  56 #define DCOND_LE A_COND_LE
  57 #define DCOND_VS A_COND_VS
  58 #define DCOND_VC A_COND_VC
  59 #define DCOND_CS A_COND_HS
  60 #define DCOND_CC A_COND_LO
  61
  62 /* addressing mode 1 */
  63 #define A_AM1_LSL 0
  64 #define A_AM1_LSR 1
  65 #define A_AM1_ASR 2
  66 #define A_AM1_ROR 3
  67
  68 #define A_AM1_IMM(ror2,imm8)                  (((ror2)<<8) | (imm8) | 0x02000000)
  69 #define A_AM1_REG_XIMM(shift_imm,shift_op,rm) (((shift_imm)<<7) | ((shift_op)<<5) | (rm))
  70 #define A_AM1_REG_XREG(rs,shift_op,rm)        (((rs)<<8) | ((shift_op)<<5) | 0x10 | (rm))
  71
  72 /* data processing op */
  73 #define A_OP_AND 0x0
  74 #define A_OP_EOR 0x1
  75 #define A_OP_SUB 0x2
  76 #define A_OP_RSB 0x3
  77 #define A_OP_ADD 0x4
  78 #define A_OP_ADC 0x5
  79 #define A_OP_SBC 0x6
  80 #define A_OP_TST 0x8
  81 #define A_OP_TEQ 0x9
  82 #define A_OP_CMP 0xa
  83 #define A_OP_ORR 0xc
  84 #define A_OP_MOV 0xd
  85 #define A_OP_BIC 0xe
  86 #define A_OP_MVN 0xf
  87
  88 #define EOP_C_DOP_X(cond,op,s,rn,rd,shifter_op) \
  89         EMIT(((cond)<<28) | ((op)<< 21) | ((s)<<20) | ((rn)<<16) | ((rd)<<12) | (shifter_op))
  90
  91 #define EOP_C_DOP_IMM(     cond,op,s,rn,rd,ror2,imm8)             EOP_C_DOP_X(cond,op,s,rn,rd,A_AM1_IMM(ror2,imm8))
  92 #define EOP_C_DOP_REG_XIMM(cond,op,s,rn,rd,shift_imm,shift_op,rm) EOP_C_DOP_X(cond,op,s,rn,rd,A_AM1_REG_XIMM(shift_imm,shift_op,rm))
  93 #define EOP_C_DOP_REG_XREG(cond,op,s,rn,rd,rs,       shift_op,rm) EOP_C_DOP_X(cond,op,s,rn,rd,A_AM1_REG_XREG(rs,       shift_op,rm))
  94
  95 #define EOP_MOV_IMM(rd,   ror2,imm8) EOP_C_DOP_IMM(A_COND_AL,A_OP_MOV,0, 0,rd,ror2,imm8)
  96 #define EOP_ORR_IMM(rd,rn,ror2,imm8) EOP_C_DOP_IMM(A_COND_AL,A_OP_ORR,0,rn,rd,ror2,imm8)
  97 #define EOP_EOR_IMM(rd,rn,ror2,imm8) EOP_C_DOP_IMM(A_COND_AL,A_OP_EOR,0,rn,rd,ror2,imm8)
  98 #define EOP_ADD_IMM(rd,rn,ror2,imm8) EOP_C_DOP_IMM(A_COND_AL,A_OP_ADD,0,rn,rd,ror2,imm8)
  99 #define EOP_BIC_IMM(rd,rn,ror2,imm8) EOP_C_DOP_IMM(A_COND_AL,A_OP_BIC,0,rn,rd,ror2,imm8)
 100 #define EOP_AND_IMM(rd,rn,ror2,imm8) EOP_C_DOP_IMM(A_COND_AL,A_OP_AND,0,rn,rd,ror2,imm8)
 101 #define EOP_SUB_IMM(rd,rn,ror2,imm8) EOP_C_DOP_IMM(A_COND_AL,A_OP_SUB,0,rn,rd,ror2,imm8)
 102 #define EOP_TST_IMM(   rn,ror2,imm8) EOP_C_DOP_IMM(A_COND_AL,A_OP_TST,1,rn, 0,ror2,imm8)
 103 #define EOP_CMP_IMM(   rn,ror2,imm8) EOP_C_DOP_IMM(A_COND_AL,A_OP_CMP,1,rn, 0,ror2,imm8)
 104 #define EOP_RSB_IMM(rd,rn,ror2,imm8) EOP_C_DOP_IMM(A_COND_AL,A_OP_RSB,0,rn,rd,ror2,imm8)
 105
 106 #define EOP_MOV_IMM_C(cond,rd,   ror2,imm8) EOP_C_DOP_IMM(cond,A_OP_MOV,0, 0,rd,ror2,imm8)
 107 #define EOP_ORR_IMM_C(cond,rd,rn,ror2,imm8) EOP_C_DOP_IMM(cond,A_OP_ORR,0,rn,rd,ror2,imm8)
 108 #define EOP_RSB_IMM_C(cond,rd,rn,ror2,imm8) EOP_C_DOP_IMM(cond,A_OP_RSB,0,rn,rd,ror2,imm8)
 109
 110 #define EOP_MOV_REG(cond,s,rd,   rm,shift_op,shift_imm) EOP_C_DOP_REG_XIMM(cond,A_OP_MOV,s, 0,rd,shift_imm,shift_op,rm)
 111 #define EOP_ORR_REG(cond,s,rd,rn,rm,shift_op,shift_imm) EOP_C_DOP_REG_XIMM(cond,A_OP_ORR,s,rn,rd,shift_imm,shift_op,rm)
 112 #define EOP_ADD_REG(cond,s,rd,rn,rm,shift_op,shift_imm) EOP_C_DOP_REG_XIMM(cond,A_OP_ADD,s,rn,rd,shift_imm,shift_op,rm)
 113 #define EOP_ADC_REG(cond,s,rd,rn,rm,shift_op,shift_imm) EOP_C_DOP_REG_XIMM(cond,A_OP_ADC,s,rn,rd,shift_imm,shift_op,rm)
 114 #define EOP_SUB_REG(cond,s,rd,rn,rm,shift_op,shift_imm) EOP_C_DOP_REG_XIMM(cond,A_OP_SUB,s,rn,rd,shift_imm,shift_op,rm)
 115 #define EOP_SBC_REG(cond,s,rd,rn,rm,shift_op,shift_imm) EOP_C_DOP_REG_XIMM(cond,A_OP_SBC,s,rn,rd,shift_imm,shift_op,rm)
 116 #define EOP_AND_REG(cond,s,rd,rn,rm,shift_op,shift_imm) EOP_C_DOP_REG_XIMM(cond,A_OP_AND,s,rn,rd,shift_imm,shift_op,rm)
 117 #define EOP_EOR_REG(cond,s,rd,rn,rm,shift_op,shift_imm) EOP_C_DOP_REG_XIMM(cond,A_OP_EOR,s,rn,rd,shift_imm,shift_op,rm)
 118 #define EOP_CMP_REG(cond,     rn,rm,shift_op,shift_imm) EOP_C_DOP_REG_XIMM(cond,A_OP_CMP,1,rn, 0,shift_imm,shift_op,rm)
 119 #define EOP_TST_REG(cond,     rn,rm,shift_op,shift_imm) EOP_C_DOP_REG_XIMM(cond,A_OP_TST,1,rn, 0,shift_imm,shift_op,rm)
 120 #define EOP_TEQ_REG(cond,     rn,rm,shift_op,shift_imm) EOP_C_DOP_REG_XIMM(cond,A_OP_TEQ,1,rn, 0,shift_imm,shift_op,rm)
 121
 122 #define EOP_MOV_REG2(s,rd,   rm,shift_op,rs) EOP_C_DOP_REG_XREG(A_COND_AL,A_OP_MOV,s, 0,rd,rs,shift_op,rm)
 123 #define EOP_ADD_REG2(s,rd,rn,rm,shift_op,rs) EOP_C_DOP_REG_XREG(A_COND_AL,A_OP_ADD,s,rn,rd,rs,shift_op,rm)
 124 #define EOP_SUB_REG2(s,rd,rn,rm,shift_op,rs) EOP_C_DOP_REG_XREG(A_COND_AL,A_OP_SUB,s,rn,rd,rs,shift_op,rm)
 125
 126 #define EOP_MOV_REG_SIMPLE(rd,rm)           EOP_MOV_REG(A_COND_AL,0,rd,rm,A_AM1_LSL,0)
 127 #define EOP_MOV_REG_LSL(rd,   rm,shift_imm) EOP_MOV_REG(A_COND_AL,0,rd,rm,A_AM1_LSL,shift_imm)
 128 #define EOP_MOV_REG_LSR(rd,   rm,shift_imm) EOP_MOV_REG(A_COND_AL,0,rd,rm,A_AM1_LSR,shift_imm)
 129 #define EOP_MOV_REG_ASR(rd,   rm,shift_imm) EOP_MOV_REG(A_COND_AL,0,rd,rm,A_AM1_ASR,shift_imm)
 130 #define EOP_MOV_REG_ROR(rd,   rm,shift_imm) EOP_MOV_REG(A_COND_AL,0,rd,rm,A_AM1_ROR,shift_imm)
 131
 132 #define EOP_ORR_REG_SIMPLE(rd,rm)           EOP_ORR_REG(A_COND_AL,0,rd,rd,rm,A_AM1_LSL,0)
 133 #define EOP_ORR_REG_LSL(rd,rn,rm,shift_imm) EOP_ORR_REG(A_COND_AL,0,rd,rn,rm,A_AM1_LSL,shift_imm)
 134 #define EOP_ORR_REG_LSR(rd,rn,rm,shift_imm) EOP_ORR_REG(A_COND_AL,0,rd,rn,rm,A_AM1_LSR,shift_imm)
 135 #define EOP_ORR_REG_ASR(rd,rn,rm,shift_imm) EOP_ORR_REG(A_COND_AL,0,rd,rn,rm,A_AM1_ASR,shift_imm)
 136 #define EOP_ORR_REG_ROR(rd,rn,rm,shift_imm) EOP_ORR_REG(A_COND_AL,0,rd,rn,rm,A_AM1_ROR,shift_imm)
 137
 138 #define EOP_ADD_REG_SIMPLE(rd,rm)           EOP_ADD_REG(A_COND_AL,0,rd,rd,rm,A_AM1_LSL,0)
 139 #define EOP_ADD_REG_LSL(rd,rn,rm,shift_imm) EOP_ADD_REG(A_COND_AL,0,rd,rn,rm,A_AM1_LSL,shift_imm)
 140 #define EOP_ADD_REG_LSR(rd,rn,rm,shift_imm) EOP_ADD_REG(A_COND_AL,0,rd,rn,rm,A_AM1_LSR,shift_imm)
 141
 142 #define EOP_TST_REG_SIMPLE(rn,rm)           EOP_TST_REG(A_COND_AL,  rn,   0,A_AM1_LSL,rm)
 143
 144 #define EOP_MOV_REG2_LSL(rd,   rm,rs)       EOP_MOV_REG2(0,rd,   rm,A_AM1_LSL,rs)
 145 #define EOP_MOV_REG2_ROR(rd,   rm,rs)       EOP_MOV_REG2(0,rd,   rm,A_AM1_ROR,rs)
 146 #define EOP_ADD_REG2_LSL(rd,rn,rm,rs)       EOP_ADD_REG2(0,rd,rn,rm,A_AM1_LSL,rs)
 147 #define EOP_SUB_REG2_LSL(rd,rn,rm,rs)       EOP_SUB_REG2(0,rd,rn,rm,A_AM1_LSL,rs)
 148
 149 /* addressing mode 2 */
 150 #define EOP_C_AM2_IMM(cond,u,b,l,rn,rd,offset_12) \
 151         EMIT(((cond)<<28) | 0x05000000 | ((u)<<23) | ((b)<<22) | ((l)<<20) | ((rn)<<16) | ((rd)<<12) | (offset_12))
 152
 153 /* addressing mode 3 */
 154 #define EOP_C_AM3(cond,u,r,l,rn,rd,s,h,immed_reg) \
 155         EMIT(((cond)<<28) | 0x01000090 | ((u)<<23) | ((r)<<22) | ((l)<<20) | ((rn)<<16) | ((rd)<<12) | \
 156                         ((s)<<6) | ((h)<<5) | (immed_reg))
 157
 158 #define EOP_C_AM3_IMM(cond,u,l,rn,rd,s,h,offset_8) EOP_C_AM3(cond,u,1,l,rn,rd,s,h,(((offset_8)&0xf0)<<4)|((offset_8)&0xf))
 159
 160 #define EOP_C_AM3_REG(cond,u,l,rn,rd,s,h,rm)       EOP_C_AM3(cond,u,0,l,rn,rd,s,h,rm)
 161
 162 /* ldr and str */
 163 #define EOP_LDR_IMM(   rd,rn,offset_12) EOP_C_AM2_IMM(A_COND_AL,1,0,1,rn,rd,offset_12)
 164 #define EOP_LDR_NEGIMM(rd,rn,offset_12) EOP_C_AM2_IMM(A_COND_AL,0,0,1,rn,rd,offset_12)
 165 #define EOP_LDR_SIMPLE(rd,rn)           EOP_C_AM2_IMM(A_COND_AL,1,0,1,rn,rd,0)
 166 #define EOP_STR_IMM(   rd,rn,offset_12) EOP_C_AM2_IMM(A_COND_AL,1,0,0,rn,rd,offset_12)
 167 #define EOP_STR_SIMPLE(rd,rn)           EOP_C_AM2_IMM(A_COND_AL,1,0,0,rn,rd,0)
 168
 169 #define EOP_LDRH_IMM(   rd,rn,offset_8)  EOP_C_AM3_IMM(A_COND_AL,1,1,rn,rd,0,1,offset_8)
 170 #define EOP_LDRH_SIMPLE(rd,rn)           EOP_C_AM3_IMM(A_COND_AL,1,1,rn,rd,0,1,0)
 171 #define EOP_LDRH_REG(   rd,rn,rm)        EOP_C_AM3_REG(A_COND_AL,1,1,rn,rd,0,1,rm)
 172 #define EOP_STRH_IMM(   rd,rn,offset_8)  EOP_C_AM3_IMM(A_COND_AL,1,0,rn,rd,0,1,offset_8)
 173 #define EOP_STRH_SIMPLE(rd,rn)           EOP_C_AM3_IMM(A_COND_AL,1,0,rn,rd,0,1,0)
 174 #define EOP_STRH_REG(   rd,rn,rm)        EOP_C_AM3_REG(A_COND_AL,1,0,rn,rd,0,1,rm)
 175
 176 /* ldm and stm */
 177 #define EOP_XXM(cond,p,u,s,w,l,rn,list) \
 178         EMIT(((cond)<<28) | (1<<27) | ((p)<<24) | ((u)<<23) | ((s)<<22) | ((w)<<21) | ((l)<<20) | ((rn)<<16) | (list))
 179
 180 #define EOP_STMFD_ST(list) EOP_XXM(A_COND_AL,1,0,0,1,0,13,list)
 181 #define EOP_LDMFD_ST(list) EOP_XXM(A_COND_AL,0,1,0,1,1,13,list)
 182
 183 /* branches */
 184 #define EOP_C_BX(cond,rm) \
 185         EMIT(((cond)<<28) | 0x012fff10 | (rm))
 186
 187 #define EOP_BX(rm) EOP_C_BX(A_COND_AL,rm)
 188
 189 #define EOP_C_B(cond,l,signed_immed_24) \
 190         EMIT(((cond)<<28) | 0x0a000000 | ((l)<<24) | (signed_immed_24))
 191
 192 #define EOP_B( signed_immed_24) EOP_C_B(A_COND_AL,0,signed_immed_24)
 193 #define EOP_BL(signed_immed_24) EOP_C_B(A_COND_AL,1,signed_immed_24)
 194
 195 /* misc */
 196 #define EOP_C_MUL(cond,s,rd,rs,rm) \
 197         EMIT(((cond)<<28) | ((s)<<20) | ((rd)<<16) | ((rs)<<8) | 0x90 | (rm))
 198
 199 #define EOP_C_UMULL(cond,s,rdhi,rdlo,rs,rm) \
 200         EMIT(((cond)<<28) | 0x00800000 | ((s)<<20) | ((rdhi)<<16) | ((rdlo)<<12) | ((rs)<<8) | 0x90 | (rm))
 201
 202 #define EOP_C_SMULL(cond,s,rdhi,rdlo,rs,rm) \
 203         EMIT(((cond)<<28) | 0x00c00000 | ((s)<<20) | ((rdhi)<<16) | ((rdlo)<<12) | ((rs)<<8) | 0x90 | (rm))
 204
 205 #define EOP_MUL(rd,rm,rs) EOP_C_MUL(A_COND_AL,0,rd,rs,rm) // note: rd != rm
 206
 207 #define EOP_C_MRS(cond,rd) \
 208         EMIT(((cond)<<28) | 0x010f0000 | ((rd)<<12))
 209
 210 #define EOP_C_MSR_IMM(cond,ror2,imm) \
 211         EMIT(((cond)<<28) | 0x0328f000 | ((ror2)<<8) | (imm)) // cpsr_f
 212
 213 #define EOP_C_MSR_REG(cond,rm) \
 214         EMIT(((cond)<<28) | 0x0128f000 | (rm)) // cpsr_f
 215
 216 #define EOP_MRS(rd)           EOP_C_MRS(A_COND_AL,rd)
 217 #define EOP_MSR_IMM(ror2,imm) EOP_C_MSR_IMM(A_COND_AL,ror2,imm)
 218 #define EOP_MSR_REG(rm)       EOP_C_MSR_REG(A_COND_AL,rm)
 219
 220
 221 static void emith_op_imm(int cond, int s, int op, int r, unsigned int imm)
 222 {
 223         int ror2, rd = r, rn = r;
 224         u32 v;
 225
 226         if (op == A_OP_MOV)
 227                 rn = 0;
 228         else if (op == A_OP_TST || op == A_OP_TEQ)
 229                 rd = 0;
 230         else if (imm == 0)
 231                 return;
 232
 233         for (v = imm, ror2 = 0; v != 0 || op == A_OP_MOV; v >>= 8, ror2 -= 8/2) {
 234                 /* shift down to get 'best' rot2 */
 235                 for (; v && !(v & 3); v >>= 2)
 236                         ror2--;
 237
 238                 EOP_C_DOP_IMM(cond, op, s, rn, rd, ror2 & 0x0f, v & 0xff);
 239
 240                 if (op == A_OP_MOV) {
 241                         op = A_OP_ORR;
 242                         rn = r;
 243                 }
 244         }
 245 }
 246
 247 #define is_offset_24(val) \
 248         ((val) >= (int)0xff000000 && (val) <= 0x00ffffff)
 249
 250 static int emith_xbranch(int cond, void *target, int is_call)
 251 {
 252         int val = (u32 *)target - (u32 *)tcache_ptr - 2;
 253         int direct = is_offset_24(val);
 254         u32 *start_ptr = (u32 *)tcache_ptr;
 255
 256         if (direct)
 257         {
 258                 EOP_C_B(cond,is_call,val & 0xffffff);           // b, bl target
 259         }
 260         else
 261         {
 262 #ifdef __EPOC32__
 263 //              elprintf(EL_SVP, "emitting indirect jmp %08x->%08x", tcache_ptr, target);
 264                 if (is_call)
 265                         EOP_ADD_IMM(14,15,0,8);                 // add lr,pc,#8
 266                 EOP_C_AM2_IMM(cond,1,0,1,15,15,0);              // ldrcc pc,[pc]
 267                 EOP_MOV_REG_SIMPLE(15,15);                      // mov pc, pc
 268                 EMIT((u32)target);
 269 #else
 270                 // should never happen
 271                 elprintf(EL_STATUS|EL_SVP|EL_ANOMALY, "indirect jmp %08x->%08x", target, tcache_ptr);
 272                 exit(1);
 273 #endif
 274         }
 275
 276         return (u32 *)tcache_ptr - start_ptr;
 277 }
 278
 279
 280 // fake "simple" or "short" jump - using cond insns instead
 281 #define EMITH_SJMP_START(cond) \
 282         (void)(cond)
 283
 284 #define EMITH_SJMP_END(cond) \
 285         (void)(cond)
 286
 287 #define emith_move_r_r(d, s) \
 288         EOP_MOV_REG_SIMPLE(d, s)
 289
 290 #define emith_or_r_r_r_lsl(d, s1, s2, lslimm) \
 291         EOP_ORR_REG(A_COND_AL,0,d,s1,s2,A_AM1_LSL,lslimm)
 292
 293 #define emith_eor_r_r_r_lsl(d, s1, s2, lslimm) \
 294         EOP_EOR_REG(A_COND_AL,0,d,s1,s2,A_AM1_LSL,lslimm)
 295
 296 #define emith_or_r_r_r(d, s1, s2) \
 297         emith_or_r_r_r_lsl(d, s1, s2, 0)
 298
 299 #define emith_eor_r_r_r(d, s1, s2) \
 300         emith_eor_r_r_r_lsl(d, s1, s2, 0)
 301
 302 #define emith_add_r_r(d, s) \
 303         EOP_ADD_REG(A_COND_AL,0,d,d,s,A_AM1_LSL,0)
 304
 305 #define emith_sub_r_r(d, s) \
 306         EOP_SUB_REG(A_COND_AL,0,d,d,s,A_AM1_LSL,0)
 307
 308 #define emith_and_r_r(d, s) \
 309         EOP_AND_REG(A_COND_AL,0,d,d,s,A_AM1_LSL,0)
 310
 311 #define emith_or_r_r(d, s) \
 312         emith_or_r_r_r(d, d, s)
 313
 314 #define emith_eor_r_r(d, s) \
 315         emith_eor_r_r_r(d, d, s)
 316
 317 #define emith_tst_r_r(d, s) \
 318         EOP_TST_REG(A_COND_AL,d,s,A_AM1_LSL,0)
 319
 320 #define emith_teq_r_r(d, s) \
 321         EOP_TEQ_REG(A_COND_AL,d,s,A_AM1_LSL,0)
 322
 323 #define emith_cmp_r_r(d, s) \
 324         EOP_CMP_REG(A_COND_AL,d,s,A_AM1_LSL,0)
 325
 326 #define emith_addf_r_r(d, s) \
 327         EOP_ADD_REG(A_COND_AL,1,d,d,s,A_AM1_LSL,0)
 328
 329 #define emith_subf_r_r(d, s) \
 330         EOP_SUB_REG(A_COND_AL,1,d,d,s,A_AM1_LSL,0)
 331
 332 #define emith_adcf_r_r(d, s) \
 333         EOP_ADC_REG(A_COND_AL,1,d,d,s,A_AM1_LSL,0)
 334
 335 #define emith_sbcf_r_r(d, s) \
 336         EOP_SBC_REG(A_COND_AL,1,d,d,s,A_AM1_LSL,0)
 337
 338 #define emith_move_r_imm(r, imm) \
 339         emith_op_imm(A_COND_AL, 0, A_OP_MOV, r, imm)
 340
 341 #define emith_add_r_imm(r, imm) \
 342         emith_op_imm(A_COND_AL, 0, A_OP_ADD, r, imm)
 343
 344 #define emith_sub_r_imm(r, imm) \
 345         emith_op_imm(A_COND_AL, 0, A_OP_SUB, r, imm)
 346
 347 #define emith_bic_r_imm(r, imm) \
 348         emith_op_imm(A_COND_AL, 0, A_OP_BIC, r, imm)
 349
 350 #define emith_or_r_imm(r, imm) \
 351         emith_op_imm(A_COND_AL, 0, A_OP_ORR, r, imm)
 352
 353 // note: use 8bit imm only
 354 #define emith_tst_r_imm(r, imm) \
 355         emith_op_imm(A_COND_AL, 1, A_OP_TST, r, imm)
 356
 357 #define emith_subf_r_imm(r, imm) \
 358         emith_op_imm(A_COND_AL, 1, A_OP_SUB, r, imm)
 359
 360 #define emith_add_r_imm_c(cond, r, imm) \
 361         emith_op_imm(cond, 0, A_OP_ADD, r, imm)
 362
 363 #define emith_sub_r_imm_c(cond, r, imm) \
 364         emith_op_imm(cond, 0, A_OP_SUB, r, imm)
 365
 366 #define emith_or_r_imm_c(cond, r, imm) \
 367         emith_op_imm(cond, 0, A_OP_ORR, r, imm)
 368
 369 #define emith_bic_r_imm_c(cond, r, imm) \
 370         emith_op_imm(cond, 0, A_OP_BIC, r, imm)
 371
 372 #define emith_lsl(d, s, cnt) \
 373         EOP_MOV_REG(A_COND_AL,0,d,s,A_AM1_LSL,cnt)
 374
 375 #define emith_lsr(d, s, cnt) \
 376         EOP_MOV_REG(A_COND_AL,0,d,s,A_AM1_LSR,cnt)
 377
 378 #define emith_lslf(d, s, cnt) \
 379         EOP_MOV_REG(A_COND_AL,1,d,s,A_AM1_LSL,cnt)
 380
 381 #define emith_asrf(d, s, cnt) \
 382         EOP_MOV_REG(A_COND_AL,1,d,s,A_AM1_ASR,cnt)
 383
 384 #define emith_mul(d, s1, s2) { \
 385         if ((d) != (s1)) /* rd != rm limitation */ \
 386                 EOP_MUL(d, s1, s2); \
 387         else \
 388                 EOP_MUL(d, s2, s1); \
 389 }
 390
 391 #define emith_mul_u64(dlo, dhi, s1, s2) \
 392         EOP_C_UMULL(A_COND_AL,0,dhi,dlo,s1,s2)
 393
 394 #define emith_mul_s64(dlo, dhi, s1, s2) \
 395         EOP_C_SMULL(A_COND_AL,0,dhi,dlo,s1,s2)
 396
 397 // misc
 398 #define emith_ctx_read(r, offs) \
 399         EOP_LDR_IMM(r, CONTEXT_REG, offs)
 400
 401 #define emith_ctx_write(r, offs) \
 402         EOP_STR_IMM(r, CONTEXT_REG, offs)
 403
 404 #define emith_clear_msb(d, s, count) { \
 405         u32 t; \
 406         if ((count) <= 8) { \
 407                 t = (count) - 8; \
 408                 t = (0xff << t) & 0xff; \
 409                 EOP_BIC_IMM(d,s,8/2,t); \
 410         } else if ((count) >= 24) { \
 411                 t = (count) - 24; \
 412                 t = 0xff >> t; \
 413                 EOP_AND_IMM(d,s,0,t); \
 414         } else { \
 415                 EOP_MOV_REG_LSL(d,s,count); \
 416                 EOP_MOV_REG_LSR(d,d,count); \
 417         } \
 418 }
 419
 420 #define emith_sext(d, s, bits) { \
 421         EOP_MOV_REG_LSL(d,s,32 - (bits)); \
 422         EOP_MOV_REG_ASR(d,d,32 - (bits)); \
 423 }
 424
 425 // put bit0 of r0 to carry
 426 #define emith_set_carry(r0) \
 427         EOP_TST_REG(A_COND_AL,r0,r0,A_AM1_LSR,1) /* shift out to carry */ \
 428
 429 // put bit0 of r0 to carry (for subtraction, inverted on ARM)
 430 #define emith_set_carry_sub(r0) { \
 431         int t = rcache_get_tmp(); \
 432         EOP_EOR_IMM(t,r0,0,1); /* invert */ \
 433         EOP_MOV_REG(A_COND_AL,1,t,t,A_AM1_LSR,1); /* shift out to carry */ \
 434         rcache_free_tmp(t); \
 435 }
 436
 437 #define host_arg2reg(rd, arg) \
 438         rd = arg
 439
 440 // upto 4 args
 441 #define emith_pass_arg_r(arg, reg) \
 442         EOP_MOV_REG_SIMPLE(arg, reg)
 443
 444 #define emith_pass_arg_imm(arg, imm) \
 445         emith_move_r_imm(arg, imm)
 446
 447 #define emith_call_cond(cond, target) \
 448         emith_xbranch(cond, target, 1)
 449
 450 #define emith_jump_cond(cond, target) \
 451         emith_xbranch(cond, target, 0)
 452
 453 #define emith_call(target) \
 454         emith_call_cond(A_COND_AL, target)
 455
 456 #define emith_jump(target) \
 457         emith_jump_cond(A_COND_AL, target)
 458
 459 /* SH2 drc specific */
 460 #define emith_sh2_test_t() { \
 461         int r = rcache_get_reg(SHR_SR, RC_GR_READ); \
 462         EOP_TST_IMM(r, 0, 1); \
 463 }
 464
 465 #define emith_sh2_dtbf_loop() { \
 466         int cr, rn;                                                          \
 467         tmp = rcache_get_tmp();                                              \
 468         cr = rcache_get_reg(SHR_SR, RC_GR_RMW);                              \
 469         rn = rcache_get_reg((op >> 8) & 0x0f, RC_GR_RMW);                    \
 470         emith_sub_r_imm(rn, 1);                /* sub rn, #1 */              \
 471         emith_bic_r_imm(cr, 1);                /* bic cr, #1 */              \
 472         emith_sub_r_imm(cr, (cycles+1) << 12); /* sub cr, #(cycles+1)<<12 */ \
 473         cycles = 0;                                                          \
 474         emith_asrf(tmp, cr, 2+12);             /* movs tmp, cr, asr #2+12 */ \
 475         EOP_MOV_IMM_C(A_COND_MI,tmp,0,0);      /* movmi tmp, #0 */           \
 476         emith_lsl(cr, cr, 20);                 /* mov cr, cr, lsl #20 */     \
 477         emith_lsr(cr, cr, 20);                 /* mov cr, cr, lsr #20 */     \
 478         emith_subf_r_r(rn, tmp);               /* subs rn, tmp */            \
 479         EOP_RSB_IMM_C(A_COND_LS,tmp,rn,0,0);   /* rsbls tmp, rn, #0 */       \
 480         EOP_ORR_REG(A_COND_LS,0,cr,cr,tmp,A_AM1_LSL,12+2); /* orrls cr,tmp,lsl #12+2 */\
 481         EOP_ORR_IMM_C(A_COND_LS,cr,cr,0,1);    /* orrls cr, #1 */            \
 482         EOP_MOV_IMM_C(A_COND_LS,rn,0,0);       /* movls rn, #0 */            \
 483         rcache_free_tmp(tmp);                                                \
 484 }
 485