cpu/drc/emit_arm.c

   1 // Basic macros to emit ARM instructions and some utils
   2
   3 // (c) Copyright 2008-2009, Grazvydas "notaz" Ignotas
   4 // Free for non-commercial use.
   5
   6 #define CONTEXT_REG 7
   7
   8 // XXX: tcache_ptr type for SVP and SH2 compilers differs..
   9 #define EMIT_PTR(ptr, x) \
  10         do { \
  11                 *(u32 *)ptr = x; \
  12                 ptr = (void *)((u8 *)ptr + sizeof(u32)); \
  13         } while (0)
  14
  15 #define EMIT(x) EMIT_PTR(tcache_ptr, x)
  16
  17 #define A_R4M  (1 << 4)
  18 #define A_R5M  (1 << 5)
  19 #define A_R6M  (1 << 6)
  20 #define A_R7M  (1 << 7)
  21 #define A_R8M  (1 << 8)
  22 #define A_R9M  (1 << 9)
  23 #define A_R10M (1 << 10)
  24 #define A_R11M (1 << 11)
  25 #define A_R14M (1 << 14)
  26
  27 #define A_COND_AL 0xe
  28 #define A_COND_EQ 0x0
  29 #define A_COND_NE 0x1
  30 #define A_COND_MI 0x4
  31 #define A_COND_PL 0x5
  32 #define A_COND_LE 0xd
  33
  34 /* addressing mode 1 */
  35 #define A_AM1_LSL 0
  36 #define A_AM1_LSR 1
  37 #define A_AM1_ASR 2
  38 #define A_AM1_ROR 3
  39
  40 #define A_AM1_IMM(ror2,imm8)                  (((ror2)<<8) | (imm8) | 0x02000000)
  41 #define A_AM1_REG_XIMM(shift_imm,shift_op,rm) (((shift_imm)<<7) | ((shift_op)<<5) | (rm))
  42 #define A_AM1_REG_XREG(rs,shift_op,rm)        (((rs)<<8) | ((shift_op)<<5) | 0x10 | (rm))
  43
  44 /* data processing op */
  45 #define A_OP_AND 0x0
  46 #define A_OP_EOR 0x1
  47 #define A_OP_SUB 0x2
  48 #define A_OP_RSB 0x3
  49 #define A_OP_ADD 0x4
  50 #define A_OP_TST 0x8
  51 #define A_OP_CMP 0xa
  52 #define A_OP_ORR 0xc
  53 #define A_OP_MOV 0xd
  54 #define A_OP_BIC 0xe
  55
  56 #define EOP_C_DOP_X(cond,op,s,rn,rd,shifter_op) \
  57         EMIT(((cond)<<28) | ((op)<< 21) | ((s)<<20) | ((rn)<<16) | ((rd)<<12) | (shifter_op))
  58
  59 #define EOP_C_DOP_IMM(     cond,op,s,rn,rd,ror2,imm8)             EOP_C_DOP_X(cond,op,s,rn,rd,A_AM1_IMM(ror2,imm8))
  60 #define EOP_C_DOP_REG_XIMM(cond,op,s,rn,rd,shift_imm,shift_op,rm) EOP_C_DOP_X(cond,op,s,rn,rd,A_AM1_REG_XIMM(shift_imm,shift_op,rm))
  61 #define EOP_C_DOP_REG_XREG(cond,op,s,rn,rd,rs,       shift_op,rm) EOP_C_DOP_X(cond,op,s,rn,rd,A_AM1_REG_XREG(rs,       shift_op,rm))
  62
  63 #define EOP_MOV_IMM(rd,   ror2,imm8) EOP_C_DOP_IMM(A_COND_AL,A_OP_MOV,0, 0,rd,ror2,imm8)
  64 #define EOP_ORR_IMM(rd,rn,ror2,imm8) EOP_C_DOP_IMM(A_COND_AL,A_OP_ORR,0,rn,rd,ror2,imm8)
  65 #define EOP_ADD_IMM(rd,rn,ror2,imm8) EOP_C_DOP_IMM(A_COND_AL,A_OP_ADD,0,rn,rd,ror2,imm8)
  66 #define EOP_BIC_IMM(rd,rn,ror2,imm8) EOP_C_DOP_IMM(A_COND_AL,A_OP_BIC,0,rn,rd,ror2,imm8)
  67 #define EOP_AND_IMM(rd,rn,ror2,imm8) EOP_C_DOP_IMM(A_COND_AL,A_OP_AND,0,rn,rd,ror2,imm8)
  68 #define EOP_SUB_IMM(rd,rn,ror2,imm8) EOP_C_DOP_IMM(A_COND_AL,A_OP_SUB,0,rn,rd,ror2,imm8)
  69 #define EOP_TST_IMM(   rn,ror2,imm8) EOP_C_DOP_IMM(A_COND_AL,A_OP_TST,1,rn, 0,ror2,imm8)
  70 #define EOP_CMP_IMM(   rn,ror2,imm8) EOP_C_DOP_IMM(A_COND_AL,A_OP_CMP,1,rn, 0,ror2,imm8)
  71 #define EOP_RSB_IMM(rd,rn,ror2,imm8) EOP_C_DOP_IMM(A_COND_AL,A_OP_RSB,0,rn,rd,ror2,imm8)
  72
  73 #define EOP_MOV_REG(s,   rd,shift_imm,shift_op,rm) EOP_C_DOP_REG_XIMM(A_COND_AL,A_OP_MOV,s, 0,rd,shift_imm,shift_op,rm)
  74 #define EOP_ORR_REG(s,rn,rd,shift_imm,shift_op,rm) EOP_C_DOP_REG_XIMM(A_COND_AL,A_OP_ORR,s,rn,rd,shift_imm,shift_op,rm)
  75 #define EOP_ADD_REG(s,rn,rd,shift_imm,shift_op,rm) EOP_C_DOP_REG_XIMM(A_COND_AL,A_OP_ADD,s,rn,rd,shift_imm,shift_op,rm)
  76 #define EOP_TST_REG(  rn,   shift_imm,shift_op,rm) EOP_C_DOP_REG_XIMM(A_COND_AL,A_OP_TST,1,rn, 0,shift_imm,shift_op,rm)
  77
  78 #define EOP_MOV_REG2(s,   rd,rs,shift_op,rm) EOP_C_DOP_REG_XREG(A_COND_AL,A_OP_MOV,s, 0,rd,rs,shift_op,rm)
  79 #define EOP_ADD_REG2(s,rn,rd,rs,shift_op,rm) EOP_C_DOP_REG_XREG(A_COND_AL,A_OP_ADD,s,rn,rd,rs,shift_op,rm)
  80 #define EOP_SUB_REG2(s,rn,rd,rs,shift_op,rm) EOP_C_DOP_REG_XREG(A_COND_AL,A_OP_SUB,s,rn,rd,rs,shift_op,rm)
  81
  82 #define EOP_MOV_REG_SIMPLE(rd,rm)           EOP_MOV_REG(0,rd,0,A_AM1_LSL,rm)
  83 #define EOP_MOV_REG_LSL(rd,   rm,shift_imm) EOP_MOV_REG(0,rd,shift_imm,A_AM1_LSL,rm)
  84 #define EOP_MOV_REG_LSR(rd,   rm,shift_imm) EOP_MOV_REG(0,rd,shift_imm,A_AM1_LSR,rm)
  85 #define EOP_MOV_REG_ASR(rd,   rm,shift_imm) EOP_MOV_REG(0,rd,shift_imm,A_AM1_ASR,rm)
  86 #define EOP_MOV_REG_ROR(rd,   rm,shift_imm) EOP_MOV_REG(0,rd,shift_imm,A_AM1_ROR,rm)
  87
  88 #define EOP_ORR_REG_SIMPLE(rd,rm)           EOP_ORR_REG(0,rd,rd,0,A_AM1_LSL,rm)
  89 #define EOP_ORR_REG_LSL(rd,rn,rm,shift_imm) EOP_ORR_REG(0,rn,rd,shift_imm,A_AM1_LSL,rm)
  90 #define EOP_ORR_REG_LSR(rd,rn,rm,shift_imm) EOP_ORR_REG(0,rn,rd,shift_imm,A_AM1_LSR,rm)
  91 #define EOP_ORR_REG_ASR(rd,rn,rm,shift_imm) EOP_ORR_REG(0,rn,rd,shift_imm,A_AM1_ASR,rm)
  92 #define EOP_ORR_REG_ROR(rd,rn,rm,shift_imm) EOP_ORR_REG(0,rn,rd,shift_imm,A_AM1_ROR,rm)
  93
  94 #define EOP_ADD_REG_SIMPLE(rd,rm)           EOP_ADD_REG(0,rd,rd,0,A_AM1_LSL,rm)
  95 #define EOP_ADD_REG_LSL(rd,rn,rm,shift_imm) EOP_ADD_REG(0,rn,rd,shift_imm,A_AM1_LSL,rm)
  96 #define EOP_ADD_REG_LSR(rd,rn,rm,shift_imm) EOP_ADD_REG(0,rn,rd,shift_imm,A_AM1_LSR,rm)
  97
  98 #define EOP_TST_REG_SIMPLE(rn,rm)           EOP_TST_REG(  rn,   0,A_AM1_LSL,rm)
  99
 100 #define EOP_MOV_REG2_LSL(rd,   rm,rs)       EOP_MOV_REG2(0,   rd,rs,A_AM1_LSL,rm)
 101 #define EOP_MOV_REG2_ROR(rd,   rm,rs)       EOP_MOV_REG2(0,   rd,rs,A_AM1_ROR,rm)
 102 #define EOP_ADD_REG2_LSL(rd,rn,rm,rs)       EOP_ADD_REG2(0,rn,rd,rs,A_AM1_LSL,rm)
 103 #define EOP_SUB_REG2_LSL(rd,rn,rm,rs)       EOP_SUB_REG2(0,rn,rd,rs,A_AM1_LSL,rm)
 104
 105 /* addressing mode 2 */
 106 #define EOP_C_AM2_IMM(cond,u,b,l,rn,rd,offset_12) \
 107         EMIT(((cond)<<28) | 0x05000000 | ((u)<<23) | ((b)<<22) | ((l)<<20) | ((rn)<<16) | ((rd)<<12) | (offset_12))
 108
 109 /* addressing mode 3 */
 110 #define EOP_C_AM3(cond,u,r,l,rn,rd,s,h,immed_reg) \
 111         EMIT(((cond)<<28) | 0x01000090 | ((u)<<23) | ((r)<<22) | ((l)<<20) | ((rn)<<16) | ((rd)<<12) | \
 112                         ((s)<<6) | ((h)<<5) | (immed_reg))
 113
 114 #define EOP_C_AM3_IMM(cond,u,l,rn,rd,s,h,offset_8) EOP_C_AM3(cond,u,1,l,rn,rd,s,h,(((offset_8)&0xf0)<<4)|((offset_8)&0xf))
 115
 116 #define EOP_C_AM3_REG(cond,u,l,rn,rd,s,h,rm)       EOP_C_AM3(cond,u,0,l,rn,rd,s,h,rm)
 117
 118 /* ldr and str */
 119 #define EOP_LDR_IMM(   rd,rn,offset_12) EOP_C_AM2_IMM(A_COND_AL,1,0,1,rn,rd,offset_12)
 120 #define EOP_LDR_NEGIMM(rd,rn,offset_12) EOP_C_AM2_IMM(A_COND_AL,0,0,1,rn,rd,offset_12)
 121 #define EOP_LDR_SIMPLE(rd,rn)           EOP_C_AM2_IMM(A_COND_AL,1,0,1,rn,rd,0)
 122 #define EOP_STR_IMM(   rd,rn,offset_12) EOP_C_AM2_IMM(A_COND_AL,1,0,0,rn,rd,offset_12)
 123 #define EOP_STR_SIMPLE(rd,rn)           EOP_C_AM2_IMM(A_COND_AL,1,0,0,rn,rd,0)
 124
 125 #define EOP_LDRH_IMM(   rd,rn,offset_8)  EOP_C_AM3_IMM(A_COND_AL,1,1,rn,rd,0,1,offset_8)
 126 #define EOP_LDRH_SIMPLE(rd,rn)           EOP_C_AM3_IMM(A_COND_AL,1,1,rn,rd,0,1,0)
 127 #define EOP_LDRH_REG(   rd,rn,rm)        EOP_C_AM3_REG(A_COND_AL,1,1,rn,rd,0,1,rm)
 128 #define EOP_STRH_IMM(   rd,rn,offset_8)  EOP_C_AM3_IMM(A_COND_AL,1,0,rn,rd,0,1,offset_8)
 129 #define EOP_STRH_SIMPLE(rd,rn)           EOP_C_AM3_IMM(A_COND_AL,1,0,rn,rd,0,1,0)
 130 #define EOP_STRH_REG(   rd,rn,rm)        EOP_C_AM3_REG(A_COND_AL,1,0,rn,rd,0,1,rm)
 131
 132 /* ldm and stm */
 133 #define EOP_XXM(cond,p,u,s,w,l,rn,list) \
 134         EMIT(((cond)<<28) | (1<<27) | ((p)<<24) | ((u)<<23) | ((s)<<22) | ((w)<<21) | ((l)<<20) | ((rn)<<16) | (list))
 135
 136 #define EOP_STMFD_ST(list) EOP_XXM(A_COND_AL,1,0,0,1,0,13,list)
 137 #define EOP_LDMFD_ST(list) EOP_XXM(A_COND_AL,0,1,0,1,1,13,list)
 138
 139 /* branches */
 140 #define EOP_C_BX(cond,rm) \
 141         EMIT(((cond)<<28) | 0x012fff10 | (rm))
 142
 143 #define EOP_BX(rm) EOP_C_BX(A_COND_AL,rm)
 144
 145 #define EOP_C_B(cond,l,signed_immed_24) \
 146         EMIT(((cond)<<28) | 0x0a000000 | ((l)<<24) | (signed_immed_24))
 147
 148 #define EOP_B( signed_immed_24) EOP_C_B(A_COND_AL,0,signed_immed_24)
 149 #define EOP_BL(signed_immed_24) EOP_C_B(A_COND_AL,1,signed_immed_24)
 150
 151 /* misc */
 152 #define EOP_C_MUL(cond,s,rd,rs,rm) \
 153         EMIT(((cond)<<28) | ((s)<<20) | ((rd)<<16) | ((rs)<<8) | 0x90 | (rm))
 154
 155 #define EOP_MUL(rd,rm,rs) EOP_C_MUL(A_COND_AL,0,rd,rs,rm) // note: rd != rm
 156
 157 #define EOP_C_MRS(cond,rd) \
 158         EMIT(((cond)<<28) | 0x010f0000 | ((rd)<<12))
 159
 160 #define EOP_C_MSR_IMM(cond,ror2,imm) \
 161         EMIT(((cond)<<28) | 0x0328f000 | ((ror2)<<8) | (imm)) // cpsr_f
 162
 163 #define EOP_C_MSR_REG(cond,rm) \
 164         EMIT(((cond)<<28) | 0x0128f000 | (rm)) // cpsr_f
 165
 166 #define EOP_MRS(rd)           EOP_C_MRS(A_COND_AL,rd)
 167 #define EOP_MSR_IMM(ror2,imm) EOP_C_MSR_IMM(A_COND_AL,ror2,imm)
 168 #define EOP_MSR_REG(rm)       EOP_C_MSR_REG(A_COND_AL,rm)
 169
 170
 171 static void emith_op_imm(int cond, int op, int r, unsigned int imm)
 172 {
 173         u32 v, ror2;
 174
 175         if (imm == 0 && op != A_OP_MOV)
 176                 return;
 177
 178         /* shift down to get starting rot2 */
 179         for (v = imm, ror2 = 0; v && !(v & 3); v >>= 2)
 180                 ror2++;
 181         ror2 = 16 - ror2;
 182
 183         EOP_C_DOP_IMM(cond, op, 0, op == A_OP_MOV ? 0 : r, r, ror2 & 0x0f, v & 0xff);
 184         if (op == A_OP_MOV)
 185                 op = A_OP_ORR;
 186
 187         v >>= 8;
 188         if (v & 0xff)
 189                 EOP_C_DOP_IMM(cond, op, 0, r, r, (ror2 - 8/2) & 0x0f, v & 0xff);
 190         v >>= 8;
 191         if (v & 0xff)
 192                 EOP_C_DOP_IMM(cond, op, 0, r, r, (ror2 - 16/2) & 0x0f, v & 0xff);
 193         v >>= 8;
 194         if (v & 0xff)
 195                 EOP_C_DOP_IMM(cond, op, 0, r, r, (ror2 - 24/2) & 0x0f, v & 0xff);
 196 }
 197
 198 #define is_offset_24(val) \
 199         ((val) >= (int)0xff000000 && (val) <= 0x00ffffff)
 200
 201 static int emith_xbranch(int cond, void *target, int is_call)
 202 {
 203         int val = (u32 *)target - (u32 *)tcache_ptr - 2;
 204         int direct = is_offset_24(val);
 205         u32 *start_ptr = (u32 *)tcache_ptr;
 206
 207         if (direct)
 208         {
 209                 EOP_C_B(cond,is_call,val & 0xffffff);           // b, bl target
 210         }
 211         else
 212         {
 213 #ifdef __EPOC32__
 214 //              elprintf(EL_SVP, "emitting indirect jmp %08x->%08x", tcache_ptr, target);
 215                 if (is_call)
 216                         EOP_ADD_IMM(14,15,0,8);                 // add lr,pc,#8
 217                 EOP_C_AM2_IMM(cond,1,0,1,15,15,0);              // ldrcc pc,[pc]
 218                 EOP_MOV_REG_SIMPLE(15,15);                      // mov pc, pc
 219                 EMIT((u32)target);
 220 #else
 221                 // should never happen
 222                 elprintf(EL_STATUS|EL_SVP|EL_ANOMALY, "indirect jmp %08x->%08x", target, tcache_ptr);
 223                 exit(1);
 224 #endif
 225         }
 226
 227         return (u32 *)tcache_ptr - start_ptr;
 228 }
 229
 230 static void handle_caches(void)
 231 {
 232 #ifdef ARM
 233         extern void cache_flush_d_inval_i(const void *start_addr, const void *end_addr);
 234         cache_flush_d_inval_i(tcache, tcache_ptr);
 235 #endif
 236 }
 237
 238
 239 #define EMITH_CONDITIONAL(code, is_nonzero) { \
 240         u32 val, cond, *ptr; \
 241         cond = (is_nonzero) ? A_COND_NE : A_COND_EQ; \
 242         ptr = (void *)tcache_ptr; \
 243         tcache_ptr = (void *)(ptr + 1); \
 244         code; \
 245         val = (u32 *)tcache_ptr - (ptr + 2); \
 246         EMIT_PTR(ptr, ((cond)<<28) | 0x0a000000 | (val & 0xffffff)); \
 247 }
 248
 249 #define emith_move_r_r(dst, src) \
 250         EOP_MOV_REG_SIMPLE(dst, src)
 251
 252 #define emith_move_r_imm(r, imm) \
 253         emith_op_imm(A_COND_AL, A_OP_MOV, r, imm)
 254
 255 #define emith_add_r_imm(r, imm) \
 256         emith_op_imm(A_COND_AL, A_OP_ADD, r, imm)
 257
 258 #define emith_sub_r_imm(r, imm) \
 259         emith_op_imm(A_COND_AL, A_OP_SUB, r, imm)
 260
 261 #define emith_ctx_read(r, offs) \
 262         EOP_LDR_IMM(r, CONTEXT_REG, offs)
 263
 264 #define emith_ctx_write(r, offs) \
 265         EOP_STR_IMM(r, CONTEXT_REG, offs)
 266
 267 #define emith_ctx_sub(val, offs) { \
 268         emith_ctx_read(0, offs); \
 269         emith_sub_r_imm(0, val); \
 270         emith_ctx_write(0, offs); \
 271 }
 272
 273 // upto 4 args
 274 #define emith_pass_arg_r(arg, reg) \
 275         EOP_MOV_REG_SIMPLE(arg, reg)
 276
 277 #define emith_pass_arg_imm(arg, imm) \
 278         emith_move_r_imm(arg, imm)
 279
 280 #define emith_call_cond(cond, target) \
 281         emith_xbranch(cond, target, 1)
 282
 283 #define emith_jump_cond(cond, target) \
 284         emith_xbranch(cond, target, 0)
 285
 286 #define emith_call(target) \
 287         emith_call_cond(A_COND_AL, target)
 288
 289 #define emith_jump(target) \
 290         emith_jump_cond(A_COND_AL, target)
 291
 292 /* SH2 drc specific */
 293 #define emith_test_t() { \
 294         int r = reg_map_g2h[SHR_SR]; \
 295         if (r == -1) { \
 296                 emith_ctx_read(0, SHR_SR * 4); \
 297                 r = 0; \
 298         } \
 299         EOP_TST_IMM(r, 0, 1); \
 300 }
 301
 302