cpu/drc/emit_arm.c

   1 /*
   2  * Basic macros to emit ARM instructions and some utils
   3  * Copyright (C) 2008,2009,2010 notaz
   4  *
   5  * This work is licensed under the terms of MAME license.
   6  * See COPYING file in the top-level directory.
   7  */
   8 #define CONTEXT_REG 11
   9
  10 // XXX: tcache_ptr type for SVP and SH2 compilers differs..
  11 #define EMIT_PTR(ptr, x) \
  12         do { \
  13                 *(u32 *)ptr = x; \
  14                 ptr = (void *)((u8 *)ptr + sizeof(u32)); \
  15                 COUNT_OP; \
  16         } while (0)
  17
  18 #define EMIT(x) EMIT_PTR(tcache_ptr, x)
  19
  20 #define A_R4M  (1 << 4)
  21 #define A_R5M  (1 << 5)
  22 #define A_R6M  (1 << 6)
  23 #define A_R7M  (1 << 7)
  24 #define A_R8M  (1 << 8)
  25 #define A_R9M  (1 << 9)
  26 #define A_R10M (1 << 10)
  27 #define A_R11M (1 << 11)
  28 #define A_R14M (1 << 14)
  29 #define A_R15M (1 << 15)
  30
  31 #define A_COND_AL 0xe
  32 #define A_COND_EQ 0x0
  33 #define A_COND_NE 0x1
  34 #define A_COND_HS 0x2
  35 #define A_COND_LO 0x3
  36 #define A_COND_MI 0x4
  37 #define A_COND_PL 0x5
  38 #define A_COND_VS 0x6
  39 #define A_COND_VC 0x7
  40 #define A_COND_HI 0x8
  41 #define A_COND_LS 0x9
  42 #define A_COND_GE 0xa
  43 #define A_COND_LT 0xb
  44 #define A_COND_GT 0xc
  45 #define A_COND_LE 0xd
  46 #define A_COND_CS A_COND_HS
  47 #define A_COND_CC A_COND_LO
  48
  49 /* unified conditions */
  50 #define DCOND_EQ A_COND_EQ
  51 #define DCOND_NE A_COND_NE
  52 #define DCOND_MI A_COND_MI
  53 #define DCOND_PL A_COND_PL
  54 #define DCOND_HI A_COND_HI
  55 #define DCOND_HS A_COND_HS
  56 #define DCOND_LO A_COND_LO
  57 #define DCOND_GE A_COND_GE
  58 #define DCOND_GT A_COND_GT
  59 #define DCOND_LT A_COND_LT
  60 #define DCOND_LS A_COND_LS
  61 #define DCOND_LE A_COND_LE
  62 #define DCOND_VS A_COND_VS
  63 #define DCOND_VC A_COND_VC
  64
  65 /* addressing mode 1 */
  66 #define A_AM1_LSL 0
  67 #define A_AM1_LSR 1
  68 #define A_AM1_ASR 2
  69 #define A_AM1_ROR 3
  70
  71 #define A_AM1_IMM(ror2,imm8)                  (((ror2)<<8) | (imm8) | 0x02000000)
  72 #define A_AM1_REG_XIMM(shift_imm,shift_op,rm) (((shift_imm)<<7) | ((shift_op)<<5) | (rm))
  73 #define A_AM1_REG_XREG(rs,shift_op,rm)        (((rs)<<8) | ((shift_op)<<5) | 0x10 | (rm))
  74
  75 /* data processing op */
  76 #define A_OP_AND 0x0
  77 #define A_OP_EOR 0x1
  78 #define A_OP_SUB 0x2
  79 #define A_OP_RSB 0x3
  80 #define A_OP_ADD 0x4
  81 #define A_OP_ADC 0x5
  82 #define A_OP_SBC 0x6
  83 #define A_OP_RSC 0x7
  84 #define A_OP_TST 0x8
  85 #define A_OP_TEQ 0x9
  86 #define A_OP_CMP 0xa
  87 #define A_OP_CMN 0xa
  88 #define A_OP_ORR 0xc
  89 #define A_OP_MOV 0xd
  90 #define A_OP_BIC 0xe
  91 #define A_OP_MVN 0xf
  92
  93 #define EOP_C_DOP_X(cond,op,s,rn,rd,shifter_op) \
  94         EMIT(((cond)<<28) | ((op)<< 21) | ((s)<<20) | ((rn)<<16) | ((rd)<<12) | (shifter_op))
  95
  96 #define EOP_C_DOP_IMM(     cond,op,s,rn,rd,ror2,imm8)             EOP_C_DOP_X(cond,op,s,rn,rd,A_AM1_IMM(ror2,imm8))
  97 #define EOP_C_DOP_REG_XIMM(cond,op,s,rn,rd,shift_imm,shift_op,rm) EOP_C_DOP_X(cond,op,s,rn,rd,A_AM1_REG_XIMM(shift_imm,shift_op,rm))
  98 #define EOP_C_DOP_REG_XREG(cond,op,s,rn,rd,rs,       shift_op,rm) EOP_C_DOP_X(cond,op,s,rn,rd,A_AM1_REG_XREG(rs,       shift_op,rm))
  99
 100 #define EOP_MOV_IMM(rd,   ror2,imm8) EOP_C_DOP_IMM(A_COND_AL,A_OP_MOV,0, 0,rd,ror2,imm8)
 101 #define EOP_MVN_IMM(rd,   ror2,imm8) EOP_C_DOP_IMM(A_COND_AL,A_OP_MVN,0, 0,rd,ror2,imm8)
 102 #define EOP_ORR_IMM(rd,rn,ror2,imm8) EOP_C_DOP_IMM(A_COND_AL,A_OP_ORR,0,rn,rd,ror2,imm8)
 103 #define EOP_EOR_IMM(rd,rn,ror2,imm8) EOP_C_DOP_IMM(A_COND_AL,A_OP_EOR,0,rn,rd,ror2,imm8)
 104 #define EOP_ADD_IMM(rd,rn,ror2,imm8) EOP_C_DOP_IMM(A_COND_AL,A_OP_ADD,0,rn,rd,ror2,imm8)
 105 #define EOP_BIC_IMM(rd,rn,ror2,imm8) EOP_C_DOP_IMM(A_COND_AL,A_OP_BIC,0,rn,rd,ror2,imm8)
 106 #define EOP_AND_IMM(rd,rn,ror2,imm8) EOP_C_DOP_IMM(A_COND_AL,A_OP_AND,0,rn,rd,ror2,imm8)
 107 #define EOP_SUB_IMM(rd,rn,ror2,imm8) EOP_C_DOP_IMM(A_COND_AL,A_OP_SUB,0,rn,rd,ror2,imm8)
 108 #define EOP_TST_IMM(   rn,ror2,imm8) EOP_C_DOP_IMM(A_COND_AL,A_OP_TST,1,rn, 0,ror2,imm8)
 109 #define EOP_CMP_IMM(   rn,ror2,imm8) EOP_C_DOP_IMM(A_COND_AL,A_OP_CMP,1,rn, 0,ror2,imm8)
 110 #define EOP_RSB_IMM(rd,rn,ror2,imm8) EOP_C_DOP_IMM(A_COND_AL,A_OP_RSB,0,rn,rd,ror2,imm8)
 111
 112 #define EOP_MOV_IMM_C(cond,rd,   ror2,imm8) EOP_C_DOP_IMM(cond,A_OP_MOV,0, 0,rd,ror2,imm8)
 113 #define EOP_ORR_IMM_C(cond,rd,rn,ror2,imm8) EOP_C_DOP_IMM(cond,A_OP_ORR,0,rn,rd,ror2,imm8)
 114 #define EOP_RSB_IMM_C(cond,rd,rn,ror2,imm8) EOP_C_DOP_IMM(cond,A_OP_RSB,0,rn,rd,ror2,imm8)
 115
 116 #define EOP_MOV_REG(cond,s,rd,   rm,shift_op,shift_imm) EOP_C_DOP_REG_XIMM(cond,A_OP_MOV,s, 0,rd,shift_imm,shift_op,rm)
 117 #define EOP_MVN_REG(cond,s,rd,   rm,shift_op,shift_imm) EOP_C_DOP_REG_XIMM(cond,A_OP_MVN,s, 0,rd,shift_imm,shift_op,rm)
 118 #define EOP_ORR_REG(cond,s,rd,rn,rm,shift_op,shift_imm) EOP_C_DOP_REG_XIMM(cond,A_OP_ORR,s,rn,rd,shift_imm,shift_op,rm)
 119 #define EOP_ADD_REG(cond,s,rd,rn,rm,shift_op,shift_imm) EOP_C_DOP_REG_XIMM(cond,A_OP_ADD,s,rn,rd,shift_imm,shift_op,rm)
 120 #define EOP_ADC_REG(cond,s,rd,rn,rm,shift_op,shift_imm) EOP_C_DOP_REG_XIMM(cond,A_OP_ADC,s,rn,rd,shift_imm,shift_op,rm)
 121 #define EOP_SUB_REG(cond,s,rd,rn,rm,shift_op,shift_imm) EOP_C_DOP_REG_XIMM(cond,A_OP_SUB,s,rn,rd,shift_imm,shift_op,rm)
 122 #define EOP_SBC_REG(cond,s,rd,rn,rm,shift_op,shift_imm) EOP_C_DOP_REG_XIMM(cond,A_OP_SBC,s,rn,rd,shift_imm,shift_op,rm)
 123 #define EOP_AND_REG(cond,s,rd,rn,rm,shift_op,shift_imm) EOP_C_DOP_REG_XIMM(cond,A_OP_AND,s,rn,rd,shift_imm,shift_op,rm)
 124 #define EOP_EOR_REG(cond,s,rd,rn,rm,shift_op,shift_imm) EOP_C_DOP_REG_XIMM(cond,A_OP_EOR,s,rn,rd,shift_imm,shift_op,rm)
 125 #define EOP_CMP_REG(cond,     rn,rm,shift_op,shift_imm) EOP_C_DOP_REG_XIMM(cond,A_OP_CMP,1,rn, 0,shift_imm,shift_op,rm)
 126 #define EOP_TST_REG(cond,     rn,rm,shift_op,shift_imm) EOP_C_DOP_REG_XIMM(cond,A_OP_TST,1,rn, 0,shift_imm,shift_op,rm)
 127 #define EOP_TEQ_REG(cond,     rn,rm,shift_op,shift_imm) EOP_C_DOP_REG_XIMM(cond,A_OP_TEQ,1,rn, 0,shift_imm,shift_op,rm)
 128
 129 #define EOP_MOV_REG2(s,rd,   rm,shift_op,rs) EOP_C_DOP_REG_XREG(A_COND_AL,A_OP_MOV,s, 0,rd,rs,shift_op,rm)
 130 #define EOP_ADD_REG2(s,rd,rn,rm,shift_op,rs) EOP_C_DOP_REG_XREG(A_COND_AL,A_OP_ADD,s,rn,rd,rs,shift_op,rm)
 131 #define EOP_SUB_REG2(s,rd,rn,rm,shift_op,rs) EOP_C_DOP_REG_XREG(A_COND_AL,A_OP_SUB,s,rn,rd,rs,shift_op,rm)
 132
 133 #define EOP_MOV_REG_SIMPLE(rd,rm)           EOP_MOV_REG(A_COND_AL,0,rd,rm,A_AM1_LSL,0)
 134 #define EOP_MOV_REG_LSL(rd,   rm,shift_imm) EOP_MOV_REG(A_COND_AL,0,rd,rm,A_AM1_LSL,shift_imm)
 135 #define EOP_MOV_REG_LSR(rd,   rm,shift_imm) EOP_MOV_REG(A_COND_AL,0,rd,rm,A_AM1_LSR,shift_imm)
 136 #define EOP_MOV_REG_ASR(rd,   rm,shift_imm) EOP_MOV_REG(A_COND_AL,0,rd,rm,A_AM1_ASR,shift_imm)
 137 #define EOP_MOV_REG_ROR(rd,   rm,shift_imm) EOP_MOV_REG(A_COND_AL,0,rd,rm,A_AM1_ROR,shift_imm)
 138
 139 #define EOP_ORR_REG_SIMPLE(rd,rm)           EOP_ORR_REG(A_COND_AL,0,rd,rd,rm,A_AM1_LSL,0)
 140 #define EOP_ORR_REG_LSL(rd,rn,rm,shift_imm) EOP_ORR_REG(A_COND_AL,0,rd,rn,rm,A_AM1_LSL,shift_imm)
 141 #define EOP_ORR_REG_LSR(rd,rn,rm,shift_imm) EOP_ORR_REG(A_COND_AL,0,rd,rn,rm,A_AM1_LSR,shift_imm)
 142 #define EOP_ORR_REG_ASR(rd,rn,rm,shift_imm) EOP_ORR_REG(A_COND_AL,0,rd,rn,rm,A_AM1_ASR,shift_imm)
 143 #define EOP_ORR_REG_ROR(rd,rn,rm,shift_imm) EOP_ORR_REG(A_COND_AL,0,rd,rn,rm,A_AM1_ROR,shift_imm)
 144
 145 #define EOP_ADD_REG_SIMPLE(rd,rm)           EOP_ADD_REG(A_COND_AL,0,rd,rd,rm,A_AM1_LSL,0)
 146 #define EOP_ADD_REG_LSL(rd,rn,rm,shift_imm) EOP_ADD_REG(A_COND_AL,0,rd,rn,rm,A_AM1_LSL,shift_imm)
 147 #define EOP_ADD_REG_LSR(rd,rn,rm,shift_imm) EOP_ADD_REG(A_COND_AL,0,rd,rn,rm,A_AM1_LSR,shift_imm)
 148
 149 #define EOP_TST_REG_SIMPLE(rn,rm)           EOP_TST_REG(A_COND_AL,  rn,   0,A_AM1_LSL,rm)
 150
 151 #define EOP_MOV_REG2_LSL(rd,   rm,rs)       EOP_MOV_REG2(0,rd,   rm,A_AM1_LSL,rs)
 152 #define EOP_MOV_REG2_ROR(rd,   rm,rs)       EOP_MOV_REG2(0,rd,   rm,A_AM1_ROR,rs)
 153 #define EOP_ADD_REG2_LSL(rd,rn,rm,rs)       EOP_ADD_REG2(0,rd,rn,rm,A_AM1_LSL,rs)
 154 #define EOP_SUB_REG2_LSL(rd,rn,rm,rs)       EOP_SUB_REG2(0,rd,rn,rm,A_AM1_LSL,rs)
 155
 156 /* addressing mode 2 */
 157 #define EOP_C_AM2_IMM(cond,u,b,l,rn,rd,offset_12) \
 158         EMIT(((cond)<<28) | 0x05000000 | ((u)<<23) | ((b)<<22) | ((l)<<20) | ((rn)<<16) | ((rd)<<12) | (offset_12))
 159
 160 #define EOP_C_AM2_REG(cond,u,b,l,rn,rd,shift_imm,shift_op,rm) \
 161         EMIT(((cond)<<28) | 0x07000000 | ((u)<<23) | ((b)<<22) | ((l)<<20) | ((rn)<<16) | ((rd)<<12) | \
 162                 ((shift_imm)<<7) | ((shift_op)<<5) | (rm))
 163
 164 /* addressing mode 3 */
 165 #define EOP_C_AM3(cond,u,r,l,rn,rd,s,h,immed_reg) \
 166         EMIT(((cond)<<28) | 0x01000090 | ((u)<<23) | ((r)<<22) | ((l)<<20) | ((rn)<<16) | ((rd)<<12) | \
 167                         ((s)<<6) | ((h)<<5) | (immed_reg))
 168
 169 #define EOP_C_AM3_IMM(cond,u,l,rn,rd,s,h,offset_8) EOP_C_AM3(cond,u,1,l,rn,rd,s,h,(((offset_8)&0xf0)<<4)|((offset_8)&0xf))
 170
 171 #define EOP_C_AM3_REG(cond,u,l,rn,rd,s,h,rm)       EOP_C_AM3(cond,u,0,l,rn,rd,s,h,rm)
 172
 173 /* ldr and str */
 174 #define EOP_LDR_IMM2(cond,rd,rn,offset_12)  EOP_C_AM2_IMM(cond,1,0,1,rn,rd,offset_12)
 175 #define EOP_LDRB_IMM2(cond,rd,rn,offset_12) EOP_C_AM2_IMM(cond,1,1,1,rn,rd,offset_12)
 176
 177 #define EOP_LDR_IMM(   rd,rn,offset_12) EOP_C_AM2_IMM(A_COND_AL,1,0,1,rn,rd,offset_12)
 178 #define EOP_LDR_NEGIMM(rd,rn,offset_12) EOP_C_AM2_IMM(A_COND_AL,0,0,1,rn,rd,offset_12)
 179 #define EOP_LDR_SIMPLE(rd,rn)           EOP_C_AM2_IMM(A_COND_AL,1,0,1,rn,rd,0)
 180 #define EOP_STR_IMM(   rd,rn,offset_12) EOP_C_AM2_IMM(A_COND_AL,1,0,0,rn,rd,offset_12)
 181 #define EOP_STR_SIMPLE(rd,rn)           EOP_C_AM2_IMM(A_COND_AL,1,0,0,rn,rd,0)
 182
 183 #define EOP_LDR_REG_LSL(cond,rd,rn,rm,shift_imm) EOP_C_AM2_REG(cond,1,0,1,rn,rd,shift_imm,A_AM1_LSL,rm)
 184
 185 #define EOP_LDRH_IMM2(cond,rd,rn,offset_8)  EOP_C_AM3_IMM(cond,1,1,rn,rd,0,1,offset_8)
 186
 187 #define EOP_LDRH_IMM(   rd,rn,offset_8)  EOP_C_AM3_IMM(A_COND_AL,1,1,rn,rd,0,1,offset_8)
 188 #define EOP_LDRH_SIMPLE(rd,rn)           EOP_C_AM3_IMM(A_COND_AL,1,1,rn,rd,0,1,0)
 189 #define EOP_LDRH_REG(   rd,rn,rm)        EOP_C_AM3_REG(A_COND_AL,1,1,rn,rd,0,1,rm)
 190 #define EOP_STRH_IMM(   rd,rn,offset_8)  EOP_C_AM3_IMM(A_COND_AL,1,0,rn,rd,0,1,offset_8)
 191 #define EOP_STRH_SIMPLE(rd,rn)           EOP_C_AM3_IMM(A_COND_AL,1,0,rn,rd,0,1,0)
 192 #define EOP_STRH_REG(   rd,rn,rm)        EOP_C_AM3_REG(A_COND_AL,1,0,rn,rd,0,1,rm)
 193
 194 /* ldm and stm */
 195 #define EOP_XXM(cond,p,u,s,w,l,rn,list) \
 196         EMIT(((cond)<<28) | (1<<27) | ((p)<<24) | ((u)<<23) | ((s)<<22) | ((w)<<21) | ((l)<<20) | ((rn)<<16) | (list))
 197
 198 #define EOP_STMIA(rb,list) EOP_XXM(A_COND_AL,0,1,0,0,0,rb,list)
 199 #define EOP_LDMIA(rb,list) EOP_XXM(A_COND_AL,0,1,0,0,1,rb,list)
 200
 201 #define EOP_STMFD_SP(list) EOP_XXM(A_COND_AL,1,0,0,1,0,13,list)
 202 #define EOP_LDMFD_SP(list) EOP_XXM(A_COND_AL,0,1,0,1,1,13,list)
 203
 204 /* branches */
 205 #define EOP_C_BX(cond,rm) \
 206         EMIT(((cond)<<28) | 0x012fff10 | (rm))
 207
 208 #define EOP_C_B_PTR(ptr,cond,l,signed_immed_24) \
 209         EMIT_PTR(ptr, ((cond)<<28) | 0x0a000000 | ((l)<<24) | (signed_immed_24))
 210
 211 #define EOP_C_B(cond,l,signed_immed_24) \
 212         EOP_C_B_PTR(tcache_ptr,cond,l,signed_immed_24)
 213
 214 #define EOP_B( signed_immed_24) EOP_C_B(A_COND_AL,0,signed_immed_24)
 215 #define EOP_BL(signed_immed_24) EOP_C_B(A_COND_AL,1,signed_immed_24)
 216
 217 /* misc */
 218 #define EOP_C_MUL(cond,s,rd,rs,rm) \
 219         EMIT(((cond)<<28) | ((s)<<20) | ((rd)<<16) | ((rs)<<8) | 0x90 | (rm))
 220
 221 #define EOP_C_UMULL(cond,s,rdhi,rdlo,rs,rm) \
 222         EMIT(((cond)<<28) | 0x00800000 | ((s)<<20) | ((rdhi)<<16) | ((rdlo)<<12) | ((rs)<<8) | 0x90 | (rm))
 223
 224 #define EOP_C_SMULL(cond,s,rdhi,rdlo,rs,rm) \
 225         EMIT(((cond)<<28) | 0x00c00000 | ((s)<<20) | ((rdhi)<<16) | ((rdlo)<<12) | ((rs)<<8) | 0x90 | (rm))
 226
 227 #define EOP_C_SMLAL(cond,s,rdhi,rdlo,rs,rm) \
 228         EMIT(((cond)<<28) | 0x00e00000 | ((s)<<20) | ((rdhi)<<16) | ((rdlo)<<12) | ((rs)<<8) | 0x90 | (rm))
 229
 230 #define EOP_MUL(rd,rm,rs) EOP_C_MUL(A_COND_AL,0,rd,rs,rm) // note: rd != rm
 231
 232 #define EOP_C_MRS(cond,rd) \
 233         EMIT(((cond)<<28) | 0x010f0000 | ((rd)<<12))
 234
 235 #define EOP_C_MSR_IMM(cond,ror2,imm) \
 236         EMIT(((cond)<<28) | 0x0328f000 | ((ror2)<<8) | (imm)) // cpsr_f
 237
 238 #define EOP_C_MSR_REG(cond,rm) \
 239         EMIT(((cond)<<28) | 0x0128f000 | (rm)) // cpsr_f
 240
 241 #define EOP_MRS(rd)           EOP_C_MRS(A_COND_AL,rd)
 242 #define EOP_MSR_IMM(ror2,imm) EOP_C_MSR_IMM(A_COND_AL,ror2,imm)
 243 #define EOP_MSR_REG(rm)       EOP_C_MSR_REG(A_COND_AL,rm)
 244
 245
 246 // XXX: AND, RSB, *C, will break if 1 insn is not enough
 247 static void emith_op_imm2(int cond, int s, int op, int rd, int rn, unsigned int imm)
 248 {
 249         int ror2;
 250         u32 v;
 251
 252         switch (op) {
 253         case A_OP_MOV:
 254                 rn = 0;
 255                 if (~imm < 0x10000) {
 256                         imm = ~imm;
 257                         op = A_OP_MVN;
 258                 }
 259                 break;
 260
 261         case A_OP_EOR:
 262         case A_OP_SUB:
 263         case A_OP_ADD:
 264         case A_OP_ORR:
 265         case A_OP_BIC:
 266                 if (s == 0 && imm == 0)
 267                         return;
 268                 break;
 269         }
 270
 271         for (v = imm, ror2 = 0; ; ror2 -= 8/2) {
 272                 /* shift down to get 'best' rot2 */
 273                 for (; v && !(v & 3); v >>= 2)
 274                         ror2--;
 275
 276                 EOP_C_DOP_IMM(cond, op, s, rn, rd, ror2 & 0x0f, v & 0xff);
 277
 278                 v >>= 8;
 279                 if (v == 0)
 280                         break;
 281                 if (op == A_OP_MOV)
 282                         op = A_OP_ORR;
 283                 if (op == A_OP_MVN)
 284                         op = A_OP_BIC;
 285                 rn = rd;
 286         }
 287 }
 288
 289 #define emith_op_imm(cond, s, op, r, imm) \
 290         emith_op_imm2(cond, s, op, r, r, imm)
 291
 292 // test op
 293 #define emith_top_imm(cond, op, r, imm) do { \
 294         u32 ror2, v; \
 295         for (ror2 = 0, v = imm; v && !(v & 3); v >>= 2) \
 296                 ror2--; \
 297         EOP_C_DOP_IMM(cond, op, 1, r, 0, ror2 & 0x0f, v & 0xff); \
 298 } while (0)
 299
 300 #define is_offset_24(val) \
 301         ((val) >= (int)0xff000000 && (val) <= 0x00ffffff)
 302
 303 static int emith_xbranch(int cond, void *target, int is_call)
 304 {
 305         int val = (u32 *)target - (u32 *)tcache_ptr - 2;
 306         int direct = is_offset_24(val);
 307         u32 *start_ptr = (u32 *)tcache_ptr;
 308
 309         if (direct)
 310         {
 311                 EOP_C_B(cond,is_call,val & 0xffffff);           // b, bl target
 312         }
 313         else
 314         {
 315 #ifdef __EPOC32__
 316 //              elprintf(EL_SVP, "emitting indirect jmp %08x->%08x", tcache_ptr, target);
 317                 if (is_call)
 318                         EOP_ADD_IMM(14,15,0,8);                 // add lr,pc,#8
 319                 EOP_C_AM2_IMM(cond,1,0,1,15,15,0);              // ldrcc pc,[pc]
 320                 EOP_MOV_REG_SIMPLE(15,15);                      // mov pc, pc
 321                 EMIT((u32)target);
 322 #else
 323                 // should never happen
 324                 elprintf(EL_STATUS|EL_SVP|EL_ANOMALY, "indirect jmp %08x->%08x", target, tcache_ptr);
 325                 exit(1);
 326 #endif
 327         }
 328
 329         return (u32 *)tcache_ptr - start_ptr;
 330 }
 331
 332 #define JMP_POS(ptr) \
 333         ptr = tcache_ptr; \
 334         tcache_ptr += sizeof(u32)
 335
 336 #define JMP_EMIT(cond, ptr) { \
 337         u32 val_ = (u32 *)tcache_ptr - (u32 *)(ptr) - 2; \
 338         EOP_C_B_PTR(ptr, cond, 0, val_ & 0xffffff); \
 339 }
 340
 341 #define EMITH_JMP_START(cond) { \
 342         void *cond_ptr; \
 343         JMP_POS(cond_ptr)
 344
 345 #define EMITH_JMP_END(cond) \
 346         JMP_EMIT(cond, cond_ptr); \
 347 }
 348
 349 // fake "simple" or "short" jump - using cond insns instead
 350 #define EMITH_NOTHING1(cond) \
 351         (void)(cond)
 352
 353 #define EMITH_SJMP_START(cond)  EMITH_NOTHING1(cond)
 354 #define EMITH_SJMP_END(cond)    EMITH_NOTHING1(cond)
 355 #define EMITH_SJMP3_START(cond) EMITH_NOTHING1(cond)
 356 #define EMITH_SJMP3_MID(cond)   EMITH_NOTHING1(cond)
 357 #define EMITH_SJMP3_END()
 358
 359 #define emith_move_r_r(d, s) \
 360         EOP_MOV_REG_SIMPLE(d, s)
 361
 362 #define emith_mvn_r_r(d, s) \
 363         EOP_MVN_REG(A_COND_AL,0,d,s,A_AM1_LSL,0)
 364
 365 #define emith_or_r_r_r_lsl(d, s1, s2, lslimm) \
 366         EOP_ORR_REG(A_COND_AL,0,d,s1,s2,A_AM1_LSL,lslimm)
 367
 368 #define emith_eor_r_r_r_lsl(d, s1, s2, lslimm) \
 369         EOP_EOR_REG(A_COND_AL,0,d,s1,s2,A_AM1_LSL,lslimm)
 370
 371 #define emith_eor_r_r_r_lsr(d, s1, s2, lsrimm) \
 372         EOP_EOR_REG(A_COND_AL,0,d,s1,s2,A_AM1_LSR,lsrimm)
 373
 374 #define emith_or_r_r_lsl(d, s, lslimm) \
 375         emith_or_r_r_r_lsl(d, d, s, lslimm)
 376
 377 #define emith_eor_r_r_lsr(d, s, lsrimm) \
 378         emith_eor_r_r_r_lsr(d, d, s, lsrimm)
 379
 380 #define emith_or_r_r_r(d, s1, s2) \
 381         emith_or_r_r_r_lsl(d, s1, s2, 0)
 382
 383 #define emith_eor_r_r_r(d, s1, s2) \
 384         emith_eor_r_r_r_lsl(d, s1, s2, 0)
 385
 386 #define emith_add_r_r(d, s) \
 387         EOP_ADD_REG(A_COND_AL,0,d,d,s,A_AM1_LSL,0)
 388
 389 #define emith_sub_r_r(d, s) \
 390         EOP_SUB_REG(A_COND_AL,0,d,d,s,A_AM1_LSL,0)
 391
 392 #define emith_adc_r_r(d, s) \
 393         EOP_ADC_REG(A_COND_AL,0,d,d,s,A_AM1_LSL,0)
 394
 395 #define emith_and_r_r(d, s) \
 396         EOP_AND_REG(A_COND_AL,0,d,d,s,A_AM1_LSL,0)
 397
 398 #define emith_or_r_r(d, s) \
 399         emith_or_r_r_r(d, d, s)
 400
 401 #define emith_eor_r_r(d, s) \
 402         emith_eor_r_r_r(d, d, s)
 403
 404 #define emith_tst_r_r(d, s) \
 405         EOP_TST_REG(A_COND_AL,d,s,A_AM1_LSL,0)
 406
 407 #define emith_teq_r_r(d, s) \
 408         EOP_TEQ_REG(A_COND_AL,d,s,A_AM1_LSL,0)
 409
 410 #define emith_cmp_r_r(d, s) \
 411         EOP_CMP_REG(A_COND_AL,d,s,A_AM1_LSL,0)
 412
 413 #define emith_addf_r_r(d, s) \
 414         EOP_ADD_REG(A_COND_AL,1,d,d,s,A_AM1_LSL,0)
 415
 416 #define emith_subf_r_r(d, s) \
 417         EOP_SUB_REG(A_COND_AL,1,d,d,s,A_AM1_LSL,0)
 418
 419 #define emith_adcf_r_r(d, s) \
 420         EOP_ADC_REG(A_COND_AL,1,d,d,s,A_AM1_LSL,0)
 421
 422 #define emith_sbcf_r_r(d, s) \
 423         EOP_SBC_REG(A_COND_AL,1,d,d,s,A_AM1_LSL,0)
 424
 425 #define emith_eorf_r_r(d, s) \
 426         EOP_EOR_REG(A_COND_AL,1,d,d,s,A_AM1_LSL,0)
 427
 428 #define emith_move_r_imm(r, imm) \
 429         emith_op_imm(A_COND_AL, 0, A_OP_MOV, r, imm)
 430
 431 #define emith_add_r_imm(r, imm) \
 432         emith_op_imm(A_COND_AL, 0, A_OP_ADD, r, imm)
 433
 434 #define emith_adc_r_imm(r, imm) \
 435         emith_op_imm(A_COND_AL, 0, A_OP_ADC, r, imm)
 436
 437 #define emith_sub_r_imm(r, imm) \
 438         emith_op_imm(A_COND_AL, 0, A_OP_SUB, r, imm)
 439
 440 #define emith_bic_r_imm(r, imm) \
 441         emith_op_imm(A_COND_AL, 0, A_OP_BIC, r, imm)
 442
 443 #define emith_and_r_imm(r, imm) \
 444         emith_op_imm(A_COND_AL, 0, A_OP_AND, r, imm)
 445
 446 #define emith_or_r_imm(r, imm) \
 447         emith_op_imm(A_COND_AL, 0, A_OP_ORR, r, imm)
 448
 449 #define emith_eor_r_imm(r, imm) \
 450         emith_op_imm(A_COND_AL, 0, A_OP_EOR, r, imm)
 451
 452 // note: only use 8bit imm for these
 453 #define emith_tst_r_imm(r, imm) \
 454         emith_top_imm(A_COND_AL, A_OP_TST, r, imm)
 455
 456 #define emith_cmp_r_imm(r, imm) { \
 457         u32 op = A_OP_CMP, imm_ = imm; \
 458         if (~imm_ < 0x100) { \
 459                 imm_ = ~imm_; \
 460                 op = A_OP_CMN; \
 461         } \
 462         emith_top_imm(A_COND_AL, op, r, imm); \
 463 }
 464
 465 #define emith_subf_r_imm(r, imm) \
 466         emith_op_imm(A_COND_AL, 1, A_OP_SUB, r, imm)
 467
 468 #define emith_move_r_imm_c(cond, r, imm) \
 469         emith_op_imm(cond, 0, A_OP_MOV, r, imm)
 470
 471 #define emith_add_r_imm_c(cond, r, imm) \
 472         emith_op_imm(cond, 0, A_OP_ADD, r, imm)
 473
 474 #define emith_sub_r_imm_c(cond, r, imm) \
 475         emith_op_imm(cond, 0, A_OP_SUB, r, imm)
 476
 477 #define emith_or_r_imm_c(cond, r, imm) \
 478         emith_op_imm(cond, 0, A_OP_ORR, r, imm)
 479
 480 #define emith_eor_r_imm_c(cond, r, imm) \
 481         emith_op_imm(cond, 0, A_OP_EOR, r, imm)
 482
 483 #define emith_bic_r_imm_c(cond, r, imm) \
 484         emith_op_imm(cond, 0, A_OP_BIC, r, imm)
 485
 486 #define emith_move_r_imm_s8(r, imm) { \
 487         if ((imm) & 0x80) \
 488                 EOP_MVN_IMM(r, 0, ((imm) ^ 0xff)); \
 489         else \
 490                 EOP_MOV_IMM(r, 0, imm); \
 491 }
 492
 493 #define emith_and_r_r_imm(d, s, imm) \
 494         emith_op_imm2(A_COND_AL, 0, A_OP_AND, d, s, imm)
 495
 496 #define emith_add_r_r_imm(d, s, imm) \
 497         emith_op_imm2(A_COND_AL, 0, A_OP_ADD, d, s, imm)
 498
 499 #define emith_sub_r_r_imm(d, s, imm) \
 500         emith_op_imm2(A_COND_AL, 0, A_OP_SUB, d, s, imm)
 501
 502 #define emith_neg_r_r(d, s) \
 503         EOP_RSB_IMM(d, s, 0, 0)
 504
 505 #define emith_lsl(d, s, cnt) \
 506         EOP_MOV_REG(A_COND_AL,0,d,s,A_AM1_LSL,cnt)
 507
 508 #define emith_lsr(d, s, cnt) \
 509         EOP_MOV_REG(A_COND_AL,0,d,s,A_AM1_LSR,cnt)
 510
 511 #define emith_asr(d, s, cnt) \
 512         EOP_MOV_REG(A_COND_AL,0,d,s,A_AM1_ASR,cnt)
 513
 514 #define emith_ror_c(cond, d, s, cnt) \
 515         EOP_MOV_REG(cond,0,d,s,A_AM1_ROR,cnt)
 516
 517 #define emith_ror(d, s, cnt) \
 518         emith_ror_c(A_COND_AL, d, s, cnt)
 519
 520 #define emith_rol(d, s, cnt) \
 521         EOP_MOV_REG(A_COND_AL,0,d,s,A_AM1_ROR,32-(cnt)); \
 522
 523 #define emith_lslf(d, s, cnt) \
 524         EOP_MOV_REG(A_COND_AL,1,d,s,A_AM1_LSL,cnt)
 525
 526 #define emith_lsrf(d, s, cnt) \
 527         EOP_MOV_REG(A_COND_AL,1,d,s,A_AM1_LSR,cnt)
 528
 529 #define emith_asrf(d, s, cnt) \
 530         EOP_MOV_REG(A_COND_AL,1,d,s,A_AM1_ASR,cnt)
 531
 532 // note: only C flag updated correctly
 533 #define emith_rolf(d, s, cnt) { \
 534         EOP_MOV_REG(A_COND_AL,1,d,s,A_AM1_ROR,32-(cnt)); \
 535         /* we don't have ROL so we shift to get the right carry */ \
 536         EOP_TST_REG(A_COND_AL,d,d,A_AM1_LSR,1); \
 537 }
 538
 539 #define emith_rorf(d, s, cnt) \
 540         EOP_MOV_REG(A_COND_AL,1,d,s,A_AM1_ROR,cnt)
 541
 542 #define emith_rolcf(d) \
 543         emith_adcf_r_r(d, d)
 544
 545 #define emith_rorcf(d) \
 546         EOP_MOV_REG(A_COND_AL,1,d,d,A_AM1_ROR,0) /* ROR #0 -> RRX */
 547
 548 #define emith_negcf_r_r(d, s) \
 549         EOP_C_DOP_IMM(A_COND_AL,A_OP_RSC,1,s,d,0,0)
 550
 551 #define emith_mul(d, s1, s2) { \
 552         if ((d) != (s1)) /* rd != rm limitation */ \
 553                 EOP_MUL(d, s1, s2); \
 554         else \
 555                 EOP_MUL(d, s2, s1); \
 556 }
 557
 558 #define emith_mul_u64(dlo, dhi, s1, s2) \
 559         EOP_C_UMULL(A_COND_AL,0,dhi,dlo,s1,s2)
 560
 561 #define emith_mul_s64(dlo, dhi, s1, s2) \
 562         EOP_C_SMULL(A_COND_AL,0,dhi,dlo,s1,s2)
 563
 564 #define emith_mula_s64(dlo, dhi, s1, s2) \
 565         EOP_C_SMLAL(A_COND_AL,0,dhi,dlo,s1,s2)
 566
 567 // misc
 568 #define emith_read_r_r_offs_c(cond, r, rs, offs) \
 569         EOP_LDR_IMM2(cond, r, rs, offs)
 570
 571 #define emith_read8_r_r_offs_c(cond, r, rs, offs) \
 572         EOP_LDRB_IMM2(cond, r, rs, offs)
 573
 574 #define emith_read16_r_r_offs_c(cond, r, rs, offs) \
 575         EOP_LDRH_IMM2(cond, r, rs, offs)
 576
 577 #define emith_read_r_r_offs(r, rs, offs) \
 578         emith_read_r_r_offs_c(A_COND_AL, r, rs, offs)
 579
 580 #define emith_read8_r_r_offs(r, rs, offs) \
 581         emith_read8_r_r_offs_c(A_COND_AL, r, rs, offs)
 582
 583 #define emith_read16_r_r_offs(r, rs, offs) \
 584         emith_read16_r_r_offs_c(A_COND_AL, r, rs, offs)
 585
 586 #define emith_ctx_read(r, offs) \
 587         emith_read_r_r_offs(r, CONTEXT_REG, offs)
 588
 589 #define emith_ctx_write(r, offs) \
 590         EOP_STR_IMM(r, CONTEXT_REG, offs)
 591
 592 #define emith_ctx_do_multiple(op, r, offs, count, tmpr) do { \
 593         int v_, r_ = r, c_ = count, b_ = CONTEXT_REG;        \
 594         for (v_ = 0; c_; c_--, r_++)                         \
 595                 v_ |= 1 << r_;                               \
 596         if ((offs) != 0) {                                   \
 597                 EOP_ADD_IMM(tmpr,CONTEXT_REG,30/2,(offs)>>2);\
 598                 b_ = tmpr;                                   \
 599         }                                                    \
 600         op(b_,v_);                                           \
 601 } while(0)
 602
 603 #define emith_ctx_read_multiple(r, offs, count, tmpr) \
 604         emith_ctx_do_multiple(EOP_LDMIA, r, offs, count, tmpr)
 605
 606 #define emith_ctx_write_multiple(r, offs, count, tmpr) \
 607         emith_ctx_do_multiple(EOP_STMIA, r, offs, count, tmpr)
 608
 609 #define emith_clear_msb_c(cond, d, s, count) { \
 610         u32 t; \
 611         if ((count) <= 8) { \
 612                 t = (count) - 8; \
 613                 t = (0xff << t) & 0xff; \
 614                 EOP_BIC_IMM(d,s,8/2,t); \
 615                 EOP_C_DOP_IMM(cond,A_OP_BIC,0,s,d,8/2,t); \
 616         } else if ((count) >= 24) { \
 617                 t = (count) - 24; \
 618                 t = 0xff >> t; \
 619                 EOP_AND_IMM(d,s,0,t); \
 620                 EOP_C_DOP_IMM(cond,A_OP_AND,0,s,d,0,t); \
 621         } else { \
 622                 EOP_MOV_REG(cond,0,d,s,A_AM1_LSL,count); \
 623                 EOP_MOV_REG(cond,0,d,d,A_AM1_LSR,count); \
 624         } \
 625 }
 626
 627 #define emith_clear_msb(d, s, count) \
 628         emith_clear_msb_c(A_COND_AL, d, s, count)
 629
 630 #define emith_sext(d, s, bits) { \
 631         EOP_MOV_REG_LSL(d,s,32 - (bits)); \
 632         EOP_MOV_REG_ASR(d,d,32 - (bits)); \
 633 }
 634
 635 // upto 4 args
 636 #define emith_pass_arg_r(arg, reg) \
 637         EOP_MOV_REG_SIMPLE(arg, reg)
 638
 639 #define emith_pass_arg_imm(arg, imm) \
 640         emith_move_r_imm(arg, imm)
 641
 642 #define emith_jump(target) \
 643         emith_jump_cond(A_COND_AL, target)
 644
 645 #define emith_jump_patchable(target) \
 646         emith_jump(target)
 647
 648 #define emith_jump_cond(cond, target) \
 649         emith_xbranch(cond, target, 0)
 650
 651 #define emith_jump_cond_patchable(cond, target) \
 652         emith_jump_cond(cond, target)
 653
 654 #define emith_jump_patch(ptr, target) do { \
 655         u32 *ptr_ = ptr; \
 656         u32 val_ = (u32 *)(target) - ptr_ - 2; \
 657         *ptr_ = (*ptr_ & 0xff000000) | (val_ & 0x00ffffff); \
 658 } while (0)
 659
 660 #define emith_jump_at(ptr, target) { \
 661         u32 val_ = (u32 *)(target) - (u32 *)(ptr) - 2; \
 662         EOP_C_B_PTR(ptr, A_COND_AL, 0, val_ & 0xffffff); \
 663 }
 664
 665 #define emith_jump_reg_c(cond, r) \
 666         EOP_C_BX(cond, r)
 667
 668 #define emith_jump_reg(r) \
 669         emith_jump_reg_c(A_COND_AL, r)
 670
 671 #define emith_jump_ctx_c(cond, offs) \
 672         EOP_LDR_IMM2(cond,15,CONTEXT_REG,offs)
 673
 674 #define emith_jump_ctx(offs) \
 675         emith_jump_ctx_c(A_COND_AL, offs)
 676
 677 #define emith_call_cond(cond, target) \
 678         emith_xbranch(cond, target, 1)
 679
 680 #define emith_call(target) \
 681         emith_call_cond(A_COND_AL, target)
 682
 683 #define emith_call_ctx(offs) { \
 684         emith_move_r_r(14, 15); \
 685         emith_jump_ctx(offs); \
 686 }
 687
 688 #define emith_ret_c(cond) \
 689         emith_jump_reg_c(cond, 14)
 690
 691 #define emith_ret() \
 692         emith_ret_c(A_COND_AL)
 693
 694 #define emith_ret_to_ctx(offs) \
 695         emith_ctx_write(14, offs)
 696
 697 #define emith_push_ret() \
 698         EOP_STMFD_SP(A_R14M)
 699
 700 #define emith_pop_and_ret() \
 701         EOP_LDMFD_SP(A_R15M)
 702
 703 #define host_instructions_updated(base, end) \
 704         cache_flush_d_inval_i(base, end)
 705
 706 #define host_arg2reg(rd, arg) \
 707         rd = arg
 708
 709 /* SH2 drc specific */
 710 #define emith_sh2_drc_entry() \
 711         EOP_STMFD_SP(A_R4M|A_R5M|A_R6M|A_R7M|A_R8M|A_R9M|A_R10M|A_R11M|A_R14M)
 712
 713 #define emith_sh2_drc_exit() \
 714         EOP_LDMFD_SP(A_R4M|A_R5M|A_R6M|A_R7M|A_R8M|A_R9M|A_R10M|A_R11M|A_R15M)
 715
 716 #define emith_sh2_wcall(a, tab, ret_ptr) { \
 717         int val_ = (char *)(ret_ptr) - (char *)tcache_ptr - 2*4; \
 718         if (val_ >= 0) \
 719                 emith_add_r_r_imm(14, 15, val_); \
 720         else if (val_ < 0) \
 721                 emith_sub_r_r_imm(14, 15, -val_); \
 722         emith_lsr(12, a, SH2_WRITE_SHIFT); \
 723         EOP_LDR_REG_LSL(A_COND_AL,12,tab,12,2); \
 724         emith_ctx_read(2, offsetof(SH2, is_slave)); \
 725         emith_jump_reg(12); \
 726 }
 727
 728 #define emith_sh2_dtbf_loop() { \
 729         int cr, rn;                                                          \
 730         int tmp_ = rcache_get_tmp();                                         \
 731         cr = rcache_get_reg(SHR_SR, RC_GR_RMW);                              \
 732         rn = rcache_get_reg((op >> 8) & 0x0f, RC_GR_RMW);                    \
 733         emith_sub_r_imm(rn, 1);                /* sub rn, #1 */              \
 734         emith_bic_r_imm(cr, 1);                /* bic cr, #1 */              \
 735         emith_sub_r_imm(cr, (cycles+1) << 12); /* sub cr, #(cycles+1)<<12 */ \
 736         cycles = 0;                                                          \
 737         emith_asrf(tmp_, cr, 2+12);            /* movs tmp_, cr, asr #2+12 */\
 738         EOP_MOV_IMM_C(A_COND_MI,tmp_,0,0);     /* movmi tmp_, #0 */          \
 739         emith_lsl(cr, cr, 20);                 /* mov cr, cr, lsl #20 */     \
 740         emith_lsr(cr, cr, 20);                 /* mov cr, cr, lsr #20 */     \
 741         emith_subf_r_r(rn, tmp_);              /* subs rn, tmp_ */           \
 742         EOP_RSB_IMM_C(A_COND_LS,tmp_,rn,0,0);  /* rsbls tmp_, rn, #0 */      \
 743         EOP_ORR_REG(A_COND_LS,0,cr,cr,tmp_,A_AM1_LSL,12+2); /* orrls cr,tmp_,lsl #12+2 */\
 744         EOP_ORR_IMM_C(A_COND_LS,cr,cr,0,1);    /* orrls cr, #1 */            \
 745         EOP_MOV_IMM_C(A_COND_LS,rn,0,0);       /* movls rn, #0 */            \
 746         rcache_free_tmp(tmp_);                                               \
 747 }
 748
 749 #define emith_write_sr(sr, srcr) { \
 750         emith_lsr(sr, sr, 10); \
 751         emith_or_r_r_r_lsl(sr, sr, srcr, 22); \
 752         emith_ror(sr, sr, 22); \
 753 }
 754
 755 #define emith_carry_to_t(srr, is_sub) { \
 756         if (is_sub) { /* has inverted C on ARM */ \
 757                 emith_or_r_imm_c(A_COND_CC, srr, 1); \
 758                 emith_bic_r_imm_c(A_COND_CS, srr, 1); \
 759         } else { \
 760                 emith_or_r_imm_c(A_COND_CS, srr, 1); \
 761                 emith_bic_r_imm_c(A_COND_CC, srr, 1); \
 762         } \
 763 }
 764
 765 #define emith_tpop_carry(sr, is_sub) {  \
 766         if (is_sub)                     \
 767                 emith_eor_r_imm(sr, 1); \
 768         emith_lsrf(sr, sr, 1);          \
 769 }
 770
 771 #define emith_tpush_carry(sr, is_sub) { \
 772         emith_adc_r_r(sr, sr);          \
 773         if (is_sub)                     \
 774                 emith_eor_r_imm(sr, 1); \
 775 }
 776
 777 /*
 778  * if Q
 779  *   t = carry(Rn += Rm)
 780  * else
 781  *   t = carry(Rn -= Rm)
 782  * T ^= t
 783  */
 784 #define emith_sh2_div1_step(rn, rm, sr) {         \
 785         void *jmp0, *jmp1;                        \
 786         emith_tst_r_imm(sr, Q);  /* if (Q ^ M) */ \
 787         JMP_POS(jmp0);           /* beq do_sub */ \
 788         emith_addf_r_r(rn, rm);                   \
 789         emith_eor_r_imm_c(A_COND_CS, sr, T);      \
 790         JMP_POS(jmp1);           /* b done */     \
 791         JMP_EMIT(A_COND_EQ, jmp0); /* do_sub: */  \
 792         emith_subf_r_r(rn, rm);                   \
 793         emith_eor_r_imm_c(A_COND_CC, sr, T);      \
 794         JMP_EMIT(A_COND_AL, jmp1); /* done: */    \
 795 }
 796