6 /* ======================================================================== */
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7 /* ========================= LICENSING & COPYRIGHT ======================== */
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8 /* ======================================================================== */
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13 * A portable Motorola M680x0 processor emulation engine.
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14 * Copyright 1998-2007 Karl Stenerud. All rights reserved.
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16 * This code may be freely used for non-commercial purposes as long as this
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17 * copyright notice remains unaltered in the source code and any binary files
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18 * containing this code in compiled form.
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20 * All other lisencing terms must be negotiated with the author
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23 * The latest version of this code can be obtained at:
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24 * http://kstenerud.cjb.net
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27 /* Special thanks to Bart Trzynadlowski for his insight into the
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28 * undocumented features of this chip:
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30 * http://dynarec.com/~bart/files/68knotes.txt
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34 /* Input file for m68kmake
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35 * -----------------------
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37 * All sections begin with 80 X's in a row followed by an end-of-line
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39 * After this, m68kmake will expect to find one of the following section
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41 * M68KMAKE_PROTOTYPE_HEADER - header for opcode handler prototypes
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42 * M68KMAKE_PROTOTYPE_FOOTER - footer for opcode handler prototypes
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43 * M68KMAKE_TABLE_HEADER - header for opcode handler jumptable
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44 * M68KMAKE_TABLE_FOOTER - footer for opcode handler jumptable
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45 * M68KMAKE_TABLE_BODY - the table itself
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46 * M68KMAKE_OPCODE_HANDLER_HEADER - header for opcode handler implementation
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47 * M68KMAKE_OPCODE_HANDLER_FOOTER - footer for opcode handler implementation
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48 * M68KMAKE_OPCODE_HANDLER_BODY - body section for opcode handler implementation
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50 * NOTE: M68KMAKE_OPCODE_HANDLER_BODY must be last in the file and
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51 * M68KMAKE_TABLE_BODY must be second last in the file.
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53 * The M68KMAKE_OPHANDLER_BODY section contains the opcode handler
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54 * primitives themselves. Each opcode handler begins with:
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55 * M68KMAKE_OP(A, B, C, D)
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57 * where A is the opcode handler name, B is the size of the operation,
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58 * C denotes any special processing mode, and D denotes a specific
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60 * For C and D where nothing is specified, use "."
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63 * M68KMAKE_OP(abcd, 8, rr, .) abcd, size 8, register to register, default EA
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64 * M68KMAKE_OP(abcd, 8, mm, ax7) abcd, size 8, memory to memory, register X is A7
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65 * M68KMAKE_OP(tst, 16, ., pcix) tst, size 16, PCIX addressing
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67 * All opcode handler primitives end with a closing curly brace "}" at column 1
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69 * NOTE: Do not place a M68KMAKE_OP() directive inside the opcode handler,
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70 * and do not put a closing curly brace at column 1 unless it is
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71 * marking the end of the handler!
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73 * Inside the handler, m68kmake will recognize M68KMAKE_GET_OPER_xx_xx,
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74 * M68KMAKE_GET_EA_xx_xx, and M68KMAKE_CC directives, and create multiple
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75 * opcode handlers to handle variations in the opcode handler.
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76 * Note: M68KMAKE_CC will only be interpreted in condition code opcodes.
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77 * As well, M68KMAKE_GET_EA_xx_xx and M68KMAKE_GET_OPER_xx_xx will only
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78 * be interpreted on instructions where the corresponding table entry
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79 * specifies multiple effective addressing modes.
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81 * clr 32 . . 0100001010...... A+-DXWL... U U U 12 6 4
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83 * This table entry says that the clr.l opcde has 7 variations (A+-DXWL).
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84 * It is run in user or supervisor mode for all CPUs, and uses 12 cycles for
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85 * 68000, 6 cycles for 68010, and 4 cycles for 68020.
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88 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
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89 M68KMAKE_PROTOTYPE_HEADER
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91 #ifndef M68KOPS__HEADER
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92 #define M68KOPS__HEADER
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94 /* ======================================================================== */
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95 /* ============================ OPCODE HANDLERS =========================== */
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96 /* ======================================================================== */
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100 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
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101 M68KMAKE_PROTOTYPE_FOOTER
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104 /* Build the opcode handler table */
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105 void m68ki_build_opcode_table(void);
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107 extern void (*m68ki_instruction_jump_table[0x10000])(void); /* opcode handler jump table */
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108 extern unsigned char m68ki_cycles[][0x10000];
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111 /* ======================================================================== */
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112 /* ============================== END OF FILE ============================= */
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113 /* ======================================================================== */
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115 #endif /* M68KOPS__HEADER */
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119 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
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120 M68KMAKE_TABLE_HEADER
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122 /* ======================================================================== */
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123 /* ========================= OPCODE TABLE BUILDER ========================= */
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124 /* ======================================================================== */
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126 #include "m68kops.h"
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128 #define NUM_CPU_TYPES 4
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130 void (*m68ki_instruction_jump_table[0x10000])(void); /* opcode handler jump table */
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131 unsigned char m68ki_cycles[NUM_CPU_TYPES][0x10000]; /* Cycles used by CPU type */
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133 /* This is used to generate the opcode handler jump table */
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136 void (*opcode_handler)(void); /* handler function */
\r
137 unsigned int mask; /* mask on opcode */
\r
138 unsigned int match; /* what to match after masking */
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139 unsigned char cycles[NUM_CPU_TYPES]; /* cycles each cpu type takes */
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140 } opcode_handler_struct;
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143 /* Opcode handler table */
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144 static opcode_handler_struct m68k_opcode_handler_table[] =
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146 /* function mask match 000 010 020 040 */
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150 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
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151 M68KMAKE_TABLE_FOOTER
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153 {0, 0, 0, {0, 0, 0, 0}}
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157 /* Build the opcode handler jump table */
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158 void m68ki_build_opcode_table(void)
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160 opcode_handler_struct *ostruct;
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166 for(i = 0; i < 0x10000; i++)
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168 /* default to illegal */
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169 m68ki_instruction_jump_table[i] = m68k_op_illegal;
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170 for(k=0;k<NUM_CPU_TYPES;k++)
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171 m68ki_cycles[k][i] = 0;
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174 ostruct = m68k_opcode_handler_table;
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175 while(ostruct->mask != 0xff00)
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177 for(i = 0;i < 0x10000;i++)
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179 if((i & ostruct->mask) == ostruct->match)
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181 m68ki_instruction_jump_table[i] = ostruct->opcode_handler;
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182 for(k=0;k<NUM_CPU_TYPES;k++)
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183 m68ki_cycles[k][i] = ostruct->cycles[k];
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188 while(ostruct->mask == 0xff00)
\r
190 for(i = 0;i <= 0xff;i++)
\r
192 m68ki_instruction_jump_table[ostruct->match | i] = ostruct->opcode_handler;
\r
193 for(k=0;k<NUM_CPU_TYPES;k++)
\r
194 m68ki_cycles[k][ostruct->match | i] = ostruct->cycles[k];
\r
198 while(ostruct->mask == 0xf1f8)
\r
200 for(i = 0;i < 8;i++)
\r
202 for(j = 0;j < 8;j++)
\r
204 instr = ostruct->match | (i << 9) | j;
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205 m68ki_instruction_jump_table[instr] = ostruct->opcode_handler;
\r
206 for(k=0;k<NUM_CPU_TYPES;k++)
\r
207 m68ki_cycles[k][instr] = ostruct->cycles[k];
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212 while(ostruct->mask == 0xfff0)
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214 for(i = 0;i <= 0x0f;i++)
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216 m68ki_instruction_jump_table[ostruct->match | i] = ostruct->opcode_handler;
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217 for(k=0;k<NUM_CPU_TYPES;k++)
\r
218 m68ki_cycles[k][ostruct->match | i] = ostruct->cycles[k];
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222 while(ostruct->mask == 0xf1ff)
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224 for(i = 0;i <= 0x07;i++)
\r
226 m68ki_instruction_jump_table[ostruct->match | (i << 9)] = ostruct->opcode_handler;
\r
227 for(k=0;k<NUM_CPU_TYPES;k++)
\r
228 m68ki_cycles[k][ostruct->match | (i << 9)] = ostruct->cycles[k];
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232 while(ostruct->mask == 0xfff8)
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234 for(i = 0;i <= 0x07;i++)
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236 m68ki_instruction_jump_table[ostruct->match | i] = ostruct->opcode_handler;
\r
237 for(k=0;k<NUM_CPU_TYPES;k++)
\r
238 m68ki_cycles[k][ostruct->match | i] = ostruct->cycles[k];
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242 while(ostruct->mask == 0xffff)
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244 m68ki_instruction_jump_table[ostruct->match] = ostruct->opcode_handler;
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245 for(k=0;k<NUM_CPU_TYPES;k++)
\r
246 m68ki_cycles[k][ostruct->match] = ostruct->cycles[k];
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252 /* ======================================================================== */
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253 /* ============================== END OF FILE ============================= */
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254 /* ======================================================================== */
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258 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
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259 M68KMAKE_OPCODE_HANDLER_HEADER
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261 #include "m68kcpu.h"
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262 extern void m68040_fpu_op0(void);
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263 extern void m68040_fpu_op1(void);
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265 /* ======================================================================== */
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266 /* ========================= INSTRUCTION HANDLERS ========================= */
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267 /* ======================================================================== */
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271 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
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272 M68KMAKE_OPCODE_HANDLER_FOOTER
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274 /* ======================================================================== */
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275 /* ============================== END OF FILE ============================= */
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276 /* ======================================================================== */
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280 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
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281 M68KMAKE_TABLE_BODY
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283 The following table is arranged as follows:
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285 name: Opcode mnemonic
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287 size: Operation size
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289 spec proc: Special processing mode:
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292 r: register operand
\r
293 rr: register to register
\r
294 mm: memory to memory
\r
295 er: effective address to register
\r
296 re: register to effective address
\r
297 dd: data register to data register
\r
298 da: data register to address register
\r
299 aa: address register to address register
\r
300 cr: control register to register
\r
301 rc: register to control register
\r
302 toc: to condition code register
\r
303 tos: to status register
\r
304 tou: to user stack pointer
\r
305 frc: from condition code register
\r
306 frs: from status register
\r
307 fru: from user stack pointer
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308 * for move.x, the special processing mode is a specific
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309 destination effective addressing mode.
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311 spec ea: Specific effective addressing mode:
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315 a: address register
\r
316 ai: address register indirect
\r
317 pi: address register indirect with postincrement
\r
318 pd: address register indirect with predecrement
\r
319 di: address register indirect with displacement
\r
320 ix: address register indirect with index
\r
321 aw: absolute word address
\r
322 al: absolute long address
\r
323 pcdi: program counter relative with displacement
\r
324 pcix: program counter relative with index
\r
325 a7: register specified in instruction is A7
\r
326 ax7: register field X of instruction is A7
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327 ay7: register field Y of instruction is A7
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328 axy7: register fields X and Y of instruction are A7
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330 bit pattern: Pattern to recognize this opcode. "." means don't care.
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332 allowed ea: List of allowed addressing modes:
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334 A: address register indirect
\r
335 +: ARI (address register indirect) with postincrement
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336 -: ARI with predecrement
\r
337 D: ARI with displacement
\r
339 W: absolute word address
\r
340 L: absolute long address
\r
341 d: program counter indirect with displacement
\r
342 x: program counter indirect with index
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344 mode: CPU operating mode for each cpu type. U = user or supervisor,
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345 S = supervisor only, "." = opcode not present.
\r
347 cpu cycles: Base number of cycles required to execute this opcode on the
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348 specified CPU type.
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349 Use "." if CPU does not have this opcode.
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353 spec spec allowed ea mode cpu cycles
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354 name size proc ea bit pattern A+-DXWLdxI 0 1 2 4 000 010 020 040 comments
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355 ====== ==== ==== ==== ================ ========== = = = = === === === === =============
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356 M68KMAKE_TABLE_START
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357 1010 0 . . 1010............ .......... U U U U 4 4 4 4
\r
358 1111 0 . . 1111............ .......... U U U U 4 4 4 4
\r
359 040fpu0 32 . . 11110010........ .......... . . . U . . . 0
\r
360 040fpu1 32 . . 11110011........ .......... . . . U . . . 0
\r
361 abcd 8 rr . 1100...100000... .......... U U U U 6 6 4 4
\r
362 abcd 8 mm ax7 1100111100001... .......... U U U U 18 18 16 16
\r
363 abcd 8 mm ay7 1100...100001111 .......... U U U U 18 18 16 16
\r
364 abcd 8 mm axy7 1100111100001111 .......... U U U U 18 18 16 16
\r
365 abcd 8 mm . 1100...100001... .......... U U U U 18 18 16 16
\r
366 add 8 er d 1101...000000... .......... U U U U 4 4 2 2
\r
367 add 8 er . 1101...000...... A+-DXWLdxI U U U U 4 4 2 2
\r
368 add 16 er d 1101...001000... .......... U U U U 4 4 2 2
\r
369 add 16 er a 1101...001001... .......... U U U U 4 4 2 2
\r
370 add 16 er . 1101...001...... A+-DXWLdxI U U U U 4 4 2 2
\r
371 add 32 er d 1101...010000... .......... U U U U 6 6 2 2
\r
372 add 32 er a 1101...010001... .......... U U U U 6 6 2 2
\r
373 add 32 er . 1101...010...... A+-DXWLdxI U U U U 6 6 2 2
\r
374 add 8 re . 1101...100...... A+-DXWL... U U U U 8 8 4 4
\r
375 add 16 re . 1101...101...... A+-DXWL... U U U U 8 8 4 4
\r
376 add 32 re . 1101...110...... A+-DXWL... U U U U 12 12 4 4
\r
377 adda 16 . d 1101...011000... .......... U U U U 8 8 2 2
\r
378 adda 16 . a 1101...011001... .......... U U U U 8 8 2 2
\r
379 adda 16 . . 1101...011...... A+-DXWLdxI U U U U 8 8 2 2
\r
380 adda 32 . d 1101...111000... .......... U U U U 6 6 2 2
\r
381 adda 32 . a 1101...111001... .......... U U U U 6 6 2 2
\r
382 adda 32 . . 1101...111...... A+-DXWLdxI U U U U 6 6 2 2
\r
383 addi 8 . d 0000011000000... .......... U U U U 8 8 2 2
\r
384 addi 8 . . 0000011000...... A+-DXWL... U U U U 12 12 4 4
\r
385 addi 16 . d 0000011001000... .......... U U U U 8 8 2 2
\r
386 addi 16 . . 0000011001...... A+-DXWL... U U U U 12 12 4 4
\r
387 addi 32 . d 0000011010000... .......... U U U U 16 14 2 2
\r
388 addi 32 . . 0000011010...... A+-DXWL... U U U U 20 20 4 4
\r
389 addq 8 . d 0101...000000... .......... U U U U 4 4 2 2
\r
390 addq 8 . . 0101...000...... A+-DXWL... U U U U 8 8 4 4
\r
391 addq 16 . d 0101...001000... .......... U U U U 4 4 2 2
\r
392 addq 16 . a 0101...001001... .......... U U U U 4 4 2 2
\r
393 addq 16 . . 0101...001...... A+-DXWL... U U U U 8 8 4 4
\r
394 addq 32 . d 0101...010000... .......... U U U U 8 8 2 2
\r
395 addq 32 . a 0101...010001... .......... U U U U 8 8 2 2
\r
396 addq 32 . . 0101...010...... A+-DXWL... U U U U 12 12 4 4
\r
397 addx 8 rr . 1101...100000... .......... U U U U 4 4 2 2
\r
398 addx 16 rr . 1101...101000... .......... U U U U 4 4 2 2
\r
399 addx 32 rr . 1101...110000... .......... U U U U 8 6 2 2
\r
400 addx 8 mm ax7 1101111100001... .......... U U U U 18 18 12 12
\r
401 addx 8 mm ay7 1101...100001111 .......... U U U U 18 18 12 12
\r
402 addx 8 mm axy7 1101111100001111 .......... U U U U 18 18 12 12
\r
403 addx 8 mm . 1101...100001... .......... U U U U 18 18 12 12
\r
404 addx 16 mm . 1101...101001... .......... U U U U 18 18 12 12
\r
405 addx 32 mm . 1101...110001... .......... U U U U 30 30 12 12
\r
406 and 8 er d 1100...000000... .......... U U U U 4 4 2 2
\r
407 and 8 er . 1100...000...... A+-DXWLdxI U U U U 4 4 2 2
\r
408 and 16 er d 1100...001000... .......... U U U U 4 4 2 2
\r
409 and 16 er . 1100...001...... A+-DXWLdxI U U U U 4 4 2 2
\r
410 and 32 er d 1100...010000... .......... U U U U 6 6 2 2
\r
411 and 32 er . 1100...010...... A+-DXWLdxI U U U U 6 6 2 2
\r
412 and 8 re . 1100...100...... A+-DXWL... U U U U 8 8 4 4
\r
413 and 16 re . 1100...101...... A+-DXWL... U U U U 8 8 4 4
\r
414 and 32 re . 1100...110...... A+-DXWL... U U U U 12 12 4 4
\r
415 andi 16 toc . 0000001000111100 .......... U U U U 20 16 12 12
\r
416 andi 16 tos . 0000001001111100 .......... S S S S 20 16 12 12
\r
417 andi 8 . d 0000001000000... .......... U U U U 8 8 2 2
\r
418 andi 8 . . 0000001000...... A+-DXWL... U U U U 12 12 4 4
\r
419 andi 16 . d 0000001001000... .......... U U U U 8 8 2 2
\r
420 andi 16 . . 0000001001...... A+-DXWL... U U U U 12 12 4 4
\r
421 andi 32 . d 0000001010000... .......... U U U U 14 14 2 2
\r
422 andi 32 . . 0000001010...... A+-DXWL... U U U U 20 20 4 4
\r
423 asr 8 s . 1110...000000... .......... U U U U 6 6 6 6
\r
424 asr 16 s . 1110...001000... .......... U U U U 6 6 6 6
\r
425 asr 32 s . 1110...010000... .......... U U U U 8 8 6 6
\r
426 asr 8 r . 1110...000100... .......... U U U U 6 6 6 6
\r
427 asr 16 r . 1110...001100... .......... U U U U 6 6 6 6
\r
428 asr 32 r . 1110...010100... .......... U U U U 8 8 6 6
\r
429 asr 16 . . 1110000011...... A+-DXWL... U U U U 8 8 5 5
\r
430 asl 8 s . 1110...100000... .......... U U U U 6 6 8 8
\r
431 asl 16 s . 1110...101000... .......... U U U U 6 6 8 8
\r
432 asl 32 s . 1110...110000... .......... U U U U 8 8 8 8
\r
433 asl 8 r . 1110...100100... .......... U U U U 6 6 8 8
\r
434 asl 16 r . 1110...101100... .......... U U U U 6 6 8 8
\r
435 asl 32 r . 1110...110100... .......... U U U U 8 8 8 8
\r
436 asl 16 . . 1110000111...... A+-DXWL... U U U U 8 8 6 6
\r
437 bcc 8 . . 0110............ .......... U U U U 10 10 6 6
\r
438 bcc 16 . . 0110....00000000 .......... U U U U 10 10 6 6
\r
439 bcc 32 . . 0110....11111111 .......... U U U U 10 10 6 6
\r
440 bchg 8 r . 0000...101...... A+-DXWL... U U U U 8 8 4 4
\r
441 bchg 32 r d 0000...101000... .......... U U U U 8 8 4 4
\r
442 bchg 8 s . 0000100001...... A+-DXWL... U U U U 12 12 4 4
\r
443 bchg 32 s d 0000100001000... .......... U U U U 12 12 4 4
\r
444 bclr 8 r . 0000...110...... A+-DXWL... U U U U 8 10 4 4
\r
445 bclr 32 r d 0000...110000... .......... U U U U 10 10 4 4
\r
446 bclr 8 s . 0000100010...... A+-DXWL... U U U U 12 12 4 4
\r
447 bclr 32 s d 0000100010000... .......... U U U U 14 14 4 4
\r
448 bfchg 32 . d 1110101011000... .......... . . U U . . 12 12 timing not quite correct
\r
449 bfchg 32 . . 1110101011...... A..DXWL... . . U U . . 20 20
\r
450 bfclr 32 . d 1110110011000... .......... . . U U . . 12 12
\r
451 bfclr 32 . . 1110110011...... A..DXWL... . . U U . . 20 20
\r
452 bfexts 32 . d 1110101111000... .......... . . U U . . 8 8
\r
453 bfexts 32 . . 1110101111...... A..DXWLdx. . . U U . . 15 15
\r
454 bfextu 32 . d 1110100111000... .......... . . U U . . 8 8
\r
455 bfextu 32 . . 1110100111...... A..DXWLdx. . . U U . . 15 15
\r
456 bfffo 32 . d 1110110111000... .......... . . U U . . 18 18
\r
457 bfffo 32 . . 1110110111...... A..DXWLdx. . . U U . . 28 28
\r
458 bfins 32 . d 1110111111000... .......... . . U U . . 10 10
\r
459 bfins 32 . . 1110111111...... A..DXWL... . . U U . . 17 17
\r
460 bfset 32 . d 1110111011000... .......... . . U U . . 12 12
\r
461 bfset 32 . . 1110111011...... A..DXWL... . . U U . . 20 20
\r
462 bftst 32 . d 1110100011000... .......... . . U U . . 6 6
\r
463 bftst 32 . . 1110100011...... A..DXWLdx. . . U U . . 13 13
\r
464 bkpt 0 . . 0100100001001... .......... . U U U . 10 10 10
\r
465 bra 8 . . 01100000........ .......... U U U U 10 10 10 10
\r
466 bra 16 . . 0110000000000000 .......... U U U U 10 10 10 10
\r
467 bra 32 . . 0110000011111111 .......... U U U U 10 10 10 10
\r
468 bset 32 r d 0000...111000... .......... U U U U 8 8 4 4
\r
469 bset 8 r . 0000...111...... A+-DXWL... U U U U 8 8 4 4
\r
470 bset 8 s . 0000100011...... A+-DXWL... U U U U 12 12 4 4
\r
471 bset 32 s d 0000100011000... .......... U U U U 12 12 4 4
\r
472 bsr 8 . . 01100001........ .......... U U U U 18 18 7 7
\r
473 bsr 16 . . 0110000100000000 .......... U U U U 18 18 7 7
\r
474 bsr 32 . . 0110000111111111 .......... U U U U 18 18 7 7
\r
475 btst 8 r . 0000...100...... A+-DXWLdxI U U U U 4 4 4 4
\r
476 btst 32 r d 0000...100000... .......... U U U U 6 6 4 4
\r
477 btst 8 s . 0000100000...... A+-DXWLdx. U U U U 8 8 4 4
\r
478 btst 32 s d 0000100000000... .......... U U U U 10 10 4 4
\r
479 callm 32 . . 0000011011...... A..DXWLdx. . . U U . . 60 60 not properly emulated
\r
480 cas 8 . . 0000101011...... A+-DXWL... . . U U . . 12 12
\r
481 cas 16 . . 0000110011...... A+-DXWL... . . U U . . 12 12
\r
482 cas 32 . . 0000111011...... A+-DXWL... . . U U . . 12 12
\r
483 cas2 16 . . 0000110011111100 .......... . . U U . . 12 12
\r
484 cas2 32 . . 0000111011111100 .......... . . U U . . 12 12
\r
485 chk 16 . d 0100...110000... .......... U U U U 10 8 8 8
\r
486 chk 16 . . 0100...110...... A+-DXWLdxI U U U U 10 8 8 8
\r
487 chk 32 . d 0100...100000... .......... . . U U . . 8 8
\r
488 chk 32 . . 0100...100...... A+-DXWLdxI . . U U . . 8 8
\r
489 chk2cmp2 8 . pcdi 0000000011111010 .......... . . U U . . 23 23
\r
490 chk2cmp2 8 . pcix 0000000011111011 .......... . . U U . . 23 23
\r
491 chk2cmp2 8 . . 0000000011...... A..DXWL... . . U U . . 18 18
\r
492 chk2cmp2 16 . pcdi 0000001011111010 .......... . . U U . . 23 23
\r
493 chk2cmp2 16 . pcix 0000001011111011 .......... . . U U . . 23 23
\r
494 chk2cmp2 16 . . 0000001011...... A..DXWL... . . U U . . 18 18
\r
495 chk2cmp2 32 . pcdi 0000010011111010 .......... . . U U . . 23 23
\r
496 chk2cmp2 32 . pcix 0000010011111011 .......... . . U U . . 23 23
\r
497 chk2cmp2 32 . . 0000010011...... A..DXWL... . . U U . . 18 18
\r
498 clr 8 . d 0100001000000... .......... U U U U 4 4 2 2
\r
499 clr 8 . . 0100001000...... A+-DXWL... U U U U 8 4 4 4
\r
500 clr 16 . d 0100001001000... .......... U U U U 4 4 2 2
\r
501 clr 16 . . 0100001001...... A+-DXWL... U U U U 8 4 4 4
\r
502 clr 32 . d 0100001010000... .......... U U U U 6 6 2 2
\r
503 clr 32 . . 0100001010...... A+-DXWL... U U U U 12 6 4 4
\r
504 cmp 8 . d 1011...000000... .......... U U U U 4 4 2 2
\r
505 cmp 8 . . 1011...000...... A+-DXWLdxI U U U U 4 4 2 2
\r
506 cmp 16 . d 1011...001000... .......... U U U U 4 4 2 2
\r
507 cmp 16 . a 1011...001001... .......... U U U U 4 4 2 2
\r
508 cmp 16 . . 1011...001...... A+-DXWLdxI U U U U 4 4 2 2
\r
509 cmp 32 . d 1011...010000... .......... U U U U 6 6 2 2
\r
510 cmp 32 . a 1011...010001... .......... U U U U 6 6 2 2
\r
511 cmp 32 . . 1011...010...... A+-DXWLdxI U U U U 6 6 2 2
\r
512 cmpa 16 . d 1011...011000... .......... U U U U 6 6 4 4
\r
513 cmpa 16 . a 1011...011001... .......... U U U U 6 6 4 4
\r
514 cmpa 16 . . 1011...011...... A+-DXWLdxI U U U U 6 6 4 4
\r
515 cmpa 32 . d 1011...111000... .......... U U U U 6 6 4 4
\r
516 cmpa 32 . a 1011...111001... .......... U U U U 6 6 4 4
\r
517 cmpa 32 . . 1011...111...... A+-DXWLdxI U U U U 6 6 4 4
\r
518 cmpi 8 . d 0000110000000... .......... U U U U 8 8 2 2
\r
519 cmpi 8 . . 0000110000...... A+-DXWL... U U U U 8 8 2 2
\r
520 cmpi 8 . pcdi 0000110000111010 .......... . . U U . . 7 7
\r
521 cmpi 8 . pcix 0000110000111011 .......... . . U U . . 9 9
\r
522 cmpi 16 . d 0000110001000... .......... U U U U 8 8 2 2
\r
523 cmpi 16 . . 0000110001...... A+-DXWL... U U U U 8 8 2 2
\r
524 cmpi 16 . pcdi 0000110001111010 .......... . . U U . . 7 7
\r
525 cmpi 16 . pcix 0000110001111011 .......... . . U U . . 9 9
\r
526 cmpi 32 . d 0000110010000... .......... U U U U 14 12 2 2
\r
527 cmpi 32 . . 0000110010...... A+-DXWL... U U U U 12 12 2 2
\r
528 cmpi 32 . pcdi 0000110010111010 .......... . . U U . . 7 7
\r
529 cmpi 32 . pcix 0000110010111011 .......... . . U U . . 9 9
\r
530 cmpm 8 . ax7 1011111100001... .......... U U U U 12 12 9 9
\r
531 cmpm 8 . ay7 1011...100001111 .......... U U U U 12 12 9 9
\r
532 cmpm 8 . axy7 1011111100001111 .......... U U U U 12 12 9 9
\r
533 cmpm 8 . . 1011...100001... .......... U U U U 12 12 9 9
\r
534 cmpm 16 . . 1011...101001... .......... U U U U 12 12 9 9
\r
535 cmpm 32 . . 1011...110001... .......... U U U U 20 20 9 9
\r
536 cpbcc 32 . . 1111...01....... .......... . . U . . . 4 . unemulated
\r
537 cpdbcc 32 . . 1111...001001... .......... . . U . . . 4 . unemulated
\r
538 cpgen 32 . . 1111...000...... .......... . . U . . . 4 . unemulated
\r
539 cpscc 32 . . 1111...001...... .......... . . U . . . 4 . unemulated
\r
540 cptrapcc 32 . . 1111...001111... .......... . . U . . . 4 . unemulated
\r
541 dbt 16 . . 0101000011001... .......... U U U U 12 12 6 6
\r
542 dbf 16 . . 0101000111001... .......... U U U U 12 12 6 6
\r
543 dbcc 16 . . 0101....11001... .......... U U U U 12 12 6 6
\r
544 divs 16 . d 1000...111000... .......... U U U U 158 122 56 56
\r
545 divs 16 . . 1000...111...... A+-DXWLdxI U U U U 158 122 56 56
\r
546 divu 16 . d 1000...011000... .......... U U U U 140 108 44 44
\r
547 divu 16 . . 1000...011...... A+-DXWLdxI U U U U 140 108 44 44
\r
548 divl 32 . d 0100110001000... .......... . . U U . . 84 84
\r
549 divl 32 . . 0100110001...... A+-DXWLdxI . . U U . . 84 84
\r
550 eor 8 . d 1011...100000... .......... U U U U 4 4 2 2
\r
551 eor 8 . . 1011...100...... A+-DXWL... U U U U 8 8 4 4
\r
552 eor 16 . d 1011...101000... .......... U U U U 4 4 2 2
\r
553 eor 16 . . 1011...101...... A+-DXWL... U U U U 8 8 4 4
\r
554 eor 32 . d 1011...110000... .......... U U U U 8 6 2 2
\r
555 eor 32 . . 1011...110...... A+-DXWL... U U U U 12 12 4 4
\r
556 eori 16 toc . 0000101000111100 .......... U U U U 20 16 12 12
\r
557 eori 16 tos . 0000101001111100 .......... S S S S 20 16 12 12
\r
558 eori 8 . d 0000101000000... .......... U U U U 8 8 2 2
\r
559 eori 8 . . 0000101000...... A+-DXWL... U U U U 12 12 4 4
\r
560 eori 16 . d 0000101001000... .......... U U U U 8 8 2 2
\r
561 eori 16 . . 0000101001...... A+-DXWL... U U U U 12 12 4 4
\r
562 eori 32 . d 0000101010000... .......... U U U U 16 14 2 2
\r
563 eori 32 . . 0000101010...... A+-DXWL... U U U U 20 20 4 4
\r
564 exg 32 dd . 1100...101000... .......... U U U U 6 6 2 2
\r
565 exg 32 aa . 1100...101001... .......... U U U U 6 6 2 2
\r
566 exg 32 da . 1100...110001... .......... U U U U 6 6 2 2
\r
567 ext 16 . . 0100100010000... .......... U U U U 4 4 4 4
\r
568 ext 32 . . 0100100011000... .......... U U U U 4 4 4 4
\r
569 extb 32 . . 0100100111000... .......... . . U U . . 4 4
\r
570 illegal 0 . . 0100101011111100 .......... U U U U 4 4 4 4
\r
571 jmp 32 . . 0100111011...... A..DXWLdx. U U U U 4 4 0 0
\r
572 jsr 32 . . 0100111010...... A..DXWLdx. U U U U 12 12 0 0
\r
573 lea 32 . . 0100...111...... A..DXWLdx. U U U U 0 0 2 2
\r
574 link 16 . a7 0100111001010111 .......... U U U U 16 16 5 5
\r
575 link 16 . . 0100111001010... .......... U U U U 16 16 5 5
\r
576 link 32 . a7 0100100000001111 .......... . . U U . . 6 6
\r
577 link 32 . . 0100100000001... .......... . . U U . . 6 6
\r
578 lsr 8 s . 1110...000001... .......... U U U U 6 6 4 4
\r
579 lsr 16 s . 1110...001001... .......... U U U U 6 6 4 4
\r
580 lsr 32 s . 1110...010001... .......... U U U U 8 8 4 4
\r
581 lsr 8 r . 1110...000101... .......... U U U U 6 6 6 6
\r
582 lsr 16 r . 1110...001101... .......... U U U U 6 6 6 6
\r
583 lsr 32 r . 1110...010101... .......... U U U U 8 8 6 6
\r
584 lsr 16 . . 1110001011...... A+-DXWL... U U U U 8 8 5 5
\r
585 lsl 8 s . 1110...100001... .......... U U U U 6 6 4 4
\r
586 lsl 16 s . 1110...101001... .......... U U U U 6 6 4 4
\r
587 lsl 32 s . 1110...110001... .......... U U U U 8 8 4 4
\r
588 lsl 8 r . 1110...100101... .......... U U U U 6 6 6 6
\r
589 lsl 16 r . 1110...101101... .......... U U U U 6 6 6 6
\r
590 lsl 32 r . 1110...110101... .......... U U U U 8 8 6 6
\r
591 lsl 16 . . 1110001111...... A+-DXWL... U U U U 8 8 5 5
\r
592 move 8 d d 0001...000000... .......... U U U U 4 4 2 2
\r
593 move 8 d . 0001...000...... A+-DXWLdxI U U U U 4 4 2 2
\r
594 move 8 ai d 0001...010000... .......... U U U U 8 8 4 4
\r
595 move 8 ai . 0001...010...... A+-DXWLdxI U U U U 8 8 4 4
\r
596 move 8 pi d 0001...011000... .......... U U U U 8 8 4 4
\r
597 move 8 pi . 0001...011...... A+-DXWLdxI U U U U 8 8 4 4
\r
598 move 8 pi7 d 0001111011000... .......... U U U U 8 8 4 4
\r
599 move 8 pi7 . 0001111011...... A+-DXWLdxI U U U U 8 8 4 4
\r
600 move 8 pd d 0001...100000... .......... U U U U 8 8 5 5
\r
601 move 8 pd . 0001...100...... A+-DXWLdxI U U U U 8 8 5 5
\r
602 move 8 pd7 d 0001111100000... .......... U U U U 8 8 5 5
\r
603 move 8 pd7 . 0001111100...... A+-DXWLdxI U U U U 8 8 5 5
\r
604 move 8 di d 0001...101000... .......... U U U U 12 12 5 5
\r
605 move 8 di . 0001...101...... A+-DXWLdxI U U U U 12 12 5 5
\r
606 move 8 ix d 0001...110000... .......... U U U U 14 14 7 7
\r
607 move 8 ix . 0001...110...... A+-DXWLdxI U U U U 14 14 7 7
\r
608 move 8 aw d 0001000111000... .......... U U U U 12 12 4 4
\r
609 move 8 aw . 0001000111...... A+-DXWLdxI U U U U 12 12 4 4
\r
610 move 8 al d 0001001111000... .......... U U U U 16 16 6 6
\r
611 move 8 al . 0001001111...... A+-DXWLdxI U U U U 16 16 6 6
\r
612 move 16 d d 0011...000000... .......... U U U U 4 4 2 2
\r
613 move 16 d a 0011...000001... .......... U U U U 4 4 2 2
\r
614 move 16 d . 0011...000...... A+-DXWLdxI U U U U 4 4 2 2
\r
615 move 16 ai d 0011...010000... .......... U U U U 8 8 4 4
\r
616 move 16 ai a 0011...010001... .......... U U U U 8 8 4 4
\r
617 move 16 ai . 0011...010...... A+-DXWLdxI U U U U 8 8 4 4
\r
618 move 16 pi d 0011...011000... .......... U U U U 8 8 4 4
\r
619 move 16 pi a 0011...011001... .......... U U U U 8 8 4 4
\r
620 move 16 pi . 0011...011...... A+-DXWLdxI U U U U 8 8 4 4
\r
621 move 16 pd d 0011...100000... .......... U U U U 8 8 5 5
\r
622 move 16 pd a 0011...100001... .......... U U U U 8 8 5 5
\r
623 move 16 pd . 0011...100...... A+-DXWLdxI U U U U 8 8 5 5
\r
624 move 16 di d 0011...101000... .......... U U U U 12 12 5 5
\r
625 move 16 di a 0011...101001... .......... U U U U 12 12 5 5
\r
626 move 16 di . 0011...101...... A+-DXWLdxI U U U U 12 12 5 5
\r
627 move 16 ix d 0011...110000... .......... U U U U 14 14 7 7
\r
628 move 16 ix a 0011...110001... .......... U U U U 14 14 7 7
\r
629 move 16 ix . 0011...110...... A+-DXWLdxI U U U U 14 14 7 7
\r
630 move 16 aw d 0011000111000... .......... U U U U 12 12 4 4
\r
631 move 16 aw a 0011000111001... .......... U U U U 12 12 4 4
\r
632 move 16 aw . 0011000111...... A+-DXWLdxI U U U U 12 12 4 4
\r
633 move 16 al d 0011001111000... .......... U U U U 16 16 6 6
\r
634 move 16 al a 0011001111001... .......... U U U U 16 16 6 6
\r
635 move 16 al . 0011001111...... A+-DXWLdxI U U U U 16 16 6 6
\r
636 move 32 d d 0010...000000... .......... U U U U 4 4 2 2
\r
637 move 32 d a 0010...000001... .......... U U U U 4 4 2 2
\r
638 move 32 d . 0010...000...... A+-DXWLdxI U U U U 4 4 2 2
\r
639 move 32 ai d 0010...010000... .......... U U U U 12 12 4 4
\r
640 move 32 ai a 0010...010001... .......... U U U U 12 12 4 4
\r
641 move 32 ai . 0010...010...... A+-DXWLdxI U U U U 12 12 4 4
\r
642 move 32 pi d 0010...011000... .......... U U U U 12 12 4 4
\r
643 move 32 pi a 0010...011001... .......... U U U U 12 12 4 4
\r
644 move 32 pi . 0010...011...... A+-DXWLdxI U U U U 12 12 4 4
\r
645 move 32 pd d 0010...100000... .......... U U U U 12 14 5 5
\r
646 move 32 pd a 0010...100001... .......... U U U U 12 14 5 5
\r
647 move 32 pd . 0010...100...... A+-DXWLdxI U U U U 12 14 5 5
\r
648 move 32 di d 0010...101000... .......... U U U U 16 16 5 5
\r
649 move 32 di a 0010...101001... .......... U U U U 16 16 5 5
\r
650 move 32 di . 0010...101...... A+-DXWLdxI U U U U 16 16 5 5
\r
651 move 32 ix d 0010...110000... .......... U U U U 18 18 7 7
\r
652 move 32 ix a 0010...110001... .......... U U U U 18 18 7 7
\r
653 move 32 ix . 0010...110...... A+-DXWLdxI U U U U 18 18 7 7
\r
654 move 32 aw d 0010000111000... .......... U U U U 16 16 4 4
\r
655 move 32 aw a 0010000111001... .......... U U U U 16 16 4 4
\r
656 move 32 aw . 0010000111...... A+-DXWLdxI U U U U 16 16 4 4
\r
657 move 32 al d 0010001111000... .......... U U U U 20 20 6 6
\r
658 move 32 al a 0010001111001... .......... U U U U 20 20 6 6
\r
659 move 32 al . 0010001111...... A+-DXWLdxI U U U U 20 20 6 6
\r
660 movea 16 . d 0011...001000... .......... U U U U 4 4 2 2
\r
661 movea 16 . a 0011...001001... .......... U U U U 4 4 2 2
\r
662 movea 16 . . 0011...001...... A+-DXWLdxI U U U U 4 4 2 2
\r
663 movea 32 . d 0010...001000... .......... U U U U 4 4 2 2
\r
664 movea 32 . a 0010...001001... .......... U U U U 4 4 2 2
\r
665 movea 32 . . 0010...001...... A+-DXWLdxI U U U U 4 4 2 2
\r
666 move 16 frc d 0100001011000... .......... . U U U . 4 4 4
\r
667 move 16 frc . 0100001011...... A+-DXWL... . U U U . 8 4 4
\r
668 move 16 toc d 0100010011000... .......... U U U U 12 12 4 4
\r
669 move 16 toc . 0100010011...... A+-DXWLdxI U U U U 12 12 4 4
\r
670 move 16 frs d 0100000011000... .......... U S S S 6 4 8 8 U only for 000
\r
671 move 16 frs . 0100000011...... A+-DXWL... U S S S 8 8 8 8 U only for 000
\r
672 move 16 tos d 0100011011000... .......... S S S S 12 12 8 8
\r
673 move 16 tos . 0100011011...... A+-DXWLdxI S S S S 12 12 8 8
\r
674 move 32 fru . 0100111001101... .......... S S S S 4 6 2 2
\r
675 move 32 tou . 0100111001100... .......... S S S S 4 6 2 2
\r
676 movec 32 cr . 0100111001111010 .......... . S S S . 12 6 6
\r
677 movec 32 rc . 0100111001111011 .......... . S S S . 10 12 12
\r
678 movem 16 re pd 0100100010100... .......... U U U U 8 8 4 4
\r
679 movem 16 re . 0100100010...... A..DXWL... U U U U 8 8 4 4
\r
680 movem 32 re pd 0100100011100... .......... U U U U 8 8 4 4
\r
681 movem 32 re . 0100100011...... A..DXWL... U U U U 8 8 4 4
\r
682 movem 16 er pi 0100110010011... .......... U U U U 12 12 8 8
\r
683 movem 16 er pcdi 0100110010111010 .......... U U U U 16 16 9 9
\r
684 movem 16 er pcix 0100110010111011 .......... U U U U 18 18 11 11
\r
685 movem 16 er . 0100110010...... A..DXWL... U U U U 12 12 8 8
\r
686 movem 32 er pi 0100110011011... .......... U U U U 12 12 8 8
\r
687 movem 32 er pcdi 0100110011111010 .......... U U U U 16 16 9 9
\r
688 movem 32 er pcix 0100110011111011 .......... U U U U 18 18 11 11
\r
689 movem 32 er . 0100110011...... A..DXWL... U U U U 12 12 8 8
\r
690 movep 16 er . 0000...100001... .......... U U U U 16 16 12 12
\r
691 movep 32 er . 0000...101001... .......... U U U U 24 24 18 18
\r
692 movep 16 re . 0000...110001... .......... U U U U 16 16 11 11
\r
693 movep 32 re . 0000...111001... .......... U U U U 24 24 17 17
\r
694 moveq 32 . . 0111...0........ .......... U U U U 4 4 2 2
\r
695 moves 8 . . 0000111000...... A+-DXWL... . S S S . 14 5 5
\r
696 moves 16 . . 0000111001...... A+-DXWL... . S S S . 14 5 5
\r
697 moves 32 . . 0000111010...... A+-DXWL... . S S S . 16 5 5
\r
698 move16 32 . . 1111011000100... .......... . . . U . . . 4 TODO: correct timing
\r
699 muls 16 . d 1100...111000... .......... U U U U 54 32 27 27
\r
700 muls 16 . . 1100...111...... A+-DXWLdxI U U U U 54 32 27 27
\r
701 mulu 16 . d 1100...011000... .......... U U U U 54 30 27 27
\r
702 mulu 16 . . 1100...011...... A+-DXWLdxI U U U U 54 30 27 27
\r
703 mull 32 . d 0100110000000... .......... . . U U . . 43 43
\r
704 mull 32 . . 0100110000...... A+-DXWLdxI . . U U . . 43 43
\r
705 nbcd 8 . d 0100100000000... .......... U U U U 6 6 6 6
\r
706 nbcd 8 . . 0100100000...... A+-DXWL... U U U U 8 8 6 6
\r
707 neg 8 . d 0100010000000... .......... U U U U 4 4 2 2
\r
708 neg 8 . . 0100010000...... A+-DXWL... U U U U 8 8 4 4
\r
709 neg 16 . d 0100010001000... .......... U U U U 4 4 2 2
\r
710 neg 16 . . 0100010001...... A+-DXWL... U U U U 8 8 4 4
\r
711 neg 32 . d 0100010010000... .......... U U U U 6 6 2 2
\r
712 neg 32 . . 0100010010...... A+-DXWL... U U U U 12 12 4 4
\r
713 negx 8 . d 0100000000000... .......... U U U U 4 4 2 2
\r
714 negx 8 . . 0100000000...... A+-DXWL... U U U U 8 8 4 4
\r
715 negx 16 . d 0100000001000... .......... U U U U 4 4 2 2
\r
716 negx 16 . . 0100000001...... A+-DXWL... U U U U 8 8 4 4
\r
717 negx 32 . d 0100000010000... .......... U U U U 6 6 2 2
\r
718 negx 32 . . 0100000010...... A+-DXWL... U U U U 12 12 4 4
\r
719 nop 0 . . 0100111001110001 .......... U U U U 4 4 2 2
\r
720 not 8 . d 0100011000000... .......... U U U U 4 4 2 2
\r
721 not 8 . . 0100011000...... A+-DXWL... U U U U 8 8 4 4
\r
722 not 16 . d 0100011001000... .......... U U U U 4 4 2 2
\r
723 not 16 . . 0100011001...... A+-DXWL... U U U U 8 8 4 4
\r
724 not 32 . d 0100011010000... .......... U U U U 6 6 2 2
\r
725 not 32 . . 0100011010...... A+-DXWL... U U U U 12 12 4 4
\r
726 or 8 er d 1000...000000... .......... U U U U 4 4 2 2
\r
727 or 8 er . 1000...000...... A+-DXWLdxI U U U U 4 4 2 2
\r
728 or 16 er d 1000...001000... .......... U U U U 4 4 2 2
\r
729 or 16 er . 1000...001...... A+-DXWLdxI U U U U 4 4 2 2
\r
730 or 32 er d 1000...010000... .......... U U U U 6 6 2 2
\r
731 or 32 er . 1000...010...... A+-DXWLdxI U U U U 6 6 2 2
\r
732 or 8 re . 1000...100...... A+-DXWL... U U U U 8 8 4 4
\r
733 or 16 re . 1000...101...... A+-DXWL... U U U U 8 8 4 4
\r
734 or 32 re . 1000...110...... A+-DXWL... U U U U 12 12 4 4
\r
735 ori 16 toc . 0000000000111100 .......... U U U U 20 16 12 12
\r
736 ori 16 tos . 0000000001111100 .......... S S S S 20 16 12 12
\r
737 ori 8 . d 0000000000000... .......... U U U U 8 8 2 2
\r
738 ori 8 . . 0000000000...... A+-DXWL... U U U U 12 12 4 4
\r
739 ori 16 . d 0000000001000... .......... U U U U 8 8 2 2
\r
740 ori 16 . . 0000000001...... A+-DXWL... U U U U 12 12 4 4
\r
741 ori 32 . d 0000000010000... .......... U U U U 16 14 2 2
\r
742 ori 32 . . 0000000010...... A+-DXWL... U U U U 20 20 4 4
\r
743 pack 16 rr . 1000...101000... .......... . . U U . . 6 6
\r
744 pack 16 mm ax7 1000111101001... .......... . . U U . . 13 13
\r
745 pack 16 mm ay7 1000...101001111 .......... . . U U . . 13 13
\r
746 pack 16 mm axy7 1000111101001111 .......... . . U U . . 13 13
\r
747 pack 16 mm . 1000...101001... .......... . . U U . . 13 13
\r
748 pea 32 . . 0100100001...... A..DXWLdx. U U U U 6 6 5 5
\r
749 pflush 32 . . 1111010100011000 .......... . . . S . . . 4 TODO: correct timing
\r
750 reset 0 . . 0100111001110000 .......... S S S S 0 0 0 0
\r
751 ror 8 s . 1110...000011... .......... U U U U 6 6 8 8
\r
752 ror 16 s . 1110...001011... .......... U U U U 6 6 8 8
\r
753 ror 32 s . 1110...010011... .......... U U U U 8 8 8 8
\r
754 ror 8 r . 1110...000111... .......... U U U U 6 6 8 8
\r
755 ror 16 r . 1110...001111... .......... U U U U 6 6 8 8
\r
756 ror 32 r . 1110...010111... .......... U U U U 8 8 8 8
\r
757 ror 16 . . 1110011011...... A+-DXWL... U U U U 8 8 7 7
\r
758 rol 8 s . 1110...100011... .......... U U U U 6 6 8 8
\r
759 rol 16 s . 1110...101011... .......... U U U U 6 6 8 8
\r
760 rol 32 s . 1110...110011... .......... U U U U 8 8 8 8
\r
761 rol 8 r . 1110...100111... .......... U U U U 6 6 8 8
\r
762 rol 16 r . 1110...101111... .......... U U U U 6 6 8 8
\r
763 rol 32 r . 1110...110111... .......... U U U U 8 8 8 8
\r
764 rol 16 . . 1110011111...... A+-DXWL... U U U U 8 8 7 7
\r
765 roxr 8 s . 1110...000010... .......... U U U U 6 6 12 12
\r
766 roxr 16 s . 1110...001010... .......... U U U U 6 6 12 12
\r
767 roxr 32 s . 1110...010010... .......... U U U U 8 8 12 12
\r
768 roxr 8 r . 1110...000110... .......... U U U U 6 6 12 12
\r
769 roxr 16 r . 1110...001110... .......... U U U U 6 6 12 12
\r
770 roxr 32 r . 1110...010110... .......... U U U U 8 8 12 12
\r
771 roxr 16 . . 1110010011...... A+-DXWL... U U U U 8 8 5 5
\r
772 roxl 8 s . 1110...100010... .......... U U U U 6 6 12 12
\r
773 roxl 16 s . 1110...101010... .......... U U U U 6 6 12 12
\r
774 roxl 32 s . 1110...110010... .......... U U U U 8 8 12 12
\r
775 roxl 8 r . 1110...100110... .......... U U U U 6 6 12 12
\r
776 roxl 16 r . 1110...101110... .......... U U U U 6 6 12 12
\r
777 roxl 32 r . 1110...110110... .......... U U U U 8 8 12 12
\r
778 roxl 16 . . 1110010111...... A+-DXWL... U U U U 8 8 5 5
\r
779 rtd 32 . . 0100111001110100 .......... . U U U . 16 10 10
\r
780 rte 32 . . 0100111001110011 .......... S S S S 20 24 20 20 bus fault not emulated
\r
781 rtm 32 . . 000001101100.... .......... . . U U . . 19 19 not properly emulated
\r
782 rtr 32 . . 0100111001110111 .......... U U U U 20 20 14 14
\r
783 rts 32 . . 0100111001110101 .......... U U U U 16 16 10 10
\r
784 sbcd 8 rr . 1000...100000... .......... U U U U 6 6 4 4
\r
785 sbcd 8 mm ax7 1000111100001... .......... U U U U 18 18 16 16
\r
786 sbcd 8 mm ay7 1000...100001111 .......... U U U U 18 18 16 16
\r
787 sbcd 8 mm axy7 1000111100001111 .......... U U U U 18 18 16 16
\r
788 sbcd 8 mm . 1000...100001... .......... U U U U 18 18 16 16
\r
789 st 8 . d 0101000011000... .......... U U U U 6 4 4 4
\r
790 st 8 . . 0101000011...... A+-DXWL... U U U U 8 8 6 6
\r
791 sf 8 . d 0101000111000... .......... U U U U 4 4 4 4
\r
792 sf 8 . . 0101000111...... A+-DXWL... U U U U 8 8 6 6
\r
793 scc 8 . d 0101....11000... .......... U U U U 4 4 4 4
\r
794 scc 8 . . 0101....11...... A+-DXWL... U U U U 8 8 6 6
\r
795 stop 0 . . 0100111001110010 .......... S S S S 4 4 8 8
\r
796 sub 8 er d 1001...000000... .......... U U U U 4 4 2 2
\r
797 sub 8 er . 1001...000...... A+-DXWLdxI U U U U 4 4 2 2
\r
798 sub 16 er d 1001...001000... .......... U U U U 4 4 2 2
\r
799 sub 16 er a 1001...001001... .......... U U U U 4 4 2 2
\r
800 sub 16 er . 1001...001...... A+-DXWLdxI U U U U 4 4 2 2
\r
801 sub 32 er d 1001...010000... .......... U U U U 6 6 2 2
\r
802 sub 32 er a 1001...010001... .......... U U U U 6 6 2 2
\r
803 sub 32 er . 1001...010...... A+-DXWLdxI U U U U 6 6 2 2
\r
804 sub 8 re . 1001...100...... A+-DXWL... U U U U 8 8 4 4
\r
805 sub 16 re . 1001...101...... A+-DXWL... U U U U 8 8 4 4
\r
806 sub 32 re . 1001...110...... A+-DXWL... U U U U 12 12 4 4
\r
807 suba 16 . d 1001...011000... .......... U U U U 8 8 2 2
\r
808 suba 16 . a 1001...011001... .......... U U U U 8 8 2 2
\r
809 suba 16 . . 1001...011...... A+-DXWLdxI U U U U 8 8 2 2
\r
810 suba 32 . d 1001...111000... .......... U U U U 6 6 2 2
\r
811 suba 32 . a 1001...111001... .......... U U U U 6 6 2 2
\r
812 suba 32 . . 1001...111...... A+-DXWLdxI U U U U 6 6 2 2
\r
813 subi 8 . d 0000010000000... .......... U U U U 8 8 2 2
\r
814 subi 8 . . 0000010000...... A+-DXWL... U U U U 12 12 4 4
\r
815 subi 16 . d 0000010001000... .......... U U U U 8 8 2 2
\r
816 subi 16 . . 0000010001...... A+-DXWL... U U U U 12 12 4 4
\r
817 subi 32 . d 0000010010000... .......... U U U U 16 14 2 2
\r
818 subi 32 . . 0000010010...... A+-DXWL... U U U U 20 20 4 4
\r
819 subq 8 . d 0101...100000... .......... U U U U 4 4 2 2
\r
820 subq 8 . . 0101...100...... A+-DXWL... U U U U 8 8 4 4
\r
821 subq 16 . d 0101...101000... .......... U U U U 4 4 2 2
\r
822 subq 16 . a 0101...101001... .......... U U U U 8 4 2 2
\r
823 subq 16 . . 0101...101...... A+-DXWL... U U U U 8 8 4 4
\r
824 subq 32 . d 0101...110000... .......... U U U U 8 8 2 2
\r
825 subq 32 . a 0101...110001... .......... U U U U 8 8 2 2
\r
826 subq 32 . . 0101...110...... A+-DXWL... U U U U 12 12 4 4
\r
827 subx 8 rr . 1001...100000... .......... U U U U 4 4 2 2
\r
828 subx 16 rr . 1001...101000... .......... U U U U 4 4 2 2
\r
829 subx 32 rr . 1001...110000... .......... U U U U 8 6 2 2
\r
830 subx 8 mm ax7 1001111100001... .......... U U U U 18 18 12 12
\r
831 subx 8 mm ay7 1001...100001111 .......... U U U U 18 18 12 12
\r
832 subx 8 mm axy7 1001111100001111 .......... U U U U 18 18 12 12
\r
833 subx 8 mm . 1001...100001... .......... U U U U 18 18 12 12
\r
834 subx 16 mm . 1001...101001... .......... U U U U 18 18 12 12
\r
835 subx 32 mm . 1001...110001... .......... U U U U 30 30 12 12
\r
836 swap 32 . . 0100100001000... .......... U U U U 4 4 4 4
\r
837 tas 8 . d 0100101011000... .......... U U U U 4 4 4 4
\r
838 tas 8 . . 0100101011...... A+-DXWL... U U U U 14 14 12 12
\r
839 trap 0 . . 010011100100.... .......... U U U U 4 4 4 4
\r
840 trapt 0 . . 0101000011111100 .......... . . U U . . 4 4
\r
841 trapt 16 . . 0101000011111010 .......... . . U U . . 6 6
\r
842 trapt 32 . . 0101000011111011 .......... . . U U . . 8 8
\r
843 trapf 0 . . 0101000111111100 .......... . . U U . . 4 4
\r
844 trapf 16 . . 0101000111111010 .......... . . U U . . 6 6
\r
845 trapf 32 . . 0101000111111011 .......... . . U U . . 8 8
\r
846 trapcc 0 . . 0101....11111100 .......... . . U U . . 4 4
\r
847 trapcc 16 . . 0101....11111010 .......... . . U U . . 6 6
\r
848 trapcc 32 . . 0101....11111011 .......... . . U U . . 8 8
\r
849 trapv 0 . . 0100111001110110 .......... U U U U 4 4 4 4
\r
850 tst 8 . d 0100101000000... .......... U U U U 4 4 2 2
\r
851 tst 8 . . 0100101000...... A+-DXWL... U U U U 4 4 2 2
\r
852 tst 8 . pcdi 0100101000111010 .......... . . U U . . 7 7
\r
853 tst 8 . pcix 0100101000111011 .......... . . U U . . 9 9
\r
854 tst 8 . i 0100101000111100 .......... . . U U . . 6 6
\r
855 tst 16 . d 0100101001000... .......... U U U U 4 4 2 2
\r
856 tst 16 . a 0100101001001... .......... . . U U . . 2 2
\r
857 tst 16 . . 0100101001...... A+-DXWL... U U U U 4 4 2 2
\r
858 tst 16 . pcdi 0100101001111010 .......... . . U U . . 7 7
\r
859 tst 16 . pcix 0100101001111011 .......... . . U U . . 9 9
\r
860 tst 16 . i 0100101001111100 .......... . . U U . . 6 6
\r
861 tst 32 . d 0100101010000... .......... U U U U 4 4 2 2
\r
862 tst 32 . a 0100101010001... .......... . . U U . . 2 2
\r
863 tst 32 . . 0100101010...... A+-DXWL... U U U U 4 4 2 2
\r
864 tst 32 . pcdi 0100101010111010 .......... . . U U . . 7 7
\r
865 tst 32 . pcix 0100101010111011 .......... . . U U . . 9 9
\r
866 tst 32 . i 0100101010111100 .......... . . U U . . 6 6
\r
867 unlk 32 . a7 0100111001011111 .......... U U U U 12 12 6 6
\r
868 unlk 32 . . 0100111001011... .......... U U U U 12 12 6 6
\r
869 unpk 16 rr . 1000...110000... .......... . . U U . . 8 8
\r
870 unpk 16 mm ax7 1000111110001... .......... . . U U . . 13 13
\r
871 unpk 16 mm ay7 1000...110001111 .......... . . U U . . 13 13
\r
872 unpk 16 mm axy7 1000111110001111 .......... . . U U . . 13 13
\r
873 unpk 16 mm . 1000...110001... .......... . . U U . . 13 13
\r
877 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
\r
878 M68KMAKE_OPCODE_HANDLER_BODY
\r
880 M68KMAKE_OP(1010, 0, ., .)
\r
882 m68ki_exception_1010();
\r
886 M68KMAKE_OP(1111, 0, ., .)
\r
888 m68ki_exception_1111();
\r
892 M68KMAKE_OP(040fpu0, 32, ., .)
\r
894 if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))
\r
899 m68ki_exception_1111();
\r
903 M68KMAKE_OP(040fpu1, 32, ., .)
\r
905 if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))
\r
910 m68ki_exception_1111();
\r
915 M68KMAKE_OP(abcd, 8, rr, .)
\r
920 uint res = LOW_NIBBLE(src) + LOW_NIBBLE(dst) + XFLAG_AS_1();
\r
925 res += HIGH_NIBBLE(src) + HIGH_NIBBLE(dst);
\r
926 FLAG_V = ~res; /* Undefined V behavior */
\r
929 FLAG_X = FLAG_C = (res > 0x9f) << 8;
\r
933 FLAG_V &= res; /* Undefined V behavior part II */
\r
934 FLAG_N = NFLAG_8(res); /* Undefined N behavior */
\r
936 res = MASK_OUT_ABOVE_8(res);
\r
939 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
\r
943 M68KMAKE_OP(abcd, 8, mm, ax7)
\r
945 uint src = OPER_AY_PD_8();
\r
946 uint ea = EA_A7_PD_8();
\r
947 uint dst = m68ki_read_8(ea);
\r
948 uint res = LOW_NIBBLE(src) + LOW_NIBBLE(dst) + XFLAG_AS_1();
\r
953 res += HIGH_NIBBLE(src) + HIGH_NIBBLE(dst);
\r
954 FLAG_V = ~res; /* Undefined V behavior */
\r
957 FLAG_X = FLAG_C = (res > 0x9f) << 8;
\r
961 FLAG_V &= res; /* Undefined V behavior part II */
\r
962 FLAG_N = NFLAG_8(res); /* Undefined N behavior */
\r
964 res = MASK_OUT_ABOVE_8(res);
\r
967 m68ki_write_8(ea, res);
\r
971 M68KMAKE_OP(abcd, 8, mm, ay7)
\r
973 uint src = OPER_A7_PD_8();
\r
974 uint ea = EA_AX_PD_8();
\r
975 uint dst = m68ki_read_8(ea);
\r
976 uint res = LOW_NIBBLE(src) + LOW_NIBBLE(dst) + XFLAG_AS_1();
\r
981 res += HIGH_NIBBLE(src) + HIGH_NIBBLE(dst);
\r
982 FLAG_V = ~res; /* Undefined V behavior */
\r
985 FLAG_X = FLAG_C = (res > 0x9f) << 8;
\r
989 FLAG_V &= res; /* Undefined V behavior part II */
\r
990 FLAG_N = NFLAG_8(res); /* Undefined N behavior */
\r
992 res = MASK_OUT_ABOVE_8(res);
\r
995 m68ki_write_8(ea, res);
\r
999 M68KMAKE_OP(abcd, 8, mm, axy7)
\r
1001 uint src = OPER_A7_PD_8();
\r
1002 uint ea = EA_A7_PD_8();
\r
1003 uint dst = m68ki_read_8(ea);
\r
1004 uint res = LOW_NIBBLE(src) + LOW_NIBBLE(dst) + XFLAG_AS_1();
\r
1009 res += HIGH_NIBBLE(src) + HIGH_NIBBLE(dst);
\r
1010 FLAG_V = ~res; /* Undefined V behavior */
\r
1013 FLAG_X = FLAG_C = (res > 0x9f) << 8;
\r
1017 FLAG_V &= res; /* Undefined V behavior part II */
\r
1018 FLAG_N = NFLAG_8(res); /* Undefined N behavior */
\r
1020 res = MASK_OUT_ABOVE_8(res);
\r
1023 m68ki_write_8(ea, res);
\r
1027 M68KMAKE_OP(abcd, 8, mm, .)
\r
1029 uint src = OPER_AY_PD_8();
\r
1030 uint ea = EA_AX_PD_8();
\r
1031 uint dst = m68ki_read_8(ea);
\r
1032 uint res = LOW_NIBBLE(src) + LOW_NIBBLE(dst) + XFLAG_AS_1();
\r
1037 res += HIGH_NIBBLE(src) + HIGH_NIBBLE(dst);
\r
1038 FLAG_V = ~res; /* Undefined V behavior */
\r
1041 FLAG_X = FLAG_C = (res > 0x9f) << 8;
\r
1045 FLAG_V &= res; /* Undefined V behavior part II */
\r
1046 FLAG_N = NFLAG_8(res); /* Undefined N behavior */
\r
1048 res = MASK_OUT_ABOVE_8(res);
\r
1051 m68ki_write_8(ea, res);
\r
1055 M68KMAKE_OP(add, 8, er, d)
\r
1057 uint* r_dst = &DX;
\r
1058 uint src = MASK_OUT_ABOVE_8(DY);
\r
1059 uint dst = MASK_OUT_ABOVE_8(*r_dst);
\r
1060 uint res = src + dst;
\r
1062 FLAG_N = NFLAG_8(res);
\r
1063 FLAG_V = VFLAG_ADD_8(src, dst, res);
\r
1064 FLAG_X = FLAG_C = CFLAG_8(res);
\r
1065 FLAG_Z = MASK_OUT_ABOVE_8(res);
\r
1067 *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
\r
1071 M68KMAKE_OP(add, 8, er, .)
\r
1073 uint* r_dst = &DX;
\r
1074 uint src = M68KMAKE_GET_OPER_AY_8;
\r
1075 uint dst = MASK_OUT_ABOVE_8(*r_dst);
\r
1076 uint res = src + dst;
\r
1078 FLAG_N = NFLAG_8(res);
\r
1079 FLAG_V = VFLAG_ADD_8(src, dst, res);
\r
1080 FLAG_X = FLAG_C = CFLAG_8(res);
\r
1081 FLAG_Z = MASK_OUT_ABOVE_8(res);
\r
1083 *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
\r
1087 M68KMAKE_OP(add, 16, er, d)
\r
1089 uint* r_dst = &DX;
\r
1090 uint src = MASK_OUT_ABOVE_16(DY);
\r
1091 uint dst = MASK_OUT_ABOVE_16(*r_dst);
\r
1092 uint res = src + dst;
\r
1094 FLAG_N = NFLAG_16(res);
\r
1095 FLAG_V = VFLAG_ADD_16(src, dst, res);
\r
1096 FLAG_X = FLAG_C = CFLAG_16(res);
\r
1097 FLAG_Z = MASK_OUT_ABOVE_16(res);
\r
1099 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
\r
1103 M68KMAKE_OP(add, 16, er, a)
\r
1105 uint* r_dst = &DX;
\r
1106 uint src = MASK_OUT_ABOVE_16(AY);
\r
1107 uint dst = MASK_OUT_ABOVE_16(*r_dst);
\r
1108 uint res = src + dst;
\r
1110 FLAG_N = NFLAG_16(res);
\r
1111 FLAG_V = VFLAG_ADD_16(src, dst, res);
\r
1112 FLAG_X = FLAG_C = CFLAG_16(res);
\r
1113 FLAG_Z = MASK_OUT_ABOVE_16(res);
\r
1115 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
\r
1119 M68KMAKE_OP(add, 16, er, .)
\r
1121 uint* r_dst = &DX;
\r
1122 uint src = M68KMAKE_GET_OPER_AY_16;
\r
1123 uint dst = MASK_OUT_ABOVE_16(*r_dst);
\r
1124 uint res = src + dst;
\r
1126 FLAG_N = NFLAG_16(res);
\r
1127 FLAG_V = VFLAG_ADD_16(src, dst, res);
\r
1128 FLAG_X = FLAG_C = CFLAG_16(res);
\r
1129 FLAG_Z = MASK_OUT_ABOVE_16(res);
\r
1131 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
\r
1135 M68KMAKE_OP(add, 32, er, d)
\r
1137 uint* r_dst = &DX;
\r
1139 uint dst = *r_dst;
\r
1140 uint res = src + dst;
\r
1142 FLAG_N = NFLAG_32(res);
\r
1143 FLAG_V = VFLAG_ADD_32(src, dst, res);
\r
1144 FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
\r
1145 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
1151 M68KMAKE_OP(add, 32, er, a)
\r
1153 uint* r_dst = &DX;
\r
1155 uint dst = *r_dst;
\r
1156 uint res = src + dst;
\r
1158 FLAG_N = NFLAG_32(res);
\r
1159 FLAG_V = VFLAG_ADD_32(src, dst, res);
\r
1160 FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
\r
1161 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
1167 M68KMAKE_OP(add, 32, er, .)
\r
1169 uint* r_dst = &DX;
\r
1170 uint src = M68KMAKE_GET_OPER_AY_32;
\r
1171 uint dst = *r_dst;
\r
1172 uint res = src + dst;
\r
1174 FLAG_N = NFLAG_32(res);
\r
1175 FLAG_V = VFLAG_ADD_32(src, dst, res);
\r
1176 FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
\r
1177 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
1183 M68KMAKE_OP(add, 8, re, .)
\r
1185 uint ea = M68KMAKE_GET_EA_AY_8;
\r
1186 uint src = MASK_OUT_ABOVE_8(DX);
\r
1187 uint dst = m68ki_read_8(ea);
\r
1188 uint res = src + dst;
\r
1190 FLAG_N = NFLAG_8(res);
\r
1191 FLAG_V = VFLAG_ADD_8(src, dst, res);
\r
1192 FLAG_X = FLAG_C = CFLAG_8(res);
\r
1193 FLAG_Z = MASK_OUT_ABOVE_8(res);
\r
1195 m68ki_write_8(ea, FLAG_Z);
\r
1199 M68KMAKE_OP(add, 16, re, .)
\r
1201 uint ea = M68KMAKE_GET_EA_AY_16;
\r
1202 uint src = MASK_OUT_ABOVE_16(DX);
\r
1203 uint dst = m68ki_read_16(ea);
\r
1204 uint res = src + dst;
\r
1206 FLAG_N = NFLAG_16(res);
\r
1207 FLAG_V = VFLAG_ADD_16(src, dst, res);
\r
1208 FLAG_X = FLAG_C = CFLAG_16(res);
\r
1209 FLAG_Z = MASK_OUT_ABOVE_16(res);
\r
1211 m68ki_write_16(ea, FLAG_Z);
\r
1215 M68KMAKE_OP(add, 32, re, .)
\r
1217 uint ea = M68KMAKE_GET_EA_AY_32;
\r
1219 uint dst = m68ki_read_32(ea);
\r
1220 uint res = src + dst;
\r
1222 FLAG_N = NFLAG_32(res);
\r
1223 FLAG_V = VFLAG_ADD_32(src, dst, res);
\r
1224 FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
\r
1225 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
1227 m68ki_write_32(ea, FLAG_Z);
\r
1231 M68KMAKE_OP(adda, 16, ., d)
\r
1233 uint* r_dst = &AX;
\r
1235 *r_dst = MASK_OUT_ABOVE_32(*r_dst + MAKE_INT_16(DY));
\r
1239 M68KMAKE_OP(adda, 16, ., a)
\r
1241 uint* r_dst = &AX;
\r
1243 *r_dst = MASK_OUT_ABOVE_32(*r_dst + MAKE_INT_16(AY));
\r
1247 M68KMAKE_OP(adda, 16, ., .)
\r
1249 uint* r_dst = &AX;
\r
1250 uint src = MAKE_INT_16(M68KMAKE_GET_OPER_AY_16);
\r
1252 *r_dst = MASK_OUT_ABOVE_32(*r_dst + src);
\r
1256 M68KMAKE_OP(adda, 32, ., d)
\r
1258 uint* r_dst = &AX;
\r
1260 *r_dst = MASK_OUT_ABOVE_32(*r_dst + DY);
\r
1264 M68KMAKE_OP(adda, 32, ., a)
\r
1266 uint* r_dst = &AX;
\r
1268 *r_dst = MASK_OUT_ABOVE_32(*r_dst + AY);
\r
1272 M68KMAKE_OP(adda, 32, ., .)
\r
1274 uint* r_dst = &AX;
\r
1275 uint src = M68KMAKE_GET_OPER_AY_32; // notaz
\r
1277 *r_dst = MASK_OUT_ABOVE_32(*r_dst + src);
\r
1281 M68KMAKE_OP(addi, 8, ., d)
\r
1283 uint* r_dst = &DY;
\r
1284 uint src = OPER_I_8();
\r
1285 uint dst = MASK_OUT_ABOVE_8(*r_dst);
\r
1286 uint res = src + dst;
\r
1288 FLAG_N = NFLAG_8(res);
\r
1289 FLAG_V = VFLAG_ADD_8(src, dst, res);
\r
1290 FLAG_X = FLAG_C = CFLAG_8(res);
\r
1291 FLAG_Z = MASK_OUT_ABOVE_8(res);
\r
1293 *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
\r
1297 M68KMAKE_OP(addi, 8, ., .)
\r
1299 uint src = OPER_I_8();
\r
1300 uint ea = M68KMAKE_GET_EA_AY_8;
\r
1301 uint dst = m68ki_read_8(ea);
\r
1302 uint res = src + dst;
\r
1304 FLAG_N = NFLAG_8(res);
\r
1305 FLAG_V = VFLAG_ADD_8(src, dst, res);
\r
1306 FLAG_X = FLAG_C = CFLAG_8(res);
\r
1307 FLAG_Z = MASK_OUT_ABOVE_8(res);
\r
1309 m68ki_write_8(ea, FLAG_Z);
\r
1313 M68KMAKE_OP(addi, 16, ., d)
\r
1315 uint* r_dst = &DY;
\r
1316 uint src = OPER_I_16();
\r
1317 uint dst = MASK_OUT_ABOVE_16(*r_dst);
\r
1318 uint res = src + dst;
\r
1320 FLAG_N = NFLAG_16(res);
\r
1321 FLAG_V = VFLAG_ADD_16(src, dst, res);
\r
1322 FLAG_X = FLAG_C = CFLAG_16(res);
\r
1323 FLAG_Z = MASK_OUT_ABOVE_16(res);
\r
1325 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
\r
1329 M68KMAKE_OP(addi, 16, ., .)
\r
1331 uint src = OPER_I_16();
\r
1332 uint ea = M68KMAKE_GET_EA_AY_16;
\r
1333 uint dst = m68ki_read_16(ea);
\r
1334 uint res = src + dst;
\r
1336 FLAG_N = NFLAG_16(res);
\r
1337 FLAG_V = VFLAG_ADD_16(src, dst, res);
\r
1338 FLAG_X = FLAG_C = CFLAG_16(res);
\r
1339 FLAG_Z = MASK_OUT_ABOVE_16(res);
\r
1341 m68ki_write_16(ea, FLAG_Z);
\r
1345 M68KMAKE_OP(addi, 32, ., d)
\r
1347 uint* r_dst = &DY;
\r
1348 uint src = OPER_I_32();
\r
1349 uint dst = *r_dst;
\r
1350 uint res = src + dst;
\r
1352 FLAG_N = NFLAG_32(res);
\r
1353 FLAG_V = VFLAG_ADD_32(src, dst, res);
\r
1354 FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
\r
1355 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
1361 M68KMAKE_OP(addi, 32, ., .)
\r
1363 uint src = OPER_I_32();
\r
1364 uint ea = M68KMAKE_GET_EA_AY_32;
\r
1365 uint dst = m68ki_read_32(ea);
\r
1366 uint res = src + dst;
\r
1368 FLAG_N = NFLAG_32(res);
\r
1369 FLAG_V = VFLAG_ADD_32(src, dst, res);
\r
1370 FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
\r
1371 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
1373 m68ki_write_32(ea, FLAG_Z);
\r
1377 M68KMAKE_OP(addq, 8, ., d)
\r
1379 uint* r_dst = &DY;
\r
1380 uint src = (((REG_IR >> 9) - 1) & 7) + 1;
\r
1381 uint dst = MASK_OUT_ABOVE_8(*r_dst);
\r
1382 uint res = src + dst;
\r
1384 FLAG_N = NFLAG_8(res);
\r
1385 FLAG_V = VFLAG_ADD_8(src, dst, res);
\r
1386 FLAG_X = FLAG_C = CFLAG_8(res);
\r
1387 FLAG_Z = MASK_OUT_ABOVE_8(res);
\r
1389 *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
\r
1393 M68KMAKE_OP(addq, 8, ., .)
\r
1395 uint src = (((REG_IR >> 9) - 1) & 7) + 1;
\r
1396 uint ea = M68KMAKE_GET_EA_AY_8;
\r
1397 uint dst = m68ki_read_8(ea);
\r
1398 uint res = src + dst;
\r
1400 FLAG_N = NFLAG_8(res);
\r
1401 FLAG_V = VFLAG_ADD_8(src, dst, res);
\r
1402 FLAG_X = FLAG_C = CFLAG_8(res);
\r
1403 FLAG_Z = MASK_OUT_ABOVE_8(res);
\r
1405 m68ki_write_8(ea, FLAG_Z);
\r
1409 M68KMAKE_OP(addq, 16, ., d)
\r
1411 uint* r_dst = &DY;
\r
1412 uint src = (((REG_IR >> 9) - 1) & 7) + 1;
\r
1413 uint dst = MASK_OUT_ABOVE_16(*r_dst);
\r
1414 uint res = src + dst;
\r
1416 FLAG_N = NFLAG_16(res);
\r
1417 FLAG_V = VFLAG_ADD_16(src, dst, res);
\r
1418 FLAG_X = FLAG_C = CFLAG_16(res);
\r
1419 FLAG_Z = MASK_OUT_ABOVE_16(res);
\r
1421 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
\r
1425 M68KMAKE_OP(addq, 16, ., a)
\r
1427 uint* r_dst = &AY;
\r
1429 *r_dst = MASK_OUT_ABOVE_32(*r_dst + (((REG_IR >> 9) - 1) & 7) + 1);
\r
1433 M68KMAKE_OP(addq, 16, ., .)
\r
1435 uint src = (((REG_IR >> 9) - 1) & 7) + 1;
\r
1436 uint ea = M68KMAKE_GET_EA_AY_16;
\r
1437 uint dst = m68ki_read_16(ea);
\r
1438 uint res = src + dst;
\r
1440 FLAG_N = NFLAG_16(res);
\r
1441 FLAG_V = VFLAG_ADD_16(src, dst, res);
\r
1442 FLAG_X = FLAG_C = CFLAG_16(res);
\r
1443 FLAG_Z = MASK_OUT_ABOVE_16(res);
\r
1445 m68ki_write_16(ea, FLAG_Z);
\r
1449 M68KMAKE_OP(addq, 32, ., d)
\r
1451 uint* r_dst = &DY;
\r
1452 uint src = (((REG_IR >> 9) - 1) & 7) + 1;
\r
1453 uint dst = *r_dst;
\r
1454 uint res = src + dst;
\r
1456 FLAG_N = NFLAG_32(res);
\r
1457 FLAG_V = VFLAG_ADD_32(src, dst, res);
\r
1458 FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
\r
1459 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
1465 M68KMAKE_OP(addq, 32, ., a)
\r
1467 uint* r_dst = &AY;
\r
1469 *r_dst = MASK_OUT_ABOVE_32(*r_dst + (((REG_IR >> 9) - 1) & 7) + 1);
\r
1473 M68KMAKE_OP(addq, 32, ., .)
\r
1475 uint src = (((REG_IR >> 9) - 1) & 7) + 1;
\r
1476 uint ea = M68KMAKE_GET_EA_AY_32;
\r
1477 uint dst = m68ki_read_32(ea);
\r
1478 uint res = src + dst;
\r
1481 FLAG_N = NFLAG_32(res);
\r
1482 FLAG_V = VFLAG_ADD_32(src, dst, res);
\r
1483 FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
\r
1484 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
1486 m68ki_write_32(ea, FLAG_Z);
\r
1490 M68KMAKE_OP(addx, 8, rr, .)
\r
1492 uint* r_dst = &DX;
\r
1493 uint src = MASK_OUT_ABOVE_8(DY);
\r
1494 uint dst = MASK_OUT_ABOVE_8(*r_dst);
\r
1495 uint res = src + dst + XFLAG_AS_1();
\r
1497 FLAG_N = NFLAG_8(res);
\r
1498 FLAG_V = VFLAG_ADD_8(src, dst, res);
\r
1499 FLAG_X = FLAG_C = CFLAG_8(res);
\r
1501 res = MASK_OUT_ABOVE_8(res);
\r
1504 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
\r
1508 M68KMAKE_OP(addx, 16, rr, .)
\r
1510 uint* r_dst = &DX;
\r
1511 uint src = MASK_OUT_ABOVE_16(DY);
\r
1512 uint dst = MASK_OUT_ABOVE_16(*r_dst);
\r
1513 uint res = src + dst + XFLAG_AS_1();
\r
1515 FLAG_N = NFLAG_16(res);
\r
1516 FLAG_V = VFLAG_ADD_16(src, dst, res);
\r
1517 FLAG_X = FLAG_C = CFLAG_16(res);
\r
1519 res = MASK_OUT_ABOVE_16(res);
\r
1522 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
\r
1526 M68KMAKE_OP(addx, 32, rr, .)
\r
1528 uint* r_dst = &DX;
\r
1530 uint dst = *r_dst;
\r
1531 uint res = src + dst + XFLAG_AS_1();
\r
1533 FLAG_N = NFLAG_32(res);
\r
1534 FLAG_V = VFLAG_ADD_32(src, dst, res);
\r
1535 FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
\r
1537 res = MASK_OUT_ABOVE_32(res);
\r
1544 M68KMAKE_OP(addx, 8, mm, ax7)
\r
1546 uint src = OPER_AY_PD_8();
\r
1547 uint ea = EA_A7_PD_8();
\r
1548 uint dst = m68ki_read_8(ea);
\r
1549 uint res = src + dst + XFLAG_AS_1();
\r
1551 FLAG_N = NFLAG_8(res);
\r
1552 FLAG_V = VFLAG_ADD_8(src, dst, res);
\r
1553 FLAG_X = FLAG_C = CFLAG_8(res);
\r
1555 res = MASK_OUT_ABOVE_8(res);
\r
1558 m68ki_write_8(ea, res);
\r
1562 M68KMAKE_OP(addx, 8, mm, ay7)
\r
1564 uint src = OPER_A7_PD_8();
\r
1565 uint ea = EA_AX_PD_8();
\r
1566 uint dst = m68ki_read_8(ea);
\r
1567 uint res = src + dst + XFLAG_AS_1();
\r
1569 FLAG_N = NFLAG_8(res);
\r
1570 FLAG_V = VFLAG_ADD_8(src, dst, res);
\r
1571 FLAG_X = FLAG_C = CFLAG_8(res);
\r
1573 res = MASK_OUT_ABOVE_8(res);
\r
1576 m68ki_write_8(ea, res);
\r
1580 M68KMAKE_OP(addx, 8, mm, axy7)
\r
1582 uint src = OPER_A7_PD_8();
\r
1583 uint ea = EA_A7_PD_8();
\r
1584 uint dst = m68ki_read_8(ea);
\r
1585 uint res = src + dst + XFLAG_AS_1();
\r
1587 FLAG_N = NFLAG_8(res);
\r
1588 FLAG_V = VFLAG_ADD_8(src, dst, res);
\r
1589 FLAG_X = FLAG_C = CFLAG_8(res);
\r
1591 res = MASK_OUT_ABOVE_8(res);
\r
1594 m68ki_write_8(ea, res);
\r
1598 M68KMAKE_OP(addx, 8, mm, .)
\r
1600 uint src = OPER_AY_PD_8();
\r
1601 uint ea = EA_AX_PD_8();
\r
1602 uint dst = m68ki_read_8(ea);
\r
1603 uint res = src + dst + XFLAG_AS_1();
\r
1605 FLAG_N = NFLAG_8(res);
\r
1606 FLAG_V = VFLAG_ADD_8(src, dst, res);
\r
1607 FLAG_X = FLAG_C = CFLAG_8(res);
\r
1609 res = MASK_OUT_ABOVE_8(res);
\r
1612 m68ki_write_8(ea, res);
\r
1616 M68KMAKE_OP(addx, 16, mm, .)
\r
1618 uint src = OPER_AY_PD_16();
\r
1619 uint ea = EA_AX_PD_16();
\r
1620 uint dst = m68ki_read_16(ea);
\r
1621 uint res = src + dst + XFLAG_AS_1();
\r
1623 FLAG_N = NFLAG_16(res);
\r
1624 FLAG_V = VFLAG_ADD_16(src, dst, res);
\r
1625 FLAG_X = FLAG_C = CFLAG_16(res);
\r
1627 res = MASK_OUT_ABOVE_16(res);
\r
1630 m68ki_write_16(ea, res);
\r
1634 M68KMAKE_OP(addx, 32, mm, .)
\r
1636 uint src = OPER_AY_PD_32();
\r
1637 uint ea = EA_AX_PD_32();
\r
1638 uint dst = m68ki_read_32(ea);
\r
1639 uint res = src + dst + XFLAG_AS_1();
\r
1641 FLAG_N = NFLAG_32(res);
\r
1642 FLAG_V = VFLAG_ADD_32(src, dst, res);
\r
1643 FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
\r
1645 res = MASK_OUT_ABOVE_32(res);
\r
1648 m68ki_write_32(ea, res);
\r
1652 M68KMAKE_OP(and, 8, er, d)
\r
1654 FLAG_Z = MASK_OUT_ABOVE_8(DX &= (DY | 0xffffff00));
\r
1656 FLAG_N = NFLAG_8(FLAG_Z);
\r
1657 FLAG_C = CFLAG_CLEAR;
\r
1658 FLAG_V = VFLAG_CLEAR;
\r
1662 M68KMAKE_OP(and, 8, er, .)
\r
1664 FLAG_Z = MASK_OUT_ABOVE_8(DX &= (M68KMAKE_GET_OPER_AY_8 | 0xffffff00));
\r
1666 FLAG_N = NFLAG_8(FLAG_Z);
\r
1667 FLAG_C = CFLAG_CLEAR;
\r
1668 FLAG_V = VFLAG_CLEAR;
\r
1672 M68KMAKE_OP(and, 16, er, d)
\r
1674 FLAG_Z = MASK_OUT_ABOVE_16(DX &= (DY | 0xffff0000));
\r
1676 FLAG_N = NFLAG_16(FLAG_Z);
\r
1677 FLAG_C = CFLAG_CLEAR;
\r
1678 FLAG_V = VFLAG_CLEAR;
\r
1682 M68KMAKE_OP(and, 16, er, .)
\r
1684 FLAG_Z = MASK_OUT_ABOVE_16(DX &= (M68KMAKE_GET_OPER_AY_16 | 0xffff0000));
\r
1686 FLAG_N = NFLAG_16(FLAG_Z);
\r
1687 FLAG_C = CFLAG_CLEAR;
\r
1688 FLAG_V = VFLAG_CLEAR;
\r
1692 M68KMAKE_OP(and, 32, er, d)
\r
1694 FLAG_Z = DX &= DY;
\r
1696 FLAG_N = NFLAG_32(FLAG_Z);
\r
1697 FLAG_C = CFLAG_CLEAR;
\r
1698 FLAG_V = VFLAG_CLEAR;
\r
1702 M68KMAKE_OP(and, 32, er, .)
\r
1704 FLAG_Z = DX &= M68KMAKE_GET_OPER_AY_32;
\r
1706 FLAG_N = NFLAG_32(FLAG_Z);
\r
1707 FLAG_C = CFLAG_CLEAR;
\r
1708 FLAG_V = VFLAG_CLEAR;
\r
1712 M68KMAKE_OP(and, 8, re, .)
\r
1714 uint ea = M68KMAKE_GET_EA_AY_8;
\r
1715 uint res = DX & m68ki_read_8(ea);
\r
1717 FLAG_N = NFLAG_8(res);
\r
1718 FLAG_C = CFLAG_CLEAR;
\r
1719 FLAG_V = VFLAG_CLEAR;
\r
1720 FLAG_Z = MASK_OUT_ABOVE_8(res);
\r
1722 m68ki_write_8(ea, FLAG_Z);
\r
1726 M68KMAKE_OP(and, 16, re, .)
\r
1728 uint ea = M68KMAKE_GET_EA_AY_16;
\r
1729 uint res = DX & m68ki_read_16(ea);
\r
1731 FLAG_N = NFLAG_16(res);
\r
1732 FLAG_C = CFLAG_CLEAR;
\r
1733 FLAG_V = VFLAG_CLEAR;
\r
1734 FLAG_Z = MASK_OUT_ABOVE_16(res);
\r
1736 m68ki_write_16(ea, FLAG_Z);
\r
1740 M68KMAKE_OP(and, 32, re, .)
\r
1742 uint ea = M68KMAKE_GET_EA_AY_32;
\r
1743 uint res = DX & m68ki_read_32(ea);
\r
1745 FLAG_N = NFLAG_32(res);
\r
1747 FLAG_C = CFLAG_CLEAR;
\r
1748 FLAG_V = VFLAG_CLEAR;
\r
1750 m68ki_write_32(ea, res);
\r
1754 M68KMAKE_OP(andi, 8, ., d)
\r
1756 FLAG_Z = MASK_OUT_ABOVE_8(DY &= (OPER_I_8() | 0xffffff00));
\r
1758 FLAG_N = NFLAG_8(FLAG_Z);
\r
1759 FLAG_C = CFLAG_CLEAR;
\r
1760 FLAG_V = VFLAG_CLEAR;
\r
1764 M68KMAKE_OP(andi, 8, ., .)
\r
1766 uint src = OPER_I_8();
\r
1767 uint ea = M68KMAKE_GET_EA_AY_8;
\r
1768 uint res = src & m68ki_read_8(ea);
\r
1770 FLAG_N = NFLAG_8(res);
\r
1772 FLAG_C = CFLAG_CLEAR;
\r
1773 FLAG_V = VFLAG_CLEAR;
\r
1775 m68ki_write_8(ea, res);
\r
1779 M68KMAKE_OP(andi, 16, ., d)
\r
1781 FLAG_Z = MASK_OUT_ABOVE_16(DY &= (OPER_I_16() | 0xffff0000));
\r
1783 FLAG_N = NFLAG_16(FLAG_Z);
\r
1784 FLAG_C = CFLAG_CLEAR;
\r
1785 FLAG_V = VFLAG_CLEAR;
\r
1789 M68KMAKE_OP(andi, 16, ., .)
\r
1791 uint src = OPER_I_16();
\r
1792 uint ea = M68KMAKE_GET_EA_AY_16;
\r
1793 uint res = src & m68ki_read_16(ea);
\r
1795 FLAG_N = NFLAG_16(res);
\r
1797 FLAG_C = CFLAG_CLEAR;
\r
1798 FLAG_V = VFLAG_CLEAR;
\r
1800 m68ki_write_16(ea, res);
\r
1804 M68KMAKE_OP(andi, 32, ., d)
\r
1806 FLAG_Z = DY &= (OPER_I_32());
\r
1808 FLAG_N = NFLAG_32(FLAG_Z);
\r
1809 FLAG_C = CFLAG_CLEAR;
\r
1810 FLAG_V = VFLAG_CLEAR;
\r
1814 M68KMAKE_OP(andi, 32, ., .)
\r
1816 uint src = OPER_I_32();
\r
1817 uint ea = M68KMAKE_GET_EA_AY_32;
\r
1818 uint res = src & m68ki_read_32(ea);
\r
1820 FLAG_N = NFLAG_32(res);
\r
1822 FLAG_C = CFLAG_CLEAR;
\r
1823 FLAG_V = VFLAG_CLEAR;
\r
1825 m68ki_write_32(ea, res);
\r
1829 M68KMAKE_OP(andi, 16, toc, .)
\r
1831 m68ki_set_ccr(m68ki_get_ccr() & OPER_I_16());
\r
1835 M68KMAKE_OP(andi, 16, tos, .)
\r
1839 uint src = OPER_I_16();
\r
1840 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
1841 m68ki_set_sr(m68ki_get_sr() & src);
\r
1844 m68ki_exception_privilege_violation();
\r
1848 M68KMAKE_OP(asr, 8, s, .)
\r
1850 uint* r_dst = &DY;
\r
1851 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
\r
1852 uint src = MASK_OUT_ABOVE_8(*r_dst);
\r
1853 uint res = src >> shift;
\r
1856 USE_CYCLES(shift<<CYC_SHIFT);
\r
1858 if(GET_MSB_8(src))
\r
1859 res |= m68ki_shift_8_table[shift];
\r
1861 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
\r
1863 FLAG_N = NFLAG_8(res);
\r
1865 FLAG_V = VFLAG_CLEAR;
\r
1866 FLAG_X = FLAG_C = src << (9-shift);
\r
1870 M68KMAKE_OP(asr, 16, s, .)
\r
1872 uint* r_dst = &DY;
\r
1873 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
\r
1874 uint src = MASK_OUT_ABOVE_16(*r_dst);
\r
1875 uint res = src >> shift;
\r
1878 USE_CYCLES(shift<<CYC_SHIFT);
\r
1880 if(GET_MSB_16(src))
\r
1881 res |= m68ki_shift_16_table[shift];
\r
1883 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
\r
1885 FLAG_N = NFLAG_16(res);
\r
1887 FLAG_V = VFLAG_CLEAR;
\r
1888 FLAG_X = FLAG_C = src << (9-shift);
\r
1892 M68KMAKE_OP(asr, 32, s, .)
\r
1894 uint* r_dst = &DY;
\r
1895 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
\r
1896 uint src = *r_dst;
\r
1897 uint res = src >> shift;
\r
1900 USE_CYCLES(shift<<CYC_SHIFT);
\r
1902 if(GET_MSB_32(src))
\r
1903 res |= m68ki_shift_32_table[shift];
\r
1907 FLAG_N = NFLAG_32(res);
\r
1909 FLAG_V = VFLAG_CLEAR;
\r
1910 FLAG_X = FLAG_C = src << (9-shift);
\r
1914 M68KMAKE_OP(asr, 8, r, .)
\r
1916 uint* r_dst = &DY;
\r
1917 uint shift = DX & 0x3f;
\r
1918 uint src = MASK_OUT_ABOVE_8(*r_dst);
\r
1919 uint res = src >> shift;
\r
1923 USE_CYCLES(shift<<CYC_SHIFT);
\r
1927 if(GET_MSB_8(src))
\r
1928 res |= m68ki_shift_8_table[shift];
\r
1930 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
\r
1932 FLAG_X = FLAG_C = src << (9-shift);
\r
1933 FLAG_N = NFLAG_8(res);
\r
1935 FLAG_V = VFLAG_CLEAR;
\r
1939 if(GET_MSB_8(src))
\r
1942 FLAG_C = CFLAG_SET;
\r
1943 FLAG_X = XFLAG_SET;
\r
1944 FLAG_N = NFLAG_SET;
\r
1945 FLAG_Z = ZFLAG_CLEAR;
\r
1946 FLAG_V = VFLAG_CLEAR;
\r
1950 *r_dst &= 0xffffff00;
\r
1951 FLAG_C = CFLAG_CLEAR;
\r
1952 FLAG_X = XFLAG_CLEAR;
\r
1953 FLAG_N = NFLAG_CLEAR;
\r
1954 FLAG_Z = ZFLAG_SET;
\r
1955 FLAG_V = VFLAG_CLEAR;
\r
1959 FLAG_C = CFLAG_CLEAR;
\r
1960 FLAG_N = NFLAG_8(src);
\r
1962 FLAG_V = VFLAG_CLEAR;
\r
1966 M68KMAKE_OP(asr, 16, r, .)
\r
1968 uint* r_dst = &DY;
\r
1969 uint shift = DX & 0x3f;
\r
1970 uint src = MASK_OUT_ABOVE_16(*r_dst);
\r
1971 uint res = src >> shift;
\r
1975 USE_CYCLES(shift<<CYC_SHIFT);
\r
1979 if(GET_MSB_16(src))
\r
1980 res |= m68ki_shift_16_table[shift];
\r
1982 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
\r
1984 FLAG_C = FLAG_X = (src >> (shift - 1))<<8;
\r
1985 FLAG_N = NFLAG_16(res);
\r
1987 FLAG_V = VFLAG_CLEAR;
\r
1991 if(GET_MSB_16(src))
\r
1994 FLAG_C = CFLAG_SET;
\r
1995 FLAG_X = XFLAG_SET;
\r
1996 FLAG_N = NFLAG_SET;
\r
1997 FLAG_Z = ZFLAG_CLEAR;
\r
1998 FLAG_V = VFLAG_CLEAR;
\r
2002 *r_dst &= 0xffff0000;
\r
2003 FLAG_C = CFLAG_CLEAR;
\r
2004 FLAG_X = XFLAG_CLEAR;
\r
2005 FLAG_N = NFLAG_CLEAR;
\r
2006 FLAG_Z = ZFLAG_SET;
\r
2007 FLAG_V = VFLAG_CLEAR;
\r
2011 FLAG_C = CFLAG_CLEAR;
\r
2012 FLAG_N = NFLAG_16(src);
\r
2014 FLAG_V = VFLAG_CLEAR;
\r
2018 M68KMAKE_OP(asr, 32, r, .)
\r
2020 uint* r_dst = &DY;
\r
2021 uint shift = DX & 0x3f;
\r
2022 uint src = *r_dst;
\r
2023 uint res = src >> shift;
\r
2027 USE_CYCLES(shift<<CYC_SHIFT);
\r
2031 if(GET_MSB_32(src))
\r
2032 res |= m68ki_shift_32_table[shift];
\r
2036 FLAG_C = FLAG_X = (src >> (shift - 1))<<8;
\r
2037 FLAG_N = NFLAG_32(res);
\r
2039 FLAG_V = VFLAG_CLEAR;
\r
2043 if(GET_MSB_32(src))
\r
2045 *r_dst = 0xffffffff;
\r
2046 FLAG_C = CFLAG_SET;
\r
2047 FLAG_X = XFLAG_SET;
\r
2048 FLAG_N = NFLAG_SET;
\r
2049 FLAG_Z = ZFLAG_CLEAR;
\r
2050 FLAG_V = VFLAG_CLEAR;
\r
2055 FLAG_C = CFLAG_CLEAR;
\r
2056 FLAG_X = XFLAG_CLEAR;
\r
2057 FLAG_N = NFLAG_CLEAR;
\r
2058 FLAG_Z = ZFLAG_SET;
\r
2059 FLAG_V = VFLAG_CLEAR;
\r
2063 FLAG_C = CFLAG_CLEAR;
\r
2064 FLAG_N = NFLAG_32(src);
\r
2066 FLAG_V = VFLAG_CLEAR;
\r
2070 M68KMAKE_OP(asr, 16, ., .)
\r
2072 uint ea = M68KMAKE_GET_EA_AY_16;
\r
2073 uint src = m68ki_read_16(ea);
\r
2074 uint res = src >> 1;
\r
2076 if(GET_MSB_16(src))
\r
2079 m68ki_write_16(ea, res);
\r
2081 FLAG_N = NFLAG_16(res);
\r
2083 FLAG_V = VFLAG_CLEAR;
\r
2084 FLAG_C = FLAG_X = src << 8;
\r
2088 M68KMAKE_OP(asl, 8, s, .)
\r
2090 uint* r_dst = &DY;
\r
2091 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
\r
2092 uint src = MASK_OUT_ABOVE_8(*r_dst);
\r
2093 uint res = MASK_OUT_ABOVE_8(src << shift);
\r
2096 USE_CYCLES(shift<<CYC_SHIFT);
\r
2098 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
\r
2100 FLAG_X = FLAG_C = src << shift;
\r
2101 FLAG_N = NFLAG_8(res);
\r
2103 src &= m68ki_shift_8_table[shift + 1];
\r
2104 FLAG_V = (!(src == 0 || (src == m68ki_shift_8_table[shift + 1] && shift < 8)))<<7;
\r
2108 M68KMAKE_OP(asl, 16, s, .)
\r
2110 uint* r_dst = &DY;
\r
2111 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
\r
2112 uint src = MASK_OUT_ABOVE_16(*r_dst);
\r
2113 uint res = MASK_OUT_ABOVE_16(src << shift);
\r
2116 USE_CYCLES(shift<<CYC_SHIFT);
\r
2118 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
\r
2120 FLAG_N = NFLAG_16(res);
\r
2122 FLAG_X = FLAG_C = src >> (8-shift);
\r
2123 src &= m68ki_shift_16_table[shift + 1];
\r
2124 FLAG_V = (!(src == 0 || src == m68ki_shift_16_table[shift + 1]))<<7;
\r
2128 M68KMAKE_OP(asl, 32, s, .)
\r
2130 uint* r_dst = &DY;
\r
2131 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
\r
2132 uint src = *r_dst;
\r
2133 uint res = MASK_OUT_ABOVE_32(src << shift);
\r
2136 USE_CYCLES(shift<<CYC_SHIFT);
\r
2140 FLAG_N = NFLAG_32(res);
\r
2142 FLAG_X = FLAG_C = src >> (24-shift);
\r
2143 src &= m68ki_shift_32_table[shift + 1];
\r
2144 FLAG_V = (!(src == 0 || src == m68ki_shift_32_table[shift + 1]))<<7;
\r
2148 M68KMAKE_OP(asl, 8, r, .)
\r
2150 uint* r_dst = &DY;
\r
2151 uint shift = DX & 0x3f;
\r
2152 uint src = MASK_OUT_ABOVE_8(*r_dst);
\r
2153 uint res = MASK_OUT_ABOVE_8(src << shift);
\r
2157 USE_CYCLES(shift<<CYC_SHIFT);
\r
2161 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
\r
2162 FLAG_X = FLAG_C = src << shift;
\r
2163 FLAG_N = NFLAG_8(res);
\r
2165 src &= m68ki_shift_8_table[shift + 1];
\r
2166 FLAG_V = (!(src == 0 || src == m68ki_shift_8_table[shift + 1]))<<7;
\r
2170 *r_dst &= 0xffffff00;
\r
2171 FLAG_X = FLAG_C = ((shift == 8 ? src & 1 : 0))<<8;
\r
2172 FLAG_N = NFLAG_CLEAR;
\r
2173 FLAG_Z = ZFLAG_SET;
\r
2174 FLAG_V = (!(src == 0))<<7;
\r
2178 FLAG_C = CFLAG_CLEAR;
\r
2179 FLAG_N = NFLAG_8(src);
\r
2181 FLAG_V = VFLAG_CLEAR;
\r
2185 M68KMAKE_OP(asl, 16, r, .)
\r
2187 uint* r_dst = &DY;
\r
2188 uint shift = DX & 0x3f;
\r
2189 uint src = MASK_OUT_ABOVE_16(*r_dst);
\r
2190 uint res = MASK_OUT_ABOVE_16(src << shift);
\r
2194 USE_CYCLES(shift<<CYC_SHIFT);
\r
2198 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
\r
2199 FLAG_X = FLAG_C = (src << shift) >> 8;
\r
2200 FLAG_N = NFLAG_16(res);
\r
2202 src &= m68ki_shift_16_table[shift + 1];
\r
2203 FLAG_V = (!(src == 0 || src == m68ki_shift_16_table[shift + 1]))<<7;
\r
2207 *r_dst &= 0xffff0000;
\r
2208 FLAG_X = FLAG_C = ((shift == 16 ? src & 1 : 0))<<8;
\r
2209 FLAG_N = NFLAG_CLEAR;
\r
2210 FLAG_Z = ZFLAG_SET;
\r
2211 FLAG_V = (!(src == 0))<<7;
\r
2215 FLAG_C = CFLAG_CLEAR;
\r
2216 FLAG_N = NFLAG_16(src);
\r
2218 FLAG_V = VFLAG_CLEAR;
\r
2222 M68KMAKE_OP(asl, 32, r, .)
\r
2224 uint* r_dst = &DY;
\r
2225 uint shift = DX & 0x3f;
\r
2226 uint src = *r_dst;
\r
2227 uint res = MASK_OUT_ABOVE_32(src << shift);
\r
2231 USE_CYCLES(shift<<CYC_SHIFT);
\r
2236 FLAG_X = FLAG_C = (src >> (32 - shift)) << 8;
\r
2237 FLAG_N = NFLAG_32(res);
\r
2239 src &= m68ki_shift_32_table[shift + 1];
\r
2240 FLAG_V = (!(src == 0 || src == m68ki_shift_32_table[shift + 1]))<<7;
\r
2245 FLAG_X = FLAG_C = ((shift == 32 ? src & 1 : 0))<<8;
\r
2246 FLAG_N = NFLAG_CLEAR;
\r
2247 FLAG_Z = ZFLAG_SET;
\r
2248 FLAG_V = (!(src == 0))<<7;
\r
2252 FLAG_C = CFLAG_CLEAR;
\r
2253 FLAG_N = NFLAG_32(src);
\r
2255 FLAG_V = VFLAG_CLEAR;
\r
2259 M68KMAKE_OP(asl, 16, ., .)
\r
2261 uint ea = M68KMAKE_GET_EA_AY_16;
\r
2262 uint src = m68ki_read_16(ea);
\r
2263 uint res = MASK_OUT_ABOVE_16(src << 1);
\r
2265 m68ki_write_16(ea, res);
\r
2267 FLAG_N = NFLAG_16(res);
\r
2269 FLAG_X = FLAG_C = src >> 7;
\r
2271 FLAG_V = (!(src == 0 || src == 0xc000))<<7;
\r
2275 M68KMAKE_OP(bcc, 8, ., .)
\r
2279 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
2280 m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));
\r
2283 USE_CYCLES(CYC_BCC_NOTAKE_B);
\r
2287 M68KMAKE_OP(bcc, 16, ., .)
\r
2291 uint offset = OPER_I_16();
\r
2293 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
2294 m68ki_branch_16(offset);
\r
2298 USE_CYCLES(CYC_BCC_NOTAKE_W);
\r
2302 M68KMAKE_OP(bcc, 32, ., .)
\r
2304 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
2308 uint offset = OPER_I_32();
\r
2310 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
2311 m68ki_branch_32(offset);
\r
2321 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
2322 m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));
\r
2325 USE_CYCLES(CYC_BCC_NOTAKE_B);
\r
2330 M68KMAKE_OP(bchg, 32, r, d)
\r
2332 uint* r_dst = &DY;
\r
2333 uint mask = 1 << (DX & 0x1f);
\r
2335 FLAG_Z = *r_dst & mask;
\r
2340 M68KMAKE_OP(bchg, 8, r, .)
\r
2342 uint ea = M68KMAKE_GET_EA_AY_8;
\r
2343 uint src = m68ki_read_8(ea);
\r
2344 uint mask = 1 << (DX & 7);
\r
2346 FLAG_Z = src & mask;
\r
2347 m68ki_write_8(ea, src ^ mask);
\r
2351 M68KMAKE_OP(bchg, 32, s, d)
\r
2353 uint* r_dst = &DY;
\r
2354 uint mask = 1 << (OPER_I_8() & 0x1f);
\r
2356 FLAG_Z = *r_dst & mask;
\r
2361 M68KMAKE_OP(bchg, 8, s, .)
\r
2363 uint mask = 1 << (OPER_I_8() & 7);
\r
2364 uint ea = M68KMAKE_GET_EA_AY_8;
\r
2365 uint src = m68ki_read_8(ea);
\r
2367 FLAG_Z = src & mask;
\r
2368 m68ki_write_8(ea, src ^ mask);
\r
2372 M68KMAKE_OP(bclr, 32, r, d)
\r
2374 uint* r_dst = &DY;
\r
2375 uint mask = 1 << (DX & 0x1f);
\r
2377 FLAG_Z = *r_dst & mask;
\r
2382 M68KMAKE_OP(bclr, 8, r, .)
\r
2384 uint ea = M68KMAKE_GET_EA_AY_8;
\r
2385 uint src = m68ki_read_8(ea);
\r
2386 uint mask = 1 << (DX & 7);
\r
2388 FLAG_Z = src & mask;
\r
2389 m68ki_write_8(ea, src & ~mask);
\r
2393 M68KMAKE_OP(bclr, 32, s, d)
\r
2395 uint* r_dst = &DY;
\r
2396 uint mask = 1 << (OPER_I_8() & 0x1f);
\r
2398 FLAG_Z = *r_dst & mask;
\r
2403 M68KMAKE_OP(bclr, 8, s, .)
\r
2405 uint mask = 1 << (OPER_I_8() & 7);
\r
2406 uint ea = M68KMAKE_GET_EA_AY_8;
\r
2407 uint src = m68ki_read_8(ea);
\r
2409 FLAG_Z = src & mask;
\r
2410 m68ki_write_8(ea, src & ~mask);
\r
2414 M68KMAKE_OP(bfchg, 32, ., d)
\r
2416 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
2418 uint word2 = OPER_I_16();
\r
2419 uint offset = (word2>>6)&31;
\r
2420 uint width = word2;
\r
2426 offset = REG_D[offset&7];
\r
2428 width = REG_D[width&7];
\r
2431 width = ((width-1) & 31) + 1;
\r
2433 mask = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
\r
2434 mask = ROR_32(mask, offset);
\r
2436 FLAG_N = NFLAG_32(*data<<offset);
\r
2437 FLAG_Z = *data & mask;
\r
2438 FLAG_V = VFLAG_CLEAR;
\r
2439 FLAG_C = CFLAG_CLEAR;
\r
2445 m68ki_exception_illegal();
\r
2449 M68KMAKE_OP(bfchg, 32, ., .)
\r
2451 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
2453 uint word2 = OPER_I_16();
\r
2454 sint offset = (word2>>6)&31;
\r
2455 uint width = word2;
\r
2459 uint data_byte = 0;
\r
2460 uint mask_byte = 0;
\r
2461 uint ea = M68KMAKE_GET_EA_AY_8;
\r
2465 offset = MAKE_INT_32(REG_D[offset&7]);
\r
2467 width = REG_D[width&7];
\r
2469 /* Offset is signed so we have to use ugly math =( */
\r
2477 width = ((width-1) & 31) + 1;
\r
2479 mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
\r
2480 mask_long = mask_base >> offset;
\r
2482 data_long = m68ki_read_32(ea);
\r
2483 FLAG_N = NFLAG_32(data_long << offset);
\r
2484 FLAG_Z = data_long & mask_long;
\r
2485 FLAG_V = VFLAG_CLEAR;
\r
2486 FLAG_C = CFLAG_CLEAR;
\r
2488 m68ki_write_32(ea, data_long ^ mask_long);
\r
2490 if((width + offset) > 32)
\r
2492 mask_byte = MASK_OUT_ABOVE_8(mask_base);
\r
2493 data_byte = m68ki_read_8(ea+4);
\r
2494 FLAG_Z |= (data_byte & mask_byte);
\r
2495 m68ki_write_8(ea+4, data_byte ^ mask_byte);
\r
2499 m68ki_exception_illegal();
\r
2503 M68KMAKE_OP(bfclr, 32, ., d)
\r
2505 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
2507 uint word2 = OPER_I_16();
\r
2508 uint offset = (word2>>6)&31;
\r
2509 uint width = word2;
\r
2515 offset = REG_D[offset&7];
\r
2517 width = REG_D[width&7];
\r
2521 width = ((width-1) & 31) + 1;
\r
2524 mask = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
\r
2525 mask = ROR_32(mask, offset);
\r
2527 FLAG_N = NFLAG_32(*data<<offset);
\r
2528 FLAG_Z = *data & mask;
\r
2529 FLAG_V = VFLAG_CLEAR;
\r
2530 FLAG_C = CFLAG_CLEAR;
\r
2536 m68ki_exception_illegal();
\r
2540 M68KMAKE_OP(bfclr, 32, ., .)
\r
2542 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
2544 uint word2 = OPER_I_16();
\r
2545 sint offset = (word2>>6)&31;
\r
2546 uint width = word2;
\r
2550 uint data_byte = 0;
\r
2551 uint mask_byte = 0;
\r
2552 uint ea = M68KMAKE_GET_EA_AY_8;
\r
2556 offset = MAKE_INT_32(REG_D[offset&7]);
\r
2558 width = REG_D[width&7];
\r
2560 /* Offset is signed so we have to use ugly math =( */
\r
2568 width = ((width-1) & 31) + 1;
\r
2570 mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
\r
2571 mask_long = mask_base >> offset;
\r
2573 data_long = m68ki_read_32(ea);
\r
2574 FLAG_N = NFLAG_32(data_long << offset);
\r
2575 FLAG_Z = data_long & mask_long;
\r
2576 FLAG_V = VFLAG_CLEAR;
\r
2577 FLAG_C = CFLAG_CLEAR;
\r
2579 m68ki_write_32(ea, data_long & ~mask_long);
\r
2581 if((width + offset) > 32)
\r
2583 mask_byte = MASK_OUT_ABOVE_8(mask_base);
\r
2584 data_byte = m68ki_read_8(ea+4);
\r
2585 FLAG_Z |= (data_byte & mask_byte);
\r
2586 m68ki_write_8(ea+4, data_byte & ~mask_byte);
\r
2590 m68ki_exception_illegal();
\r
2594 M68KMAKE_OP(bfexts, 32, ., d)
\r
2596 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
2598 uint word2 = OPER_I_16();
\r
2599 uint offset = (word2>>6)&31;
\r
2600 uint width = word2;
\r
2605 offset = REG_D[offset&7];
\r
2607 width = REG_D[width&7];
\r
2610 width = ((width-1) & 31) + 1;
\r
2612 data = ROL_32(data, offset);
\r
2613 FLAG_N = NFLAG_32(data);
\r
2614 data = MAKE_INT_32(data) >> (32 - width);
\r
2617 FLAG_V = VFLAG_CLEAR;
\r
2618 FLAG_C = CFLAG_CLEAR;
\r
2620 REG_D[(word2>>12)&7] = data;
\r
2624 m68ki_exception_illegal();
\r
2628 M68KMAKE_OP(bfexts, 32, ., .)
\r
2630 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
2632 uint word2 = OPER_I_16();
\r
2633 sint offset = (word2>>6)&31;
\r
2634 uint width = word2;
\r
2636 uint ea = M68KMAKE_GET_EA_AY_8;
\r
2640 offset = MAKE_INT_32(REG_D[offset&7]);
\r
2642 width = REG_D[width&7];
\r
2644 /* Offset is signed so we have to use ugly math =( */
\r
2652 width = ((width-1) & 31) + 1;
\r
2654 data = m68ki_read_32(ea);
\r
2656 data = MASK_OUT_ABOVE_32(data<<offset);
\r
2658 if((offset+width) > 32)
\r
2659 data |= (m68ki_read_8(ea+4) << offset) >> 8;
\r
2661 FLAG_N = NFLAG_32(data);
\r
2662 data = MAKE_INT_32(data) >> (32 - width);
\r
2665 FLAG_V = VFLAG_CLEAR;
\r
2666 FLAG_C = CFLAG_CLEAR;
\r
2668 REG_D[(word2 >> 12) & 7] = data;
\r
2672 m68ki_exception_illegal();
\r
2676 M68KMAKE_OP(bfextu, 32, ., d)
\r
2678 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
2680 uint word2 = OPER_I_16();
\r
2681 uint offset = (word2>>6)&31;
\r
2682 uint width = word2;
\r
2687 offset = REG_D[offset&7];
\r
2689 width = REG_D[width&7];
\r
2692 width = ((width-1) & 31) + 1;
\r
2694 data = ROL_32(data, offset);
\r
2695 FLAG_N = NFLAG_32(data);
\r
2696 data >>= 32 - width;
\r
2699 FLAG_V = VFLAG_CLEAR;
\r
2700 FLAG_C = CFLAG_CLEAR;
\r
2702 REG_D[(word2>>12)&7] = data;
\r
2706 m68ki_exception_illegal();
\r
2710 M68KMAKE_OP(bfextu, 32, ., .)
\r
2712 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
2714 uint word2 = OPER_I_16();
\r
2715 sint offset = (word2>>6)&31;
\r
2716 uint width = word2;
\r
2718 uint ea = M68KMAKE_GET_EA_AY_8;
\r
2722 offset = MAKE_INT_32(REG_D[offset&7]);
\r
2724 width = REG_D[width&7];
\r
2726 /* Offset is signed so we have to use ugly math =( */
\r
2734 width = ((width-1) & 31) + 1;
\r
2736 data = m68ki_read_32(ea);
\r
2737 data = MASK_OUT_ABOVE_32(data<<offset);
\r
2739 if((offset+width) > 32)
\r
2740 data |= (m68ki_read_8(ea+4) << offset) >> 8;
\r
2742 FLAG_N = NFLAG_32(data);
\r
2743 data >>= (32 - width);
\r
2746 FLAG_V = VFLAG_CLEAR;
\r
2747 FLAG_C = CFLAG_CLEAR;
\r
2749 REG_D[(word2 >> 12) & 7] = data;
\r
2753 m68ki_exception_illegal();
\r
2757 M68KMAKE_OP(bfffo, 32, ., d)
\r
2759 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
2761 uint word2 = OPER_I_16();
\r
2762 uint offset = (word2>>6)&31;
\r
2763 uint width = word2;
\r
2769 offset = REG_D[offset&7];
\r
2771 width = REG_D[width&7];
\r
2774 width = ((width-1) & 31) + 1;
\r
2776 data = ROL_32(data, offset);
\r
2777 FLAG_N = NFLAG_32(data);
\r
2778 data >>= 32 - width;
\r
2781 FLAG_V = VFLAG_CLEAR;
\r
2782 FLAG_C = CFLAG_CLEAR;
\r
2784 for(bit = 1<<(width-1);bit && !(data & bit);bit>>= 1)
\r
2787 REG_D[(word2>>12)&7] = offset;
\r
2791 m68ki_exception_illegal();
\r
2795 M68KMAKE_OP(bfffo, 32, ., .)
\r
2797 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
2799 uint word2 = OPER_I_16();
\r
2800 sint offset = (word2>>6)&31;
\r
2801 sint local_offset;
\r
2802 uint width = word2;
\r
2805 uint ea = M68KMAKE_GET_EA_AY_8;
\r
2809 offset = MAKE_INT_32(REG_D[offset&7]);
\r
2811 width = REG_D[width&7];
\r
2813 /* Offset is signed so we have to use ugly math =( */
\r
2815 local_offset = offset % 8;
\r
2816 if(local_offset < 0)
\r
2818 local_offset += 8;
\r
2821 width = ((width-1) & 31) + 1;
\r
2823 data = m68ki_read_32(ea);
\r
2824 data = MASK_OUT_ABOVE_32(data<<local_offset);
\r
2826 if((local_offset+width) > 32)
\r
2827 data |= (m68ki_read_8(ea+4) << local_offset) >> 8;
\r
2829 FLAG_N = NFLAG_32(data);
\r
2830 data >>= (32 - width);
\r
2833 FLAG_V = VFLAG_CLEAR;
\r
2834 FLAG_C = CFLAG_CLEAR;
\r
2836 for(bit = 1<<(width-1);bit && !(data & bit);bit>>= 1)
\r
2839 REG_D[(word2>>12)&7] = offset;
\r
2843 m68ki_exception_illegal();
\r
2847 M68KMAKE_OP(bfins, 32, ., d)
\r
2849 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
2851 uint word2 = OPER_I_16();
\r
2852 uint offset = (word2>>6)&31;
\r
2853 uint width = word2;
\r
2856 uint64 insert = REG_D[(word2>>12)&7];
\r
2860 offset = REG_D[offset&7];
\r
2862 width = REG_D[width&7];
\r
2866 width = ((width-1) & 31) + 1;
\r
2869 mask = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
\r
2870 mask = ROR_32(mask, offset);
\r
2872 insert = MASK_OUT_ABOVE_32(insert << (32 - width));
\r
2873 FLAG_N = NFLAG_32(insert);
\r
2875 insert = ROR_32(insert, offset);
\r
2877 FLAG_V = VFLAG_CLEAR;
\r
2878 FLAG_C = CFLAG_CLEAR;
\r
2885 m68ki_exception_illegal();
\r
2889 M68KMAKE_OP(bfins, 32, ., .)
\r
2891 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
2893 uint word2 = OPER_I_16();
\r
2894 sint offset = (word2>>6)&31;
\r
2895 uint width = word2;
\r
2896 uint insert_base = REG_D[(word2>>12)&7];
\r
2902 uint data_byte = 0;
\r
2903 uint mask_byte = 0;
\r
2904 uint ea = M68KMAKE_GET_EA_AY_8;
\r
2908 offset = MAKE_INT_32(REG_D[offset&7]);
\r
2910 width = REG_D[width&7];
\r
2912 /* Offset is signed so we have to use ugly math =( */
\r
2920 width = ((width-1) & 31) + 1;
\r
2922 mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
\r
2923 mask_long = mask_base >> offset;
\r
2925 insert_base = MASK_OUT_ABOVE_32(insert_base << (32 - width));
\r
2926 FLAG_N = NFLAG_32(insert_base);
\r
2927 FLAG_Z = insert_base;
\r
2928 insert_long = insert_base >> offset;
\r
2930 data_long = m68ki_read_32(ea);
\r
2931 FLAG_V = VFLAG_CLEAR;
\r
2932 FLAG_C = CFLAG_CLEAR;
\r
2934 m68ki_write_32(ea, (data_long & ~mask_long) | insert_long);
\r
2936 if((width + offset) > 32)
\r
2938 mask_byte = MASK_OUT_ABOVE_8(mask_base);
\r
2939 insert_byte = MASK_OUT_ABOVE_8(insert_base);
\r
2940 data_byte = m68ki_read_8(ea+4);
\r
2941 FLAG_Z |= (data_byte & mask_byte);
\r
2942 m68ki_write_8(ea+4, (data_byte & ~mask_byte) | insert_byte);
\r
2946 m68ki_exception_illegal();
\r
2950 M68KMAKE_OP(bfset, 32, ., d)
\r
2952 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
2954 uint word2 = OPER_I_16();
\r
2955 uint offset = (word2>>6)&31;
\r
2956 uint width = word2;
\r
2962 offset = REG_D[offset&7];
\r
2964 width = REG_D[width&7];
\r
2968 width = ((width-1) & 31) + 1;
\r
2971 mask = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
\r
2972 mask = ROR_32(mask, offset);
\r
2974 FLAG_N = NFLAG_32(*data<<offset);
\r
2975 FLAG_Z = *data & mask;
\r
2976 FLAG_V = VFLAG_CLEAR;
\r
2977 FLAG_C = CFLAG_CLEAR;
\r
2983 m68ki_exception_illegal();
\r
2987 M68KMAKE_OP(bfset, 32, ., .)
\r
2989 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
2991 uint word2 = OPER_I_16();
\r
2992 sint offset = (word2>>6)&31;
\r
2993 uint width = word2;
\r
2997 uint data_byte = 0;
\r
2998 uint mask_byte = 0;
\r
2999 uint ea = M68KMAKE_GET_EA_AY_8;
\r
3003 offset = MAKE_INT_32(REG_D[offset&7]);
\r
3005 width = REG_D[width&7];
\r
3007 /* Offset is signed so we have to use ugly math =( */
\r
3015 width = ((width-1) & 31) + 1;
\r
3018 mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
\r
3019 mask_long = mask_base >> offset;
\r
3021 data_long = m68ki_read_32(ea);
\r
3022 FLAG_N = NFLAG_32(data_long << offset);
\r
3023 FLAG_Z = data_long & mask_long;
\r
3024 FLAG_V = VFLAG_CLEAR;
\r
3025 FLAG_C = CFLAG_CLEAR;
\r
3027 m68ki_write_32(ea, data_long | mask_long);
\r
3029 if((width + offset) > 32)
\r
3031 mask_byte = MASK_OUT_ABOVE_8(mask_base);
\r
3032 data_byte = m68ki_read_8(ea+4);
\r
3033 FLAG_Z |= (data_byte & mask_byte);
\r
3034 m68ki_write_8(ea+4, data_byte | mask_byte);
\r
3038 m68ki_exception_illegal();
\r
3042 M68KMAKE_OP(bftst, 32, ., d)
\r
3044 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
3046 uint word2 = OPER_I_16();
\r
3047 uint offset = (word2>>6)&31;
\r
3048 uint width = word2;
\r
3054 offset = REG_D[offset&7];
\r
3056 width = REG_D[width&7];
\r
3060 width = ((width-1) & 31) + 1;
\r
3063 mask = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
\r
3064 mask = ROR_32(mask, offset);
\r
3066 FLAG_N = NFLAG_32(*data<<offset);
\r
3067 FLAG_Z = *data & mask;
\r
3068 FLAG_V = VFLAG_CLEAR;
\r
3069 FLAG_C = CFLAG_CLEAR;
\r
3073 m68ki_exception_illegal();
\r
3077 M68KMAKE_OP(bftst, 32, ., .)
\r
3079 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
3081 uint word2 = OPER_I_16();
\r
3082 sint offset = (word2>>6)&31;
\r
3083 uint width = word2;
\r
3087 uint data_byte = 0;
\r
3088 uint mask_byte = 0;
\r
3089 uint ea = M68KMAKE_GET_EA_AY_8;
\r
3092 offset = MAKE_INT_32(REG_D[offset&7]);
\r
3094 width = REG_D[width&7];
\r
3096 /* Offset is signed so we have to use ugly math =( */
\r
3104 width = ((width-1) & 31) + 1;
\r
3107 mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
\r
3108 mask_long = mask_base >> offset;
\r
3110 data_long = m68ki_read_32(ea);
\r
3111 FLAG_N = ((data_long & (0x80000000 >> offset))<<offset)>>24;
\r
3112 FLAG_Z = data_long & mask_long;
\r
3113 FLAG_V = VFLAG_CLEAR;
\r
3114 FLAG_C = CFLAG_CLEAR;
\r
3116 if((width + offset) > 32)
\r
3118 mask_byte = MASK_OUT_ABOVE_8(mask_base);
\r
3119 data_byte = m68ki_read_8(ea+4);
\r
3120 FLAG_Z |= (data_byte & mask_byte);
\r
3124 m68ki_exception_illegal();
\r
3128 M68KMAKE_OP(bkpt, 0, ., .)
\r
3130 if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
\r
3132 m68ki_bkpt_ack(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE) ? REG_IR & 7 : 0); /* auto-disable (see m68kcpu.h) */
\r
3134 m68ki_exception_illegal();
\r
3138 M68KMAKE_OP(bra, 8, ., .)
\r
3140 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
3141 m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));
\r
3142 if(REG_PC == REG_PPC)
\r
3147 M68KMAKE_OP(bra, 16, ., .)
\r
3149 uint offset = OPER_I_16();
\r
3151 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
3152 m68ki_branch_16(offset);
\r
3153 if(REG_PC == REG_PPC)
\r
3158 M68KMAKE_OP(bra, 32, ., .)
\r
3160 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
3162 uint offset = OPER_I_32();
\r
3164 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
3165 m68ki_branch_32(offset);
\r
3166 if(REG_PC == REG_PPC)
\r
3172 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
3173 m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));
\r
3174 if(REG_PC == REG_PPC)
\r
3180 M68KMAKE_OP(bset, 32, r, d)
\r
3182 uint* r_dst = &DY;
\r
3183 uint mask = 1 << (DX & 0x1f);
\r
3185 FLAG_Z = *r_dst & mask;
\r
3190 M68KMAKE_OP(bset, 8, r, .)
\r
3192 uint ea = M68KMAKE_GET_EA_AY_8;
\r
3193 uint src = m68ki_read_8(ea);
\r
3194 uint mask = 1 << (DX & 7);
\r
3196 FLAG_Z = src & mask;
\r
3197 m68ki_write_8(ea, src | mask);
\r
3201 M68KMAKE_OP(bset, 32, s, d)
\r
3203 uint* r_dst = &DY;
\r
3204 uint mask = 1 << (OPER_I_8() & 0x1f);
\r
3206 FLAG_Z = *r_dst & mask;
\r
3211 M68KMAKE_OP(bset, 8, s, .)
\r
3213 uint mask = 1 << (OPER_I_8() & 7);
\r
3214 uint ea = M68KMAKE_GET_EA_AY_8;
\r
3215 uint src = m68ki_read_8(ea);
\r
3217 FLAG_Z = src & mask;
\r
3218 m68ki_write_8(ea, src | mask);
\r
3222 M68KMAKE_OP(bsr, 8, ., .)
\r
3224 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
3225 m68ki_push_32(REG_PC);
\r
3226 m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));
\r
3230 M68KMAKE_OP(bsr, 16, ., .)
\r
3232 uint offset = OPER_I_16();
\r
3233 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
3234 m68ki_push_32(REG_PC);
\r
3236 m68ki_branch_16(offset);
\r
3240 M68KMAKE_OP(bsr, 32, ., .)
\r
3242 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
3244 uint offset = OPER_I_32();
\r
3245 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
3246 m68ki_push_32(REG_PC);
\r
3248 m68ki_branch_32(offset);
\r
3253 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
3254 m68ki_push_32(REG_PC);
\r
3255 m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));
\r
3260 M68KMAKE_OP(btst, 32, r, d)
\r
3262 FLAG_Z = DY & (1 << (DX & 0x1f));
\r
3266 M68KMAKE_OP(btst, 8, r, .)
\r
3268 FLAG_Z = M68KMAKE_GET_OPER_AY_8 & (1 << (DX & 7));
\r
3272 M68KMAKE_OP(btst, 32, s, d)
\r
3274 FLAG_Z = DY & (1 << (OPER_I_8() & 0x1f));
\r
3278 M68KMAKE_OP(btst, 8, s, .)
\r
3280 uint bit = OPER_I_8() & 7;
\r
3282 FLAG_Z = M68KMAKE_GET_OPER_AY_8 & (1 << bit);
\r
3286 M68KMAKE_OP(callm, 32, ., .)
\r
3288 /* note: watch out for pcrelative modes */
\r
3289 if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
\r
3291 uint ea = M68KMAKE_GET_EA_AY_32;
\r
3293 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
3295 (void)ea; /* just to avoid an 'unused variable' warning */
\r
3296 M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n",
\r
3297 m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR,
\r
3298 m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2))));
\r
3301 m68ki_exception_illegal();
\r
3305 M68KMAKE_OP(cas, 8, ., .)
\r
3307 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
3309 uint word2 = OPER_I_16();
\r
3310 uint ea = M68KMAKE_GET_EA_AY_8;
\r
3311 uint dest = m68ki_read_8(ea);
\r
3312 uint* compare = ®_D[word2 & 7];
\r
3313 uint res = dest - MASK_OUT_ABOVE_8(*compare);
\r
3315 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
3316 FLAG_N = NFLAG_8(res);
\r
3317 FLAG_Z = MASK_OUT_ABOVE_8(res);
\r
3318 FLAG_V = VFLAG_SUB_8(*compare, dest, res);
\r
3319 FLAG_C = CFLAG_8(res);
\r
3322 *compare = MASK_OUT_BELOW_8(*compare) | dest;
\r
3326 m68ki_write_8(ea, MASK_OUT_ABOVE_8(REG_D[(word2 >> 6) & 7]));
\r
3330 m68ki_exception_illegal();
\r
3334 M68KMAKE_OP(cas, 16, ., .)
\r
3336 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
3338 uint word2 = OPER_I_16();
\r
3339 uint ea = M68KMAKE_GET_EA_AY_16;
\r
3340 uint dest = m68ki_read_16(ea);
\r
3341 uint* compare = ®_D[word2 & 7];
\r
3342 uint res = dest - MASK_OUT_ABOVE_16(*compare);
\r
3344 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
3345 FLAG_N = NFLAG_16(res);
\r
3346 FLAG_Z = MASK_OUT_ABOVE_16(res);
\r
3347 FLAG_V = VFLAG_SUB_16(*compare, dest, res);
\r
3348 FLAG_C = CFLAG_16(res);
\r
3351 *compare = MASK_OUT_BELOW_16(*compare) | dest;
\r
3355 m68ki_write_16(ea, MASK_OUT_ABOVE_16(REG_D[(word2 >> 6) & 7]));
\r
3359 m68ki_exception_illegal();
\r
3363 M68KMAKE_OP(cas, 32, ., .)
\r
3365 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
3367 uint word2 = OPER_I_16();
\r
3368 uint ea = M68KMAKE_GET_EA_AY_32;
\r
3369 uint dest = m68ki_read_32(ea);
\r
3370 uint* compare = ®_D[word2 & 7];
\r
3371 uint res = dest - *compare;
\r
3373 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
3374 FLAG_N = NFLAG_32(res);
\r
3375 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
3376 FLAG_V = VFLAG_SUB_32(*compare, dest, res);
\r
3377 FLAG_C = CFLAG_SUB_32(*compare, dest, res);
\r
3384 m68ki_write_32(ea, REG_D[(word2 >> 6) & 7]);
\r
3388 m68ki_exception_illegal();
\r
3392 M68KMAKE_OP(cas2, 16, ., .)
\r
3394 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
3396 uint word2 = OPER_I_32();
\r
3397 uint* compare1 = ®_D[(word2 >> 16) & 7];
\r
3398 uint ea1 = REG_DA[(word2 >> 28) & 15];
\r
3399 uint dest1 = m68ki_read_16(ea1);
\r
3400 uint res1 = dest1 - MASK_OUT_ABOVE_16(*compare1);
\r
3401 uint* compare2 = ®_D[word2 & 7];
\r
3402 uint ea2 = REG_DA[(word2 >> 12) & 15];
\r
3403 uint dest2 = m68ki_read_16(ea2);
\r
3406 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
3407 FLAG_N = NFLAG_16(res1);
\r
3408 FLAG_Z = MASK_OUT_ABOVE_16(res1);
\r
3409 FLAG_V = VFLAG_SUB_16(*compare1, dest1, res1);
\r
3410 FLAG_C = CFLAG_16(res1);
\r
3414 res2 = dest2 - MASK_OUT_ABOVE_16(*compare2);
\r
3416 FLAG_N = NFLAG_16(res2);
\r
3417 FLAG_Z = MASK_OUT_ABOVE_16(res2);
\r
3418 FLAG_V = VFLAG_SUB_16(*compare2, dest2, res2);
\r
3419 FLAG_C = CFLAG_16(res2);
\r
3424 m68ki_write_16(ea1, REG_D[(word2 >> 22) & 7]);
\r
3425 m68ki_write_16(ea2, REG_D[(word2 >> 6) & 7]);
\r
3429 *compare1 = BIT_1F(word2) ? MAKE_INT_16(dest1) : MASK_OUT_BELOW_16(*compare1) | dest1;
\r
3430 *compare2 = BIT_F(word2) ? MAKE_INT_16(dest2) : MASK_OUT_BELOW_16(*compare2) | dest2;
\r
3433 m68ki_exception_illegal();
\r
3437 M68KMAKE_OP(cas2, 32, ., .)
\r
3439 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
3441 uint word2 = OPER_I_32();
\r
3442 uint* compare1 = ®_D[(word2 >> 16) & 7];
\r
3443 uint ea1 = REG_DA[(word2 >> 28) & 15];
\r
3444 uint dest1 = m68ki_read_32(ea1);
\r
3445 uint res1 = dest1 - *compare1;
\r
3446 uint* compare2 = ®_D[word2 & 7];
\r
3447 uint ea2 = REG_DA[(word2 >> 12) & 15];
\r
3448 uint dest2 = m68ki_read_32(ea2);
\r
3451 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
3452 FLAG_N = NFLAG_32(res1);
\r
3453 FLAG_Z = MASK_OUT_ABOVE_32(res1);
\r
3454 FLAG_V = VFLAG_SUB_32(*compare1, dest1, res1);
\r
3455 FLAG_C = CFLAG_SUB_32(*compare1, dest1, res1);
\r
3459 res2 = dest2 - *compare2;
\r
3461 FLAG_N = NFLAG_32(res2);
\r
3462 FLAG_Z = MASK_OUT_ABOVE_32(res2);
\r
3463 FLAG_V = VFLAG_SUB_32(*compare2, dest2, res2);
\r
3464 FLAG_C = CFLAG_SUB_32(*compare2, dest2, res2);
\r
3469 m68ki_write_32(ea1, REG_D[(word2 >> 22) & 7]);
\r
3470 m68ki_write_32(ea2, REG_D[(word2 >> 6) & 7]);
\r
3474 *compare1 = dest1;
\r
3475 *compare2 = dest2;
\r
3478 m68ki_exception_illegal();
\r
3482 M68KMAKE_OP(chk, 16, ., d)
\r
3484 sint src = MAKE_INT_16(DX);
\r
3485 sint bound = MAKE_INT_16(DY);
\r
3487 FLAG_Z = ZFLAG_16(src); /* Undocumented */
\r
3488 FLAG_V = VFLAG_CLEAR; /* Undocumented */
\r
3489 FLAG_C = CFLAG_CLEAR; /* Undocumented */
\r
3491 if(src >= 0 && src <= bound)
\r
3495 FLAG_N = (src < 0)<<7;
\r
3496 m68ki_exception_trap(EXCEPTION_CHK);
\r
3500 M68KMAKE_OP(chk, 16, ., .)
\r
3502 sint src = MAKE_INT_16(DX);
\r
3503 sint bound = MAKE_INT_16(M68KMAKE_GET_OPER_AY_16);
\r
3505 FLAG_Z = ZFLAG_16(src); /* Undocumented */
\r
3506 FLAG_V = VFLAG_CLEAR; /* Undocumented */
\r
3507 FLAG_C = CFLAG_CLEAR; /* Undocumented */
\r
3509 if(src >= 0 && src <= bound)
\r
3513 FLAG_N = (src < 0)<<7;
\r
3514 m68ki_exception_trap(EXCEPTION_CHK);
\r
3518 M68KMAKE_OP(chk, 32, ., d)
\r
3520 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
3522 sint src = MAKE_INT_32(DX);
\r
3523 sint bound = MAKE_INT_32(DY);
\r
3525 FLAG_Z = ZFLAG_32(src); /* Undocumented */
\r
3526 FLAG_V = VFLAG_CLEAR; /* Undocumented */
\r
3527 FLAG_C = CFLAG_CLEAR; /* Undocumented */
\r
3529 if(src >= 0 && src <= bound)
\r
3533 FLAG_N = (src < 0)<<7;
\r
3534 m68ki_exception_trap(EXCEPTION_CHK);
\r
3537 m68ki_exception_illegal();
\r
3541 M68KMAKE_OP(chk, 32, ., .)
\r
3543 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
3545 sint src = MAKE_INT_32(DX);
\r
3546 sint bound = MAKE_INT_32(M68KMAKE_GET_OPER_AY_32);
\r
3548 FLAG_Z = ZFLAG_32(src); /* Undocumented */
\r
3549 FLAG_V = VFLAG_CLEAR; /* Undocumented */
\r
3550 FLAG_C = CFLAG_CLEAR; /* Undocumented */
\r
3552 if(src >= 0 && src <= bound)
\r
3556 FLAG_N = (src < 0)<<7;
\r
3557 m68ki_exception_trap(EXCEPTION_CHK);
\r
3560 m68ki_exception_illegal();
\r
3564 M68KMAKE_OP(chk2cmp2, 8, ., pcdi)
\r
3566 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
3568 uint word2 = OPER_I_16();
\r
3569 uint compare = REG_DA[(word2 >> 12) & 15]&0xff;
\r
3570 uint ea = EA_PCDI_8();
\r
3571 uint lower_bound = m68ki_read_pcrel_8(ea);
\r
3572 uint upper_bound = m68ki_read_pcrel_8(ea + 1);
\r
3575 FLAG_C = MAKE_INT_8(compare) - MAKE_INT_8(lower_bound);
\r
3577 FLAG_C = compare - lower_bound;
\r
3578 FLAG_Z = !((upper_bound==compare) | (lower_bound==compare));
\r
3582 m68ki_exception_trap(EXCEPTION_CHK);
\r
3586 FLAG_C = upper_bound - compare;
\r
3587 if(COND_CS() && BIT_B(word2))
\r
3588 m68ki_exception_trap(EXCEPTION_CHK);
\r
3591 m68ki_exception_illegal();
\r
3595 M68KMAKE_OP(chk2cmp2, 8, ., pcix)
\r
3597 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
3599 uint word2 = OPER_I_16();
\r
3600 uint compare = REG_DA[(word2 >> 12) & 15]&0xff;
\r
3601 uint ea = EA_PCIX_8();
\r
3602 uint lower_bound = m68ki_read_pcrel_8(ea);
\r
3603 uint upper_bound = m68ki_read_pcrel_8(ea + 1);
\r
3606 FLAG_C = MAKE_INT_8(compare) - MAKE_INT_8(lower_bound);
\r
3608 FLAG_C = compare - lower_bound;
\r
3609 FLAG_Z = !((upper_bound==compare) | (lower_bound==compare));
\r
3613 m68ki_exception_trap(EXCEPTION_CHK);
\r
3617 FLAG_C = upper_bound - compare;
\r
3618 if(COND_CS() && BIT_B(word2))
\r
3619 m68ki_exception_trap(EXCEPTION_CHK);
\r
3622 m68ki_exception_illegal();
\r
3626 M68KMAKE_OP(chk2cmp2, 8, ., .)
\r
3628 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
3630 uint word2 = OPER_I_16();
\r
3631 uint compare = REG_DA[(word2 >> 12) & 15]&0xff;
\r
3632 uint ea = M68KMAKE_GET_EA_AY_8;
\r
3633 uint lower_bound = m68ki_read_8(ea);
\r
3634 uint upper_bound = m68ki_read_8(ea + 1);
\r
3637 FLAG_C = MAKE_INT_8(compare) - MAKE_INT_8(lower_bound);
\r
3639 FLAG_C = compare - lower_bound;
\r
3640 FLAG_Z = !((upper_bound==compare) | (lower_bound==compare));
\r
3644 m68ki_exception_trap(EXCEPTION_CHK);
\r
3648 FLAG_C = upper_bound - compare;
\r
3649 if(COND_CS() && BIT_B(word2))
\r
3650 m68ki_exception_trap(EXCEPTION_CHK);
\r
3653 m68ki_exception_illegal();
\r
3657 M68KMAKE_OP(chk2cmp2, 16, ., pcdi)
\r
3659 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
3661 uint word2 = OPER_I_16();
\r
3662 uint compare = REG_DA[(word2 >> 12) & 15]&0xffff;
\r
3663 uint ea = EA_PCDI_16();
\r
3664 uint lower_bound = m68ki_read_pcrel_16(ea);
\r
3665 uint upper_bound = m68ki_read_pcrel_16(ea + 2);
\r
3668 FLAG_C = MAKE_INT_16(compare) - MAKE_INT_16(lower_bound);
\r
3670 FLAG_C = compare - lower_bound;
\r
3671 FLAG_Z = !((upper_bound==compare) | (lower_bound==compare));
\r
3672 FLAG_C = CFLAG_16(FLAG_C);
\r
3676 m68ki_exception_trap(EXCEPTION_CHK);
\r
3681 FLAG_C = MAKE_INT_16(upper_bound) - MAKE_INT_16(compare);
\r
3683 FLAG_C = upper_bound - compare;
\r
3684 FLAG_C = CFLAG_16(FLAG_C);
\r
3685 if(COND_CS() && BIT_B(word2))
\r
3686 m68ki_exception_trap(EXCEPTION_CHK);
\r
3689 m68ki_exception_illegal();
\r
3693 M68KMAKE_OP(chk2cmp2, 16, ., pcix)
\r
3695 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
3697 uint word2 = OPER_I_16();
\r
3698 uint compare = REG_DA[(word2 >> 12) & 15]&0xffff;
\r
3699 uint ea = EA_PCIX_16();
\r
3700 uint lower_bound = m68ki_read_pcrel_16(ea);
\r
3701 uint upper_bound = m68ki_read_pcrel_16(ea + 2);
\r
3704 FLAG_C = MAKE_INT_16(compare) - MAKE_INT_16(lower_bound);
\r
3706 FLAG_C = compare - lower_bound;
\r
3707 FLAG_Z = !((upper_bound==compare) | (lower_bound==compare));
\r
3708 FLAG_C = CFLAG_16(FLAG_C);
\r
3712 m68ki_exception_trap(EXCEPTION_CHK);
\r
3717 FLAG_C = MAKE_INT_16(upper_bound) - MAKE_INT_16(compare);
\r
3719 FLAG_C = upper_bound - compare;
\r
3720 FLAG_C = CFLAG_16(FLAG_C);
\r
3721 if(COND_CS() && BIT_B(word2))
\r
3722 m68ki_exception_trap(EXCEPTION_CHK);
\r
3725 m68ki_exception_illegal();
\r
3729 M68KMAKE_OP(chk2cmp2, 16, ., .)
\r
3731 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
3733 uint word2 = OPER_I_16();
\r
3734 uint compare = REG_DA[(word2 >> 12) & 15]&0xffff;
\r
3735 uint ea = M68KMAKE_GET_EA_AY_16;
\r
3736 uint lower_bound = m68ki_read_16(ea);
\r
3737 uint upper_bound = m68ki_read_16(ea + 2);
\r
3740 FLAG_C = MAKE_INT_16(compare) - MAKE_INT_16(lower_bound);
\r
3742 FLAG_C = compare - lower_bound;
\r
3744 FLAG_Z = !((upper_bound==compare) | (lower_bound==compare));
\r
3745 FLAG_C = CFLAG_16(FLAG_C);
\r
3749 m68ki_exception_trap(EXCEPTION_CHK);
\r
3753 FLAG_C = MAKE_INT_16(upper_bound) - MAKE_INT_16(compare);
\r
3755 FLAG_C = upper_bound - compare;
\r
3757 FLAG_C = CFLAG_16(FLAG_C);
\r
3758 if(COND_CS() && BIT_B(word2))
\r
3759 m68ki_exception_trap(EXCEPTION_CHK);
\r
3762 m68ki_exception_illegal();
\r
3766 M68KMAKE_OP(chk2cmp2, 32, ., pcdi)
\r
3768 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
3770 uint word2 = OPER_I_16();
\r
3771 uint compare = REG_DA[(word2 >> 12) & 15];
\r
3772 uint ea = EA_PCDI_32();
\r
3773 uint lower_bound = m68ki_read_pcrel_32(ea);
\r
3774 uint upper_bound = m68ki_read_pcrel_32(ea + 4);
\r
3776 FLAG_C = compare - lower_bound;
\r
3777 FLAG_Z = !((upper_bound==compare) | (lower_bound==compare));
\r
3778 FLAG_C = CFLAG_SUB_32(lower_bound, compare, FLAG_C);
\r
3782 m68ki_exception_trap(EXCEPTION_CHK);
\r
3786 FLAG_C = upper_bound - compare;
\r
3787 FLAG_C = CFLAG_SUB_32(compare, upper_bound, FLAG_C);
\r
3788 if(COND_CS() && BIT_B(word2))
\r
3789 m68ki_exception_trap(EXCEPTION_CHK);
\r
3792 m68ki_exception_illegal();
\r
3796 M68KMAKE_OP(chk2cmp2, 32, ., pcix)
\r
3798 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
3800 uint word2 = OPER_I_16();
\r
3801 uint compare = REG_DA[(word2 >> 12) & 15];
\r
3802 uint ea = EA_PCIX_32();
\r
3803 uint lower_bound = m68ki_read_pcrel_32(ea);
\r
3804 uint upper_bound = m68ki_read_pcrel_32(ea + 4);
\r
3806 FLAG_C = compare - lower_bound;
\r
3807 FLAG_Z = !((upper_bound==compare) | (lower_bound==compare));
\r
3808 FLAG_C = CFLAG_SUB_32(lower_bound, compare, FLAG_C);
\r
3812 m68ki_exception_trap(EXCEPTION_CHK);
\r
3816 FLAG_C = upper_bound - compare;
\r
3817 FLAG_C = CFLAG_SUB_32(compare, upper_bound, FLAG_C);
\r
3818 if(COND_CS() && BIT_B(word2))
\r
3819 m68ki_exception_trap(EXCEPTION_CHK);
\r
3822 m68ki_exception_illegal();
\r
3826 M68KMAKE_OP(chk2cmp2, 32, ., .)
\r
3828 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
3830 uint word2 = OPER_I_16();
\r
3831 uint compare = REG_DA[(word2 >> 12) & 15];
\r
3832 uint ea = M68KMAKE_GET_EA_AY_32;
\r
3833 uint lower_bound = m68ki_read_32(ea);
\r
3834 uint upper_bound = m68ki_read_32(ea + 4);
\r
3836 FLAG_C = compare - lower_bound;
\r
3837 FLAG_Z = !((upper_bound==compare) | (lower_bound==compare));
\r
3838 FLAG_C = CFLAG_SUB_32(lower_bound, compare, FLAG_C);
\r
3842 m68ki_exception_trap(EXCEPTION_CHK);
\r
3846 FLAG_C = upper_bound - compare;
\r
3847 FLAG_C = CFLAG_SUB_32(compare, upper_bound, FLAG_C);
\r
3848 if(COND_CS() && BIT_B(word2))
\r
3849 m68ki_exception_trap(EXCEPTION_CHK);
\r
3852 m68ki_exception_illegal();
\r
3856 M68KMAKE_OP(clr, 8, ., d)
\r
3860 FLAG_N = NFLAG_CLEAR;
\r
3861 FLAG_V = VFLAG_CLEAR;
\r
3862 FLAG_C = CFLAG_CLEAR;
\r
3863 FLAG_Z = ZFLAG_SET;
\r
3867 M68KMAKE_OP(clr, 8, ., .)
\r
3869 m68ki_write_8(M68KMAKE_GET_EA_AY_8, 0);
\r
3871 FLAG_N = NFLAG_CLEAR;
\r
3872 FLAG_V = VFLAG_CLEAR;
\r
3873 FLAG_C = CFLAG_CLEAR;
\r
3874 FLAG_Z = ZFLAG_SET;
\r
3878 M68KMAKE_OP(clr, 16, ., d)
\r
3882 FLAG_N = NFLAG_CLEAR;
\r
3883 FLAG_V = VFLAG_CLEAR;
\r
3884 FLAG_C = CFLAG_CLEAR;
\r
3885 FLAG_Z = ZFLAG_SET;
\r
3889 M68KMAKE_OP(clr, 16, ., .)
\r
3891 m68ki_write_16(M68KMAKE_GET_EA_AY_16, 0);
\r
3893 FLAG_N = NFLAG_CLEAR;
\r
3894 FLAG_V = VFLAG_CLEAR;
\r
3895 FLAG_C = CFLAG_CLEAR;
\r
3896 FLAG_Z = ZFLAG_SET;
\r
3900 M68KMAKE_OP(clr, 32, ., d)
\r
3904 FLAG_N = NFLAG_CLEAR;
\r
3905 FLAG_V = VFLAG_CLEAR;
\r
3906 FLAG_C = CFLAG_CLEAR;
\r
3907 FLAG_Z = ZFLAG_SET;
\r
3911 M68KMAKE_OP(clr, 32, ., .)
\r
3913 m68ki_write_32(M68KMAKE_GET_EA_AY_32, 0);
\r
3915 FLAG_N = NFLAG_CLEAR;
\r
3916 FLAG_V = VFLAG_CLEAR;
\r
3917 FLAG_C = CFLAG_CLEAR;
\r
3918 FLAG_Z = ZFLAG_SET;
\r
3922 M68KMAKE_OP(cmp, 8, ., d)
\r
3924 uint src = MASK_OUT_ABOVE_8(DY);
\r
3925 uint dst = MASK_OUT_ABOVE_8(DX);
\r
3926 uint res = dst - src;
\r
3928 FLAG_N = NFLAG_8(res);
\r
3929 FLAG_Z = MASK_OUT_ABOVE_8(res);
\r
3930 FLAG_V = VFLAG_SUB_8(src, dst, res);
\r
3931 FLAG_C = CFLAG_8(res);
\r
3935 M68KMAKE_OP(cmp, 8, ., .)
\r
3937 uint src = M68KMAKE_GET_OPER_AY_8;
\r
3938 uint dst = MASK_OUT_ABOVE_8(DX);
\r
3939 uint res = dst - src;
\r
3941 FLAG_N = NFLAG_8(res);
\r
3942 FLAG_Z = MASK_OUT_ABOVE_8(res);
\r
3943 FLAG_V = VFLAG_SUB_8(src, dst, res);
\r
3944 FLAG_C = CFLAG_8(res);
\r
3948 M68KMAKE_OP(cmp, 16, ., d)
\r
3950 uint src = MASK_OUT_ABOVE_16(DY);
\r
3951 uint dst = MASK_OUT_ABOVE_16(DX);
\r
3952 uint res = dst - src;
\r
3954 FLAG_N = NFLAG_16(res);
\r
3955 FLAG_Z = MASK_OUT_ABOVE_16(res);
\r
3956 FLAG_V = VFLAG_SUB_16(src, dst, res);
\r
3957 FLAG_C = CFLAG_16(res);
\r
3961 M68KMAKE_OP(cmp, 16, ., a)
\r
3963 uint src = MASK_OUT_ABOVE_16(AY);
\r
3964 uint dst = MASK_OUT_ABOVE_16(DX);
\r
3965 uint res = dst - src;
\r
3967 FLAG_N = NFLAG_16(res);
\r
3968 FLAG_Z = MASK_OUT_ABOVE_16(res);
\r
3969 FLAG_V = VFLAG_SUB_16(src, dst, res);
\r
3970 FLAG_C = CFLAG_16(res);
\r
3974 M68KMAKE_OP(cmp, 16, ., .)
\r
3976 uint src = M68KMAKE_GET_OPER_AY_16;
\r
3977 uint dst = MASK_OUT_ABOVE_16(DX);
\r
3978 uint res = dst - src;
\r
3980 FLAG_N = NFLAG_16(res);
\r
3981 FLAG_Z = MASK_OUT_ABOVE_16(res);
\r
3982 FLAG_V = VFLAG_SUB_16(src, dst, res);
\r
3983 FLAG_C = CFLAG_16(res);
\r
3987 M68KMAKE_OP(cmp, 32, ., d)
\r
3991 uint res = dst - src;
\r
3993 FLAG_N = NFLAG_32(res);
\r
3994 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
3995 FLAG_V = VFLAG_SUB_32(src, dst, res);
\r
3996 FLAG_C = CFLAG_SUB_32(src, dst, res);
\r
4000 M68KMAKE_OP(cmp, 32, ., a)
\r
4004 uint res = dst - src;
\r
4006 FLAG_N = NFLAG_32(res);
\r
4007 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
4008 FLAG_V = VFLAG_SUB_32(src, dst, res);
\r
4009 FLAG_C = CFLAG_SUB_32(src, dst, res);
\r
4013 M68KMAKE_OP(cmp, 32, ., .)
\r
4015 uint src = M68KMAKE_GET_OPER_AY_32;
\r
4017 uint res = dst - src;
\r
4019 FLAG_N = NFLAG_32(res);
\r
4020 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
4021 FLAG_V = VFLAG_SUB_32(src, dst, res);
\r
4022 FLAG_C = CFLAG_SUB_32(src, dst, res);
\r
4026 M68KMAKE_OP(cmpa, 16, ., d)
\r
4028 uint src = MAKE_INT_16(DY);
\r
4030 uint res = dst - src;
\r
4032 FLAG_N = NFLAG_32(res);
\r
4033 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
4034 FLAG_V = VFLAG_SUB_32(src, dst, res);
\r
4035 FLAG_C = CFLAG_SUB_32(src, dst, res);
\r
4039 M68KMAKE_OP(cmpa, 16, ., a)
\r
4041 uint src = MAKE_INT_16(AY);
\r
4043 uint res = dst - src;
\r
4045 FLAG_N = NFLAG_32(res);
\r
4046 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
4047 FLAG_V = VFLAG_SUB_32(src, dst, res);
\r
4048 FLAG_C = CFLAG_SUB_32(src, dst, res);
\r
4052 M68KMAKE_OP(cmpa, 16, ., .)
\r
4054 uint src = MAKE_INT_16(M68KMAKE_GET_OPER_AY_16);
\r
4056 uint res = dst - src;
\r
4058 FLAG_N = NFLAG_32(res);
\r
4059 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
4060 FLAG_V = VFLAG_SUB_32(src, dst, res);
\r
4061 FLAG_C = CFLAG_SUB_32(src, dst, res);
\r
4065 M68KMAKE_OP(cmpa, 32, ., d)
\r
4069 uint res = dst - src;
\r
4071 FLAG_N = NFLAG_32(res);
\r
4072 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
4073 FLAG_V = VFLAG_SUB_32(src, dst, res);
\r
4074 FLAG_C = CFLAG_SUB_32(src, dst, res);
\r
4078 M68KMAKE_OP(cmpa, 32, ., a)
\r
4082 uint res = dst - src;
\r
4084 FLAG_N = NFLAG_32(res);
\r
4085 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
4086 FLAG_V = VFLAG_SUB_32(src, dst, res);
\r
4087 FLAG_C = CFLAG_SUB_32(src, dst, res);
\r
4091 M68KMAKE_OP(cmpa, 32, ., .)
\r
4093 uint src = M68KMAKE_GET_OPER_AY_32;
\r
4095 uint res = dst - src;
\r
4097 FLAG_N = NFLAG_32(res);
\r
4098 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
4099 FLAG_V = VFLAG_SUB_32(src, dst, res);
\r
4100 FLAG_C = CFLAG_SUB_32(src, dst, res);
\r
4104 M68KMAKE_OP(cmpi, 8, ., d)
\r
4106 uint src = OPER_I_8();
\r
4107 uint dst = MASK_OUT_ABOVE_8(DY);
\r
4108 uint res = dst - src;
\r
4110 FLAG_N = NFLAG_8(res);
\r
4111 FLAG_Z = MASK_OUT_ABOVE_8(res);
\r
4112 FLAG_V = VFLAG_SUB_8(src, dst, res);
\r
4113 FLAG_C = CFLAG_8(res);
\r
4117 M68KMAKE_OP(cmpi, 8, ., .)
\r
4119 uint src = OPER_I_8();
\r
4120 uint dst = M68KMAKE_GET_OPER_AY_8;
\r
4121 uint res = dst - src;
\r
4123 FLAG_N = NFLAG_8(res);
\r
4124 FLAG_Z = MASK_OUT_ABOVE_8(res);
\r
4125 FLAG_V = VFLAG_SUB_8(src, dst, res);
\r
4126 FLAG_C = CFLAG_8(res);
\r
4130 M68KMAKE_OP(cmpi, 8, ., pcdi)
\r
4132 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
4134 uint src = OPER_I_8();
\r
4135 uint dst = OPER_PCDI_8();
\r
4136 uint res = dst - src;
\r
4138 FLAG_N = NFLAG_8(res);
\r
4139 FLAG_Z = MASK_OUT_ABOVE_8(res);
\r
4140 FLAG_V = VFLAG_SUB_8(src, dst, res);
\r
4141 FLAG_C = CFLAG_8(res);
\r
4144 m68ki_exception_illegal();
\r
4148 M68KMAKE_OP(cmpi, 8, ., pcix)
\r
4150 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
4152 uint src = OPER_I_8();
\r
4153 uint dst = OPER_PCIX_8();
\r
4154 uint res = dst - src;
\r
4156 FLAG_N = NFLAG_8(res);
\r
4157 FLAG_Z = MASK_OUT_ABOVE_8(res);
\r
4158 FLAG_V = VFLAG_SUB_8(src, dst, res);
\r
4159 FLAG_C = CFLAG_8(res);
\r
4162 m68ki_exception_illegal();
\r
4166 M68KMAKE_OP(cmpi, 16, ., d)
\r
4168 uint src = OPER_I_16();
\r
4169 uint dst = MASK_OUT_ABOVE_16(DY);
\r
4170 uint res = dst - src;
\r
4172 FLAG_N = NFLAG_16(res);
\r
4173 FLAG_Z = MASK_OUT_ABOVE_16(res);
\r
4174 FLAG_V = VFLAG_SUB_16(src, dst, res);
\r
4175 FLAG_C = CFLAG_16(res);
\r
4179 M68KMAKE_OP(cmpi, 16, ., .)
\r
4181 uint src = OPER_I_16();
\r
4182 uint dst = M68KMAKE_GET_OPER_AY_16;
\r
4183 uint res = dst - src;
\r
4185 FLAG_N = NFLAG_16(res);
\r
4186 FLAG_Z = MASK_OUT_ABOVE_16(res);
\r
4187 FLAG_V = VFLAG_SUB_16(src, dst, res);
\r
4188 FLAG_C = CFLAG_16(res);
\r
4192 M68KMAKE_OP(cmpi, 16, ., pcdi)
\r
4194 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
4196 uint src = OPER_I_16();
\r
4197 uint dst = OPER_PCDI_16();
\r
4198 uint res = dst - src;
\r
4200 FLAG_N = NFLAG_16(res);
\r
4201 FLAG_Z = MASK_OUT_ABOVE_16(res);
\r
4202 FLAG_V = VFLAG_SUB_16(src, dst, res);
\r
4203 FLAG_C = CFLAG_16(res);
\r
4206 m68ki_exception_illegal();
\r
4210 M68KMAKE_OP(cmpi, 16, ., pcix)
\r
4212 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
4214 uint src = OPER_I_16();
\r
4215 uint dst = OPER_PCIX_16();
\r
4216 uint res = dst - src;
\r
4218 FLAG_N = NFLAG_16(res);
\r
4219 FLAG_Z = MASK_OUT_ABOVE_16(res);
\r
4220 FLAG_V = VFLAG_SUB_16(src, dst, res);
\r
4221 FLAG_C = CFLAG_16(res);
\r
4224 m68ki_exception_illegal();
\r
4228 M68KMAKE_OP(cmpi, 32, ., d)
\r
4230 uint src = OPER_I_32();
\r
4232 uint res = dst - src;
\r
4234 m68ki_cmpild_callback(src, REG_IR & 7); /* auto-disable (see m68kcpu.h) */
\r
4236 FLAG_N = NFLAG_32(res);
\r
4237 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
4238 FLAG_V = VFLAG_SUB_32(src, dst, res);
\r
4239 FLAG_C = CFLAG_SUB_32(src, dst, res);
\r
4243 M68KMAKE_OP(cmpi, 32, ., .)
\r
4245 uint src = OPER_I_32();
\r
4246 uint dst = M68KMAKE_GET_OPER_AY_32;
\r
4247 uint res = dst - src;
\r
4249 FLAG_N = NFLAG_32(res);
\r
4250 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
4251 FLAG_V = VFLAG_SUB_32(src, dst, res);
\r
4252 FLAG_C = CFLAG_SUB_32(src, dst, res);
\r
4256 M68KMAKE_OP(cmpi, 32, ., pcdi)
\r
4258 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
4260 uint src = OPER_I_32();
\r
4261 uint dst = OPER_PCDI_32();
\r
4262 uint res = dst - src;
\r
4264 FLAG_N = NFLAG_32(res);
\r
4265 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
4266 FLAG_V = VFLAG_SUB_32(src, dst, res);
\r
4267 FLAG_C = CFLAG_SUB_32(src, dst, res);
\r
4270 m68ki_exception_illegal();
\r
4274 M68KMAKE_OP(cmpi, 32, ., pcix)
\r
4276 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
4278 uint src = OPER_I_32();
\r
4279 uint dst = OPER_PCIX_32();
\r
4280 uint res = dst - src;
\r
4282 FLAG_N = NFLAG_32(res);
\r
4283 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
4284 FLAG_V = VFLAG_SUB_32(src, dst, res);
\r
4285 FLAG_C = CFLAG_SUB_32(src, dst, res);
\r
4288 m68ki_exception_illegal();
\r
4292 M68KMAKE_OP(cmpm, 8, ., ax7)
\r
4294 uint src = OPER_AY_PI_8();
\r
4295 uint dst = OPER_A7_PI_8();
\r
4296 uint res = dst - src;
\r
4298 FLAG_N = NFLAG_8(res);
\r
4299 FLAG_Z = MASK_OUT_ABOVE_8(res);
\r
4300 FLAG_V = VFLAG_SUB_8(src, dst, res);
\r
4301 FLAG_C = CFLAG_8(res);
\r
4305 M68KMAKE_OP(cmpm, 8, ., ay7)
\r
4307 uint src = OPER_A7_PI_8();
\r
4308 uint dst = OPER_AX_PI_8();
\r
4309 uint res = dst - src;
\r
4311 FLAG_N = NFLAG_8(res);
\r
4312 FLAG_Z = MASK_OUT_ABOVE_8(res);
\r
4313 FLAG_V = VFLAG_SUB_8(src, dst, res);
\r
4314 FLAG_C = CFLAG_8(res);
\r
4318 M68KMAKE_OP(cmpm, 8, ., axy7)
\r
4320 uint src = OPER_A7_PI_8();
\r
4321 uint dst = OPER_A7_PI_8();
\r
4322 uint res = dst - src;
\r
4324 FLAG_N = NFLAG_8(res);
\r
4325 FLAG_Z = MASK_OUT_ABOVE_8(res);
\r
4326 FLAG_V = VFLAG_SUB_8(src, dst, res);
\r
4327 FLAG_C = CFLAG_8(res);
\r
4331 M68KMAKE_OP(cmpm, 8, ., .)
\r
4333 uint src = OPER_AY_PI_8();
\r
4334 uint dst = OPER_AX_PI_8();
\r
4335 uint res = dst - src;
\r
4337 FLAG_N = NFLAG_8(res);
\r
4338 FLAG_Z = MASK_OUT_ABOVE_8(res);
\r
4339 FLAG_V = VFLAG_SUB_8(src, dst, res);
\r
4340 FLAG_C = CFLAG_8(res);
\r
4344 M68KMAKE_OP(cmpm, 16, ., .)
\r
4346 uint src = OPER_AY_PI_16();
\r
4347 uint dst = OPER_AX_PI_16();
\r
4348 uint res = dst - src;
\r
4350 FLAG_N = NFLAG_16(res);
\r
4351 FLAG_Z = MASK_OUT_ABOVE_16(res);
\r
4352 FLAG_V = VFLAG_SUB_16(src, dst, res);
\r
4353 FLAG_C = CFLAG_16(res);
\r
4357 M68KMAKE_OP(cmpm, 32, ., .)
\r
4359 uint src = OPER_AY_PI_32();
\r
4360 uint dst = OPER_AX_PI_32();
\r
4361 uint res = dst - src;
\r
4363 FLAG_N = NFLAG_32(res);
\r
4364 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
4365 FLAG_V = VFLAG_SUB_32(src, dst, res);
\r
4366 FLAG_C = CFLAG_SUB_32(src, dst, res);
\r
4370 M68KMAKE_OP(cpbcc, 32, ., .)
\r
4372 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
4374 M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n",
\r
4375 m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR,
\r
4376 m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2))));
\r
4379 m68ki_exception_1111();
\r
4383 M68KMAKE_OP(cpdbcc, 32, ., .)
\r
4385 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
4387 M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n",
\r
4388 m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR,
\r
4389 m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2))));
\r
4392 m68ki_exception_1111();
\r
4396 M68KMAKE_OP(cpgen, 32, ., .)
\r
4398 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
4400 M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n",
\r
4401 m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR,
\r
4402 m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2))));
\r
4405 m68ki_exception_1111();
\r
4409 M68KMAKE_OP(cpscc, 32, ., .)
\r
4411 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
4413 M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n",
\r
4414 m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR,
\r
4415 m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2))));
\r
4418 m68ki_exception_1111();
\r
4422 M68KMAKE_OP(cptrapcc, 32, ., .)
\r
4424 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
4426 M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n",
\r
4427 m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR,
\r
4428 m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2))));
\r
4431 m68ki_exception_1111();
\r
4435 M68KMAKE_OP(dbt, 16, ., .)
\r
4441 M68KMAKE_OP(dbf, 16, ., .)
\r
4443 uint* r_dst = &DY;
\r
4444 uint res = MASK_OUT_ABOVE_16(*r_dst - 1);
\r
4446 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
\r
4449 uint offset = OPER_I_16();
\r
4451 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
4452 m68ki_branch_16(offset);
\r
4453 USE_CYCLES(CYC_DBCC_F_NOEXP);
\r
4457 USE_CYCLES(CYC_DBCC_F_EXP);
\r
4461 M68KMAKE_OP(dbcc, 16, ., .)
\r
4463 if(M68KMAKE_NOT_CC)
\r
4465 uint* r_dst = &DY;
\r
4466 uint res = MASK_OUT_ABOVE_16(*r_dst - 1);
\r
4468 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
\r
4471 uint offset = OPER_I_16();
\r
4473 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
4474 m68ki_branch_16(offset);
\r
4475 USE_CYCLES(CYC_DBCC_F_NOEXP);
\r
4479 USE_CYCLES(CYC_DBCC_F_EXP);
\r
4486 M68KMAKE_OP(divs, 16, ., d)
\r
4488 uint* r_dst = &DX;
\r
4489 sint src = MAKE_INT_16(DY);
\r
4495 if((uint32)*r_dst == 0x80000000 && src == -1)
\r
4498 FLAG_N = NFLAG_CLEAR;
\r
4499 FLAG_V = VFLAG_CLEAR;
\r
4500 FLAG_C = CFLAG_CLEAR;
\r
4505 quotient = MAKE_INT_32(*r_dst) / src;
\r
4506 remainder = MAKE_INT_32(*r_dst) % src;
\r
4508 if(quotient == MAKE_INT_16(quotient))
\r
4510 FLAG_Z = quotient;
\r
4511 FLAG_N = NFLAG_16(quotient);
\r
4512 FLAG_V = VFLAG_CLEAR;
\r
4513 FLAG_C = CFLAG_CLEAR;
\r
4514 *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16));
\r
4517 FLAG_V = VFLAG_SET;
\r
4520 m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
\r
4524 M68KMAKE_OP(divs, 16, ., .)
\r
4526 uint* r_dst = &DX;
\r
4527 sint src = MAKE_INT_16(M68KMAKE_GET_OPER_AY_16);
\r
4533 if((uint32)*r_dst == 0x80000000 && src == -1)
\r
4536 FLAG_N = NFLAG_CLEAR;
\r
4537 FLAG_V = VFLAG_CLEAR;
\r
4538 FLAG_C = CFLAG_CLEAR;
\r
4543 quotient = MAKE_INT_32(*r_dst) / src;
\r
4544 remainder = MAKE_INT_32(*r_dst) % src;
\r
4546 if(quotient == MAKE_INT_16(quotient))
\r
4548 FLAG_Z = quotient;
\r
4549 FLAG_N = NFLAG_16(quotient);
\r
4550 FLAG_V = VFLAG_CLEAR;
\r
4551 FLAG_C = CFLAG_CLEAR;
\r
4552 *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16));
\r
4555 FLAG_V = VFLAG_SET;
\r
4558 m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
\r
4562 M68KMAKE_OP(divu, 16, ., d)
\r
4564 uint* r_dst = &DX;
\r
4565 uint src = MASK_OUT_ABOVE_16(DY);
\r
4569 uint quotient = *r_dst / src;
\r
4570 uint remainder = *r_dst % src;
\r
4572 if(quotient < 0x10000)
\r
4574 FLAG_Z = quotient;
\r
4575 FLAG_N = NFLAG_16(quotient);
\r
4576 FLAG_V = VFLAG_CLEAR;
\r
4577 FLAG_C = CFLAG_CLEAR;
\r
4578 *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16));
\r
4581 FLAG_V = VFLAG_SET;
\r
4584 m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
\r
4588 M68KMAKE_OP(divu, 16, ., .)
\r
4590 uint* r_dst = &DX;
\r
4591 uint src = M68KMAKE_GET_OPER_AY_16;
\r
4595 uint quotient = *r_dst / src;
\r
4596 uint remainder = *r_dst % src;
\r
4598 if(quotient < 0x10000)
\r
4600 FLAG_Z = quotient;
\r
4601 FLAG_N = NFLAG_16(quotient);
\r
4602 FLAG_V = VFLAG_CLEAR;
\r
4603 FLAG_C = CFLAG_CLEAR;
\r
4604 *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16));
\r
4607 FLAG_V = VFLAG_SET;
\r
4610 m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
\r
4614 M68KMAKE_OP(divl, 32, ., d)
\r
4616 #if M68K_USE_64_BIT
\r
4618 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
4620 uint word2 = OPER_I_16();
\r
4621 uint64 divisor = DY;
\r
4622 uint64 dividend = 0;
\r
4623 uint64 quotient = 0;
\r
4624 uint64 remainder = 0;
\r
4628 if(BIT_A(word2)) /* 64 bit */
\r
4630 dividend = REG_D[word2 & 7];
\r
4632 dividend |= REG_D[(word2 >> 12) & 7];
\r
4634 if(BIT_B(word2)) /* signed */
\r
4636 quotient = (uint64)((sint64)dividend / (sint64)((sint32)divisor));
\r
4637 remainder = (uint64)((sint64)dividend % (sint64)((sint32)divisor));
\r
4638 if((sint64)quotient != (sint64)((sint32)quotient))
\r
4640 FLAG_V = VFLAG_SET;
\r
4644 else /* unsigned */
\r
4646 quotient = dividend / divisor;
\r
4647 if(quotient > 0xffffffff)
\r
4649 FLAG_V = VFLAG_SET;
\r
4652 remainder = dividend % divisor;
\r
4657 dividend = REG_D[(word2 >> 12) & 7];
\r
4658 if(BIT_B(word2)) /* signed */
\r
4660 quotient = (uint64)((sint64)((sint32)dividend) / (sint64)((sint32)divisor));
\r
4661 remainder = (uint64)((sint64)((sint32)dividend) % (sint64)((sint32)divisor));
\r
4663 else /* unsigned */
\r
4665 quotient = dividend / divisor;
\r
4666 remainder = dividend % divisor;
\r
4670 REG_D[word2 & 7] = remainder;
\r
4671 REG_D[(word2 >> 12) & 7] = quotient;
\r
4673 FLAG_N = NFLAG_32(quotient);
\r
4674 FLAG_Z = quotient;
\r
4675 FLAG_V = VFLAG_CLEAR;
\r
4676 FLAG_C = CFLAG_CLEAR;
\r
4679 m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
\r
4682 m68ki_exception_illegal();
\r
4686 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
4688 uint word2 = OPER_I_16();
\r
4689 uint divisor = DY;
\r
4690 uint dividend_hi = REG_D[word2 & 7];
\r
4691 uint dividend_lo = REG_D[(word2 >> 12) & 7];
\r
4692 uint quotient = 0;
\r
4693 uint remainder = 0;
\r
4694 uint dividend_neg = 0;
\r
4695 uint divisor_neg = 0;
\r
4701 /* quad / long : long quotient, long remainder */
\r
4704 if(BIT_B(word2)) /* signed */
\r
4706 /* special case in signed divide */
\r
4707 if(dividend_hi == 0 && dividend_lo == 0x80000000 && divisor == 0xffffffff)
\r
4709 REG_D[word2 & 7] = 0;
\r
4710 REG_D[(word2 >> 12) & 7] = 0x80000000;
\r
4712 FLAG_N = NFLAG_SET;
\r
4713 FLAG_Z = ZFLAG_CLEAR;
\r
4714 FLAG_V = VFLAG_CLEAR;
\r
4715 FLAG_C = CFLAG_CLEAR;
\r
4718 if(GET_MSB_32(dividend_hi))
\r
4721 dividend_hi = (uint)MASK_OUT_ABOVE_32((-(sint)dividend_hi) - (dividend_lo != 0));
\r
4722 dividend_lo = (uint)MASK_OUT_ABOVE_32(-(sint)dividend_lo);
\r
4724 if(GET_MSB_32(divisor))
\r
4727 divisor = (uint)MASK_OUT_ABOVE_32(-(sint)divisor);
\r
4732 /* if the upper long is greater than the divisor, we're overflowing. */
\r
4733 if(dividend_hi >= divisor)
\r
4735 FLAG_V = VFLAG_SET;
\r
4739 for(i = 31; i >= 0; i--)
\r
4742 remainder = (remainder << 1) + ((dividend_hi >> i) & 1);
\r
4743 if(remainder >= divisor)
\r
4745 remainder -= divisor;
\r
4749 for(i = 31; i >= 0; i--)
\r
4752 overflow = GET_MSB_32(remainder);
\r
4753 remainder = (remainder << 1) + ((dividend_lo >> i) & 1);
\r
4754 if(remainder >= divisor || overflow)
\r
4756 remainder -= divisor;
\r
4761 if(BIT_B(word2)) /* signed */
\r
4763 if(quotient > 0x7fffffff)
\r
4765 FLAG_V = VFLAG_SET;
\r
4770 remainder = (uint)MASK_OUT_ABOVE_32(-(sint)remainder);
\r
4771 quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient);
\r
4774 quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient);
\r
4777 REG_D[word2 & 7] = remainder;
\r
4778 REG_D[(word2 >> 12) & 7] = quotient;
\r
4780 FLAG_N = NFLAG_32(quotient);
\r
4781 FLAG_Z = quotient;
\r
4782 FLAG_V = VFLAG_CLEAR;
\r
4783 FLAG_C = CFLAG_CLEAR;
\r
4787 /* long / long: long quotient, maybe long remainder */
\r
4788 if(BIT_B(word2)) /* signed */
\r
4790 /* Special case in divide */
\r
4791 if(dividend_lo == 0x80000000 && divisor == 0xffffffff)
\r
4793 FLAG_N = NFLAG_SET;
\r
4794 FLAG_Z = ZFLAG_CLEAR;
\r
4795 FLAG_V = VFLAG_CLEAR;
\r
4796 FLAG_C = CFLAG_CLEAR;
\r
4797 REG_D[(word2 >> 12) & 7] = 0x80000000;
\r
4798 REG_D[word2 & 7] = 0;
\r
4801 REG_D[word2 & 7] = MAKE_INT_32(dividend_lo) % MAKE_INT_32(divisor);
\r
4802 quotient = REG_D[(word2 >> 12) & 7] = MAKE_INT_32(dividend_lo) / MAKE_INT_32(divisor);
\r
4806 REG_D[word2 & 7] = MASK_OUT_ABOVE_32(dividend_lo) % MASK_OUT_ABOVE_32(divisor);
\r
4807 quotient = REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(dividend_lo) / MASK_OUT_ABOVE_32(divisor);
\r
4810 FLAG_N = NFLAG_32(quotient);
\r
4811 FLAG_Z = quotient;
\r
4812 FLAG_V = VFLAG_CLEAR;
\r
4813 FLAG_C = CFLAG_CLEAR;
\r
4816 m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
\r
4819 m68ki_exception_illegal();
\r
4825 M68KMAKE_OP(divl, 32, ., .)
\r
4827 #if M68K_USE_64_BIT
\r
4829 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
4831 uint word2 = OPER_I_16();
\r
4832 uint64 divisor = M68KMAKE_GET_OPER_AY_32;
\r
4833 uint64 dividend = 0;
\r
4834 uint64 quotient = 0;
\r
4835 uint64 remainder = 0;
\r
4839 if(BIT_A(word2)) /* 64 bit */
\r
4841 dividend = REG_D[word2 & 7];
\r
4843 dividend |= REG_D[(word2 >> 12) & 7];
\r
4845 if(BIT_B(word2)) /* signed */
\r
4847 quotient = (uint64)((sint64)dividend / (sint64)((sint32)divisor));
\r
4848 remainder = (uint64)((sint64)dividend % (sint64)((sint32)divisor));
\r
4849 if((sint64)quotient != (sint64)((sint32)quotient))
\r
4851 FLAG_V = VFLAG_SET;
\r
4855 else /* unsigned */
\r
4857 quotient = dividend / divisor;
\r
4858 if(quotient > 0xffffffff)
\r
4860 FLAG_V = VFLAG_SET;
\r
4863 remainder = dividend % divisor;
\r
4868 dividend = REG_D[(word2 >> 12) & 7];
\r
4869 if(BIT_B(word2)) /* signed */
\r
4871 quotient = (uint64)((sint64)((sint32)dividend) / (sint64)((sint32)divisor));
\r
4872 remainder = (uint64)((sint64)((sint32)dividend) % (sint64)((sint32)divisor));
\r
4874 else /* unsigned */
\r
4876 quotient = dividend / divisor;
\r
4877 remainder = dividend % divisor;
\r
4881 REG_D[word2 & 7] = remainder;
\r
4882 REG_D[(word2 >> 12) & 7] = quotient;
\r
4884 FLAG_N = NFLAG_32(quotient);
\r
4885 FLAG_Z = quotient;
\r
4886 FLAG_V = VFLAG_CLEAR;
\r
4887 FLAG_C = CFLAG_CLEAR;
\r
4890 m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
\r
4893 m68ki_exception_illegal();
\r
4897 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
4899 uint word2 = OPER_I_16();
\r
4900 uint divisor = M68KMAKE_GET_OPER_AY_32;
\r
4901 uint dividend_hi = REG_D[word2 & 7];
\r
4902 uint dividend_lo = REG_D[(word2 >> 12) & 7];
\r
4903 uint quotient = 0;
\r
4904 uint remainder = 0;
\r
4905 uint dividend_neg = 0;
\r
4906 uint divisor_neg = 0;
\r
4912 /* quad / long : long quotient, long remainder */
\r
4915 if(BIT_B(word2)) /* signed */
\r
4917 /* special case in signed divide */
\r
4918 if(dividend_hi == 0 && dividend_lo == 0x80000000 && divisor == 0xffffffff)
\r
4920 REG_D[word2 & 7] = 0;
\r
4921 REG_D[(word2 >> 12) & 7] = 0x80000000;
\r
4923 FLAG_N = NFLAG_SET;
\r
4924 FLAG_Z = ZFLAG_CLEAR;
\r
4925 FLAG_V = VFLAG_CLEAR;
\r
4926 FLAG_C = CFLAG_CLEAR;
\r
4929 if(GET_MSB_32(dividend_hi))
\r
4932 dividend_hi = (uint)MASK_OUT_ABOVE_32((-(sint)dividend_hi) - (dividend_lo != 0));
\r
4933 dividend_lo = (uint)MASK_OUT_ABOVE_32(-(sint)dividend_lo);
\r
4935 if(GET_MSB_32(divisor))
\r
4938 divisor = (uint)MASK_OUT_ABOVE_32(-(sint)divisor);
\r
4943 /* if the upper long is greater than the divisor, we're overflowing. */
\r
4944 if(dividend_hi >= divisor)
\r
4946 FLAG_V = VFLAG_SET;
\r
4950 for(i = 31; i >= 0; i--)
\r
4953 remainder = (remainder << 1) + ((dividend_hi >> i) & 1);
\r
4954 if(remainder >= divisor)
\r
4956 remainder -= divisor;
\r
4960 for(i = 31; i >= 0; i--)
\r
4963 overflow = GET_MSB_32(remainder);
\r
4964 remainder = (remainder << 1) + ((dividend_lo >> i) & 1);
\r
4965 if(remainder >= divisor || overflow)
\r
4967 remainder -= divisor;
\r
4972 if(BIT_B(word2)) /* signed */
\r
4974 if(quotient > 0x7fffffff)
\r
4976 FLAG_V = VFLAG_SET;
\r
4981 remainder = (uint)MASK_OUT_ABOVE_32(-(sint)remainder);
\r
4982 quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient);
\r
4985 quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient);
\r
4988 REG_D[word2 & 7] = remainder;
\r
4989 REG_D[(word2 >> 12) & 7] = quotient;
\r
4991 FLAG_N = NFLAG_32(quotient);
\r
4992 FLAG_Z = quotient;
\r
4993 FLAG_V = VFLAG_CLEAR;
\r
4994 FLAG_C = CFLAG_CLEAR;
\r
4998 /* long / long: long quotient, maybe long remainder */
\r
4999 if(BIT_B(word2)) /* signed */
\r
5001 /* Special case in divide */
\r
5002 if(dividend_lo == 0x80000000 && divisor == 0xffffffff)
\r
5004 FLAG_N = NFLAG_SET;
\r
5005 FLAG_Z = ZFLAG_CLEAR;
\r
5006 FLAG_V = VFLAG_CLEAR;
\r
5007 FLAG_C = CFLAG_CLEAR;
\r
5008 REG_D[(word2 >> 12) & 7] = 0x80000000;
\r
5009 REG_D[word2 & 7] = 0;
\r
5012 REG_D[word2 & 7] = MAKE_INT_32(dividend_lo) % MAKE_INT_32(divisor);
\r
5013 quotient = REG_D[(word2 >> 12) & 7] = MAKE_INT_32(dividend_lo) / MAKE_INT_32(divisor);
\r
5017 REG_D[word2 & 7] = MASK_OUT_ABOVE_32(dividend_lo) % MASK_OUT_ABOVE_32(divisor);
\r
5018 quotient = REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(dividend_lo) / MASK_OUT_ABOVE_32(divisor);
\r
5021 FLAG_N = NFLAG_32(quotient);
\r
5022 FLAG_Z = quotient;
\r
5023 FLAG_V = VFLAG_CLEAR;
\r
5024 FLAG_C = CFLAG_CLEAR;
\r
5027 m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
\r
5030 m68ki_exception_illegal();
\r
5036 M68KMAKE_OP(eor, 8, ., d)
\r
5038 uint res = MASK_OUT_ABOVE_8(DY ^= MASK_OUT_ABOVE_8(DX));
\r
5040 FLAG_N = NFLAG_8(res);
\r
5042 FLAG_C = CFLAG_CLEAR;
\r
5043 FLAG_V = VFLAG_CLEAR;
\r
5047 M68KMAKE_OP(eor, 8, ., .)
\r
5049 uint ea = M68KMAKE_GET_EA_AY_8;
\r
5050 uint res = MASK_OUT_ABOVE_8(DX ^ m68ki_read_8(ea));
\r
5052 m68ki_write_8(ea, res);
\r
5054 FLAG_N = NFLAG_8(res);
\r
5056 FLAG_C = CFLAG_CLEAR;
\r
5057 FLAG_V = VFLAG_CLEAR;
\r
5061 M68KMAKE_OP(eor, 16, ., d)
\r
5063 uint res = MASK_OUT_ABOVE_16(DY ^= MASK_OUT_ABOVE_16(DX));
\r
5065 FLAG_N = NFLAG_16(res);
\r
5067 FLAG_C = CFLAG_CLEAR;
\r
5068 FLAG_V = VFLAG_CLEAR;
\r
5072 M68KMAKE_OP(eor, 16, ., .)
\r
5074 uint ea = M68KMAKE_GET_EA_AY_16;
\r
5075 uint res = MASK_OUT_ABOVE_16(DX ^ m68ki_read_16(ea));
\r
5077 m68ki_write_16(ea, res);
\r
5079 FLAG_N = NFLAG_16(res);
\r
5081 FLAG_C = CFLAG_CLEAR;
\r
5082 FLAG_V = VFLAG_CLEAR;
\r
5086 M68KMAKE_OP(eor, 32, ., d)
\r
5088 uint res = DY ^= DX;
\r
5090 FLAG_N = NFLAG_32(res);
\r
5092 FLAG_C = CFLAG_CLEAR;
\r
5093 FLAG_V = VFLAG_CLEAR;
\r
5097 M68KMAKE_OP(eor, 32, ., .)
\r
5099 uint ea = M68KMAKE_GET_EA_AY_32;
\r
5100 uint res = DX ^ m68ki_read_32(ea);
\r
5102 m68ki_write_32(ea, res);
\r
5104 FLAG_N = NFLAG_32(res);
\r
5106 FLAG_C = CFLAG_CLEAR;
\r
5107 FLAG_V = VFLAG_CLEAR;
\r
5111 M68KMAKE_OP(eori, 8, ., d)
\r
5113 uint res = MASK_OUT_ABOVE_8(DY ^= OPER_I_8());
\r
5115 FLAG_N = NFLAG_8(res);
\r
5117 FLAG_C = CFLAG_CLEAR;
\r
5118 FLAG_V = VFLAG_CLEAR;
\r
5122 M68KMAKE_OP(eori, 8, ., .)
\r
5124 uint src = OPER_I_8();
\r
5125 uint ea = M68KMAKE_GET_EA_AY_8;
\r
5126 uint res = src ^ m68ki_read_8(ea);
\r
5128 m68ki_write_8(ea, res);
\r
5130 FLAG_N = NFLAG_8(res);
\r
5132 FLAG_C = CFLAG_CLEAR;
\r
5133 FLAG_V = VFLAG_CLEAR;
\r
5137 M68KMAKE_OP(eori, 16, ., d)
\r
5139 uint res = MASK_OUT_ABOVE_16(DY ^= OPER_I_16());
\r
5141 FLAG_N = NFLAG_16(res);
\r
5143 FLAG_C = CFLAG_CLEAR;
\r
5144 FLAG_V = VFLAG_CLEAR;
\r
5148 M68KMAKE_OP(eori, 16, ., .)
\r
5150 uint src = OPER_I_16();
\r
5151 uint ea = M68KMAKE_GET_EA_AY_16;
\r
5152 uint res = src ^ m68ki_read_16(ea);
\r
5154 m68ki_write_16(ea, res);
\r
5156 FLAG_N = NFLAG_16(res);
\r
5158 FLAG_C = CFLAG_CLEAR;
\r
5159 FLAG_V = VFLAG_CLEAR;
\r
5163 M68KMAKE_OP(eori, 32, ., d)
\r
5165 uint res = DY ^= OPER_I_32();
\r
5167 FLAG_N = NFLAG_32(res);
\r
5169 FLAG_C = CFLAG_CLEAR;
\r
5170 FLAG_V = VFLAG_CLEAR;
\r
5174 M68KMAKE_OP(eori, 32, ., .)
\r
5176 uint src = OPER_I_32();
\r
5177 uint ea = M68KMAKE_GET_EA_AY_32;
\r
5178 uint res = src ^ m68ki_read_32(ea);
\r
5180 m68ki_write_32(ea, res);
\r
5182 FLAG_N = NFLAG_32(res);
\r
5184 FLAG_C = CFLAG_CLEAR;
\r
5185 FLAG_V = VFLAG_CLEAR;
\r
5189 M68KMAKE_OP(eori, 16, toc, .)
\r
5191 m68ki_set_ccr(m68ki_get_ccr() ^ OPER_I_16());
\r
5195 M68KMAKE_OP(eori, 16, tos, .)
\r
5199 uint src = OPER_I_16();
\r
5200 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
5201 m68ki_set_sr(m68ki_get_sr() ^ src);
\r
5204 m68ki_exception_privilege_violation();
\r
5208 M68KMAKE_OP(exg, 32, dd, .)
\r
5210 uint* reg_a = &DX;
\r
5211 uint* reg_b = &DY;
\r
5212 uint tmp = *reg_a;
\r
5218 M68KMAKE_OP(exg, 32, aa, .)
\r
5220 uint* reg_a = &AX;
\r
5221 uint* reg_b = &AY;
\r
5222 uint tmp = *reg_a;
\r
5228 M68KMAKE_OP(exg, 32, da, .)
\r
5230 uint* reg_a = &DX;
\r
5231 uint* reg_b = &AY;
\r
5232 uint tmp = *reg_a;
\r
5238 M68KMAKE_OP(ext, 16, ., .)
\r
5240 uint* r_dst = &DY;
\r
5242 *r_dst = MASK_OUT_BELOW_16(*r_dst) | MASK_OUT_ABOVE_8(*r_dst) | (GET_MSB_8(*r_dst) ? 0xff00 : 0);
\r
5244 FLAG_N = NFLAG_16(*r_dst);
\r
5245 FLAG_Z = MASK_OUT_ABOVE_16(*r_dst);
\r
5246 FLAG_V = VFLAG_CLEAR;
\r
5247 FLAG_C = CFLAG_CLEAR;
\r
5251 M68KMAKE_OP(ext, 32, ., .)
\r
5253 uint* r_dst = &DY;
\r
5255 *r_dst = MASK_OUT_ABOVE_16(*r_dst) | (GET_MSB_16(*r_dst) ? 0xffff0000 : 0);
\r
5257 FLAG_N = NFLAG_32(*r_dst);
\r
5259 FLAG_V = VFLAG_CLEAR;
\r
5260 FLAG_C = CFLAG_CLEAR;
\r
5264 M68KMAKE_OP(extb, 32, ., .)
\r
5266 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
5268 uint* r_dst = &DY;
\r
5270 *r_dst = MASK_OUT_ABOVE_8(*r_dst) | (GET_MSB_8(*r_dst) ? 0xffffff00 : 0);
\r
5272 FLAG_N = NFLAG_32(*r_dst);
\r
5274 FLAG_V = VFLAG_CLEAR;
\r
5275 FLAG_C = CFLAG_CLEAR;
\r
5278 m68ki_exception_illegal();
\r
5282 M68KMAKE_OP(illegal, 0, ., .)
\r
5284 m68ki_exception_illegal();
\r
5287 M68KMAKE_OP(jmp, 32, ., .)
\r
5289 m68ki_jump(M68KMAKE_GET_EA_AY_32);
\r
5290 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
5291 if(REG_PC == REG_PPC)
\r
5296 M68KMAKE_OP(jsr, 32, ., .)
\r
5298 uint ea = M68KMAKE_GET_EA_AY_32;
\r
5299 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
5300 m68ki_push_32(REG_PC);
\r
5305 M68KMAKE_OP(lea, 32, ., .)
\r
5307 AX = M68KMAKE_GET_EA_AY_32;
\r
5311 M68KMAKE_OP(link, 16, ., a7)
\r
5314 m68ki_write_32(REG_A[7], REG_A[7]);
\r
5315 REG_A[7] = MASK_OUT_ABOVE_32(REG_A[7] + MAKE_INT_16(OPER_I_16()));
\r
5319 M68KMAKE_OP(link, 16, ., .)
\r
5321 uint* r_dst = &AY;
\r
5323 m68ki_push_32(*r_dst);
\r
5324 *r_dst = REG_A[7];
\r
5325 REG_A[7] = MASK_OUT_ABOVE_32(REG_A[7] + MAKE_INT_16(OPER_I_16()));
\r
5329 M68KMAKE_OP(link, 32, ., a7)
\r
5331 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
5334 m68ki_write_32(REG_A[7], REG_A[7]);
\r
5335 REG_A[7] = MASK_OUT_ABOVE_32(REG_A[7] + OPER_I_32());
\r
5338 m68ki_exception_illegal();
\r
5342 M68KMAKE_OP(link, 32, ., .)
\r
5344 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
5346 uint* r_dst = &AY;
\r
5348 m68ki_push_32(*r_dst);
\r
5349 *r_dst = REG_A[7];
\r
5350 REG_A[7] = MASK_OUT_ABOVE_32(REG_A[7] + OPER_I_32());
\r
5353 m68ki_exception_illegal();
\r
5357 M68KMAKE_OP(lsr, 8, s, .)
\r
5359 uint* r_dst = &DY;
\r
5360 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
\r
5361 uint src = MASK_OUT_ABOVE_8(*r_dst);
\r
5362 uint res = src >> shift;
\r
5365 USE_CYCLES(shift<<CYC_SHIFT);
\r
5367 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
\r
5369 FLAG_N = NFLAG_CLEAR;
\r
5371 FLAG_X = FLAG_C = src << (9-shift);
\r
5372 FLAG_V = VFLAG_CLEAR;
\r
5376 M68KMAKE_OP(lsr, 16, s, .)
\r
5378 uint* r_dst = &DY;
\r
5379 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
\r
5380 uint src = MASK_OUT_ABOVE_16(*r_dst);
\r
5381 uint res = src >> shift;
\r
5384 USE_CYCLES(shift<<CYC_SHIFT);
\r
5386 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
\r
5388 FLAG_N = NFLAG_CLEAR;
\r
5390 FLAG_X = FLAG_C = src << (9-shift);
\r
5391 FLAG_V = VFLAG_CLEAR;
\r
5395 M68KMAKE_OP(lsr, 32, s, .)
\r
5397 uint* r_dst = &DY;
\r
5398 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
\r
5399 uint src = *r_dst;
\r
5400 uint res = src >> shift;
\r
5403 USE_CYCLES(shift<<CYC_SHIFT);
\r
5407 FLAG_N = NFLAG_CLEAR;
\r
5409 FLAG_X = FLAG_C = src << (9-shift);
\r
5410 FLAG_V = VFLAG_CLEAR;
\r
5414 M68KMAKE_OP(lsr, 8, r, .)
\r
5416 uint* r_dst = &DY;
\r
5417 uint shift = DX & 0x3f;
\r
5418 uint src = MASK_OUT_ABOVE_8(*r_dst);
\r
5419 uint res = src >> shift;
\r
5423 USE_CYCLES(shift<<CYC_SHIFT);
\r
5427 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
\r
5428 FLAG_X = FLAG_C = src << (9-shift);
\r
5429 FLAG_N = NFLAG_CLEAR;
\r
5431 FLAG_V = VFLAG_CLEAR;
\r
5435 *r_dst &= 0xffffff00;
\r
5436 FLAG_X = XFLAG_CLEAR;
\r
5437 FLAG_C = CFLAG_CLEAR;
\r
5438 FLAG_N = NFLAG_CLEAR;
\r
5439 FLAG_Z = ZFLAG_SET;
\r
5440 FLAG_V = VFLAG_CLEAR;
\r
5444 FLAG_C = CFLAG_CLEAR;
\r
5445 FLAG_N = NFLAG_8(src);
\r
5447 FLAG_V = VFLAG_CLEAR;
\r
5451 M68KMAKE_OP(lsr, 16, r, .)
\r
5453 uint* r_dst = &DY;
\r
5454 uint shift = DX & 0x3f;
\r
5455 uint src = MASK_OUT_ABOVE_16(*r_dst);
\r
5456 uint res = src >> shift;
\r
5460 USE_CYCLES(shift<<CYC_SHIFT);
\r
5464 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
\r
5465 FLAG_C = FLAG_X = (src >> (shift - 1))<<8;
\r
5466 FLAG_N = NFLAG_CLEAR;
\r
5468 FLAG_V = VFLAG_CLEAR;
\r
5472 *r_dst &= 0xffff0000;
\r
5473 FLAG_X = XFLAG_CLEAR;
\r
5474 FLAG_C = CFLAG_CLEAR;
\r
5475 FLAG_N = NFLAG_CLEAR;
\r
5476 FLAG_Z = ZFLAG_SET;
\r
5477 FLAG_V = VFLAG_CLEAR;
\r
5481 FLAG_C = CFLAG_CLEAR;
\r
5482 FLAG_N = NFLAG_16(src);
\r
5484 FLAG_V = VFLAG_CLEAR;
\r
5488 M68KMAKE_OP(lsr, 32, r, .)
\r
5490 uint* r_dst = &DY;
\r
5491 uint shift = DX & 0x3f;
\r
5492 uint src = *r_dst;
\r
5493 uint res = src >> shift;
\r
5497 USE_CYCLES(shift<<CYC_SHIFT);
\r
5502 FLAG_C = FLAG_X = (src >> (shift - 1))<<8;
\r
5503 FLAG_N = NFLAG_CLEAR;
\r
5505 FLAG_V = VFLAG_CLEAR;
\r
5510 FLAG_X = FLAG_C = (shift == 32 ? GET_MSB_32(src)>>23 : 0);
\r
5511 FLAG_N = NFLAG_CLEAR;
\r
5512 FLAG_Z = ZFLAG_SET;
\r
5513 FLAG_V = VFLAG_CLEAR;
\r
5517 FLAG_C = CFLAG_CLEAR;
\r
5518 FLAG_N = NFLAG_32(src);
\r
5520 FLAG_V = VFLAG_CLEAR;
\r
5524 M68KMAKE_OP(lsr, 16, ., .)
\r
5526 uint ea = M68KMAKE_GET_EA_AY_16;
\r
5527 uint src = m68ki_read_16(ea);
\r
5528 uint res = src >> 1;
\r
5530 m68ki_write_16(ea, res);
\r
5532 FLAG_N = NFLAG_CLEAR;
\r
5534 FLAG_C = FLAG_X = src << 8;
\r
5535 FLAG_V = VFLAG_CLEAR;
\r
5539 M68KMAKE_OP(lsl, 8, s, .)
\r
5541 uint* r_dst = &DY;
\r
5542 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
\r
5543 uint src = MASK_OUT_ABOVE_8(*r_dst);
\r
5544 uint res = MASK_OUT_ABOVE_8(src << shift);
\r
5547 USE_CYCLES(shift<<CYC_SHIFT);
\r
5549 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
\r
5551 FLAG_N = NFLAG_8(res);
\r
5553 FLAG_X = FLAG_C = src << shift;
\r
5554 FLAG_V = VFLAG_CLEAR;
\r
5558 M68KMAKE_OP(lsl, 16, s, .)
\r
5560 uint* r_dst = &DY;
\r
5561 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
\r
5562 uint src = MASK_OUT_ABOVE_16(*r_dst);
\r
5563 uint res = MASK_OUT_ABOVE_16(src << shift);
\r
5566 USE_CYCLES(shift<<CYC_SHIFT);
\r
5568 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
\r
5570 FLAG_N = NFLAG_16(res);
\r
5572 FLAG_X = FLAG_C = src >> (8-shift);
\r
5573 FLAG_V = VFLAG_CLEAR;
\r
5577 M68KMAKE_OP(lsl, 32, s, .)
\r
5579 uint* r_dst = &DY;
\r
5580 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
\r
5581 uint src = *r_dst;
\r
5582 uint res = MASK_OUT_ABOVE_32(src << shift);
\r
5585 USE_CYCLES(shift<<CYC_SHIFT);
\r
5589 FLAG_N = NFLAG_32(res);
\r
5591 FLAG_X = FLAG_C = src >> (24-shift);
\r
5592 FLAG_V = VFLAG_CLEAR;
\r
5596 M68KMAKE_OP(lsl, 8, r, .)
\r
5598 uint* r_dst = &DY;
\r
5599 uint shift = DX & 0x3f;
\r
5600 uint src = MASK_OUT_ABOVE_8(*r_dst);
\r
5601 uint res = MASK_OUT_ABOVE_8(src << shift);
\r
5605 USE_CYCLES(shift<<CYC_SHIFT);
\r
5609 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
\r
5610 FLAG_X = FLAG_C = src << shift;
\r
5611 FLAG_N = NFLAG_8(res);
\r
5613 FLAG_V = VFLAG_CLEAR;
\r
5617 *r_dst &= 0xffffff00;
\r
5618 FLAG_X = XFLAG_CLEAR;
\r
5619 FLAG_C = CFLAG_CLEAR;
\r
5620 FLAG_N = NFLAG_CLEAR;
\r
5621 FLAG_Z = ZFLAG_SET;
\r
5622 FLAG_V = VFLAG_CLEAR;
\r
5626 FLAG_C = CFLAG_CLEAR;
\r
5627 FLAG_N = NFLAG_8(src);
\r
5629 FLAG_V = VFLAG_CLEAR;
\r
5633 M68KMAKE_OP(lsl, 16, r, .)
\r
5635 uint* r_dst = &DY;
\r
5636 uint shift = DX & 0x3f;
\r
5637 uint src = MASK_OUT_ABOVE_16(*r_dst);
\r
5638 uint res = MASK_OUT_ABOVE_16(src << shift);
\r
5642 USE_CYCLES(shift<<CYC_SHIFT);
\r
5646 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
\r
5647 FLAG_X = FLAG_C = (src << shift) >> 8;
\r
5648 FLAG_N = NFLAG_16(res);
\r
5650 FLAG_V = VFLAG_CLEAR;
\r
5654 *r_dst &= 0xffff0000;
\r
5655 FLAG_X = XFLAG_CLEAR;
\r
5656 FLAG_C = CFLAG_CLEAR;
\r
5657 FLAG_N = NFLAG_CLEAR;
\r
5658 FLAG_Z = ZFLAG_SET;
\r
5659 FLAG_V = VFLAG_CLEAR;
\r
5663 FLAG_C = CFLAG_CLEAR;
\r
5664 FLAG_N = NFLAG_16(src);
\r
5666 FLAG_V = VFLAG_CLEAR;
\r
5670 M68KMAKE_OP(lsl, 32, r, .)
\r
5672 uint* r_dst = &DY;
\r
5673 uint shift = DX & 0x3f;
\r
5674 uint src = *r_dst;
\r
5675 uint res = MASK_OUT_ABOVE_32(src << shift);
\r
5679 USE_CYCLES(shift<<CYC_SHIFT);
\r
5684 FLAG_X = FLAG_C = (src >> (32 - shift)) << 8;
\r
5685 FLAG_N = NFLAG_32(res);
\r
5687 FLAG_V = VFLAG_CLEAR;
\r
5692 FLAG_X = FLAG_C = ((shift == 32 ? src & 1 : 0))<<8;
\r
5693 FLAG_N = NFLAG_CLEAR;
\r
5694 FLAG_Z = ZFLAG_SET;
\r
5695 FLAG_V = VFLAG_CLEAR;
\r
5699 FLAG_C = CFLAG_CLEAR;
\r
5700 FLAG_N = NFLAG_32(src);
\r
5702 FLAG_V = VFLAG_CLEAR;
\r
5706 M68KMAKE_OP(lsl, 16, ., .)
\r
5708 uint ea = M68KMAKE_GET_EA_AY_16;
\r
5709 uint src = m68ki_read_16(ea);
\r
5710 uint res = MASK_OUT_ABOVE_16(src << 1);
\r
5712 m68ki_write_16(ea, res);
\r
5714 FLAG_N = NFLAG_16(res);
\r
5716 FLAG_X = FLAG_C = src >> 7;
\r
5717 FLAG_V = VFLAG_CLEAR;
\r
5721 M68KMAKE_OP(move, 8, d, d)
\r
5723 uint res = MASK_OUT_ABOVE_8(DY);
\r
5724 uint* r_dst = &DX;
\r
5726 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
\r
5728 FLAG_N = NFLAG_8(res);
\r
5730 FLAG_V = VFLAG_CLEAR;
\r
5731 FLAG_C = CFLAG_CLEAR;
\r
5735 M68KMAKE_OP(move, 8, d, .)
\r
5737 uint res = M68KMAKE_GET_OPER_AY_8;
\r
5738 uint* r_dst = &DX;
\r
5740 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
\r
5742 FLAG_N = NFLAG_8(res);
\r
5744 FLAG_V = VFLAG_CLEAR;
\r
5745 FLAG_C = CFLAG_CLEAR;
\r
5749 M68KMAKE_OP(move, 8, ai, d)
\r
5751 uint res = MASK_OUT_ABOVE_8(DY);
\r
5752 uint ea = EA_AX_AI_8();
\r
5754 m68ki_write_8(ea, res);
\r
5756 FLAG_N = NFLAG_8(res);
\r
5758 FLAG_V = VFLAG_CLEAR;
\r
5759 FLAG_C = CFLAG_CLEAR;
\r
5763 M68KMAKE_OP(move, 8, ai, .)
\r
5765 uint res = M68KMAKE_GET_OPER_AY_8;
\r
5766 uint ea = EA_AX_AI_8();
\r
5768 m68ki_write_8(ea, res);
\r
5770 FLAG_N = NFLAG_8(res);
\r
5772 FLAG_V = VFLAG_CLEAR;
\r
5773 FLAG_C = CFLAG_CLEAR;
\r
5777 M68KMAKE_OP(move, 8, pi7, d)
\r
5779 uint res = MASK_OUT_ABOVE_8(DY);
\r
5780 uint ea = EA_A7_PI_8();
\r
5782 m68ki_write_8(ea, res);
\r
5784 FLAG_N = NFLAG_8(res);
\r
5786 FLAG_V = VFLAG_CLEAR;
\r
5787 FLAG_C = CFLAG_CLEAR;
\r
5791 M68KMAKE_OP(move, 8, pi, d)
\r
5793 uint res = MASK_OUT_ABOVE_8(DY);
\r
5794 uint ea = EA_AX_PI_8();
\r
5796 m68ki_write_8(ea, res);
\r
5798 FLAG_N = NFLAG_8(res);
\r
5800 FLAG_V = VFLAG_CLEAR;
\r
5801 FLAG_C = CFLAG_CLEAR;
\r
5805 M68KMAKE_OP(move, 8, pi7, .)
\r
5807 uint res = M68KMAKE_GET_OPER_AY_8;
\r
5808 uint ea = EA_A7_PI_8();
\r
5810 m68ki_write_8(ea, res);
\r
5812 FLAG_N = NFLAG_8(res);
\r
5814 FLAG_V = VFLAG_CLEAR;
\r
5815 FLAG_C = CFLAG_CLEAR;
\r
5819 M68KMAKE_OP(move, 8, pi, .)
\r
5821 uint res = M68KMAKE_GET_OPER_AY_8;
\r
5822 uint ea = EA_AX_PI_8();
\r
5824 m68ki_write_8(ea, res);
\r
5826 FLAG_N = NFLAG_8(res);
\r
5828 FLAG_V = VFLAG_CLEAR;
\r
5829 FLAG_C = CFLAG_CLEAR;
\r
5833 M68KMAKE_OP(move, 8, pd7, d)
\r
5835 uint res = MASK_OUT_ABOVE_8(DY);
\r
5836 uint ea = EA_A7_PD_8();
\r
5838 m68ki_write_8(ea, res);
\r
5840 FLAG_N = NFLAG_8(res);
\r
5842 FLAG_V = VFLAG_CLEAR;
\r
5843 FLAG_C = CFLAG_CLEAR;
\r
5847 M68KMAKE_OP(move, 8, pd, d)
\r
5849 uint res = MASK_OUT_ABOVE_8(DY);
\r
5850 uint ea = EA_AX_PD_8();
\r
5852 m68ki_write_8(ea, res);
\r
5854 FLAG_N = NFLAG_8(res);
\r
5856 FLAG_V = VFLAG_CLEAR;
\r
5857 FLAG_C = CFLAG_CLEAR;
\r
5861 M68KMAKE_OP(move, 8, pd7, .)
\r
5863 uint res = M68KMAKE_GET_OPER_AY_8;
\r
5864 uint ea = EA_A7_PD_8();
\r
5866 m68ki_write_8(ea, res);
\r
5868 FLAG_N = NFLAG_8(res);
\r
5870 FLAG_V = VFLAG_CLEAR;
\r
5871 FLAG_C = CFLAG_CLEAR;
\r
5875 M68KMAKE_OP(move, 8, pd, .)
\r
5877 uint res = M68KMAKE_GET_OPER_AY_8;
\r
5878 uint ea = EA_AX_PD_8();
\r
5880 m68ki_write_8(ea, res);
\r
5882 FLAG_N = NFLAG_8(res);
\r
5884 FLAG_V = VFLAG_CLEAR;
\r
5885 FLAG_C = CFLAG_CLEAR;
\r
5889 M68KMAKE_OP(move, 8, di, d)
\r
5891 uint res = MASK_OUT_ABOVE_8(DY);
\r
5892 uint ea = EA_AX_DI_8();
\r
5894 m68ki_write_8(ea, res);
\r
5896 FLAG_N = NFLAG_8(res);
\r
5898 FLAG_V = VFLAG_CLEAR;
\r
5899 FLAG_C = CFLAG_CLEAR;
\r
5903 M68KMAKE_OP(move, 8, di, .)
\r
5905 uint res = M68KMAKE_GET_OPER_AY_8;
\r
5906 uint ea = EA_AX_DI_8();
\r
5908 m68ki_write_8(ea, res);
\r
5910 FLAG_N = NFLAG_8(res);
\r
5912 FLAG_V = VFLAG_CLEAR;
\r
5913 FLAG_C = CFLAG_CLEAR;
\r
5917 M68KMAKE_OP(move, 8, ix, d)
\r
5919 uint res = MASK_OUT_ABOVE_8(DY);
\r
5920 uint ea = EA_AX_IX_8();
\r
5922 m68ki_write_8(ea, res);
\r
5924 FLAG_N = NFLAG_8(res);
\r
5926 FLAG_V = VFLAG_CLEAR;
\r
5927 FLAG_C = CFLAG_CLEAR;
\r
5931 M68KMAKE_OP(move, 8, ix, .)
\r
5933 uint res = M68KMAKE_GET_OPER_AY_8;
\r
5934 uint ea = EA_AX_IX_8();
\r
5936 m68ki_write_8(ea, res);
\r
5938 FLAG_N = NFLAG_8(res);
\r
5940 FLAG_V = VFLAG_CLEAR;
\r
5941 FLAG_C = CFLAG_CLEAR;
\r
5945 M68KMAKE_OP(move, 8, aw, d)
\r
5947 uint res = MASK_OUT_ABOVE_8(DY);
\r
5948 uint ea = EA_AW_8();
\r
5950 m68ki_write_8(ea, res);
\r
5952 FLAG_N = NFLAG_8(res);
\r
5954 FLAG_V = VFLAG_CLEAR;
\r
5955 FLAG_C = CFLAG_CLEAR;
\r
5959 M68KMAKE_OP(move, 8, aw, .)
\r
5961 uint res = M68KMAKE_GET_OPER_AY_8;
\r
5962 uint ea = EA_AW_8();
\r
5964 m68ki_write_8(ea, res);
\r
5966 FLAG_N = NFLAG_8(res);
\r
5968 FLAG_V = VFLAG_CLEAR;
\r
5969 FLAG_C = CFLAG_CLEAR;
\r
5973 M68KMAKE_OP(move, 8, al, d)
\r
5975 uint res = MASK_OUT_ABOVE_8(DY);
\r
5976 uint ea = EA_AL_8();
\r
5978 m68ki_write_8(ea, res);
\r
5980 FLAG_N = NFLAG_8(res);
\r
5982 FLAG_V = VFLAG_CLEAR;
\r
5983 FLAG_C = CFLAG_CLEAR;
\r
5987 M68KMAKE_OP(move, 8, al, .)
\r
5989 uint res = M68KMAKE_GET_OPER_AY_8;
\r
5990 uint ea = EA_AL_8();
\r
5992 m68ki_write_8(ea, res);
\r
5994 FLAG_N = NFLAG_8(res);
\r
5996 FLAG_V = VFLAG_CLEAR;
\r
5997 FLAG_C = CFLAG_CLEAR;
\r
6001 M68KMAKE_OP(move, 16, d, d)
\r
6003 uint res = MASK_OUT_ABOVE_16(DY);
\r
6004 uint* r_dst = &DX;
\r
6006 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
\r
6008 FLAG_N = NFLAG_16(res);
\r
6010 FLAG_V = VFLAG_CLEAR;
\r
6011 FLAG_C = CFLAG_CLEAR;
\r
6015 M68KMAKE_OP(move, 16, d, a)
\r
6017 uint res = MASK_OUT_ABOVE_16(AY);
\r
6018 uint* r_dst = &DX;
\r
6020 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
\r
6022 FLAG_N = NFLAG_16(res);
\r
6024 FLAG_V = VFLAG_CLEAR;
\r
6025 FLAG_C = CFLAG_CLEAR;
\r
6029 M68KMAKE_OP(move, 16, d, .)
\r
6031 uint res = M68KMAKE_GET_OPER_AY_16;
\r
6032 uint* r_dst = &DX;
\r
6034 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
\r
6036 FLAG_N = NFLAG_16(res);
\r
6038 FLAG_V = VFLAG_CLEAR;
\r
6039 FLAG_C = CFLAG_CLEAR;
\r
6043 M68KMAKE_OP(move, 16, ai, d)
\r
6045 uint res = MASK_OUT_ABOVE_16(DY);
\r
6046 uint ea = EA_AX_AI_16();
\r
6048 m68ki_write_16(ea, res);
\r
6050 FLAG_N = NFLAG_16(res);
\r
6052 FLAG_V = VFLAG_CLEAR;
\r
6053 FLAG_C = CFLAG_CLEAR;
\r
6057 M68KMAKE_OP(move, 16, ai, a)
\r
6059 uint res = MASK_OUT_ABOVE_16(AY);
\r
6060 uint ea = EA_AX_AI_16();
\r
6062 m68ki_write_16(ea, res);
\r
6064 FLAG_N = NFLAG_16(res);
\r
6066 FLAG_V = VFLAG_CLEAR;
\r
6067 FLAG_C = CFLAG_CLEAR;
\r
6071 M68KMAKE_OP(move, 16, ai, .)
\r
6073 uint res = M68KMAKE_GET_OPER_AY_16;
\r
6074 uint ea = EA_AX_AI_16();
\r
6076 m68ki_write_16(ea, res);
\r
6078 FLAG_N = NFLAG_16(res);
\r
6080 FLAG_V = VFLAG_CLEAR;
\r
6081 FLAG_C = CFLAG_CLEAR;
\r
6085 M68KMAKE_OP(move, 16, pi, d)
\r
6087 uint res = MASK_OUT_ABOVE_16(DY);
\r
6088 uint ea = EA_AX_PI_16();
\r
6090 m68ki_write_16(ea, res);
\r
6092 FLAG_N = NFLAG_16(res);
\r
6094 FLAG_V = VFLAG_CLEAR;
\r
6095 FLAG_C = CFLAG_CLEAR;
\r
6099 M68KMAKE_OP(move, 16, pi, a)
\r
6101 uint res = MASK_OUT_ABOVE_16(AY);
\r
6102 uint ea = EA_AX_PI_16();
\r
6104 m68ki_write_16(ea, res);
\r
6106 FLAG_N = NFLAG_16(res);
\r
6108 FLAG_V = VFLAG_CLEAR;
\r
6109 FLAG_C = CFLAG_CLEAR;
\r
6113 M68KMAKE_OP(move, 16, pi, .)
\r
6115 uint res = M68KMAKE_GET_OPER_AY_16;
\r
6116 uint ea = EA_AX_PI_16();
\r
6118 m68ki_write_16(ea, res);
\r
6120 FLAG_N = NFLAG_16(res);
\r
6122 FLAG_V = VFLAG_CLEAR;
\r
6123 FLAG_C = CFLAG_CLEAR;
\r
6127 M68KMAKE_OP(move, 16, pd, d)
\r
6129 uint res = MASK_OUT_ABOVE_16(DY);
\r
6130 uint ea = EA_AX_PD_16();
\r
6132 m68ki_write_16(ea, res);
\r
6134 FLAG_N = NFLAG_16(res);
\r
6136 FLAG_V = VFLAG_CLEAR;
\r
6137 FLAG_C = CFLAG_CLEAR;
\r
6141 M68KMAKE_OP(move, 16, pd, a)
\r
6143 uint res = MASK_OUT_ABOVE_16(AY);
\r
6144 uint ea = EA_AX_PD_16();
\r
6146 m68ki_write_16(ea, res);
\r
6148 FLAG_N = NFLAG_16(res);
\r
6150 FLAG_V = VFLAG_CLEAR;
\r
6151 FLAG_C = CFLAG_CLEAR;
\r
6155 M68KMAKE_OP(move, 16, pd, .)
\r
6157 uint res = M68KMAKE_GET_OPER_AY_16;
\r
6158 uint ea = EA_AX_PD_16();
\r
6160 m68ki_write_16(ea, res);
\r
6162 FLAG_N = NFLAG_16(res);
\r
6164 FLAG_V = VFLAG_CLEAR;
\r
6165 FLAG_C = CFLAG_CLEAR;
\r
6169 M68KMAKE_OP(move, 16, di, d)
\r
6171 uint res = MASK_OUT_ABOVE_16(DY);
\r
6172 uint ea = EA_AX_DI_16();
\r
6174 m68ki_write_16(ea, res);
\r
6176 FLAG_N = NFLAG_16(res);
\r
6178 FLAG_V = VFLAG_CLEAR;
\r
6179 FLAG_C = CFLAG_CLEAR;
\r
6183 M68KMAKE_OP(move, 16, di, a)
\r
6185 uint res = MASK_OUT_ABOVE_16(AY);
\r
6186 uint ea = EA_AX_DI_16();
\r
6188 m68ki_write_16(ea, res);
\r
6190 FLAG_N = NFLAG_16(res);
\r
6192 FLAG_V = VFLAG_CLEAR;
\r
6193 FLAG_C = CFLAG_CLEAR;
\r
6197 M68KMAKE_OP(move, 16, di, .)
\r
6199 uint res = M68KMAKE_GET_OPER_AY_16;
\r
6200 uint ea = EA_AX_DI_16();
\r
6202 m68ki_write_16(ea, res);
\r
6204 FLAG_N = NFLAG_16(res);
\r
6206 FLAG_V = VFLAG_CLEAR;
\r
6207 FLAG_C = CFLAG_CLEAR;
\r
6211 M68KMAKE_OP(move, 16, ix, d)
\r
6213 uint res = MASK_OUT_ABOVE_16(DY);
\r
6214 uint ea = EA_AX_IX_16();
\r
6216 m68ki_write_16(ea, res);
\r
6218 FLAG_N = NFLAG_16(res);
\r
6220 FLAG_V = VFLAG_CLEAR;
\r
6221 FLAG_C = CFLAG_CLEAR;
\r
6225 M68KMAKE_OP(move, 16, ix, a)
\r
6227 uint res = MASK_OUT_ABOVE_16(AY);
\r
6228 uint ea = EA_AX_IX_16();
\r
6230 m68ki_write_16(ea, res);
\r
6232 FLAG_N = NFLAG_16(res);
\r
6234 FLAG_V = VFLAG_CLEAR;
\r
6235 FLAG_C = CFLAG_CLEAR;
\r
6239 M68KMAKE_OP(move, 16, ix, .)
\r
6241 uint res = M68KMAKE_GET_OPER_AY_16;
\r
6242 uint ea = EA_AX_IX_16();
\r
6244 m68ki_write_16(ea, res);
\r
6246 FLAG_N = NFLAG_16(res);
\r
6248 FLAG_V = VFLAG_CLEAR;
\r
6249 FLAG_C = CFLAG_CLEAR;
\r
6253 M68KMAKE_OP(move, 16, aw, d)
\r
6255 uint res = MASK_OUT_ABOVE_16(DY);
\r
6256 uint ea = EA_AW_16();
\r
6258 m68ki_write_16(ea, res);
\r
6260 FLAG_N = NFLAG_16(res);
\r
6262 FLAG_V = VFLAG_CLEAR;
\r
6263 FLAG_C = CFLAG_CLEAR;
\r
6267 M68KMAKE_OP(move, 16, aw, a)
\r
6269 uint res = MASK_OUT_ABOVE_16(AY);
\r
6270 uint ea = EA_AW_16();
\r
6272 m68ki_write_16(ea, res);
\r
6274 FLAG_N = NFLAG_16(res);
\r
6276 FLAG_V = VFLAG_CLEAR;
\r
6277 FLAG_C = CFLAG_CLEAR;
\r
6281 M68KMAKE_OP(move, 16, aw, .)
\r
6283 uint res = M68KMAKE_GET_OPER_AY_16;
\r
6284 uint ea = EA_AW_16();
\r
6286 m68ki_write_16(ea, res);
\r
6288 FLAG_N = NFLAG_16(res);
\r
6290 FLAG_V = VFLAG_CLEAR;
\r
6291 FLAG_C = CFLAG_CLEAR;
\r
6295 M68KMAKE_OP(move, 16, al, d)
\r
6297 uint res = MASK_OUT_ABOVE_16(DY);
\r
6298 uint ea = EA_AL_16();
\r
6300 m68ki_write_16(ea, res);
\r
6302 FLAG_N = NFLAG_16(res);
\r
6304 FLAG_V = VFLAG_CLEAR;
\r
6305 FLAG_C = CFLAG_CLEAR;
\r
6309 M68KMAKE_OP(move, 16, al, a)
\r
6311 uint res = MASK_OUT_ABOVE_16(AY);
\r
6312 uint ea = EA_AL_16();
\r
6314 m68ki_write_16(ea, res);
\r
6316 FLAG_N = NFLAG_16(res);
\r
6318 FLAG_V = VFLAG_CLEAR;
\r
6319 FLAG_C = CFLAG_CLEAR;
\r
6323 M68KMAKE_OP(move, 16, al, .)
\r
6325 uint res = M68KMAKE_GET_OPER_AY_16;
\r
6326 uint ea = EA_AL_16();
\r
6328 m68ki_write_16(ea, res);
\r
6330 FLAG_N = NFLAG_16(res);
\r
6332 FLAG_V = VFLAG_CLEAR;
\r
6333 FLAG_C = CFLAG_CLEAR;
\r
6337 M68KMAKE_OP(move, 32, d, d)
\r
6340 uint* r_dst = &DX;
\r
6344 FLAG_N = NFLAG_32(res);
\r
6346 FLAG_V = VFLAG_CLEAR;
\r
6347 FLAG_C = CFLAG_CLEAR;
\r
6351 M68KMAKE_OP(move, 32, d, a)
\r
6354 uint* r_dst = &DX;
\r
6358 FLAG_N = NFLAG_32(res);
\r
6360 FLAG_V = VFLAG_CLEAR;
\r
6361 FLAG_C = CFLAG_CLEAR;
\r
6365 M68KMAKE_OP(move, 32, d, .)
\r
6367 uint res = M68KMAKE_GET_OPER_AY_32;
\r
6368 uint* r_dst = &DX;
\r
6372 FLAG_N = NFLAG_32(res);
\r
6374 FLAG_V = VFLAG_CLEAR;
\r
6375 FLAG_C = CFLAG_CLEAR;
\r
6379 M68KMAKE_OP(move, 32, ai, d)
\r
6382 uint ea = EA_AX_AI_32();
\r
6384 m68ki_write_32(ea, res);
\r
6386 FLAG_N = NFLAG_32(res);
\r
6388 FLAG_V = VFLAG_CLEAR;
\r
6389 FLAG_C = CFLAG_CLEAR;
\r
6393 M68KMAKE_OP(move, 32, ai, a)
\r
6396 uint ea = EA_AX_AI_32();
\r
6398 m68ki_write_32(ea, res);
\r
6400 FLAG_N = NFLAG_32(res);
\r
6402 FLAG_V = VFLAG_CLEAR;
\r
6403 FLAG_C = CFLAG_CLEAR;
\r
6407 M68KMAKE_OP(move, 32, ai, .)
\r
6409 uint res = M68KMAKE_GET_OPER_AY_32;
\r
6410 uint ea = EA_AX_AI_32();
\r
6412 m68ki_write_32(ea, res);
\r
6414 FLAG_N = NFLAG_32(res);
\r
6416 FLAG_V = VFLAG_CLEAR;
\r
6417 FLAG_C = CFLAG_CLEAR;
\r
6421 M68KMAKE_OP(move, 32, pi, d)
\r
6424 uint ea = EA_AX_PI_32();
\r
6426 m68ki_write_32(ea, res);
\r
6428 FLAG_N = NFLAG_32(res);
\r
6430 FLAG_V = VFLAG_CLEAR;
\r
6431 FLAG_C = CFLAG_CLEAR;
\r
6435 M68KMAKE_OP(move, 32, pi, a)
\r
6438 uint ea = EA_AX_PI_32();
\r
6440 m68ki_write_32(ea, res);
\r
6442 FLAG_N = NFLAG_32(res);
\r
6444 FLAG_V = VFLAG_CLEAR;
\r
6445 FLAG_C = CFLAG_CLEAR;
\r
6449 M68KMAKE_OP(move, 32, pi, .)
\r
6451 uint res = M68KMAKE_GET_OPER_AY_32;
\r
6452 uint ea = EA_AX_PI_32();
\r
6454 m68ki_write_32(ea, res);
\r
6456 FLAG_N = NFLAG_32(res);
\r
6458 FLAG_V = VFLAG_CLEAR;
\r
6459 FLAG_C = CFLAG_CLEAR;
\r
6463 M68KMAKE_OP(move, 32, pd, d)
\r
6466 uint ea = EA_AX_PD_32();
\r
6468 m68ki_write_16(ea+2, res & 0xFFFF );
\r
6469 m68ki_write_16(ea, (res >> 16) & 0xFFFF );
\r
6471 FLAG_N = NFLAG_32(res);
\r
6473 FLAG_V = VFLAG_CLEAR;
\r
6474 FLAG_C = CFLAG_CLEAR;
\r
6478 M68KMAKE_OP(move, 32, pd, a)
\r
6481 uint ea = EA_AX_PD_32();
\r
6483 m68ki_write_16(ea+2, res & 0xFFFF );
\r
6484 m68ki_write_16(ea, (res >> 16) & 0xFFFF );
\r
6486 FLAG_N = NFLAG_32(res);
\r
6488 FLAG_V = VFLAG_CLEAR;
\r
6489 FLAG_C = CFLAG_CLEAR;
\r
6493 M68KMAKE_OP(move, 32, pd, .)
\r
6495 uint res = M68KMAKE_GET_OPER_AY_32;
\r
6496 uint ea = EA_AX_PD_32();
\r
6498 m68ki_write_16(ea+2, res & 0xFFFF );
\r
6499 m68ki_write_16(ea, (res >> 16) & 0xFFFF );
\r
6501 FLAG_N = NFLAG_32(res);
\r
6503 FLAG_V = VFLAG_CLEAR;
\r
6504 FLAG_C = CFLAG_CLEAR;
\r
6508 M68KMAKE_OP(move, 32, di, d)
\r
6511 uint ea = EA_AX_DI_32();
\r
6513 m68ki_write_32(ea, res);
\r
6515 FLAG_N = NFLAG_32(res);
\r
6517 FLAG_V = VFLAG_CLEAR;
\r
6518 FLAG_C = CFLAG_CLEAR;
\r
6522 M68KMAKE_OP(move, 32, di, a)
\r
6525 uint ea = EA_AX_DI_32();
\r
6527 m68ki_write_32(ea, res);
\r
6529 FLAG_N = NFLAG_32(res);
\r
6531 FLAG_V = VFLAG_CLEAR;
\r
6532 FLAG_C = CFLAG_CLEAR;
\r
6536 M68KMAKE_OP(move, 32, di, .)
\r
6538 uint res = M68KMAKE_GET_OPER_AY_32;
\r
6539 uint ea = EA_AX_DI_32();
\r
6541 m68ki_write_32(ea, res);
\r
6543 FLAG_N = NFLAG_32(res);
\r
6545 FLAG_V = VFLAG_CLEAR;
\r
6546 FLAG_C = CFLAG_CLEAR;
\r
6550 M68KMAKE_OP(move, 32, ix, d)
\r
6553 uint ea = EA_AX_IX_32();
\r
6555 m68ki_write_32(ea, res);
\r
6557 FLAG_N = NFLAG_32(res);
\r
6559 FLAG_V = VFLAG_CLEAR;
\r
6560 FLAG_C = CFLAG_CLEAR;
\r
6564 M68KMAKE_OP(move, 32, ix, a)
\r
6567 uint ea = EA_AX_IX_32();
\r
6569 m68ki_write_32(ea, res);
\r
6571 FLAG_N = NFLAG_32(res);
\r
6573 FLAG_V = VFLAG_CLEAR;
\r
6574 FLAG_C = CFLAG_CLEAR;
\r
6578 M68KMAKE_OP(move, 32, ix, .)
\r
6580 uint res = M68KMAKE_GET_OPER_AY_32;
\r
6581 uint ea = EA_AX_IX_32();
\r
6583 m68ki_write_32(ea, res);
\r
6585 FLAG_N = NFLAG_32(res);
\r
6587 FLAG_V = VFLAG_CLEAR;
\r
6588 FLAG_C = CFLAG_CLEAR;
\r
6592 M68KMAKE_OP(move, 32, aw, d)
\r
6595 uint ea = EA_AW_32();
\r
6597 m68ki_write_32(ea, res);
\r
6599 FLAG_N = NFLAG_32(res);
\r
6601 FLAG_V = VFLAG_CLEAR;
\r
6602 FLAG_C = CFLAG_CLEAR;
\r
6606 M68KMAKE_OP(move, 32, aw, a)
\r
6609 uint ea = EA_AW_32();
\r
6611 m68ki_write_32(ea, res);
\r
6613 FLAG_N = NFLAG_32(res);
\r
6615 FLAG_V = VFLAG_CLEAR;
\r
6616 FLAG_C = CFLAG_CLEAR;
\r
6620 M68KMAKE_OP(move, 32, aw, .)
\r
6622 uint res = M68KMAKE_GET_OPER_AY_32;
\r
6623 uint ea = EA_AW_32();
\r
6625 m68ki_write_32(ea, res);
\r
6627 FLAG_N = NFLAG_32(res);
\r
6629 FLAG_V = VFLAG_CLEAR;
\r
6630 FLAG_C = CFLAG_CLEAR;
\r
6634 M68KMAKE_OP(move, 32, al, d)
\r
6637 uint ea = EA_AL_32();
\r
6639 m68ki_write_32(ea, res);
\r
6641 FLAG_N = NFLAG_32(res);
\r
6643 FLAG_V = VFLAG_CLEAR;
\r
6644 FLAG_C = CFLAG_CLEAR;
\r
6648 M68KMAKE_OP(move, 32, al, a)
\r
6651 uint ea = EA_AL_32();
\r
6653 m68ki_write_32(ea, res);
\r
6655 FLAG_N = NFLAG_32(res);
\r
6657 FLAG_V = VFLAG_CLEAR;
\r
6658 FLAG_C = CFLAG_CLEAR;
\r
6662 M68KMAKE_OP(move, 32, al, .)
\r
6664 uint res = M68KMAKE_GET_OPER_AY_32;
\r
6665 uint ea = EA_AL_32();
\r
6667 m68ki_write_32(ea, res);
\r
6669 FLAG_N = NFLAG_32(res);
\r
6671 FLAG_V = VFLAG_CLEAR;
\r
6672 FLAG_C = CFLAG_CLEAR;
\r
6676 M68KMAKE_OP(movea, 16, ., d)
\r
6678 AX = MAKE_INT_16(DY);
\r
6682 M68KMAKE_OP(movea, 16, ., a)
\r
6684 AX = MAKE_INT_16(AY);
\r
6688 M68KMAKE_OP(movea, 16, ., .)
\r
6690 AX = MAKE_INT_16(M68KMAKE_GET_OPER_AY_16);
\r
6694 M68KMAKE_OP(movea, 32, ., d)
\r
6700 M68KMAKE_OP(movea, 32, ., a)
\r
6706 M68KMAKE_OP(movea, 32, ., .)
\r
6708 AX = M68KMAKE_GET_OPER_AY_32;
\r
6712 M68KMAKE_OP(move, 16, frc, d)
\r
6714 if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
\r
6716 DY = MASK_OUT_BELOW_16(DY) | m68ki_get_ccr();
\r
6719 m68ki_exception_illegal();
\r
6723 M68KMAKE_OP(move, 16, frc, .)
\r
6725 if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
\r
6727 m68ki_write_16(M68KMAKE_GET_EA_AY_16, m68ki_get_ccr());
\r
6730 m68ki_exception_illegal();
\r
6734 M68KMAKE_OP(move, 16, toc, d)
\r
6736 m68ki_set_ccr(DY);
\r
6740 M68KMAKE_OP(move, 16, toc, .)
\r
6742 m68ki_set_ccr(M68KMAKE_GET_OPER_AY_16);
\r
6746 M68KMAKE_OP(move, 16, frs, d)
\r
6748 if(CPU_TYPE_IS_000(CPU_TYPE) || FLAG_S) /* NS990408 */
\r
6750 DY = MASK_OUT_BELOW_16(DY) | m68ki_get_sr();
\r
6753 m68ki_exception_privilege_violation();
\r
6757 M68KMAKE_OP(move, 16, frs, .)
\r
6759 if(CPU_TYPE_IS_000(CPU_TYPE) || FLAG_S) /* NS990408 */
\r
6761 uint ea = M68KMAKE_GET_EA_AY_16;
\r
6762 m68ki_write_16(ea, m68ki_get_sr());
\r
6765 m68ki_exception_privilege_violation();
\r
6769 M68KMAKE_OP(move, 16, tos, d)
\r
6776 m68ki_exception_privilege_violation();
\r
6780 M68KMAKE_OP(move, 16, tos, .)
\r
6784 uint new_sr = M68KMAKE_GET_OPER_AY_16;
\r
6785 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
6786 m68ki_set_sr(new_sr);
\r
6789 m68ki_exception_privilege_violation();
\r
6793 M68KMAKE_OP(move, 32, fru, .)
\r
6800 m68ki_exception_privilege_violation();
\r
6804 M68KMAKE_OP(move, 32, tou, .)
\r
6808 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
6812 m68ki_exception_privilege_violation();
\r
6816 M68KMAKE_OP(movec, 32, cr, .)
\r
6818 if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
\r
6822 uint word2 = OPER_I_16();
\r
6824 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
6825 switch (word2 & 0xfff)
\r
6827 case 0x000: /* SFC */
\r
6828 REG_DA[(word2 >> 12) & 15] = REG_SFC;
\r
6830 case 0x001: /* DFC */
\r
6831 REG_DA[(word2 >> 12) & 15] = REG_DFC;
\r
6833 case 0x002: /* CACR */
\r
6834 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
6836 REG_DA[(word2 >> 12) & 15] = REG_CACR;
\r
6840 case 0x800: /* USP */
\r
6841 REG_DA[(word2 >> 12) & 15] = REG_USP;
\r
6843 case 0x801: /* VBR */
\r
6844 REG_DA[(word2 >> 12) & 15] = REG_VBR;
\r
6846 case 0x802: /* CAAR */
\r
6847 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
6849 REG_DA[(word2 >> 12) & 15] = REG_CAAR;
\r
6852 m68ki_exception_illegal();
\r
6854 case 0x803: /* MSP */
\r
6855 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
6857 REG_DA[(word2 >> 12) & 15] = FLAG_M ? REG_SP : REG_MSP;
\r
6860 m68ki_exception_illegal();
\r
6862 case 0x804: /* ISP */
\r
6863 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
6865 REG_DA[(word2 >> 12) & 15] = FLAG_M ? REG_ISP : REG_SP;
\r
6868 m68ki_exception_illegal();
\r
6870 case 0x003: /* TC */
\r
6871 if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))
\r
6876 m68ki_exception_illegal();
\r
6878 case 0x004: /* ITT0 */
\r
6879 if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))
\r
6884 m68ki_exception_illegal();
\r
6886 case 0x005: /* ITT1 */
\r
6887 if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))
\r
6892 m68ki_exception_illegal();
\r
6894 case 0x006: /* DTT0 */
\r
6895 if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))
\r
6900 m68ki_exception_illegal();
\r
6902 case 0x007: /* DTT1 */
\r
6903 if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))
\r
6908 m68ki_exception_illegal();
\r
6910 case 0x805: /* MMUSR */
\r
6911 if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))
\r
6916 m68ki_exception_illegal();
\r
6918 case 0x806: /* URP */
\r
6919 if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))
\r
6924 m68ki_exception_illegal();
\r
6926 case 0x807: /* SRP */
\r
6927 if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))
\r
6932 m68ki_exception_illegal();
\r
6935 m68ki_exception_illegal();
\r
6939 m68ki_exception_privilege_violation();
\r
6942 m68ki_exception_illegal();
\r
6946 M68KMAKE_OP(movec, 32, rc, .)
\r
6948 if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
\r
6952 uint word2 = OPER_I_16();
\r
6954 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
6955 switch (word2 & 0xfff)
\r
6957 case 0x000: /* SFC */
\r
6958 REG_SFC = REG_DA[(word2 >> 12) & 15] & 7;
\r
6960 case 0x001: /* DFC */
\r
6961 REG_DFC = REG_DA[(word2 >> 12) & 15] & 7;
\r
6963 case 0x002: /* CACR */
\r
6964 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
6966 if (CPU_TYPE_IS_040_PLUS(CPU_TYPE))
\r
6968 REG_CACR = REG_DA[(word2 >> 12) & 15];
\r
6972 /* non 68040 can only set the lower 4 bits (C,CE,F,E) */
\r
6973 REG_CACR = REG_DA[(word2 >> 12) & 15] & 0x0f;
\r
6977 m68ki_exception_illegal();
\r
6979 case 0x800: /* USP */
\r
6980 REG_USP = REG_DA[(word2 >> 12) & 15];
\r
6982 case 0x801: /* VBR */
\r
6983 REG_VBR = REG_DA[(word2 >> 12) & 15];
\r
6985 case 0x802: /* CAAR */
\r
6986 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
6988 REG_CAAR = REG_DA[(word2 >> 12) & 15];
\r
6991 m68ki_exception_illegal();
\r
6993 case 0x803: /* MSP */
\r
6994 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
6996 /* we are in supervisor mode so just check for M flag */
\r
6999 REG_MSP = REG_DA[(word2 >> 12) & 15];
\r
7002 REG_SP = REG_DA[(word2 >> 12) & 15];
\r
7005 m68ki_exception_illegal();
\r
7007 case 0x804: /* ISP */
\r
7008 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
7012 REG_SP = REG_DA[(word2 >> 12) & 15];
\r
7015 REG_ISP = REG_DA[(word2 >> 12) & 15];
\r
7018 m68ki_exception_illegal();
\r
7020 case 0x003: /* TC */
\r
7021 if (CPU_TYPE_IS_040_PLUS(CPU_TYPE))
\r
7026 m68ki_exception_illegal();
\r
7028 case 0x004: /* ITT0 */
\r
7029 if (CPU_TYPE_IS_040_PLUS(CPU_TYPE))
\r
7034 m68ki_exception_illegal();
\r
7036 case 0x005: /* ITT1 */
\r
7037 if (CPU_TYPE_IS_040_PLUS(CPU_TYPE))
\r
7042 m68ki_exception_illegal();
\r
7044 case 0x006: /* DTT0 */
\r
7045 if (CPU_TYPE_IS_040_PLUS(CPU_TYPE))
\r
7050 m68ki_exception_illegal();
\r
7052 case 0x007: /* DTT1 */
\r
7053 if (CPU_TYPE_IS_040_PLUS(CPU_TYPE))
\r
7058 m68ki_exception_illegal();
\r
7060 case 0x805: /* MMUSR */
\r
7061 if (CPU_TYPE_IS_040_PLUS(CPU_TYPE))
\r
7066 m68ki_exception_illegal();
\r
7068 case 0x806: /* URP */
\r
7069 if (CPU_TYPE_IS_040_PLUS(CPU_TYPE))
\r
7074 m68ki_exception_illegal();
\r
7076 case 0x807: /* SRP */
\r
7077 if (CPU_TYPE_IS_040_PLUS(CPU_TYPE))
\r
7082 m68ki_exception_illegal();
\r
7085 m68ki_exception_illegal();
\r
7089 m68ki_exception_privilege_violation();
\r
7092 m68ki_exception_illegal();
\r
7096 M68KMAKE_OP(movem, 16, re, pd)
\r
7099 uint register_list = OPER_I_16();
\r
7103 for(; i < 16; i++)
\r
7104 if(register_list & (1 << i))
\r
7107 m68ki_write_16(ea, MASK_OUT_ABOVE_16(REG_DA[15-i]));
\r
7112 USE_CYCLES(count<<CYC_MOVEM_W);
\r
7116 M68KMAKE_OP(movem, 16, re, .)
\r
7119 uint register_list = OPER_I_16();
\r
7120 uint ea = M68KMAKE_GET_EA_AY_16;
\r
7123 for(; i < 16; i++)
\r
7124 if(register_list & (1 << i))
\r
7126 m68ki_write_16(ea, MASK_OUT_ABOVE_16(REG_DA[i]));
\r
7131 USE_CYCLES(count<<CYC_MOVEM_W);
\r
7135 M68KMAKE_OP(movem, 32, re, pd)
\r
7138 uint register_list = OPER_I_16();
\r
7142 for(; i < 16; i++)
\r
7143 if(register_list & (1 << i))
\r
7147 m68ki_write_32(ea, REG_DA[15-i] ); // notaz Cyclone hack
\r
7149 m68ki_write_16(ea+2, REG_DA[15-i] & 0xFFFF );
\r
7150 m68ki_write_16(ea, (REG_DA[15-i] >> 16) & 0xFFFF );
\r
7156 USE_CYCLES(count<<CYC_MOVEM_L);
\r
7160 M68KMAKE_OP(movem, 32, re, .)
\r
7163 uint register_list = OPER_I_16();
\r
7164 uint ea = M68KMAKE_GET_EA_AY_32;
\r
7167 for(; i < 16; i++)
\r
7168 if(register_list & (1 << i))
\r
7170 m68ki_write_32(ea, REG_DA[i]);
\r
7175 USE_CYCLES(count<<CYC_MOVEM_L);
\r
7179 M68KMAKE_OP(movem, 16, er, pi)
\r
7182 uint register_list = OPER_I_16();
\r
7186 for(; i < 16; i++)
\r
7187 if(register_list & (1 << i))
\r
7189 REG_DA[i] = MAKE_INT_16(MASK_OUT_ABOVE_16(m68ki_read_16(ea)));
\r
7195 USE_CYCLES(count<<CYC_MOVEM_W);
\r
7199 M68KMAKE_OP(movem, 16, er, pcdi)
\r
7202 uint register_list = OPER_I_16();
\r
7203 uint ea = EA_PCDI_16();
\r
7206 for(; i < 16; i++)
\r
7207 if(register_list & (1 << i))
\r
7209 REG_DA[i] = MAKE_INT_16(MASK_OUT_ABOVE_16(m68ki_read_pcrel_16(ea)));
\r
7214 USE_CYCLES(count<<CYC_MOVEM_W);
\r
7218 M68KMAKE_OP(movem, 16, er, pcix)
\r
7221 uint register_list = OPER_I_16();
\r
7222 uint ea = EA_PCIX_16();
\r
7225 for(; i < 16; i++)
\r
7226 if(register_list & (1 << i))
\r
7228 REG_DA[i] = MAKE_INT_16(MASK_OUT_ABOVE_16(m68ki_read_pcrel_16(ea)));
\r
7233 USE_CYCLES(count<<CYC_MOVEM_W);
\r
7237 M68KMAKE_OP(movem, 16, er, .)
\r
7240 uint register_list = OPER_I_16();
\r
7241 uint ea = M68KMAKE_GET_EA_AY_16;
\r
7244 for(; i < 16; i++)
\r
7245 if(register_list & (1 << i))
\r
7247 REG_DA[i] = MAKE_INT_16(MASK_OUT_ABOVE_16(m68ki_read_16(ea)));
\r
7252 USE_CYCLES(count<<CYC_MOVEM_W);
\r
7256 M68KMAKE_OP(movem, 32, er, pi)
\r
7259 uint register_list = OPER_I_16();
\r
7263 for(; i < 16; i++)
\r
7264 if(register_list & (1 << i))
\r
7266 REG_DA[i] = m68ki_read_32(ea);
\r
7272 USE_CYCLES(count<<CYC_MOVEM_L);
\r
7276 M68KMAKE_OP(movem, 32, er, pcdi)
\r
7279 uint register_list = OPER_I_16();
\r
7280 uint ea = EA_PCDI_32();
\r
7283 for(; i < 16; i++)
\r
7284 if(register_list & (1 << i))
\r
7286 REG_DA[i] = m68ki_read_pcrel_32(ea);
\r
7291 USE_CYCLES(count<<CYC_MOVEM_L);
\r
7295 M68KMAKE_OP(movem, 32, er, pcix)
\r
7298 uint register_list = OPER_I_16();
\r
7299 uint ea = EA_PCIX_32();
\r
7302 for(; i < 16; i++)
\r
7303 if(register_list & (1 << i))
\r
7305 REG_DA[i] = m68ki_read_pcrel_32(ea);
\r
7310 USE_CYCLES(count<<CYC_MOVEM_L);
\r
7314 M68KMAKE_OP(movem, 32, er, .)
\r
7317 uint register_list = OPER_I_16();
\r
7318 uint ea = M68KMAKE_GET_EA_AY_32;
\r
7321 for(; i < 16; i++)
\r
7322 if(register_list & (1 << i))
\r
7324 REG_DA[i] = m68ki_read_32(ea);
\r
7329 USE_CYCLES(count<<CYC_MOVEM_L);
\r
7333 M68KMAKE_OP(movep, 16, re, .)
\r
7335 uint ea = EA_AY_DI_16();
\r
7338 m68ki_write_8(ea, MASK_OUT_ABOVE_8(src >> 8));
\r
7339 m68ki_write_8(ea += 2, MASK_OUT_ABOVE_8(src));
\r
7343 M68KMAKE_OP(movep, 32, re, .)
\r
7345 uint ea = EA_AY_DI_32();
\r
7348 m68ki_write_8(ea, MASK_OUT_ABOVE_8(src >> 24));
\r
7349 m68ki_write_8(ea += 2, MASK_OUT_ABOVE_8(src >> 16));
\r
7350 m68ki_write_8(ea += 2, MASK_OUT_ABOVE_8(src >> 8));
\r
7351 m68ki_write_8(ea += 2, MASK_OUT_ABOVE_8(src));
\r
7355 M68KMAKE_OP(movep, 16, er, .)
\r
7357 uint ea = EA_AY_DI_16();
\r
7358 uint* r_dst = &DX;
\r
7360 *r_dst = MASK_OUT_BELOW_16(*r_dst) | ((m68ki_read_8(ea) << 8) + m68ki_read_8(ea + 2));
\r
7364 M68KMAKE_OP(movep, 32, er, .)
\r
7366 uint ea = EA_AY_DI_32();
\r
7368 DX = (m68ki_read_8(ea) << 24) + (m68ki_read_8(ea + 2) << 16)
\r
7369 + (m68ki_read_8(ea + 4) << 8) + m68ki_read_8(ea + 6);
\r
7373 M68KMAKE_OP(moves, 8, ., .)
\r
7375 if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
\r
7379 uint word2 = OPER_I_16();
\r
7380 uint ea = M68KMAKE_GET_EA_AY_8;
\r
7382 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
7383 if(BIT_B(word2)) /* Register to memory */
\r
7385 m68ki_write_8_fc(ea, REG_DFC, MASK_OUT_ABOVE_8(REG_DA[(word2 >> 12) & 15]));
\r
7388 if(BIT_F(word2)) /* Memory to address register */
\r
7390 REG_A[(word2 >> 12) & 7] = MAKE_INT_8(m68ki_read_8_fc(ea, REG_SFC));
\r
7391 if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
\r
7395 /* Memory to data register */
\r
7396 REG_D[(word2 >> 12) & 7] = MASK_OUT_BELOW_8(REG_D[(word2 >> 12) & 7]) | m68ki_read_8_fc(ea, REG_SFC);
\r
7397 if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
\r
7401 m68ki_exception_privilege_violation();
\r
7404 m68ki_exception_illegal();
\r
7408 M68KMAKE_OP(moves, 16, ., .)
\r
7410 if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
\r
7414 uint word2 = OPER_I_16();
\r
7415 uint ea = M68KMAKE_GET_EA_AY_16;
\r
7417 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
7418 if(BIT_B(word2)) /* Register to memory */
\r
7420 m68ki_write_16_fc(ea, REG_DFC, MASK_OUT_ABOVE_16(REG_DA[(word2 >> 12) & 15]));
\r
7423 if(BIT_F(word2)) /* Memory to address register */
\r
7425 REG_A[(word2 >> 12) & 7] = MAKE_INT_16(m68ki_read_16_fc(ea, REG_SFC));
\r
7426 if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
\r
7430 /* Memory to data register */
\r
7431 REG_D[(word2 >> 12) & 7] = MASK_OUT_BELOW_16(REG_D[(word2 >> 12) & 7]) | m68ki_read_16_fc(ea, REG_SFC);
\r
7432 if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
\r
7436 m68ki_exception_privilege_violation();
\r
7439 m68ki_exception_illegal();
\r
7443 M68KMAKE_OP(moves, 32, ., .)
\r
7445 if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
\r
7449 uint word2 = OPER_I_16();
\r
7450 uint ea = M68KMAKE_GET_EA_AY_32;
\r
7452 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
7453 if(BIT_B(word2)) /* Register to memory */
\r
7455 m68ki_write_32_fc(ea, REG_DFC, REG_DA[(word2 >> 12) & 15]);
\r
7456 if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
\r
7460 /* Memory to register */
\r
7461 REG_DA[(word2 >> 12) & 15] = m68ki_read_32_fc(ea, REG_SFC);
\r
7462 if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
\r
7466 m68ki_exception_privilege_violation();
\r
7469 m68ki_exception_illegal();
\r
7473 M68KMAKE_OP(moveq, 32, ., .)
\r
7475 uint res = DX = MAKE_INT_8(MASK_OUT_ABOVE_8(REG_IR));
\r
7477 FLAG_N = NFLAG_32(res);
\r
7479 FLAG_V = VFLAG_CLEAR;
\r
7480 FLAG_C = CFLAG_CLEAR;
\r
7484 M68KMAKE_OP(move16, 32, ., .)
\r
7486 UINT16 w2 = OPER_I_16();
\r
7487 int ax = REG_IR & 7;
\r
7488 int ay = (w2 >> 12) & 7;
\r
7490 m68ki_write_32(REG_A[ay], m68ki_read_32(REG_A[ax]));
\r
7491 m68ki_write_32(REG_A[ay]+4, m68ki_read_32(REG_A[ax]+4));
\r
7492 m68ki_write_32(REG_A[ay]+8, m68ki_read_32(REG_A[ax]+8));
\r
7493 m68ki_write_32(REG_A[ay]+12, m68ki_read_32(REG_A[ax]+12));
\r
7500 M68KMAKE_OP(muls, 16, ., d)
\r
7502 uint* r_dst = &DX;
\r
7503 uint res = MASK_OUT_ABOVE_32(MAKE_INT_16(DY) * MAKE_INT_16(MASK_OUT_ABOVE_16(*r_dst)));
\r
7508 FLAG_N = NFLAG_32(res);
\r
7509 FLAG_V = VFLAG_CLEAR;
\r
7510 FLAG_C = CFLAG_CLEAR;
\r
7514 M68KMAKE_OP(muls, 16, ., .)
\r
7516 uint* r_dst = &DX;
\r
7517 uint res = MASK_OUT_ABOVE_32(MAKE_INT_16(M68KMAKE_GET_OPER_AY_16) * MAKE_INT_16(MASK_OUT_ABOVE_16(*r_dst)));
\r
7522 FLAG_N = NFLAG_32(res);
\r
7523 FLAG_V = VFLAG_CLEAR;
\r
7524 FLAG_C = CFLAG_CLEAR;
\r
7528 M68KMAKE_OP(mulu, 16, ., d)
\r
7530 uint* r_dst = &DX;
\r
7531 uint res = MASK_OUT_ABOVE_16(DY) * MASK_OUT_ABOVE_16(*r_dst);
\r
7536 FLAG_N = NFLAG_32(res);
\r
7537 FLAG_V = VFLAG_CLEAR;
\r
7538 FLAG_C = CFLAG_CLEAR;
\r
7542 M68KMAKE_OP(mulu, 16, ., .)
\r
7544 uint* r_dst = &DX;
\r
7545 uint res = M68KMAKE_GET_OPER_AY_16 * MASK_OUT_ABOVE_16(*r_dst);
\r
7550 FLAG_N = NFLAG_32(res);
\r
7551 FLAG_V = VFLAG_CLEAR;
\r
7552 FLAG_C = CFLAG_CLEAR;
\r
7556 M68KMAKE_OP(mull, 32, ., d)
\r
7558 #if M68K_USE_64_BIT
\r
7560 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
7562 uint word2 = OPER_I_16();
\r
7564 uint64 dst = REG_D[(word2 >> 12) & 7];
\r
7567 FLAG_C = CFLAG_CLEAR;
\r
7569 if(BIT_B(word2)) /* signed */
\r
7571 res = (sint64)((sint32)src) * (sint64)((sint32)dst);
\r
7574 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
7575 FLAG_N = NFLAG_32(res);
\r
7576 FLAG_V = ((sint64)res != (sint32)res)<<7;
\r
7577 REG_D[(word2 >> 12) & 7] = FLAG_Z;
\r
7580 FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32);
\r
7581 FLAG_N = NFLAG_64(res);
\r
7582 FLAG_V = VFLAG_CLEAR;
\r
7583 REG_D[word2 & 7] = (res >> 32);
\r
7584 REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res);
\r
7591 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
7592 FLAG_N = NFLAG_32(res);
\r
7593 FLAG_V = (res > 0xffffffff)<<7;
\r
7594 REG_D[(word2 >> 12) & 7] = FLAG_Z;
\r
7597 FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32);
\r
7598 FLAG_N = NFLAG_64(res);
\r
7599 FLAG_V = VFLAG_CLEAR;
\r
7600 REG_D[word2 & 7] = (res >> 32);
\r
7601 REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res);
\r
7604 m68ki_exception_illegal();
\r
7608 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
7610 uint word2 = OPER_I_16();
\r
7612 uint dst = REG_D[(word2 >> 12) & 7];
\r
7613 uint neg = GET_MSB_32(src ^ dst);
\r
7625 FLAG_C = CFLAG_CLEAR;
\r
7627 if(BIT_B(word2)) /* signed */
\r
7629 if(GET_MSB_32(src))
\r
7630 src = (uint)MASK_OUT_ABOVE_32(-(sint)src);
\r
7631 if(GET_MSB_32(dst))
\r
7632 dst = (uint)MASK_OUT_ABOVE_32(-(sint)dst);
\r
7635 src1 = MASK_OUT_ABOVE_16(src);
\r
7637 dst1 = MASK_OUT_ABOVE_16(dst);
\r
7646 lo = r1 + (MASK_OUT_ABOVE_16(r2)<<16) + (MASK_OUT_ABOVE_16(r3)<<16);
\r
7647 hi = r4 + (r2>>16) + (r3>>16) + (((r1>>16) + MASK_OUT_ABOVE_16(r2) + MASK_OUT_ABOVE_16(r3)) >> 16);
\r
7649 if(BIT_B(word2) && neg)
\r
7651 hi = (uint)MASK_OUT_ABOVE_32((-(sint)hi) - (lo != 0));
\r
7652 lo = (uint)MASK_OUT_ABOVE_32(-(sint)lo);
\r
7657 REG_D[word2 & 7] = hi;
\r
7658 REG_D[(word2 >> 12) & 7] = lo;
\r
7659 FLAG_N = NFLAG_32(hi);
\r
7661 FLAG_V = VFLAG_CLEAR;
\r
7665 REG_D[(word2 >> 12) & 7] = lo;
\r
7666 FLAG_N = NFLAG_32(lo);
\r
7669 FLAG_V = (!((GET_MSB_32(lo) && hi == 0xffffffff) || (!GET_MSB_32(lo) && !hi)))<<7;
\r
7671 FLAG_V = (hi != 0) << 7;
\r
7674 m68ki_exception_illegal();
\r
7680 M68KMAKE_OP(mull, 32, ., .)
\r
7682 #if M68K_USE_64_BIT
\r
7684 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
7686 uint word2 = OPER_I_16();
\r
7687 uint64 src = M68KMAKE_GET_OPER_AY_32;
\r
7688 uint64 dst = REG_D[(word2 >> 12) & 7];
\r
7691 FLAG_C = CFLAG_CLEAR;
\r
7693 if(BIT_B(word2)) /* signed */
\r
7695 res = (sint64)((sint32)src) * (sint64)((sint32)dst);
\r
7698 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
7699 FLAG_N = NFLAG_32(res);
\r
7700 FLAG_V = ((sint64)res != (sint32)res)<<7;
\r
7701 REG_D[(word2 >> 12) & 7] = FLAG_Z;
\r
7704 FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32);
\r
7705 FLAG_N = NFLAG_64(res);
\r
7706 FLAG_V = VFLAG_CLEAR;
\r
7707 REG_D[word2 & 7] = (res >> 32);
\r
7708 REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res);
\r
7715 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
7716 FLAG_N = NFLAG_32(res);
\r
7717 FLAG_V = (res > 0xffffffff)<<7;
\r
7718 REG_D[(word2 >> 12) & 7] = FLAG_Z;
\r
7721 FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32);
\r
7722 FLAG_N = NFLAG_64(res);
\r
7723 FLAG_V = VFLAG_CLEAR;
\r
7724 REG_D[word2 & 7] = (res >> 32);
\r
7725 REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res);
\r
7728 m68ki_exception_illegal();
\r
7732 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
7734 uint word2 = OPER_I_16();
\r
7735 uint src = M68KMAKE_GET_OPER_AY_32;
\r
7736 uint dst = REG_D[(word2 >> 12) & 7];
\r
7737 uint neg = GET_MSB_32(src ^ dst);
\r
7749 FLAG_C = CFLAG_CLEAR;
\r
7751 if(BIT_B(word2)) /* signed */
\r
7753 if(GET_MSB_32(src))
\r
7754 src = (uint)MASK_OUT_ABOVE_32(-(sint)src);
\r
7755 if(GET_MSB_32(dst))
\r
7756 dst = (uint)MASK_OUT_ABOVE_32(-(sint)dst);
\r
7759 src1 = MASK_OUT_ABOVE_16(src);
\r
7761 dst1 = MASK_OUT_ABOVE_16(dst);
\r
7770 lo = r1 + (MASK_OUT_ABOVE_16(r2)<<16) + (MASK_OUT_ABOVE_16(r3)<<16);
\r
7771 hi = r4 + (r2>>16) + (r3>>16) + (((r1>>16) + MASK_OUT_ABOVE_16(r2) + MASK_OUT_ABOVE_16(r3)) >> 16);
\r
7773 if(BIT_B(word2) && neg)
\r
7775 hi = (uint)MASK_OUT_ABOVE_32((-(sint)hi) - (lo != 0));
\r
7776 lo = (uint)MASK_OUT_ABOVE_32(-(sint)lo);
\r
7781 REG_D[word2 & 7] = hi;
\r
7782 REG_D[(word2 >> 12) & 7] = lo;
\r
7783 FLAG_N = NFLAG_32(hi);
\r
7785 FLAG_V = VFLAG_CLEAR;
\r
7789 REG_D[(word2 >> 12) & 7] = lo;
\r
7790 FLAG_N = NFLAG_32(lo);
\r
7793 FLAG_V = (!((GET_MSB_32(lo) && hi == 0xffffffff) || (!GET_MSB_32(lo) && !hi)))<<7;
\r
7795 FLAG_V = (hi != 0) << 7;
\r
7798 m68ki_exception_illegal();
\r
7804 M68KMAKE_OP(nbcd, 8, ., d)
\r
7806 uint* r_dst = &DY;
\r
7807 uint dst = MASK_OUT_ABOVE_8(*r_dst);
\r
7808 uint res = -dst - XFLAG_AS_1();
\r
7812 FLAG_V = res; /* Undefined V behavior */
\r
7814 if(((res|dst) & 0x0f) == 0)
\r
7815 res = (res & 0xf0) + 6;
\r
7817 res = MASK_OUT_ABOVE_8(res + 0x9a);
\r
7819 FLAG_V &= ~res; /* Undefined V behavior part II */
\r
7821 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
\r
7824 FLAG_C = CFLAG_SET;
\r
7825 FLAG_X = XFLAG_SET;
\r
7829 FLAG_V = VFLAG_CLEAR;
\r
7830 FLAG_C = CFLAG_CLEAR;
\r
7831 FLAG_X = XFLAG_CLEAR;
\r
7833 FLAG_N = NFLAG_8(res); /* Undefined N behavior */
\r
7837 M68KMAKE_OP(nbcd, 8, ., .)
\r
7839 uint ea = M68KMAKE_GET_EA_AY_8;
\r
7840 uint dst = m68ki_read_8(ea);
\r
7841 uint res = -dst - XFLAG_AS_1();
\r
7845 FLAG_V = res; /* Undefined V behavior */
\r
7847 if(((res|dst) & 0x0f) == 0)
\r
7848 res = (res & 0xf0) + 6;
\r
7850 res = MASK_OUT_ABOVE_8(res + 0x9a);
\r
7852 FLAG_V &= ~res; /* Undefined V behavior part II */
\r
7854 m68ki_write_8(ea, MASK_OUT_ABOVE_8(res));
\r
7857 FLAG_C = CFLAG_SET;
\r
7858 FLAG_X = XFLAG_SET;
\r
7862 FLAG_V = VFLAG_CLEAR;
\r
7863 FLAG_C = CFLAG_CLEAR;
\r
7864 FLAG_X = XFLAG_CLEAR;
\r
7866 FLAG_N = NFLAG_8(res); /* Undefined N behavior */
\r
7870 M68KMAKE_OP(neg, 8, ., d)
\r
7872 uint* r_dst = &DY;
\r
7873 uint res = 0 - MASK_OUT_ABOVE_8(*r_dst);
\r
7875 FLAG_N = NFLAG_8(res);
\r
7876 FLAG_C = FLAG_X = CFLAG_8(res);
\r
7877 FLAG_V = *r_dst & res;
\r
7878 FLAG_Z = MASK_OUT_ABOVE_8(res);
\r
7880 *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
\r
7884 M68KMAKE_OP(neg, 8, ., .)
\r
7886 uint ea = M68KMAKE_GET_EA_AY_8;
\r
7887 uint src = m68ki_read_8(ea);
\r
7888 uint res = 0 - src;
\r
7890 FLAG_N = NFLAG_8(res);
\r
7891 FLAG_C = FLAG_X = CFLAG_8(res);
\r
7892 FLAG_V = src & res;
\r
7893 FLAG_Z = MASK_OUT_ABOVE_8(res);
\r
7895 m68ki_write_8(ea, FLAG_Z);
\r
7899 M68KMAKE_OP(neg, 16, ., d)
\r
7901 uint* r_dst = &DY;
\r
7902 uint res = 0 - MASK_OUT_ABOVE_16(*r_dst);
\r
7904 FLAG_N = NFLAG_16(res);
\r
7905 FLAG_C = FLAG_X = CFLAG_16(res);
\r
7906 FLAG_V = (*r_dst & res)>>8;
\r
7907 FLAG_Z = MASK_OUT_ABOVE_16(res);
\r
7909 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
\r
7913 M68KMAKE_OP(neg, 16, ., .)
\r
7915 uint ea = M68KMAKE_GET_EA_AY_16;
\r
7916 uint src = m68ki_read_16(ea);
\r
7917 uint res = 0 - src;
\r
7919 FLAG_N = NFLAG_16(res);
\r
7920 FLAG_C = FLAG_X = CFLAG_16(res);
\r
7921 FLAG_V = (src & res)>>8;
\r
7922 FLAG_Z = MASK_OUT_ABOVE_16(res);
\r
7924 m68ki_write_16(ea, FLAG_Z);
\r
7928 M68KMAKE_OP(neg, 32, ., d)
\r
7930 uint* r_dst = &DY;
\r
7931 uint res = 0 - *r_dst;
\r
7933 FLAG_N = NFLAG_32(res);
\r
7934 FLAG_C = FLAG_X = CFLAG_SUB_32(*r_dst, 0, res);
\r
7935 FLAG_V = (*r_dst & res)>>24;
\r
7936 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
7942 M68KMAKE_OP(neg, 32, ., .)
\r
7944 uint ea = M68KMAKE_GET_EA_AY_32;
\r
7945 uint src = m68ki_read_32(ea);
\r
7946 uint res = 0 - src;
\r
7948 FLAG_N = NFLAG_32(res);
\r
7949 FLAG_C = FLAG_X = CFLAG_SUB_32(src, 0, res);
\r
7950 FLAG_V = (src & res)>>24;
\r
7951 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
7953 m68ki_write_32(ea, FLAG_Z);
\r
7957 M68KMAKE_OP(negx, 8, ., d)
\r
7959 uint* r_dst = &DY;
\r
7960 uint res = 0 - MASK_OUT_ABOVE_8(*r_dst) - XFLAG_AS_1();
\r
7962 FLAG_N = NFLAG_8(res);
\r
7963 FLAG_X = FLAG_C = CFLAG_8(res);
\r
7964 FLAG_V = *r_dst & res;
\r
7966 res = MASK_OUT_ABOVE_8(res);
\r
7969 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
\r
7973 M68KMAKE_OP(negx, 8, ., .)
\r
7975 uint ea = M68KMAKE_GET_EA_AY_8;
\r
7976 uint src = m68ki_read_8(ea);
\r
7977 uint res = 0 - src - XFLAG_AS_1();
\r
7979 FLAG_N = NFLAG_8(res);
\r
7980 FLAG_X = FLAG_C = CFLAG_8(res);
\r
7981 FLAG_V = src & res;
\r
7983 res = MASK_OUT_ABOVE_8(res);
\r
7986 m68ki_write_8(ea, res);
\r
7990 M68KMAKE_OP(negx, 16, ., d)
\r
7992 uint* r_dst = &DY;
\r
7993 uint res = 0 - MASK_OUT_ABOVE_16(*r_dst) - XFLAG_AS_1();
\r
7995 FLAG_N = NFLAG_16(res);
\r
7996 FLAG_X = FLAG_C = CFLAG_16(res);
\r
7997 FLAG_V = (*r_dst & res)>>8;
\r
7999 res = MASK_OUT_ABOVE_16(res);
\r
8002 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
\r
8006 M68KMAKE_OP(negx, 16, ., .)
\r
8008 uint ea = M68KMAKE_GET_EA_AY_16;
\r
8009 uint src = m68ki_read_16(ea);
\r
8010 uint res = 0 - MASK_OUT_ABOVE_16(src) - XFLAG_AS_1();
\r
8012 FLAG_N = NFLAG_16(res);
\r
8013 FLAG_X = FLAG_C = CFLAG_16(res);
\r
8014 FLAG_V = (src & res)>>8;
\r
8016 res = MASK_OUT_ABOVE_16(res);
\r
8019 m68ki_write_16(ea, res);
\r
8023 M68KMAKE_OP(negx, 32, ., d)
\r
8025 uint* r_dst = &DY;
\r
8026 uint res = 0 - MASK_OUT_ABOVE_32(*r_dst) - XFLAG_AS_1();
\r
8028 FLAG_N = NFLAG_32(res);
\r
8029 FLAG_X = FLAG_C = CFLAG_SUB_32(*r_dst, 0, res);
\r
8030 FLAG_V = (*r_dst & res)>>24;
\r
8032 res = MASK_OUT_ABOVE_32(res);
\r
8039 M68KMAKE_OP(negx, 32, ., .)
\r
8041 uint ea = M68KMAKE_GET_EA_AY_32;
\r
8042 uint src = m68ki_read_32(ea);
\r
8043 uint res = 0 - MASK_OUT_ABOVE_32(src) - XFLAG_AS_1();
\r
8045 FLAG_N = NFLAG_32(res);
\r
8046 FLAG_X = FLAG_C = CFLAG_SUB_32(src, 0, res);
\r
8047 FLAG_V = (src & res)>>24;
\r
8049 res = MASK_OUT_ABOVE_32(res);
\r
8052 m68ki_write_32(ea, res);
\r
8056 M68KMAKE_OP(nop, 0, ., .)
\r
8058 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
8062 M68KMAKE_OP(not, 8, ., d)
\r
8064 uint* r_dst = &DY;
\r
8065 uint res = MASK_OUT_ABOVE_8(~*r_dst);
\r
8067 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
\r
8069 FLAG_N = NFLAG_8(res);
\r
8071 FLAG_C = CFLAG_CLEAR;
\r
8072 FLAG_V = VFLAG_CLEAR;
\r
8076 M68KMAKE_OP(not, 8, ., .)
\r
8078 uint ea = M68KMAKE_GET_EA_AY_8;
\r
8079 uint res = MASK_OUT_ABOVE_8(~m68ki_read_8(ea));
\r
8081 m68ki_write_8(ea, res);
\r
8083 FLAG_N = NFLAG_8(res);
\r
8085 FLAG_C = CFLAG_CLEAR;
\r
8086 FLAG_V = VFLAG_CLEAR;
\r
8090 M68KMAKE_OP(not, 16, ., d)
\r
8092 uint* r_dst = &DY;
\r
8093 uint res = MASK_OUT_ABOVE_16(~*r_dst);
\r
8095 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
\r
8097 FLAG_N = NFLAG_16(res);
\r
8099 FLAG_C = CFLAG_CLEAR;
\r
8100 FLAG_V = VFLAG_CLEAR;
\r
8104 M68KMAKE_OP(not, 16, ., .)
\r
8106 uint ea = M68KMAKE_GET_EA_AY_16;
\r
8107 uint res = MASK_OUT_ABOVE_16(~m68ki_read_16(ea));
\r
8109 m68ki_write_16(ea, res);
\r
8111 FLAG_N = NFLAG_16(res);
\r
8113 FLAG_C = CFLAG_CLEAR;
\r
8114 FLAG_V = VFLAG_CLEAR;
\r
8118 M68KMAKE_OP(not, 32, ., d)
\r
8120 uint* r_dst = &DY;
\r
8121 uint res = *r_dst = MASK_OUT_ABOVE_32(~*r_dst);
\r
8123 FLAG_N = NFLAG_32(res);
\r
8125 FLAG_C = CFLAG_CLEAR;
\r
8126 FLAG_V = VFLAG_CLEAR;
\r
8130 M68KMAKE_OP(not, 32, ., .)
\r
8132 uint ea = M68KMAKE_GET_EA_AY_32;
\r
8133 uint res = MASK_OUT_ABOVE_32(~m68ki_read_32(ea));
\r
8135 m68ki_write_32(ea, res);
\r
8137 FLAG_N = NFLAG_32(res);
\r
8139 FLAG_C = CFLAG_CLEAR;
\r
8140 FLAG_V = VFLAG_CLEAR;
\r
8144 M68KMAKE_OP(or, 8, er, d)
\r
8146 uint res = MASK_OUT_ABOVE_8((DX |= MASK_OUT_ABOVE_8(DY)));
\r
8148 FLAG_N = NFLAG_8(res);
\r
8150 FLAG_C = CFLAG_CLEAR;
\r
8151 FLAG_V = VFLAG_CLEAR;
\r
8155 M68KMAKE_OP(or, 8, er, .)
\r
8157 uint res = MASK_OUT_ABOVE_8((DX |= M68KMAKE_GET_OPER_AY_8));
\r
8159 FLAG_N = NFLAG_8(res);
\r
8161 FLAG_C = CFLAG_CLEAR;
\r
8162 FLAG_V = VFLAG_CLEAR;
\r
8166 M68KMAKE_OP(or, 16, er, d)
\r
8168 uint res = MASK_OUT_ABOVE_16((DX |= MASK_OUT_ABOVE_16(DY)));
\r
8170 FLAG_N = NFLAG_16(res);
\r
8172 FLAG_C = CFLAG_CLEAR;
\r
8173 FLAG_V = VFLAG_CLEAR;
\r
8177 M68KMAKE_OP(or, 16, er, .)
\r
8179 uint res = MASK_OUT_ABOVE_16((DX |= M68KMAKE_GET_OPER_AY_16));
\r
8181 FLAG_N = NFLAG_16(res);
\r
8183 FLAG_C = CFLAG_CLEAR;
\r
8184 FLAG_V = VFLAG_CLEAR;
\r
8188 M68KMAKE_OP(or, 32, er, d)
\r
8190 uint res = DX |= DY;
\r
8192 FLAG_N = NFLAG_32(res);
\r
8194 FLAG_C = CFLAG_CLEAR;
\r
8195 FLAG_V = VFLAG_CLEAR;
\r
8199 M68KMAKE_OP(or, 32, er, .)
\r
8201 uint res = DX |= M68KMAKE_GET_OPER_AY_32;
\r
8203 FLAG_N = NFLAG_32(res);
\r
8205 FLAG_C = CFLAG_CLEAR;
\r
8206 FLAG_V = VFLAG_CLEAR;
\r
8210 M68KMAKE_OP(or, 8, re, .)
\r
8212 uint ea = M68KMAKE_GET_EA_AY_8;
\r
8213 uint res = MASK_OUT_ABOVE_8(DX | m68ki_read_8(ea));
\r
8215 m68ki_write_8(ea, res);
\r
8217 FLAG_N = NFLAG_8(res);
\r
8219 FLAG_C = CFLAG_CLEAR;
\r
8220 FLAG_V = VFLAG_CLEAR;
\r
8224 M68KMAKE_OP(or, 16, re, .)
\r
8226 uint ea = M68KMAKE_GET_EA_AY_16;
\r
8227 uint res = MASK_OUT_ABOVE_16(DX | m68ki_read_16(ea));
\r
8229 m68ki_write_16(ea, res);
\r
8231 FLAG_N = NFLAG_16(res);
\r
8233 FLAG_C = CFLAG_CLEAR;
\r
8234 FLAG_V = VFLAG_CLEAR;
\r
8238 M68KMAKE_OP(or, 32, re, .)
\r
8240 uint ea = M68KMAKE_GET_EA_AY_32;
\r
8241 uint res = DX | m68ki_read_32(ea);
\r
8243 m68ki_write_32(ea, res);
\r
8245 FLAG_N = NFLAG_32(res);
\r
8247 FLAG_C = CFLAG_CLEAR;
\r
8248 FLAG_V = VFLAG_CLEAR;
\r
8252 M68KMAKE_OP(ori, 8, ., d)
\r
8254 uint res = MASK_OUT_ABOVE_8((DY |= OPER_I_8()));
\r
8256 FLAG_N = NFLAG_8(res);
\r
8258 FLAG_C = CFLAG_CLEAR;
\r
8259 FLAG_V = VFLAG_CLEAR;
\r
8263 M68KMAKE_OP(ori, 8, ., .)
\r
8265 uint src = OPER_I_8();
\r
8266 uint ea = M68KMAKE_GET_EA_AY_8;
\r
8267 uint res = MASK_OUT_ABOVE_8(src | m68ki_read_8(ea));
\r
8269 m68ki_write_8(ea, res);
\r
8271 FLAG_N = NFLAG_8(res);
\r
8273 FLAG_C = CFLAG_CLEAR;
\r
8274 FLAG_V = VFLAG_CLEAR;
\r
8278 M68KMAKE_OP(ori, 16, ., d)
\r
8280 uint res = MASK_OUT_ABOVE_16(DY |= OPER_I_16());
\r
8282 FLAG_N = NFLAG_16(res);
\r
8284 FLAG_C = CFLAG_CLEAR;
\r
8285 FLAG_V = VFLAG_CLEAR;
\r
8289 M68KMAKE_OP(ori, 16, ., .)
\r
8291 uint src = OPER_I_16();
\r
8292 uint ea = M68KMAKE_GET_EA_AY_16;
\r
8293 uint res = MASK_OUT_ABOVE_16(src | m68ki_read_16(ea));
\r
8295 m68ki_write_16(ea, res);
\r
8297 FLAG_N = NFLAG_16(res);
\r
8299 FLAG_C = CFLAG_CLEAR;
\r
8300 FLAG_V = VFLAG_CLEAR;
\r
8304 M68KMAKE_OP(ori, 32, ., d)
\r
8306 uint res = DY |= OPER_I_32();
\r
8308 FLAG_N = NFLAG_32(res);
\r
8310 FLAG_C = CFLAG_CLEAR;
\r
8311 FLAG_V = VFLAG_CLEAR;
\r
8315 M68KMAKE_OP(ori, 32, ., .)
\r
8317 uint src = OPER_I_32();
\r
8318 uint ea = M68KMAKE_GET_EA_AY_32;
\r
8319 uint res = src | m68ki_read_32(ea);
\r
8321 m68ki_write_32(ea, res);
\r
8323 FLAG_N = NFLAG_32(res);
\r
8325 FLAG_C = CFLAG_CLEAR;
\r
8326 FLAG_V = VFLAG_CLEAR;
\r
8330 M68KMAKE_OP(ori, 16, toc, .)
\r
8332 m68ki_set_ccr(m68ki_get_ccr() | OPER_I_16());
\r
8336 M68KMAKE_OP(ori, 16, tos, .)
\r
8340 uint src = OPER_I_16();
\r
8341 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
8342 m68ki_set_sr(m68ki_get_sr() | src);
\r
8345 m68ki_exception_privilege_violation();
\r
8349 M68KMAKE_OP(pack, 16, rr, .)
\r
8351 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
8353 /* Note: DX and DY are reversed in Motorola's docs */
\r
8354 uint src = DY + OPER_I_16();
\r
8355 uint* r_dst = &DX;
\r
8357 *r_dst = MASK_OUT_BELOW_8(*r_dst) | ((src >> 4) & 0x00f0) | (src & 0x000f);
\r
8360 m68ki_exception_illegal();
\r
8364 M68KMAKE_OP(pack, 16, mm, ax7)
\r
8366 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
8368 /* Note: AX and AY are reversed in Motorola's docs */
\r
8369 uint ea_src = EA_AY_PD_8();
\r
8370 uint src = m68ki_read_8(ea_src);
\r
8371 ea_src = EA_AY_PD_8();
\r
8372 src = ((src << 8) | m68ki_read_8(ea_src)) + OPER_I_16();
\r
8374 m68ki_write_8(EA_A7_PD_8(), ((src >> 4) & 0x00f0) | (src & 0x000f));
\r
8377 m68ki_exception_illegal();
\r
8381 M68KMAKE_OP(pack, 16, mm, ay7)
\r
8383 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
8385 /* Note: AX and AY are reversed in Motorola's docs */
\r
8386 uint ea_src = EA_A7_PD_8();
\r
8387 uint src = m68ki_read_8(ea_src);
\r
8388 ea_src = EA_A7_PD_8();
\r
8389 src = ((src << 8) | m68ki_read_8(ea_src)) + OPER_I_16();
\r
8391 m68ki_write_8(EA_AX_PD_8(), ((src >> 4) & 0x00f0) | (src & 0x000f));
\r
8394 m68ki_exception_illegal();
\r
8398 M68KMAKE_OP(pack, 16, mm, axy7)
\r
8400 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
8402 uint ea_src = EA_A7_PD_8();
\r
8403 uint src = m68ki_read_8(ea_src);
\r
8404 ea_src = EA_A7_PD_8();
\r
8405 src = ((src << 8) | m68ki_read_8(ea_src)) + OPER_I_16();
\r
8407 m68ki_write_8(EA_A7_PD_8(), ((src >> 4) & 0x00f0) | (src & 0x000f));
\r
8410 m68ki_exception_illegal();
\r
8414 M68KMAKE_OP(pack, 16, mm, .)
\r
8416 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
8418 /* Note: AX and AY are reversed in Motorola's docs */
\r
8419 uint ea_src = EA_AY_PD_8();
\r
8420 uint src = m68ki_read_8(ea_src);
\r
8421 ea_src = EA_AY_PD_8();
\r
8422 src = ((src << 8) | m68ki_read_8(ea_src)) + OPER_I_16();
\r
8424 m68ki_write_8(EA_AX_PD_8(), ((src >> 4) & 0x00f0) | (src & 0x000f));
\r
8427 m68ki_exception_illegal();
\r
8431 M68KMAKE_OP(pea, 32, ., .)
\r
8433 uint ea = M68KMAKE_GET_EA_AY_32;
\r
8435 m68ki_push_32(ea);
\r
8439 M68KMAKE_OP(pflush, 32, ., .)
\r
8441 if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))
\r
8443 // Nothing to do, unless address translation cache is emulated
\r
8446 m68ki_exception_illegal();
\r
8450 M68KMAKE_OP(reset, 0, ., .)
\r
8454 m68ki_output_reset(); /* auto-disable (see m68kcpu.h) */
\r
8455 USE_CYCLES(CYC_RESET);
\r
8458 m68ki_exception_privilege_violation();
\r
8462 M68KMAKE_OP(ror, 8, s, .)
\r
8464 uint* r_dst = &DY;
\r
8465 uint orig_shift = (((REG_IR >> 9) - 1) & 7) + 1;
\r
8466 uint shift = orig_shift & 7;
\r
8467 uint src = MASK_OUT_ABOVE_8(*r_dst);
\r
8468 uint res = ROR_8(src, shift);
\r
8470 if(orig_shift != 0)
\r
8471 USE_CYCLES(orig_shift<<CYC_SHIFT);
\r
8473 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
\r
8475 FLAG_N = NFLAG_8(res);
\r
8477 FLAG_C = src << (9-orig_shift);
\r
8478 FLAG_V = VFLAG_CLEAR;
\r
8482 M68KMAKE_OP(ror, 16, s, .)
\r
8484 uint* r_dst = &DY;
\r
8485 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
\r
8486 uint src = MASK_OUT_ABOVE_16(*r_dst);
\r
8487 uint res = ROR_16(src, shift);
\r
8490 USE_CYCLES(shift<<CYC_SHIFT);
\r
8492 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
\r
8494 FLAG_N = NFLAG_16(res);
\r
8496 FLAG_C = src << (9-shift);
\r
8497 FLAG_V = VFLAG_CLEAR;
\r
8501 M68KMAKE_OP(ror, 32, s, .)
\r
8503 uint* r_dst = &DY;
\r
8504 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
\r
8505 uint64 src = *r_dst;
\r
8506 uint res = ROR_32(src, shift);
\r
8509 USE_CYCLES(shift<<CYC_SHIFT);
\r
8513 FLAG_N = NFLAG_32(res);
\r
8515 FLAG_C = src << (9-shift);
\r
8516 FLAG_V = VFLAG_CLEAR;
\r
8520 M68KMAKE_OP(ror, 8, r, .)
\r
8522 uint* r_dst = &DY;
\r
8523 uint orig_shift = DX & 0x3f;
\r
8524 uint shift = orig_shift & 7;
\r
8525 uint src = MASK_OUT_ABOVE_8(*r_dst);
\r
8526 uint res = ROR_8(src, shift);
\r
8528 if(orig_shift != 0)
\r
8530 USE_CYCLES(orig_shift<<CYC_SHIFT);
\r
8532 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
\r
8533 FLAG_C = src << (8-((shift-1)&7));
\r
8534 FLAG_N = NFLAG_8(res);
\r
8536 FLAG_V = VFLAG_CLEAR;
\r
8540 FLAG_C = CFLAG_CLEAR;
\r
8541 FLAG_N = NFLAG_8(src);
\r
8543 FLAG_V = VFLAG_CLEAR;
\r
8547 M68KMAKE_OP(ror, 16, r, .)
\r
8549 uint* r_dst = &DY;
\r
8550 uint orig_shift = DX & 0x3f;
\r
8551 uint shift = orig_shift & 15;
\r
8552 uint src = MASK_OUT_ABOVE_16(*r_dst);
\r
8553 uint res = ROR_16(src, shift);
\r
8555 if(orig_shift != 0)
\r
8557 USE_CYCLES(orig_shift<<CYC_SHIFT);
\r
8559 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
\r
8560 FLAG_C = (src >> ((shift - 1) & 15)) << 8;
\r
8561 FLAG_N = NFLAG_16(res);
\r
8563 FLAG_V = VFLAG_CLEAR;
\r
8567 FLAG_C = CFLAG_CLEAR;
\r
8568 FLAG_N = NFLAG_16(src);
\r
8570 FLAG_V = VFLAG_CLEAR;
\r
8574 M68KMAKE_OP(ror, 32, r, .)
\r
8576 uint* r_dst = &DY;
\r
8577 uint orig_shift = DX & 0x3f;
\r
8578 uint shift = orig_shift & 31;
\r
8579 uint64 src = *r_dst;
\r
8580 uint res = ROR_32(src, shift);
\r
8582 if(orig_shift != 0)
\r
8584 USE_CYCLES(orig_shift<<CYC_SHIFT);
\r
8587 FLAG_C = (src >> ((shift - 1) & 31)) << 8;
\r
8588 FLAG_N = NFLAG_32(res);
\r
8590 FLAG_V = VFLAG_CLEAR;
\r
8594 FLAG_C = CFLAG_CLEAR;
\r
8595 FLAG_N = NFLAG_32(src);
\r
8597 FLAG_V = VFLAG_CLEAR;
\r
8601 M68KMAKE_OP(ror, 16, ., .)
\r
8603 uint ea = M68KMAKE_GET_EA_AY_16;
\r
8604 uint src = m68ki_read_16(ea);
\r
8605 uint res = ROR_16(src, 1);
\r
8607 m68ki_write_16(ea, res);
\r
8609 FLAG_N = NFLAG_16(res);
\r
8611 FLAG_C = src << 8;
\r
8612 FLAG_V = VFLAG_CLEAR;
\r
8616 M68KMAKE_OP(rol, 8, s, .)
\r
8618 uint* r_dst = &DY;
\r
8619 uint orig_shift = (((REG_IR >> 9) - 1) & 7) + 1;
\r
8620 uint shift = orig_shift & 7;
\r
8621 uint src = MASK_OUT_ABOVE_8(*r_dst);
\r
8622 uint res = ROL_8(src, shift);
\r
8624 if(orig_shift != 0)
\r
8625 USE_CYCLES(orig_shift<<CYC_SHIFT);
\r
8627 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
\r
8629 FLAG_N = NFLAG_8(res);
\r
8631 FLAG_C = src << orig_shift;
\r
8632 FLAG_V = VFLAG_CLEAR;
\r
8636 M68KMAKE_OP(rol, 16, s, .)
\r
8638 uint* r_dst = &DY;
\r
8639 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
\r
8640 uint src = MASK_OUT_ABOVE_16(*r_dst);
\r
8641 uint res = ROL_16(src, shift);
\r
8644 USE_CYCLES(shift<<CYC_SHIFT);
\r
8646 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
\r
8648 FLAG_N = NFLAG_16(res);
\r
8650 FLAG_C = src >> (8-shift);
\r
8651 FLAG_V = VFLAG_CLEAR;
\r
8655 M68KMAKE_OP(rol, 32, s, .)
\r
8657 uint* r_dst = &DY;
\r
8658 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
\r
8659 uint64 src = *r_dst;
\r
8660 uint res = ROL_32(src, shift);
\r
8663 USE_CYCLES(shift<<CYC_SHIFT);
\r
8667 FLAG_N = NFLAG_32(res);
\r
8669 FLAG_C = src >> (24-shift);
\r
8670 FLAG_V = VFLAG_CLEAR;
\r
8674 M68KMAKE_OP(rol, 8, r, .)
\r
8676 uint* r_dst = &DY;
\r
8677 uint orig_shift = DX & 0x3f;
\r
8678 uint shift = orig_shift & 7;
\r
8679 uint src = MASK_OUT_ABOVE_8(*r_dst);
\r
8680 uint res = ROL_8(src, shift);
\r
8682 if(orig_shift != 0)
\r
8684 USE_CYCLES(orig_shift<<CYC_SHIFT);
\r
8688 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
\r
8689 FLAG_C = src << shift;
\r
8690 FLAG_N = NFLAG_8(res);
\r
8692 FLAG_V = VFLAG_CLEAR;
\r
8695 FLAG_C = (src & 1)<<8;
\r
8696 FLAG_N = NFLAG_8(src);
\r
8698 FLAG_V = VFLAG_CLEAR;
\r
8702 FLAG_C = CFLAG_CLEAR;
\r
8703 FLAG_N = NFLAG_8(src);
\r
8705 FLAG_V = VFLAG_CLEAR;
\r
8709 M68KMAKE_OP(rol, 16, r, .)
\r
8711 uint* r_dst = &DY;
\r
8712 uint orig_shift = DX & 0x3f;
\r
8713 uint shift = orig_shift & 15;
\r
8714 uint src = MASK_OUT_ABOVE_16(*r_dst);
\r
8715 uint res = MASK_OUT_ABOVE_16(ROL_16(src, shift));
\r
8717 if(orig_shift != 0)
\r
8719 USE_CYCLES(orig_shift<<CYC_SHIFT);
\r
8723 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
\r
8724 FLAG_C = (src << shift) >> 8;
\r
8725 FLAG_N = NFLAG_16(res);
\r
8727 FLAG_V = VFLAG_CLEAR;
\r
8730 FLAG_C = (src & 1)<<8;
\r
8731 FLAG_N = NFLAG_16(src);
\r
8733 FLAG_V = VFLAG_CLEAR;
\r
8737 FLAG_C = CFLAG_CLEAR;
\r
8738 FLAG_N = NFLAG_16(src);
\r
8740 FLAG_V = VFLAG_CLEAR;
\r
8744 M68KMAKE_OP(rol, 32, r, .)
\r
8746 uint* r_dst = &DY;
\r
8747 uint orig_shift = DX & 0x3f;
\r
8748 uint shift = orig_shift & 31;
\r
8749 uint64 src = *r_dst;
\r
8750 uint res = ROL_32(src, shift);
\r
8752 if(orig_shift != 0)
\r
8754 USE_CYCLES(orig_shift<<CYC_SHIFT);
\r
8758 FLAG_C = (src >> ((32 - shift) & 0x1f)) << 8;
\r
8759 FLAG_N = NFLAG_32(res);
\r
8761 FLAG_V = VFLAG_CLEAR;
\r
8765 FLAG_C = CFLAG_CLEAR;
\r
8766 FLAG_N = NFLAG_32(src);
\r
8768 FLAG_V = VFLAG_CLEAR;
\r
8772 M68KMAKE_OP(rol, 16, ., .)
\r
8774 uint ea = M68KMAKE_GET_EA_AY_16;
\r
8775 uint src = m68ki_read_16(ea);
\r
8776 uint res = MASK_OUT_ABOVE_16(ROL_16(src, 1));
\r
8778 m68ki_write_16(ea, res);
\r
8780 FLAG_N = NFLAG_16(res);
\r
8782 FLAG_C = src >> 7;
\r
8783 FLAG_V = VFLAG_CLEAR;
\r
8787 M68KMAKE_OP(roxr, 8, s, .)
\r
8789 uint* r_dst = &DY;
\r
8790 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
\r
8791 uint src = MASK_OUT_ABOVE_8(*r_dst);
\r
8792 uint res = ROR_9(src | (XFLAG_AS_1() << 8), shift);
\r
8795 USE_CYCLES(shift<<CYC_SHIFT);
\r
8797 FLAG_C = FLAG_X = res;
\r
8798 res = MASK_OUT_ABOVE_8(res);
\r
8800 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
\r
8802 FLAG_N = NFLAG_8(res);
\r
8804 FLAG_V = VFLAG_CLEAR;
\r
8808 M68KMAKE_OP(roxr, 16, s, .)
\r
8810 uint* r_dst = &DY;
\r
8811 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
\r
8812 uint src = MASK_OUT_ABOVE_16(*r_dst);
\r
8813 uint res = ROR_17(src | (XFLAG_AS_1() << 16), shift);
\r
8816 USE_CYCLES(shift<<CYC_SHIFT);
\r
8818 FLAG_C = FLAG_X = res >> 8;
\r
8819 res = MASK_OUT_ABOVE_16(res);
\r
8821 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
\r
8823 FLAG_N = NFLAG_16(res);
\r
8825 FLAG_V = VFLAG_CLEAR;
\r
8829 M68KMAKE_OP(roxr, 32, s, .)
\r
8831 #if M68K_USE_64_BIT
\r
8833 uint* r_dst = &DY;
\r
8834 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
\r
8835 uint64 src = *r_dst;
\r
8836 uint64 res = src | (((uint64)XFLAG_AS_1()) << 32);
\r
8839 USE_CYCLES(shift<<CYC_SHIFT);
\r
8841 res = ROR_33_64(res, shift);
\r
8843 FLAG_C = FLAG_X = res >> 24;
\r
8844 res = MASK_OUT_ABOVE_32(res);
\r
8848 FLAG_N = NFLAG_32(res);
\r
8850 FLAG_V = VFLAG_CLEAR;
\r
8854 uint* r_dst = &DY;
\r
8855 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
\r
8856 uint src = *r_dst;
\r
8857 uint res = MASK_OUT_ABOVE_32((ROR_33(src, shift) & ~(1 << (32 - shift))) | (XFLAG_AS_1() << (32 - shift)));
\r
8858 uint new_x_flag = src & (1 << (shift - 1));
\r
8861 USE_CYCLES(shift<<CYC_SHIFT);
\r
8865 FLAG_C = FLAG_X = (new_x_flag != 0)<<8;
\r
8866 FLAG_N = NFLAG_32(res);
\r
8868 FLAG_V = VFLAG_CLEAR;
\r
8874 M68KMAKE_OP(roxr, 8, r, .)
\r
8876 uint* r_dst = &DY;
\r
8877 uint orig_shift = DX & 0x3f;
\r
8879 if(orig_shift != 0)
\r
8881 uint shift = orig_shift % 9;
\r
8882 uint src = MASK_OUT_ABOVE_8(*r_dst);
\r
8883 uint res = ROR_9(src | (XFLAG_AS_1() << 8), shift);
\r
8885 USE_CYCLES(orig_shift<<CYC_SHIFT);
\r
8887 FLAG_C = FLAG_X = res;
\r
8888 res = MASK_OUT_ABOVE_8(res);
\r
8890 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
\r
8891 FLAG_N = NFLAG_8(res);
\r
8893 FLAG_V = VFLAG_CLEAR;
\r
8898 FLAG_N = NFLAG_8(*r_dst);
\r
8899 FLAG_Z = MASK_OUT_ABOVE_8(*r_dst);
\r
8900 FLAG_V = VFLAG_CLEAR;
\r
8904 M68KMAKE_OP(roxr, 16, r, .)
\r
8906 uint* r_dst = &DY;
\r
8907 uint orig_shift = DX & 0x3f;
\r
8909 if(orig_shift != 0)
\r
8911 uint shift = orig_shift % 17;
\r
8912 uint src = MASK_OUT_ABOVE_16(*r_dst);
\r
8913 uint res = ROR_17(src | (XFLAG_AS_1() << 16), shift);
\r
8915 USE_CYCLES(orig_shift<<CYC_SHIFT);
\r
8917 FLAG_C = FLAG_X = res >> 8;
\r
8918 res = MASK_OUT_ABOVE_16(res);
\r
8920 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
\r
8921 FLAG_N = NFLAG_16(res);
\r
8923 FLAG_V = VFLAG_CLEAR;
\r
8928 FLAG_N = NFLAG_16(*r_dst);
\r
8929 FLAG_Z = MASK_OUT_ABOVE_16(*r_dst);
\r
8930 FLAG_V = VFLAG_CLEAR;
\r
8934 M68KMAKE_OP(roxr, 32, r, .)
\r
8936 #if M68K_USE_64_BIT
\r
8938 uint* r_dst = &DY;
\r
8939 uint orig_shift = DX & 0x3f;
\r
8941 if(orig_shift != 0)
\r
8943 uint shift = orig_shift % 33;
\r
8944 uint64 src = *r_dst;
\r
8945 uint64 res = src | (((uint64)XFLAG_AS_1()) << 32);
\r
8947 res = ROR_33_64(res, shift);
\r
8949 USE_CYCLES(orig_shift<<CYC_SHIFT);
\r
8951 FLAG_C = FLAG_X = res >> 24;
\r
8952 res = MASK_OUT_ABOVE_32(res);
\r
8955 FLAG_N = NFLAG_32(res);
\r
8957 FLAG_V = VFLAG_CLEAR;
\r
8962 FLAG_N = NFLAG_32(*r_dst);
\r
8964 FLAG_V = VFLAG_CLEAR;
\r
8968 uint* r_dst = &DY;
\r
8969 uint orig_shift = DX & 0x3f;
\r
8970 uint shift = orig_shift % 33;
\r
8971 uint src = *r_dst;
\r
8972 uint res = MASK_OUT_ABOVE_32((ROR_33(src, shift) & ~(1 << (32 - shift))) | (XFLAG_AS_1() << (32 - shift)));
\r
8973 uint new_x_flag = src & (1 << (shift - 1));
\r
8975 if(orig_shift != 0)
\r
8976 USE_CYCLES(orig_shift<<CYC_SHIFT);
\r
8981 FLAG_X = (new_x_flag != 0)<<8;
\r
8986 FLAG_N = NFLAG_32(res);
\r
8988 FLAG_V = VFLAG_CLEAR;
\r
8994 M68KMAKE_OP(roxr, 16, ., .)
\r
8996 uint ea = M68KMAKE_GET_EA_AY_16;
\r
8997 uint src = m68ki_read_16(ea);
\r
8998 uint res = ROR_17(src | (XFLAG_AS_1() << 16), 1);
\r
9000 FLAG_C = FLAG_X = res >> 8;
\r
9001 res = MASK_OUT_ABOVE_16(res);
\r
9003 m68ki_write_16(ea, res);
\r
9005 FLAG_N = NFLAG_16(res);
\r
9007 FLAG_V = VFLAG_CLEAR;
\r
9011 M68KMAKE_OP(roxl, 8, s, .)
\r
9013 uint* r_dst = &DY;
\r
9014 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
\r
9015 uint src = MASK_OUT_ABOVE_8(*r_dst);
\r
9016 uint res = ROL_9(src | (XFLAG_AS_1() << 8), shift);
\r
9019 USE_CYCLES(shift<<CYC_SHIFT);
\r
9021 FLAG_C = FLAG_X = res;
\r
9022 res = MASK_OUT_ABOVE_8(res);
\r
9024 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
\r
9026 FLAG_N = NFLAG_8(res);
\r
9028 FLAG_V = VFLAG_CLEAR;
\r
9032 M68KMAKE_OP(roxl, 16, s, .)
\r
9034 uint* r_dst = &DY;
\r
9035 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
\r
9036 uint src = MASK_OUT_ABOVE_16(*r_dst);
\r
9037 uint res = ROL_17(src | (XFLAG_AS_1() << 16), shift);
\r
9040 USE_CYCLES(shift<<CYC_SHIFT);
\r
9042 FLAG_C = FLAG_X = res >> 8;
\r
9043 res = MASK_OUT_ABOVE_16(res);
\r
9045 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
\r
9047 FLAG_N = NFLAG_16(res);
\r
9049 FLAG_V = VFLAG_CLEAR;
\r
9053 M68KMAKE_OP(roxl, 32, s, .)
\r
9055 #if M68K_USE_64_BIT
\r
9057 uint* r_dst = &DY;
\r
9058 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
\r
9059 uint64 src = *r_dst;
\r
9060 uint64 res = src | (((uint64)XFLAG_AS_1()) << 32);
\r
9063 USE_CYCLES(shift<<CYC_SHIFT);
\r
9065 res = ROL_33_64(res, shift);
\r
9067 FLAG_C = FLAG_X = res >> 24;
\r
9068 res = MASK_OUT_ABOVE_32(res);
\r
9072 FLAG_N = NFLAG_32(res);
\r
9074 FLAG_V = VFLAG_CLEAR;
\r
9078 uint* r_dst = &DY;
\r
9079 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
\r
9080 uint src = *r_dst;
\r
9081 uint res = MASK_OUT_ABOVE_32((ROL_33(src, shift) & ~(1 << (shift - 1))) | (XFLAG_AS_1() << (shift - 1)));
\r
9082 uint new_x_flag = src & (1 << (32 - shift));
\r
9085 USE_CYCLES(shift<<CYC_SHIFT);
\r
9089 FLAG_C = FLAG_X = (new_x_flag != 0)<<8;
\r
9090 FLAG_N = NFLAG_32(res);
\r
9092 FLAG_V = VFLAG_CLEAR;
\r
9098 M68KMAKE_OP(roxl, 8, r, .)
\r
9100 uint* r_dst = &DY;
\r
9101 uint orig_shift = DX & 0x3f;
\r
9104 if(orig_shift != 0)
\r
9106 uint shift = orig_shift % 9;
\r
9107 uint src = MASK_OUT_ABOVE_8(*r_dst);
\r
9108 uint res = ROL_9(src | (XFLAG_AS_1() << 8), shift);
\r
9110 USE_CYCLES(orig_shift<<CYC_SHIFT);
\r
9112 FLAG_C = FLAG_X = res;
\r
9113 res = MASK_OUT_ABOVE_8(res);
\r
9115 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
\r
9116 FLAG_N = NFLAG_8(res);
\r
9118 FLAG_V = VFLAG_CLEAR;
\r
9123 FLAG_N = NFLAG_8(*r_dst);
\r
9124 FLAG_Z = MASK_OUT_ABOVE_8(*r_dst);
\r
9125 FLAG_V = VFLAG_CLEAR;
\r
9129 M68KMAKE_OP(roxl, 16, r, .)
\r
9131 uint* r_dst = &DY;
\r
9132 uint orig_shift = DX & 0x3f;
\r
9134 if(orig_shift != 0)
\r
9136 uint shift = orig_shift % 17;
\r
9137 uint src = MASK_OUT_ABOVE_16(*r_dst);
\r
9138 uint res = ROL_17(src | (XFLAG_AS_1() << 16), shift);
\r
9140 USE_CYCLES(orig_shift<<CYC_SHIFT);
\r
9142 FLAG_C = FLAG_X = res >> 8;
\r
9143 res = MASK_OUT_ABOVE_16(res);
\r
9145 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
\r
9146 FLAG_N = NFLAG_16(res);
\r
9148 FLAG_V = VFLAG_CLEAR;
\r
9153 FLAG_N = NFLAG_16(*r_dst);
\r
9154 FLAG_Z = MASK_OUT_ABOVE_16(*r_dst);
\r
9155 FLAG_V = VFLAG_CLEAR;
\r
9159 M68KMAKE_OP(roxl, 32, r, .)
\r
9161 #if M68K_USE_64_BIT
\r
9163 uint* r_dst = &DY;
\r
9164 uint orig_shift = DX & 0x3f;
\r
9166 if(orig_shift != 0)
\r
9168 uint shift = orig_shift % 33;
\r
9169 uint64 src = *r_dst;
\r
9170 uint64 res = src | (((uint64)XFLAG_AS_1()) << 32);
\r
9172 res = ROL_33_64(res, shift);
\r
9174 USE_CYCLES(orig_shift<<CYC_SHIFT);
\r
9176 FLAG_C = FLAG_X = res >> 24;
\r
9177 res = MASK_OUT_ABOVE_32(res);
\r
9180 FLAG_N = NFLAG_32(res);
\r
9182 FLAG_V = VFLAG_CLEAR;
\r
9187 FLAG_N = NFLAG_32(*r_dst);
\r
9189 FLAG_V = VFLAG_CLEAR;
\r
9193 uint* r_dst = &DY;
\r
9194 uint orig_shift = DX & 0x3f;
\r
9195 uint shift = orig_shift % 33;
\r
9196 uint src = *r_dst;
\r
9197 uint res = MASK_OUT_ABOVE_32((ROL_33(src, shift) & ~(1 << (shift - 1))) | (XFLAG_AS_1() << (shift - 1)));
\r
9198 uint new_x_flag = src & (1 << (32 - shift));
\r
9200 if(orig_shift != 0)
\r
9201 USE_CYCLES(orig_shift<<CYC_SHIFT);
\r
9206 FLAG_X = (new_x_flag != 0)<<8;
\r
9211 FLAG_N = NFLAG_32(res);
\r
9213 FLAG_V = VFLAG_CLEAR;
\r
9219 M68KMAKE_OP(roxl, 16, ., .)
\r
9221 uint ea = M68KMAKE_GET_EA_AY_16;
\r
9222 uint src = m68ki_read_16(ea);
\r
9223 uint res = ROL_17(src | (XFLAG_AS_1() << 16), 1);
\r
9225 FLAG_C = FLAG_X = res >> 8;
\r
9226 res = MASK_OUT_ABOVE_16(res);
\r
9228 m68ki_write_16(ea, res);
\r
9230 FLAG_N = NFLAG_16(res);
\r
9232 FLAG_V = VFLAG_CLEAR;
\r
9236 M68KMAKE_OP(rtd, 32, ., .)
\r
9238 if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
\r
9240 uint new_pc = m68ki_pull_32();
\r
9242 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
9243 REG_A[7] = MASK_OUT_ABOVE_32(REG_A[7] + MAKE_INT_16(OPER_I_16()));
\r
9244 m68ki_jump(new_pc);
\r
9247 m68ki_exception_illegal();
\r
9251 M68KMAKE_OP(rte, 32, ., .)
\r
9259 m68ki_rte_callback(); /* auto-disable (see m68kcpu.h) */
\r
9260 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
9262 if(CPU_TYPE_IS_000(CPU_TYPE))
\r
9264 new_sr = m68ki_pull_16();
\r
9265 new_pc = m68ki_pull_32();
\r
9266 m68ki_jump(new_pc);
\r
9267 m68ki_set_sr(new_sr);
\r
9269 CPU_INSTR_MODE = INSTRUCTION_YES;
\r
9270 CPU_RUN_MODE = RUN_MODE_NORMAL;
\r
9275 if(CPU_TYPE_IS_010(CPU_TYPE))
\r
9277 format_word = m68ki_read_16(REG_A[7]+6) >> 12;
\r
9278 if(format_word == 0)
\r
9280 new_sr = m68ki_pull_16();
\r
9281 new_pc = m68ki_pull_32();
\r
9282 m68ki_fake_pull_16(); /* format word */
\r
9283 m68ki_jump(new_pc);
\r
9284 m68ki_set_sr(new_sr);
\r
9285 CPU_INSTR_MODE = INSTRUCTION_YES;
\r
9286 CPU_RUN_MODE = RUN_MODE_NORMAL;
\r
9289 CPU_INSTR_MODE = INSTRUCTION_YES;
\r
9290 CPU_RUN_MODE = RUN_MODE_NORMAL;
\r
9291 /* Not handling bus fault (9) */
\r
9292 m68ki_exception_format_error();
\r
9296 /* Otherwise it's 020 */
\r
9298 format_word = m68ki_read_16(REG_A[7]+6) >> 12;
\r
9299 switch(format_word)
\r
9301 case 0: /* Normal */
\r
9302 new_sr = m68ki_pull_16();
\r
9303 new_pc = m68ki_pull_32();
\r
9304 m68ki_fake_pull_16(); /* format word */
\r
9305 m68ki_jump(new_pc);
\r
9306 m68ki_set_sr(new_sr);
\r
9307 CPU_INSTR_MODE = INSTRUCTION_YES;
\r
9308 CPU_RUN_MODE = RUN_MODE_NORMAL;
\r
9310 case 1: /* Throwaway */
\r
9311 new_sr = m68ki_pull_16();
\r
9312 m68ki_fake_pull_32(); /* program counter */
\r
9313 m68ki_fake_pull_16(); /* format word */
\r
9314 m68ki_set_sr_noint(new_sr);
\r
9316 case 2: /* Trap */
\r
9317 new_sr = m68ki_pull_16();
\r
9318 new_pc = m68ki_pull_32();
\r
9319 m68ki_fake_pull_16(); /* format word */
\r
9320 m68ki_fake_pull_32(); /* address */
\r
9321 m68ki_jump(new_pc);
\r
9322 m68ki_set_sr(new_sr);
\r
9323 CPU_INSTR_MODE = INSTRUCTION_YES;
\r
9324 CPU_RUN_MODE = RUN_MODE_NORMAL;
\r
9327 /* Not handling long or short bus fault */
\r
9328 CPU_INSTR_MODE = INSTRUCTION_YES;
\r
9329 CPU_RUN_MODE = RUN_MODE_NORMAL;
\r
9330 m68ki_exception_format_error();
\r
9333 m68ki_exception_privilege_violation();
\r
9337 M68KMAKE_OP(rtm, 32, ., .)
\r
9339 if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
\r
9341 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
9342 M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n",
\r
9343 m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR,
\r
9344 m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2))));
\r
9347 m68ki_exception_illegal();
\r
9351 M68KMAKE_OP(rtr, 32, ., .)
\r
9353 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
9354 m68ki_set_ccr(m68ki_pull_16());
\r
9355 m68ki_jump(m68ki_pull_32());
\r
9359 M68KMAKE_OP(rts, 32, ., .)
\r
9361 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
9362 m68ki_jump(m68ki_pull_32());
\r
9366 M68KMAKE_OP(sbcd, 8, rr, .)
\r
9368 uint* r_dst = &DX;
\r
9370 uint dst = *r_dst;
\r
9371 uint res = LOW_NIBBLE(dst) - LOW_NIBBLE(src) - XFLAG_AS_1();
\r
9376 res += HIGH_NIBBLE(dst) - HIGH_NIBBLE(src);
\r
9377 FLAG_V = res; /* Undefined V behavior */
\r
9381 FLAG_X = FLAG_C = CFLAG_SET;
\r
9383 else if(res < corf)
\r
9384 FLAG_X = FLAG_C = CFLAG_SET;
\r
9386 FLAG_X = FLAG_C = 0;
\r
9388 res = MASK_OUT_ABOVE_8(res - corf);
\r
9390 FLAG_V &= ~res; /* Undefined V behavior part II */
\r
9391 FLAG_N = NFLAG_8(res); /* Undefined N behavior */
\r
9394 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
\r
9398 M68KMAKE_OP(sbcd, 8, mm, ax7)
\r
9400 uint src = OPER_AY_PD_8();
\r
9401 uint ea = EA_A7_PD_8();
\r
9402 uint dst = m68ki_read_8(ea);
\r
9403 uint res = LOW_NIBBLE(dst) - LOW_NIBBLE(src) - XFLAG_AS_1();
\r
9408 res += HIGH_NIBBLE(dst) - HIGH_NIBBLE(src);
\r
9409 FLAG_V = res; /* Undefined V behavior */
\r
9413 FLAG_X = FLAG_C = CFLAG_SET;
\r
9415 else if(res < corf)
\r
9416 FLAG_X = FLAG_C = CFLAG_SET;
\r
9418 FLAG_X = FLAG_C = 0;
\r
9420 res = MASK_OUT_ABOVE_8(res - corf);
\r
9422 FLAG_V &= ~res; /* Undefined V behavior part II */
\r
9423 FLAG_N = NFLAG_8(res); /* Undefined N behavior */
\r
9426 m68ki_write_8(ea, res);
\r
9430 M68KMAKE_OP(sbcd, 8, mm, ay7)
\r
9432 uint src = OPER_A7_PD_8();
\r
9433 uint ea = EA_AX_PD_8();
\r
9434 uint dst = m68ki_read_8(ea);
\r
9435 uint res = LOW_NIBBLE(dst) - LOW_NIBBLE(src) - XFLAG_AS_1();
\r
9440 res += HIGH_NIBBLE(dst) - HIGH_NIBBLE(src);
\r
9441 FLAG_V = res; /* Undefined V behavior */
\r
9445 FLAG_X = FLAG_C = CFLAG_SET;
\r
9447 else if(res < corf)
\r
9448 FLAG_X = FLAG_C = CFLAG_SET;
\r
9450 FLAG_X = FLAG_C = 0;
\r
9452 res = MASK_OUT_ABOVE_8(res - corf);
\r
9454 FLAG_V &= ~res; /* Undefined V behavior part II */
\r
9455 FLAG_N = NFLAG_8(res); /* Undefined N behavior */
\r
9458 m68ki_write_8(ea, res);
\r
9462 M68KMAKE_OP(sbcd, 8, mm, axy7)
\r
9464 uint src = OPER_A7_PD_8();
\r
9465 uint ea = EA_A7_PD_8();
\r
9466 uint dst = m68ki_read_8(ea);
\r
9467 uint res = LOW_NIBBLE(dst) - LOW_NIBBLE(src) - XFLAG_AS_1();
\r
9472 res += HIGH_NIBBLE(dst) - HIGH_NIBBLE(src);
\r
9473 FLAG_V = res; /* Undefined V behavior */
\r
9477 FLAG_X = FLAG_C = CFLAG_SET;
\r
9479 else if(res < corf)
\r
9480 FLAG_X = FLAG_C = CFLAG_SET;
\r
9482 FLAG_X = FLAG_C = 0;
\r
9484 res = MASK_OUT_ABOVE_8(res - corf);
\r
9486 FLAG_V &= ~res; /* Undefined V behavior part II */
\r
9487 FLAG_N = NFLAG_8(res); /* Undefined N behavior */
\r
9490 m68ki_write_8(ea, res);
\r
9494 M68KMAKE_OP(sbcd, 8, mm, .)
\r
9496 uint src = OPER_AY_PD_8();
\r
9497 uint ea = EA_AX_PD_8();
\r
9498 uint dst = m68ki_read_8(ea);
\r
9499 uint res = LOW_NIBBLE(dst) - LOW_NIBBLE(src) - XFLAG_AS_1();
\r
9504 res += HIGH_NIBBLE(dst) - HIGH_NIBBLE(src);
\r
9505 FLAG_V = res; /* Undefined V behavior */
\r
9509 FLAG_X = FLAG_C = CFLAG_SET;
\r
9511 else if(res < corf)
\r
9512 FLAG_X = FLAG_C = CFLAG_SET;
\r
9514 FLAG_X = FLAG_C = 0;
\r
9516 res = MASK_OUT_ABOVE_8(res - corf);
\r
9518 FLAG_V &= ~res; /* Undefined V behavior part II */
\r
9519 FLAG_N = NFLAG_8(res); /* Undefined N behavior */
\r
9522 m68ki_write_8(ea, res);
\r
9526 M68KMAKE_OP(st, 8, ., d)
\r
9532 M68KMAKE_OP(st, 8, ., .)
\r
9534 m68ki_write_8(M68KMAKE_GET_EA_AY_8, 0xff);
\r
9538 M68KMAKE_OP(sf, 8, ., d)
\r
9544 M68KMAKE_OP(sf, 8, ., .)
\r
9546 m68ki_write_8(M68KMAKE_GET_EA_AY_8, 0);
\r
9550 M68KMAKE_OP(scc, 8, ., d)
\r
9555 USE_CYCLES(CYC_SCC_R_TRUE);
\r
9562 M68KMAKE_OP(scc, 8, ., .)
\r
9564 m68ki_write_8(M68KMAKE_GET_EA_AY_8, M68KMAKE_CC ? 0xff : 0);
\r
9568 M68KMAKE_OP(stop, 0, ., .)
\r
9572 uint new_sr = OPER_I_16();
\r
9573 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
9574 CPU_STOPPED |= STOP_LEVEL_STOP;
\r
9575 m68ki_set_sr(new_sr);
\r
9576 m68ki_remaining_cycles = 0;
\r
9579 m68ki_exception_privilege_violation();
\r
9583 M68KMAKE_OP(sub, 8, er, d)
\r
9585 uint* r_dst = &DX;
\r
9586 uint src = MASK_OUT_ABOVE_8(DY);
\r
9587 uint dst = MASK_OUT_ABOVE_8(*r_dst);
\r
9588 uint res = dst - src;
\r
9590 FLAG_N = NFLAG_8(res);
\r
9591 FLAG_X = FLAG_C = CFLAG_8(res);
\r
9592 FLAG_V = VFLAG_SUB_8(src, dst, res);
\r
9593 FLAG_Z = MASK_OUT_ABOVE_8(res);
\r
9595 *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
\r
9599 M68KMAKE_OP(sub, 8, er, .)
\r
9601 uint* r_dst = &DX;
\r
9602 uint src = M68KMAKE_GET_OPER_AY_8;
\r
9603 uint dst = MASK_OUT_ABOVE_8(*r_dst);
\r
9604 uint res = dst - src;
\r
9606 FLAG_N = NFLAG_8(res);
\r
9607 FLAG_X = FLAG_C = CFLAG_8(res);
\r
9608 FLAG_V = VFLAG_SUB_8(src, dst, res);
\r
9609 FLAG_Z = MASK_OUT_ABOVE_8(res);
\r
9611 *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
\r
9615 M68KMAKE_OP(sub, 16, er, d)
\r
9617 uint* r_dst = &DX;
\r
9618 uint src = MASK_OUT_ABOVE_16(DY);
\r
9619 uint dst = MASK_OUT_ABOVE_16(*r_dst);
\r
9620 uint res = dst - src;
\r
9622 FLAG_N = NFLAG_16(res);
\r
9623 FLAG_X = FLAG_C = CFLAG_16(res);
\r
9624 FLAG_V = VFLAG_SUB_16(src, dst, res);
\r
9625 FLAG_Z = MASK_OUT_ABOVE_16(res);
\r
9627 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
\r
9631 M68KMAKE_OP(sub, 16, er, a)
\r
9633 uint* r_dst = &DX;
\r
9634 uint src = MASK_OUT_ABOVE_16(AY);
\r
9635 uint dst = MASK_OUT_ABOVE_16(*r_dst);
\r
9636 uint res = dst - src;
\r
9638 FLAG_N = NFLAG_16(res);
\r
9639 FLAG_X = FLAG_C = CFLAG_16(res);
\r
9640 FLAG_V = VFLAG_SUB_16(src, dst, res);
\r
9641 FLAG_Z = MASK_OUT_ABOVE_16(res);
\r
9643 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
\r
9647 M68KMAKE_OP(sub, 16, er, .)
\r
9649 uint* r_dst = &DX;
\r
9650 uint src = M68KMAKE_GET_OPER_AY_16;
\r
9651 uint dst = MASK_OUT_ABOVE_16(*r_dst);
\r
9652 uint res = dst - src;
\r
9654 FLAG_N = NFLAG_16(res);
\r
9655 FLAG_X = FLAG_C = CFLAG_16(res);
\r
9656 FLAG_V = VFLAG_SUB_16(src, dst, res);
\r
9657 FLAG_Z = MASK_OUT_ABOVE_16(res);
\r
9659 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
\r
9663 M68KMAKE_OP(sub, 32, er, d)
\r
9665 uint* r_dst = &DX;
\r
9667 uint dst = *r_dst;
\r
9668 uint res = dst - src;
\r
9670 FLAG_N = NFLAG_32(res);
\r
9671 FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
\r
9672 FLAG_V = VFLAG_SUB_32(src, dst, res);
\r
9673 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
9679 M68KMAKE_OP(sub, 32, er, a)
\r
9681 uint* r_dst = &DX;
\r
9683 uint dst = *r_dst;
\r
9684 uint res = dst - src;
\r
9686 FLAG_N = NFLAG_32(res);
\r
9687 FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
\r
9688 FLAG_V = VFLAG_SUB_32(src, dst, res);
\r
9689 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
9695 M68KMAKE_OP(sub, 32, er, .)
\r
9697 uint* r_dst = &DX;
\r
9698 uint src = M68KMAKE_GET_OPER_AY_32;
\r
9699 uint dst = *r_dst;
\r
9700 uint res = dst - src;
\r
9702 FLAG_N = NFLAG_32(res);
\r
9703 FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
\r
9704 FLAG_V = VFLAG_SUB_32(src, dst, res);
\r
9705 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
9711 M68KMAKE_OP(sub, 8, re, .)
\r
9713 uint ea = M68KMAKE_GET_EA_AY_8;
\r
9714 uint src = MASK_OUT_ABOVE_8(DX);
\r
9715 uint dst = m68ki_read_8(ea);
\r
9716 uint res = dst - src;
\r
9718 FLAG_N = NFLAG_8(res);
\r
9719 FLAG_Z = MASK_OUT_ABOVE_8(res);
\r
9720 FLAG_X = FLAG_C = CFLAG_8(res);
\r
9721 FLAG_V = VFLAG_SUB_8(src, dst, res);
\r
9723 m68ki_write_8(ea, FLAG_Z);
\r
9727 M68KMAKE_OP(sub, 16, re, .)
\r
9729 uint ea = M68KMAKE_GET_EA_AY_16;
\r
9730 uint src = MASK_OUT_ABOVE_16(DX);
\r
9731 uint dst = m68ki_read_16(ea);
\r
9732 uint res = dst - src;
\r
9734 FLAG_N = NFLAG_16(res);
\r
9735 FLAG_Z = MASK_OUT_ABOVE_16(res);
\r
9736 FLAG_X = FLAG_C = CFLAG_16(res);
\r
9737 FLAG_V = VFLAG_SUB_16(src, dst, res);
\r
9739 m68ki_write_16(ea, FLAG_Z);
\r
9743 M68KMAKE_OP(sub, 32, re, .)
\r
9745 uint ea = M68KMAKE_GET_EA_AY_32;
\r
9747 uint dst = m68ki_read_32(ea);
\r
9748 uint res = dst - src;
\r
9750 FLAG_N = NFLAG_32(res);
\r
9751 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
9752 FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
\r
9753 FLAG_V = VFLAG_SUB_32(src, dst, res);
\r
9755 m68ki_write_32(ea, FLAG_Z);
\r
9759 M68KMAKE_OP(suba, 16, ., d)
\r
9761 uint* r_dst = &AX;
\r
9763 *r_dst = MASK_OUT_ABOVE_32(*r_dst - MAKE_INT_16(DY));
\r
9767 M68KMAKE_OP(suba, 16, ., a)
\r
9769 uint* r_dst = &AX;
\r
9771 *r_dst = MASK_OUT_ABOVE_32(*r_dst - MAKE_INT_16(AY));
\r
9775 M68KMAKE_OP(suba, 16, ., .)
\r
9777 uint* r_dst = &AX;
\r
9778 uint src = MAKE_INT_16(M68KMAKE_GET_OPER_AY_16);
\r
9780 *r_dst = MASK_OUT_ABOVE_32(*r_dst - src);
\r
9784 M68KMAKE_OP(suba, 32, ., d)
\r
9786 uint* r_dst = &AX;
\r
9788 *r_dst = MASK_OUT_ABOVE_32(*r_dst - DY);
\r
9792 M68KMAKE_OP(suba, 32, ., a)
\r
9794 uint* r_dst = &AX;
\r
9796 *r_dst = MASK_OUT_ABOVE_32(*r_dst - AY);
\r
9800 M68KMAKE_OP(suba, 32, ., .)
\r
9802 uint* r_dst = &AX;
\r
9803 uint src = M68KMAKE_GET_OPER_AY_32; // notaz
\r
9805 *r_dst = MASK_OUT_ABOVE_32(*r_dst - src);
\r
9809 M68KMAKE_OP(subi, 8, ., d)
\r
9811 uint* r_dst = &DY;
\r
9812 uint src = OPER_I_8();
\r
9813 uint dst = MASK_OUT_ABOVE_8(*r_dst);
\r
9814 uint res = dst - src;
\r
9816 FLAG_N = NFLAG_8(res);
\r
9817 FLAG_Z = MASK_OUT_ABOVE_8(res);
\r
9818 FLAG_X = FLAG_C = CFLAG_8(res);
\r
9819 FLAG_V = VFLAG_SUB_8(src, dst, res);
\r
9821 *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
\r
9825 M68KMAKE_OP(subi, 8, ., .)
\r
9827 uint src = OPER_I_8();
\r
9828 uint ea = M68KMAKE_GET_EA_AY_8;
\r
9829 uint dst = m68ki_read_8(ea);
\r
9830 uint res = dst - src;
\r
9832 FLAG_N = NFLAG_8(res);
\r
9833 FLAG_Z = MASK_OUT_ABOVE_8(res);
\r
9834 FLAG_X = FLAG_C = CFLAG_8(res);
\r
9835 FLAG_V = VFLAG_SUB_8(src, dst, res);
\r
9837 m68ki_write_8(ea, FLAG_Z);
\r
9841 M68KMAKE_OP(subi, 16, ., d)
\r
9843 uint* r_dst = &DY;
\r
9844 uint src = OPER_I_16();
\r
9845 uint dst = MASK_OUT_ABOVE_16(*r_dst);
\r
9846 uint res = dst - src;
\r
9848 FLAG_N = NFLAG_16(res);
\r
9849 FLAG_Z = MASK_OUT_ABOVE_16(res);
\r
9850 FLAG_X = FLAG_C = CFLAG_16(res);
\r
9851 FLAG_V = VFLAG_SUB_16(src, dst, res);
\r
9853 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
\r
9857 M68KMAKE_OP(subi, 16, ., .)
\r
9859 uint src = OPER_I_16();
\r
9860 uint ea = M68KMAKE_GET_EA_AY_16;
\r
9861 uint dst = m68ki_read_16(ea);
\r
9862 uint res = dst - src;
\r
9864 FLAG_N = NFLAG_16(res);
\r
9865 FLAG_Z = MASK_OUT_ABOVE_16(res);
\r
9866 FLAG_X = FLAG_C = CFLAG_16(res);
\r
9867 FLAG_V = VFLAG_SUB_16(src, dst, res);
\r
9869 m68ki_write_16(ea, FLAG_Z);
\r
9873 M68KMAKE_OP(subi, 32, ., d)
\r
9875 uint* r_dst = &DY;
\r
9876 uint src = OPER_I_32();
\r
9877 uint dst = *r_dst;
\r
9878 uint res = dst - src;
\r
9880 FLAG_N = NFLAG_32(res);
\r
9881 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
9882 FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
\r
9883 FLAG_V = VFLAG_SUB_32(src, dst, res);
\r
9889 M68KMAKE_OP(subi, 32, ., .)
\r
9891 uint src = OPER_I_32();
\r
9892 uint ea = M68KMAKE_GET_EA_AY_32;
\r
9893 uint dst = m68ki_read_32(ea);
\r
9894 uint res = dst - src;
\r
9896 FLAG_N = NFLAG_32(res);
\r
9897 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
9898 FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
\r
9899 FLAG_V = VFLAG_SUB_32(src, dst, res);
\r
9901 m68ki_write_32(ea, FLAG_Z);
\r
9905 M68KMAKE_OP(subq, 8, ., d)
\r
9907 uint* r_dst = &DY;
\r
9908 uint src = (((REG_IR >> 9) - 1) & 7) + 1;
\r
9909 uint dst = MASK_OUT_ABOVE_8(*r_dst);
\r
9910 uint res = dst - src;
\r
9912 FLAG_N = NFLAG_8(res);
\r
9913 FLAG_Z = MASK_OUT_ABOVE_8(res);
\r
9914 FLAG_X = FLAG_C = CFLAG_8(res);
\r
9915 FLAG_V = VFLAG_SUB_8(src, dst, res);
\r
9917 *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
\r
9921 M68KMAKE_OP(subq, 8, ., .)
\r
9923 uint src = (((REG_IR >> 9) - 1) & 7) + 1;
\r
9924 uint ea = M68KMAKE_GET_EA_AY_8;
\r
9925 uint dst = m68ki_read_8(ea);
\r
9926 uint res = dst - src;
\r
9928 FLAG_N = NFLAG_8(res);
\r
9929 FLAG_Z = MASK_OUT_ABOVE_8(res);
\r
9930 FLAG_X = FLAG_C = CFLAG_8(res);
\r
9931 FLAG_V = VFLAG_SUB_8(src, dst, res);
\r
9933 m68ki_write_8(ea, FLAG_Z);
\r
9937 M68KMAKE_OP(subq, 16, ., d)
\r
9939 uint* r_dst = &DY;
\r
9940 uint src = (((REG_IR >> 9) - 1) & 7) + 1;
\r
9941 uint dst = MASK_OUT_ABOVE_16(*r_dst);
\r
9942 uint res = dst - src;
\r
9944 FLAG_N = NFLAG_16(res);
\r
9945 FLAG_Z = MASK_OUT_ABOVE_16(res);
\r
9946 FLAG_X = FLAG_C = CFLAG_16(res);
\r
9947 FLAG_V = VFLAG_SUB_16(src, dst, res);
\r
9949 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
\r
9953 M68KMAKE_OP(subq, 16, ., a)
\r
9955 uint* r_dst = &AY;
\r
9957 *r_dst = MASK_OUT_ABOVE_32(*r_dst - ((((REG_IR >> 9) - 1) & 7) + 1));
\r
9961 M68KMAKE_OP(subq, 16, ., .)
\r
9963 uint src = (((REG_IR >> 9) - 1) & 7) + 1;
\r
9964 uint ea = M68KMAKE_GET_EA_AY_16;
\r
9965 uint dst = m68ki_read_16(ea);
\r
9966 uint res = dst - src;
\r
9968 FLAG_N = NFLAG_16(res);
\r
9969 FLAG_Z = MASK_OUT_ABOVE_16(res);
\r
9970 FLAG_X = FLAG_C = CFLAG_16(res);
\r
9971 FLAG_V = VFLAG_SUB_16(src, dst, res);
\r
9973 m68ki_write_16(ea, FLAG_Z);
\r
9977 M68KMAKE_OP(subq, 32, ., d)
\r
9979 uint* r_dst = &DY;
\r
9980 uint src = (((REG_IR >> 9) - 1) & 7) + 1;
\r
9981 uint dst = *r_dst;
\r
9982 uint res = dst - src;
\r
9984 FLAG_N = NFLAG_32(res);
\r
9985 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
9986 FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
\r
9987 FLAG_V = VFLAG_SUB_32(src, dst, res);
\r
9993 M68KMAKE_OP(subq, 32, ., a)
\r
9995 uint* r_dst = &AY;
\r
9997 *r_dst = MASK_OUT_ABOVE_32(*r_dst - ((((REG_IR >> 9) - 1) & 7) + 1));
\r
10001 M68KMAKE_OP(subq, 32, ., .)
\r
10003 uint src = (((REG_IR >> 9) - 1) & 7) + 1;
\r
10004 uint ea = M68KMAKE_GET_EA_AY_32;
\r
10005 uint dst = m68ki_read_32(ea);
\r
10006 uint res = dst - src;
\r
10008 FLAG_N = NFLAG_32(res);
\r
10009 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
10010 FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
\r
10011 FLAG_V = VFLAG_SUB_32(src, dst, res);
\r
10013 m68ki_write_32(ea, FLAG_Z);
\r
10017 M68KMAKE_OP(subx, 8, rr, .)
\r
10019 uint* r_dst = &DX;
\r
10020 uint src = MASK_OUT_ABOVE_8(DY);
\r
10021 uint dst = MASK_OUT_ABOVE_8(*r_dst);
\r
10022 uint res = dst - src - XFLAG_AS_1();
\r
10024 FLAG_N = NFLAG_8(res);
\r
10025 FLAG_X = FLAG_C = CFLAG_8(res);
\r
10026 FLAG_V = VFLAG_SUB_8(src, dst, res);
\r
10028 res = MASK_OUT_ABOVE_8(res);
\r
10031 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
\r
10035 M68KMAKE_OP(subx, 16, rr, .)
\r
10037 uint* r_dst = &DX;
\r
10038 uint src = MASK_OUT_ABOVE_16(DY);
\r
10039 uint dst = MASK_OUT_ABOVE_16(*r_dst);
\r
10040 uint res = dst - src - XFLAG_AS_1();
\r
10042 FLAG_N = NFLAG_16(res);
\r
10043 FLAG_X = FLAG_C = CFLAG_16(res);
\r
10044 FLAG_V = VFLAG_SUB_16(src, dst, res);
\r
10046 res = MASK_OUT_ABOVE_16(res);
\r
10049 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
\r
10053 M68KMAKE_OP(subx, 32, rr, .)
\r
10055 uint* r_dst = &DX;
\r
10057 uint dst = *r_dst;
\r
10058 uint res = dst - src - XFLAG_AS_1();
\r
10060 FLAG_N = NFLAG_32(res);
\r
10061 FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
\r
10062 FLAG_V = VFLAG_SUB_32(src, dst, res);
\r
10064 res = MASK_OUT_ABOVE_32(res);
\r
10071 M68KMAKE_OP(subx, 8, mm, ax7)
\r
10073 uint src = OPER_AY_PD_8();
\r
10074 uint ea = EA_A7_PD_8();
\r
10075 uint dst = m68ki_read_8(ea);
\r
10076 uint res = dst - src - XFLAG_AS_1();
\r
10078 FLAG_N = NFLAG_8(res);
\r
10079 FLAG_X = FLAG_C = CFLAG_8(res);
\r
10080 FLAG_V = VFLAG_SUB_8(src, dst, res);
\r
10082 res = MASK_OUT_ABOVE_8(res);
\r
10085 m68ki_write_8(ea, res);
\r
10089 M68KMAKE_OP(subx, 8, mm, ay7)
\r
10091 uint src = OPER_A7_PD_8();
\r
10092 uint ea = EA_AX_PD_8();
\r
10093 uint dst = m68ki_read_8(ea);
\r
10094 uint res = dst - src - XFLAG_AS_1();
\r
10096 FLAG_N = NFLAG_8(res);
\r
10097 FLAG_X = FLAG_C = CFLAG_8(res);
\r
10098 FLAG_V = VFLAG_SUB_8(src, dst, res);
\r
10100 res = MASK_OUT_ABOVE_8(res);
\r
10103 m68ki_write_8(ea, res);
\r
10107 M68KMAKE_OP(subx, 8, mm, axy7)
\r
10109 uint src = OPER_A7_PD_8();
\r
10110 uint ea = EA_A7_PD_8();
\r
10111 uint dst = m68ki_read_8(ea);
\r
10112 uint res = dst - src - XFLAG_AS_1();
\r
10114 FLAG_N = NFLAG_8(res);
\r
10115 FLAG_X = FLAG_C = CFLAG_8(res);
\r
10116 FLAG_V = VFLAG_SUB_8(src, dst, res);
\r
10118 res = MASK_OUT_ABOVE_8(res);
\r
10121 m68ki_write_8(ea, res);
\r
10125 M68KMAKE_OP(subx, 8, mm, .)
\r
10127 uint src = OPER_AY_PD_8();
\r
10128 uint ea = EA_AX_PD_8();
\r
10129 uint dst = m68ki_read_8(ea);
\r
10130 uint res = dst - src - XFLAG_AS_1();
\r
10132 FLAG_N = NFLAG_8(res);
\r
10133 FLAG_X = FLAG_C = CFLAG_8(res);
\r
10134 FLAG_V = VFLAG_SUB_8(src, dst, res);
\r
10136 res = MASK_OUT_ABOVE_8(res);
\r
10139 m68ki_write_8(ea, res);
\r
10143 M68KMAKE_OP(subx, 16, mm, .)
\r
10145 uint src = OPER_AY_PD_16();
\r
10146 uint ea = EA_AX_PD_16();
\r
10147 uint dst = m68ki_read_16(ea);
\r
10148 uint res = dst - src - XFLAG_AS_1();
\r
10150 FLAG_N = NFLAG_16(res);
\r
10151 FLAG_X = FLAG_C = CFLAG_16(res);
\r
10152 FLAG_V = VFLAG_SUB_16(src, dst, res);
\r
10154 res = MASK_OUT_ABOVE_16(res);
\r
10157 m68ki_write_16(ea, res);
\r
10161 M68KMAKE_OP(subx, 32, mm, .)
\r
10163 uint src = OPER_AY_PD_32();
\r
10164 uint ea = EA_AX_PD_32();
\r
10165 uint dst = m68ki_read_32(ea);
\r
10166 uint res = dst - src - XFLAG_AS_1();
\r
10168 FLAG_N = NFLAG_32(res);
\r
10169 FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
\r
10170 FLAG_V = VFLAG_SUB_32(src, dst, res);
\r
10172 res = MASK_OUT_ABOVE_32(res);
\r
10175 m68ki_write_32(ea, res);
\r
10179 M68KMAKE_OP(swap, 32, ., .)
\r
10181 uint* r_dst = &DY;
\r
10183 FLAG_Z = MASK_OUT_ABOVE_32(*r_dst<<16);
\r
10184 *r_dst = (*r_dst>>16) | FLAG_Z;
\r
10187 FLAG_N = NFLAG_32(*r_dst);
\r
10188 FLAG_C = CFLAG_CLEAR;
\r
10189 FLAG_V = VFLAG_CLEAR;
\r
10193 M68KMAKE_OP(tas, 8, ., d)
\r
10195 uint* r_dst = &DY;
\r
10197 FLAG_Z = MASK_OUT_ABOVE_8(*r_dst);
\r
10198 FLAG_N = NFLAG_8(*r_dst);
\r
10199 FLAG_V = VFLAG_CLEAR;
\r
10200 FLAG_C = CFLAG_CLEAR;
\r
10205 M68KMAKE_OP(tas, 8, ., .)
\r
10207 uint ea = M68KMAKE_GET_EA_AY_8;
\r
10208 uint dst = m68ki_read_8(ea);
\r
10209 uint allow_writeback;
\r
10212 FLAG_N = NFLAG_8(dst);
\r
10213 FLAG_V = VFLAG_CLEAR;
\r
10214 FLAG_C = CFLAG_CLEAR;
\r
10216 /* The Genesis/Megadrive games Gargoyles and Ex-Mutants need the TAS writeback
\r
10217 disabled in order to function properly. Some Amiga software may also rely
\r
10218 on this, but only when accessing specific addresses so additional functionality
\r
10219 will be needed. */
\r
10220 allow_writeback = m68ki_tas_callback();
\r
10222 if (allow_writeback==1) m68ki_write_8(ea, dst | 0x80);
\r
10226 M68KMAKE_OP(trap, 0, ., .)
\r
10228 /* Trap#n stacks exception frame type 0 */
\r
10229 m68ki_exception_trapN(EXCEPTION_TRAP_BASE + (REG_IR & 0xf)); /* HJB 990403 */
\r
10233 M68KMAKE_OP(trapt, 0, ., .)
\r
10235 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
10237 m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */
\r
10240 m68ki_exception_illegal();
\r
10244 M68KMAKE_OP(trapt, 16, ., .)
\r
10246 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
10248 m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */
\r
10251 m68ki_exception_illegal();
\r
10255 M68KMAKE_OP(trapt, 32, ., .)
\r
10257 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
10259 m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */
\r
10262 m68ki_exception_illegal();
\r
10266 M68KMAKE_OP(trapf, 0, ., .)
\r
10268 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
10272 m68ki_exception_illegal();
\r
10276 M68KMAKE_OP(trapf, 16, ., .)
\r
10278 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
10283 m68ki_exception_illegal();
\r
10287 M68KMAKE_OP(trapf, 32, ., .)
\r
10289 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
10294 m68ki_exception_illegal();
\r
10298 M68KMAKE_OP(trapcc, 0, ., .)
\r
10300 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
10303 m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */
\r
10306 m68ki_exception_illegal();
\r
10310 M68KMAKE_OP(trapcc, 16, ., .)
\r
10312 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
10316 m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */
\r
10322 m68ki_exception_illegal();
\r
10326 M68KMAKE_OP(trapcc, 32, ., .)
\r
10328 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
10332 m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */
\r
10338 m68ki_exception_illegal();
\r
10342 M68KMAKE_OP(trapv, 0, ., .)
\r
10348 m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */
\r
10352 M68KMAKE_OP(tst, 8, ., d)
\r
10354 uint res = MASK_OUT_ABOVE_8(DY);
\r
10356 FLAG_N = NFLAG_8(res);
\r
10358 FLAG_V = VFLAG_CLEAR;
\r
10359 FLAG_C = CFLAG_CLEAR;
\r
10363 M68KMAKE_OP(tst, 8, ., .)
\r
10365 uint res = M68KMAKE_GET_OPER_AY_8;
\r
10367 FLAG_N = NFLAG_8(res);
\r
10369 FLAG_V = VFLAG_CLEAR;
\r
10370 FLAG_C = CFLAG_CLEAR;
\r
10374 M68KMAKE_OP(tst, 8, ., pcdi)
\r
10376 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
10378 uint res = OPER_PCDI_8();
\r
10380 FLAG_N = NFLAG_8(res);
\r
10382 FLAG_V = VFLAG_CLEAR;
\r
10383 FLAG_C = CFLAG_CLEAR;
\r
10386 m68ki_exception_illegal();
\r
10390 M68KMAKE_OP(tst, 8, ., pcix)
\r
10392 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
10394 uint res = OPER_PCIX_8();
\r
10396 FLAG_N = NFLAG_8(res);
\r
10398 FLAG_V = VFLAG_CLEAR;
\r
10399 FLAG_C = CFLAG_CLEAR;
\r
10402 m68ki_exception_illegal();
\r
10406 M68KMAKE_OP(tst, 8, ., i)
\r
10408 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
10410 uint res = OPER_I_8();
\r
10412 FLAG_N = NFLAG_8(res);
\r
10414 FLAG_V = VFLAG_CLEAR;
\r
10415 FLAG_C = CFLAG_CLEAR;
\r
10418 m68ki_exception_illegal();
\r
10422 M68KMAKE_OP(tst, 16, ., d)
\r
10424 uint res = MASK_OUT_ABOVE_16(DY);
\r
10426 FLAG_N = NFLAG_16(res);
\r
10428 FLAG_V = VFLAG_CLEAR;
\r
10429 FLAG_C = CFLAG_CLEAR;
\r
10433 M68KMAKE_OP(tst, 16, ., a)
\r
10435 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
10437 uint res = MAKE_INT_16(AY);
\r
10439 FLAG_N = NFLAG_16(res);
\r
10441 FLAG_V = VFLAG_CLEAR;
\r
10442 FLAG_C = CFLAG_CLEAR;
\r
10445 m68ki_exception_illegal();
\r
10449 M68KMAKE_OP(tst, 16, ., .)
\r
10451 uint res = M68KMAKE_GET_OPER_AY_16;
\r
10453 FLAG_N = NFLAG_16(res);
\r
10455 FLAG_V = VFLAG_CLEAR;
\r
10456 FLAG_C = CFLAG_CLEAR;
\r
10460 M68KMAKE_OP(tst, 16, ., pcdi)
\r
10462 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
10464 uint res = OPER_PCDI_16();
\r
10466 FLAG_N = NFLAG_16(res);
\r
10468 FLAG_V = VFLAG_CLEAR;
\r
10469 FLAG_C = CFLAG_CLEAR;
\r
10472 m68ki_exception_illegal();
\r
10476 M68KMAKE_OP(tst, 16, ., pcix)
\r
10478 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
10480 uint res = OPER_PCIX_16();
\r
10482 FLAG_N = NFLAG_16(res);
\r
10484 FLAG_V = VFLAG_CLEAR;
\r
10485 FLAG_C = CFLAG_CLEAR;
\r
10488 m68ki_exception_illegal();
\r
10492 M68KMAKE_OP(tst, 16, ., i)
\r
10494 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
10496 uint res = OPER_I_16();
\r
10498 FLAG_N = NFLAG_16(res);
\r
10500 FLAG_V = VFLAG_CLEAR;
\r
10501 FLAG_C = CFLAG_CLEAR;
\r
10504 m68ki_exception_illegal();
\r
10508 M68KMAKE_OP(tst, 32, ., d)
\r
10512 FLAG_N = NFLAG_32(res);
\r
10514 FLAG_V = VFLAG_CLEAR;
\r
10515 FLAG_C = CFLAG_CLEAR;
\r
10519 M68KMAKE_OP(tst, 32, ., a)
\r
10521 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
10525 FLAG_N = NFLAG_32(res);
\r
10527 FLAG_V = VFLAG_CLEAR;
\r
10528 FLAG_C = CFLAG_CLEAR;
\r
10531 m68ki_exception_illegal();
\r
10535 M68KMAKE_OP(tst, 32, ., .)
\r
10537 uint res = M68KMAKE_GET_OPER_AY_32;
\r
10539 FLAG_N = NFLAG_32(res);
\r
10541 FLAG_V = VFLAG_CLEAR;
\r
10542 FLAG_C = CFLAG_CLEAR;
\r
10546 M68KMAKE_OP(tst, 32, ., pcdi)
\r
10548 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
10550 uint res = OPER_PCDI_32();
\r
10552 FLAG_N = NFLAG_32(res);
\r
10554 FLAG_V = VFLAG_CLEAR;
\r
10555 FLAG_C = CFLAG_CLEAR;
\r
10558 m68ki_exception_illegal();
\r
10562 M68KMAKE_OP(tst, 32, ., pcix)
\r
10564 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
10566 uint res = OPER_PCIX_32();
\r
10568 FLAG_N = NFLAG_32(res);
\r
10570 FLAG_V = VFLAG_CLEAR;
\r
10571 FLAG_C = CFLAG_CLEAR;
\r
10574 m68ki_exception_illegal();
\r
10578 M68KMAKE_OP(tst, 32, ., i)
\r
10580 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
10582 uint res = OPER_I_32();
\r
10584 FLAG_N = NFLAG_32(res);
\r
10586 FLAG_V = VFLAG_CLEAR;
\r
10587 FLAG_C = CFLAG_CLEAR;
\r
10590 m68ki_exception_illegal();
\r
10594 M68KMAKE_OP(unlk, 32, ., a7)
\r
10596 REG_A[7] = m68ki_read_32(REG_A[7]);
\r
10600 M68KMAKE_OP(unlk, 32, ., .)
\r
10602 uint* r_dst = &AY;
\r
10604 REG_A[7] = *r_dst;
\r
10605 *r_dst = m68ki_pull_32();
\r
10609 M68KMAKE_OP(unpk, 16, rr, .)
\r
10611 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
10613 /* Note: DX and DY are reversed in Motorola's docs */
\r
10615 uint* r_dst = &DX;
\r
10617 *r_dst = MASK_OUT_BELOW_16(*r_dst) | (((((src << 4) & 0x0f00) | (src & 0x000f)) + OPER_I_16()) & 0xffff);
\r
10620 m68ki_exception_illegal();
\r
10624 M68KMAKE_OP(unpk, 16, mm, ax7)
\r
10626 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
10628 /* Note: AX and AY are reversed in Motorola's docs */
\r
10629 uint src = OPER_AY_PD_8();
\r
10632 src = (((src << 4) & 0x0f00) | (src & 0x000f)) + OPER_I_16();
\r
10633 ea_dst = EA_A7_PD_8();
\r
10634 m68ki_write_8(ea_dst, (src >> 8) & 0xff);
\r
10635 ea_dst = EA_A7_PD_8();
\r
10636 m68ki_write_8(ea_dst, src & 0xff);
\r
10639 m68ki_exception_illegal();
\r
10643 M68KMAKE_OP(unpk, 16, mm, ay7)
\r
10645 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
10647 /* Note: AX and AY are reversed in Motorola's docs */
\r
10648 uint src = OPER_A7_PD_8();
\r
10651 src = (((src << 4) & 0x0f00) | (src & 0x000f)) + OPER_I_16();
\r
10652 ea_dst = EA_AX_PD_8();
\r
10653 m68ki_write_8(ea_dst, (src >> 8) & 0xff);
\r
10654 ea_dst = EA_AX_PD_8();
\r
10655 m68ki_write_8(ea_dst, src & 0xff);
\r
10658 m68ki_exception_illegal();
\r
10662 M68KMAKE_OP(unpk, 16, mm, axy7)
\r
10664 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
10666 uint src = OPER_A7_PD_8();
\r
10669 src = (((src << 4) & 0x0f00) | (src & 0x000f)) + OPER_I_16();
\r
10670 ea_dst = EA_A7_PD_8();
\r
10671 m68ki_write_8(ea_dst, (src >> 8) & 0xff);
\r
10672 ea_dst = EA_A7_PD_8();
\r
10673 m68ki_write_8(ea_dst, src & 0xff);
\r
10676 m68ki_exception_illegal();
\r
10680 M68KMAKE_OP(unpk, 16, mm, .)
\r
10682 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
10684 /* Note: AX and AY are reversed in Motorola's docs */
\r
10685 uint src = OPER_AY_PD_8();
\r
10688 src = (((src << 4) & 0x0f00) | (src & 0x000f)) + OPER_I_16();
\r
10689 ea_dst = EA_AX_PD_8();
\r
10690 m68ki_write_8(ea_dst, (src >> 8) & 0xff);
\r
10691 ea_dst = EA_AX_PD_8();
\r
10692 m68ki_write_8(ea_dst, src & 0xff);
\r
10695 m68ki_exception_illegal();
\r
10700 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
\r
notaz.gp2x.de / picodrive.git / blob