3 * (C) notaz, 2009,2010,2013
5 * This work is licensed under the terms of MAME license.
6 * See COPYING file in the top-level directory.
9 * a15100 F....... R.....EA F.....AC N...VHMP 4000 // Fm Ren nrEs Aden Cart heN V H cMd Pwm
10 * a15102 ........ ......SM ? 4002 // intS intM
11 * a15104 ........ ......10 ........ hhhhhhhh 4004 // bk1 bk0 Hint
12 * a15106 ........ F....SDR UE...... .....SDR 4006 // Full 68S Dma Rv fUll[fb] Empt[fb]
13 * a15108 (32bit DREQ src) 4008
14 * a1510c (32bit DREQ dst) 400c
15 * a15110 llllllll llllll00 4010 // DREQ Len
16 * a15112 (16bit FIFO reg) 4012
17 * a15114 0 (16bit VRES clr) 4014
18 * a15116 0 (16bit Vint clr) 4016
19 * a15118 0 (16bit Hint clr) 4018
20 * a1511a .......? .......C (16bit CMD clr) 401a // TV Cm
21 * a1511c 0 (16bit PWM clr) 401c
23 * a15120 (16 bytes comm) 2020
27 * iii. .cc. ..xx * // Internal, Cs, x
29 * sh2 map, wait/bus cycles (from docs):
31 * rom 0000000-0003fff 1 -
32 * sys reg 0004000-00040ff 1 1
33 * vdp reg 0004100-00041ff 5 5
34 * vdp pal 0004200-00043ff 5 5
35 * cart 2000000-23fffff 6-15
36 * dram/fb 4000000-401ffff 5-12 1-3
37 * fb ovr 4020000-403ffff
38 * sdram 6000000-603ffff 12 2 (cycles)
41 #include "../pico_int.h"
42 #include "../memory.h"
43 #include "../../cpu/sh2/compiler.h"
45 static const char str_mars[] = "MARS";
47 void *p32x_bios_g, *p32x_bios_m, *p32x_bios_s;
48 struct Pico32xMem *Pico32xMem;
50 static void bank_switch(int b);
52 // addressing byte in 16bit reg
53 #define REG8IN16(ptr, offs) ((u8 *)ptr)[(offs) ^ 1]
56 #define POLL_THRESHOLD 3
63 static int m68k_poll_detect(u32 a, u32 cycles, u32 flags)
67 if (a - 2 <= m68k_poll.addr && m68k_poll.addr <= a + 2
68 && cycles - m68k_poll.cycles <= 64)
70 if (m68k_poll.cnt++ > POLL_THRESHOLD) {
71 if (!(Pico32x.emu_flags & flags)) {
72 elprintf(EL_32X, "m68k poll addr %08x, cyc %u",
73 a, cycles - m68k_poll.cycles);
76 Pico32x.emu_flags |= flags;
83 m68k_poll.cycles = cycles;
88 void p32x_m68k_poll_event(u32 flags)
90 if (Pico32x.emu_flags & flags) {
91 elprintf(EL_32X, "m68k poll %02x -> %02x", Pico32x.emu_flags,
92 Pico32x.emu_flags & ~flags);
93 Pico32x.emu_flags &= ~flags;
96 m68k_poll.addr = m68k_poll.cnt = 0;
99 static void sh2_poll_detect(SH2 *sh2, u32 a, u32 flags, int maxcnt)
101 int cycles_left = sh2_cycles_left(sh2);
103 if (a == sh2->poll_addr && sh2->poll_cycles - cycles_left <= 10) {
104 if (sh2->poll_cnt++ > maxcnt) {
105 if (!(sh2->state & flags))
106 elprintf_sh2(sh2, EL_32X, "state: %02x->%02x",
107 sh2->state, sh2->state | flags);
111 pevt_log_sh2(sh2, EVT_POLL_START);
118 sh2->poll_cycles = cycles_left;
121 void p32x_sh2_poll_event(SH2 *sh2, u32 flags, u32 m68k_cycles)
123 if (sh2->state & flags) {
124 elprintf_sh2(sh2, EL_32X, "state: %02x->%02x", sh2->state,
125 sh2->state & ~flags);
127 if (sh2->m68krcycles_done < m68k_cycles)
128 sh2->m68krcycles_done = m68k_cycles;
130 pevt_log_sh2_o(sh2, EVT_POLL_END);
133 sh2->state &= ~flags;
134 sh2->poll_addr = sh2->poll_cycles = sh2->poll_cnt = 0;
137 static void sh2s_sync_on_read(SH2 *sh2)
140 if (sh2->poll_cnt != 0)
143 cycles = sh2_cycles_done(sh2);
145 p32x_sync_other_sh2(sh2, sh2->m68krcycles_done + cycles / 3);
151 static int p32x_csum_faked;
152 static const u16 comm_fakevals[] = {
153 0x4d5f, 0x4f4b, // M_OK
154 0x535f, 0x4f4b, // S_OK
155 0x4D41, 0x5346, // MASF - Brutal Unleashed
156 0x5331, 0x4d31, // Darxide
159 0x0000, 0x0000, // eq for doom
160 0x0002, // Mortal Kombat
164 static u32 sh2_comm_faker(u32 a)
167 if (a == 0x28 && !p32x_csum_faked) {
169 return *(unsigned short *)(Pico.rom + 0x18e);
171 if (f >= sizeof(comm_fakevals) / sizeof(comm_fakevals[0]))
173 return comm_fakevals[f++];
177 // ------------------------------------------------------------------
180 static u32 p32x_reg_read16(u32 a)
185 if ((a & 0x30) == 0x20)
186 return sh2_comm_faker(a);
188 if ((a & 0x30) == 0x20) {
190 unsigned int cycles = SekCyclesDoneT();
191 int comreg = 1 << (a & 0x0f) / 2;
193 // evil X-Men proto polls in a dbra loop and expects it to expire..
194 if (SekDar(2) != dr2)
198 if (cycles - msh2.m68krcycles_done > 500)
199 p32x_sync_sh2s(cycles);
200 if (Pico32x.comm_dirty_sh2 & comreg)
201 Pico32x.comm_dirty_sh2 &= ~comreg;
202 else if (m68k_poll_detect(a, cycles, P32XF_68KCPOLL)) {
211 if (a == 2) { // INTM, INTS
212 unsigned int cycles = SekCyclesDoneT();
213 if (cycles - msh2.m68krcycles_done > 64)
214 p32x_sync_sh2s(cycles);
218 if ((a & 0x30) == 0x30)
219 return p32x_pwm_read16(a, NULL, SekCyclesDoneT());
222 return Pico32x.regs[a / 2];
225 static void dreq0_write(u16 *r, u32 d)
227 if (!(r[6 / 2] & P32XS_68S)) {
228 elprintf(EL_32X|EL_ANOMALY, "DREQ FIFO w16 without 68S?");
229 return; // ignored - tested
231 if (Pico32x.dmac0_fifo_ptr < DMAC_FIFO_LEN) {
232 Pico32x.dmac_fifo[Pico32x.dmac0_fifo_ptr++] = d;
233 if (Pico32x.dmac0_fifo_ptr == DMAC_FIFO_LEN)
234 r[6 / 2] |= P32XS_FULL;
235 // tested: len register decrements and 68S clears
236 // even if SH2s/DMAC aren't active..
238 if (r[0x10 / 2] == 0)
239 r[6 / 2] &= ~P32XS_68S;
241 if ((Pico32x.dmac0_fifo_ptr & 3) == 0) {
242 p32x_sync_sh2s(SekCyclesDoneT());
243 p32x_dreq0_trigger();
247 elprintf(EL_32X|EL_ANOMALY, "DREQ FIFO overflow!");
250 // writable bits tested
251 static void p32x_reg_write8(u32 a, u32 d)
253 u16 *r = Pico32x.regs;
256 // for things like bset on comm port
260 case 0x00: // adapter ctl: FM writable
261 REG8IN16(r, 0x00) = d & 0x80;
263 case 0x01: // adapter ctl: RES and ADEN writable
264 if ((d ^ r[0]) & d & P32XS_nRES)
266 REG8IN16(r, 0x01) &= ~(P32XS_nRES|P32XS_ADEN);
267 REG8IN16(r, 0x01) |= d & (P32XS_nRES|P32XS_ADEN);
269 case 0x02: // ignored, always 0
271 case 0x03: // irq ctl
272 if ((d ^ r[0x02 / 2]) & 3) {
273 int cycles = SekCyclesDoneT();
274 p32x_sync_sh2s(cycles);
276 p32x_update_cmd_irq(NULL, cycles);
279 case 0x04: // ignored, always 0
283 if (r[0x04 / 2] != d) {
288 case 0x06: // ignored, always 0
290 case 0x07: // DREQ ctl
291 REG8IN16(r, 0x07) &= ~(P32XS_68S|P32XS_DMA|P32XS_RV);
292 if (!(d & P32XS_68S)) {
293 Pico32x.dmac0_fifo_ptr = 0;
294 REG8IN16(r, 0x07) &= ~P32XS_FULL;
296 REG8IN16(r, 0x07) |= d & (P32XS_68S|P32XS_DMA|P32XS_RV);
298 case 0x08: // ignored, always 0
300 case 0x09: // DREQ src
301 REG8IN16(r, 0x09) = d;
304 REG8IN16(r, 0x0a) = d;
307 REG8IN16(r, 0x0b) = d & 0xfe;
309 case 0x0c: // ignored, always 0
311 case 0x0d: // DREQ dest
314 case 0x10: // DREQ len
318 REG8IN16(r, a) = d & 0xfc;
320 // DREQ FIFO - writes to odd addr go to fifo
321 // do writes to even work? Reads return 0
326 d = (REG8IN16(r, 0x12) << 8) | (d & 0xff);
327 REG8IN16(r, 0x12) = 0;
330 case 0x14: // ignored, always 0
337 case 0x1a: // what's this?
338 elprintf(EL_32X|EL_ANOMALY, "mystery w8 %02x %02x", a, d);
339 REG8IN16(r, a) = d & 0x01;
342 REG8IN16(r, a) = d & 0x01;
344 case 0x1c: // ignored, always 0
350 case 0x31: // PWM control
351 REG8IN16(r, a) &= ~0x0f;
352 REG8IN16(r, a) |= d & 0x0f;
355 case 0x32: // PWM cycle
356 REG8IN16(r, a) = d & 0x0f;
363 // PWM pulse regs.. Only writes to odd address send a value
364 // to FIFO; reads are 0 (except status bits)
373 d = (REG8IN16(r, a ^ 1) << 8) | (d & 0xff);
374 REG8IN16(r, a ^ 1) = 0;
376 case 0x3a: // ignored, always 0
384 p32x_pwm_write16(a & ~1, d, NULL, SekCyclesDoneT());
388 if ((a & 0x30) == 0x20) {
389 int cycles = SekCyclesDoneT();
392 if (REG8IN16(r, a) == d)
395 comreg = 1 << (a & 0x0f) / 2;
396 if (Pico32x.comm_dirty_68k & comreg)
397 p32x_sync_sh2s(cycles);
400 p32x_sh2_poll_event(&sh2s[0], SH2_STATE_CPOLL, cycles);
401 p32x_sh2_poll_event(&sh2s[1], SH2_STATE_CPOLL, cycles);
402 Pico32x.comm_dirty_68k |= comreg;
404 if (cycles - (int)msh2.m68krcycles_done > 120)
405 p32x_sync_sh2s(cycles);
410 static void p32x_reg_write16(u32 a, u32 d)
412 u16 *r = Pico32x.regs;
415 // for things like bset on comm port
419 case 0x00: // adapter ctl
420 if ((d ^ r[0]) & d & P32XS_nRES)
422 r[0] &= ~(P32XS_FM|P32XS_nRES|P32XS_ADEN);
423 r[0] |= d & (P32XS_FM|P32XS_nRES|P32XS_ADEN);
425 case 0x08: // DREQ src
431 case 0x0c: // DREQ dest
437 case 0x10: // DREQ len
440 case 0x12: // FIFO reg
443 case 0x1a: // TV + mystery bit
444 r[a / 2] = d & 0x0101;
446 case 0x30: // PWM control
447 d = (r[a / 2] & ~0x0f) | (d & 0x0f);
449 p32x_pwm_write16(a, d, NULL, SekCyclesDoneT());
454 if ((a & 0x30) == 0x20) {
455 int cycles = SekCyclesDoneT();
461 comreg = 1 << (a & 0x0f) / 2;
462 if (Pico32x.comm_dirty_68k & comreg)
463 p32x_sync_sh2s(cycles);
466 p32x_sh2_poll_event(&sh2s[0], SH2_STATE_CPOLL, cycles);
467 p32x_sh2_poll_event(&sh2s[1], SH2_STATE_CPOLL, cycles);
468 Pico32x.comm_dirty_68k |= comreg;
470 if (cycles - (int)msh2.m68krcycles_done > 120)
471 p32x_sync_sh2s(cycles);
475 else if ((a & 0x30) == 0x30) {
476 p32x_pwm_write16(a, d, NULL, SekCyclesDoneT());
480 p32x_reg_write8(a + 1, d);
483 // ------------------------------------------------------------------
485 static u32 p32x_vdp_read16(u32 a)
490 d = Pico32x.vdp_regs[a / 2];
492 // tested: FEN seems to be randomly pulsing on hcnt 0x80-0xf0,
493 // most often at 0xb1-0xb5, even during vblank,
494 // what's the deal with that?
495 // we'll just fake it along with hblank for now
496 Pico32x.vdp_fbcr_fake++;
497 if (Pico32x.vdp_fbcr_fake & 4)
499 if ((Pico32x.vdp_fbcr_fake & 7) == 0)
505 static void p32x_vdp_write8(u32 a, u32 d)
507 u16 *r = Pico32x.vdp_regs;
510 // TODO: verify what's writeable
513 // priority inversion is handled in palette
514 if ((r[0] ^ d) & P32XV_PRI)
515 Pico32x.dirty_pal = 1;
516 r[0] = (r[0] & P32XV_nPAL) | (d & 0xff);
518 case 0x03: // shift (for pp mode)
521 case 0x05: // fill len
526 Pico32x.pending_fb = d;
527 // if we are blanking and FS bit is changing
528 if (((r[0x0a/2] & P32XV_VBLK) || (r[0] & P32XV_Mx) == 0) && ((r[0x0a/2] ^ d) & P32XV_FS)) {
529 r[0x0a/2] ^= P32XV_FS;
530 Pico32xSwapDRAM(d ^ 1);
531 elprintf(EL_32X, "VDP FS: %d", r[0x0a/2] & P32XV_FS);
537 static void p32x_vdp_write16(u32 a, u32 d, SH2 *sh2)
540 if (a == 6) { // fill start
541 Pico32x.vdp_regs[6 / 2] = d;
544 if (a == 8) { // fill data
545 u16 *dram = Pico32xMem->dram[(Pico32x.vdp_regs[0x0a/2] & P32XV_FS) ^ 1];
546 int len = Pico32x.vdp_regs[4 / 2] + 1;
548 a = Pico32x.vdp_regs[6 / 2];
551 a = (a & 0xff00) | ((a + 1) & 0xff);
553 Pico32x.vdp_regs[0x06 / 2] = a;
554 Pico32x.vdp_regs[0x08 / 2] = d;
555 if (sh2 != NULL && len > 4) {
556 Pico32x.vdp_regs[0x0a / 2] |= P32XV_nFEN;
557 // supposedly takes 3 bus/6 sh2 cycles? or 3 sh2 cycles?
558 p32x_event_schedule_sh2(sh2, P32X_EVENT_FILLEND, 3 + len);
563 p32x_vdp_write8(a | 1, d);
566 // ------------------------------------------------------------------
569 static u32 p32x_sh2reg_read16(u32 a, SH2 *sh2)
571 u16 *r = Pico32x.regs;
575 case 0x00: // adapter/irq ctl
576 return (r[0] & P32XS_FM) | Pico32x.sh2_regs[0]
577 | Pico32x.sh2irq_mask[sh2->is_slave];
578 case 0x04: // H count (often as comm too)
579 sh2_poll_detect(sh2, a, SH2_STATE_CPOLL, 3);
580 sh2s_sync_on_read(sh2);
581 return Pico32x.sh2_regs[4 / 2];
583 return (r[a / 2] & ~P32XS_FULL) | 0x4000;
584 case 0x08: // DREQ src
586 case 0x0c: // DREQ dst
588 case 0x10: // DREQ len
590 case 0x12: // DREQ FIFO - does this work on hw?
591 if (Pico32x.dmac0_fifo_ptr > 0) {
592 Pico32x.dmac0_fifo_ptr--;
593 r[a / 2] = Pico32x.dmac_fifo[0];
594 memmove(&Pico32x.dmac_fifo[0], &Pico32x.dmac_fifo[1],
595 Pico32x.dmac0_fifo_ptr * 2);
607 if ((a & 0x30) == 0x20) {
608 int comreg = 1 << (a & 0x0f) / 2;
609 if (Pico32x.comm_dirty_68k & comreg)
610 Pico32x.comm_dirty_68k &= ~comreg;
612 sh2_poll_detect(sh2, a, SH2_STATE_CPOLL, 3);
613 sh2s_sync_on_read(sh2);
616 if ((a & 0x30) == 0x30)
617 return p32x_pwm_read16(a, sh2, sh2_cycles_done_m68k(sh2));
619 elprintf_sh2(sh2, EL_32X|EL_ANOMALY,
620 "unhandled sysreg r16 [%02x] @%08x", a, sh2_pc(sh2));
624 static void p32x_sh2reg_write8(u32 a, u32 d, SH2 *sh2)
626 u16 *r = Pico32x.regs;
635 r[0] |= (d << 8) & P32XS_FM;
637 case 0x01: // HEN/irq masks
638 old = Pico32x.sh2irq_mask[sh2->is_slave];
640 p32x_pwm_sync_to_sh2(sh2);
642 Pico32x.sh2irq_mask[sh2->is_slave] = d & 0x0f;
643 Pico32x.sh2_regs[0] &= ~0x80;
644 Pico32x.sh2_regs[0] |= d & 0x80;
647 p32x_pwm_schedule_sh2(sh2);
649 p32x_update_cmd_irq(sh2, 0);
651 p32x_schedule_hint(sh2, 0);
653 case 0x04: // ignored?
655 case 0x05: // H count
657 if (Pico32x.sh2_regs[4 / 2] != d) {
658 Pico32x.sh2_regs[4 / 2] = d;
659 p32x_sh2_poll_event(sh2->other_sh2, SH2_STATE_CPOLL,
660 sh2_cycles_done_m68k(sh2));
665 REG8IN16(r, a) = d & 0x0f;
668 case 0x31: // PWM control
669 REG8IN16(r, a) = d & 0x8f;
672 case 0x32: // PWM cycle
673 REG8IN16(r, a) = d & 0x0f;
680 // PWM pulse regs.. Only writes to odd address send a value
681 // to FIFO; reads are 0 (except status bits)
690 d = (REG8IN16(r, a ^ 1) << 8) | (d & 0xff);
691 REG8IN16(r, a ^ 1) = 0;
693 case 0x3a: // ignored, always 0?
701 p32x_pwm_write16(a & ~1, d, sh2, 0);
705 if ((a & 0x30) == 0x20) {
707 if (REG8IN16(r, a) == d)
711 p32x_m68k_poll_event(P32XF_68KCPOLL);
712 p32x_sh2_poll_event(sh2->other_sh2, SH2_STATE_CPOLL,
713 sh2_cycles_done_m68k(sh2));
714 comreg = 1 << (a & 0x0f) / 2;
715 Pico32x.comm_dirty_sh2 |= comreg;
719 elprintf(EL_32X|EL_ANOMALY,
720 "unhandled sysreg w8 [%02x] %02x @%08x", a, d, sh2_pc(sh2));
723 static void p32x_sh2reg_write16(u32 a, u32 d, SH2 *sh2)
730 if ((a & 0x30) == 0x20) {
732 if (Pico32x.regs[a / 2] == d)
735 Pico32x.regs[a / 2] = d;
736 p32x_m68k_poll_event(P32XF_68KCPOLL);
737 p32x_sh2_poll_event(sh2->other_sh2, SH2_STATE_CPOLL,
738 sh2_cycles_done_m68k(sh2));
739 comreg = 1 << (a & 0x0f) / 2;
740 Pico32x.comm_dirty_sh2 |= comreg;
744 else if ((a & 0x30) == 0x30) {
745 p32x_pwm_write16(a, d, sh2, sh2_cycles_done_m68k(sh2));
751 Pico32x.regs[0] &= ~P32XS_FM;
752 Pico32x.regs[0] |= d & P32XS_FM;
755 Pico32x.sh2irqs &= ~P32XI_VRES;
758 Pico32x.sh2irqi[sh2->is_slave] &= ~P32XI_VINT;
761 Pico32x.sh2irqi[sh2->is_slave] &= ~P32XI_HINT;
764 Pico32x.regs[2 / 2] &= ~(1 << sh2->is_slave);
765 p32x_update_cmd_irq(sh2, 0);
768 p32x_pwm_sync_to_sh2(sh2);
769 Pico32x.sh2irqi[sh2->is_slave] &= ~P32XI_PWM;
770 p32x_pwm_schedule_sh2(sh2);
774 p32x_sh2reg_write8(a | 1, d, sh2);
778 p32x_update_irls(sh2, 0);
781 // ------------------------------------------------------------------
785 static u32 PicoRead8_32x_on(u32 a)
788 if ((a & 0xffc0) == 0x5100) { // a15100
789 d = p32x_reg_read16(a);
793 if ((a & 0xfc00) != 0x5000)
794 return PicoRead8_io(a);
796 if ((a & 0xfff0) == 0x5180) { // a15180
797 d = p32x_vdp_read16(a);
801 if ((a & 0xfe00) == 0x5200) { // a15200
802 d = Pico32xMem->pal[(a & 0x1ff) / 2];
806 if ((a & 0xfffc) == 0x30ec) { // a130ec
811 elprintf(EL_UIO, "m68k unmapped r8 [%06x] @%06x", a, SekPc);
821 elprintf(EL_32X, "m68k 32x r8 [%06x] %02x @%06x", a, d, SekPc);
825 static u32 PicoRead16_32x_on(u32 a)
828 if ((a & 0xffc0) == 0x5100) { // a15100
829 d = p32x_reg_read16(a);
833 if ((a & 0xfc00) != 0x5000)
834 return PicoRead16_io(a);
836 if ((a & 0xfff0) == 0x5180) { // a15180
837 d = p32x_vdp_read16(a);
841 if ((a & 0xfe00) == 0x5200) { // a15200
842 d = Pico32xMem->pal[(a & 0x1ff) / 2];
846 if ((a & 0xfffc) == 0x30ec) { // a130ec
847 d = !(a & 2) ? ('M'<<8)|'A' : ('R'<<8)|'S';
851 elprintf(EL_UIO, "m68k unmapped r16 [%06x] @%06x", a, SekPc);
855 elprintf(EL_32X, "m68k 32x r16 [%06x] %04x @%06x", a, d, SekPc);
859 static void PicoWrite8_32x_on(u32 a, u32 d)
861 if ((a & 0xfc00) == 0x5000)
862 elprintf(EL_32X, "m68k 32x w8 [%06x] %02x @%06x", a, d & 0xff, SekPc);
864 if ((a & 0xffc0) == 0x5100) { // a15100
865 p32x_reg_write8(a, d);
869 if ((a & 0xfc00) != 0x5000) {
872 bank_switch(Pico32x.regs[4 / 2]);
876 if (!(Pico32x.regs[0] & P32XS_FM)) {
877 if ((a & 0xfff0) == 0x5180) { // a15180
878 p32x_vdp_write8(a, d);
883 if ((a & 0xfe00) == 0x5200) { // a15200
884 elprintf(EL_32X|EL_ANOMALY, "m68k 32x PAL w8 [%06x] %02x @%06x", a, d & 0xff, SekPc);
885 ((u8 *)Pico32xMem->pal)[(a & 0x1ff) ^ 1] = d;
886 Pico32x.dirty_pal = 1;
891 elprintf(EL_UIO, "m68k unmapped w8 [%06x] %02x @%06x", a, d & 0xff, SekPc);
894 static void PicoWrite16_32x_on(u32 a, u32 d)
896 if ((a & 0xfc00) == 0x5000)
897 elprintf(EL_32X, "m68k 32x w16 [%06x] %04x @%06x", a, d & 0xffff, SekPc);
899 if ((a & 0xffc0) == 0x5100) { // a15100
900 p32x_reg_write16(a, d);
904 if ((a & 0xfc00) != 0x5000) {
905 PicoWrite16_io(a, d);
907 bank_switch(Pico32x.regs[4 / 2]);
911 if (!(Pico32x.regs[0] & P32XS_FM)) {
912 if ((a & 0xfff0) == 0x5180) { // a15180
913 p32x_vdp_write16(a, d, NULL); // FIXME?
917 if ((a & 0xfe00) == 0x5200) { // a15200
918 Pico32xMem->pal[(a & 0x1ff) / 2] = d;
919 Pico32x.dirty_pal = 1;
924 elprintf(EL_UIO, "m68k unmapped w16 [%06x] %04x @%06x", a, d & 0xffff, SekPc);
928 u32 PicoRead8_32x(u32 a)
931 if ((a & 0xffc0) == 0x5100) { // a15100
932 // regs are always readable
933 d = ((u8 *)Pico32x.regs)[(a & 0x3f) ^ 1];
937 if ((a & 0xfffc) == 0x30ec) { // a130ec
942 elprintf(EL_UIO, "m68k unmapped r8 [%06x] @%06x", a, SekPc);
946 elprintf(EL_32X, "m68k 32x r8 [%06x] %02x @%06x", a, d, SekPc);
950 u32 PicoRead16_32x(u32 a)
953 if ((a & 0xffc0) == 0x5100) { // a15100
954 d = Pico32x.regs[(a & 0x3f) / 2];
958 if ((a & 0xfffc) == 0x30ec) { // a130ec
959 d = !(a & 2) ? ('M'<<8)|'A' : ('R'<<8)|'S';
963 elprintf(EL_UIO, "m68k unmapped r16 [%06x] @%06x", a, SekPc);
967 elprintf(EL_32X, "m68k 32x r16 [%06x] %04x @%06x", a, d, SekPc);
971 void PicoWrite8_32x(u32 a, u32 d)
973 if ((a & 0xffc0) == 0x5100) { // a15100
974 u16 *r = Pico32x.regs;
976 elprintf(EL_32X, "m68k 32x w8 [%06x] %02x @%06x", a, d & 0xff, SekPc);
979 if ((d ^ r[0]) & d & P32XS_ADEN) {
981 r[0] &= ~P32XS_nRES; // causes reset if specified by this write
983 p32x_reg_write8(a, d); // forward for reset processing
988 // allow only COMM for now
989 if ((a & 0x30) == 0x20) {
996 elprintf(EL_UIO, "m68k unmapped w8 [%06x] %02x @%06x", a, d & 0xff, SekPc);
999 void PicoWrite16_32x(u32 a, u32 d)
1001 if ((a & 0xffc0) == 0x5100) { // a15100
1002 u16 *r = Pico32x.regs;
1004 elprintf(EL_UIO, "m68k 32x w16 [%06x] %04x @%06x", a, d & 0xffff, SekPc);
1007 if ((d ^ r[0]) & d & P32XS_ADEN) {
1009 r[0] &= ~P32XS_nRES; // causes reset if specified by this write
1011 p32x_reg_write16(a, d); // forward for reset processing
1016 // allow only COMM for now
1017 if ((a & 0x30) == 0x20)
1022 elprintf(EL_UIO, "m68k unmapped w16 [%06x] %04x @%06x", a, d & 0xffff, SekPc);
1025 /* quirk: in both normal and overwrite areas only nonzero values go through */
1026 #define sh2_write8_dramN(n) \
1027 if ((d & 0xff) != 0) { \
1028 u8 *dram = (u8 *)Pico32xMem->dram[n]; \
1029 dram[(a & 0x1ffff) ^ 1] = d; \
1032 static void m68k_write8_dram0_ow(u32 a, u32 d)
1034 sh2_write8_dramN(0);
1037 static void m68k_write8_dram1_ow(u32 a, u32 d)
1039 sh2_write8_dramN(1);
1042 #define sh2_write16_dramN(n) \
1043 u16 *pd = &Pico32xMem->dram[n][(a & 0x1ffff) / 2]; \
1044 if (!(a & 0x20000)) { \
1049 if (!(d & 0xff00)) d |= *pd & 0xff00; \
1050 if (!(d & 0x00ff)) d |= *pd & 0x00ff; \
1053 static void m68k_write16_dram0_ow(u32 a, u32 d)
1055 sh2_write16_dramN(0);
1058 static void m68k_write16_dram1_ow(u32 a, u32 d)
1060 sh2_write16_dramN(1);
1063 // -----------------------------------------------------------------
1065 // hint vector is writeable
1066 static void PicoWrite8_hint(u32 a, u32 d)
1068 if ((a & 0xfffc) == 0x0070) {
1069 Pico32xMem->m68k_rom[a ^ 1] = d;
1073 elprintf(EL_UIO, "m68k unmapped w8 [%06x] %02x @%06x",
1074 a, d & 0xff, SekPc);
1077 static void PicoWrite16_hint(u32 a, u32 d)
1079 if ((a & 0xfffc) == 0x0070) {
1080 ((u16 *)Pico32xMem->m68k_rom)[a/2] = d;
1084 elprintf(EL_UIO, "m68k unmapped w16 [%06x] %04x @%06x",
1085 a, d & 0xffff, SekPc);
1088 // normally not writable, but somebody could make a RAM cart
1089 static void PicoWrite8_cart(u32 a, u32 d)
1091 elprintf(EL_UIO, "m68k w8 [%06x] %02x @%06x", a, d & 0xff, SekPc);
1097 static void PicoWrite16_cart(u32 a, u32 d)
1099 elprintf(EL_UIO, "m68k w16 [%06x] %04x @%06x", a, d & 0xffff, SekPc);
1105 // same with bank, but save ram is sometimes here
1106 static u32 PicoRead8_bank(u32 a)
1108 a = (Pico32x.regs[4 / 2] << 20) | (a & 0xfffff);
1109 return m68k_read8(a);
1112 static u32 PicoRead16_bank(u32 a)
1114 a = (Pico32x.regs[4 / 2] << 20) | (a & 0xfffff);
1115 return m68k_read16(a);
1118 static void PicoWrite8_bank(u32 a, u32 d)
1120 if (!(Pico.m.sram_reg & SRR_MAPPED))
1121 elprintf(EL_UIO, "m68k w8 [%06x] %02x @%06x",
1122 a, d & 0xff, SekPc);
1124 a = (Pico32x.regs[4 / 2] << 20) | (a & 0xfffff);
1128 static void PicoWrite16_bank(u32 a, u32 d)
1130 if (!(Pico.m.sram_reg & SRR_MAPPED))
1131 elprintf(EL_UIO, "m68k w16 [%06x] %04x @%06x",
1132 a, d & 0xffff, SekPc);
1134 a = (Pico32x.regs[4 / 2] << 20) | (a & 0xfffff);
1138 static void bank_map_handler(void)
1140 cpu68k_map_set(m68k_read8_map, 0x900000, 0x9fffff, PicoRead8_bank, 1);
1141 cpu68k_map_set(m68k_read16_map, 0x900000, 0x9fffff, PicoRead16_bank, 1);
1144 static void bank_switch(int b)
1146 unsigned int rs, bank;
1149 if ((Pico.m.sram_reg & SRR_MAPPED) && bank == SRam.start) {
1154 if (bank >= Pico.romsize) {
1155 elprintf(EL_32X|EL_ANOMALY, "missing bank @ %06x", bank);
1160 // 32X ROM (unbanked, XXX: consider mirroring?)
1161 rs = (Pico.romsize + M68K_BANK_MASK) & ~M68K_BANK_MASK;
1165 cpu68k_map_set(m68k_read8_map, 0x900000, 0x900000 + rs - 1, Pico.rom + bank, 0);
1166 cpu68k_map_set(m68k_read16_map, 0x900000, 0x900000 + rs - 1, Pico.rom + bank, 0);
1168 elprintf(EL_32X, "bank %06x-%06x -> %06x", 0x900000, 0x900000 + rs - 1, bank);
1171 // setup FAME fetchmap
1172 for (rs = 0x90; rs < 0xa0; rs++)
1173 PicoCpuFM68k.Fetch[rs] = (unsigned long)Pico.rom + bank - 0x900000;
1177 // -----------------------------------------------------------------
1179 // -----------------------------------------------------------------
1182 static u32 sh2_read8_unmapped(u32 a, SH2 *sh2)
1184 elprintf_sh2(sh2, EL_32X, "unmapped r8 [%08x] %02x @%06x",
1189 static u32 sh2_read8_cs0(u32 a, SH2 *sh2)
1193 sh2_burn_cycles(sh2, 1*2);
1195 // 0x3ff00 is veridied
1196 if ((a & 0x3ff00) == 0x4000) {
1197 d = p32x_sh2reg_read16(a, sh2);
1201 if ((a & 0x3ff00) == 0x4100) {
1202 d = p32x_vdp_read16(a);
1203 sh2_poll_detect(sh2, a, SH2_STATE_VPOLL, 7);
1208 if (!sh2->is_slave && a < sizeof(Pico32xMem->sh2_rom_m))
1209 return Pico32xMem->sh2_rom_m[a ^ 1];
1210 if (sh2->is_slave && a < sizeof(Pico32xMem->sh2_rom_s))
1211 return Pico32xMem->sh2_rom_s[a ^ 1];
1213 if ((a & 0x3fe00) == 0x4200) {
1214 d = Pico32xMem->pal[(a & 0x1ff) / 2];
1218 return sh2_read8_unmapped(a, sh2);
1226 elprintf_sh2(sh2, EL_32X, "r8 [%08x] %02x @%06x",
1231 static u32 sh2_read8_da(u32 a, SH2 *sh2)
1233 return sh2->data_array[(a & 0xfff) ^ 1];
1237 static u32 sh2_read16_unmapped(u32 a, SH2 *sh2)
1239 elprintf_sh2(sh2, EL_32X, "unmapped r16 [%08x] %04x @%06x",
1244 static u32 sh2_read16_cs0(u32 a, SH2 *sh2)
1248 sh2_burn_cycles(sh2, 1*2);
1250 if ((a & 0x3ff00) == 0x4000) {
1251 d = p32x_sh2reg_read16(a, sh2);
1252 if (!(EL_LOGMASK & EL_PWM) && (a & 0x30) == 0x30) // hide PWM
1257 if ((a & 0x3ff00) == 0x4100) {
1258 d = p32x_vdp_read16(a);
1259 sh2_poll_detect(sh2, a, SH2_STATE_VPOLL, 7);
1263 if (!sh2->is_slave && a < sizeof(Pico32xMem->sh2_rom_m))
1264 return *(u16 *)(Pico32xMem->sh2_rom_m + a);
1265 if (sh2->is_slave && a < sizeof(Pico32xMem->sh2_rom_s))
1266 return *(u16 *)(Pico32xMem->sh2_rom_s + a);
1268 if ((a & 0x3fe00) == 0x4200) {
1269 d = Pico32xMem->pal[(a & 0x1ff) / 2];
1273 return sh2_read16_unmapped(a, sh2);
1276 elprintf_sh2(sh2, EL_32X, "r16 [%08x] %04x @%06x",
1281 static u32 sh2_read16_da(u32 a, SH2 *sh2)
1283 return ((u16 *)sh2->data_array)[(a & 0xfff) / 2];
1287 static void REGPARM(3) sh2_write_ignore(u32 a, u32 d, SH2 *sh2)
1292 static void REGPARM(3) sh2_write8_unmapped(u32 a, u32 d, SH2 *sh2)
1294 elprintf_sh2(sh2, EL_32X, "unmapped w8 [%08x] %02x @%06x",
1295 a, d & 0xff, sh2_pc(sh2));
1298 static void REGPARM(3) sh2_write8_cs0(u32 a, u32 d, SH2 *sh2)
1300 elprintf_sh2(sh2, EL_32X, "w8 [%08x] %02x @%06x",
1301 a, d & 0xff, sh2_pc(sh2));
1303 if (Pico32x.regs[0] & P32XS_FM) {
1304 if ((a & 0x3ff00) == 0x4100) {
1306 p32x_vdp_write8(a, d);
1311 if ((a & 0x3ff00) == 0x4000) {
1312 p32x_sh2reg_write8(a, d, sh2);
1316 sh2_write8_unmapped(a, d, sh2);
1319 static void REGPARM(3) sh2_write8_dram0(u32 a, u32 d, SH2 *sh2)
1321 sh2_write8_dramN(0);
1324 static void REGPARM(3) sh2_write8_dram1(u32 a, u32 d, SH2 *sh2)
1326 sh2_write8_dramN(1);
1329 static void REGPARM(3) sh2_write8_sdram(u32 a, u32 d, SH2 *sh2)
1331 u32 a1 = a & 0x3ffff;
1333 int t = Pico32xMem->drcblk_ram[a1 >> SH2_DRCBLK_RAM_SHIFT];
1335 sh2_drc_wcheck_ram(a, t, sh2->is_slave);
1337 Pico32xMem->sdram[a1 ^ 1] = d;
1340 static void REGPARM(3) sh2_write8_sdram_wt(u32 a, u32 d, SH2 *sh2)
1344 sh2_end_run(sh2, 32);
1346 sh2_write8_sdram(a, d, sh2);
1349 static void REGPARM(3) sh2_write8_da(u32 a, u32 d, SH2 *sh2)
1353 int id = sh2->is_slave;
1354 int t = Pico32xMem->drcblk_da[id][a1 >> SH2_DRCBLK_DA_SHIFT];
1356 sh2_drc_wcheck_da(a, t, id);
1358 sh2->data_array[a1 ^ 1] = d;
1362 static void REGPARM(3) sh2_write16_unmapped(u32 a, u32 d, SH2 *sh2)
1364 elprintf_sh2(sh2, EL_32X, "unmapped w16 [%08x] %04x @%06x",
1365 a, d & 0xffff, sh2_pc(sh2));
1368 static void REGPARM(3) sh2_write16_cs0(u32 a, u32 d, SH2 *sh2)
1370 if (((EL_LOGMASK & EL_PWM) || (a & 0x30) != 0x30)) // hide PWM
1371 elprintf_sh2(sh2, EL_32X, "w16 [%08x] %04x @%06x",
1372 a, d & 0xffff, sh2_pc(sh2));
1374 if (Pico32x.regs[0] & P32XS_FM) {
1375 if ((a & 0x3ff00) == 0x4100) {
1377 p32x_vdp_write16(a, d, sh2);
1381 if ((a & 0x3fe00) == 0x4200) {
1382 Pico32xMem->pal[(a & 0x1ff) / 2] = d;
1383 Pico32x.dirty_pal = 1;
1388 if ((a & 0x3ff00) == 0x4000) {
1389 p32x_sh2reg_write16(a, d, sh2);
1393 sh2_write16_unmapped(a, d, sh2);
1396 static void REGPARM(3) sh2_write16_dram0(u32 a, u32 d, SH2 *sh2)
1398 sh2_write16_dramN(0);
1401 static void REGPARM(3) sh2_write16_dram1(u32 a, u32 d, SH2 *sh2)
1403 sh2_write16_dramN(1);
1406 static void REGPARM(3) sh2_write16_sdram(u32 a, u32 d, SH2 *sh2)
1408 u32 a1 = a & 0x3ffff;
1410 int t = Pico32xMem->drcblk_ram[a1 >> SH2_DRCBLK_RAM_SHIFT];
1412 sh2_drc_wcheck_ram(a, t, sh2->is_slave);
1414 ((u16 *)Pico32xMem->sdram)[a1 / 2] = d;
1417 static void REGPARM(3) sh2_write16_da(u32 a, u32 d, SH2 *sh2)
1421 int id = sh2->is_slave;
1422 int t = Pico32xMem->drcblk_da[id][a1 >> SH2_DRCBLK_DA_SHIFT];
1424 sh2_drc_wcheck_da(a, t, id);
1426 ((u16 *)sh2->data_array)[a1 / 2] = d;
1430 typedef u32 (sh2_read_handler)(u32 a, SH2 *sh2);
1431 typedef void REGPARM(3) (sh2_write_handler)(u32 a, u32 d, SH2 *sh2);
1433 #define SH2MAP_ADDR2OFFS_R(a) \
1434 ((u32)(a) >> SH2_READ_SHIFT)
1436 #define SH2MAP_ADDR2OFFS_W(a) \
1437 ((u32)(a) >> SH2_WRITE_SHIFT)
1439 u32 REGPARM(2) p32x_sh2_read8(u32 a, SH2 *sh2)
1441 const sh2_memmap *sh2_map = sh2->read8_map;
1444 sh2_map += SH2MAP_ADDR2OFFS_R(a);
1446 if (map_flag_set(p))
1447 return ((sh2_read_handler *)(p << 1))(a, sh2);
1449 return *(u8 *)((p << 1) + ((a & sh2_map->mask) ^ 1));
1452 u32 REGPARM(2) p32x_sh2_read16(u32 a, SH2 *sh2)
1454 const sh2_memmap *sh2_map = sh2->read16_map;
1457 sh2_map += SH2MAP_ADDR2OFFS_R(a);
1459 if (map_flag_set(p))
1460 return ((sh2_read_handler *)(p << 1))(a, sh2);
1462 return *(u16 *)((p << 1) + ((a & sh2_map->mask) & ~1));
1465 u32 REGPARM(2) p32x_sh2_read32(u32 a, SH2 *sh2)
1467 const sh2_memmap *sh2_map = sh2->read16_map;
1468 sh2_read_handler *handler;
1472 offs = SH2MAP_ADDR2OFFS_R(a);
1475 if (!map_flag_set(p)) {
1476 // XXX: maybe 32bit access instead with ror?
1477 u16 *pd = (u16 *)((p << 1) + ((a & sh2_map->mask) & ~1));
1478 return (pd[0] << 16) | pd[1];
1481 if (offs == SH2MAP_ADDR2OFFS_R(0xffffc000))
1482 return sh2_peripheral_read32(a, sh2);
1484 handler = (sh2_read_handler *)(p << 1);
1485 return (handler(a, sh2) << 16) | handler(a + 2, sh2);
1488 void REGPARM(3) p32x_sh2_write8(u32 a, u32 d, SH2 *sh2)
1490 const void **sh2_wmap = sh2->write8_tab;
1491 sh2_write_handler *wh;
1493 wh = sh2_wmap[SH2MAP_ADDR2OFFS_W(a)];
1497 void REGPARM(3) p32x_sh2_write16(u32 a, u32 d, SH2 *sh2)
1499 const void **sh2_wmap = sh2->write16_tab;
1500 sh2_write_handler *wh;
1502 wh = sh2_wmap[SH2MAP_ADDR2OFFS_W(a)];
1506 void REGPARM(3) p32x_sh2_write32(u32 a, u32 d, SH2 *sh2)
1508 const void **sh2_wmap = sh2->write16_tab;
1509 sh2_write_handler *wh;
1512 offs = SH2MAP_ADDR2OFFS_W(a);
1514 if (offs == SH2MAP_ADDR2OFFS_W(0xffffc000)) {
1515 sh2_peripheral_write32(a, d, sh2);
1519 wh = sh2_wmap[offs];
1520 wh(a, d >> 16, sh2);
1524 // -----------------------------------------------------------------
1526 static const u16 msh2_code[] = {
1527 // trap instructions
1528 0xaffe, // bra <self>
1530 // have to wait a bit until m68k initial program finishes clearing stuff
1531 // to avoid races with game SH2 code, like in Tempo
1532 0xd004, // mov.l @(_m_ok,pc), r0
1533 0xd105, // mov.l @(_cnt,pc), r1
1534 0xd205, // mov.l @(_start,pc), r2
1535 0x71ff, // add #-1, r1
1536 0x4115, // cmp/pl r1
1538 0xc208, // mov.l r0, @(h'20,gbr)
1539 0x6822, // mov.l @r2, r8
1542 ('M'<<8)|'_', ('O'<<8)|'K',
1544 0x2200, 0x03e0 // master start pointer in ROM
1547 static const u16 ssh2_code[] = {
1548 0xaffe, // bra <self>
1550 // code to wait for master, in case authentic master BIOS is used
1551 0xd104, // mov.l @(_m_ok,pc), r1
1552 0xd206, // mov.l @(_start,pc), r2
1553 0xc608, // mov.l @(h'20,gbr), r0
1554 0x3100, // cmp/eq r0, r1
1556 0xd003, // mov.l @(_s_ok,pc), r0
1557 0xc209, // mov.l r0, @(h'24,gbr)
1558 0x6822, // mov.l @r2, r8
1561 ('M'<<8)|'_', ('O'<<8)|'K',
1562 ('S'<<8)|'_', ('O'<<8)|'K',
1563 0x2200, 0x03e4 // slave start pointer in ROM
1566 #define HWSWAP(x) (((u16)(x) << 16) | ((x) >> 16))
1567 static void get_bios(void)
1574 if (p32x_bios_g != NULL) {
1575 elprintf(EL_STATUS|EL_32X, "32x: using supplied 68k BIOS");
1576 Byteswap(Pico32xMem->m68k_rom, p32x_bios_g, sizeof(Pico32xMem->m68k_rom));
1580 ps = (u16 *)Pico32xMem->m68k_rom;
1582 for (i = 1; i < 0xc0/4; i++)
1583 pl[i] = HWSWAP(0x880200 + (i - 1) * 6);
1586 for (i = 0xc0/2; i < 0x100/2; i++)
1590 ps[0xc0/2] = 0x46fc;
1591 ps[0xc2/2] = 0x2700; // move #0x2700,sr
1592 ps[0xfe/2] = 0x60fe; // jump to self
1594 ps[0xfe/2] = 0x4e75; // rts
1597 // fill remaining m68k_rom page with game ROM
1598 memcpy(Pico32xMem->m68k_rom_bank + sizeof(Pico32xMem->m68k_rom),
1599 Pico.rom + sizeof(Pico32xMem->m68k_rom),
1600 sizeof(Pico32xMem->m68k_rom_bank) - sizeof(Pico32xMem->m68k_rom));
1603 if (p32x_bios_m != NULL) {
1604 elprintf(EL_STATUS|EL_32X, "32x: using supplied master SH2 BIOS");
1605 Byteswap(Pico32xMem->sh2_rom_m, p32x_bios_m, sizeof(Pico32xMem->sh2_rom_m));
1608 pl = (u32 *)Pico32xMem->sh2_rom_m;
1610 // fill exception vector table to our trap address
1611 for (i = 0; i < 128; i++)
1612 pl[i] = HWSWAP(0x200);
1615 memcpy(Pico32xMem->sh2_rom_m + 0x200, msh2_code, sizeof(msh2_code));
1618 pl[1] = pl[3] = HWSWAP(0x6040000);
1620 pl[0] = pl[2] = HWSWAP(0x204);
1624 if (p32x_bios_s != NULL) {
1625 elprintf(EL_STATUS|EL_32X, "32x: using supplied slave SH2 BIOS");
1626 Byteswap(Pico32xMem->sh2_rom_s, p32x_bios_s, sizeof(Pico32xMem->sh2_rom_s));
1629 pl = (u32 *)Pico32xMem->sh2_rom_s;
1631 // fill exception vector table to our trap address
1632 for (i = 0; i < 128; i++)
1633 pl[i] = HWSWAP(0x200);
1636 memcpy(Pico32xMem->sh2_rom_s + 0x200, ssh2_code, sizeof(ssh2_code));
1639 pl[1] = pl[3] = HWSWAP(0x603f800);
1641 pl[0] = pl[2] = HWSWAP(0x204);
1645 #define MAP_MEMORY(m) ((uptr)(m) >> 1)
1646 #define MAP_HANDLER(h) ( ((uptr)(h) >> 1) | ((uptr)1 << (sizeof(uptr) * 8 - 1)) )
1648 static sh2_memmap sh2_read8_map[0x80], sh2_read16_map[0x80];
1649 // for writes we are using handlers only
1650 static sh2_write_handler *sh2_write8_map[0x80], *sh2_write16_map[0x80];
1652 void Pico32xSwapDRAM(int b)
1654 cpu68k_map_set(m68k_read8_map, 0x840000, 0x85ffff, Pico32xMem->dram[b], 0);
1655 cpu68k_map_set(m68k_read16_map, 0x840000, 0x85ffff, Pico32xMem->dram[b], 0);
1656 cpu68k_map_set(m68k_read8_map, 0x860000, 0x87ffff, Pico32xMem->dram[b], 0);
1657 cpu68k_map_set(m68k_read16_map, 0x860000, 0x87ffff, Pico32xMem->dram[b], 0);
1658 cpu68k_map_set(m68k_write8_map, 0x840000, 0x87ffff,
1659 b ? m68k_write8_dram1_ow : m68k_write8_dram0_ow, 1);
1660 cpu68k_map_set(m68k_write16_map, 0x840000, 0x87ffff,
1661 b ? m68k_write16_dram1_ow : m68k_write16_dram0_ow, 1);
1664 sh2_read8_map[0x04/2].addr = sh2_read8_map[0x24/2].addr =
1665 sh2_read16_map[0x04/2].addr = sh2_read16_map[0x24/2].addr = MAP_MEMORY(Pico32xMem->dram[b]);
1667 sh2_write8_map[0x04/2] = sh2_write8_map[0x24/2] = b ? sh2_write8_dram1 : sh2_write8_dram0;
1668 sh2_write16_map[0x04/2] = sh2_write16_map[0x24/2] = b ? sh2_write16_dram1 : sh2_write16_dram0;
1671 void PicoMemSetup32x(void)
1676 Pico32xMem = plat_mmap(0x06000000, sizeof(*Pico32xMem), 0, 0);
1677 if (Pico32xMem == NULL) {
1678 elprintf(EL_STATUS, "OOM");
1684 // cartridge area becomes unmapped
1685 // XXX: we take the easy way and don't unmap ROM,
1686 // so that we can avoid handling the RV bit.
1687 // m68k_map_unmap(0x000000, 0x3fffff);
1690 rs = sizeof(Pico32xMem->m68k_rom_bank);
1691 cpu68k_map_set(m68k_read8_map, 0x000000, rs - 1, Pico32xMem->m68k_rom_bank, 0);
1692 cpu68k_map_set(m68k_read16_map, 0x000000, rs - 1, Pico32xMem->m68k_rom_bank, 0);
1693 cpu68k_map_set(m68k_write8_map, 0x000000, rs - 1, PicoWrite8_hint, 1); // TODO verify
1694 cpu68k_map_set(m68k_write16_map, 0x000000, rs - 1, PicoWrite16_hint, 1);
1696 // 32X ROM (unbanked, XXX: consider mirroring?)
1697 rs = (Pico.romsize + M68K_BANK_MASK) & ~M68K_BANK_MASK;
1700 cpu68k_map_set(m68k_read8_map, 0x880000, 0x880000 + rs - 1, Pico.rom, 0);
1701 cpu68k_map_set(m68k_read16_map, 0x880000, 0x880000 + rs - 1, Pico.rom, 0);
1702 cpu68k_map_set(m68k_write8_map, 0x880000, 0x880000 + rs - 1, PicoWrite8_cart, 1);
1703 cpu68k_map_set(m68k_write16_map, 0x880000, 0x880000 + rs - 1, PicoWrite16_cart, 1);
1705 // setup FAME fetchmap
1706 PicoCpuFM68k.Fetch[0] = (unsigned long)Pico32xMem->m68k_rom;
1707 for (rs = 0x88; rs < 0x90; rs++)
1708 PicoCpuFM68k.Fetch[rs] = (unsigned long)Pico.rom - 0x880000;
1713 cpu68k_map_set(m68k_write8_map, 0x900000, 0x9fffff, PicoWrite8_bank, 1);
1714 cpu68k_map_set(m68k_write16_map, 0x900000, 0x9fffff, PicoWrite16_bank, 1);
1717 cpu68k_map_set(m68k_read8_map, 0xa10000, 0xa1ffff, PicoRead8_32x_on, 1);
1718 cpu68k_map_set(m68k_read16_map, 0xa10000, 0xa1ffff, PicoRead16_32x_on, 1);
1719 cpu68k_map_set(m68k_write8_map, 0xa10000, 0xa1ffff, PicoWrite8_32x_on, 1);
1720 cpu68k_map_set(m68k_write16_map, 0xa10000, 0xa1ffff, PicoWrite16_32x_on, 1);
1722 // SH2 maps: A31,A30,A29,CS1,CS0
1723 // all unmapped by default
1724 for (i = 0; i < ARRAY_SIZE(sh2_read8_map); i++) {
1725 sh2_read8_map[i].addr = MAP_HANDLER(sh2_read8_unmapped);
1726 sh2_read16_map[i].addr = MAP_HANDLER(sh2_read16_unmapped);
1729 for (i = 0; i < ARRAY_SIZE(sh2_write8_map); i++) {
1730 sh2_write8_map[i] = sh2_write8_unmapped;
1731 sh2_write16_map[i] = sh2_write16_unmapped;
1735 for (i = 0x40; i <= 0x5f; i++) {
1736 sh2_write8_map[i >> 1] =
1737 sh2_write16_map[i >> 1] = sh2_write_ignore;
1741 sh2_read8_map[0x00/2].addr = sh2_read8_map[0x20/2].addr = MAP_HANDLER(sh2_read8_cs0);
1742 sh2_read16_map[0x00/2].addr = sh2_read16_map[0x20/2].addr = MAP_HANDLER(sh2_read16_cs0);
1743 sh2_write8_map[0x00/2] = sh2_write8_map[0x20/2] = sh2_write8_cs0;
1744 sh2_write16_map[0x00/2] = sh2_write16_map[0x20/2] = sh2_write16_cs0;
1746 sh2_read8_map[0x02/2].addr = sh2_read8_map[0x22/2].addr =
1747 sh2_read16_map[0x02/2].addr = sh2_read16_map[0x22/2].addr = MAP_MEMORY(Pico.rom);
1748 sh2_read8_map[0x02/2].mask = sh2_read8_map[0x22/2].mask =
1749 sh2_read16_map[0x02/2].mask = sh2_read16_map[0x22/2].mask = 0x3fffff; // FIXME
1750 // CS2 - DRAM - done by Pico32xSwapDRAM()
1751 sh2_read8_map[0x04/2].mask = sh2_read8_map[0x24/2].mask =
1752 sh2_read16_map[0x04/2].mask = sh2_read16_map[0x24/2].mask = 0x01ffff;
1754 sh2_read8_map[0x06/2].addr = sh2_read8_map[0x26/2].addr =
1755 sh2_read16_map[0x06/2].addr = sh2_read16_map[0x26/2].addr = MAP_MEMORY(Pico32xMem->sdram);
1756 sh2_write8_map[0x06/2] = sh2_write8_sdram;
1757 sh2_write8_map[0x26/2] = sh2_write8_sdram_wt;
1758 sh2_write16_map[0x06/2] = sh2_write16_map[0x26/2] = sh2_write16_sdram;
1759 sh2_read8_map[0x06/2].mask = sh2_read8_map[0x26/2].mask =
1760 sh2_read16_map[0x06/2].mask = sh2_read16_map[0x26/2].mask = 0x03ffff;
1762 sh2_read8_map[0xc0/2].addr = MAP_HANDLER(sh2_read8_da);
1763 sh2_read16_map[0xc0/2].addr = MAP_HANDLER(sh2_read16_da);
1764 sh2_write8_map[0xc0/2] = sh2_write8_da;
1765 sh2_write16_map[0xc0/2] = sh2_write16_da;
1767 sh2_read8_map[0xff/2].addr = MAP_HANDLER(sh2_peripheral_read8);
1768 sh2_read16_map[0xff/2].addr = MAP_HANDLER(sh2_peripheral_read16);
1769 sh2_write8_map[0xff/2] = sh2_peripheral_write8;
1770 sh2_write16_map[0xff/2] = sh2_peripheral_write16;
1772 // map DRAM area, both 68k and SH2
1775 msh2.read8_map = ssh2.read8_map = sh2_read8_map;
1776 msh2.read16_map = ssh2.read16_map = sh2_read16_map;
1777 msh2.write8_tab = ssh2.write8_tab = (const void **)(void *)sh2_write8_map;
1778 msh2.write16_tab = ssh2.write16_tab = (const void **)(void *)sh2_write16_map;
1780 sh2_drc_mem_setup(&msh2);
1781 sh2_drc_mem_setup(&ssh2);
1784 void Pico32xMemStateLoaded(void)
1786 bank_switch(Pico32x.regs[4 / 2]);
1787 Pico32xSwapDRAM((Pico32x.vdp_regs[0x0a / 2] & P32XV_FS) ^ P32XV_FS);
1788 memset(Pico32xMem->pwm, 0, sizeof(Pico32xMem->pwm));
1789 Pico32x.dirty_pal = 1;
1791 Pico32x.emu_flags &= ~(P32XF_68KCPOLL | P32XF_68KVPOLL);
1792 memset(&m68k_poll, 0, sizeof(m68k_poll));
1794 msh2.poll_addr = msh2.poll_cycles = msh2.poll_cnt = 0;
1796 ssh2.poll_addr = ssh2.poll_cycles = ssh2.poll_cnt = 0;
1798 sh2_drc_flush_all();
1801 // vim:shiftwidth=2:ts=2:expandtab