#include "../pico_int.h"\r
#include "../memory.h"\r
\r
-#include "gfx_cd.h"\r
-#include "pcm.h"\r
-\r
uptr s68k_read8_map [0x1000000 >> M68K_MEM_SHIFT];\r
uptr s68k_read16_map [0x1000000 >> M68K_MEM_SHIFT];\r
uptr s68k_write8_map [0x1000000 >> M68K_MEM_SHIFT];\r
\r
// provided by ASM code:\r
#ifdef _ASM_CD_MEMORY_C\r
-u32 PicoReadM68k8_io(u32 a);\r
-u32 PicoReadM68k16_io(u32 a);\r
-void PicoWriteM68k8_io(u32 a, u32 d);\r
-void PicoWriteM68k16_io(u32 a, u32 d);\r
-\r
u32 PicoReadS68k8_pr(u32 a);\r
u32 PicoReadS68k16_pr(u32 a);\r
void PicoWriteS68k8_pr(u32 a, u32 d);\r
void PicoWriteS68k16_dec_m2b1(u32 a, u32 d);\r
#endif\r
\r
-static void remap_prg_window(void);\r
-static void remap_word_ram(int r3);\r
+static void remap_prg_window(u32 r1, u32 r3);\r
+static void remap_word_ram(u32 r3);\r
\r
// poller detection\r
#define POLL_LIMIT 16\r
-#define POLL_CYCLES 124\r
-unsigned int s68k_poll_adclk, s68k_poll_cnt;\r
+#define POLL_CYCLES 64\r
+\r
+void m68k_comm_check(u32 a)\r
+{\r
+ pcd_sync_s68k(SekCyclesDone(), 0);\r
+ if (a >= 0x0e && !Pico_mcd->m.need_sync) {\r
+ // there are cases when slave updates comm and only switches RAM\r
+ // over after that (mcd1b), so there must be a resync..\r
+ SekEndRun(64);\r
+ Pico_mcd->m.need_sync = 1;\r
+ }\r
+ if (SekNotPolling || a != Pico_mcd->m.m68k_poll_a) {\r
+ Pico_mcd->m.m68k_poll_a = a;\r
+ Pico_mcd->m.m68k_poll_cnt = 0;\r
+ SekNotPolling = 0;\r
+ return;\r
+ }\r
+ Pico_mcd->m.m68k_poll_cnt++;\r
+}\r
\r
#ifndef _ASM_CD_MEMORY_C\r
static u32 m68k_reg_read16(u32 a)\r
{\r
- u32 d=0;\r
+ u32 d = 0;\r
a &= 0x3e;\r
\r
switch (a) {\r
case 0:\r
- d = ((Pico_mcd->s68k_regs[0x33]<<13)&0x8000) | Pico_mcd->m.busreq; // here IFL2 is always 0, just like in Gens\r
+ // here IFL2 is always 0, just like in Gens\r
+ d = ((Pico_mcd->s68k_regs[0x33] << 13) & 0x8000)\r
+ | Pico_mcd->m.busreq;\r
goto end;\r
case 2:\r
+ m68k_comm_check(a);\r
d = (Pico_mcd->s68k_regs[a]<<8) | (Pico_mcd->s68k_regs[a+1]&0xc7);\r
elprintf(EL_CDREG3, "m68k_regs r3: %02x @%06x", (u8)d, SekPc);\r
goto end;\r
d = *(u16 *)(Pico_mcd->bios + 0x72);\r
goto end;\r
case 8:\r
- d = Read_CDC_Host(0);\r
+ d = cdc_host_r();\r
goto end;\r
case 0xA:\r
elprintf(EL_UIO, "m68k FIXME: reserved read");\r
\r
if (a < 0x30) {\r
// comm flag/cmd/status (0xE-0x2F)\r
+ m68k_comm_check(a);\r
d = (Pico_mcd->s68k_regs[a]<<8) | Pico_mcd->s68k_regs[a+1];\r
goto end;\r
}\r
elprintf(EL_UIO, "m68k_regs FIXME invalid read @ %02x", a);\r
\r
end:\r
-\r
return d;\r
}\r
#endif\r
switch (a) {\r
case 0:\r
d &= 1;\r
- if ((d&1) && (Pico_mcd->s68k_regs[0x33]&(1<<2))) { elprintf(EL_INTS, "m68k: s68k irq 2"); SekInterruptS68k(2); }\r
+ if (d && (Pico_mcd->s68k_regs[0x33] & PCDS_IEN2)) {\r
+ elprintf(EL_INTS, "m68k: s68k irq 2");\r
+ pcd_sync_s68k(SekCyclesDone(), 0);\r
+ SekInterruptS68k(2);\r
+ }\r
return;\r
case 1:\r
d &= 3;\r
- if (!(d&1)) Pico_mcd->m.state_flags |= 1; // reset pending, needed to be sure we fetch the right vectors on reset\r
- if ( (Pico_mcd->m.busreq&1) != (d&1)) elprintf(EL_INTSW, "m68k: s68k reset %i", !(d&1));\r
- if ( (Pico_mcd->m.busreq&2) != (d&2)) elprintf(EL_INTSW, "m68k: s68k brq %i", (d&2)>>1);\r
- if ((Pico_mcd->m.state_flags&1) && (d&3)==1) {\r
- SekResetS68k(); // S68k comes out of RESET or BRQ state\r
- Pico_mcd->m.state_flags&=~1;\r
- elprintf(EL_CDREGS, "m68k: resetting s68k, cycles=%i", SekCyclesLeft);\r
- }\r
+ dold = Pico_mcd->m.busreq;\r
if (!(d & 1))\r
- d |= 2; // verified: reset also gives bus\r
- if ((d ^ Pico_mcd->m.busreq) & 2)\r
- remap_prg_window();\r
+ d |= 2; // verified: can't release bus on reset\r
+ if (dold == d)\r
+ return;\r
+\r
+ pcd_sync_s68k(SekCyclesDone(), 0);\r
+\r
+ if ((dold ^ d) & 1)\r
+ elprintf(EL_INTSW, "m68k: s68k reset %i", !(d&1));\r
+ if (!(d & 1))\r
+ Pico_mcd->m.state_flags |= PCD_ST_S68K_RST;\r
+ else if (d == 1 && (Pico_mcd->m.state_flags & PCD_ST_S68K_RST)) {\r
+ Pico_mcd->m.state_flags &= ~PCD_ST_S68K_RST;\r
+ elprintf(EL_CDREGS, "m68k: resetting s68k");\r
+ SekResetS68k();\r
+ }\r
+ if ((dold ^ d) & 2) {\r
+ elprintf(EL_INTSW, "m68k: s68k brq %i", d >> 1);\r
+ remap_prg_window(d, Pico_mcd->s68k_regs[3]);\r
+ }\r
Pico_mcd->m.busreq = d;\r
return;\r
case 2:\r
case 3:\r
dold = Pico_mcd->s68k_regs[3];\r
elprintf(EL_CDREG3, "m68k_regs w3: %02x @%06x", (u8)d, SekPc);\r
- //if ((Pico_mcd->s68k_regs[3]&4) != (d&4)) dprintf("m68k: ram mode %i mbit", (d&4) ? 1 : 2);\r
- //if ((Pico_mcd->s68k_regs[3]&2) != (d&2)) dprintf("m68k: %s", (d&4) ? ((d&2) ? "word swap req" : "noop?") :\r
- // ((d&2) ? "word ram to s68k" : "word ram to m68k"));\r
- if (dold & 4) { // 1M mode\r
- d ^= 2; // writing 0 to DMNA actually sets it, 1 does nothing\r
- } else {\r
- if ((d ^ dold) & d & 2) { // DMNA is being set\r
- dold &= ~1; // return word RAM to s68k\r
- /* Silpheed hack: bset(w3), r3, btst, bne, r3 */\r
- SekEndRun(20+16+10+12+16);\r
- }\r
- }\r
- Pico_mcd->s68k_regs[3] = (d & 0xc2) | (dold & 0x1f);\r
if ((d ^ dold) & 0xc0) {\r
- elprintf(EL_CDREGS, "m68k: prg bank: %i -> %i", (Pico_mcd->s68k_regs[a]>>6), ((d>>6)&3));\r
- remap_prg_window();\r
+ elprintf(EL_CDREGS, "m68k: prg bank: %i -> %i",\r
+ (Pico_mcd->s68k_regs[a]>>6), ((d>>6)&3));\r
+ remap_prg_window(Pico_mcd->m.busreq, d);\r
}\r
-#ifdef USE_POLL_DETECT\r
- if ((s68k_poll_adclk&0xfe) == 2 && s68k_poll_cnt > POLL_LIMIT) {\r
- SekSetStopS68k(0); s68k_poll_adclk = 0;\r
- elprintf(EL_CDPOLL, "s68k poll release, a=%02x", a);\r
+\r
+ // 2M mode state is tracked regardless of current mode\r
+ if (d & 2) {\r
+ Pico_mcd->m.dmna_ret_2m |= 2;\r
+ Pico_mcd->m.dmna_ret_2m &= ~1;\r
}\r
-#endif\r
- return;\r
+ if (dold & 4) { // 1M mode\r
+ d ^= 2; // 0 sets DMNA, 1 does nothing\r
+ d = (d & 0xc2) | (dold & 0x1f);\r
+ }\r
+ else\r
+ d = (d & 0xc0) | (dold & 0x1c) | Pico_mcd->m.dmna_ret_2m;\r
+\r
+ goto write_comm;\r
case 6:\r
Pico_mcd->bios[0x72 + 1] = d; // simple hint vector changer\r
return;\r
elprintf(EL_CDREGS, "hint vector set to %04x%04x",\r
((u16 *)Pico_mcd->bios)[0x70/2], ((u16 *)Pico_mcd->bios)[0x72/2]);\r
return;\r
- case 0xf:\r
- d = (d << 1) | ((d >> 7) & 1); // rol8 1 (special case)\r
- case 0xe:\r
- //dprintf("m68k: comm flag: %02x", d);\r
- Pico_mcd->s68k_regs[0xe] = d;\r
-#ifdef USE_POLL_DETECT\r
- if ((s68k_poll_adclk&0xfe) == 0xe && s68k_poll_cnt > POLL_LIMIT) {\r
- SekSetStopS68k(0); s68k_poll_adclk = 0;\r
- elprintf(EL_CDPOLL, "s68k poll release, a=%02x", a);\r
- }\r
-#endif\r
- return;\r
+ case 0x0f:\r
+ a = 0x0e;\r
+ case 0x0e:\r
+ goto write_comm;\r
}\r
\r
- if ((a&0xf0) == 0x10) {\r
- Pico_mcd->s68k_regs[a] = d;\r
-#ifdef USE_POLL_DETECT\r
- if ((a&0xfe) == (s68k_poll_adclk&0xfe) && s68k_poll_cnt > POLL_LIMIT) {\r
- SekSetStopS68k(0); s68k_poll_adclk = 0;\r
- elprintf(EL_CDPOLL, "s68k poll release, a=%02x", a);\r
- }\r
-#endif\r
- return;\r
- }\r
+ if ((a&0xf0) == 0x10)\r
+ goto write_comm;\r
\r
elprintf(EL_UIO, "m68k FIXME: invalid write? [%02x] %02x", a, d);\r
+ return;\r
+\r
+write_comm:\r
+ if (d == Pico_mcd->s68k_regs[a])\r
+ return;\r
+\r
+ pcd_sync_s68k(SekCyclesDone(), 0);\r
+ Pico_mcd->s68k_regs[a] = d;\r
+ if (Pico_mcd->m.s68k_poll_a == (a & ~1))\r
+ {\r
+ if (Pico_mcd->m.s68k_poll_cnt > POLL_LIMIT) {\r
+ elprintf(EL_CDPOLL, "s68k poll release, a=%02x", a);\r
+ SekSetStopS68k(0);\r
+ }\r
+ Pico_mcd->m.s68k_poll_a = 0;\r
+ }\r
}\r
\r
-#ifndef _ASM_CD_MEMORY_C\r
-static\r
-#endif\r
u32 s68k_poll_detect(u32 a, u32 d)\r
{\r
#ifdef USE_POLL_DETECT\r
- // needed mostly for Cyclone, which doesn't always check it's cycle counter\r
- if (SekIsStoppedS68k()) return d;\r
- // polling detection\r
- if (a == (s68k_poll_adclk&0xff)) {\r
- unsigned int clkdiff = SekCyclesDoneS68k() - (s68k_poll_adclk>>8);\r
+ u32 cycles, cnt = 0;\r
+ if (SekIsStoppedS68k())\r
+ return d;\r
+\r
+ cycles = SekCyclesDoneS68k();\r
+ if (!SekNotPolling && a == Pico_mcd->m.s68k_poll_a) {\r
+ u32 clkdiff = cycles - Pico_mcd->m.s68k_poll_clk;\r
if (clkdiff <= POLL_CYCLES) {\r
- s68k_poll_cnt++;\r
- //printf("-- diff: %u, cnt = %i\n", clkdiff, s68k_poll_cnt);\r
- if (s68k_poll_cnt > POLL_LIMIT) {\r
+ cnt = Pico_mcd->m.s68k_poll_cnt + 1;\r
+ //printf("-- diff: %u, cnt = %i\n", clkdiff, cnt);\r
+ if (Pico_mcd->m.s68k_poll_cnt > POLL_LIMIT) {\r
SekSetStopS68k(1);\r
- elprintf(EL_CDPOLL, "s68k poll detected @ %06x, a=%02x", SekPcS68k, a);\r
+ elprintf(EL_CDPOLL, "s68k poll detected @%06x, a=%02x",\r
+ SekPcS68k, a);\r
}\r
- s68k_poll_adclk = (SekCyclesDoneS68k() << 8) | a;\r
- return d;\r
}\r
}\r
- s68k_poll_adclk = (SekCyclesDoneS68k() << 8) | a;\r
- s68k_poll_cnt = 0;\r
+ Pico_mcd->m.s68k_poll_a = a;\r
+ Pico_mcd->m.s68k_poll_clk = cycles;\r
+ Pico_mcd->m.s68k_poll_cnt = cnt;\r
+ SekNotPollingS68k = 0;\r
#endif\r
return d;\r
}\r
elprintf(EL_CDREG3, "s68k_regs r3: %02x @%06x", (u8)d, SekPcS68k);\r
return s68k_poll_detect(a, d);\r
case 6:\r
- return CDC_Read_Reg();\r
+ return cdc_reg_r();\r
case 8:\r
- return Read_CDC_Host(1); // Gens returns 0 here on byte reads\r
+ return cdc_host_r();\r
case 0xC:\r
d = SekCyclesDoneS68k() - Pico_mcd->m.stopwatch_base_c;\r
d /= 384;\r
{\r
// Warning: d might have upper bits set\r
switch (a) {\r
+ case 1:\r
+ if (!(d & 1))\r
+ pcd_soft_reset();\r
+ return;\r
case 2:\r
return; // only m68k can change WP\r
case 3: {\r
elprintf(EL_CDREG3, "s68k_regs w3: %02x @%06x", (u8)d, SekPcS68k);\r
d &= 0x1d;\r
d |= dold & 0xc2;\r
+\r
+ // 2M mode state\r
+ if (d & 1) {\r
+ Pico_mcd->m.dmna_ret_2m |= 1;\r
+ Pico_mcd->m.dmna_ret_2m &= ~2; // DMNA clears\r
+ }\r
+\r
if (d & 4)\r
{\r
- if ((d ^ dold) & 0x1d) {\r
- d &= ~2; // in case of mode or bank change we clear DMNA (m68k req) bit\r
- remap_word_ram(d);\r
- }\r
if (!(dold & 4)) {\r
elprintf(EL_CDREG3, "wram mode 2M->1M");\r
wram_2M_to_1M(Pico_mcd->word_ram2M);\r
}\r
+\r
+ if ((d ^ dold) & 0x1d)\r
+ remap_word_ram(d);\r
+\r
+ if ((d ^ dold) & 0x05)\r
+ d &= ~2; // clear DMNA - swap complete\r
}\r
else\r
{\r
if (dold & 4) {\r
elprintf(EL_CDREG3, "wram mode 1M->2M");\r
- if (!(d&1)) { // it didn't set the ret bit, which means it doesn't want to give WRAM to m68k\r
- d &= ~3;\r
- d |= (dold&1) ? 2 : 1; // then give it to the one which had bank0 in 1M mode\r
- }\r
wram_1M_to_2M(Pico_mcd->word_ram2M);\r
remap_word_ram(d);\r
}\r
- // s68k can only set RET, writing 0 has no effect\r
- else if ((dold ^ d) & d & 1) { // RET being set\r
- SekEndRunS68k(20+16+10+12+16); // see DMNA case\r
- } else\r
- d |= dold & 1;\r
- if (d & 1)\r
- d &= ~2; // DMNA clears\r
+ d = (d & ~3) | Pico_mcd->m.dmna_ret_2m;\r
}\r
- break;\r
+ goto write_comm;\r
}\r
case 4:\r
elprintf(EL_CDREGS, "s68k CDC dest: %x", d&7);\r
//dprintf("s68k CDC reg addr: %x", d&0xf);\r
break;\r
case 7:\r
- CDC_Write_Reg(d);\r
+ cdc_reg_w(d & 0xff);\r
return;\r
case 0xa:\r
elprintf(EL_CDREGS, "s68k set CDC dma addr");\r
// does this also reset internal 384 cycle counter?\r
Pico_mcd->m.stopwatch_base_c = SekCyclesDoneS68k();\r
return;\r
- case 0xe:\r
- Pico_mcd->s68k_regs[0xf] = (d>>1) | (d<<7); // ror8 1, Gens note: Dragons lair\r
- return;\r
+ case 0x0e:\r
+ a = 0x0f;\r
+ case 0x0f:\r
+ goto write_comm;\r
case 0x31: // 384 cycle int3 timer\r
d &= 0xff;\r
elprintf(EL_CDREGS|EL_CD, "s68k set int3 timer: %02x", d);\r
elprintf(EL_CDREGS|EL_CD, "s68k irq mask: %02x", d);\r
d &= 0x7e;\r
if ((d ^ Pico_mcd->s68k_regs[0x33]) & d & PCDS_IEN4) {\r
- if (Pico_mcd->s68k_regs[0x37] & 4)\r
- CDD_Export_Status();\r
+ // XXX: emulate pending irq instead?\r
+ if (Pico_mcd->s68k_regs[0x37] & 4) {\r
+ elprintf(EL_INTS, "cdd export irq 4 (unmask)");\r
+ SekInterruptS68k(4);\r
+ }\r
}\r
break;\r
case 0x34: // fader\r
return; // d/m bit is unsetable\r
case 0x37: {\r
u32 d_old = Pico_mcd->s68k_regs[0x37];\r
- Pico_mcd->s68k_regs[0x37] = d&7;\r
+ Pico_mcd->s68k_regs[0x37] = d & 7;\r
if ((d&4) && !(d_old&4)) {\r
- CDD_Export_Status();\r
+ // ??\r
+ pcd_event_schedule_s68k(PCD_EVENT_CDC, 12500000/75);\r
+\r
+ if (Pico_mcd->s68k_regs[0x33] & PCDS_IEN4) {\r
+ elprintf(EL_INTS, "cdd export irq 4");\r
+ SekInterruptS68k(4);\r
+ }\r
}\r
return;\r
}\r
case 0x4b:\r
- Pico_mcd->s68k_regs[a] = (u8) d;\r
- CDD_Import_Command();\r
+ Pico_mcd->s68k_regs[a] = 0; // (u8) d; ?\r
+ cdd_process();\r
+ {\r
+ static const char *nm[] =\r
+ { "stat", "stop", "read_toc", "play",\r
+ "seek", "???", "pause", "resume",\r
+ "ff", "fr", "tjump", "???",\r
+ "close","open", "???", "???" };\r
+ u8 *c = &Pico_mcd->s68k_regs[0x42];\r
+ u8 *s = &Pico_mcd->s68k_regs[0x38];\r
+ elprintf(EL_CD,\r
+ "CDD command: %02x %02x %02x %02x %02x %02x %02x %02x %12s",\r
+ c[0], c[1], c[2], c[3], c[4], c[5], c[6], c[7], nm[c[0] & 0x0f]);\r
+ elprintf(EL_CD,\r
+ "CDD status: %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x",\r
+ s[0], s[1], s[2], s[3], s[4], s[5], s[6], s[7], s[8], s[9]);\r
+ }\r
+ return;\r
+ case 0x58:\r
return;\r
}\r
\r
+ if ((a&0x1f0) == 0x20)\r
+ goto write_comm;\r
+\r
if ((a&0x1f0) == 0x10 || (a >= 0x38 && a < 0x42))\r
{\r
elprintf(EL_UIO, "s68k FIXME: invalid write @ %02x?", a);\r
}\r
\r
Pico_mcd->s68k_regs[a] = (u8) d;\r
+ return;\r
+\r
+write_comm:\r
+ Pico_mcd->s68k_regs[a] = (u8) d;\r
+ if (Pico_mcd->m.m68k_poll_cnt)\r
+ SekEndRunS68k(0);\r
+ Pico_mcd->m.m68k_poll_cnt = 0;\r
+}\r
+\r
+void s68k_reg_write16(u32 a, u32 d)\r
+{\r
+ u8 *r = Pico_mcd->s68k_regs;\r
+\r
+ if ((a & 0x1f0) == 0x20)\r
+ goto write_comm;\r
+\r
+ switch (a) {\r
+ case 0x0e:\r
+ // special case, 2 byte writes would be handled differently\r
+ // TODO: verify\r
+ r[0xf] = d;\r
+ return;\r
+ case 0x58: // stamp data size\r
+ r[0x59] = d & 7;\r
+ return;\r
+ case 0x5a: // stamp map base address\r
+ r[0x5a] = d >> 8;\r
+ r[0x5b] = d & 0xe0;\r
+ return;\r
+ case 0x5c: // V cell size\r
+ r[0x5d] = d & 0x1f;\r
+ return;\r
+ case 0x5e: // image buffer start address\r
+ r[0x5e] = d >> 8;\r
+ r[0x5f] = d & 0xf8;\r
+ return;\r
+ case 0x60: // image buffer offset\r
+ r[0x61] = d & 0x3f;\r
+ return;\r
+ case 0x62: // h dot size\r
+ r[0x62] = (d >> 8) & 1;\r
+ r[0x63] = d;\r
+ return;\r
+ case 0x64: // v dot size\r
+ r[0x65] = d;\r
+ return;\r
+ case 0x66: // trace vector base address\r
+ d &= 0xfffe;\r
+ r[0x66] = d >> 8;\r
+ r[0x67] = d;\r
+ gfx_start(d);\r
+ return;\r
+ default:\r
+ break;\r
+ }\r
+\r
+ s68k_reg_write8(a, d >> 8);\r
+ s68k_reg_write8(a + 1, d & 0xff);\r
+ return;\r
+\r
+write_comm:\r
+ r[a] = d >> 8;\r
+ r[a + 1] = d;\r
+ if (Pico_mcd->m.m68k_poll_cnt)\r
+ SekEndRunS68k(0);\r
+ Pico_mcd->m.m68k_poll_cnt = 0;\r
}\r
\r
// -----------------------------------------------------------------\r
{\r
u32 d = 0;\r
if (a == 0x400001) {\r
- if (SRam.data != NULL)\r
+ if (Pico.sv.data != NULL)\r
d = 3; // 64k cart\r
return d;\r
}\r
\r
if ((a & 0xfe0000) == 0x600000) {\r
- if (SRam.data != NULL)\r
- d = SRam.data[((a >> 1) & 0xffff) + 0x2000];\r
+ if (Pico.sv.data != NULL)\r
+ d = Pico.sv.data[((a >> 1) & 0xffff) + 0x2000];\r
return d;\r
}\r
\r
static void PicoWriteM68k8_ramc(u32 a, u32 d)\r
{\r
if ((a & 0xfe0000) == 0x600000) {\r
- if (SRam.data != NULL && (Pico_mcd->m.bcram_reg & 1)) {\r
- SRam.data[((a>>1) & 0xffff) + 0x2000] = d;\r
- SRam.changed = 1;\r
+ if (Pico.sv.data != NULL && (Pico_mcd->m.bcram_reg & 1)) {\r
+ Pico.sv.data[((a>>1) & 0xffff) + 0x2000] = d;\r
+ Pico.sv.changed = 1;\r
}\r
return;\r
}\r
return;\r
}\r
\r
- elprintf(EL_UIO, "m68k unmapped w8 [%06x] %02x @%06x", a, d & 0xff, SekPc);\r
+ elprintf(EL_UIO, "m68k unmapped w8 [%06x] %02x @%06x",\r
+ a, d & 0xff, SekPc);\r
}\r
\r
static void PicoWriteM68k16_ramc(u32 a, u32 d)\r
{\r
- elprintf(EL_ANOMALY, "ramcart w16: [%06x] %04x @%06x", a, d, SekPcS68k);\r
+ elprintf(EL_ANOMALY, "ramcart w16: [%06x] %04x @%06x",\r
+ a, d, SekPcS68k);\r
PicoWriteM68k8_ramc(a + 1, d);\r
}\r
\r
// IO/control/cd registers (a10000 - ...)\r
#ifndef _ASM_CD_MEMORY_C\r
-static u32 PicoReadM68k8_io(u32 a)\r
+u32 PicoRead8_mcd_io(u32 a)\r
{\r
u32 d;\r
if ((a & 0xff00) == 0x2000) { // a12000 - a120ff\r
if (!(a & 1))\r
d >>= 8;\r
d &= 0xff;\r
- elprintf(EL_CDREGS, "m68k_regs r8: [%02x] %02x @%06x", a & 0x3f, d, SekPc);\r
+ elprintf(EL_CDREGS, "m68k_regs r8: [%02x] %02x @%06x",\r
+ a & 0x3f, d, SekPc);\r
return d;\r
}\r
\r
return PicoRead8_io(a);\r
}\r
\r
-static u32 PicoReadM68k16_io(u32 a)\r
+u32 PicoRead16_mcd_io(u32 a)\r
{\r
u32 d;\r
if ((a & 0xff00) == 0x2000) {\r
d = m68k_reg_read16(a);\r
- elprintf(EL_CDREGS, "m68k_regs r16: [%02x] %04x @%06x", a & 0x3f, d, SekPc);\r
+ elprintf(EL_CDREGS, "m68k_regs r16: [%02x] %04x @%06x",\r
+ a & 0x3f, d, SekPc);\r
return d;\r
}\r
\r
return PicoRead16_io(a);\r
}\r
\r
-static void PicoWriteM68k8_io(u32 a, u32 d)\r
+void PicoWrite8_mcd_io(u32 a, u32 d)\r
{\r
if ((a & 0xff00) == 0x2000) { // a12000 - a120ff\r
- elprintf(EL_CDREGS, "m68k_regs w8: [%02x] %02x @%06x", a&0x3f, d, SekPc);\r
+ elprintf(EL_CDREGS, "m68k_regs w8: [%02x] %02x @%06x",\r
+ a & 0x3f, d, SekPc);\r
m68k_reg_write8(a, d);\r
return;\r
}\r
\r
- PicoWrite16_io(a, d);\r
+ PicoWrite8_io(a, d);\r
}\r
\r
-static void PicoWriteM68k16_io(u32 a, u32 d)\r
+void PicoWrite16_mcd_io(u32 a, u32 d)\r
{\r
if ((a & 0xff00) == 0x2000) { // a12000 - a120ff\r
- elprintf(EL_CDREGS, "m68k_regs w16: [%02x] %04x @%06x", a&0x3f, d, SekPc);\r
-/* TODO FIXME?\r
- if (a == 0xe) { // special case, 2 byte writes would be handled differently\r
- Pico_mcd->s68k_regs[0xe] = d >> 8;\r
-#ifdef USE_POLL_DETECT\r
- if ((s68k_poll_adclk&0xfe) == 0xe && s68k_poll_cnt > POLL_LIMIT) {\r
- SekSetStopS68k(0); s68k_poll_adclk = 0;\r
- elprintf(EL_CDPOLL, "s68k poll release, a=%02x", a);\r
- }\r
-#endif\r
- return;\r
- }\r
-*/\r
- m68k_reg_write8(a, d >> 8);\r
- m68k_reg_write8(a + 1, d & 0xff);\r
+ elprintf(EL_CDREGS, "m68k_regs w16: [%02x] %04x @%06x",\r
+ a & 0x3f, d, SekPc);\r
+\r
+ m68k_reg_write8(a, d >> 8);\r
+ if ((a & 0x3e) != 0x0e) // special case\r
+ m68k_reg_write8(a + 1, d & 0xff);\r
return;\r
}\r
\r
\r
static void s68k_unmapped_write8(u32 a, u32 d)\r
{\r
- elprintf(EL_UIO, "s68k unmapped w8 [%06x] %02x @%06x", a, d & 0xff, SekPc);\r
+ elprintf(EL_UIO, "s68k unmapped w8 [%06x] %02x @%06x",\r
+ a, d & 0xff, SekPc);\r
}\r
\r
static void s68k_unmapped_write16(u32 a, u32 d)\r
{\r
- elprintf(EL_UIO, "s68k unmapped w16 [%06x] %04x @%06x", a, d & 0xffff, SekPc);\r
+ elprintf(EL_UIO, "s68k unmapped w16 [%06x] %04x @%06x",\r
+ a, d & 0xffff, SekPc);\r
}\r
\r
-// PRG RAM protected range (000000 - 00ff00)?\r
+// PRG RAM protected range (000000 - 01fdff)?\r
// XXX verify: ff00 or 1fe00 max?\r
static void PicoWriteS68k8_prgwp(u32 a, u32 d)\r
{\r
- if (a >= (Pico_mcd->s68k_regs[2] << 8))\r
+ if (a >= (Pico_mcd->s68k_regs[2] << 9))\r
Pico_mcd->prg_ram[a ^ 1] = d;\r
}\r
\r
static void PicoWriteS68k16_prgwp(u32 a, u32 d)\r
{\r
- if (a >= (Pico_mcd->s68k_regs[2] << 8))\r
+ if (a >= (Pico_mcd->s68k_regs[2] << 9))\r
*(u16 *)(Pico_mcd->prg_ram + a) = d;\r
}\r
\r
static void PicoWriteS68k8_bram(u32 a, u32 d)\r
{\r
Pico_mcd->bram[(a >> 1) & 0x1fff] = d;\r
- SRam.changed = 1;\r
+ Pico.sv.changed = 1;\r
}\r
\r
static void PicoWriteS68k16_bram(u32 a, u32 d)\r
a = (a >> 1) & 0x1fff;\r
Pico_mcd->bram[a++] = d;\r
Pico_mcd->bram[a++] = d >> 8; // TODO: verify..\r
- SRam.changed = 1;\r
+ Pico.sv.changed = 1;\r
}\r
\r
#ifndef _ASM_CD_MEMORY_C\r
// regs\r
if ((a & 0xfe00) == 0x8000) {\r
a &= 0x1ff;\r
- elprintf(EL_CDREGS, "s68k_regs r8: [%02x] @ %06x", a, SekPcS68k);\r
if (a >= 0x0e && a < 0x30) {\r
d = Pico_mcd->s68k_regs[a];\r
- s68k_poll_detect(a, d);\r
- elprintf(EL_CDREGS, "ret = %02x", (u8)d);\r
- return d;\r
+ s68k_poll_detect(a & ~1, d);\r
+ goto regs_done;\r
}\r
- else if (a >= 0x58 && a < 0x68)\r
- d = gfx_cd_read(a & ~1);\r
- else d = s68k_reg_read16(a & ~1);\r
+ d = s68k_reg_read16(a & ~1);\r
if (!(a & 1))\r
d >>= 8;\r
- elprintf(EL_CDREGS, "ret = %02x", (u8)d);\r
- return d & 0xff;\r
+\r
+regs_done:\r
+ d &= 0xff;\r
+ elprintf(EL_CDREGS, "s68k_regs r8: [%02x] %02x @%06x",\r
+ a, d, SekPcS68k);\r
+ return d;\r
}\r
\r
// PCM\r
a &= 0x7fff;\r
if (a >= 0x2000)\r
d = Pico_mcd->pcm_ram_b[Pico_mcd->pcm.bank][(a >> 1) & 0xfff];\r
- else if (a >= 0x20) {\r
- a &= 0x1e;\r
- d = Pico_mcd->pcm.ch[a>>2].addr >> PCM_STEP_SHIFT;\r
- if (a & 2)\r
- d >>= 8;\r
- }\r
- return d & 0xff;\r
+ else if (a >= 0x20)\r
+ d = pcd_pcm_read(a >> 1);\r
+\r
+ return d;\r
}\r
\r
return s68k_unmapped_read8(a);\r
// regs\r
if ((a & 0xfe00) == 0x8000) {\r
a &= 0x1fe;\r
- elprintf(EL_CDREGS, "s68k_regs r16: [%02x] @ %06x", a, SekPcS68k);\r
- if (0x58 <= a && a < 0x68)\r
- d = gfx_cd_read(a);\r
- else d = s68k_reg_read16(a);\r
- elprintf(EL_CDREGS, "ret = %04x", d);\r
+ d = s68k_reg_read16(a);\r
+\r
+ elprintf(EL_CDREGS, "s68k_regs r16: [%02x] %04x @%06x",\r
+ a, d, SekPcS68k);\r
return d;\r
}\r
\r
// PCM\r
if ((a & 0x8000) == 0x0000) {\r
- //elprintf(EL_ANOMALY, "FIXME: s68k_pcm r16: [%06x] @%06x", a, SekPcS68k);\r
a &= 0x7fff;\r
if (a >= 0x2000)\r
- d = Pico_mcd->pcm_ram_b[Pico_mcd->pcm.bank][(a>>1)&0xfff];\r
- else if (a >= 0x20) {\r
- a &= 0x1e;\r
- d = Pico_mcd->pcm.ch[a>>2].addr >> PCM_STEP_SHIFT;\r
- if (a & 2) d >>= 8;\r
- }\r
- elprintf(EL_CDREGS, "ret = %04x", d);\r
+ d = Pico_mcd->pcm_ram_b[Pico_mcd->pcm.bank][(a >> 1) & 0xfff];\r
+ else if (a >= 0x20)\r
+ d = pcd_pcm_read(a >> 1);\r
+\r
return d;\r
}\r
\r
// regs\r
if ((a & 0xfe00) == 0x8000) {\r
a &= 0x1ff;\r
- elprintf(EL_CDREGS, "s68k_regs w8: [%02x] %02x @ %06x", a, d, SekPcS68k);\r
- if (0x58 <= a && a < 0x68)\r
- gfx_cd_write16(a&~1, (d<<8)|d);\r
- else s68k_reg_write8(a,d);\r
+ elprintf(EL_CDREGS, "s68k_regs w8: [%02x] %02x @%06x", a, d, SekPcS68k);\r
+ if (0x59 <= a && a < 0x68) // word regs\r
+ s68k_reg_write16(a & ~1, (d << 8) | d);\r
+ else\r
+ s68k_reg_write8(a, d);\r
return;\r
}\r
\r
if (a >= 0x2000)\r
Pico_mcd->pcm_ram_b[Pico_mcd->pcm.bank][(a>>1)&0xfff] = d;\r
else if (a < 0x12)\r
- pcm_write(a>>1, d);\r
+ pcd_pcm_write(a>>1, d);\r
return;\r
}\r
\r
// regs\r
if ((a & 0xfe00) == 0x8000) {\r
a &= 0x1fe;\r
- elprintf(EL_CDREGS, "s68k_regs w16: [%02x] %04x @ %06x", a, d, SekPcS68k);\r
- if (a >= 0x58 && a < 0x68)\r
- gfx_cd_write16(a, d);\r
- else {\r
- if (a == 0xe) {\r
- // special case, 2 byte writes would be handled differently\r
- // TODO: verify\r
- Pico_mcd->s68k_regs[0xf] = d;\r
- return;\r
- }\r
- s68k_reg_write8(a, d >> 8);\r
- s68k_reg_write8(a + 1, d & 0xff);\r
- }\r
+ elprintf(EL_CDREGS, "s68k_regs w16: [%02x] %04x @%06x", a, d, SekPcS68k);\r
+ s68k_reg_write16(a, d);\r
return;\r
}\r
\r
if (a >= 0x2000)\r
Pico_mcd->pcm_ram_b[Pico_mcd->pcm.bank][(a>>1)&0xfff] = d;\r
else if (a < 0x12)\r
- pcm_write(a>>1, d & 0xff);\r
+ pcd_pcm_write(a>>1, d & 0xff);\r
return;\r
}\r
\r
\r
// -----------------------------------------------------------------\r
\r
-static void remap_prg_window(void)\r
+static void remap_prg_window(u32 r1, u32 r3)\r
{\r
// PRG RAM\r
- if (Pico_mcd->m.busreq & 2) {\r
- void *bank = Pico_mcd->prg_ram_b[Pico_mcd->s68k_regs[3] >> 6];\r
+ if (r1 & 2) {\r
+ void *bank = Pico_mcd->prg_ram_b[(r3 >> 6) & 3];\r
cpu68k_map_all_ram(0x020000, 0x03ffff, bank, 0);\r
}\r
else {\r
}\r
}\r
\r
-static void remap_word_ram(int r3)\r
+static void remap_word_ram(u32 r3)\r
{\r
void *bank;\r
\r
cpu68k_map_set(s68k_write8_map, 0x080000, 0x0bffff, s68k_dec_write8[b0 ^ 1][m], 1);\r
cpu68k_map_set(s68k_write16_map, 0x080000, 0x0bffff, s68k_dec_write16[b0 ^ 1][m], 1);\r
}\r
-\r
-#ifdef EMU_F68K\r
- // update fetchmap..\r
- int i;\r
- if (!(r3 & 4))\r
- {\r
- for (i = M68K_FETCHBANK1*2/16; (i<<(24-FAMEC_FETCHBITS)) < 0x240000; i++)\r
- PicoCpuFM68k.Fetch[i] = (unsigned long)Pico_mcd->word_ram2M - 0x200000;\r
- }\r
- else\r
- {\r
- for (i = M68K_FETCHBANK1*2/16; (i<<(24-FAMEC_FETCHBITS)) < 0x220000; i++)\r
- PicoCpuFM68k.Fetch[i] = (unsigned long)Pico_mcd->word_ram1M[r3 & 1] - 0x200000;\r
- for (i = M68K_FETCHBANK1*0x0c/0x100; (i<<(24-FAMEC_FETCHBITS)) < 0x0e0000; i++)\r
- PicoCpuFS68k.Fetch[i] = (unsigned long)Pico_mcd->word_ram1M[(r3&1)^1] - 0x0c0000;\r
- }\r
-#endif\r
}\r
\r
void pcd_state_loaded_mem(void)\r
{\r
- int r3 = Pico_mcd->s68k_regs[3];\r
+ u32 r3 = Pico_mcd->s68k_regs[3];\r
\r
/* after load events */\r
if (r3 & 4) // 1M mode?\r
wram_2M_to_1M(Pico_mcd->word_ram2M);\r
remap_word_ram(r3);\r
- remap_prg_window();\r
+ remap_prg_window(Pico_mcd->m.busreq, r3);\r
+ Pico_mcd->m.dmna_ret_2m &= 3;\r
\r
// restore hint vector\r
*(unsigned short *)(Pico_mcd->bios + 0x72) = Pico_mcd->m.hint_vector;\r
}\r
\r
// registers/IO:\r
- cpu68k_map_set(m68k_read8_map, 0xa10000, 0xa1ffff, PicoReadM68k8_io, 1);\r
- cpu68k_map_set(m68k_read16_map, 0xa10000, 0xa1ffff, PicoReadM68k16_io, 1);\r
- cpu68k_map_set(m68k_write8_map, 0xa10000, 0xa1ffff, PicoWriteM68k8_io, 1);\r
- cpu68k_map_set(m68k_write16_map, 0xa10000, 0xa1ffff, PicoWriteM68k16_io, 1);\r
+ cpu68k_map_set(m68k_read8_map, 0xa10000, 0xa1ffff, PicoRead8_mcd_io, 1);\r
+ cpu68k_map_set(m68k_read16_map, 0xa10000, 0xa1ffff, PicoRead16_mcd_io, 1);\r
+ cpu68k_map_set(m68k_write8_map, 0xa10000, 0xa1ffff, PicoWrite8_mcd_io, 1);\r
+ cpu68k_map_set(m68k_write16_map, 0xa10000, 0xa1ffff, PicoWrite16_mcd_io, 1);\r
\r
// sub68k map\r
cpu68k_map_set(s68k_read8_map, 0x000000, 0xffffff, s68k_unmapped_read8, 1);\r
cpu68k_map_set(s68k_read16_map, 0x000000, 0x07ffff, Pico_mcd->prg_ram, 0);\r
cpu68k_map_set(s68k_write8_map, 0x000000, 0x07ffff, Pico_mcd->prg_ram, 0);\r
cpu68k_map_set(s68k_write16_map, 0x000000, 0x07ffff, Pico_mcd->prg_ram, 0);\r
- cpu68k_map_set(s68k_write8_map, 0x000000, 0x00ffff, PicoWriteS68k8_prgwp, 1);\r
- cpu68k_map_set(s68k_write16_map, 0x000000, 0x00ffff, PicoWriteS68k16_prgwp, 1);\r
+ cpu68k_map_set(s68k_write8_map, 0x000000, 0x01ffff, PicoWriteS68k8_prgwp, 1);\r
+ cpu68k_map_set(s68k_write16_map, 0x000000, 0x01ffff, PicoWriteS68k16_prgwp, 1);\r
\r
// BRAM\r
cpu68k_map_set(s68k_read8_map, 0xfe0000, 0xfeffff, PicoReadS68k8_bram, 1);\r
PicoCpuFM68k.Fetch[i] = (unsigned long)Pico.rom;\r
// .. and RAM\r
for (i = M68K_FETCHBANK1*14/16; i < M68K_FETCHBANK1; i++)\r
- PicoCpuFM68k.Fetch[i] = (unsigned long)Pico.ram - (i<<(24-FAMEC_FETCHBITS));\r
+ PicoCpuFM68k.Fetch[i] = (unsigned long)PicoMem.ram - (i<<(24-FAMEC_FETCHBITS));\r
// S68k\r
// PRG RAM is default\r
for (i = 0; i < M68K_FETCHBANK1; i++)\r
#ifdef EMU_M68K\r
m68k_mem_setup_cd();\r
#endif\r
-\r
- // m68k_poll_addr = m68k_poll_cnt = 0;\r
- s68k_poll_adclk = s68k_poll_cnt = 0;\r
}\r
\r
\r
notaz.gp2x.de / picodrive.git / blobdiff