* See COPYING file in the top-level directory.\r
*/\r
\r
+#include "pico_int_o32.h"\r
+\r
.equ SRR_MAPPED, (1 << 0)\r
.equ SRR_READONLY, (1 << 1)\r
.equ SRF_EEPROM, (1 << 1)\r
.global PicoWrite8_io\r
.global PicoWrite16_io\r
\r
-PicoRead8_sram: @ u32 a, u32 d\r
- ldr r2, =(SRam)\r
- ldr r3, =(Pico+0x22200)\r
- ldr r1, [r2, #8] @ SRam.end\r
+PicoRead8_sram: @ u32 a\r
+ ldr r3, =Pico\r
+ ldr r1, [r3, #OFS_Pico_sv_end]\r
cmp r0, r1\r
bgt m_read8_nosram\r
- ldr r1, [r2, #4] @ SRam.start\r
- cmp r0, r1\r
+ ldr r2, [r3, #OFS_Pico_sv_start]\r
+ cmp r0, r2\r
blt m_read8_nosram\r
- ldrb r1, [r3, #0x11] @ Pico.m.sram_reg\r
+ ldrb r1, [r3, #OFS_Pico_m_sram_reg]\r
tst r1, #SRR_MAPPED\r
beq m_read8_nosram\r
- ldr r1, [r2, #0x0c]\r
+ ldr r1, [r3, #OFS_Pico_sv_flags]\r
tst r1, #SRF_EEPROM\r
bne m_read8_eeprom\r
- ldr r1, [r2, #4] @ SRam.start\r
- ldr r2, [r2] @ SRam.data\r
- sub r0, r0, r1\r
- add r0, r0, r2\r
- ldrb r0, [r0]\r
+ ldr r1, [r3, #OFS_Pico_sv_data]\r
+ sub r0, r0, r2\r
+ ldrb r0, [r0, r1]\r
bx lr\r
\r
m_read8_nosram:\r
- ldr r1, [r3, #4] @ romsize\r
+ ldr r1, [r3, #OFS_Pico_romsize]\r
cmp r0, r1\r
movgt r0, #0\r
bxgt lr @ bad location\r
@ XXX: banking unfriendly\r
- ldr r1, [r3]\r
+ ldr r1, [r3, #OFS_Pico_rom]\r
eor r0, r0, #1\r
ldrb r0, [r1, r0]\r
bx lr\r
bx lr\r
\r
\r
-PicoRead8_io: @ u32 a, u32 d\r
+PicoRead8_io: @ u32 a\r
bic r2, r0, #0x001f @ most commonly we get i/o port read,\r
cmp r2, #0xa10000 @ so check for it first\r
beq io_ports_read\r
cmp r2, #0x1000\r
bne m_read8_not_brq\r
\r
- ldr r3, =(Pico+0x22200)\r
+ ldr r3, =Pico\r
mov r1, r0\r
- ldr r0, [r3, #8] @ Pico.m.rotate\r
+ ldr r0, [r3, #OFS_Pico_m_rotate]\r
add r0, r0, #1\r
- strb r0, [r3, #8]\r
+ strb r0, [r3, #OFS_Pico_m_rotate]\r
eor r0, r0, r0, lsl #6\r
\r
tst r1, #1\r
cmp r2, #0x1100\r
bxne lr @ not busreq\r
\r
- ldrb r1, [r3, #(8+0x01)] @ Pico.m.z80Run\r
- ldrb r2, [r3, #(8+0x0f)] @ Pico.m.z80_reset\r
+ ldrb r1, [r3, #OFS_Pico_m_z80Run]\r
+ ldrb r2, [r3, #OFS_Pico_m_z80_reset]\r
orr r0, r0, r1\r
orr r0, r0, r2\r
bx lr\r
@ @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@\r
\r
PicoRead16_sram: @ u32 a, u32 d\r
- ldr r2, =(SRam)\r
- ldr r3, =(Pico+0x22200)\r
- ldr r1, [r2, #8] @ SRam.end\r
+ ldr r3, =Pico\r
+ ldr r1, [r3, #OFS_Pico_sv_end]\r
cmp r0, r1\r
bgt m_read16_nosram\r
- ldr r1, [r2, #4] @ SRam.start\r
- cmp r0, r1\r
+ ldr r2, [r3, #OFS_Pico_sv_start]\r
+ cmp r0, r2\r
blt m_read16_nosram\r
- ldrb r1, [r3, #0x11] @ Pico.m.sram_reg\r
+ ldrb r1, [r3, #OFS_Pico_m_sram_reg]\r
tst r1, #SRR_MAPPED\r
beq m_read16_nosram\r
- ldr r1, [r2, #0x0c]\r
+ ldr r1, [r3, #OFS_Pico_sv_flags]\r
tst r1, #SRF_EEPROM\r
bne EEPROM_read\r
- ldr r1, [r2, #4] @ SRam.start\r
- ldr r2, [r2] @ SRam.data\r
- sub r0, r0, r1\r
- add r0, r0, r2\r
- ldrb r1, [r0], #1\r
- ldrb r0, [r0]\r
+ ldr r1, [r3, #OFS_Pico_sv_data]\r
+ sub r0, r0, r2\r
+ ldrb r1, [r0, r1]!\r
+ ldrb r0, [r0, #1]\r
orr r0, r0, r1, lsl #8\r
bx lr\r
\r
m_read16_nosram:\r
- ldr r1, [r3, #4] @ romsize\r
+ ldr r1, [r3, #OFS_Pico_romsize]\r
cmp r0, r1\r
movgt r0, #0\r
bxgt lr @ bad location\r
@ XXX: banking unfriendly\r
- ldr r1, [r3]\r
+ ldr r1, [r3, #OFS_Pico_rom]\r
ldrh r0, [r1, r0]\r
bx lr\r
\r
cmp r2, #0x1000\r
bne m_read16_not_brq\r
\r
- ldr r3, =(Pico+0x22200)\r
+ ldr r3, =Pico\r
and r2, r0, #0xff00\r
- ldr r0, [r3, #8] @ Pico.m.rotate\r
+ ldr r0, [r3, #OFS_Pico_m_rotate]\r
add r0, r0, #1\r
- strb r0, [r3, #8]\r
+ strb r0, [r3, #OFS_Pico_m_rotate]\r
eor r0, r0, r0, lsl #5\r
eor r0, r0, r0, lsl #8\r
bic r0, r0, #0x100 @ bit8 defined in this area\r
cmp r2, #0x1100\r
bxne lr @ not busreq\r
\r
- ldrb r1, [r3, #(8+0x01)] @ Pico.m.z80Run\r
- ldrb r2, [r3, #(8+0x0f)] @ Pico.m.z80_reset\r
+ ldrb r1, [r3, #OFS_Pico_m_z80Run]\r
+ ldrb r2, [r3, #OFS_Pico_m_z80_reset]\r
orr r0, r0, r1, lsl #8\r
orr r0, r0, r2, lsl #8\r
bx lr\r
eor r2, r2, #0x003000\r
eors r2, r2, #0x0000f1\r
bne m_write8_not_sreg\r
- ldr r3, =(Pico+0x22200)\r
- ldrb r2, [r3, #(8+9)] @ Pico.m.sram_reg\r
+ ldr r3, =Pico\r
+ ldrb r2, [r3, #OFS_Pico_m_sram_reg]\r
and r1, r1, #(SRR_MAPPED|SRR_READONLY)\r
bic r2, r2, #(SRR_MAPPED|SRR_READONLY)\r
orr r2, r2, r1\r
- strb r2, [r3, #(8+9)]\r
+ strb r2, [r3, #OFS_Pico_m_sram_reg]\r
bx lr\r
\r
m_write8_not_sreg:\r
eor r2, r2, #0x003000\r
eors r2, r2, #0x0000f0\r
bne m_write16_not_sreg\r
- ldr r3, =(Pico+0x22200)\r
- ldrb r2, [r3, #(8+9)] @ Pico.m.sram_reg\r
+ ldr r3, =Pico\r
+ ldrb r2, [r3, #OFS_Pico_m_sram_reg]\r
and r1, r1, #(SRR_MAPPED|SRR_READONLY)\r
bic r2, r2, #(SRR_MAPPED|SRR_READONLY)\r
orr r2, r2, r1\r
- strb r2, [r3, #(8+9)]\r
+ strb r2, [r3, #OFS_Pico_m_sram_reg]\r
bx lr\r
\r
m_write16_not_sreg:\r