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final fixes for UIQ3
[picodrive.git] / Pico / cd / Memory.c
CommitLineData
6cadc2da 1// Memory I/O handlers for Sega/Mega CD.\r
2// Loosely based on Gens code.\r
3// (c) Copyright 2007, Grazvydas "notaz" Ignotas\r
cc68a136 4\r
cc68a136 5\r
cc68a136 6#include "../PicoInt.h"\r
7\r
cc68a136 8#include "../sound/ym2612.h"\r
9#include "../sound/sn76496.h"\r
10\r
cb4a513a 11#include "gfx_cd.h"\r
4f265db7 12#include "pcm.h"\r
cb4a513a 13\r
eff55556 14#ifndef UTYPES_DEFINED\r
cc68a136 15typedef unsigned char u8;\r
16typedef unsigned short u16;\r
17typedef unsigned int u32;\r
eff55556 18#define UTYPES_DEFINED\r
19#endif\r
cc68a136 20\r
dca310c4 21#ifdef _MSC_VER\r
22#define rdprintf\r
23#define wrdprintf\r
39230401 24#define r3printf\r
dca310c4 25#else\r
b5e5172d 26//#define rdprintf dprintf\r
27#define rdprintf(...)\r
68cba51e 28//#define wrdprintf dprintf\r
913ef4b7 29#define wrdprintf(...)\r
39230401 30#define r3printf(...)\r
dca310c4 31#endif\r
cc68a136 32\r
b5e5172d 33#ifdef EMU_CORE_DEBUG\r
34extern u32 lastread_a, lastread_d[16], lastwrite_cyc_d[16];\r
35extern int lrp_cyc, lwp_cyc;\r
36#undef USE_POLL_DETECT\r
37#endif\r
38\r
cc68a136 39// -----------------------------------------------------------------\r
40\r
7a1f6e45 41// poller detection\r
7a1f6e45 42#define POLL_LIMIT 16\r
43#define POLL_CYCLES 124\r
44// int m68k_poll_addr, m68k_poll_cnt;\r
45unsigned int s68k_poll_adclk, s68k_poll_cnt;\r
cc68a136 46\r
4ff2d527 47#ifndef _ASM_CD_MEMORY_C\r
cb4a513a 48static u32 m68k_reg_read16(u32 a)\r
cc68a136 49{\r
50 u32 d=0;\r
51 a &= 0x3e;\r
672ad671 52 // dprintf("m68k_regs r%2i: [%02x] @%06x", realsize&~1, a+(realsize&1), SekPc);\r
cc68a136 53\r
54 switch (a) {\r
672ad671 55 case 0:\r
c459aefd 56 d = ((Pico_mcd->s68k_regs[0x33]<<13)&0x8000) | Pico_mcd->m.busreq; // here IFL2 is always 0, just like in Gens\r
672ad671 57 goto end;\r
cc68a136 58 case 2:\r
672ad671 59 d = (Pico_mcd->s68k_regs[a]<<8) | (Pico_mcd->s68k_regs[a+1]&0xc7);\r
c008977e 60 // the DMNA delay must only be visible on s68k side (Lunar2, Silpheed)\r
61 if (Pico_mcd->m.state_flags&2) { d &= ~1; d |= 2; }\r
39230401 62 r3printf(EL_STATUS, "m68k_regs r3: %02x @%06x", (u8)d, SekPc);\r
cc68a136 63 goto end;\r
c459aefd 64 case 4:\r
65 d = Pico_mcd->s68k_regs[4]<<8;\r
66 goto end;\r
67 case 6:\r
913ef4b7 68 d = *(u16 *)(Pico_mcd->bios + 0x72);\r
c459aefd 69 goto end;\r
cc68a136 70 case 8:\r
cc68a136 71 d = Read_CDC_Host(0);\r
72 goto end;\r
c459aefd 73 case 0xA:\r
ca61ee42 74 elprintf(EL_UIO, "m68k FIXME: reserved read");\r
c459aefd 75 goto end;\r
cc68a136 76 case 0xC:\r
1cd356a3 77 d = Pico_mcd->m.timer_stopwatch >> 16;\r
4ff2d527 78 dprintf("m68k stopwatch timer read (%04x)", d);\r
1cd356a3 79 goto end;\r
cc68a136 80 }\r
81\r
cc68a136 82 if (a < 0x30) {\r
83 // comm flag/cmd/status (0xE-0x2F)\r
84 d = (Pico_mcd->s68k_regs[a]<<8) | Pico_mcd->s68k_regs[a+1];\r
85 goto end;\r
86 }\r
87\r
ca61ee42 88 elprintf(EL_UIO, "m68k_regs FIXME invalid read @ %02x", a);\r
cc68a136 89\r
90end:\r
91\r
cc68a136 92 return d;\r
93}\r
4ff2d527 94#endif\r
cc68a136 95\r
4ff2d527 96#ifndef _ASM_CD_MEMORY_C\r
97static\r
98#endif\r
99void m68k_reg_write8(u32 a, u32 d)\r
cc68a136 100{\r
101 a &= 0x3f;\r
672ad671 102 // dprintf("m68k_regs w%2i: [%02x] %02x @%06x", realsize, a, d, SekPc);\r
cc68a136 103\r
104 switch (a) {\r
105 case 0:\r
672ad671 106 d &= 1;\r
ca61ee42 107 if ((d&1) && (Pico_mcd->s68k_regs[0x33]&(1<<2))) { elprintf(EL_INTS, "m68k: s68k irq 2"); SekInterruptS68k(2); }\r
c459aefd 108 return;\r
cc68a136 109 case 1:\r
672ad671 110 d &= 3;\r
51a902ae 111 if (!(d&1)) Pico_mcd->m.state_flags |= 1; // reset pending, needed to be sure we fetch the right vectors on reset\r
c459aefd 112 if ( (Pico_mcd->m.busreq&1) != (d&1)) dprintf("m68k: s68k reset %i", !(d&1));\r
113 if ( (Pico_mcd->m.busreq&2) != (d&2)) dprintf("m68k: s68k brq %i", (d&2)>>1);\r
51a902ae 114 if ((Pico_mcd->m.state_flags&1) && (d&3)==1) {\r
cc68a136 115 SekResetS68k(); // S68k comes out of RESET or BRQ state\r
4ff2d527 116 Pico_mcd->m.state_flags&=~1;\r
117 dprintf("m68k: resetting s68k, cycles=%i", SekCyclesLeft);\r
cc68a136 118 }\r
c459aefd 119 Pico_mcd->m.busreq = d;\r
120 return;\r
672ad671 121 case 2:\r
721cd396 122 dprintf("m68k: prg wp=%02x", d);\r
672ad671 123 Pico_mcd->s68k_regs[2] = d; // really use s68k side register\r
124 return;\r
66fdc0f0 125 case 3: {\r
126 u32 dold = Pico_mcd->s68k_regs[3]&0x1f;\r
39230401 127 r3printf(EL_STATUS, "m68k_regs w3: %02x @%06x", (u8)d, SekPc);\r
672ad671 128 d &= 0xc2;\r
66fdc0f0 129 if ((dold>>6) != ((d>>6)&3))\r
672ad671 130 dprintf("m68k: prg bank: %i -> %i", (Pico_mcd->s68k_regs[a]>>6), ((d>>6)&3));\r
131 //if ((Pico_mcd->s68k_regs[3]&4) != (d&4)) dprintf("m68k: ram mode %i mbit", (d&4) ? 1 : 2);\r
132 //if ((Pico_mcd->s68k_regs[3]&2) != (d&2)) dprintf("m68k: %s", (d&4) ? ((d&2) ? "word swap req" : "noop?") :\r
133 // ((d&2) ? "word ram to s68k" : "word ram to m68k"));\r
66fdc0f0 134 if (dold & 4) {\r
135 d ^= 2; // writing 0 to DMNA actually sets it, 1 does nothing\r
136 } else {\r
137 //dold &= ~2; // ??\r
89fa852d 138#if 1\r
39230401 139 if (d & (d ^ dold) & 2) { // DMNA is being set\r
89fa852d 140 Pico_mcd->m.state_flags |= 2; // we must delay setting DMNA bit (needed for Silpheed)\r
141 d &= ~2;\r
142 }\r
39230401 143 else\r
144 Pico_mcd->m.state_flags &= ~2;\r
89fa852d 145#else\r
66fdc0f0 146 if (d & 2) dold &= ~1; // return word RAM to s68k in 2M mode\r
89fa852d 147#endif\r
66fdc0f0 148 }\r
149 Pico_mcd->s68k_regs[3] = d | dold; // really use s68k side register\r
7a1f6e45 150#ifdef USE_POLL_DETECT\r
151 if ((s68k_poll_adclk&0xfe) == 2 && s68k_poll_cnt > POLL_LIMIT) {\r
152 SekSetStopS68k(0); s68k_poll_adclk = 0;\r
8f8fe01e 153 elprintf(EL_CDPOLL, "s68k poll release, a=%02x", a);\r
7a1f6e45 154 }\r
155#endif\r
672ad671 156 return;\r
66fdc0f0 157 }\r
c459aefd 158 case 6:\r
d1df8786 159 Pico_mcd->bios[0x72 + 1] = d; // simple hint vector changer\r
c459aefd 160 return;\r
161 case 7:\r
d1df8786 162 Pico_mcd->bios[0x72] = d;\r
913ef4b7 163 dprintf("hint vector set to %08x", PicoRead32(0x70));\r
c459aefd 164 return;\r
7a1f6e45 165 case 0xf:\r
166 d = (d << 1) | ((d >> 7) & 1); // rol8 1 (special case)\r
cc68a136 167 case 0xe:\r
672ad671 168 //dprintf("m68k: comm flag: %02x", d);\r
cc68a136 169 Pico_mcd->s68k_regs[0xe] = d;\r
7a1f6e45 170#ifdef USE_POLL_DETECT\r
171 if ((s68k_poll_adclk&0xfe) == 0xe && s68k_poll_cnt > POLL_LIMIT) {\r
172 SekSetStopS68k(0); s68k_poll_adclk = 0;\r
8f8fe01e 173 elprintf(EL_CDPOLL, "s68k poll release, a=%02x", a);\r
7a1f6e45 174 }\r
175#endif\r
c459aefd 176 return;\r
672ad671 177 }\r
178\r
179 if ((a&0xf0) == 0x10) {\r
cc68a136 180 Pico_mcd->s68k_regs[a] = d;\r
7a1f6e45 181#ifdef USE_POLL_DETECT\r
182 if ((a&0xfe) == (s68k_poll_adclk&0xfe) && s68k_poll_cnt > POLL_LIMIT) {\r
183 SekSetStopS68k(0); s68k_poll_adclk = 0;\r
8f8fe01e 184 elprintf(EL_CDPOLL, "s68k poll release, a=%02x", a);\r
7a1f6e45 185 }\r
186#endif\r
672ad671 187 return;\r
cc68a136 188 }\r
189\r
ca61ee42 190 elprintf(EL_UIO, "m68k FIXME: invalid write? [%02x] %02x", a, d);\r
cc68a136 191}\r
192\r
2433f409 193#ifndef _ASM_CD_MEMORY_C\r
194static\r
195#endif\r
196u32 s68k_poll_detect(u32 a, u32 d)\r
197{\r
198#ifdef USE_POLL_DETECT\r
ca61ee42 199 // needed mostly for Cyclone, which doesn't always check it's cycle counter\r
200 if (SekIsStoppedS68k()) return d;\r
2433f409 201 // polling detection\r
202 if (a == (s68k_poll_adclk&0xff)) {\r
203 unsigned int clkdiff = SekCyclesDoneS68k() - (s68k_poll_adclk>>8);\r
204 if (clkdiff <= POLL_CYCLES) {\r
205 s68k_poll_cnt++;\r
206 //printf("-- diff: %u, cnt = %i\n", clkdiff, s68k_poll_cnt);\r
207 if (s68k_poll_cnt > POLL_LIMIT) {\r
208 SekSetStopS68k(1);\r
8f8fe01e 209 elprintf(EL_CDPOLL, "s68k poll detected @ %06x, a=%02x", SekPcS68k, a);\r
2433f409 210 }\r
211 s68k_poll_adclk = (SekCyclesDoneS68k() << 8) | a;\r
212 return d;\r
213 }\r
214 }\r
215 s68k_poll_adclk = (SekCyclesDoneS68k() << 8) | a;\r
216 s68k_poll_cnt = 0;\r
217#endif\r
218 return d;\r
219}\r
cc68a136 220\r
913ef4b7 221#define READ_FONT_DATA(basemask) \\r
222{ \\r
223 unsigned int fnt = *(unsigned int *)(Pico_mcd->s68k_regs + 0x4c); \\r
224 unsigned int col0 = (fnt >> 8) & 0x0f, col1 = (fnt >> 12) & 0x0f; \\r
225 if (fnt & (basemask << 0)) d = col1 ; else d = col0; \\r
226 if (fnt & (basemask << 1)) d |= col1 << 4; else d |= col0 << 4; \\r
227 if (fnt & (basemask << 2)) d |= col1 << 8; else d |= col0 << 8; \\r
228 if (fnt & (basemask << 3)) d |= col1 << 12; else d |= col0 << 12; \\r
229}\r
230\r
cc68a136 231\r
4ff2d527 232#ifndef _ASM_CD_MEMORY_C\r
233static\r
234#endif\r
235u32 s68k_reg_read16(u32 a)\r
cc68a136 236{\r
237 u32 d=0;\r
cc68a136 238\r
672ad671 239 // dprintf("s68k_regs r%2i: [%02x] @ %06x", realsize&~1, a+(realsize&1), SekPcS68k);\r
cc68a136 240\r
241 switch (a) {\r
242 case 0:\r
7a1f6e45 243 return ((Pico_mcd->s68k_regs[0]&3)<<8) | 1; // ver = 0, not in reset state\r
672ad671 244 case 2:\r
2433f409 245 d = (Pico_mcd->s68k_regs[2]<<8) | (Pico_mcd->s68k_regs[3]&0x1f);\r
39230401 246 r3printf(EL_STATUS, "s68k_regs r3: %02x @%06x", (u8)d, SekPcS68k);\r
2433f409 247 return s68k_poll_detect(a, d);\r
cc68a136 248 case 6:\r
7a1f6e45 249 return CDC_Read_Reg();\r
cc68a136 250 case 8:\r
7a1f6e45 251 return Read_CDC_Host(1); // Gens returns 0 here on byte reads\r
cc68a136 252 case 0xC:\r
4f265db7 253 d = Pico_mcd->m.timer_stopwatch >> 16;\r
4ff2d527 254 dprintf("s68k stopwatch timer read (%04x)", d);\r
7a1f6e45 255 return d;\r
d1df8786 256 case 0x30:\r
7a1f6e45 257 dprintf("s68k int3 timer read (%02x)", Pico_mcd->s68k_regs[31]);\r
258 return Pico_mcd->s68k_regs[31];\r
cc68a136 259 case 0x34: // fader\r
7a1f6e45 260 return 0; // no busy bit\r
913ef4b7 261 case 0x50: // font data (check: Lunar 2, Silpheed)\r
262 READ_FONT_DATA(0x00100000);\r
7a1f6e45 263 return d;\r
913ef4b7 264 case 0x52:\r
265 READ_FONT_DATA(0x00010000);\r
7a1f6e45 266 return d;\r
913ef4b7 267 case 0x54:\r
268 READ_FONT_DATA(0x10000000);\r
7a1f6e45 269 return d;\r
913ef4b7 270 case 0x56:\r
271 READ_FONT_DATA(0x01000000);\r
7a1f6e45 272 return d;\r
cc68a136 273 }\r
274\r
275 d = (Pico_mcd->s68k_regs[a]<<8) | Pico_mcd->s68k_regs[a+1];\r
276\r
2433f409 277 if (a >= 0x0e && a < 0x30)\r
278 return s68k_poll_detect(a, d);\r
7a1f6e45 279\r
cc68a136 280 return d;\r
281}\r
282\r
4ff2d527 283#ifndef _ASM_CD_MEMORY_C\r
284static\r
285#endif\r
286void s68k_reg_write8(u32 a, u32 d)\r
cc68a136 287{\r
672ad671 288 //dprintf("s68k_regs w%2i: [%02x] %02x @ %06x", realsize, a, d, SekPcS68k);\r
cc68a136 289\r
48e8482f 290 // Warning: d might have upper bits set\r
cc68a136 291 switch (a) {\r
672ad671 292 case 2:\r
293 return; // only m68k can change WP\r
fa1e5e29 294 case 3: {\r
295 int dold = Pico_mcd->s68k_regs[3];\r
39230401 296 r3printf(EL_STATUS, "s68k_regs w3: %02x @%06x", (u8)d, SekPcS68k);\r
672ad671 297 d &= 0x1d;\r
4ff2d527 298 d |= dold&0xc2;\r
39230401 299 if (d&4)\r
300 {\r
4ff2d527 301 if ((d ^ dold) & 5) {\r
302 d &= ~2; // in case of mode or bank change we clear DMNA (m68k req) bit\r
4ff2d527 303 PicoMemResetCD(d);\r
4ff2d527 304 }\r
48e8482f 305#ifdef _ASM_CD_MEMORY_C\r
306 if ((d ^ dold) & 0x1d)\r
307 PicoMemResetCDdecode(d);\r
308#endif\r
fa1e5e29 309 if (!(dold & 4)) {\r
39230401 310 r3printf(EL_STATUS, "wram mode 2M->1M");\r
fa1e5e29 311 wram_2M_to_1M(Pico_mcd->word_ram2M);\r
4ff2d527 312 }\r
39230401 313 }\r
314 else\r
315 {\r
fa1e5e29 316 if (dold & 4) {\r
39230401 317 r3printf(EL_STATUS, "wram mode 1M->2M");\r
4ff2d527 318 if (!(d&1)) { // it didn't set the ret bit, which means it doesn't want to give WRAM to m68k\r
319 d &= ~3;\r
320 d |= (dold&1) ? 2 : 1; // then give it to the one which had bank0 in 1M mode\r
321 }\r
fa1e5e29 322 wram_1M_to_2M(Pico_mcd->word_ram2M);\r
4ff2d527 323 PicoMemResetCD(d);\r
4ff2d527 324 }\r
325 else\r
326 d |= dold&1;\r
327 if (d&1) d &= ~2; // return word RAM to m68k in 2M mode\r
d0d47c5b 328 }\r
39230401 329 Pico_mcd->m.state_flags &= ~2;\r
672ad671 330 break;\r
fa1e5e29 331 }\r
cc68a136 332 case 4:\r
333 dprintf("s68k CDC dest: %x", d&7);\r
334 Pico_mcd->s68k_regs[4] = (Pico_mcd->s68k_regs[4]&0xC0) | (d&7); // CDC mode\r
335 return;\r
336 case 5:\r
c459aefd 337 //dprintf("s68k CDC reg addr: %x", d&0xf);\r
cc68a136 338 break;\r
339 case 7:\r
340 CDC_Write_Reg(d);\r
341 return;\r
342 case 0xa:\r
343 dprintf("s68k set CDC dma addr");\r
344 break;\r
d1df8786 345 case 0xc:\r
4f265db7 346 case 0xd:\r
d1df8786 347 dprintf("s68k set stopwatch timer");\r
4f265db7 348 Pico_mcd->m.timer_stopwatch = 0;\r
349 return;\r
1cd356a3 350 case 0xe:\r
7a1f6e45 351 Pico_mcd->s68k_regs[0xf] = (d>>1) | (d<<7); // ror8 1, Gens note: Dragons lair\r
1cd356a3 352 return;\r
d1df8786 353 case 0x31:\r
4f265db7 354 dprintf("s68k set int3 timer: %02x", d);\r
48e8482f 355 Pico_mcd->m.timer_int3 = (d & 0xff) << 16;\r
d1df8786 356 break;\r
cc68a136 357 case 0x33: // IRQ mask\r
358 dprintf("s68k irq mask: %02x", d);\r
359 if ((d&(1<<4)) && (Pico_mcd->s68k_regs[0x37]&4) && !(Pico_mcd->s68k_regs[0x33]&(1<<4))) {\r
360 CDD_Export_Status();\r
cc68a136 361 }\r
362 break;\r
363 case 0x34: // fader\r
364 Pico_mcd->s68k_regs[a] = (u8) d & 0x7f;\r
365 return;\r
672ad671 366 case 0x36:\r
367 return; // d/m bit is unsetable\r
368 case 0x37: {\r
369 u32 d_old = Pico_mcd->s68k_regs[0x37];\r
370 Pico_mcd->s68k_regs[0x37] = d&7;\r
371 if ((d&4) && !(d_old&4)) {\r
cc68a136 372 CDD_Export_Status();\r
cc68a136 373 }\r
672ad671 374 return;\r
375 }\r
cc68a136 376 case 0x4b:\r
377 Pico_mcd->s68k_regs[a] = (u8) d;\r
378 CDD_Import_Command();\r
379 return;\r
380 }\r
381\r
1cd356a3 382 if ((a&0x1f0) == 0x10 || (a >= 0x38 && a < 0x42))\r
cc68a136 383 {\r
ca61ee42 384 elprintf(EL_UIO, "s68k FIXME: invalid write @ %02x?", a);\r
cc68a136 385 return;\r
386 }\r
387\r
388 Pico_mcd->s68k_regs[a] = (u8) d;\r
389}\r
390\r
391\r
fa1e5e29 392static u32 OtherRead16End(u32 a, int realsize)\r
cc68a136 393{\r
394 u32 d=0;\r
395\r
0ffefdb8 396#ifndef _ASM_CD_MEMORY_C\r
672ad671 397 if ((a&0xffffc0)==0xa12000) {\r
cb4a513a 398 d=m68k_reg_read16(a);\r
672ad671 399 goto end;\r
400 }\r
cc68a136 401\r
8022f53d 402 if (a==0x400000) {\r
403 if (SRam.data != NULL) d=3; // 64k cart\r
404 goto end;\r
405 }\r
406\r
407 if ((a&0xfe0000)==0x600000) {\r
408 if (SRam.data != NULL) {\r
409 d=SRam.data[((a>>1)&0xffff)+0x2000];\r
410 if (realsize == 8) d|=d<<8;\r
411 }\r
412 goto end;\r
413 }\r
414\r
415 if (a==0x7ffffe) {\r
416 d=Pico_mcd->m.bcram_reg;\r
417 goto end;\r
418 }\r
0ffefdb8 419#endif\r
8022f53d 420\r
ca61ee42 421 elprintf(EL_UIO, "m68k FIXME: unusual r%i: %06x @%06x", realsize&~1, (a&0xfffffe)+(realsize&1), SekPc);\r
cc68a136 422\r
0ffefdb8 423#ifndef _ASM_CD_MEMORY_C\r
cc68a136 424end:\r
0ffefdb8 425#endif\r
cc68a136 426 return d;\r
427}\r
428\r
cc68a136 429\r
fa1e5e29 430static void OtherWrite8End(u32 a, u32 d, int realsize)\r
cc68a136 431{\r
0ffefdb8 432#ifndef _ASM_CD_MEMORY_C\r
cb4a513a 433 if ((a&0xffffc0)==0xa12000) { m68k_reg_write8(a, d); return; }\r
cc68a136 434\r
8022f53d 435 if ((a&0xfe0000)==0x600000) {\r
436 if (SRam.data != NULL && (Pico_mcd->m.bcram_reg&1)) {\r
437 SRam.data[((a>>1)&0xffff)+0x2000]=d;\r
438 SRam.changed = 1;\r
439 }\r
440 return;\r
441 }\r
442\r
443 if (a==0x7fffff) {\r
444 Pico_mcd->m.bcram_reg=d;\r
445 return;\r
446 }\r
0ffefdb8 447#endif\r
8022f53d 448\r
ca61ee42 449 elprintf(EL_UIO, "m68k FIXME: strange w%i: [%06x], %08x @%06x", realsize, a&0xffffff, d, SekPc);\r
cc68a136 450}\r
451\r
0ffefdb8 452#ifndef _ASM_CD_MEMORY_C\r
69996cb7 453#define _CD_MEMORY_C\r
fa1e5e29 454#undef _ASM_MEMORY_C\r
455#include "../MemoryCmn.c"\r
4ff2d527 456#include "cell_map.c"\r
0ffefdb8 457#endif\r
cc68a136 458\r
2433f409 459\r
cc68a136 460// -----------------------------------------------------------------\r
461// Read Rom and read Ram\r
462\r
4ff2d527 463#ifdef _ASM_CD_MEMORY_C\r
0af33fe0 464u32 PicoReadM68k8(u32 a);\r
4ff2d527 465#else\r
81fda4e8 466u32 PicoReadM68k8(u32 a)\r
cc68a136 467{\r
468 u32 d=0;\r
469\r
cc68a136 470 a&=0xffffff;\r
471\r
b542be46 472 switch (a >> 17)\r
473 {\r
474 case 0x00>>1: // BIOS: 000000 - 020000\r
475 d = *(u8 *)(Pico_mcd->bios+(a^1));\r
476 break;\r
477 case 0x02>>1: // prg RAM\r
478 if ((Pico_mcd->m.busreq&3)!=1) {\r
479 u8 *prg_bank = Pico_mcd->prg_ram_b[Pico_mcd->s68k_regs[3]>>6];\r
480 d = *(prg_bank+((a^1)&0x1ffff));\r
481 }\r
482 break;\r
483 case 0x20>>1: // word RAM: 200000 - 220000\r
484 wrdprintf("m68k_wram r8: [%06x] @%06x", a, SekPc);\r
485 a &= 0x1ffff;\r
486 if (Pico_mcd->s68k_regs[3]&4) { // 1M mode?\r
487 int bank = Pico_mcd->s68k_regs[3]&1;\r
488 d = Pico_mcd->word_ram1M[bank][a^1];\r
489 } else {\r
490 // allow access in any mode, like Gens does\r
491 d = Pico_mcd->word_ram2M[a^1];\r
492 }\r
493 wrdprintf("ret = %02x", (u8)d);\r
494 break;\r
495 case 0x22>>1: // word RAM: 220000 - 240000\r
496 wrdprintf("m68k_wram r8: [%06x] @%06x", a, SekPc);\r
497 if (Pico_mcd->s68k_regs[3]&4) { // 1M mode?\r
498 int bank = Pico_mcd->s68k_regs[3]&1;\r
499 a = (a&3) | (cell_map(a >> 2) << 2); // cell arranged\r
500 d = Pico_mcd->word_ram1M[bank][a^1];\r
501 } else {\r
502 // allow access in any mode, like Gens does\r
503 d = Pico_mcd->word_ram2M[(a^1)&0x3ffff];\r
504 }\r
505 wrdprintf("ret = %02x", (u8)d);\r
506 break;\r
507 case 0xc0>>1: case 0xc2>>1: case 0xc4>>1: case 0xc6>>1:\r
508 case 0xc8>>1: case 0xca>>1: case 0xcc>>1: case 0xce>>1:\r
509 case 0xd0>>1: case 0xd2>>1: case 0xd4>>1: case 0xd6>>1:\r
510 case 0xd8>>1: case 0xda>>1: case 0xdc>>1: case 0xde>>1:\r
511 // VDP\r
9761a7d0 512 if ((a&0xe700e0)==0xc00000)\r
513 d=PicoVideoRead8(a);\r
b542be46 514 break;\r
515 case 0xe0>>1: case 0xe2>>1: case 0xe4>>1: case 0xe6>>1:\r
516 case 0xe8>>1: case 0xea>>1: case 0xec>>1: case 0xee>>1:\r
517 case 0xf0>>1: case 0xf2>>1: case 0xf4>>1: case 0xf6>>1:\r
518 case 0xf8>>1: case 0xfa>>1: case 0xfc>>1: case 0xfe>>1:\r
519 // RAM:\r
520 d = *(u8 *)(Pico.ram+((a^1)&0xffff));\r
521 break;\r
522 default:\r
523 if ((a&0xff4000)==0xa00000) { d=z80Read8(a); break; } // Z80 Ram\r
524 if ((a&0xffffc0)==0xa12000)\r
525 rdprintf("m68k_regs r8: [%02x] @%06x", a&0x3f, SekPc);\r
cc68a136 526\r
b542be46 527 d=OtherRead16(a&~1, 8|(a&1)); if ((a&1)==0) d>>=8;\r
cc68a136 528\r
b542be46 529 if ((a&0xffffc0)==0xa12000)\r
530 rdprintf("ret = %02x", (u8)d);\r
531 break;\r
d0d47c5b 532 }\r
533\r
cc68a136 534\r
ca61ee42 535 elprintf(EL_IO, "r8 : %06x, %02x @%06x", a&0xffffff, (u8)d, SekPc);\r
b5e5172d 536#ifdef EMU_CORE_DEBUG\r
537 if (a>=Pico.romsize) {\r
538 lastread_a = a;\r
539 lastread_d[lrp_cyc++&15] = d;\r
540 }\r
cc68a136 541#endif\r
0af33fe0 542 return d;\r
cc68a136 543}\r
4ff2d527 544#endif\r
cc68a136 545\r
ab0607f7 546\r
4ff2d527 547#ifdef _ASM_CD_MEMORY_C\r
0af33fe0 548u32 PicoReadM68k16(u32 a);\r
4ff2d527 549#else\r
0af33fe0 550static u32 PicoReadM68k16(u32 a)\r
cc68a136 551{\r
0af33fe0 552 u32 d=0;\r
cc68a136 553\r
cc68a136 554 a&=0xfffffe;\r
555\r
b542be46 556 switch (a >> 17)\r
557 {\r
558 case 0x00>>1: // BIOS: 000000 - 020000\r
559 d = *(u16 *)(Pico_mcd->bios+a);\r
560 break;\r
561 case 0x02>>1: // prg RAM\r
562 if ((Pico_mcd->m.busreq&3)!=1) {\r
563 u8 *prg_bank = Pico_mcd->prg_ram_b[Pico_mcd->s68k_regs[3]>>6];\r
564 wrdprintf("m68k_prgram r16: [%i,%06x] @%06x", Pico_mcd->s68k_regs[3]>>6, a, SekPc);\r
565 d = *(u16 *)(prg_bank+(a&0x1fffe));\r
566 wrdprintf("ret = %04x", d);\r
567 }\r
568 break;\r
569 case 0x20>>1: // word RAM: 200000 - 220000\r
570 wrdprintf("m68k_wram r16: [%06x] @%06x", a, SekPc);\r
571 a &= 0x1fffe;\r
572 if (Pico_mcd->s68k_regs[3]&4) { // 1M mode?\r
573 int bank = Pico_mcd->s68k_regs[3]&1;\r
574 d = *(u16 *)(Pico_mcd->word_ram1M[bank]+a);\r
575 } else {\r
576 // allow access in any mode, like Gens does\r
577 d = *(u16 *)(Pico_mcd->word_ram2M+a);\r
578 }\r
579 wrdprintf("ret = %04x", d);\r
580 break;\r
581 case 0x22>>1: // word RAM: 220000 - 240000\r
582 wrdprintf("m68k_wram r16: [%06x] @%06x", a, SekPc);\r
583 if (Pico_mcd->s68k_regs[3]&4) { // 1M mode?\r
584 int bank = Pico_mcd->s68k_regs[3]&1;\r
585 a = (a&2) | (cell_map(a >> 2) << 2); // cell arranged\r
586 d = *(u16 *)(Pico_mcd->word_ram1M[bank]+a);\r
587 } else {\r
588 // allow access in any mode, like Gens does\r
589 d = *(u16 *)(Pico_mcd->word_ram2M+(a&0x3fffe));\r
590 }\r
591 wrdprintf("ret = %04x", d);\r
592 break;\r
593 case 0xc0>>1: case 0xc2>>1: case 0xc4>>1: case 0xc6>>1:\r
594 case 0xc8>>1: case 0xca>>1: case 0xcc>>1: case 0xce>>1:\r
595 case 0xd0>>1: case 0xd2>>1: case 0xd4>>1: case 0xd6>>1:\r
596 case 0xd8>>1: case 0xda>>1: case 0xdc>>1: case 0xde>>1:\r
597 // VDP\r
598 if ((a&0xe700e0)==0xc00000)\r
599 d=PicoVideoRead(a);\r
600 break;\r
601 case 0xe0>>1: case 0xe2>>1: case 0xe4>>1: case 0xe6>>1:\r
602 case 0xe8>>1: case 0xea>>1: case 0xec>>1: case 0xee>>1:\r
603 case 0xf0>>1: case 0xf2>>1: case 0xf4>>1: case 0xf6>>1:\r
604 case 0xf8>>1: case 0xfa>>1: case 0xfc>>1: case 0xfe>>1:\r
605 // RAM:\r
606 d=*(u16 *)(Pico.ram+(a&0xfffe));\r
607 break;\r
608 default:\r
609 if ((a&0xffffc0)==0xa12000)\r
610 rdprintf("m68k_regs r16: [%02x] @%06x", a&0x3f, SekPc);\r
cc68a136 611\r
b542be46 612 d = OtherRead16(a, 16);\r
cc68a136 613\r
b542be46 614 if ((a&0xffffc0)==0xa12000)\r
615 rdprintf("ret = %04x", d);\r
616 break;\r
d0d47c5b 617 }\r
618\r
cc68a136 619\r
ca61ee42 620 elprintf(EL_IO, "r16: %06x, %04x @%06x", a&0xffffff, d, SekPc);\r
b5e5172d 621#ifdef EMU_CORE_DEBUG\r
622 if (a>=Pico.romsize) {\r
623 lastread_a = a;\r
624 lastread_d[lrp_cyc++&15] = d;\r
625 }\r
cc68a136 626#endif\r
627 return d;\r
628}\r
4ff2d527 629#endif\r
cc68a136 630\r
ab0607f7 631\r
4ff2d527 632#ifdef _ASM_CD_MEMORY_C\r
633u32 PicoReadM68k32(u32 a);\r
634#else\r
635static u32 PicoReadM68k32(u32 a)\r
cc68a136 636{\r
637 u32 d=0;\r
638\r
cc68a136 639 a&=0xfffffe;\r
640\r
b542be46 641 switch (a >> 17)\r
642 {\r
643 case 0x00>>1: { // BIOS: 000000 - 020000\r
644 u16 *pm=(u16 *)(Pico_mcd->bios+a);\r
645 d = (pm[0]<<16)|pm[1];\r
646 break;\r
647 }\r
648 case 0x02>>1: // prg RAM\r
649 if ((Pico_mcd->m.busreq&3)!=1) {\r
650 u8 *prg_bank = Pico_mcd->prg_ram_b[Pico_mcd->s68k_regs[3]>>6];\r
651 u16 *pm=(u16 *)(prg_bank+(a&0x1fffe));\r
652 d = (pm[0]<<16)|pm[1];\r
653 }\r
654 break;\r
655 case 0x20>>1: // word RAM: 200000 - 220000\r
656 wrdprintf("m68k_wram r32: [%06x] @%06x", a, SekPc);\r
657 a&=0x1fffe;\r
658 if (Pico_mcd->s68k_regs[3]&4) { // 1M mode?\r
659 int bank = Pico_mcd->s68k_regs[3]&1;\r
660 u16 *pm=(u16 *)(Pico_mcd->word_ram1M[bank]+a);\r
661 d = (pm[0]<<16)|pm[1];\r
662 } else {\r
663 // allow access in any mode, like Gens does\r
664 u16 *pm=(u16 *)(Pico_mcd->word_ram2M+a);\r
665 d = (pm[0]<<16)|pm[1];\r
666 }\r
667 wrdprintf("ret = %08x", d);\r
668 break;\r
669 case 0x22>>1: // word RAM: 220000 - 240000\r
670 wrdprintf("m68k_wram r32: [%06x] @%06x", a, SekPc);\r
671 if (Pico_mcd->s68k_regs[3]&4) { // 1M mode, cell arranged?\r
fa1e5e29 672 u32 a1, a2;\r
b542be46 673 int bank = Pico_mcd->s68k_regs[3]&1;\r
fa1e5e29 674 a1 = (a&2) | (cell_map(a >> 2) << 2);\r
4ff2d527 675 if (a&2) a2 = cell_map((a+2) >> 2) << 2;\r
676 else a2 = a1 + 2;\r
677 d = *(u16 *)(Pico_mcd->word_ram1M[bank]+a1) << 16;\r
678 d |= *(u16 *)(Pico_mcd->word_ram1M[bank]+a2);\r
bf098bc5 679 } else {\r
b542be46 680 // allow access in any mode, like Gens does\r
681 u16 *pm=(u16 *)(Pico_mcd->word_ram2M+(a&0x3fffe));\r
682 d = (pm[0]<<16)|pm[1];\r
bf098bc5 683 }\r
b542be46 684 wrdprintf("ret = %08x", d);\r
685 break;\r
686 case 0xc0>>1: case 0xc2>>1: case 0xc4>>1: case 0xc6>>1:\r
687 case 0xc8>>1: case 0xca>>1: case 0xcc>>1: case 0xce>>1:\r
688 case 0xd0>>1: case 0xd2>>1: case 0xd4>>1: case 0xd6>>1:\r
689 case 0xd8>>1: case 0xda>>1: case 0xdc>>1: case 0xde>>1:\r
690 // VDP\r
691 d = (PicoVideoRead(a)<<16)|PicoVideoRead(a+2);\r
692 break;\r
693 case 0xe0>>1: case 0xe2>>1: case 0xe4>>1: case 0xe6>>1:\r
694 case 0xe8>>1: case 0xea>>1: case 0xec>>1: case 0xee>>1:\r
695 case 0xf0>>1: case 0xf2>>1: case 0xf4>>1: case 0xf6>>1:\r
696 case 0xf8>>1: case 0xfa>>1: case 0xfc>>1: case 0xfe>>1: {\r
697 // RAM:\r
698 u16 *pm=(u16 *)(Pico.ram+(a&0xfffe));\r
699 d = (pm[0]<<16)|pm[1];\r
700 break;\r
d0d47c5b 701 }\r
b542be46 702 default:\r
703 if ((a&0xffffc0)==0xa12000)\r
704 rdprintf("m68k_regs r32: [%02x] @%06x", a&0x3f, SekPc);\r
d0d47c5b 705\r
b542be46 706 d = (OtherRead16(a, 32)<<16)|OtherRead16(a+2, 32);\r
672ad671 707\r
b542be46 708 if ((a&0xffffc0)==0xa12000)\r
709 rdprintf("ret = %08x", d);\r
710 break;\r
711 }\r
cc68a136 712\r
672ad671 713\r
ca61ee42 714 elprintf(EL_IO, "r32: %06x, %08x @%06x", a&0xffffff, d, SekPc);\r
b5e5172d 715#ifdef EMU_CORE_DEBUG\r
716 if (a>=Pico.romsize) {\r
717 lastread_a = a;\r
718 lastread_d[lrp_cyc++&15] = d;\r
719 }\r
cc68a136 720#endif\r
721 return d;\r
722}\r
4ff2d527 723#endif\r
cc68a136 724\r
ab0607f7 725\r
cc68a136 726// -----------------------------------------------------------------\r
cc68a136 727\r
4ff2d527 728#ifdef _ASM_CD_MEMORY_C\r
729void PicoWriteM68k8(u32 a,u8 d);\r
730#else\r
81fda4e8 731void PicoWriteM68k8(u32 a,u8 d)\r
cc68a136 732{\r
ca61ee42 733 elprintf(EL_IO, "w8 : %06x, %02x @%06x", a&0xffffff, d, SekPc);\r
b5e5172d 734#ifdef EMU_CORE_DEBUG\r
735 lastwrite_cyc_d[lwp_cyc++&15] = d;\r
736#endif\r
cc68a136 737\r
ab0607f7 738 if ((a&0xe00000)==0xe00000) { // Ram\r
739 *(u8 *)(Pico.ram+((a^1)&0xffff)) = d;\r
740 return;\r
741 }\r
cc68a136 742\r
cc68a136 743 // prg RAM\r
721cd396 744 if ((a&0xfe0000)==0x020000 && (Pico_mcd->m.busreq&3)!=1) {\r
672ad671 745 u8 *prg_bank = Pico_mcd->prg_ram_b[Pico_mcd->s68k_regs[3]>>6];\r
bf098bc5 746 *(u8 *)(prg_bank+((a^1)&0x1ffff))=d;\r
cc68a136 747 return;\r
748 }\r
749\r
b542be46 750 a&=0xffffff;\r
751\r
d0d47c5b 752 // word RAM\r
753 if ((a&0xfc0000)==0x200000) {\r
913ef4b7 754 wrdprintf("m68k_wram w8: [%06x] %02x @%06x", a, d, SekPc);\r
d0d47c5b 755 if (Pico_mcd->s68k_regs[3]&4) { // 1M mode?\r
fa1e5e29 756 int bank = Pico_mcd->s68k_regs[3]&1;\r
757 if (a >= 0x220000)\r
758 a = (a&3) | (cell_map(a >> 2) << 2); // cell arranged\r
759 else a &= 0x1ffff;\r
760 *(u8 *)(Pico_mcd->word_ram1M[bank]+(a^1))=d;\r
d0d47c5b 761 } else {\r
762 // allow access in any mode, like Gens does\r
fa1e5e29 763 *(u8 *)(Pico_mcd->word_ram2M+((a^1)&0x3ffff))=d;\r
d0d47c5b 764 }\r
765 return;\r
766 }\r
767\r
2433f409 768 if ((a&0xffffc0)==0xa12000) {\r
c459aefd 769 rdprintf("m68k_regs w8: [%02x] %02x @%06x", a&0x3f, d, SekPc);\r
2433f409 770 m68k_reg_write8(a, d);\r
771 return;\r
772 }\r
672ad671 773\r
fb9bec94 774 OtherWrite8(a,d);\r
cc68a136 775}\r
4ff2d527 776#endif\r
cc68a136 777\r
ab0607f7 778\r
4ff2d527 779#ifdef _ASM_CD_MEMORY_C\r
780void PicoWriteM68k16(u32 a,u16 d);\r
781#else\r
782static void PicoWriteM68k16(u32 a,u16 d)\r
cc68a136 783{\r
ca61ee42 784 elprintf(EL_IO, "w16: %06x, %04x", a&0xffffff, d);\r
b5e5172d 785#ifdef EMU_CORE_DEBUG\r
786 lastwrite_cyc_d[lwp_cyc++&15] = d;\r
787#endif\r
cc68a136 788\r
ab0607f7 789 if ((a&0xe00000)==0xe00000) { // Ram\r
790 *(u16 *)(Pico.ram+(a&0xfffe))=d;\r
791 return;\r
792 }\r
cc68a136 793\r
cc68a136 794 // prg RAM\r
721cd396 795 if ((a&0xfe0000)==0x020000 && (Pico_mcd->m.busreq&3)!=1) {\r
672ad671 796 u8 *prg_bank = Pico_mcd->prg_ram_b[Pico_mcd->s68k_regs[3]>>6];\r
c008977e 797 wrdprintf("m68k_prgram w16: [%i,%06x] %04x @%06x", Pico_mcd->s68k_regs[3]>>6, a, d, SekPc);\r
cc68a136 798 *(u16 *)(prg_bank+(a&0x1fffe))=d;\r
799 return;\r
800 }\r
801\r
b542be46 802 a&=0xfffffe;\r
803\r
d0d47c5b 804 // word RAM\r
805 if ((a&0xfc0000)==0x200000) {\r
913ef4b7 806 wrdprintf("m68k_wram w16: [%06x] %04x @%06x", a, d, SekPc);\r
d0d47c5b 807 if (Pico_mcd->s68k_regs[3]&4) { // 1M mode?\r
fa1e5e29 808 int bank = Pico_mcd->s68k_regs[3]&1;\r
809 if (a >= 0x220000)\r
810 a = (a&2) | (cell_map(a >> 2) << 2); // cell arranged\r
811 else a &= 0x1fffe;\r
812 *(u16 *)(Pico_mcd->word_ram1M[bank]+a)=d;\r
d0d47c5b 813 } else {\r
814 // allow access in any mode, like Gens does\r
fa1e5e29 815 *(u16 *)(Pico_mcd->word_ram2M+(a&0x3fffe))=d;\r
d0d47c5b 816 }\r
817 return;\r
818 }\r
819\r
7a1f6e45 820 // regs\r
821 if ((a&0xffffc0)==0xa12000) {\r
c459aefd 822 rdprintf("m68k_regs w16: [%02x] %04x @%06x", a&0x3f, d, SekPc);\r
7a1f6e45 823 if (a == 0xe) { // special case, 2 byte writes would be handled differently\r
824 Pico_mcd->s68k_regs[0xe] = d >> 8;\r
825#ifdef USE_POLL_DETECT\r
826 if ((s68k_poll_adclk&0xfe) == 0xe && s68k_poll_cnt > POLL_LIMIT) {\r
6cadc2da 827 SekSetStopS68k(0); s68k_poll_adclk = 0;\r
8f8fe01e 828 elprintf(EL_CDPOLL, "s68k poll release, a=%02x", a);\r
7a1f6e45 829 }\r
830#endif\r
831 return;\r
832 }\r
833 m68k_reg_write8(a, d>>8);\r
834 m68k_reg_write8(a+1,d&0xff);\r
835 return;\r
836 }\r
cc68a136 837\r
b542be46 838 // VDP\r
839 if ((a&0xe700e0)==0xc00000) {\r
840 PicoVideoWrite(a,(u16)d);\r
841 return;\r
842 }\r
843\r
cc68a136 844 OtherWrite16(a,d);\r
845}\r
4ff2d527 846#endif\r
cc68a136 847\r
ab0607f7 848\r
4ff2d527 849#ifdef _ASM_CD_MEMORY_C\r
850void PicoWriteM68k32(u32 a,u32 d);\r
851#else\r
852static void PicoWriteM68k32(u32 a,u32 d)\r
cc68a136 853{\r
ca61ee42 854 elprintf(EL_IO, "w32: %06x, %08x", a&0xffffff, d);\r
b5e5172d 855#ifdef EMU_CORE_DEBUG\r
856 lastwrite_cyc_d[lwp_cyc++&15] = d;\r
857#endif\r
cc68a136 858\r
859 if ((a&0xe00000)==0xe00000)\r
860 {\r
861 // Ram:\r
862 u16 *pm=(u16 *)(Pico.ram+(a&0xfffe));\r
863 pm[0]=(u16)(d>>16); pm[1]=(u16)d;\r
864 return;\r
865 }\r
866\r
cc68a136 867 // prg RAM\r
721cd396 868 if ((a&0xfe0000)==0x020000 && (Pico_mcd->m.busreq&3)!=1) {\r
672ad671 869 u8 *prg_bank = Pico_mcd->prg_ram_b[Pico_mcd->s68k_regs[3]>>6];\r
cc68a136 870 u16 *pm=(u16 *)(prg_bank+(a&0x1fffe));\r
871 pm[0]=(u16)(d>>16); pm[1]=(u16)d;\r
872 return;\r
873 }\r
874\r
b542be46 875 a&=0xfffffe;\r
876\r
672ad671 877 // word RAM\r
d0d47c5b 878 if ((a&0xfc0000)==0x200000) {\r
879 if (d != 0) // don't log clears\r
913ef4b7 880 wrdprintf("m68k_wram w32: [%06x] %08x @%06x", a, d, SekPc);\r
d0d47c5b 881 if (Pico_mcd->s68k_regs[3]&4) { // 1M mode?\r
fa1e5e29 882 int bank = Pico_mcd->s68k_regs[3]&1;\r
883 if (a >= 0x220000) { // cell arranged\r
884 u32 a1, a2;\r
885 a1 = (a&2) | (cell_map(a >> 2) << 2);\r
4ff2d527 886 if (a&2) a2 = cell_map((a+2) >> 2) << 2;\r
887 else a2 = a1 + 2;\r
888 *(u16 *)(Pico_mcd->word_ram1M[bank]+a1) = d >> 16;\r
889 *(u16 *)(Pico_mcd->word_ram1M[bank]+a2) = d;\r
bf098bc5 890 } else {\r
fa1e5e29 891 u16 *pm=(u16 *)(Pico_mcd->word_ram1M[bank]+(a&0x1fffe));\r
892 pm[0]=(u16)(d>>16); pm[1]=(u16)d;\r
bf098bc5 893 }\r
d0d47c5b 894 } else {\r
895 // allow access in any mode, like Gens does\r
fa1e5e29 896 u16 *pm=(u16 *)(Pico_mcd->word_ram2M+(a&0x3fffe));\r
d0d47c5b 897 pm[0]=(u16)(d>>16); pm[1]=(u16)d;\r
898 }\r
672ad671 899 return;\r
d0d47c5b 900 }\r
672ad671 901\r
2433f409 902 if ((a&0xffffc0)==0xa12000) {\r
c459aefd 903 rdprintf("m68k_regs w32: [%02x] %08x @%06x", a&0x3f, d, SekPc);\r
2433f409 904 if ((a&0x3e) == 0xe) dprintf("m68k FIXME: w32 [%02x]", a&0x3f);\r
905 }\r
cc68a136 906\r
b542be46 907 // VDP\r
908 if ((a&0xe700e0)==0xc00000)\r
909 {\r
910 PicoVideoWrite(a, (u16)(d>>16));\r
911 PicoVideoWrite(a+2,(u16)d);\r
912 return;\r
913 }\r
914\r
cc68a136 915 OtherWrite16(a, (u16)(d>>16));\r
916 OtherWrite16(a+2,(u16)d);\r
917}\r
4ff2d527 918#endif\r
cc68a136 919\r
920\r
721cd396 921// -----------------------------------------------------------------\r
922// S68k\r
cc68a136 923// -----------------------------------------------------------------\r
924\r
4ff2d527 925#ifdef _ASM_CD_MEMORY_C\r
0af33fe0 926u32 PicoReadS68k8(u32 a);\r
4ff2d527 927#else\r
0af33fe0 928static u32 PicoReadS68k8(u32 a)\r
cc68a136 929{\r
930 u32 d=0;\r
931\r
b5e5172d 932#ifdef EMU_CORE_DEBUG\r
933 u32 ab=a&0xfffffe;\r
934#endif\r
cc68a136 935 a&=0xffffff;\r
936\r
937 // prg RAM\r
938 if (a < 0x80000) {\r
939 d = *(Pico_mcd->prg_ram+(a^1));\r
940 goto end;\r
941 }\r
942\r
943 // regs\r
944 if ((a&0xfffe00) == 0xff8000) {\r
cb4a513a 945 a &= 0x1ff;\r
946 rdprintf("s68k_regs r8: [%02x] @ %06x", a, SekPcS68k);\r
2433f409 947 if (a >= 0x0e && a < 0x30) {\r
948 d = Pico_mcd->s68k_regs[a];\r
949 s68k_poll_detect(a, d);\r
950 rdprintf("ret = %02x", (u8)d);\r
951 goto end;\r
952 }\r
953 else if (a >= 0x58 && a < 0x68)\r
cb4a513a 954 d = gfx_cd_read(a&~1);\r
955 else d = s68k_reg_read16(a&~1);\r
956 if ((a&1)==0) d>>=8;\r
c459aefd 957 rdprintf("ret = %02x", (u8)d);\r
cc68a136 958 goto end;\r
959 }\r
960\r
d0d47c5b 961 // word RAM (2M area)\r
962 if ((a&0xfc0000)==0x080000) { // 080000-0bffff\r
fa1e5e29 963 // test: batman returns\r
913ef4b7 964 wrdprintf("s68k_wram2M r8: [%06x] @%06x", a, SekPcS68k);\r
fa1e5e29 965 if (Pico_mcd->s68k_regs[3]&4) { // 1M decode mode?\r
3aa1e148 966 int bank = (Pico_mcd->s68k_regs[3]&1)^1;\r
fa1e5e29 967 d = Pico_mcd->word_ram1M[bank][((a>>1)^1)&0x1ffff];\r
968 if (a&1) d &= 0x0f;\r
969 else d >>= 4;\r
d0d47c5b 970 } else {\r
971 // allow access in any mode, like Gens does\r
fa1e5e29 972 d = Pico_mcd->word_ram2M[(a^1)&0x3ffff];\r
d0d47c5b 973 }\r
913ef4b7 974 wrdprintf("ret = %02x", (u8)d);\r
d0d47c5b 975 goto end;\r
976 }\r
977\r
978 // word RAM (1M area)\r
68cba51e 979 if ((a&0xfe0000)==0x0c0000 && (Pico_mcd->s68k_regs[3]&4)) { // 0c0000-0dffff\r
fa1e5e29 980 int bank;\r
913ef4b7 981 wrdprintf("s68k_wram1M r8: [%06x] @%06x", a, SekPcS68k);\r
68cba51e 982// if (!(Pico_mcd->s68k_regs[3]&4))\r
983// dprintf("s68k_wram1M FIXME: wrong mode");\r
3aa1e148 984 bank = (Pico_mcd->s68k_regs[3]&1)^1;\r
fa1e5e29 985 d = Pico_mcd->word_ram1M[bank][(a^1)&0x1ffff];\r
913ef4b7 986 wrdprintf("ret = %02x", (u8)d);\r
d0d47c5b 987 goto end;\r
988 }\r
989\r
4f265db7 990 // PCM\r
991 if ((a&0xff8000)==0xff0000) {\r
ca61ee42 992 elprintf(EL_IO, "s68k_pcm r8: [%06x] @%06x", a, SekPcS68k);\r
4f265db7 993 a &= 0x7fff;\r
994 if (a >= 0x2000)\r
995 d = Pico_mcd->pcm_ram_b[Pico_mcd->pcm.bank][(a>>1)&0xfff];\r
996 else if (a >= 0x20) {\r
997 a &= 0x1e;\r
998 d = Pico_mcd->pcm.ch[a>>2].addr >> PCM_STEP_SHIFT;\r
999 if (a & 2) d >>= 8;\r
1000 }\r
ca61ee42 1001 elprintf(EL_IO, "ret = %02x", (u8)d);\r
4f265db7 1002 goto end;\r
1003 }\r
1004\r
ab0607f7 1005 // bram\r
1006 if ((a&0xff0000)==0xfe0000) {\r
1007 d = Pico_mcd->bram[(a>>1)&0x1fff];\r
1008 goto end;\r
1009 }\r
1010\r
ca61ee42 1011 elprintf(EL_UIO, "s68k r8 : %06x, %02x @%06x", a&0xffffff, (u8)d, SekPcS68k);\r
cc68a136 1012\r
1013 end:\r
1014\r
ca61ee42 1015 elprintf(EL_IO, "s68k r8 : %06x, %02x @%06x", a&0xffffff, (u8)d, SekPcS68k);\r
b5e5172d 1016#ifdef EMU_CORE_DEBUG\r
1017 lastread_a = ab;\r
1018 lastread_d[lrp_cyc++&15] = d;\r
cc68a136 1019#endif\r
0af33fe0 1020 return d;\r
cc68a136 1021}\r
4ff2d527 1022#endif\r
cc68a136 1023\r
ab0607f7 1024\r
4ff2d527 1025#ifdef _ASM_CD_MEMORY_C\r
0af33fe0 1026u32 PicoReadS68k16(u32 a);\r
4ff2d527 1027#else\r
0af33fe0 1028static u32 PicoReadS68k16(u32 a)\r
cc68a136 1029{\r
4f265db7 1030 u32 d=0;\r
cc68a136 1031\r
b5e5172d 1032#ifdef EMU_CORE_DEBUG\r
1033 u32 ab=a&0xfffffe;\r
1034#endif\r
cc68a136 1035 a&=0xfffffe;\r
1036\r
1037 // prg RAM\r
1038 if (a < 0x80000) {\r
c008977e 1039 wrdprintf("s68k_prgram r16: [%06x] @%06x", a, SekPcS68k);\r
cc68a136 1040 d = *(u16 *)(Pico_mcd->prg_ram+a);\r
c008977e 1041 wrdprintf("ret = %04x", d);\r
cc68a136 1042 goto end;\r
1043 }\r
1044\r
1045 // regs\r
1046 if ((a&0xfffe00) == 0xff8000) {\r
cb4a513a 1047 a &= 0x1fe;\r
1048 rdprintf("s68k_regs r16: [%02x] @ %06x", a, SekPcS68k);\r
913ef4b7 1049 if (a >= 0x58 && a < 0x68)\r
cb4a513a 1050 d = gfx_cd_read(a);\r
1051 else d = s68k_reg_read16(a);\r
c459aefd 1052 rdprintf("ret = %04x", d);\r
cc68a136 1053 goto end;\r
1054 }\r
1055\r
d0d47c5b 1056 // word RAM (2M area)\r
1057 if ((a&0xfc0000)==0x080000) { // 080000-0bffff\r
913ef4b7 1058 wrdprintf("s68k_wram2M r16: [%06x] @%06x", a, SekPcS68k);\r
fa1e5e29 1059 if (Pico_mcd->s68k_regs[3]&4) { // 1M decode mode?\r
3aa1e148 1060 int bank = (Pico_mcd->s68k_regs[3]&1)^1;\r
fa1e5e29 1061 d = Pico_mcd->word_ram1M[bank][((a>>1)^1)&0x1ffff];\r
1062 d |= d << 4; d &= ~0xf0;\r
d0d47c5b 1063 } else {\r
1064 // allow access in any mode, like Gens does\r
fa1e5e29 1065 d = *(u16 *)(Pico_mcd->word_ram2M+(a&0x3fffe));\r
d0d47c5b 1066 }\r
913ef4b7 1067 wrdprintf("ret = %04x", d);\r
d0d47c5b 1068 goto end;\r
1069 }\r
1070\r
1071 // word RAM (1M area)\r
68cba51e 1072 if ((a&0xfe0000)==0x0c0000 && (Pico_mcd->s68k_regs[3]&4)) { // 0c0000-0dffff\r
fa1e5e29 1073 int bank;\r
913ef4b7 1074 wrdprintf("s68k_wram1M r16: [%06x] @%06x", a, SekPcS68k);\r
68cba51e 1075// if (!(Pico_mcd->s68k_regs[3]&4))\r
1076// dprintf("s68k_wram1M FIXME: wrong mode");\r
3aa1e148 1077 bank = (Pico_mcd->s68k_regs[3]&1)^1;\r
fa1e5e29 1078 d = *(u16 *)(Pico_mcd->word_ram1M[bank]+(a&0x1fffe));\r
913ef4b7 1079 wrdprintf("ret = %04x", d);\r
ab0607f7 1080 goto end;\r
1081 }\r
1082\r
1083 // bram\r
1084 if ((a&0xff0000)==0xfe0000) {\r
4ff2d527 1085 dprintf("FIXME: s68k_bram r16: [%06x] @%06x", a, SekPcS68k);\r
ab0607f7 1086 a = (a>>1)&0x1fff;\r
4f265db7 1087 d = Pico_mcd->bram[a++]; // Gens does little endian here, and so do we..\r
4ff2d527 1088 d|= Pico_mcd->bram[a++] << 8; // This is most likely wrong\r
ab0607f7 1089 dprintf("ret = %04x", d);\r
d0d47c5b 1090 goto end;\r
1091 }\r
1092\r
4f265db7 1093 // PCM\r
1094 if ((a&0xff8000)==0xff0000) {\r
4ff2d527 1095 dprintf("FIXME: s68k_pcm r16: [%06x] @%06x", a, SekPcS68k);\r
4f265db7 1096 a &= 0x7fff;\r
1097 if (a >= 0x2000)\r
1098 d = Pico_mcd->pcm_ram_b[Pico_mcd->pcm.bank][(a>>1)&0xfff];\r
1099 else if (a >= 0x20) {\r
1100 a &= 0x1e;\r
1101 d = Pico_mcd->pcm.ch[a>>2].addr >> PCM_STEP_SHIFT;\r
1102 if (a & 2) d >>= 8;\r
1103 }\r
1104 dprintf("ret = %04x", d);\r
1105 goto end;\r
1106 }\r
1107\r
ca61ee42 1108 elprintf(EL_UIO, "s68k r16: %06x, %04x @%06x", a&0xffffff, d, SekPcS68k);\r
cc68a136 1109\r
1110 end:\r
1111\r
ca61ee42 1112 elprintf(EL_IO, "s68k r16: %06x, %04x @%06x", a&0xffffff, d, SekPcS68k);\r
b5e5172d 1113#ifdef EMU_CORE_DEBUG\r
1114 lastread_a = ab;\r
1115 lastread_d[lrp_cyc++&15] = d;\r
cc68a136 1116#endif\r
1117 return d;\r
1118}\r
4ff2d527 1119#endif\r
cc68a136 1120\r
ab0607f7 1121\r
4ff2d527 1122#ifdef _ASM_CD_MEMORY_C\r
1123u32 PicoReadS68k32(u32 a);\r
1124#else\r
1125static u32 PicoReadS68k32(u32 a)\r
cc68a136 1126{\r
1127 u32 d=0;\r
1128\r
b5e5172d 1129#ifdef EMU_CORE_DEBUG\r
1130 u32 ab=a&0xfffffe;\r
1131#endif\r
cc68a136 1132 a&=0xfffffe;\r
1133\r
1134 // prg RAM\r
1135 if (a < 0x80000) {\r
1136 u16 *pm=(u16 *)(Pico_mcd->prg_ram+a);\r
1137 d = (pm[0]<<16)|pm[1];\r
1138 goto end;\r
1139 }\r
1140\r
1141 // regs\r
1142 if ((a&0xfffe00) == 0xff8000) {\r
cb4a513a 1143 a &= 0x1fe;\r
1144 rdprintf("s68k_regs r32: [%02x] @ %06x", a, SekPcS68k);\r
913ef4b7 1145 if (a >= 0x58 && a < 0x68)\r
cb4a513a 1146 d = (gfx_cd_read(a)<<16)|gfx_cd_read(a+2);\r
1147 else d = (s68k_reg_read16(a)<<16)|s68k_reg_read16(a+2);\r
c459aefd 1148 rdprintf("ret = %08x", d);\r
cc68a136 1149 goto end;\r
1150 }\r
1151\r
d0d47c5b 1152 // word RAM (2M area)\r
1153 if ((a&0xfc0000)==0x080000) { // 080000-0bffff\r
913ef4b7 1154 wrdprintf("s68k_wram2M r32: [%06x] @%06x", a, SekPcS68k);\r
fa1e5e29 1155 if (Pico_mcd->s68k_regs[3]&4) { // 1M decode mode?\r
3aa1e148 1156 int bank = (Pico_mcd->s68k_regs[3]&1)^1;\r
fa1e5e29 1157 a >>= 1;\r
1158 d = Pico_mcd->word_ram1M[bank][((a+0)^1)&0x1ffff] << 16;\r
1159 d |= Pico_mcd->word_ram1M[bank][((a+1)^1)&0x1ffff];\r
1160 d |= d << 4; d &= 0x0f0f0f0f;\r
d0d47c5b 1161 } else {\r
1162 // allow access in any mode, like Gens does\r
fa1e5e29 1163 u16 *pm=(u16 *)(Pico_mcd->word_ram2M+(a&0x3fffe)); d = (pm[0]<<16)|pm[1];\r
d0d47c5b 1164 }\r
913ef4b7 1165 wrdprintf("ret = %08x", d);\r
d0d47c5b 1166 goto end;\r
1167 }\r
1168\r
1169 // word RAM (1M area)\r
68cba51e 1170 if ((a&0xfe0000)==0x0c0000 && (Pico_mcd->s68k_regs[3]&4)) { // 0c0000-0dffff\r
fa1e5e29 1171 int bank;\r
dca310c4 1172 u16 *pm;\r
913ef4b7 1173 wrdprintf("s68k_wram1M r32: [%06x] @%06x", a, SekPcS68k);\r
68cba51e 1174// if (!(Pico_mcd->s68k_regs[3]&4))\r
1175// dprintf("s68k_wram1M FIXME: wrong mode");\r
3aa1e148 1176 bank = (Pico_mcd->s68k_regs[3]&1)^1;\r
dca310c4 1177 pm=(u16 *)(Pico_mcd->word_ram1M[bank]+(a&0x1fffe)); d = (pm[0]<<16)|pm[1];\r
913ef4b7 1178 wrdprintf("ret = %08x", d);\r
ab0607f7 1179 goto end;\r
1180 }\r
1181\r
4f265db7 1182 // PCM\r
1183 if ((a&0xff8000)==0xff0000) {\r
2433f409 1184 dprintf("s68k_pcm r32: [%06x] @%06x", a, SekPcS68k);\r
4f265db7 1185 a &= 0x7fff;\r
1186 if (a >= 0x2000) {\r
1187 a >>= 1;\r
1188 d = Pico_mcd->pcm_ram_b[Pico_mcd->pcm.bank][a&0xfff] << 16;\r
1189 d |= Pico_mcd->pcm_ram_b[Pico_mcd->pcm.bank][(a+1)&0xfff];\r
1190 } else if (a >= 0x20) {\r
1191 a &= 0x1e;\r
1192 if (a & 2) {\r
1193 a >>= 2;\r
1194 d = (Pico_mcd->pcm.ch[a].addr >> (PCM_STEP_SHIFT-8)) & 0xff0000;\r
1195 d |= (Pico_mcd->pcm.ch[(a+1)&7].addr >> PCM_STEP_SHIFT) & 0xff;\r
1196 } else {\r
1197 d = Pico_mcd->pcm.ch[a>>2].addr >> PCM_STEP_SHIFT;\r
1198 d = ((d<<16)&0xff0000) | ((d>>8)&0xff); // PCM chip is LE\r
1199 }\r
1200 }\r
1201 dprintf("ret = %08x", d);\r
1202 goto end;\r
1203 }\r
1204\r
ab0607f7 1205 // bram\r
1206 if ((a&0xff0000)==0xfe0000) {\r
4ff2d527 1207 dprintf("FIXME: s68k_bram r32: [%06x] @%06x", a, SekPcS68k);\r
ab0607f7 1208 a = (a>>1)&0x1fff;\r
1209 d = Pico_mcd->bram[a++] << 16; // middle endian? TODO: verify against Fusion..\r
1210 d|= Pico_mcd->bram[a++] << 24;\r
1211 d|= Pico_mcd->bram[a++];\r
1212 d|= Pico_mcd->bram[a++] << 8;\r
1213 dprintf("ret = %08x", d);\r
d0d47c5b 1214 goto end;\r
1215 }\r
1216\r
ca61ee42 1217 elprintf(EL_UIO, "s68k r32: %06x, %08x @%06x", a&0xffffff, d, SekPcS68k);\r
cc68a136 1218\r
1219 end:\r
1220\r
ca61ee42 1221 elprintf(EL_IO, "s68k r32: %06x, %08x @%06x", a&0xffffff, d, SekPcS68k);\r
b5e5172d 1222#ifdef EMU_CORE_DEBUG\r
1223 if (ab > 0x78) { // not vectors and stuff\r
1224 lastread_a = ab;\r
1225 lastread_d[lrp_cyc++&15] = d;\r
1226 }\r
cc68a136 1227#endif\r
1228 return d;\r
1229}\r
4ff2d527 1230#endif\r
cc68a136 1231\r
ab0607f7 1232\r
a4030801 1233#ifndef _ASM_CD_MEMORY_C\r
0a051f55 1234/* check: jaguar xj 220 (draws entire world using decode) */\r
1235static void decode_write8(u32 a, u8 d, int r3)\r
1236{\r
3aa1e148 1237 u8 *pd = Pico_mcd->word_ram1M[(r3 & 1)^1] + (((a>>1)^1)&0x1ffff);\r
0a051f55 1238 u8 oldmask = (a&1) ? 0xf0 : 0x0f;\r
1239\r
0a051f55 1240 r3 &= 0x18;\r
1241 d &= 0x0f;\r
1242 if (!(a&1)) d <<= 4;\r
1243\r
0a051f55 1244 if (r3 == 8) {\r
1245 if ((!(*pd & (~oldmask))) && d) goto do_it;\r
1246 } else if (r3 > 8) {\r
1247 if (d) goto do_it;\r
1248 } else {\r
1249 goto do_it;\r
1250 }\r
1251\r
1252 return;\r
1253do_it:\r
1254 *pd = d | (*pd & oldmask);\r
1255}\r
1256\r
1257\r
1258static void decode_write16(u32 a, u16 d, int r3)\r
1259{\r
3aa1e148 1260 u8 *pd = Pico_mcd->word_ram1M[(r3 & 1)^1] + (((a>>1)^1)&0x1ffff);\r
0a051f55 1261\r
1262 //if ((a & 0x3ffff) < 0x28000) return;\r
1263\r
1264 r3 &= 0x18;\r
1265 d &= 0x0f0f;\r
1266 d |= d >> 4;\r
1267\r
1268 if (r3 == 8) {\r
1269 u8 dold = *pd;\r
1270 if (!(dold & 0xf0)) dold |= d & 0xf0;\r
1271 if (!(dold & 0x0f)) dold |= d & 0x0f;\r
1272 *pd = dold;\r
1273 } else if (r3 > 8) {\r
1274 u8 dold = *pd;\r
1275 if (!(d & 0xf0)) d |= dold & 0xf0;\r
1276 if (!(d & 0x0f)) d |= dold & 0x0f;\r
1277 *pd = d;\r
1278 } else {\r
1279 *pd = d;\r
1280 }\r
0a051f55 1281}\r
a4030801 1282#endif\r
0a051f55 1283\r
cc68a136 1284// -----------------------------------------------------------------\r
1285\r
4ff2d527 1286#ifdef _ASM_CD_MEMORY_C\r
1287void PicoWriteS68k8(u32 a,u8 d);\r
1288#else\r
1289static void PicoWriteS68k8(u32 a,u8 d)\r
cc68a136 1290{\r
ca61ee42 1291 elprintf(EL_IO, "s68k w8 : %06x, %02x @%06x", a&0xffffff, d, SekPcS68k);\r
cc68a136 1292\r
1293 a&=0xffffff;\r
1294\r
b5e5172d 1295#ifdef EMU_CORE_DEBUG\r
1296 lastwrite_cyc_d[lwp_cyc++&15] = d;\r
1297#endif\r
1298\r
cc68a136 1299 // prg RAM\r
1300 if (a < 0x80000) {\r
1301 u8 *pm=(u8 *)(Pico_mcd->prg_ram+(a^1));\r
721cd396 1302 if (a >= (Pico_mcd->s68k_regs[2]<<8)) *pm=d;\r
cc68a136 1303 return;\r
1304 }\r
1305\r
1306 // regs\r
1307 if ((a&0xfffe00) == 0xff8000) {\r
cb4a513a 1308 a &= 0x1ff;\r
1309 rdprintf("s68k_regs w8: [%02x] %02x @ %06x", a, d, SekPcS68k);\r
913ef4b7 1310 if (a >= 0x58 && a < 0x68)\r
48e8482f 1311 gfx_cd_write16(a&~1, (d<<8)|d);\r
cb4a513a 1312 else s68k_reg_write8(a,d);\r
cc68a136 1313 return;\r
1314 }\r
1315\r
d0d47c5b 1316 // word RAM (2M area)\r
1317 if ((a&0xfc0000)==0x080000) { // 080000-0bffff\r
0a051f55 1318 int r3 = Pico_mcd->s68k_regs[3];\r
913ef4b7 1319 wrdprintf("s68k_wram2M w8: [%06x] %02x @%06x", a, d, SekPcS68k);\r
0a051f55 1320 if (r3 & 4) { // 1M decode mode?\r
1321 decode_write8(a, d, r3);\r
d0d47c5b 1322 } else {\r
1323 // allow access in any mode, like Gens does\r
fa1e5e29 1324 *(u8 *)(Pico_mcd->word_ram2M+((a^1)&0x3ffff))=d;\r
d0d47c5b 1325 }\r
1326 return;\r
1327 }\r
1328\r
1329 // word RAM (1M area)\r
68cba51e 1330 if ((a&0xfe0000)==0x0c0000 && (Pico_mcd->s68k_regs[3]&4)) { // 0c0000-0dffff\r
1331 // Wing Commander tries to write here in wrong mode\r
fa1e5e29 1332 int bank;\r
d0d47c5b 1333 if (d)\r
913ef4b7 1334 wrdprintf("s68k_wram1M w8: [%06x] %02x @%06x", a, d, SekPcS68k);\r
68cba51e 1335// if (!(Pico_mcd->s68k_regs[3]&4))\r
1336// dprintf("s68k_wram1M FIXME: wrong mode");\r
3aa1e148 1337 bank = (Pico_mcd->s68k_regs[3]&1)^1;\r
fa1e5e29 1338 *(u8 *)(Pico_mcd->word_ram1M[bank]+((a^1)&0x1ffff))=d;\r
d0d47c5b 1339 return;\r
1340 }\r
1341\r
4f265db7 1342 // PCM\r
1343 if ((a&0xff8000)==0xff0000) {\r
1344 a &= 0x7fff;\r
1345 if (a >= 0x2000)\r
1346 Pico_mcd->pcm_ram_b[Pico_mcd->pcm.bank][(a>>1)&0xfff] = d;\r
1347 else if (a < 0x12)\r
1348 pcm_write(a>>1, d);\r
1349 return;\r
1350 }\r
1351\r
ab0607f7 1352 // bram\r
1353 if ((a&0xff0000)==0xfe0000) {\r
1354 Pico_mcd->bram[(a>>1)&0x1fff] = d;\r
1355 SRam.changed = 1;\r
1356 return;\r
1357 }\r
1358\r
ca61ee42 1359 elprintf(EL_UIO, "s68k w8 : %06x, %02x @%06x", a&0xffffff, d, SekPcS68k);\r
cc68a136 1360}\r
4ff2d527 1361#endif\r
cc68a136 1362\r
ab0607f7 1363\r
4ff2d527 1364#ifdef _ASM_CD_MEMORY_C\r
1365void PicoWriteS68k16(u32 a,u16 d);\r
1366#else\r
1367static void PicoWriteS68k16(u32 a,u16 d)\r
cc68a136 1368{\r
ca61ee42 1369 elprintf(EL_IO, "s68k w16: %06x, %04x @%06x", a&0xffffff, d, SekPcS68k);\r
cc68a136 1370\r
1371 a&=0xfffffe;\r
1372\r
b5e5172d 1373#ifdef EMU_CORE_DEBUG\r
1374 lastwrite_cyc_d[lwp_cyc++&15] = d;\r
1375#endif\r
1376\r
cc68a136 1377 // prg RAM\r
1378 if (a < 0x80000) {\r
c008977e 1379 wrdprintf("s68k_prgram w16: [%06x] %04x @%06x", a, d, SekPcS68k);\r
721cd396 1380 if (a >= (Pico_mcd->s68k_regs[2]<<8)) // needed for Dungeon Explorer\r
1381 *(u16 *)(Pico_mcd->prg_ram+a)=d;\r
cc68a136 1382 return;\r
1383 }\r
1384\r
1385 // regs\r
1386 if ((a&0xfffe00) == 0xff8000) {\r
cb4a513a 1387 a &= 0x1fe;\r
1388 rdprintf("s68k_regs w16: [%02x] %04x @ %06x", a, d, SekPcS68k);\r
913ef4b7 1389 if (a >= 0x58 && a < 0x68)\r
48e8482f 1390 gfx_cd_write16(a, d);\r
cb4a513a 1391 else {\r
1cd356a3 1392 if (a == 0xe) { // special case, 2 byte writes would be handled differently\r
1393 Pico_mcd->s68k_regs[0xf] = d;\r
4ff2d527 1394 return;\r
1cd356a3 1395 }\r
cb4a513a 1396 s68k_reg_write8(a, d>>8);\r
1397 s68k_reg_write8(a+1,d&0xff);\r
1398 }\r
cc68a136 1399 return;\r
1400 }\r
1401\r
d0d47c5b 1402 // word RAM (2M area)\r
1403 if ((a&0xfc0000)==0x080000) { // 080000-0bffff\r
0a051f55 1404 int r3 = Pico_mcd->s68k_regs[3];\r
913ef4b7 1405 wrdprintf("s68k_wram2M w16: [%06x] %04x @%06x", a, d, SekPcS68k);\r
0a051f55 1406 if (r3 & 4) { // 1M decode mode?\r
1407 decode_write16(a, d, r3);\r
d0d47c5b 1408 } else {\r
1409 // allow access in any mode, like Gens does\r
fa1e5e29 1410 *(u16 *)(Pico_mcd->word_ram2M+(a&0x3fffe))=d;\r
d0d47c5b 1411 }\r
1412 return;\r
1413 }\r
1414\r
1415 // word RAM (1M area)\r
68cba51e 1416 if ((a&0xfe0000)==0x0c0000 && (Pico_mcd->s68k_regs[3]&4)) { // 0c0000-0dffff\r
fa1e5e29 1417 int bank;\r
d0d47c5b 1418 if (d)\r
913ef4b7 1419 wrdprintf("s68k_wram1M w16: [%06x] %04x @%06x", a, d, SekPcS68k);\r
68cba51e 1420// if (!(Pico_mcd->s68k_regs[3]&4))\r
1421// dprintf("s68k_wram1M FIXME: wrong mode");\r
3aa1e148 1422 bank = (Pico_mcd->s68k_regs[3]&1)^1;\r
fa1e5e29 1423 *(u16 *)(Pico_mcd->word_ram1M[bank]+(a&0x1fffe))=d;\r
d0d47c5b 1424 return;\r
1425 }\r
1426\r
4f265db7 1427 // PCM\r
1428 if ((a&0xff8000)==0xff0000) {\r
1429 a &= 0x7fff;\r
1430 if (a >= 0x2000)\r
1431 Pico_mcd->pcm_ram_b[Pico_mcd->pcm.bank][(a>>1)&0xfff] = d;\r
1432 else if (a < 0x12)\r
1433 pcm_write(a>>1, d & 0xff);\r
1434 return;\r
1435 }\r
1436\r
ab0607f7 1437 // bram\r
1438 if ((a&0xff0000)==0xfe0000) {\r
1cd356a3 1439 dprintf("s68k_bram w16: [%06x] %04x @%06x", a, d, SekPcS68k);\r
ab0607f7 1440 a = (a>>1)&0x1fff;\r
1441 Pico_mcd->bram[a++] = d; // Gens does little endian here, an so do we..\r
1442 Pico_mcd->bram[a++] = d >> 8;\r
1443 SRam.changed = 1;\r
1444 return;\r
1445 }\r
1446\r
ca61ee42 1447 elprintf(EL_UIO, "s68k w16: %06x, %04x @%06x", a&0xffffff, d, SekPcS68k);\r
cc68a136 1448}\r
4ff2d527 1449#endif\r
cc68a136 1450\r
ab0607f7 1451\r
4ff2d527 1452#ifdef _ASM_CD_MEMORY_C\r
1453void PicoWriteS68k32(u32 a,u32 d);\r
1454#else\r
1455static void PicoWriteS68k32(u32 a,u32 d)\r
cc68a136 1456{\r
ca61ee42 1457 elprintf(EL_IO, "s68k w32: %06x, %08x @%06x", a&0xffffff, d, SekPcS68k);\r
cc68a136 1458\r
1459 a&=0xfffffe;\r
1460\r
b5e5172d 1461#ifdef EMU_CORE_DEBUG\r
1462 lastwrite_cyc_d[lwp_cyc++&15] = d;\r
1463#endif\r
1464\r
cc68a136 1465 // prg RAM\r
1466 if (a < 0x80000) {\r
721cd396 1467 if (a >= (Pico_mcd->s68k_regs[2]<<8)) {\r
1468 u16 *pm=(u16 *)(Pico_mcd->prg_ram+a);\r
1469 pm[0]=(u16)(d>>16); pm[1]=(u16)d;\r
1470 }\r
cc68a136 1471 return;\r
1472 }\r
1473\r
1474 // regs\r
1475 if ((a&0xfffe00) == 0xff8000) {\r
cb4a513a 1476 a &= 0x1fe;\r
1477 rdprintf("s68k_regs w32: [%02x] %08x @ %06x", a, d, SekPcS68k);\r
913ef4b7 1478 if (a >= 0x58 && a < 0x68) {\r
48e8482f 1479 gfx_cd_write16(a, d>>16);\r
1480 gfx_cd_write16(a+2, d&0xffff);\r
cb4a513a 1481 } else {\r
2433f409 1482 if ((a&0x1fe) == 0xe) dprintf("s68k FIXME: w32 [%02x]", a&0x3f);\r
cb4a513a 1483 s68k_reg_write8(a, d>>24);\r
1484 s68k_reg_write8(a+1,(d>>16)&0xff);\r
1485 s68k_reg_write8(a+2,(d>>8) &0xff);\r
1486 s68k_reg_write8(a+3, d &0xff);\r
1487 }\r
cc68a136 1488 return;\r
1489 }\r
1490\r
d0d47c5b 1491 // word RAM (2M area)\r
1492 if ((a&0xfc0000)==0x080000) { // 080000-0bffff\r
0a051f55 1493 int r3 = Pico_mcd->s68k_regs[3];\r
913ef4b7 1494 wrdprintf("s68k_wram2M w32: [%06x] %08x @%06x", a, d, SekPcS68k);\r
0a051f55 1495 if (r3 & 4) { // 1M decode mode?\r
1496 decode_write16(a , d >> 16, r3);\r
1497 decode_write16(a+2, d , r3);\r
d0d47c5b 1498 } else {\r
1499 // allow access in any mode, like Gens does\r
fa1e5e29 1500 u16 *pm=(u16 *)(Pico_mcd->word_ram2M+(a&0x3fffe));\r
d0d47c5b 1501 pm[0]=(u16)(d>>16); pm[1]=(u16)d;\r
1502 }\r
1503 return;\r
1504 }\r
1505\r
1506 // word RAM (1M area)\r
68cba51e 1507 if ((a&0xfe0000)==0x0c0000 && (Pico_mcd->s68k_regs[3]&4)) { // 0c0000-0dffff\r
fa1e5e29 1508 int bank;\r
1509 u16 *pm;\r
d0d47c5b 1510 if (d)\r
913ef4b7 1511 wrdprintf("s68k_wram1M w32: [%06x] %08x @%06x", a, d, SekPcS68k);\r
68cba51e 1512// if (!(Pico_mcd->s68k_regs[3]&4))\r
1513// dprintf("s68k_wram1M FIXME: wrong mode");\r
3aa1e148 1514 bank = (Pico_mcd->s68k_regs[3]&1)^1;\r
fa1e5e29 1515 pm=(u16 *)(Pico_mcd->word_ram1M[bank]+(a&0x1fffe));\r
1516 pm[0]=(u16)(d>>16); pm[1]=(u16)d;\r
d0d47c5b 1517 return;\r
1518 }\r
ab0607f7 1519\r
4f265db7 1520 // PCM\r
1521 if ((a&0xff8000)==0xff0000) {\r
1522 a &= 0x7fff;\r
1523 if (a >= 0x2000) {\r
1524 a >>= 1;\r
1525 Pico_mcd->pcm_ram_b[Pico_mcd->pcm.bank][a&0xfff] = (d >> 16);\r
1526 Pico_mcd->pcm_ram_b[Pico_mcd->pcm.bank][(a+1)&0xfff] = d;\r
1527 } else if (a < 0x12) {\r
1528 a >>= 1;\r
1529 pcm_write(a, (d>>16) & 0xff);\r
1530 pcm_write(a+1, d & 0xff);\r
1531 }\r
1532 return;\r
1533 }\r
1534\r
ab0607f7 1535 // bram\r
1536 if ((a&0xff0000)==0xfe0000) {\r
1cd356a3 1537 dprintf("s68k_bram w32: [%06x] %08x @%06x", a, d, SekPcS68k);\r
ab0607f7 1538 a = (a>>1)&0x1fff;\r
1539 Pico_mcd->bram[a++] = d >> 16; // middle endian? verify?\r
1540 Pico_mcd->bram[a++] = d >> 24;\r
1541 Pico_mcd->bram[a++] = d;\r
1542 Pico_mcd->bram[a++] = d >> 8;\r
1543 SRam.changed = 1;\r
1544 return;\r
1545 }\r
1546\r
ca61ee42 1547 elprintf(EL_UIO, "s68k w32: %06x, %08x @%06x", a&0xffffff, d, SekPcS68k);\r
cc68a136 1548}\r
4ff2d527 1549#endif\r
cc68a136 1550\r
1551\r
1552// -----------------------------------------------------------------\r
1553\r
b837b69b 1554\r
3aa1e148 1555#ifdef EMU_C68K\r
b837b69b 1556static __inline int PicoMemBaseM68k(u32 pc)\r
1557{\r
fa1e5e29 1558 if ((pc&0xe00000)==0xe00000)\r
1559 return (int)Pico.ram-(pc&0xff0000); // Program Counter in Ram\r
b837b69b 1560\r
1561 if (pc < 0x20000)\r
fa1e5e29 1562 return (int)Pico_mcd->bios; // Program Counter in BIOS\r
1563\r
1564 if ((pc&0xfc0000)==0x200000)\r
b837b69b 1565 {\r
fa1e5e29 1566 if (!(Pico_mcd->s68k_regs[3]&4))\r
1567 return (int)Pico_mcd->word_ram2M - 0x200000; // Program Counter in Word Ram\r
1568 if (pc < 0x220000) {\r
3aa1e148 1569 int bank = Pico_mcd->s68k_regs[3]&1;\r
fa1e5e29 1570 return (int)Pico_mcd->word_ram1M[bank] - 0x200000;\r
1571 }\r
b837b69b 1572 }\r
1573\r
fa1e5e29 1574 // Error - Program Counter is invalid\r
ca61ee42 1575 elprintf(EL_ANOMALY, "m68k FIXME: unhandled jump to %06x", pc);\r
fa1e5e29 1576\r
1577 return (int)Pico_mcd->bios;\r
b837b69b 1578}\r
1579\r
1580\r
1581static u32 PicoCheckPcM68k(u32 pc)\r
1582{\r
3aa1e148 1583 pc-=PicoCpuCM68k.membase; // Get real pc\r
b837b69b 1584 pc&=0xfffffe;\r
1585\r
3aa1e148 1586 PicoCpuCM68k.membase=PicoMemBaseM68k(pc);\r
b837b69b 1587\r
3aa1e148 1588 return PicoCpuCM68k.membase+pc;\r
b837b69b 1589}\r
1590\r
1591\r
1592static __inline int PicoMemBaseS68k(u32 pc)\r
1593{\r
fa1e5e29 1594 if (pc < 0x80000) // PRG RAM\r
1595 return (int)Pico_mcd->prg_ram;\r
b837b69b 1596\r
fa1e5e29 1597 if ((pc&0xfc0000)==0x080000) // WORD RAM 2M area (assume we are in the right mode..)\r
1598 return (int)Pico_mcd->word_ram2M - 0x080000;\r
1599\r
1600 if ((pc&0xfe0000)==0x0c0000) { // word RAM 1M area\r
3aa1e148 1601 int bank = (Pico_mcd->s68k_regs[3]&1)^1;\r
fa1e5e29 1602 return (int)Pico_mcd->word_ram1M[bank] - 0x0c0000;\r
b837b69b 1603 }\r
1604\r
fa1e5e29 1605 // Error - Program Counter is invalid\r
ca61ee42 1606 elprintf(EL_ANOMALY, "s68k FIXME: unhandled jump to %06x", pc);\r
fa1e5e29 1607\r
1608 return (int)Pico_mcd->prg_ram;\r
b837b69b 1609}\r
1610\r
1611\r
1612static u32 PicoCheckPcS68k(u32 pc)\r
1613{\r
3aa1e148 1614 pc-=PicoCpuCS68k.membase; // Get real pc\r
b837b69b 1615 pc&=0xfffffe;\r
1616\r
3aa1e148 1617 PicoCpuCS68k.membase=PicoMemBaseS68k(pc);\r
b837b69b 1618\r
3aa1e148 1619 return PicoCpuCS68k.membase+pc;\r
b837b69b 1620}\r
1621#endif\r
1622\r
3aa1e148 1623#ifndef _ASM_CD_MEMORY_C\r
1624void PicoMemResetCD(int r3)\r
1625{\r
1626#ifdef EMU_F68K\r
1627 // update fetchmap..\r
1628 int i;\r
1629 if (!(r3 & 4))\r
1630 {\r
1631 for (i = M68K_FETCHBANK1*2/16; (i<<(24-FAMEC_FETCHBITS)) < 0x240000; i++)\r
1632 PicoCpuFM68k.Fetch[i] = (unsigned int)Pico_mcd->word_ram2M - 0x200000;\r
1633 }\r
1634 else\r
1635 {\r
1636 for (i = M68K_FETCHBANK1*2/16; (i<<(24-FAMEC_FETCHBITS)) < 0x220000; i++)\r
1637 PicoCpuFM68k.Fetch[i] = (unsigned int)Pico_mcd->word_ram1M[r3 & 1] - 0x200000;\r
1638 for (i = M68K_FETCHBANK1*0x0c/0x100; (i<<(24-FAMEC_FETCHBITS)) < 0x0e0000; i++)\r
1639 PicoCpuFS68k.Fetch[i] = (unsigned int)Pico_mcd->word_ram1M[(r3&1)^1] - 0x0c0000;\r
1640 }\r
1641#endif\r
1642}\r
1643#endif\r
b837b69b 1644\r
9037e45d 1645#ifdef EMU_M68K\r
1646static void m68k_mem_setup_cd(void);\r
1647#endif\r
1648\r
eff55556 1649PICO_INTERNAL void PicoMemSetupCD(void)\r
b837b69b 1650{\r
f53f286a 1651 // additional handlers for common code\r
1652 PicoRead16Hook = OtherRead16End;\r
1653 PicoWrite8Hook = OtherWrite8End;\r
1654\r
b837b69b 1655#ifdef EMU_C68K\r
1656 // Setup m68k memory callbacks:\r
3aa1e148 1657 PicoCpuCM68k.checkpc=PicoCheckPcM68k;\r
1658 PicoCpuCM68k.fetch8 =PicoCpuCM68k.read8 =PicoReadM68k8;\r
1659 PicoCpuCM68k.fetch16=PicoCpuCM68k.read16=PicoReadM68k16;\r
1660 PicoCpuCM68k.fetch32=PicoCpuCM68k.read32=PicoReadM68k32;\r
1661 PicoCpuCM68k.write8 =PicoWriteM68k8;\r
1662 PicoCpuCM68k.write16=PicoWriteM68k16;\r
1663 PicoCpuCM68k.write32=PicoWriteM68k32;\r
b837b69b 1664 // s68k\r
3aa1e148 1665 PicoCpuCS68k.checkpc=PicoCheckPcS68k;\r
1666 PicoCpuCS68k.fetch8 =PicoCpuCS68k.read8 =PicoReadS68k8;\r
1667 PicoCpuCS68k.fetch16=PicoCpuCS68k.read16=PicoReadS68k16;\r
1668 PicoCpuCS68k.fetch32=PicoCpuCS68k.read32=PicoReadS68k32;\r
1669 PicoCpuCS68k.write8 =PicoWriteS68k8;\r
1670 PicoCpuCS68k.write16=PicoWriteS68k16;\r
1671 PicoCpuCS68k.write32=PicoWriteS68k32;\r
b837b69b 1672#endif\r
3aa1e148 1673#ifdef EMU_F68K\r
1674 // m68k\r
1675 PicoCpuFM68k.read_byte =PicoReadM68k8;\r
1676 PicoCpuFM68k.read_word =PicoReadM68k16;\r
1677 PicoCpuFM68k.read_long =PicoReadM68k32;\r
1678 PicoCpuFM68k.write_byte=PicoWriteM68k8;\r
1679 PicoCpuFM68k.write_word=PicoWriteM68k16;\r
1680 PicoCpuFM68k.write_long=PicoWriteM68k32;\r
1681 // s68k\r
1682 PicoCpuFS68k.read_byte =PicoReadS68k8;\r
1683 PicoCpuFS68k.read_word =PicoReadS68k16;\r
1684 PicoCpuFS68k.read_long =PicoReadS68k32;\r
1685 PicoCpuFS68k.write_byte=PicoWriteS68k8;\r
1686 PicoCpuFS68k.write_word=PicoWriteS68k16;\r
1687 PicoCpuFS68k.write_long=PicoWriteS68k32;\r
1688\r
1689 // setup FAME fetchmap\r
1690 {\r
1691 int i;\r
1692 // M68k\r
1693 // by default, point everything to fitst 64k of ROM (BIOS)\r
1694 for (i = 0; i < M68K_FETCHBANK1; i++)\r
1695 PicoCpuFM68k.Fetch[i] = (unsigned int)Pico.rom - (i<<(24-FAMEC_FETCHBITS));\r
1696 // now real ROM (BIOS)\r
1697 for (i = 0; i < M68K_FETCHBANK1 && (i<<(24-FAMEC_FETCHBITS)) < Pico.romsize; i++)\r
1698 PicoCpuFM68k.Fetch[i] = (unsigned int)Pico.rom;\r
1699 // .. and RAM\r
1700 for (i = M68K_FETCHBANK1*14/16; i < M68K_FETCHBANK1; i++)\r
1701 PicoCpuFM68k.Fetch[i] = (unsigned int)Pico.ram - (i<<(24-FAMEC_FETCHBITS));\r
1702 // S68k\r
1703 // PRG RAM is default\r
1704 for (i = 0; i < M68K_FETCHBANK1; i++)\r
1705 PicoCpuFS68k.Fetch[i] = (unsigned int)Pico_mcd->prg_ram - (i<<(24-FAMEC_FETCHBITS));\r
1706 // real PRG RAM\r
1707 for (i = 0; i < M68K_FETCHBANK1 && (i<<(24-FAMEC_FETCHBITS)) < 0x80000; i++)\r
1708 PicoCpuFS68k.Fetch[i] = (unsigned int)Pico_mcd->prg_ram;\r
1709 // WORD RAM 2M area\r
1710 for (i = M68K_FETCHBANK1*0x08/0x100; i < M68K_FETCHBANK1 && (i<<(24-FAMEC_FETCHBITS)) < 0xc0000; i++)\r
1711 PicoCpuFS68k.Fetch[i] = (unsigned int)Pico_mcd->word_ram2M - 0x80000;\r
1712 // PicoMemResetCD() will setup word ram for both\r
1713 }\r
1714#endif\r
9037e45d 1715#ifdef EMU_M68K\r
1716 m68k_mem_setup_cd();\r
1717#endif\r
3aa1e148 1718\r
7a1f6e45 1719 // m68k_poll_addr = m68k_poll_cnt = 0;\r
1720 s68k_poll_adclk = s68k_poll_cnt = 0;\r
b837b69b 1721}\r
1722\r
1723\r
cc68a136 1724#ifdef EMU_M68K\r
9037e45d 1725static unsigned int PicoReadCD8w (unsigned int a) {\r
3aa1e148 1726 return m68ki_cpu_p == &PicoCpuMS68k ? PicoReadS68k8(a) : PicoReadM68k8(a);\r
cc68a136 1727}\r
9037e45d 1728static unsigned int PicoReadCD16w(unsigned int a) {\r
3aa1e148 1729 return m68ki_cpu_p == &PicoCpuMS68k ? PicoReadS68k16(a) : PicoReadM68k16(a);\r
cc68a136 1730}\r
9037e45d 1731static unsigned int PicoReadCD32w(unsigned int a) {\r
3aa1e148 1732 return m68ki_cpu_p == &PicoCpuMS68k ? PicoReadS68k32(a) : PicoReadM68k32(a);\r
cc68a136 1733}\r
9037e45d 1734static void PicoWriteCD8w (unsigned int a, unsigned char d) {\r
3aa1e148 1735 if (m68ki_cpu_p == &PicoCpuMS68k) PicoWriteS68k8(a, d); else PicoWriteM68k8(a, d);\r
cc68a136 1736}\r
9037e45d 1737static void PicoWriteCD16w(unsigned int a, unsigned short d) {\r
3aa1e148 1738 if (m68ki_cpu_p == &PicoCpuMS68k) PicoWriteS68k16(a, d); else PicoWriteM68k16(a, d);\r
cc68a136 1739}\r
9037e45d 1740static void PicoWriteCD32w(unsigned int a, unsigned int d) {\r
3aa1e148 1741 if (m68ki_cpu_p == &PicoCpuMS68k) PicoWriteS68k32(a, d); else PicoWriteM68k32(a, d);\r
cc68a136 1742}\r
1743\r
1744// these are allowed to access RAM\r
9037e45d 1745static unsigned int m68k_read_pcrelative_CD8 (unsigned int a)\r
b5e5172d 1746{\r
cc68a136 1747 a&=0xffffff;\r
3aa1e148 1748 if(m68ki_cpu_p == &PicoCpuMS68k) {\r
cc68a136 1749 if (a < 0x80000) return *(u8 *)(Pico_mcd->prg_ram+(a^1)); // PRG Ram\r
fa1e5e29 1750 if ((a&0xfc0000)==0x080000 && !(Pico_mcd->s68k_regs[3]&4)) // word RAM (2M area: 080000-0bffff)\r
1751 return *(u8 *)(Pico_mcd->word_ram2M+((a^1)&0x3ffff));\r
1752 if ((a&0xfe0000)==0x0c0000 && (Pico_mcd->s68k_regs[3]&4)) { // word RAM (1M area: 0c0000-0dffff)\r
3aa1e148 1753 int bank = (Pico_mcd->s68k_regs[3]&1)^1;\r
fa1e5e29 1754 return *(u8 *)(Pico_mcd->word_ram1M[bank]+((a^1)&0x1ffff));\r
1755 }\r
ca61ee42 1756 elprintf(EL_ANOMALY, "s68k_read_pcrelative_CD8 FIXME: can't handle %06x", a);\r
cc68a136 1757 } else {\r
cc68a136 1758 if((a&0xe00000)==0xe00000) return *(u8 *)(Pico.ram+((a^1)&0xffff)); // Ram\r
fa1e5e29 1759 if(a<0x20000) return *(u8 *)(Pico.rom+(a^1)); // Bios\r
1760 if((a&0xfc0000)==0x200000) { // word RAM\r
1761 if(!(Pico_mcd->s68k_regs[3]&4)) // 2M?\r
1762 return *(u8 *)(Pico_mcd->word_ram2M+((a^1)&0x3ffff));\r
1763 else if (a < 0x220000) {\r
1764 int bank = Pico_mcd->s68k_regs[3]&1;\r
1765 return *(u8 *)(Pico_mcd->word_ram1M[bank]+((a^1)&0x1ffff));\r
1766 }\r
1767 }\r
ca61ee42 1768 elprintf(EL_ANOMALY, "m68k_read_pcrelative_CD8 FIXME: can't handle %06x", a);\r
cc68a136 1769 }\r
1770 return 0;//(u8) lastread_d;\r
1771}\r
9037e45d 1772static unsigned int m68k_read_pcrelative_CD16(unsigned int a)\r
b5e5172d 1773{\r
cc68a136 1774 a&=0xffffff;\r
3aa1e148 1775 if(m68ki_cpu_p == &PicoCpuMS68k) {\r
cc68a136 1776 if (a < 0x80000) return *(u16 *)(Pico_mcd->prg_ram+(a&~1)); // PRG Ram\r
fa1e5e29 1777 if ((a&0xfc0000)==0x080000 && !(Pico_mcd->s68k_regs[3]&4)) // word RAM (2M area: 080000-0bffff)\r
1778 return *(u16 *)(Pico_mcd->word_ram2M+(a&0x3fffe));\r
1779 if ((a&0xfe0000)==0x0c0000 && (Pico_mcd->s68k_regs[3]&4)) { // word RAM (1M area: 0c0000-0dffff)\r
3aa1e148 1780 int bank = (Pico_mcd->s68k_regs[3]&1)^1;\r
fa1e5e29 1781 return *(u16 *)(Pico_mcd->word_ram1M[bank]+(a&0x1fffe));\r
1782 }\r
ca61ee42 1783 elprintf(EL_ANOMALY, "s68k_read_pcrelative_CD16 FIXME: can't handle %06x", a);\r
cc68a136 1784 } else {\r
cc68a136 1785 if((a&0xe00000)==0xe00000) return *(u16 *)(Pico.ram+(a&0xfffe)); // Ram\r
fa1e5e29 1786 if(a<0x20000) return *(u16 *)(Pico.rom+(a&~1)); // Bios\r
1787 if((a&0xfc0000)==0x200000) { // word RAM\r
1788 if(!(Pico_mcd->s68k_regs[3]&4)) // 2M?\r
1789 return *(u16 *)(Pico_mcd->word_ram2M+(a&0x3fffe));\r
1790 else if (a < 0x220000) {\r
1791 int bank = Pico_mcd->s68k_regs[3]&1;\r
1792 return *(u16 *)(Pico_mcd->word_ram1M[bank]+(a&0x1fffe));\r
1793 }\r
1794 }\r
ca61ee42 1795 elprintf(EL_ANOMALY, "m68k_read_pcrelative_CD16 FIXME: can't handle %06x", a);\r
cc68a136 1796 }\r
b837b69b 1797 return 0;\r
cc68a136 1798}\r
9037e45d 1799static unsigned int m68k_read_pcrelative_CD32(unsigned int a)\r
b5e5172d 1800{\r
fa1e5e29 1801 u16 *pm;\r
cc68a136 1802 a&=0xffffff;\r
3aa1e148 1803 if(m68ki_cpu_p == &PicoCpuMS68k) {\r
cc68a136 1804 if (a < 0x80000) { u16 *pm=(u16 *)(Pico_mcd->prg_ram+(a&~1)); return (pm[0]<<16)|pm[1]; } // PRG Ram\r
fa1e5e29 1805 if ((a&0xfc0000)==0x080000 && !(Pico_mcd->s68k_regs[3]&4)) // word RAM (2M area: 080000-0bffff)\r
1806 { pm=(u16 *)(Pico_mcd->word_ram2M+(a&0x3fffe)); return (pm[0]<<16)|pm[1]; }\r
1807 if ((a&0xfe0000)==0x0c0000 && (Pico_mcd->s68k_regs[3]&4)) { // word RAM (1M area: 0c0000-0dffff)\r
3aa1e148 1808 int bank = (Pico_mcd->s68k_regs[3]&1)^1;\r
fa1e5e29 1809 pm=(u16 *)(Pico_mcd->word_ram1M[bank]+(a&0x1fffe));\r
1810 return (pm[0]<<16)|pm[1];\r
1811 }\r
ca61ee42 1812 elprintf(EL_ANOMALY, "s68k_read_pcrelative_CD32 FIXME: can't handle %06x", a);\r
cc68a136 1813 } else {\r
cc68a136 1814 if((a&0xe00000)==0xe00000) { u16 *pm=(u16 *)(Pico.ram+(a&0xfffe)); return (pm[0]<<16)|pm[1]; } // Ram\r
fa1e5e29 1815 if(a<0x20000) { u16 *pm=(u16 *)(Pico.rom+(a&~1)); return (pm[0]<<16)|pm[1]; }\r
1816 if((a&0xfc0000)==0x200000) { // word RAM\r
1817 if(!(Pico_mcd->s68k_regs[3]&4)) // 2M?\r
1818 { pm=(u16 *)(Pico_mcd->word_ram2M+(a&0x3fffe)); return (pm[0]<<16)|pm[1]; }\r
1819 else if (a < 0x220000) {\r
1820 int bank = Pico_mcd->s68k_regs[3]&1;\r
1821 pm=(u16 *)(Pico_mcd->word_ram1M[bank]+(a&0x1fffe));\r
1822 return (pm[0]<<16)|pm[1];\r
1823 }\r
1824 }\r
ca61ee42 1825 elprintf(EL_ANOMALY, "m68k_read_pcrelative_CD32 FIXME: can't handle %06x", a);\r
cc68a136 1826 }\r
b837b69b 1827 return 0;\r
cc68a136 1828}\r
9037e45d 1829\r
1830extern unsigned int (*pm68k_read_memory_8) (unsigned int address);\r
1831extern unsigned int (*pm68k_read_memory_16)(unsigned int address);\r
1832extern unsigned int (*pm68k_read_memory_32)(unsigned int address);\r
1833extern void (*pm68k_write_memory_8) (unsigned int address, unsigned char value);\r
1834extern void (*pm68k_write_memory_16)(unsigned int address, unsigned short value);\r
1835extern void (*pm68k_write_memory_32)(unsigned int address, unsigned int value);\r
1836extern unsigned int (*pm68k_read_memory_pcr_8) (unsigned int address);\r
1837extern unsigned int (*pm68k_read_memory_pcr_16)(unsigned int address);\r
1838extern unsigned int (*pm68k_read_memory_pcr_32)(unsigned int address);\r
1839\r
1840static void m68k_mem_setup_cd(void)\r
1841{\r
1842 pm68k_read_memory_8 = PicoReadCD8w;\r
1843 pm68k_read_memory_16 = PicoReadCD16w;\r
1844 pm68k_read_memory_32 = PicoReadCD32w;\r
1845 pm68k_write_memory_8 = PicoWriteCD8w;\r
1846 pm68k_write_memory_16 = PicoWriteCD16w;\r
1847 pm68k_write_memory_32 = PicoWriteCD32w;\r
1848 pm68k_read_memory_pcr_8 = m68k_read_pcrelative_CD8;\r
1849 pm68k_read_memory_pcr_16 = m68k_read_pcrelative_CD16;\r
1850 pm68k_read_memory_pcr_32 = m68k_read_pcrelative_CD32;\r
1851}\r
cc68a136 1852#endif // EMU_M68K\r
1853\r
fast MegaDrive/MegaCD/32X emulator