e898de13 |
1 | /* |
2 | * vim:shiftwidth=2:expandtab |
3 | */ |
679af8a3 |
4 | #include <stdio.h> |
5 | #include <stdlib.h> |
6 | #include <assert.h> |
41397701 |
7 | |
f4bb5d6b |
8 | #include "../../pico/pico_int.h" |
679af8a3 |
9 | #include "sh2.h" |
10 | #include "compiler.h" |
11 | #include "../drc/cmn.h" |
12 | |
e898de13 |
13 | #ifndef DRC_DEBUG |
14 | #define DRC_DEBUG 0 |
15 | #endif |
16 | |
553c3eaa |
17 | #if DRC_DEBUG |
f4bb5d6b |
18 | #define dbg(l,...) { \ |
19 | if ((l) & DRC_DEBUG) \ |
20 | elprintf(EL_STATUS, ##__VA_ARGS__); \ |
21 | } |
22 | |
e898de13 |
23 | #include "mame/sh2dasm.h" |
24 | #include <platform/linux/host_dasm.h> |
25 | static int insns_compiled, hash_collisions, host_insn_count; |
553c3eaa |
26 | #define COUNT_OP \ |
27 | host_insn_count++ |
28 | #else // !DRC_DEBUG |
29 | #define COUNT_OP |
30 | #define dbg(...) |
e898de13 |
31 | #endif |
553c3eaa |
32 | |
e898de13 |
33 | #if (DRC_DEBUG & 2) |
f4bb5d6b |
34 | static u8 *tcache_dsm_ptrs[3]; |
e898de13 |
35 | static char sh2dasm_buff[64]; |
f4bb5d6b |
36 | #define do_host_disasm(tcid) \ |
37 | host_dasm(tcache_dsm_ptrs[tcid], tcache_ptr - tcache_dsm_ptrs[tcid]); \ |
38 | tcache_dsm_ptrs[tcid] = tcache_ptr |
39 | #else |
40 | #define do_host_disasm(x) |
e898de13 |
41 | #endif |
42 | |
679af8a3 |
43 | #define BLOCK_CYCLE_LIMIT 100 |
f4bb5d6b |
44 | #define MAX_BLOCK_SIZE (BLOCK_CYCLE_LIMIT * 6 * 6) |
45 | |
46 | // we have 3 translation cache buffers, split from one drc/cmn buffer. |
47 | // BIOS shares tcache with data array because it's only used for init |
48 | // and can be discarded early |
49 | static const int tcache_sizes[3] = { |
50 | DRC_TCACHE_SIZE * 6 / 8, // ROM, DRAM |
51 | DRC_TCACHE_SIZE / 8, // BIOS, data array in master sh2 |
52 | DRC_TCACHE_SIZE / 8, // ... slave |
53 | }; |
679af8a3 |
54 | |
f4bb5d6b |
55 | static u8 *tcache_bases[3]; |
56 | static u8 *tcache_ptrs[3]; |
57 | |
58 | // ptr for code emiters |
59 | static u8 *tcache_ptr; |
e898de13 |
60 | |
65c75cb0 |
61 | #ifdef ARM |
62 | #include "../drc/emit_arm.c" |
63 | |
64 | static const int reg_map_g2h[] = { |
65 | -1, -1, -1, -1, |
66 | -1, -1, -1, -1, |
67 | -1, -1, -1, -1, |
68 | -1, -1, -1, -1, |
69 | -1, -1, -1, -1, |
70 | -1, -1, -1, -1, |
71 | }; |
72 | |
73 | #else |
e898de13 |
74 | #include "../drc/emit_x86.c" |
75 | |
65c75cb0 |
76 | static const int reg_map_g2h[] = { |
77 | -1, -1, -1, -1, |
78 | -1, -1, -1, -1, |
79 | -1, -1, -1, -1, |
80 | -1, -1, -1, -1, |
81 | -1, -1, -1, -1, |
82 | -1, -1, -1, -1, |
83 | }; |
84 | |
85 | #endif |
86 | |
679af8a3 |
87 | typedef enum { |
88 | SHR_R0 = 0, SHR_R15 = 15, |
89 | SHR_PC, SHR_PPC, SHR_PR, SHR_SR, |
90 | SHR_GBR, SHR_VBR, SHR_MACH, SHR_MACL, |
91 | } sh2_reg_e; |
92 | |
93 | typedef struct block_desc_ { |
94 | u32 addr; // SH2 PC address |
f4bb5d6b |
95 | u32 end_addr; // TODO rm? |
679af8a3 |
96 | void *tcache_ptr; // translated block for above PC |
f4bb5d6b |
97 | struct block_desc_ *next; // next block with the same PC hash |
98 | #if (DRC_DEBUG & 1) |
99 | int refcount; |
100 | #endif |
679af8a3 |
101 | } block_desc; |
102 | |
f4bb5d6b |
103 | static const int block_max_counts[3] = { |
104 | 4*1024, |
105 | 256, |
106 | 256, |
107 | }; |
108 | static block_desc *block_tables[3]; |
109 | static int block_counts[3]; |
679af8a3 |
110 | |
f4bb5d6b |
111 | // ROM hash table |
679af8a3 |
112 | #define MAX_HASH_ENTRIES 1024 |
113 | #define HASH_MASK (MAX_HASH_ENTRIES - 1) |
f4bb5d6b |
114 | static void **hash_table; |
679af8a3 |
115 | |
679af8a3 |
116 | extern void sh2_drc_entry(SH2 *sh2, void *block); |
117 | extern void sh2_drc_exit(void); |
118 | |
119 | // tmp |
553c3eaa |
120 | extern void REGPARM(2) sh2_do_op(SH2 *sh2, int opcode); |
121 | static void REGPARM(1) sh2_test_irq(SH2 *sh2); |
679af8a3 |
122 | |
f4bb5d6b |
123 | static void flush_tcache(int tcid) |
124 | { |
553c3eaa |
125 | dbg(1, "tcache #%d flush! (%d/%d, bds %d/%d)", tcid, |
f4bb5d6b |
126 | tcache_ptrs[tcid] - tcache_bases[tcid], tcache_sizes[tcid], |
127 | block_counts[tcid], block_max_counts[tcid]); |
128 | |
129 | block_counts[tcid] = 0; |
130 | tcache_ptrs[tcid] = tcache_bases[tcid]; |
131 | if (tcid == 0) { // ROM, RAM |
132 | memset(hash_table, 0, sizeof(hash_table[0]) * MAX_HASH_ENTRIES); |
133 | memset(Pico32xMem->drcblk_ram, 0, sizeof(Pico32xMem->drcblk_ram)); |
134 | } |
135 | else |
136 | memset(Pico32xMem->drcblk_da[tcid - 1], 0, sizeof(Pico32xMem->drcblk_da[0])); |
137 | #if (DRC_DEBUG & 2) |
138 | tcache_dsm_ptrs[tcid] = tcache_bases[tcid]; |
139 | #endif |
140 | } |
141 | |
679af8a3 |
142 | static void *dr_find_block(block_desc *tab, u32 addr) |
143 | { |
144 | for (tab = tab->next; tab != NULL; tab = tab->next) |
145 | if (tab->addr == addr) |
146 | break; |
147 | |
148 | if (tab != NULL) |
149 | return tab->tcache_ptr; |
150 | |
151 | printf("block miss for %08x\n", addr); |
152 | return NULL; |
153 | } |
154 | |
f4bb5d6b |
155 | static block_desc *dr_add_block(u32 addr, int tcache_id, int *blk_id) |
679af8a3 |
156 | { |
f4bb5d6b |
157 | int *bcount = &block_counts[tcache_id]; |
679af8a3 |
158 | block_desc *bd; |
159 | |
f4bb5d6b |
160 | if (*bcount >= block_max_counts[tcache_id]) |
161 | return NULL; |
679af8a3 |
162 | |
f4bb5d6b |
163 | bd = &block_tables[tcache_id][*bcount]; |
679af8a3 |
164 | bd->addr = addr; |
165 | bd->tcache_ptr = tcache_ptr; |
f4bb5d6b |
166 | *blk_id = *bcount; |
167 | (*bcount)++; |
679af8a3 |
168 | |
169 | return bd; |
170 | } |
171 | |
172 | #define HASH_FUNC(hash_tab, addr) \ |
173 | ((block_desc **)(hash_tab))[(addr) & HASH_MASK] |
174 | |
175 | // --------------------------------------------------------------- |
176 | |
177 | static void emit_move_r_imm32(sh2_reg_e dst, u32 imm) |
41397701 |
178 | { |
679af8a3 |
179 | int host_dst = reg_map_g2h[dst]; |
180 | int tmp = 0; |
181 | |
182 | if (host_dst != -1) |
183 | tmp = host_dst; |
184 | emith_move_r_imm(tmp, imm); |
185 | if (host_dst == -1) |
186 | emith_ctx_write(tmp, dst * 4); |
187 | } |
188 | |
189 | static void emit_move_r_r(sh2_reg_e dst, sh2_reg_e src) |
190 | { |
191 | int host_dst = reg_map_g2h[dst], host_src = reg_map_g2h[src]; |
192 | int tmp = 0; |
193 | |
194 | if (host_dst != -1 && host_src != -1) { |
195 | emith_move_r_r(host_dst, host_src); |
196 | return; |
197 | } |
198 | |
199 | if (host_src != -1) |
200 | tmp = host_src; |
201 | if (host_dst != -1) |
202 | tmp = host_dst; |
203 | |
204 | if (host_src == -1) |
205 | emith_ctx_read(tmp, src * 4); |
206 | if (host_dst == -1) |
207 | emith_ctx_write(tmp, dst * 4); |
208 | } |
209 | |
210 | static void emit_braf(sh2_reg_e reg, u32 pc) |
211 | { |
212 | int host_reg = reg_map_g2h[reg]; |
213 | if (host_reg == -1) { |
214 | emith_ctx_read(0, reg * 4); |
215 | } else |
216 | emith_move_r_r(0, host_reg); |
217 | emith_add_r_imm(0, pc); |
218 | |
e898de13 |
219 | emith_ctx_write(0, SHR_PPC * 4); |
679af8a3 |
220 | } |
221 | |
679af8a3 |
222 | /* |
223 | static int sh2_translate_op4(int op) |
224 | { |
225 | switch (op & 0x000f) |
226 | { |
227 | case 0x0b: |
228 | default: |
229 | emith_pass_arg(2, sh2, op); |
230 | emith_call(sh2_do_op); |
231 | break; |
232 | } |
233 | |
234 | return 0; |
235 | } |
236 | */ |
237 | |
e898de13 |
238 | #define DELAYED_OP \ |
239 | delayed_op = 2 |
240 | |
241 | #define CHECK_UNHANDLED_BITS(mask) { \ |
242 | if ((op & (mask)) != 0) \ |
243 | goto default_; \ |
244 | } |
245 | |
679af8a3 |
246 | static void *sh2_translate(SH2 *sh2, block_desc *other_block) |
247 | { |
f4bb5d6b |
248 | void *block_entry; |
679af8a3 |
249 | block_desc *this_block; |
41397701 |
250 | unsigned int pc = sh2->pc; |
e898de13 |
251 | int op, delayed_op = 0, test_irq = 0; |
f4bb5d6b |
252 | int tcache_id = 0, blkid = 0; |
679af8a3 |
253 | int cycles = 0; |
e898de13 |
254 | u32 tmp, tmp2; |
679af8a3 |
255 | |
f4bb5d6b |
256 | // validate PC |
257 | tmp = sh2->pc >> 29; |
258 | if ((tmp != 0 && tmp != 1 && tmp != 6) || sh2->pc == 0) { |
259 | printf("invalid PC, aborting: %08x\n", sh2->pc); |
260 | // FIXME: be less destructive |
261 | exit(1); |
262 | } |
263 | |
264 | if ((sh2->pc & 0xe0000000) == 0xc0000000 || (sh2->pc & ~0xfff) == 0) { |
265 | // data_array, BIOS have separate tcache (shared) |
266 | tcache_id = 1 + sh2->is_slave; |
267 | } |
268 | |
269 | tcache_ptr = tcache_ptrs[tcache_id]; |
270 | this_block = dr_add_block(pc, tcache_id, &blkid); |
271 | |
272 | tmp = tcache_ptr - tcache_bases[tcache_id]; |
273 | if (tmp > tcache_sizes[tcache_id] - MAX_BLOCK_SIZE || this_block == NULL) { |
274 | flush_tcache(tcache_id); |
275 | tcache_ptr = tcache_ptrs[tcache_id]; |
276 | other_block = NULL; // also gone too due to flush |
277 | this_block = dr_add_block(pc, tcache_id, &blkid); |
278 | } |
e898de13 |
279 | |
f4bb5d6b |
280 | this_block->next = other_block; |
281 | if ((sh2->pc & 0xc6000000) == 0x02000000) // ROM |
282 | HASH_FUNC(hash_table, pc) = this_block; |
679af8a3 |
283 | |
f4bb5d6b |
284 | block_entry = tcache_ptr; |
e898de13 |
285 | #if (DRC_DEBUG & 1) |
f4bb5d6b |
286 | printf("== %csh2 block #%d,%d %08x -> %p\n", sh2->is_slave ? 's' : 'm', |
287 | tcache_id, block_counts[tcache_id], pc, block_entry); |
e898de13 |
288 | if (other_block != NULL) { |
289 | printf(" hash collision with %08x\n", other_block->addr); |
290 | hash_collisions++; |
291 | } |
679af8a3 |
292 | #endif |
293 | |
e898de13 |
294 | while (cycles < BLOCK_CYCLE_LIMIT || delayed_op) |
679af8a3 |
295 | { |
e898de13 |
296 | if (delayed_op > 0) |
297 | delayed_op--; |
298 | |
2b2b46b0 |
299 | op = p32x_sh2_read16(pc, sh2); |
e898de13 |
300 | |
301 | #if (DRC_DEBUG & 3) |
302 | insns_compiled++; |
303 | #if (DRC_DEBUG & 2) |
304 | DasmSH2(sh2dasm_buff, pc, op); |
305 | printf("%08x %04x %s\n", pc, op, sh2dasm_buff); |
306 | #endif |
679af8a3 |
307 | #endif |
679af8a3 |
308 | |
309 | pc += 2; |
310 | cycles++; |
311 | |
312 | switch ((op >> 12) & 0x0f) |
313 | { |
314 | case 0x00: |
e898de13 |
315 | switch (op & 0x0f) { |
316 | case 0x03: |
317 | CHECK_UNHANDLED_BITS(0xd0); |
318 | // BRAF Rm 0000mmmm00100011 |
319 | // BSRF Rm 0000mmmm00000011 |
679af8a3 |
320 | DELAYED_OP; |
e898de13 |
321 | if (!(op & 0x20)) |
322 | emit_move_r_imm32(SHR_PR, pc + 2); |
323 | emit_braf((op >> 8) & 0x0f, pc + 2); |
679af8a3 |
324 | cycles++; |
e898de13 |
325 | goto end_op; |
326 | case 0x09: |
327 | CHECK_UNHANDLED_BITS(0xf0); |
328 | // NOP 0000000000001001 |
329 | goto end_op; |
330 | case 0x0b: |
331 | CHECK_UNHANDLED_BITS(0xd0); |
679af8a3 |
332 | DELAYED_OP; |
e898de13 |
333 | if (!(op & 0x20)) { |
334 | // RTS 0000000000001011 |
335 | emit_move_r_r(SHR_PPC, SHR_PR); |
336 | cycles++; |
337 | } else { |
338 | // RTE 0000000000101011 |
339 | //emit_move_r_r(SHR_PC, SHR_PR); |
340 | emit_move_r_imm32(SHR_PC, pc - 2); |
f4bb5d6b |
341 | emith_pass_arg_r(0, CONTEXT_REG); |
342 | emith_pass_arg_imm(1, op); |
e898de13 |
343 | emith_call(sh2_do_op); |
344 | emit_move_r_r(SHR_PPC, SHR_PC); |
345 | test_irq = 1; |
346 | cycles += 3; |
347 | } |
348 | goto end_op; |
679af8a3 |
349 | } |
350 | goto default_; |
351 | |
352 | case 0x04: |
e898de13 |
353 | switch (op & 0x0f) { |
354 | case 0x07: |
355 | if ((op & 0xf0) != 0) |
356 | goto default_; |
357 | // LDC.L @Rm+,SR 0100mmmm00000111 |
358 | test_irq = 1; |
359 | goto default_; |
360 | case 0x0b: |
361 | if ((op & 0xd0) != 0) |
362 | goto default_; |
363 | // JMP @Rm 0100mmmm00101011 |
364 | // JSR @Rm 0100mmmm00001011 |
679af8a3 |
365 | DELAYED_OP; |
e898de13 |
366 | if (!(op & 0x20)) |
367 | emit_move_r_imm32(SHR_PR, pc + 2); |
368 | emit_move_r_r(SHR_PPC, (op >> 8) & 0x0f); |
679af8a3 |
369 | cycles++; |
e898de13 |
370 | goto end_op; |
371 | case 0x0e: |
372 | if ((op & 0xf0) != 0) |
373 | goto default_; |
374 | // LDC Rm,SR 0100mmmm00001110 |
375 | test_irq = 1; |
376 | goto default_; |
679af8a3 |
377 | } |
378 | goto default_; |
379 | |
e898de13 |
380 | case 0x08: |
679af8a3 |
381 | switch (op & 0x0f00) { |
382 | // BT/S label 10001101dddddddd |
383 | case 0x0d00: |
384 | // BF/S label 10001111dddddddd |
385 | case 0x0f00: |
386 | DELAYED_OP; |
387 | cycles--; |
679af8a3 |
388 | // fallthrough |
389 | // BT label 10001001dddddddd |
390 | case 0x0900: |
391 | // BF label 10001011dddddddd |
392 | case 0x0b00: |
679af8a3 |
393 | tmp = ((signed int)(op << 24) >> 23); |
e898de13 |
394 | tmp2 = delayed_op ? SHR_PPC : SHR_PC; |
395 | emit_move_r_imm32(tmp2, pc + (delayed_op ? 2 : 0)); |
396 | emith_test_t(); |
65c75cb0 |
397 | EMITH_CONDITIONAL(emit_move_r_imm32(tmp2, pc + tmp + 2), (op & 0x0200) ? 1 : 0); |
e898de13 |
398 | cycles += 2; |
399 | if (!delayed_op) |
400 | goto end_block; |
401 | goto end_op; |
679af8a3 |
402 | } |
403 | goto default_; |
679af8a3 |
404 | |
405 | case 0x0a: |
406 | // BRA label 1010dddddddddddd |
407 | DELAYED_OP; |
408 | do_bra: |
409 | tmp = ((signed int)(op << 20) >> 19); |
e898de13 |
410 | emit_move_r_imm32(SHR_PPC, pc + tmp + 2); |
679af8a3 |
411 | cycles++; |
e898de13 |
412 | break; |
679af8a3 |
413 | |
414 | case 0x0b: |
415 | // BSR label 1011dddddddddddd |
416 | DELAYED_OP; |
e898de13 |
417 | emit_move_r_imm32(SHR_PR, pc + 2); |
679af8a3 |
418 | goto do_bra; |
419 | |
420 | default: |
421 | default_: |
422 | emit_move_r_imm32(SHR_PC, pc - 2); |
f4bb5d6b |
423 | emith_pass_arg_r(0, CONTEXT_REG); |
424 | emith_pass_arg_imm(1, op); |
679af8a3 |
425 | emith_call(sh2_do_op); |
426 | break; |
427 | } |
428 | |
e898de13 |
429 | end_op: |
6add7875 |
430 | if (delayed_op == 1) |
e898de13 |
431 | emit_move_r_r(SHR_PC, SHR_PPC); |
6add7875 |
432 | |
e898de13 |
433 | if (test_irq && delayed_op != 2) { |
f4bb5d6b |
434 | emith_pass_arg_r(0, CONTEXT_REG); |
e898de13 |
435 | emith_call(sh2_test_irq); |
436 | break; |
437 | } |
6add7875 |
438 | if (delayed_op == 1) |
439 | break; |
e898de13 |
440 | |
f4bb5d6b |
441 | do_host_disasm(tcache_id); |
679af8a3 |
442 | } |
443 | |
444 | end_block: |
f4bb5d6b |
445 | this_block->end_addr = pc; |
446 | |
447 | // mark memory blocks as containing compiled code |
448 | if ((sh2->pc & 0xe0000000) == 0xc0000000 || (sh2->pc & ~0xfff) == 0) { |
449 | // data array, BIOS |
450 | u16 *drcblk = Pico32xMem->drcblk_da[sh2->is_slave]; |
451 | tmp = (this_block->addr & 0xfff) >> SH2_DRCBLK_DA_SHIFT; |
452 | tmp2 = (this_block->end_addr & 0xfff) >> SH2_DRCBLK_DA_SHIFT; |
453 | Pico32xMem->drcblk_da[sh2->is_slave][tmp] = (blkid << 1) | 1; |
454 | for (++tmp; tmp < tmp2; tmp++) { |
455 | if (drcblk[tmp]) |
456 | break; // dont overwrite overlay block |
457 | drcblk[tmp] = blkid << 1; |
458 | } |
459 | } |
460 | else if ((this_block->addr & 0xc7fc0000) == 0x06000000) { // DRAM |
461 | tmp = (this_block->addr & 0x3ffff) >> SH2_DRCBLK_RAM_SHIFT; |
462 | tmp2 = (this_block->end_addr & 0x3ffff) >> SH2_DRCBLK_RAM_SHIFT; |
463 | Pico32xMem->drcblk_ram[tmp] = (blkid << 1) | 1; |
464 | for (++tmp; tmp < tmp2; tmp++) { |
465 | if (Pico32xMem->drcblk_ram[tmp]) |
466 | break; |
467 | Pico32xMem->drcblk_ram[tmp] = blkid << 1; |
468 | } |
679af8a3 |
469 | } |
470 | |
471 | if (reg_map_g2h[SHR_SR] == -1) { |
472 | emith_ctx_sub(cycles << 12, SHR_SR * 4); |
473 | } else |
474 | emith_sub_r_imm(reg_map_g2h[SHR_SR], cycles << 12); |
475 | emith_jump(sh2_drc_exit); |
f4bb5d6b |
476 | tcache_ptrs[tcache_id] = tcache_ptr; |
477 | |
553c3eaa |
478 | #ifdef ARM |
479 | cache_flush_d_inval_i(block_entry, tcache_ptr); |
480 | #endif |
481 | |
f4bb5d6b |
482 | do_host_disasm(tcache_id); |
483 | dbg(1, " block #%d,%d tcache %d/%d, insns %d -> %d %.3f", |
484 | tcache_id, block_counts[tcache_id], |
485 | tcache_ptr - tcache_bases[tcache_id], tcache_sizes[tcache_id], |
486 | insns_compiled, host_insn_count, (double)host_insn_count / insns_compiled); |
487 | if ((sh2->pc & 0xc6000000) == 0x02000000) // ROM |
488 | dbg(1, " hash collisions %d/%d", hash_collisions, block_counts[tcache_id]); |
553c3eaa |
489 | #if (DRC_DEBUG & 2) |
490 | fflush(stdout); |
491 | #endif |
492 | |
679af8a3 |
493 | return block_entry; |
f4bb5d6b |
494 | /* |
679af8a3 |
495 | unimplemented: |
496 | // last op |
f4bb5d6b |
497 | do_host_disasm(tcache_id); |
679af8a3 |
498 | exit(1); |
f4bb5d6b |
499 | */ |
679af8a3 |
500 | } |
501 | |
502 | void __attribute__((noinline)) sh2_drc_dispatcher(SH2 *sh2) |
503 | { |
504 | while (((signed int)sh2->sr >> 12) > 0) |
505 | { |
679af8a3 |
506 | void *block = NULL; |
f4bb5d6b |
507 | block_desc *bd = NULL; |
6add7875 |
508 | |
509 | // FIXME: must avoid doing it so often.. |
510 | sh2_test_irq(sh2); |
511 | |
f4bb5d6b |
512 | // we have full block id tables for data_array and RAM |
513 | // BIOS goes to data_array table too |
514 | if ((sh2->pc & 0xff000000) == 0xc0000000 || (sh2->pc & ~0xfff) == 0) { |
515 | int blkid = Pico32xMem->drcblk_da[sh2->is_slave][(sh2->pc & 0xfff) >> SH2_DRCBLK_DA_SHIFT]; |
516 | if (blkid & 1) { |
517 | bd = &block_tables[1 + sh2->is_slave][blkid >> 1]; |
518 | block = bd->tcache_ptr; |
519 | } |
520 | } |
521 | // RAM |
522 | else if ((sh2->pc & 0xc6000000) == 0x06000000) { |
523 | int blkid = Pico32xMem->drcblk_ram[(sh2->pc & 0x3ffff) >> SH2_DRCBLK_RAM_SHIFT]; |
524 | if (blkid & 1) { |
525 | bd = &block_tables[0][blkid >> 1]; |
679af8a3 |
526 | block = bd->tcache_ptr; |
f4bb5d6b |
527 | } |
528 | } |
529 | // ROM |
530 | else if ((sh2->pc & 0xc6000000) == 0x02000000) { |
531 | bd = HASH_FUNC(hash_table, sh2->pc); |
532 | |
533 | if (bd != NULL) { |
534 | if (bd->addr == sh2->pc) |
535 | block = bd->tcache_ptr; |
536 | else |
537 | block = dr_find_block(bd, sh2->pc); |
538 | } |
679af8a3 |
539 | } |
540 | |
541 | if (block == NULL) |
542 | block = sh2_translate(sh2, bd); |
543 | |
f4bb5d6b |
544 | dbg(4, "= %csh2 enter %08x %p, c=%d", sh2->is_slave ? 's' : 'm', |
545 | sh2->pc, block, (signed int)sh2->sr >> 12); |
546 | #if (DRC_DEBUG & 1) |
547 | if (bd != NULL) |
548 | bd->refcount++; |
679af8a3 |
549 | #endif |
550 | sh2_drc_entry(sh2, block); |
551 | } |
552 | } |
553 | |
f4bb5d6b |
554 | static void sh2_smc_rm_block(u16 *drcblk, u16 *p, block_desc *btab, u32 a) |
555 | { |
556 | u16 id = *p >> 1; |
557 | block_desc *bd = btab + id; |
558 | |
559 | dbg(1, " killing block %08x", bd->addr); |
560 | bd->addr = bd->end_addr = 0; |
561 | |
562 | while (p > drcblk && (p[-1] >> 1) == id) |
563 | p--; |
564 | |
565 | // check for possible overlay block |
566 | if (p > 0 && p[-1] != 0) { |
567 | bd = btab + (p[-1] >> 1); |
568 | if (bd->addr <= a && a < bd->end_addr) |
569 | sh2_smc_rm_block(drcblk, p - 1, btab, a); |
570 | } |
571 | |
572 | do { |
573 | *p++ = 0; |
574 | } |
575 | while ((*p >> 1) == id); |
576 | } |
577 | |
578 | void sh2_drc_wcheck_ram(unsigned int a, int val, int cpuid) |
579 | { |
580 | u16 *drcblk = Pico32xMem->drcblk_ram; |
581 | u16 *p = drcblk + ((a & 0x3ffff) >> SH2_DRCBLK_RAM_SHIFT); |
582 | |
583 | dbg(1, "%csh2 smc check @%08x", cpuid ? 's' : 'm', a); |
584 | sh2_smc_rm_block(drcblk, p, block_tables[0], a); |
585 | } |
586 | |
587 | void sh2_drc_wcheck_da(unsigned int a, int val, int cpuid) |
588 | { |
589 | u16 *drcblk = Pico32xMem->drcblk_da[cpuid]; |
590 | u16 *p = drcblk + ((a & 0xfff) >> SH2_DRCBLK_DA_SHIFT); |
591 | |
592 | dbg(1, "%csh2 smc check @%08x", cpuid ? 's' : 'm', a); |
593 | sh2_smc_rm_block(drcblk, p, block_tables[1 + cpuid], a); |
594 | } |
595 | |
679af8a3 |
596 | void sh2_execute(SH2 *sh2, int cycles) |
597 | { |
598 | sh2->cycles_aim += cycles; |
599 | cycles = sh2->cycles_aim - sh2->cycles_done; |
600 | |
601 | // cycles are kept in SHR_SR unused bits (upper 20) |
602 | sh2->sr &= 0x3f3; |
603 | sh2->sr |= cycles << 12; |
604 | sh2_drc_dispatcher(sh2); |
605 | |
606 | sh2->cycles_done += cycles - ((signed int)sh2->sr >> 12); |
607 | } |
608 | |
553c3eaa |
609 | static void REGPARM(1) sh2_test_irq(SH2 *sh2) |
679af8a3 |
610 | { |
6add7875 |
611 | if (sh2->pending_level > ((sh2->sr >> 4) & 0x0f)) |
612 | { |
613 | if (sh2->pending_irl > sh2->pending_int_irq) |
614 | sh2_do_irq(sh2, sh2->pending_irl, 64 + sh2->pending_irl/2); |
615 | else { |
616 | sh2_do_irq(sh2, sh2->pending_int_irq, sh2->pending_int_vector); |
617 | sh2->pending_int_irq = 0; // auto-clear |
618 | sh2->pending_level = sh2->pending_irl; |
619 | } |
620 | } |
679af8a3 |
621 | } |
622 | |
f4bb5d6b |
623 | #if (DRC_DEBUG & 1) |
624 | static void block_stats(void) |
625 | { |
626 | int c, b, i, total = 0; |
627 | |
628 | for (b = 0; b < ARRAY_SIZE(block_tables); b++) |
629 | for (i = 0; i < block_counts[b]; i++) |
630 | if (block_tables[b][i].addr != 0) |
631 | total += block_tables[b][i].refcount; |
632 | |
633 | for (c = 0; c < 10; c++) { |
634 | block_desc *blk, *maxb = NULL; |
635 | int max = 0; |
636 | for (b = 0; b < ARRAY_SIZE(block_tables); b++) { |
637 | for (i = 0; i < block_counts[b]; i++) { |
638 | blk = &block_tables[b][i]; |
639 | if (blk->addr != 0 && blk->refcount > max) { |
640 | max = blk->refcount; |
641 | maxb = blk; |
642 | } |
643 | } |
644 | } |
645 | if (maxb == NULL) |
646 | break; |
647 | printf("%08x %9d %2.3f%%\n", maxb->addr, maxb->refcount, |
648 | (double)maxb->refcount / total * 100.0); |
649 | maxb->refcount = 0; |
650 | } |
553c3eaa |
651 | |
652 | for (b = 0; b < ARRAY_SIZE(block_tables); b++) |
653 | for (i = 0; i < block_counts[b]; i++) |
654 | block_tables[b][i].refcount = 0; |
f4bb5d6b |
655 | } |
553c3eaa |
656 | #else |
657 | #define block_stats() |
f4bb5d6b |
658 | #endif |
659 | |
553c3eaa |
660 | void sh2_drc_flush_all(void) |
661 | { |
662 | block_stats(); |
663 | flush_tcache(0); |
664 | flush_tcache(1); |
665 | flush_tcache(2); |
666 | } |
667 | |
679af8a3 |
668 | int sh2_drc_init(SH2 *sh2) |
669 | { |
f4bb5d6b |
670 | if (block_tables[0] == NULL) { |
671 | int i, cnt; |
7f5a3fc1 |
672 | |
673 | drc_cmn_init(); |
674 | |
f4bb5d6b |
675 | cnt = block_max_counts[0] + block_max_counts[1] + block_max_counts[2]; |
676 | block_tables[0] = calloc(cnt, sizeof(*block_tables[0])); |
677 | if (block_tables[0] == NULL) |
e898de13 |
678 | return -1; |
679 | |
f4bb5d6b |
680 | memset(block_counts, 0, sizeof(block_counts)); |
681 | tcache_bases[0] = tcache_ptrs[0] = tcache; |
682 | |
683 | for (i = 1; i < ARRAY_SIZE(block_tables); i++) { |
684 | block_tables[i] = block_tables[i - 1] + block_max_counts[i - 1]; |
685 | tcache_bases[i] = tcache_ptrs[i] = tcache_bases[i - 1] + tcache_sizes[i - 1]; |
686 | } |
687 | |
553c3eaa |
688 | // tmp |
689 | PicoOpt |= POPT_DIS_VDP_FIFO; |
690 | |
f4bb5d6b |
691 | #if (DRC_DEBUG & 2) |
692 | for (i = 0; i < ARRAY_SIZE(block_tables); i++) |
693 | tcache_dsm_ptrs[i] = tcache_bases[i]; |
694 | #endif |
e898de13 |
695 | #if (DRC_DEBUG & 1) |
696 | hash_collisions = 0; |
697 | #endif |
679af8a3 |
698 | } |
699 | |
f4bb5d6b |
700 | if (hash_table == NULL) { |
701 | hash_table = calloc(sizeof(hash_table[0]), MAX_HASH_ENTRIES); |
702 | if (hash_table == NULL) |
703 | return -1; |
704 | } |
41397701 |
705 | |
679af8a3 |
706 | return 0; |
41397701 |
707 | } |
708 | |
e898de13 |
709 | void sh2_drc_finish(SH2 *sh2) |
710 | { |
f4bb5d6b |
711 | if (block_tables[0] != NULL) { |
f4bb5d6b |
712 | block_stats(); |
f4bb5d6b |
713 | free(block_tables[0]); |
714 | memset(block_tables, 0, sizeof(block_tables)); |
7f5a3fc1 |
715 | |
716 | drc_cmn_cleanup(); |
e898de13 |
717 | } |
718 | |
f4bb5d6b |
719 | if (hash_table != NULL) { |
720 | free(hash_table); |
721 | hash_table = NULL; |
722 | } |
e898de13 |
723 | } |