e898de13 |
1 | /* |
2 | * vim:shiftwidth=2:expandtab |
3 | */ |
f0d7b1fa |
4 | #include <stddef.h> |
679af8a3 |
5 | #include <stdio.h> |
6 | #include <stdlib.h> |
7 | #include <assert.h> |
41397701 |
8 | |
f4bb5d6b |
9 | #include "../../pico/pico_int.h" |
679af8a3 |
10 | #include "sh2.h" |
11 | #include "compiler.h" |
12 | #include "../drc/cmn.h" |
13 | |
e898de13 |
14 | #ifndef DRC_DEBUG |
15 | #define DRC_DEBUG 0 |
16 | #endif |
17 | |
553c3eaa |
18 | #if DRC_DEBUG |
f4bb5d6b |
19 | #define dbg(l,...) { \ |
20 | if ((l) & DRC_DEBUG) \ |
21 | elprintf(EL_STATUS, ##__VA_ARGS__); \ |
22 | } |
23 | |
e898de13 |
24 | #include "mame/sh2dasm.h" |
25 | #include <platform/linux/host_dasm.h> |
26 | static int insns_compiled, hash_collisions, host_insn_count; |
553c3eaa |
27 | #define COUNT_OP \ |
28 | host_insn_count++ |
29 | #else // !DRC_DEBUG |
30 | #define COUNT_OP |
31 | #define dbg(...) |
e898de13 |
32 | #endif |
553c3eaa |
33 | |
e898de13 |
34 | #if (DRC_DEBUG & 2) |
f4bb5d6b |
35 | static u8 *tcache_dsm_ptrs[3]; |
e898de13 |
36 | static char sh2dasm_buff[64]; |
f4bb5d6b |
37 | #define do_host_disasm(tcid) \ |
38 | host_dasm(tcache_dsm_ptrs[tcid], tcache_ptr - tcache_dsm_ptrs[tcid]); \ |
39 | tcache_dsm_ptrs[tcid] = tcache_ptr |
40 | #else |
41 | #define do_host_disasm(x) |
e898de13 |
42 | #endif |
43 | |
679af8a3 |
44 | #define BLOCK_CYCLE_LIMIT 100 |
f4bb5d6b |
45 | #define MAX_BLOCK_SIZE (BLOCK_CYCLE_LIMIT * 6 * 6) |
46 | |
47 | // we have 3 translation cache buffers, split from one drc/cmn buffer. |
48 | // BIOS shares tcache with data array because it's only used for init |
49 | // and can be discarded early |
50 | static const int tcache_sizes[3] = { |
51 | DRC_TCACHE_SIZE * 6 / 8, // ROM, DRAM |
52 | DRC_TCACHE_SIZE / 8, // BIOS, data array in master sh2 |
53 | DRC_TCACHE_SIZE / 8, // ... slave |
54 | }; |
679af8a3 |
55 | |
f4bb5d6b |
56 | static u8 *tcache_bases[3]; |
57 | static u8 *tcache_ptrs[3]; |
58 | |
59 | // ptr for code emiters |
60 | static u8 *tcache_ptr; |
e898de13 |
61 | |
c18edb34 |
62 | // host register tracking |
63 | enum { |
64 | HR_FREE, |
65 | HR_CACHED, // 'val' has sh2_reg_e |
66 | HR_CACHED_DIRTY, |
67 | HR_CONST, // 'val' has constant |
68 | HR_TEMP, // reg used for temp storage |
69 | }; |
70 | |
71 | typedef struct { |
72 | u8 reg; |
73 | u8 type; |
74 | u16 stamp; // kind of a timestamp |
75 | u32 val; |
76 | } temp_reg_t; |
77 | |
80599a42 |
78 | // note: reg_temp[] must have at least the amount of |
3863edbd |
79 | // registers used by handlers in worst case (currently 4) |
65c75cb0 |
80 | #ifdef ARM |
81 | #include "../drc/emit_arm.c" |
82 | |
83 | static const int reg_map_g2h[] = { |
c18edb34 |
84 | -1, -1, -1, -1, |
85 | -1, -1, -1, -1, |
86 | -1, -1, -1, -1, |
87 | -1, -1, -1, -1, |
88 | -1, -1, -1, -1, |
89 | -1, -1, -1, -1, |
90 | }; |
91 | |
92 | static temp_reg_t reg_temp[] = { |
93 | { 0, }, |
94 | { 1, }, |
95 | { 12, }, |
96 | { 14, }, |
97 | { 2, }, |
98 | { 3, }, |
65c75cb0 |
99 | }; |
100 | |
101 | #else |
e898de13 |
102 | #include "../drc/emit_x86.c" |
103 | |
65c75cb0 |
104 | static const int reg_map_g2h[] = { |
c18edb34 |
105 | -1, -1, -1, -1, |
106 | -1, -1, -1, -1, |
107 | -1, -1, -1, -1, |
108 | -1, -1, -1, -1, |
109 | -1, -1, -1, -1, |
110 | -1, -1, -1, -1, |
111 | }; |
112 | |
3863edbd |
113 | // ax, cx, dx are usually temporaries by convention |
c18edb34 |
114 | static temp_reg_t reg_temp[] = { |
115 | { xAX, }, |
3863edbd |
116 | { xBX, }, |
c18edb34 |
117 | { xCX, }, |
118 | { xDX, }, |
65c75cb0 |
119 | }; |
120 | |
121 | #endif |
122 | |
80599a42 |
123 | #define T 0x00000001 |
124 | #define S 0x00000002 |
125 | #define I 0x000000f0 |
126 | #define Q 0x00000100 |
127 | #define M 0x00000200 |
128 | |
f0d7b1fa |
129 | #define Q_SHIFT 8 |
130 | #define M_SHIFT 9 |
131 | |
679af8a3 |
132 | typedef enum { |
52d759c3 |
133 | SHR_R0 = 0, SHR_SP = 15, |
679af8a3 |
134 | SHR_PC, SHR_PPC, SHR_PR, SHR_SR, |
135 | SHR_GBR, SHR_VBR, SHR_MACH, SHR_MACL, |
136 | } sh2_reg_e; |
137 | |
138 | typedef struct block_desc_ { |
139 | u32 addr; // SH2 PC address |
f4bb5d6b |
140 | u32 end_addr; // TODO rm? |
679af8a3 |
141 | void *tcache_ptr; // translated block for above PC |
f4bb5d6b |
142 | struct block_desc_ *next; // next block with the same PC hash |
143 | #if (DRC_DEBUG & 1) |
144 | int refcount; |
145 | #endif |
679af8a3 |
146 | } block_desc; |
147 | |
f4bb5d6b |
148 | static const int block_max_counts[3] = { |
149 | 4*1024, |
150 | 256, |
151 | 256, |
152 | }; |
153 | static block_desc *block_tables[3]; |
154 | static int block_counts[3]; |
679af8a3 |
155 | |
f4bb5d6b |
156 | // ROM hash table |
679af8a3 |
157 | #define MAX_HASH_ENTRIES 1024 |
158 | #define HASH_MASK (MAX_HASH_ENTRIES - 1) |
f4bb5d6b |
159 | static void **hash_table; |
679af8a3 |
160 | |
679af8a3 |
161 | extern void sh2_drc_entry(SH2 *sh2, void *block); |
162 | extern void sh2_drc_exit(void); |
163 | |
164 | // tmp |
553c3eaa |
165 | extern void REGPARM(2) sh2_do_op(SH2 *sh2, int opcode); |
166 | static void REGPARM(1) sh2_test_irq(SH2 *sh2); |
679af8a3 |
167 | |
f4bb5d6b |
168 | static void flush_tcache(int tcid) |
169 | { |
553c3eaa |
170 | dbg(1, "tcache #%d flush! (%d/%d, bds %d/%d)", tcid, |
f4bb5d6b |
171 | tcache_ptrs[tcid] - tcache_bases[tcid], tcache_sizes[tcid], |
172 | block_counts[tcid], block_max_counts[tcid]); |
173 | |
174 | block_counts[tcid] = 0; |
175 | tcache_ptrs[tcid] = tcache_bases[tcid]; |
176 | if (tcid == 0) { // ROM, RAM |
177 | memset(hash_table, 0, sizeof(hash_table[0]) * MAX_HASH_ENTRIES); |
178 | memset(Pico32xMem->drcblk_ram, 0, sizeof(Pico32xMem->drcblk_ram)); |
179 | } |
180 | else |
181 | memset(Pico32xMem->drcblk_da[tcid - 1], 0, sizeof(Pico32xMem->drcblk_da[0])); |
182 | #if (DRC_DEBUG & 2) |
183 | tcache_dsm_ptrs[tcid] = tcache_bases[tcid]; |
184 | #endif |
185 | } |
186 | |
679af8a3 |
187 | static void *dr_find_block(block_desc *tab, u32 addr) |
188 | { |
189 | for (tab = tab->next; tab != NULL; tab = tab->next) |
190 | if (tab->addr == addr) |
191 | break; |
192 | |
193 | if (tab != NULL) |
194 | return tab->tcache_ptr; |
195 | |
196 | printf("block miss for %08x\n", addr); |
197 | return NULL; |
198 | } |
199 | |
f4bb5d6b |
200 | static block_desc *dr_add_block(u32 addr, int tcache_id, int *blk_id) |
679af8a3 |
201 | { |
f4bb5d6b |
202 | int *bcount = &block_counts[tcache_id]; |
679af8a3 |
203 | block_desc *bd; |
204 | |
f4bb5d6b |
205 | if (*bcount >= block_max_counts[tcache_id]) |
206 | return NULL; |
679af8a3 |
207 | |
f4bb5d6b |
208 | bd = &block_tables[tcache_id][*bcount]; |
679af8a3 |
209 | bd->addr = addr; |
210 | bd->tcache_ptr = tcache_ptr; |
f4bb5d6b |
211 | *blk_id = *bcount; |
212 | (*bcount)++; |
679af8a3 |
213 | |
214 | return bd; |
215 | } |
216 | |
217 | #define HASH_FUNC(hash_tab, addr) \ |
218 | ((block_desc **)(hash_tab))[(addr) & HASH_MASK] |
219 | |
220 | // --------------------------------------------------------------- |
221 | |
c18edb34 |
222 | // register chache |
223 | static u16 rcache_counter; |
224 | |
225 | static temp_reg_t *rcache_evict(void) |
41397701 |
226 | { |
c18edb34 |
227 | // evict reg with oldest stamp |
228 | int i, oldest = -1; |
229 | u16 min_stamp = (u16)-1; |
230 | |
231 | for (i = 0; i < ARRAY_SIZE(reg_temp); i++) { |
232 | if (reg_temp[i].type == HR_CACHED || reg_temp[i].type == HR_CACHED_DIRTY) |
233 | if (reg_temp[i].stamp <= min_stamp) { |
234 | min_stamp = reg_temp[i].stamp; |
235 | oldest = i; |
236 | } |
237 | } |
238 | |
239 | if (oldest == -1) { |
80599a42 |
240 | printf("no registers to evict, aborting\n"); |
c18edb34 |
241 | exit(1); |
242 | } |
243 | |
244 | i = oldest; |
245 | if (reg_temp[i].type == HR_CACHED_DIRTY) { |
246 | // writeback |
247 | emith_ctx_write(reg_temp[i].reg, reg_temp[i].val * 4); |
248 | } |
249 | |
250 | return ®_temp[i]; |
679af8a3 |
251 | } |
252 | |
c18edb34 |
253 | typedef enum { |
254 | RC_GR_READ, |
255 | RC_GR_WRITE, |
256 | RC_GR_RMW, |
257 | } rc_gr_mode; |
258 | |
80599a42 |
259 | // note: must not be called when doing conditional code |
c18edb34 |
260 | static int rcache_get_reg(sh2_reg_e r, rc_gr_mode mode) |
679af8a3 |
261 | { |
c18edb34 |
262 | temp_reg_t *tr; |
263 | int i; |
264 | |
265 | // maybe already statically mapped? |
266 | i = reg_map_g2h[r]; |
267 | if (i != -1) |
268 | return i; |
679af8a3 |
269 | |
c18edb34 |
270 | rcache_counter++; |
271 | |
272 | // maybe already cached? |
273 | for (i = ARRAY_SIZE(reg_temp) - 1; i >= 0; i--) { |
274 | if ((reg_temp[i].type == HR_CACHED || reg_temp[i].type == HR_CACHED_DIRTY) && |
275 | reg_temp[i].val == r) |
276 | { |
277 | reg_temp[i].stamp = rcache_counter; |
278 | if (mode != RC_GR_READ) |
279 | reg_temp[i].type = HR_CACHED_DIRTY; |
280 | return reg_temp[i].reg; |
281 | } |
679af8a3 |
282 | } |
283 | |
c18edb34 |
284 | // use any free reg |
285 | for (i = ARRAY_SIZE(reg_temp) - 1; i >= 0; i--) { |
286 | if (reg_temp[i].type == HR_FREE || reg_temp[i].type == HR_CONST) { |
287 | tr = ®_temp[i]; |
288 | goto do_alloc; |
289 | } |
290 | } |
291 | |
292 | tr = rcache_evict(); |
293 | |
294 | do_alloc: |
295 | if (mode != RC_GR_WRITE) |
296 | emith_ctx_read(tr->reg, r * 4); |
679af8a3 |
297 | |
c18edb34 |
298 | tr->type = mode != RC_GR_READ ? HR_CACHED_DIRTY : HR_CACHED; |
299 | tr->val = r; |
300 | tr->stamp = rcache_counter; |
301 | return tr->reg; |
679af8a3 |
302 | } |
303 | |
c18edb34 |
304 | static int rcache_get_tmp(void) |
679af8a3 |
305 | { |
c18edb34 |
306 | temp_reg_t *tr; |
307 | int i; |
308 | |
309 | for (i = 0; i < ARRAY_SIZE(reg_temp); i++) |
310 | if (reg_temp[i].type == HR_FREE || reg_temp[i].type == HR_CONST) { |
311 | tr = ®_temp[i]; |
312 | goto do_alloc; |
313 | } |
314 | |
315 | tr = rcache_evict(); |
316 | |
317 | do_alloc: |
318 | tr->type = HR_TEMP; |
319 | return tr->reg; |
320 | } |
321 | |
80599a42 |
322 | static int rcache_get_arg_id(int arg) |
323 | { |
324 | int i, r = 0; |
325 | host_arg2reg(r, arg); |
326 | |
327 | for (i = 0; i < ARRAY_SIZE(reg_temp); i++) |
328 | if (reg_temp[i].reg == r) |
329 | break; |
330 | |
331 | if (i == ARRAY_SIZE(reg_temp)) |
332 | // let's just say it's untracked arg reg |
333 | return r; |
334 | |
335 | if (reg_temp[i].type == HR_CACHED_DIRTY) { |
336 | // writeback |
337 | emith_ctx_write(reg_temp[i].reg, reg_temp[i].val * 4); |
338 | } |
339 | else if (reg_temp[i].type == HR_TEMP) { |
340 | printf("arg %d reg %d already used, aborting\n", arg, r); |
341 | exit(1); |
342 | } |
343 | |
344 | return i; |
345 | } |
346 | |
347 | // get a reg to be used as function arg |
348 | // it's assumed that regs are cleaned before call |
349 | static int rcache_get_tmp_arg(int arg) |
350 | { |
351 | int id = rcache_get_arg_id(arg); |
352 | reg_temp[id].type = HR_TEMP; |
353 | |
354 | return reg_temp[id].reg; |
355 | } |
356 | |
357 | // same but caches reg. RC_GR_READ only. |
358 | static int rcache_get_reg_arg(int arg, sh2_reg_e r) |
359 | { |
360 | int i, srcr, dstr, dstid; |
361 | |
362 | dstid = rcache_get_arg_id(arg); |
363 | dstr = reg_temp[dstid].reg; |
364 | |
365 | // maybe already statically mapped? |
366 | srcr = reg_map_g2h[r]; |
367 | if (srcr != -1) |
368 | goto do_cache; |
369 | |
370 | // maybe already cached? |
371 | for (i = ARRAY_SIZE(reg_temp) - 1; i >= 0; i--) { |
372 | if ((reg_temp[i].type == HR_CACHED || reg_temp[i].type == HR_CACHED_DIRTY) && |
373 | reg_temp[i].val == r) |
374 | { |
375 | srcr = reg_temp[i].reg; |
376 | goto do_cache; |
377 | } |
378 | } |
379 | |
380 | // must read |
381 | srcr = dstr; |
382 | emith_ctx_read(srcr, r * 4); |
383 | |
384 | do_cache: |
385 | if (srcr != dstr) |
386 | emith_move_r_r(dstr, srcr); |
387 | |
388 | reg_temp[dstid].stamp = ++rcache_counter; |
389 | reg_temp[dstid].type = HR_CACHED; |
390 | reg_temp[dstid].val = r; |
391 | return dstr; |
392 | } |
393 | |
c18edb34 |
394 | static void rcache_free_tmp(int hr) |
395 | { |
396 | int i; |
397 | for (i = 0; i < ARRAY_SIZE(reg_temp); i++) |
398 | if (reg_temp[i].reg == hr) |
399 | break; |
400 | |
80599a42 |
401 | if (i == ARRAY_SIZE(reg_temp) || reg_temp[i].type != HR_TEMP) { |
c18edb34 |
402 | printf("rcache_free_tmp fail: #%i hr %d, type %d\n", i, hr, reg_temp[i].type); |
80599a42 |
403 | return; |
404 | } |
405 | |
406 | reg_temp[i].type = HR_FREE; |
c18edb34 |
407 | } |
408 | |
80599a42 |
409 | static void rcache_clean(void) |
c18edb34 |
410 | { |
411 | int i; |
80599a42 |
412 | for (i = 0; i < ARRAY_SIZE(reg_temp); i++) |
c18edb34 |
413 | if (reg_temp[i].type == HR_CACHED_DIRTY) { |
414 | // writeback |
415 | emith_ctx_write(reg_temp[i].reg, reg_temp[i].val * 4); |
80599a42 |
416 | reg_temp[i].type = HR_CACHED; |
c18edb34 |
417 | } |
80599a42 |
418 | } |
419 | |
420 | static void rcache_invalidate(void) |
421 | { |
422 | int i; |
423 | for (i = 0; i < ARRAY_SIZE(reg_temp); i++) |
c18edb34 |
424 | reg_temp[i].type = HR_FREE; |
c18edb34 |
425 | rcache_counter = 0; |
426 | } |
427 | |
80599a42 |
428 | static void rcache_flush(void) |
429 | { |
430 | rcache_clean(); |
431 | rcache_invalidate(); |
432 | } |
433 | |
c18edb34 |
434 | // --------------------------------------------------------------- |
435 | |
436 | static void emit_move_r_imm32(sh2_reg_e dst, u32 imm) |
437 | { |
52d759c3 |
438 | // TODO: propagate this constant |
c18edb34 |
439 | int hr = rcache_get_reg(dst, RC_GR_WRITE); |
440 | emith_move_r_imm(hr, imm); |
441 | } |
442 | |
443 | static void emit_move_r_r(sh2_reg_e dst, sh2_reg_e src) |
444 | { |
445 | int hr_d = rcache_get_reg(dst, RC_GR_WRITE); |
446 | int hr_s = rcache_get_reg(src, RC_GR_READ); |
447 | |
448 | emith_move_r_r(hr_d, hr_s); |
679af8a3 |
449 | } |
450 | |
52d759c3 |
451 | // T must be clear, and comparison done just before this |
452 | static void emit_or_t_if_eq(int srr) |
453 | { |
454 | EMITH_SJMP_START(DCOND_NE); |
455 | emith_or_r_imm_c(DCOND_EQ, srr, T); |
456 | EMITH_SJMP_END(DCOND_NE); |
457 | } |
458 | |
80599a42 |
459 | // arguments must be ready |
460 | // reg cache must be clean before call |
461 | static int emit_memhandler_read(int size) |
679af8a3 |
462 | { |
80599a42 |
463 | int ctxr; |
464 | host_arg2reg(ctxr, 1); |
465 | emith_move_r_r(ctxr, CONTEXT_REG); |
466 | switch (size) { |
467 | case 0: // 8 |
468 | emith_call(p32x_sh2_read8); |
469 | break; |
470 | case 1: // 16 |
471 | emith_call(p32x_sh2_read16); |
472 | break; |
473 | case 2: // 32 |
474 | emith_call(p32x_sh2_read32); |
679af8a3 |
475 | break; |
476 | } |
80599a42 |
477 | rcache_invalidate(); |
478 | // assuming arg0 and retval reg matches |
479 | return rcache_get_tmp_arg(0); |
480 | } |
679af8a3 |
481 | |
80599a42 |
482 | static void emit_memhandler_write(int size) |
483 | { |
484 | int ctxr; |
485 | host_arg2reg(ctxr, 2); |
486 | emith_move_r_r(ctxr, CONTEXT_REG); |
487 | switch (size) { |
488 | case 0: // 8 |
489 | emith_call(p32x_sh2_write8); |
490 | break; |
491 | case 1: // 16 |
492 | emith_call(p32x_sh2_write16); |
493 | break; |
494 | case 2: // 32 |
495 | emith_call(p32x_sh2_write32); |
496 | break; |
497 | } |
498 | rcache_invalidate(); |
679af8a3 |
499 | } |
80599a42 |
500 | |
52d759c3 |
501 | // @(Rx,Ry) |
502 | static int emit_indirect_indexed_read(int rx, int ry, int size) |
503 | { |
504 | int a0, t; |
505 | rcache_clean(); |
506 | a0 = rcache_get_reg_arg(0, rx); |
507 | t = rcache_get_reg(ry, RC_GR_READ); |
508 | emith_add_r_r(a0, t); |
509 | return emit_memhandler_read(size); |
510 | } |
511 | |
512 | // Rwr -> @(Rx,Ry) |
513 | static void emit_indirect_indexed_write(int rx, int ry, int wr, int size) |
514 | { |
515 | int a0, t; |
516 | rcache_clean(); |
517 | rcache_get_reg_arg(1, wr); |
518 | a0 = rcache_get_reg_arg(0, rx); |
519 | t = rcache_get_reg(ry, RC_GR_READ); |
520 | emith_add_r_r(a0, t); |
521 | emit_memhandler_write(size); |
522 | } |
523 | |
f0d7b1fa |
524 | // read @Rn, @rm |
525 | static void emit_indirect_read_double(u32 *rnr, u32 *rmr, int rn, int rm, int size) |
526 | { |
527 | int tmp; |
528 | |
529 | rcache_clean(); |
530 | rcache_get_reg_arg(0, rn); |
531 | tmp = emit_memhandler_read(size); |
532 | emith_ctx_write(tmp, offsetof(SH2, drc_tmp)); |
533 | rcache_free_tmp(tmp); |
534 | tmp = rcache_get_reg(rn, RC_GR_RMW); |
535 | emith_add_r_imm(tmp, 1 << size); |
536 | |
537 | rcache_clean(); |
538 | rcache_get_reg_arg(0, rm); |
539 | *rmr = emit_memhandler_read(size); |
540 | *rnr = rcache_get_tmp(); |
541 | emith_ctx_read(*rnr, offsetof(SH2, drc_tmp)); |
542 | tmp = rcache_get_reg(rm, RC_GR_RMW); |
543 | emith_add_r_imm(tmp, 1 << size); |
544 | } |
545 | |
546 | // fixup for saturated MAC, to be called from generated code |
547 | // FIXME: statically alloced regs need to be fixed |
548 | static void sh2_macl_sat_fixup(void) |
549 | { |
550 | if ((signed int)sh2->mach < 0 && sh2->mach < 0xffff8000) |
551 | { |
552 | sh2->mach = 0x00008000; |
553 | sh2->macl = 0x00000000; |
554 | } |
555 | else if ((signed int)sh2->mach > 0 && sh2->mach > 0x00007fff) |
556 | { |
557 | sh2->mach = 0x00007fff; |
558 | sh2->macl = 0xffffffff; |
559 | } |
560 | } |
561 | |
562 | static void sh2_macw_sat_fixup(void) |
563 | { |
564 | signed int t = sh2->mach; |
565 | if (t < -1 || (t == -1 && !(sh2->macl & 0x80000000))) |
566 | { |
567 | sh2->mach = 0xffffffff; // ? |
568 | sh2->macl = 0x80000000; |
569 | } |
570 | else if (t > 0 || (t == 0 && (sh2->macl & 0x80000000))) |
571 | { |
572 | sh2->mach = 0x7fffffff; |
573 | sh2->macl = 0xffffffff; |
574 | } |
575 | } |
679af8a3 |
576 | |
e898de13 |
577 | #define DELAYED_OP \ |
578 | delayed_op = 2 |
579 | |
580 | #define CHECK_UNHANDLED_BITS(mask) { \ |
581 | if ((op & (mask)) != 0) \ |
582 | goto default_; \ |
583 | } |
584 | |
80599a42 |
585 | #define GET_Fx() \ |
586 | ((op >> 4) & 0x0f) |
587 | |
588 | #define GET_Rm GET_Fx |
589 | |
590 | #define GET_Rn() \ |
591 | ((op >> 8) & 0x0f) |
592 | |
ed8cf79b |
593 | #define CHECK_FX_LT(n) \ |
52d759c3 |
594 | if (GET_Fx() >= n) \ |
80599a42 |
595 | goto default_ |
596 | |
679af8a3 |
597 | static void *sh2_translate(SH2 *sh2, block_desc *other_block) |
598 | { |
f4bb5d6b |
599 | void *block_entry; |
679af8a3 |
600 | block_desc *this_block; |
41397701 |
601 | unsigned int pc = sh2->pc; |
e898de13 |
602 | int op, delayed_op = 0, test_irq = 0; |
f4bb5d6b |
603 | int tcache_id = 0, blkid = 0; |
679af8a3 |
604 | int cycles = 0; |
f0d7b1fa |
605 | u32 tmp, tmp2, tmp3, tmp4, sr; |
679af8a3 |
606 | |
f4bb5d6b |
607 | // validate PC |
608 | tmp = sh2->pc >> 29; |
609 | if ((tmp != 0 && tmp != 1 && tmp != 6) || sh2->pc == 0) { |
610 | printf("invalid PC, aborting: %08x\n", sh2->pc); |
611 | // FIXME: be less destructive |
612 | exit(1); |
613 | } |
614 | |
615 | if ((sh2->pc & 0xe0000000) == 0xc0000000 || (sh2->pc & ~0xfff) == 0) { |
616 | // data_array, BIOS have separate tcache (shared) |
617 | tcache_id = 1 + sh2->is_slave; |
618 | } |
619 | |
620 | tcache_ptr = tcache_ptrs[tcache_id]; |
621 | this_block = dr_add_block(pc, tcache_id, &blkid); |
622 | |
623 | tmp = tcache_ptr - tcache_bases[tcache_id]; |
624 | if (tmp > tcache_sizes[tcache_id] - MAX_BLOCK_SIZE || this_block == NULL) { |
625 | flush_tcache(tcache_id); |
626 | tcache_ptr = tcache_ptrs[tcache_id]; |
627 | other_block = NULL; // also gone too due to flush |
628 | this_block = dr_add_block(pc, tcache_id, &blkid); |
629 | } |
e898de13 |
630 | |
f4bb5d6b |
631 | this_block->next = other_block; |
632 | if ((sh2->pc & 0xc6000000) == 0x02000000) // ROM |
633 | HASH_FUNC(hash_table, pc) = this_block; |
679af8a3 |
634 | |
f4bb5d6b |
635 | block_entry = tcache_ptr; |
e898de13 |
636 | #if (DRC_DEBUG & 1) |
f4bb5d6b |
637 | printf("== %csh2 block #%d,%d %08x -> %p\n", sh2->is_slave ? 's' : 'm', |
638 | tcache_id, block_counts[tcache_id], pc, block_entry); |
e898de13 |
639 | if (other_block != NULL) { |
640 | printf(" hash collision with %08x\n", other_block->addr); |
641 | hash_collisions++; |
642 | } |
679af8a3 |
643 | #endif |
644 | |
e898de13 |
645 | while (cycles < BLOCK_CYCLE_LIMIT || delayed_op) |
679af8a3 |
646 | { |
e898de13 |
647 | if (delayed_op > 0) |
648 | delayed_op--; |
649 | |
2b2b46b0 |
650 | op = p32x_sh2_read16(pc, sh2); |
e898de13 |
651 | |
652 | #if (DRC_DEBUG & 3) |
653 | insns_compiled++; |
654 | #if (DRC_DEBUG & 2) |
655 | DasmSH2(sh2dasm_buff, pc, op); |
656 | printf("%08x %04x %s\n", pc, op, sh2dasm_buff); |
657 | #endif |
679af8a3 |
658 | #endif |
679af8a3 |
659 | |
660 | pc += 2; |
661 | cycles++; |
662 | |
663 | switch ((op >> 12) & 0x0f) |
664 | { |
3863edbd |
665 | ///////////////////////////////////////////// |
679af8a3 |
666 | case 0x00: |
80599a42 |
667 | switch (op & 0x0f) |
668 | { |
669 | case 0x02: |
670 | tmp = rcache_get_reg(GET_Rn(), RC_GR_WRITE); |
671 | switch (GET_Fx()) |
672 | { |
673 | case 0: // STC SR,Rn 0000nnnn00000010 |
674 | tmp2 = SHR_SR; |
675 | break; |
676 | case 1: // STC GBR,Rn 0000nnnn00010010 |
677 | tmp2 = SHR_GBR; |
678 | break; |
679 | case 2: // STC VBR,Rn 0000nnnn00100010 |
680 | tmp2 = SHR_VBR; |
681 | break; |
682 | default: |
683 | goto default_; |
684 | } |
ed8cf79b |
685 | tmp3 = rcache_get_reg(tmp2, RC_GR_READ); |
686 | emith_move_r_r(tmp, tmp3); |
687 | if (tmp2 == SHR_SR) |
688 | emith_clear_msb(tmp, tmp, 20); // reserved bits defined by ISA as 0 |
80599a42 |
689 | goto end_op; |
e898de13 |
690 | case 0x03: |
691 | CHECK_UNHANDLED_BITS(0xd0); |
692 | // BRAF Rm 0000mmmm00100011 |
693 | // BSRF Rm 0000mmmm00000011 |
679af8a3 |
694 | DELAYED_OP; |
e898de13 |
695 | if (!(op & 0x20)) |
696 | emit_move_r_imm32(SHR_PR, pc + 2); |
c18edb34 |
697 | tmp = rcache_get_reg(SHR_PPC, RC_GR_WRITE); |
80599a42 |
698 | tmp2 = rcache_get_reg(GET_Rn(), RC_GR_READ); |
c18edb34 |
699 | emith_move_r_r(tmp, tmp2); |
700 | emith_add_r_imm(tmp, pc + 2); |
679af8a3 |
701 | cycles++; |
e898de13 |
702 | goto end_op; |
80599a42 |
703 | case 0x04: // MOV.B Rm,@(R0,Rn) 0000nnnnmmmm0100 |
704 | case 0x05: // MOV.W Rm,@(R0,Rn) 0000nnnnmmmm0101 |
705 | case 0x06: // MOV.L Rm,@(R0,Rn) 0000nnnnmmmm0110 |
52d759c3 |
706 | emit_indirect_indexed_write(SHR_R0, GET_Rn(), GET_Rm(), op & 3); |
80599a42 |
707 | goto end_op; |
708 | case 0x07: |
709 | // MUL.L Rm,Rn 0000nnnnmmmm0111 |
710 | tmp = rcache_get_reg(GET_Rn(), RC_GR_READ); |
711 | tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ); |
712 | tmp3 = rcache_get_reg(SHR_MACL, RC_GR_WRITE); |
713 | emith_mul(tmp3, tmp2, tmp); |
714 | cycles++; |
715 | goto end_op; |
716 | case 0x08: |
717 | CHECK_UNHANDLED_BITS(0xf00); |
718 | switch (GET_Fx()) |
719 | { |
720 | case 0: // CLRT 0000000000001000 |
721 | tmp = rcache_get_reg(SHR_SR, RC_GR_RMW); |
722 | emith_bic_r_imm(tmp, T); |
723 | break; |
724 | case 1: // SETT 0000000000011000 |
725 | tmp = rcache_get_reg(SHR_SR, RC_GR_RMW); |
726 | emith_or_r_imm(tmp, T); |
727 | break; |
728 | case 2: // CLRMAC 0000000000101000 |
729 | tmp = rcache_get_reg(SHR_MACL, RC_GR_WRITE); |
730 | emith_move_r_imm(tmp, 0); |
731 | tmp = rcache_get_reg(SHR_MACH, RC_GR_WRITE); |
732 | emith_move_r_imm(tmp, 0); |
733 | break; |
734 | default: |
735 | goto default_; |
736 | } |
737 | goto end_op; |
e898de13 |
738 | case 0x09: |
80599a42 |
739 | switch (GET_Fx()) |
740 | { |
741 | case 0: // NOP 0000000000001001 |
742 | CHECK_UNHANDLED_BITS(0xf00); |
743 | break; |
744 | case 1: // DIV0U 0000000000011001 |
745 | CHECK_UNHANDLED_BITS(0xf00); |
746 | tmp = rcache_get_reg(SHR_SR, RC_GR_RMW); |
747 | emith_bic_r_imm(tmp, M|Q|T); |
748 | break; |
749 | case 2: // MOVT Rn 0000nnnn00101001 |
750 | tmp = rcache_get_reg(SHR_SR, RC_GR_READ); |
751 | tmp2 = rcache_get_reg(GET_Rn(), RC_GR_WRITE); |
752 | emith_clear_msb(tmp2, tmp, 31); |
753 | break; |
754 | default: |
755 | goto default_; |
756 | } |
757 | goto end_op; |
758 | case 0x0a: |
759 | tmp = rcache_get_reg(GET_Rn(), RC_GR_WRITE); |
760 | switch (GET_Fx()) |
761 | { |
762 | case 0: // STS MACH,Rn 0000nnnn00001010 |
ed8cf79b |
763 | tmp2 = SHR_MACH; |
80599a42 |
764 | break; |
765 | case 1: // STS MACL,Rn 0000nnnn00011010 |
ed8cf79b |
766 | tmp2 = SHR_MACL; |
80599a42 |
767 | break; |
768 | case 2: // STS PR,Rn 0000nnnn00101010 |
ed8cf79b |
769 | tmp2 = SHR_PR; |
80599a42 |
770 | break; |
771 | default: |
772 | goto default_; |
773 | } |
ed8cf79b |
774 | tmp2 = rcache_get_reg(tmp2, RC_GR_READ); |
80599a42 |
775 | emith_move_r_r(tmp, tmp2); |
e898de13 |
776 | goto end_op; |
777 | case 0x0b: |
80599a42 |
778 | CHECK_UNHANDLED_BITS(0xf00); |
779 | switch (GET_Fx()) |
780 | { |
781 | case 0: // RTS 0000000000001011 |
782 | DELAYED_OP; |
e898de13 |
783 | emit_move_r_r(SHR_PPC, SHR_PR); |
784 | cycles++; |
80599a42 |
785 | break; |
786 | case 1: // SLEEP 0000000000011011 |
787 | emit_move_r_imm32(SHR_PC, pc - 2); |
788 | tmp = rcache_get_reg(SHR_SR, RC_GR_RMW); |
789 | emith_clear_msb(tmp, tmp, 20); // clear cycles |
790 | test_irq = 1; |
791 | cycles = 1; |
792 | break; |
793 | case 2: // RTE 0000000000101011 |
52d759c3 |
794 | DELAYED_OP; |
795 | rcache_clean(); |
796 | // pop PC |
797 | rcache_get_reg_arg(0, SHR_SP); |
798 | tmp = emit_memhandler_read(2); |
799 | tmp2 = rcache_get_reg(SHR_PPC, RC_GR_WRITE); |
800 | emith_move_r_r(tmp2, tmp); |
801 | rcache_free_tmp(tmp); |
802 | rcache_clean(); |
803 | // pop SR |
804 | tmp = rcache_get_reg_arg(0, SHR_SP); |
805 | emith_add_r_imm(tmp, 4); |
806 | tmp = emit_memhandler_read(2); |
807 | emith_write_sr(tmp); |
808 | rcache_free_tmp(tmp); |
809 | tmp = rcache_get_reg(SHR_SP, RC_GR_RMW); |
810 | emith_add_r_imm(tmp, 4*2); |
e898de13 |
811 | test_irq = 1; |
812 | cycles += 3; |
80599a42 |
813 | break; |
814 | default: |
815 | goto default_; |
e898de13 |
816 | } |
817 | goto end_op; |
80599a42 |
818 | case 0x0c: // MOV.B @(R0,Rm),Rn 0000nnnnmmmm1100 |
819 | case 0x0d: // MOV.W @(R0,Rm),Rn 0000nnnnmmmm1101 |
820 | case 0x0e: // MOV.L @(R0,Rm),Rn 0000nnnnmmmm1110 |
52d759c3 |
821 | tmp = emit_indirect_indexed_read(SHR_R0, GET_Rm(), op & 3); |
80599a42 |
822 | tmp2 = rcache_get_reg(GET_Rn(), RC_GR_WRITE); |
80599a42 |
823 | if ((op & 3) != 2) { |
824 | emith_sext(tmp2, tmp, (op & 1) ? 16 : 8); |
825 | } else |
826 | emith_move_r_r(tmp2, tmp); |
52d759c3 |
827 | rcache_free_tmp(tmp); |
80599a42 |
828 | goto end_op; |
829 | case 0x0f: // MAC.L @Rm+,@Rn+ 0000nnnnmmmm1111 |
f0d7b1fa |
830 | emit_indirect_read_double(&tmp, &tmp2, GET_Rn(), GET_Rm(), 2); |
831 | tmp3 = rcache_get_reg(SHR_SR, RC_GR_READ); |
832 | tmp4 = rcache_get_reg(SHR_MACH, RC_GR_RMW); |
833 | /* MS 16 MAC bits unused if saturated */ |
834 | emith_tst_r_imm(tmp3, S); |
835 | EMITH_SJMP_START(DCOND_EQ); |
836 | emith_clear_msb_c(DCOND_NE, tmp4, tmp4, 16); |
837 | EMITH_SJMP_END(DCOND_EQ); |
838 | tmp3 = rcache_get_reg(SHR_MACL, RC_GR_RMW); // might evict SR |
839 | emith_mula_s64(tmp3, tmp4, tmp, tmp2); |
840 | rcache_free_tmp(tmp); |
841 | rcache_free_tmp(tmp2); |
842 | rcache_clean(); |
843 | tmp3 = rcache_get_reg(SHR_SR, RC_GR_READ); |
844 | emith_tst_r_imm(tmp3, S); |
845 | EMITH_SJMP_START(DCOND_EQ); |
846 | emith_call_cond(DCOND_NE, sh2_macl_sat_fixup); |
847 | EMITH_SJMP_END(DCOND_EQ); |
848 | rcache_invalidate(); |
849 | cycles += 3; |
850 | goto end_op; |
80599a42 |
851 | } |
852 | goto default_; |
853 | |
3863edbd |
854 | ///////////////////////////////////////////// |
80599a42 |
855 | case 0x01: |
856 | // MOV.L Rm,@(disp,Rn) 0001nnnnmmmmdddd |
857 | rcache_clean(); |
858 | tmp = rcache_get_reg_arg(0, GET_Rn()); |
859 | tmp2 = rcache_get_reg_arg(1, GET_Rm()); |
860 | emith_add_r_imm(tmp, (op & 0x0f) * 4); |
861 | emit_memhandler_write(2); |
862 | goto end_op; |
863 | |
864 | case 0x02: |
865 | switch (op & 0x0f) |
866 | { |
867 | case 0x00: // MOV.B Rm,@Rn 0010nnnnmmmm0000 |
868 | case 0x01: // MOV.W Rm,@Rn 0010nnnnmmmm0001 |
869 | case 0x02: // MOV.L Rm,@Rn 0010nnnnmmmm0010 |
870 | rcache_clean(); |
871 | rcache_get_reg_arg(0, GET_Rn()); |
872 | rcache_get_reg_arg(1, GET_Rm()); |
873 | emit_memhandler_write(op & 3); |
874 | goto end_op; |
875 | case 0x04: // MOV.B Rm,@–Rn 0010nnnnmmmm0100 |
876 | case 0x05: // MOV.W Rm,@–Rn 0010nnnnmmmm0101 |
877 | case 0x06: // MOV.L Rm,@–Rn 0010nnnnmmmm0110 |
878 | tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW); |
879 | emith_sub_r_imm(tmp, (1 << (op & 3))); |
880 | rcache_clean(); |
881 | rcache_get_reg_arg(0, GET_Rn()); |
882 | rcache_get_reg_arg(1, GET_Rm()); |
883 | emit_memhandler_write(op & 3); |
884 | goto end_op; |
885 | case 0x07: // DIV0S Rm,Rn 0010nnnnmmmm0111 |
886 | tmp = rcache_get_reg(SHR_SR, RC_GR_RMW); |
887 | tmp2 = rcache_get_reg(GET_Rn(), RC_GR_READ); |
888 | tmp3 = rcache_get_reg(GET_Rm(), RC_GR_READ); |
889 | emith_bic_r_imm(tmp, M|Q|T); |
890 | emith_tst_r_imm(tmp2, (1<<31)); |
891 | EMITH_SJMP_START(DCOND_EQ); |
892 | emith_or_r_imm_c(DCOND_NE, tmp, Q); |
893 | EMITH_SJMP_END(DCOND_EQ); |
894 | emith_tst_r_imm(tmp3, (1<<31)); |
895 | EMITH_SJMP_START(DCOND_EQ); |
896 | emith_or_r_imm_c(DCOND_NE, tmp, M); |
897 | EMITH_SJMP_END(DCOND_EQ); |
898 | emith_teq_r_r(tmp2, tmp3); |
899 | EMITH_SJMP_START(DCOND_PL); |
900 | emith_or_r_imm_c(DCOND_MI, tmp, T); |
901 | EMITH_SJMP_END(DCOND_PL); |
902 | goto end_op; |
3863edbd |
903 | case 0x08: // TST Rm,Rn 0010nnnnmmmm1000 |
904 | tmp = rcache_get_reg(SHR_SR, RC_GR_RMW); |
905 | tmp2 = rcache_get_reg(GET_Rn(), RC_GR_READ); |
906 | tmp3 = rcache_get_reg(GET_Rm(), RC_GR_READ); |
907 | emith_bic_r_imm(tmp, T); |
908 | emith_tst_r_r(tmp2, tmp3); |
52d759c3 |
909 | emit_or_t_if_eq(tmp); |
3863edbd |
910 | goto end_op; |
911 | case 0x09: // AND Rm,Rn 0010nnnnmmmm1001 |
912 | tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW); |
913 | tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ); |
914 | emith_and_r_r(tmp, tmp2); |
915 | goto end_op; |
916 | case 0x0a: // XOR Rm,Rn 0010nnnnmmmm1010 |
917 | tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW); |
918 | tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ); |
919 | emith_eor_r_r(tmp, tmp2); |
920 | goto end_op; |
921 | case 0x0b: // OR Rm,Rn 0010nnnnmmmm1011 |
922 | tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW); |
923 | tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ); |
924 | emith_or_r_r(tmp, tmp2); |
925 | goto end_op; |
926 | case 0x0c: // CMP/STR Rm,Rn 0010nnnnmmmm1100 |
927 | tmp = rcache_get_tmp(); |
928 | tmp2 = rcache_get_reg(GET_Rn(), RC_GR_READ); |
929 | tmp3 = rcache_get_reg(GET_Rm(), RC_GR_READ); |
930 | emith_eor_r_r_r(tmp, tmp2, tmp3); |
931 | tmp2 = rcache_get_reg(SHR_SR, RC_GR_RMW); |
932 | emith_bic_r_imm(tmp2, T); |
933 | emith_tst_r_imm(tmp, 0x000000ff); |
52d759c3 |
934 | emit_or_t_if_eq(tmp); |
3863edbd |
935 | emith_tst_r_imm(tmp, 0x0000ff00); |
52d759c3 |
936 | emit_or_t_if_eq(tmp); |
3863edbd |
937 | emith_tst_r_imm(tmp, 0x00ff0000); |
52d759c3 |
938 | emit_or_t_if_eq(tmp); |
3863edbd |
939 | emith_tst_r_imm(tmp, 0xff000000); |
52d759c3 |
940 | emit_or_t_if_eq(tmp); |
3863edbd |
941 | rcache_free_tmp(tmp); |
942 | goto end_op; |
943 | case 0x0d: // XTRCT Rm,Rn 0010nnnnmmmm1101 |
944 | tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW); |
945 | tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ); |
946 | emith_lsr(tmp, tmp, 16); |
f0d7b1fa |
947 | emith_or_r_r_lsl(tmp, tmp2, 16); |
3863edbd |
948 | goto end_op; |
949 | case 0x0e: // MULU.W Rm,Rn 0010nnnnmmmm1110 |
950 | case 0x0f: // MULS.W Rm,Rn 0010nnnnmmmm1111 |
951 | tmp2 = rcache_get_reg(GET_Rn(), RC_GR_READ); |
952 | tmp = rcache_get_reg(SHR_MACL, RC_GR_WRITE); |
953 | if (op & 1) { |
954 | emith_sext(tmp, tmp2, 16); |
955 | } else |
956 | emith_clear_msb(tmp, tmp2, 16); |
957 | tmp3 = rcache_get_reg(GET_Rm(), RC_GR_READ); |
958 | tmp2 = rcache_get_tmp(); |
959 | if (op & 1) { |
960 | emith_sext(tmp2, tmp3, 16); |
961 | } else |
962 | emith_clear_msb(tmp2, tmp3, 16); |
963 | emith_mul(tmp, tmp, tmp2); |
964 | rcache_free_tmp(tmp2); |
965 | // FIXME: causes timing issues in Doom? |
966 | // cycles++; |
967 | goto end_op; |
679af8a3 |
968 | } |
969 | goto default_; |
970 | |
3863edbd |
971 | ///////////////////////////////////////////// |
972 | case 0x03: |
973 | switch (op & 0x0f) |
974 | { |
975 | case 0x00: // CMP/EQ Rm,Rn 0011nnnnmmmm0000 |
976 | case 0x02: // CMP/HS Rm,Rn 0011nnnnmmmm0010 |
977 | case 0x03: // CMP/GE Rm,Rn 0011nnnnmmmm0011 |
978 | case 0x06: // CMP/HI Rm,Rn 0011nnnnmmmm0110 |
979 | case 0x07: // CMP/GT Rm,Rn 0011nnnnmmmm0111 |
980 | tmp = rcache_get_reg(SHR_SR, RC_GR_RMW); |
981 | tmp2 = rcache_get_reg(GET_Rn(), RC_GR_READ); |
982 | tmp3 = rcache_get_reg(GET_Rm(), RC_GR_READ); |
983 | emith_bic_r_imm(tmp, T); |
984 | emith_cmp_r_r(tmp2, tmp3); |
985 | switch (op & 0x07) |
986 | { |
987 | case 0x00: // CMP/EQ |
52d759c3 |
988 | emit_or_t_if_eq(tmp); |
3863edbd |
989 | break; |
990 | case 0x02: // CMP/HS |
991 | EMITH_SJMP_START(DCOND_LO); |
992 | emith_or_r_imm_c(DCOND_HS, tmp, T); |
993 | EMITH_SJMP_END(DCOND_LO); |
994 | break; |
995 | case 0x03: // CMP/GE |
996 | EMITH_SJMP_START(DCOND_LT); |
997 | emith_or_r_imm_c(DCOND_GE, tmp, T); |
998 | EMITH_SJMP_END(DCOND_LT); |
999 | break; |
1000 | case 0x06: // CMP/HI |
1001 | EMITH_SJMP_START(DCOND_LS); |
1002 | emith_or_r_imm_c(DCOND_HI, tmp, T); |
1003 | EMITH_SJMP_END(DCOND_LS); |
1004 | break; |
1005 | case 0x07: // CMP/GT |
1006 | EMITH_SJMP_START(DCOND_LE); |
1007 | emith_or_r_imm_c(DCOND_GT, tmp, T); |
1008 | EMITH_SJMP_END(DCOND_LE); |
1009 | break; |
1010 | } |
1011 | goto end_op; |
1012 | case 0x04: // DIV1 Rm,Rn 0011nnnnmmmm0100 |
f0d7b1fa |
1013 | // Q1 = carry(Rn = (Rn << 1) | T) |
1014 | // if Q ^ M |
1015 | // Q2 = carry(Rn += Rm) |
1016 | // else |
1017 | // Q2 = carry(Rn -= Rm) |
1018 | // Q = M ^ Q1 ^ Q2 |
1019 | // T = (Q == M) = !(Q ^ M) = !(Q1 ^ Q2) |
1020 | tmp2 = rcache_get_reg(GET_Rn(), RC_GR_RMW); |
1021 | tmp3 = rcache_get_reg(GET_Rm(), RC_GR_READ); |
1022 | sr = rcache_get_reg(SHR_SR, RC_GR_RMW); |
1023 | emith_set_carry(sr); |
1024 | emith_adcf_r_r(tmp2, tmp2); |
1025 | emith_carry_to_t(sr, 0); // keep Q1 in T for now |
1026 | tmp4 = rcache_get_tmp(); |
1027 | emith_and_r_r_imm(tmp4, sr, M); |
1028 | emith_eor_r_r_lsr(sr, tmp4, M_SHIFT - Q_SHIFT); // Q ^= M |
1029 | rcache_free_tmp(tmp4); |
1030 | // add or sub, invert T if carry to get Q1 ^ Q2 |
1031 | // in: (Q ^ M) passed in Q, Q1 in T |
1032 | emith_sh2_div1_step(tmp2, tmp3, sr); |
1033 | emith_bic_r_imm(sr, Q); |
1034 | emith_tst_r_imm(sr, M); |
1035 | EMITH_SJMP_START(DCOND_EQ); |
1036 | emith_or_r_imm_c(DCOND_NE, sr, Q); // Q = M |
1037 | EMITH_SJMP_END(DCOND_EQ); |
1038 | emith_tst_r_imm(sr, T); |
1039 | EMITH_SJMP_START(DCOND_EQ); |
1040 | emith_eor_r_imm_c(DCOND_NE, sr, Q); // Q = M ^ Q1 ^ Q2 |
1041 | EMITH_SJMP_END(DCOND_EQ); |
1042 | emith_eor_r_imm(sr, T); // T = !(Q1 ^ Q2) |
1043 | goto end_op; |
3863edbd |
1044 | case 0x05: // DMULU.L Rm,Rn 0011nnnnmmmm0101 |
1045 | tmp = rcache_get_reg(GET_Rn(), RC_GR_READ); |
1046 | tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ); |
1047 | tmp3 = rcache_get_reg(SHR_MACL, RC_GR_WRITE); |
1048 | tmp4 = rcache_get_reg(SHR_MACH, RC_GR_WRITE); |
1049 | emith_mul_u64(tmp3, tmp4, tmp, tmp2); |
1050 | goto end_op; |
1051 | case 0x08: // SUB Rm,Rn 0011nnnnmmmm1000 |
1052 | case 0x0c: // ADD Rm,Rn 0011nnnnmmmm1100 |
1053 | tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW); |
1054 | tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ); |
1055 | if (op & 4) { |
1056 | emith_add_r_r(tmp, tmp2); |
1057 | } else |
1058 | emith_sub_r_r(tmp, tmp2); |
1059 | goto end_op; |
1060 | case 0x0a: // SUBC Rm,Rn 0011nnnnmmmm1010 |
1061 | case 0x0e: // ADDC Rm,Rn 0011nnnnmmmm1110 |
1062 | tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW); |
1063 | tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ); |
1064 | tmp3 = rcache_get_reg(SHR_SR, RC_GR_RMW); |
1065 | if (op & 4) { // adc |
1066 | emith_set_carry(tmp3); |
1067 | emith_adcf_r_r(tmp, tmp2); |
ed8cf79b |
1068 | emith_carry_to_t(tmp3, 0); |
3863edbd |
1069 | } else { |
1070 | emith_set_carry_sub(tmp3); |
1071 | emith_sbcf_r_r(tmp, tmp2); |
ed8cf79b |
1072 | emith_carry_to_t(tmp3, 1); |
3863edbd |
1073 | } |
3863edbd |
1074 | goto end_op; |
1075 | case 0x0b: // SUBV Rm,Rn 0011nnnnmmmm1011 |
1076 | case 0x0f: // ADDV Rm,Rn 0011nnnnmmmm1111 |
1077 | tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW); |
1078 | tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ); |
1079 | tmp3 = rcache_get_reg(SHR_SR, RC_GR_RMW); |
1080 | emith_bic_r_imm(tmp3, T); |
1081 | if (op & 4) { |
1082 | emith_addf_r_r(tmp, tmp2); |
1083 | } else |
1084 | emith_subf_r_r(tmp, tmp2); |
1085 | EMITH_SJMP_START(DCOND_VC); |
1086 | emith_or_r_imm_c(DCOND_VS, tmp3, T); |
1087 | EMITH_SJMP_END(DCOND_VC); |
1088 | goto end_op; |
1089 | case 0x0d: // DMULS.L Rm,Rn 0011nnnnmmmm1101 |
1090 | tmp = rcache_get_reg(GET_Rn(), RC_GR_READ); |
1091 | tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ); |
1092 | tmp3 = rcache_get_reg(SHR_MACL, RC_GR_WRITE); |
1093 | tmp4 = rcache_get_reg(SHR_MACH, RC_GR_WRITE); |
1094 | emith_mul_s64(tmp3, tmp4, tmp, tmp2); |
1095 | goto end_op; |
1096 | } |
1097 | goto default_; |
1098 | |
1099 | ///////////////////////////////////////////// |
679af8a3 |
1100 | case 0x04: |
3863edbd |
1101 | switch (op & 0x0f) |
1102 | { |
c18edb34 |
1103 | case 0x00: |
3863edbd |
1104 | switch (GET_Fx()) |
1105 | { |
1106 | case 0: // SHLL Rn 0100nnnn00000000 |
1107 | case 2: // SHAL Rn 0100nnnn00100000 |
1108 | tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW); |
1109 | tmp2 = rcache_get_reg(SHR_SR, RC_GR_RMW); |
3863edbd |
1110 | emith_lslf(tmp, tmp, 1); |
ed8cf79b |
1111 | emith_carry_to_t(tmp2, 0); |
3863edbd |
1112 | goto end_op; |
1113 | case 1: // DT Rn 0100nnnn00010000 |
1114 | if (p32x_sh2_read16(pc, sh2) == 0x8bfd) { // BF #-2 |
1115 | emith_sh2_dtbf_loop(); |
1116 | goto end_op; |
1117 | } |
1118 | tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW); |
1119 | tmp2 = rcache_get_reg(SHR_SR, RC_GR_RMW); |
1120 | emith_bic_r_imm(tmp2, T); |
1121 | emith_subf_r_imm(tmp, 1); |
52d759c3 |
1122 | emit_or_t_if_eq(tmp2); |
80599a42 |
1123 | goto end_op; |
1124 | } |
3863edbd |
1125 | goto default_; |
ed8cf79b |
1126 | case 0x01: |
1127 | switch (GET_Fx()) |
1128 | { |
1129 | case 0: // SHLR Rn 0100nnnn00000001 |
1130 | case 2: // SHAR Rn 0100nnnn00100001 |
1131 | tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW); |
1132 | tmp2 = rcache_get_reg(SHR_SR, RC_GR_RMW); |
1133 | if (op & 0x20) { |
1134 | emith_asrf(tmp, tmp, 1); |
1135 | } else |
1136 | emith_lsrf(tmp, tmp, 1); |
1137 | emith_carry_to_t(tmp2, 0); |
1138 | goto end_op; |
1139 | case 1: // CMP/PZ Rn 0100nnnn00010001 |
1140 | tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW); |
1141 | tmp2 = rcache_get_reg(SHR_SR, RC_GR_RMW); |
1142 | emith_bic_r_imm(tmp2, T); |
1143 | emith_cmp_r_imm(tmp, 0); |
1144 | EMITH_SJMP_START(DCOND_LT); |
1145 | emith_or_r_imm_c(DCOND_GE, tmp2, T); |
1146 | EMITH_SJMP_END(DCOND_LT); |
1147 | goto end_op; |
1148 | } |
1149 | goto default_; |
1150 | case 0x02: |
1151 | case 0x03: |
1152 | switch (op & 0x3f) |
1153 | { |
1154 | case 0x02: // STS.L MACH,@–Rn 0100nnnn00000010 |
1155 | tmp = SHR_MACH; |
1156 | break; |
1157 | case 0x12: // STS.L MACL,@–Rn 0100nnnn00010010 |
1158 | tmp = SHR_MACL; |
1159 | break; |
1160 | case 0x22: // STS.L PR,@–Rn 0100nnnn00100010 |
1161 | tmp = SHR_PR; |
1162 | break; |
1163 | case 0x03: // STC.L SR,@–Rn 0100nnnn00000011 |
1164 | tmp = SHR_SR; |
1165 | break; |
1166 | case 0x13: // STC.L GBR,@–Rn 0100nnnn00010011 |
1167 | tmp = SHR_GBR; |
1168 | break; |
1169 | case 0x23: // STC.L VBR,@–Rn 0100nnnn00100011 |
1170 | tmp = SHR_VBR; |
1171 | break; |
1172 | default: |
e898de13 |
1173 | goto default_; |
ed8cf79b |
1174 | } |
1175 | tmp2 = rcache_get_reg(GET_Rn(), RC_GR_RMW); |
1176 | emith_sub_r_imm(tmp2, 4); |
1177 | rcache_clean(); |
1178 | rcache_get_reg_arg(0, GET_Rn()); |
1179 | tmp3 = rcache_get_reg_arg(1, tmp); |
1180 | if (tmp == SHR_SR) |
1181 | emith_clear_msb(tmp3, tmp3, 20); // reserved bits defined by ISA as 0 |
1182 | emit_memhandler_write(2); |
1183 | goto end_op; |
1184 | case 0x04: |
1185 | case 0x05: |
1186 | switch (op & 0x3f) |
1187 | { |
1188 | case 0x04: // ROTL Rn 0100nnnn00000100 |
1189 | case 0x05: // ROTR Rn 0100nnnn00000101 |
1190 | tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW); |
1191 | tmp2 = rcache_get_reg(SHR_SR, RC_GR_RMW); |
1192 | if (op & 1) { |
1193 | emith_rorf(tmp, tmp, 1); |
1194 | } else |
1195 | emith_rolf(tmp, tmp, 1); |
1196 | emith_carry_to_t(tmp2, 0); |
1197 | goto end_op; |
1198 | case 0x24: // ROTCL Rn 0100nnnn00100100 |
1199 | case 0x25: // ROTCR Rn 0100nnnn00100101 |
1200 | tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW); |
1201 | tmp2 = rcache_get_reg(SHR_SR, RC_GR_RMW); |
1202 | emith_set_carry(tmp2); |
1203 | if (op & 1) { |
1204 | emith_rorcf(tmp); |
1205 | } else |
1206 | emith_rolcf(tmp); |
1207 | emith_carry_to_t(tmp2, 0); |
1208 | goto end_op; |
1209 | case 0x15: // CMP/PL Rn 0100nnnn00010101 |
1210 | tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW); |
1211 | tmp2 = rcache_get_reg(SHR_SR, RC_GR_RMW); |
1212 | emith_bic_r_imm(tmp2, T); |
1213 | emith_cmp_r_imm(tmp, 0); |
1214 | EMITH_SJMP_START(DCOND_LE); |
1215 | emith_or_r_imm_c(DCOND_GT, tmp2, T); |
1216 | EMITH_SJMP_END(DCOND_LE); |
1217 | goto end_op; |
1218 | } |
e898de13 |
1219 | goto default_; |
ed8cf79b |
1220 | case 0x06: |
1221 | case 0x07: |
1222 | switch (op & 0x3f) |
1223 | { |
1224 | case 0x06: // LDS.L @Rm+,MACH 0100mmmm00000110 |
1225 | tmp = SHR_MACH; |
1226 | break; |
1227 | case 0x16: // LDS.L @Rm+,MACL 0100mmmm00010110 |
1228 | tmp = SHR_MACL; |
1229 | break; |
1230 | case 0x26: // LDS.L @Rm+,PR 0100mmmm00100110 |
1231 | tmp = SHR_PR; |
1232 | break; |
1233 | case 0x07: // LDC.L @Rm+,SR 0100mmmm00000111 |
1234 | tmp = SHR_SR; |
1235 | break; |
1236 | case 0x17: // LDC.L @Rm+,GBR 0100mmmm00010111 |
1237 | tmp = SHR_GBR; |
1238 | break; |
1239 | case 0x27: // LDC.L @Rm+,VBR 0100mmmm00100111 |
1240 | tmp = SHR_VBR; |
1241 | break; |
1242 | default: |
1243 | goto default_; |
1244 | } |
1245 | rcache_clean(); |
1246 | rcache_get_reg_arg(0, GET_Rn()); |
1247 | tmp2 = emit_memhandler_read(2); |
1248 | if (tmp == SHR_SR) { |
1249 | emith_write_sr(tmp2); |
1250 | test_irq = 1; |
1251 | } else { |
1252 | tmp = rcache_get_reg(tmp, RC_GR_WRITE); |
1253 | emith_move_r_r(tmp, tmp2); |
1254 | } |
1255 | rcache_free_tmp(tmp2); |
1256 | tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW); |
1257 | emith_add_r_imm(tmp, 4); |
1258 | goto end_op; |
52d759c3 |
1259 | case 0x08: |
1260 | case 0x09: |
1261 | switch (GET_Fx()) |
1262 | { |
1263 | case 0: |
1264 | // SHLL2 Rn 0100nnnn00001000 |
1265 | // SHLR2 Rn 0100nnnn00001001 |
1266 | tmp = 2; |
1267 | break; |
1268 | case 1: |
1269 | // SHLL8 Rn 0100nnnn00011000 |
1270 | // SHLR8 Rn 0100nnnn00011001 |
1271 | tmp = 8; |
1272 | break; |
1273 | case 2: |
1274 | // SHLL16 Rn 0100nnnn00101000 |
1275 | // SHLR16 Rn 0100nnnn00101001 |
1276 | tmp = 16; |
1277 | break; |
1278 | default: |
1279 | goto default_; |
1280 | } |
1281 | tmp2 = rcache_get_reg(GET_Rn(), RC_GR_RMW); |
1282 | if (op & 1) { |
1283 | emith_lsr(tmp2, tmp2, tmp); |
1284 | } else |
1285 | emith_lsl(tmp2, tmp2, tmp); |
1286 | goto end_op; |
1287 | case 0x0a: |
1288 | switch (GET_Fx()) |
1289 | { |
1290 | case 0: // LDS Rm,MACH 0100mmmm00001010 |
1291 | tmp2 = SHR_MACH; |
1292 | break; |
1293 | case 1: // LDS Rm,MACL 0100mmmm00011010 |
1294 | tmp2 = SHR_MACL; |
1295 | break; |
1296 | case 2: // LDS Rm,PR 0100mmmm00101010 |
1297 | tmp2 = SHR_PR; |
1298 | break; |
1299 | default: |
1300 | goto default_; |
1301 | } |
1302 | emit_move_r_r(tmp2, GET_Rn()); |
1303 | goto end_op; |
e898de13 |
1304 | case 0x0b: |
52d759c3 |
1305 | switch (GET_Fx()) |
1306 | { |
1307 | case 0: // JSR @Rm 0100mmmm00001011 |
1308 | case 2: // JMP @Rm 0100mmmm00101011 |
1309 | DELAYED_OP; |
1310 | if (!(op & 0x20)) |
1311 | emit_move_r_imm32(SHR_PR, pc + 2); |
1312 | emit_move_r_r(SHR_PPC, (op >> 8) & 0x0f); |
1313 | cycles++; |
1314 | break; |
1315 | case 1: // TAS.B @Rn 0100nnnn00011011 |
1316 | // XXX: is TAS working on 32X? |
1317 | rcache_clean(); |
1318 | rcache_get_reg_arg(0, GET_Rn()); |
1319 | tmp = emit_memhandler_read(0); |
1320 | tmp2 = rcache_get_reg(SHR_SR, RC_GR_RMW); |
1321 | emith_bic_r_imm(tmp2, T); |
1322 | emith_cmp_r_imm(tmp, 0); |
1323 | emit_or_t_if_eq(tmp2); |
1324 | rcache_clean(); |
1325 | emith_or_r_imm(tmp, 0x80); |
1326 | tmp2 = rcache_get_tmp_arg(1); // assuming it differs to tmp |
1327 | emith_move_r_r(tmp2, tmp); |
1328 | rcache_free_tmp(tmp); |
1329 | rcache_get_reg_arg(0, GET_Rn()); |
1330 | emit_memhandler_write(0); |
1331 | cycles += 3; |
1332 | break; |
1333 | default: |
e898de13 |
1334 | goto default_; |
52d759c3 |
1335 | } |
e898de13 |
1336 | goto end_op; |
1337 | case 0x0e: |
52d759c3 |
1338 | tmp = rcache_get_reg(GET_Rn(), RC_GR_READ); |
1339 | switch (GET_Fx()) |
1340 | { |
1341 | case 0: // LDC Rm,SR 0100mmmm00001110 |
1342 | tmp2 = SHR_SR; |
1343 | break; |
1344 | case 1: // LDC Rm,GBR 0100mmmm00011110 |
1345 | tmp2 = SHR_GBR; |
1346 | break; |
1347 | case 2: // LDC Rm,VBR 0100mmmm00101110 |
1348 | tmp2 = SHR_VBR; |
1349 | break; |
1350 | default: |
e898de13 |
1351 | goto default_; |
52d759c3 |
1352 | } |
1353 | if (tmp2 == SHR_SR) { |
1354 | emith_write_sr(tmp); |
52d759c3 |
1355 | test_irq = 1; |
1356 | } else { |
1357 | tmp2 = rcache_get_reg(tmp2, RC_GR_WRITE); |
1358 | emith_move_r_r(tmp2, tmp); |
1359 | } |
1360 | goto end_op; |
1361 | case 0x0f: |
1362 | // MAC @Rm+,@Rn+ 0100nnnnmmmm1111 |
f0d7b1fa |
1363 | emit_indirect_read_double(&tmp, &tmp2, GET_Rn(), GET_Rm(), 1); |
1364 | emith_sext(tmp, tmp, 16); |
1365 | emith_sext(tmp2, tmp2, 16); |
1366 | tmp3 = rcache_get_reg(SHR_MACL, RC_GR_RMW); |
1367 | tmp4 = rcache_get_reg(SHR_MACH, RC_GR_RMW); |
1368 | emith_mula_s64(tmp3, tmp4, tmp, tmp2); |
1369 | rcache_free_tmp(tmp); |
1370 | rcache_free_tmp(tmp2); |
1371 | rcache_clean(); |
1372 | // XXX: MACH should be untouched when S is set? |
1373 | tmp3 = rcache_get_reg(SHR_SR, RC_GR_READ); |
1374 | emith_tst_r_imm(tmp3, S); |
1375 | EMITH_SJMP_START(DCOND_EQ); |
1376 | emith_call_cond(DCOND_NE, sh2_macw_sat_fixup); |
1377 | EMITH_SJMP_END(DCOND_EQ); |
1378 | rcache_invalidate(); |
1379 | cycles += 2; |
1380 | goto end_op; |
679af8a3 |
1381 | } |
1382 | goto default_; |
1383 | |
52d759c3 |
1384 | ///////////////////////////////////////////// |
1385 | case 0x05: |
1386 | // MOV.L @(disp,Rm),Rn 0101nnnnmmmmdddd |
1387 | rcache_clean(); |
1388 | tmp = rcache_get_reg_arg(0, GET_Rm()); |
1389 | emith_add_r_imm(tmp, (op & 0x0f) * 4); |
1390 | tmp = emit_memhandler_read(2); |
1391 | tmp2 = rcache_get_reg(GET_Rn(), RC_GR_WRITE); |
1392 | emith_move_r_r(tmp2, tmp); |
1393 | rcache_free_tmp(tmp); |
1394 | goto end_op; |
1395 | |
1396 | ///////////////////////////////////////////// |
1397 | case 0x06: |
1398 | switch (op & 0x0f) |
1399 | { |
1400 | case 0x00: // MOV.B @Rm,Rn 0110nnnnmmmm0000 |
1401 | case 0x01: // MOV.W @Rm,Rn 0110nnnnmmmm0001 |
1402 | case 0x02: // MOV.L @Rm,Rn 0110nnnnmmmm0010 |
1403 | case 0x04: // MOV.B @Rm+,Rn 0110nnnnmmmm0100 |
1404 | case 0x05: // MOV.W @Rm+,Rn 0110nnnnmmmm0101 |
1405 | case 0x06: // MOV.L @Rm+,Rn 0110nnnnmmmm0110 |
1406 | rcache_clean(); |
1407 | rcache_get_reg_arg(0, GET_Rm()); |
1408 | tmp = emit_memhandler_read(op & 3); |
1409 | tmp2 = rcache_get_reg(GET_Rn(), RC_GR_WRITE); |
1410 | if ((op & 3) != 2) { |
1411 | emith_sext(tmp2, tmp, (op & 1) ? 16 : 8); |
1412 | } else |
1413 | emith_move_r_r(tmp2, tmp); |
1414 | rcache_free_tmp(tmp); |
1415 | if ((op & 7) >= 4 && GET_Rn() != GET_Rm()) { |
1416 | tmp = rcache_get_reg(GET_Rm(), RC_GR_RMW); |
1417 | emith_add_r_imm(tmp, (1 << (op & 3))); |
1418 | } |
1419 | goto end_op; |
1420 | case 0x03: |
1421 | case 0x07 ... 0x0f: |
1422 | tmp = rcache_get_reg(GET_Rm(), RC_GR_READ); |
1423 | tmp2 = rcache_get_reg(GET_Rn(), RC_GR_WRITE); |
1424 | switch (op & 0x0f) |
1425 | { |
1426 | case 0x03: // MOV Rm,Rn 0110nnnnmmmm0011 |
1427 | emith_move_r_r(tmp2, tmp); |
1428 | break; |
1429 | case 0x07: // NOT Rm,Rn 0110nnnnmmmm0111 |
1430 | emith_mvn_r_r(tmp2, tmp); |
1431 | break; |
1432 | case 0x08: // SWAP.B Rm,Rn 0110nnnnmmmm1000 |
1433 | tmp3 = tmp2; |
1434 | if (tmp == tmp2) |
1435 | tmp3 = rcache_get_tmp(); |
1436 | tmp4 = rcache_get_tmp(); |
1437 | emith_lsr(tmp3, tmp, 16); |
f0d7b1fa |
1438 | emith_or_r_r_lsl(tmp3, tmp, 24); |
52d759c3 |
1439 | emith_and_r_r_imm(tmp4, tmp, 0xff00); |
f0d7b1fa |
1440 | emith_or_r_r_lsl(tmp3, tmp4, 8); |
52d759c3 |
1441 | emith_rol(tmp2, tmp3, 16); |
1442 | rcache_free_tmp(tmp4); |
1443 | if (tmp == tmp2) |
1444 | rcache_free_tmp(tmp3); |
1445 | break; |
1446 | case 0x09: // SWAP.W Rm,Rn 0110nnnnmmmm1001 |
1447 | emith_rol(tmp2, tmp, 16); |
1448 | break; |
1449 | case 0x0a: // NEGC Rm,Rn 0110nnnnmmmm1010 |
1450 | tmp3 = rcache_get_reg(SHR_SR, RC_GR_RMW); |
1451 | emith_set_carry_sub(tmp3); |
1452 | emith_negcf_r_r(tmp2, tmp); |
1453 | emith_carry_to_t(tmp3, 1); |
1454 | break; |
1455 | case 0x0b: // NEG Rm,Rn 0110nnnnmmmm1011 |
1456 | emith_neg_r_r(tmp2, tmp); |
1457 | break; |
1458 | case 0x0c: // EXTU.B Rm,Rn 0110nnnnmmmm1100 |
1459 | emith_clear_msb(tmp2, tmp, 24); |
1460 | break; |
1461 | case 0x0d: // EXTU.W Rm,Rn 0110nnnnmmmm1101 |
1462 | emith_clear_msb(tmp2, tmp, 16); |
1463 | break; |
1464 | case 0x0e: // EXTS.B Rm,Rn 0110nnnnmmmm1110 |
1465 | emith_sext(tmp2, tmp, 8); |
1466 | break; |
1467 | case 0x0f: // EXTS.W Rm,Rn 0110nnnnmmmm1111 |
1468 | emith_sext(tmp2, tmp, 16); |
1469 | break; |
1470 | } |
1471 | goto end_op; |
1472 | } |
1473 | goto default_; |
1474 | |
1475 | ///////////////////////////////////////////// |
1476 | case 0x07: |
1477 | // ADD #imm,Rn 0111nnnniiiiiiii |
1478 | tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW); |
1479 | if (op & 0x80) { // adding negative |
1480 | emith_sub_r_imm(tmp, -op & 0xff); |
1481 | } else |
1482 | emith_add_r_imm(tmp, op & 0xff); |
1483 | goto end_op; |
1484 | |
3863edbd |
1485 | ///////////////////////////////////////////// |
e898de13 |
1486 | case 0x08: |
52d759c3 |
1487 | switch (op & 0x0f00) |
1488 | { |
1489 | case 0x0000: // MOV.B R0,@(disp,Rn) 10000000nnnndddd |
1490 | case 0x0100: // MOV.W R0,@(disp,Rn) 10000001nnnndddd |
1491 | rcache_clean(); |
1492 | tmp = rcache_get_reg_arg(0, GET_Rm()); |
1493 | tmp2 = rcache_get_reg_arg(1, SHR_R0); |
1494 | tmp3 = (op & 0x100) >> 8; |
1495 | emith_add_r_imm(tmp, (op & 0x0f) << tmp3); |
1496 | emit_memhandler_write(tmp3); |
1497 | goto end_op; |
1498 | case 0x0400: // MOV.B @(disp,Rm),R0 10000100mmmmdddd |
1499 | case 0x0500: // MOV.W @(disp,Rm),R0 10000101mmmmdddd |
1500 | rcache_clean(); |
1501 | tmp = rcache_get_reg_arg(0, GET_Rm()); |
1502 | tmp3 = (op & 0x100) >> 8; |
1503 | emith_add_r_imm(tmp, (op & 0x0f) << tmp3); |
1504 | tmp = emit_memhandler_read(tmp3); |
1505 | tmp2 = rcache_get_reg(0, RC_GR_WRITE); |
1506 | emith_sext(tmp2, tmp, 8 << tmp3); |
1507 | rcache_free_tmp(tmp); |
1508 | goto end_op; |
1509 | case 0x0800: // CMP/EQ #imm,R0 10001000iiiiiiii |
1510 | // XXX: could use cmn |
1511 | tmp = rcache_get_tmp(); |
1512 | tmp2 = rcache_get_reg(0, RC_GR_READ); |
1513 | tmp3 = rcache_get_reg(SHR_SR, RC_GR_RMW); |
1514 | emith_move_r_imm_s8(tmp, op & 0xff); |
1515 | emith_bic_r_imm(tmp3, T); |
1516 | emith_cmp_r_r(tmp2, tmp); |
1517 | emit_or_t_if_eq(tmp3); |
1518 | rcache_free_tmp(tmp); |
1519 | goto end_op; |
1520 | case 0x0d00: // BT/S label 10001101dddddddd |
1521 | case 0x0f00: // BF/S label 10001111dddddddd |
679af8a3 |
1522 | DELAYED_OP; |
1523 | cycles--; |
679af8a3 |
1524 | // fallthrough |
52d759c3 |
1525 | case 0x0900: // BT label 10001001dddddddd |
1526 | case 0x0b00: { // BF label 10001011dddddddd |
80599a42 |
1527 | // jmp_cond ~ cond when guest doesn't jump |
1528 | int jmp_cond = (op & 0x0200) ? DCOND_NE : DCOND_EQ; |
1529 | int insn_cond = (op & 0x0200) ? DCOND_EQ : DCOND_NE; |
1530 | signed int offs = ((signed int)(op << 24) >> 23); |
1531 | tmp = rcache_get_reg(delayed_op ? SHR_PPC : SHR_PC, RC_GR_WRITE); |
1532 | emith_move_r_imm(tmp, pc + (delayed_op ? 2 : 0)); |
1533 | emith_sh2_test_t(); |
1534 | EMITH_SJMP_START(jmp_cond); |
1535 | if (!delayed_op) |
1536 | offs += 2; |
1537 | if (offs < 0) { |
1538 | emith_sub_r_imm_c(insn_cond, tmp, -offs); |
1539 | } else |
1540 | emith_add_r_imm_c(insn_cond, tmp, offs); |
1541 | EMITH_SJMP_END(jmp_cond); |
e898de13 |
1542 | cycles += 2; |
1543 | if (!delayed_op) |
52d759c3 |
1544 | goto end_block_btf; |
e898de13 |
1545 | goto end_op; |
80599a42 |
1546 | }} |
679af8a3 |
1547 | goto default_; |
679af8a3 |
1548 | |
52d759c3 |
1549 | ///////////////////////////////////////////// |
1550 | case 0x09: |
1551 | // MOV.W @(disp,PC),Rn 1001nnnndddddddd |
f0d7b1fa |
1552 | rcache_clean(); |
1553 | tmp = rcache_get_tmp_arg(0); |
1554 | emith_move_r_imm(tmp, pc + (op & 0xff) * 2 + 2); |
1555 | tmp = emit_memhandler_read(1); |
1556 | tmp2 = rcache_get_reg(GET_Rn(), RC_GR_WRITE); |
1557 | emith_sext(tmp2, tmp, 16); |
1558 | rcache_free_tmp(tmp); |
1559 | goto end_op; |
52d759c3 |
1560 | |
3863edbd |
1561 | ///////////////////////////////////////////// |
679af8a3 |
1562 | case 0x0a: |
1563 | // BRA label 1010dddddddddddd |
1564 | DELAYED_OP; |
1565 | do_bra: |
1566 | tmp = ((signed int)(op << 20) >> 19); |
e898de13 |
1567 | emit_move_r_imm32(SHR_PPC, pc + tmp + 2); |
679af8a3 |
1568 | cycles++; |
e898de13 |
1569 | break; |
679af8a3 |
1570 | |
3863edbd |
1571 | ///////////////////////////////////////////// |
679af8a3 |
1572 | case 0x0b: |
1573 | // BSR label 1011dddddddddddd |
1574 | DELAYED_OP; |
e898de13 |
1575 | emit_move_r_imm32(SHR_PR, pc + 2); |
679af8a3 |
1576 | goto do_bra; |
1577 | |
52d759c3 |
1578 | ///////////////////////////////////////////// |
1579 | case 0x0c: |
1580 | switch (op & 0x0f00) |
1581 | { |
1582 | case 0x0000: // MOV.B R0,@(disp,GBR) 11000000dddddddd |
1583 | case 0x0100: // MOV.W R0,@(disp,GBR) 11000001dddddddd |
1584 | case 0x0200: // MOV.L R0,@(disp,GBR) 11000010dddddddd |
1585 | rcache_clean(); |
1586 | tmp = rcache_get_reg_arg(0, SHR_GBR); |
1587 | tmp2 = rcache_get_reg_arg(1, SHR_R0); |
1588 | tmp3 = (op & 0x300) >> 8; |
1589 | emith_add_r_imm(tmp, (op & 0xff) << tmp3); |
1590 | emit_memhandler_write(tmp3); |
1591 | goto end_op; |
1592 | case 0x0400: // MOV.B @(disp,GBR),R0 11000100dddddddd |
1593 | case 0x0500: // MOV.W @(disp,GBR),R0 11000101dddddddd |
1594 | case 0x0600: // MOV.L @(disp,GBR),R0 11000110dddddddd |
1595 | rcache_clean(); |
1596 | tmp = rcache_get_reg_arg(0, SHR_GBR); |
1597 | tmp3 = (op & 0x300) >> 8; |
1598 | emith_add_r_imm(tmp, (op & 0xff) << tmp3); |
1599 | tmp = emit_memhandler_read(tmp3); |
1600 | tmp2 = rcache_get_reg(0, RC_GR_WRITE); |
1601 | if (tmp3 != 2) { |
1602 | emith_sext(tmp2, tmp, 8 << tmp3); |
1603 | } else |
1604 | emith_move_r_r(tmp2, tmp); |
1605 | rcache_free_tmp(tmp); |
1606 | goto end_op; |
1607 | case 0x0300: // TRAPA #imm 11000011iiiiiiii |
1608 | tmp = rcache_get_reg(SHR_SP, RC_GR_RMW); |
1609 | emith_sub_r_imm(tmp, 4*2); |
1610 | rcache_clean(); |
1611 | // push SR |
1612 | tmp = rcache_get_reg_arg(0, SHR_SP); |
1613 | emith_add_r_imm(tmp, 4); |
1614 | tmp = rcache_get_reg_arg(1, SHR_SR); |
1615 | emith_clear_msb(tmp, tmp, 20); |
1616 | emit_memhandler_write(2); |
1617 | // push PC |
1618 | rcache_get_reg_arg(0, SHR_SP); |
1619 | tmp = rcache_get_tmp_arg(1); |
1620 | emith_move_r_imm(tmp, pc); |
1621 | emit_memhandler_write(2); |
1622 | // obtain new PC |
1623 | tmp = rcache_get_reg_arg(0, SHR_VBR); |
1624 | emith_add_r_imm(tmp, (op & 0xff) * 4); |
1625 | tmp = emit_memhandler_read(2); |
1626 | tmp2 = rcache_get_reg(SHR_PC, RC_GR_WRITE); |
1627 | emith_move_r_r(tmp2, tmp); |
1628 | rcache_free_tmp(tmp); |
1629 | cycles += 7; |
1630 | goto end_block_btf; |
1631 | case 0x0700: // MOVA @(disp,PC),R0 11000111dddddddd |
1632 | emit_move_r_imm32(SHR_R0, (pc + (op & 0xff) * 4 + 2) & ~3); |
1633 | goto end_op; |
1634 | case 0x0800: // TST #imm,R0 11001000iiiiiiii |
1635 | tmp = rcache_get_reg(SHR_R0, RC_GR_READ); |
1636 | tmp2 = rcache_get_reg(SHR_SR, RC_GR_RMW); |
1637 | emith_bic_r_imm(tmp2, T); |
1638 | emith_tst_r_imm(tmp, op & 0xff); |
1639 | emit_or_t_if_eq(tmp2); |
1640 | goto end_op; |
1641 | case 0x0900: // AND #imm,R0 11001001iiiiiiii |
1642 | tmp = rcache_get_reg(SHR_R0, RC_GR_RMW); |
1643 | emith_and_r_imm(tmp, op & 0xff); |
1644 | goto end_op; |
1645 | case 0x0a00: // XOR #imm,R0 11001010iiiiiiii |
1646 | tmp = rcache_get_reg(SHR_R0, RC_GR_RMW); |
1647 | emith_eor_r_imm(tmp, op & 0xff); |
1648 | goto end_op; |
1649 | case 0x0b00: // OR #imm,R0 11001011iiiiiiii |
1650 | tmp = rcache_get_reg(SHR_R0, RC_GR_RMW); |
1651 | emith_or_r_imm(tmp, op & 0xff); |
1652 | goto end_op; |
1653 | case 0x0c00: // TST.B #imm,@(R0,GBR) 11001100iiiiiiii |
1654 | tmp = emit_indirect_indexed_read(SHR_R0, SHR_GBR, 0); |
1655 | tmp2 = rcache_get_reg(SHR_SR, RC_GR_RMW); |
1656 | emith_bic_r_imm(tmp2, T); |
1657 | emith_tst_r_imm(tmp, op & 0xff); |
1658 | emit_or_t_if_eq(tmp2); |
1659 | rcache_free_tmp(tmp); |
1660 | cycles += 2; |
1661 | goto end_op; |
1662 | case 0x0d00: // AND.B #imm,@(R0,GBR) 11001101iiiiiiii |
1663 | tmp = emit_indirect_indexed_read(SHR_R0, SHR_GBR, 0); |
1664 | emith_and_r_imm(tmp, op & 0xff); |
1665 | emit_indirect_indexed_write(SHR_R0, SHR_GBR, tmp, 0); |
1666 | cycles += 2; |
1667 | goto end_op; |
1668 | case 0x0e00: // XOR.B #imm,@(R0,GBR) 11001110iiiiiiii |
1669 | tmp = emit_indirect_indexed_read(SHR_R0, SHR_GBR, 0); |
1670 | emith_eor_r_imm(tmp, op & 0xff); |
1671 | emit_indirect_indexed_write(SHR_R0, SHR_GBR, tmp, 0); |
1672 | cycles += 2; |
1673 | goto end_op; |
1674 | case 0x0f00: // OR.B #imm,@(R0,GBR) 11001111iiiiiiii |
1675 | tmp = emit_indirect_indexed_read(SHR_R0, SHR_GBR, 0); |
1676 | emith_or_r_imm(tmp, op & 0xff); |
1677 | emit_indirect_indexed_write(SHR_R0, SHR_GBR, tmp, 0); |
1678 | cycles += 2; |
1679 | goto end_op; |
1680 | } |
1681 | goto default_; |
1682 | |
1683 | ///////////////////////////////////////////// |
1684 | case 0x0d: |
1685 | // MOV.L @(disp,PC),Rn 1101nnnndddddddd |
f0d7b1fa |
1686 | rcache_clean(); |
1687 | tmp = rcache_get_tmp_arg(0); |
1688 | emith_move_r_imm(tmp, (pc + (op & 0xff) * 4 + 2) & ~3); |
1689 | tmp = emit_memhandler_read(2); |
1690 | tmp2 = rcache_get_reg(GET_Rn(), RC_GR_WRITE); |
1691 | emith_move_r_r(tmp2, tmp); |
1692 | rcache_free_tmp(tmp); |
1693 | goto end_op; |
52d759c3 |
1694 | |
1695 | ///////////////////////////////////////////// |
1696 | case 0x0e: |
1697 | // MOV #imm,Rn 1110nnnniiiiiiii |
1698 | tmp = rcache_get_reg(GET_Rn(), RC_GR_WRITE); |
1699 | emith_move_r_imm_s8(tmp, op & 0xff); |
1700 | goto end_op; |
1701 | |
679af8a3 |
1702 | default: |
1703 | default_: |
f0d7b1fa |
1704 | elprintf(EL_ANOMALY, "%csh2 drc: unhandled op %04x @ %08x", |
1705 | sh2->is_slave ? 's' : 'm', op, pc - 2); |
1706 | #ifdef DRC_DEBUG_INTERP |
679af8a3 |
1707 | emit_move_r_imm32(SHR_PC, pc - 2); |
c18edb34 |
1708 | rcache_flush(); |
f4bb5d6b |
1709 | emith_pass_arg_r(0, CONTEXT_REG); |
1710 | emith_pass_arg_imm(1, op); |
679af8a3 |
1711 | emith_call(sh2_do_op); |
f0d7b1fa |
1712 | #endif |
679af8a3 |
1713 | break; |
1714 | } |
1715 | |
e898de13 |
1716 | end_op: |
6add7875 |
1717 | if (delayed_op == 1) |
e898de13 |
1718 | emit_move_r_r(SHR_PC, SHR_PPC); |
6add7875 |
1719 | |
e898de13 |
1720 | if (test_irq && delayed_op != 2) { |
f0d7b1fa |
1721 | if (!delayed_op) |
1722 | emit_move_r_imm32(SHR_PC, pc); |
c18edb34 |
1723 | rcache_flush(); |
f4bb5d6b |
1724 | emith_pass_arg_r(0, CONTEXT_REG); |
e898de13 |
1725 | emith_call(sh2_test_irq); |
f0d7b1fa |
1726 | goto end_block_btf; |
e898de13 |
1727 | } |
6add7875 |
1728 | if (delayed_op == 1) |
1729 | break; |
e898de13 |
1730 | |
f4bb5d6b |
1731 | do_host_disasm(tcache_id); |
679af8a3 |
1732 | } |
1733 | |
52d759c3 |
1734 | // delayed_op means some kind of branch - PC already handled |
1735 | if (!delayed_op) |
1736 | emit_move_r_imm32(SHR_PC, pc); |
1737 | |
1738 | end_block_btf: |
f4bb5d6b |
1739 | this_block->end_addr = pc; |
1740 | |
1741 | // mark memory blocks as containing compiled code |
1742 | if ((sh2->pc & 0xe0000000) == 0xc0000000 || (sh2->pc & ~0xfff) == 0) { |
1743 | // data array, BIOS |
1744 | u16 *drcblk = Pico32xMem->drcblk_da[sh2->is_slave]; |
1745 | tmp = (this_block->addr & 0xfff) >> SH2_DRCBLK_DA_SHIFT; |
1746 | tmp2 = (this_block->end_addr & 0xfff) >> SH2_DRCBLK_DA_SHIFT; |
1747 | Pico32xMem->drcblk_da[sh2->is_slave][tmp] = (blkid << 1) | 1; |
1748 | for (++tmp; tmp < tmp2; tmp++) { |
1749 | if (drcblk[tmp]) |
1750 | break; // dont overwrite overlay block |
1751 | drcblk[tmp] = blkid << 1; |
1752 | } |
1753 | } |
1754 | else if ((this_block->addr & 0xc7fc0000) == 0x06000000) { // DRAM |
1755 | tmp = (this_block->addr & 0x3ffff) >> SH2_DRCBLK_RAM_SHIFT; |
1756 | tmp2 = (this_block->end_addr & 0x3ffff) >> SH2_DRCBLK_RAM_SHIFT; |
1757 | Pico32xMem->drcblk_ram[tmp] = (blkid << 1) | 1; |
1758 | for (++tmp; tmp < tmp2; tmp++) { |
1759 | if (Pico32xMem->drcblk_ram[tmp]) |
1760 | break; |
1761 | Pico32xMem->drcblk_ram[tmp] = blkid << 1; |
1762 | } |
679af8a3 |
1763 | } |
1764 | |
c18edb34 |
1765 | tmp = rcache_get_reg(SHR_SR, RC_GR_RMW); |
1766 | emith_sub_r_imm(tmp, cycles << 12); |
1767 | rcache_flush(); |
679af8a3 |
1768 | emith_jump(sh2_drc_exit); |
f4bb5d6b |
1769 | tcache_ptrs[tcache_id] = tcache_ptr; |
1770 | |
553c3eaa |
1771 | #ifdef ARM |
1772 | cache_flush_d_inval_i(block_entry, tcache_ptr); |
1773 | #endif |
1774 | |
f4bb5d6b |
1775 | do_host_disasm(tcache_id); |
1776 | dbg(1, " block #%d,%d tcache %d/%d, insns %d -> %d %.3f", |
1777 | tcache_id, block_counts[tcache_id], |
1778 | tcache_ptr - tcache_bases[tcache_id], tcache_sizes[tcache_id], |
1779 | insns_compiled, host_insn_count, (double)host_insn_count / insns_compiled); |
1780 | if ((sh2->pc & 0xc6000000) == 0x02000000) // ROM |
1781 | dbg(1, " hash collisions %d/%d", hash_collisions, block_counts[tcache_id]); |
553c3eaa |
1782 | #if (DRC_DEBUG & 2) |
1783 | fflush(stdout); |
1784 | #endif |
1785 | |
679af8a3 |
1786 | return block_entry; |
f4bb5d6b |
1787 | /* |
679af8a3 |
1788 | unimplemented: |
1789 | // last op |
f4bb5d6b |
1790 | do_host_disasm(tcache_id); |
679af8a3 |
1791 | exit(1); |
f4bb5d6b |
1792 | */ |
679af8a3 |
1793 | } |
1794 | |
1795 | void __attribute__((noinline)) sh2_drc_dispatcher(SH2 *sh2) |
1796 | { |
52d759c3 |
1797 | // TODO: need to handle self-caused interrupts |
1798 | sh2_test_irq(sh2); |
1799 | |
679af8a3 |
1800 | while (((signed int)sh2->sr >> 12) > 0) |
1801 | { |
679af8a3 |
1802 | void *block = NULL; |
f4bb5d6b |
1803 | block_desc *bd = NULL; |
6add7875 |
1804 | |
1805 | // FIXME: must avoid doing it so often.. |
52d759c3 |
1806 | //sh2_test_irq(sh2); |
6add7875 |
1807 | |
f4bb5d6b |
1808 | // we have full block id tables for data_array and RAM |
1809 | // BIOS goes to data_array table too |
1810 | if ((sh2->pc & 0xff000000) == 0xc0000000 || (sh2->pc & ~0xfff) == 0) { |
1811 | int blkid = Pico32xMem->drcblk_da[sh2->is_slave][(sh2->pc & 0xfff) >> SH2_DRCBLK_DA_SHIFT]; |
1812 | if (blkid & 1) { |
1813 | bd = &block_tables[1 + sh2->is_slave][blkid >> 1]; |
1814 | block = bd->tcache_ptr; |
1815 | } |
1816 | } |
1817 | // RAM |
1818 | else if ((sh2->pc & 0xc6000000) == 0x06000000) { |
1819 | int blkid = Pico32xMem->drcblk_ram[(sh2->pc & 0x3ffff) >> SH2_DRCBLK_RAM_SHIFT]; |
1820 | if (blkid & 1) { |
1821 | bd = &block_tables[0][blkid >> 1]; |
679af8a3 |
1822 | block = bd->tcache_ptr; |
f4bb5d6b |
1823 | } |
1824 | } |
1825 | // ROM |
1826 | else if ((sh2->pc & 0xc6000000) == 0x02000000) { |
1827 | bd = HASH_FUNC(hash_table, sh2->pc); |
1828 | |
1829 | if (bd != NULL) { |
1830 | if (bd->addr == sh2->pc) |
1831 | block = bd->tcache_ptr; |
1832 | else |
1833 | block = dr_find_block(bd, sh2->pc); |
1834 | } |
679af8a3 |
1835 | } |
1836 | |
1837 | if (block == NULL) |
1838 | block = sh2_translate(sh2, bd); |
1839 | |
f4bb5d6b |
1840 | dbg(4, "= %csh2 enter %08x %p, c=%d", sh2->is_slave ? 's' : 'm', |
1841 | sh2->pc, block, (signed int)sh2->sr >> 12); |
1842 | #if (DRC_DEBUG & 1) |
1843 | if (bd != NULL) |
1844 | bd->refcount++; |
679af8a3 |
1845 | #endif |
1846 | sh2_drc_entry(sh2, block); |
1847 | } |
1848 | } |
1849 | |
f4bb5d6b |
1850 | static void sh2_smc_rm_block(u16 *drcblk, u16 *p, block_desc *btab, u32 a) |
1851 | { |
1852 | u16 id = *p >> 1; |
1853 | block_desc *bd = btab + id; |
1854 | |
1855 | dbg(1, " killing block %08x", bd->addr); |
1856 | bd->addr = bd->end_addr = 0; |
1857 | |
1858 | while (p > drcblk && (p[-1] >> 1) == id) |
1859 | p--; |
1860 | |
1861 | // check for possible overlay block |
1862 | if (p > 0 && p[-1] != 0) { |
1863 | bd = btab + (p[-1] >> 1); |
1864 | if (bd->addr <= a && a < bd->end_addr) |
1865 | sh2_smc_rm_block(drcblk, p - 1, btab, a); |
1866 | } |
1867 | |
1868 | do { |
1869 | *p++ = 0; |
1870 | } |
1871 | while ((*p >> 1) == id); |
1872 | } |
1873 | |
1874 | void sh2_drc_wcheck_ram(unsigned int a, int val, int cpuid) |
1875 | { |
1876 | u16 *drcblk = Pico32xMem->drcblk_ram; |
1877 | u16 *p = drcblk + ((a & 0x3ffff) >> SH2_DRCBLK_RAM_SHIFT); |
1878 | |
1879 | dbg(1, "%csh2 smc check @%08x", cpuid ? 's' : 'm', a); |
1880 | sh2_smc_rm_block(drcblk, p, block_tables[0], a); |
1881 | } |
1882 | |
1883 | void sh2_drc_wcheck_da(unsigned int a, int val, int cpuid) |
1884 | { |
1885 | u16 *drcblk = Pico32xMem->drcblk_da[cpuid]; |
1886 | u16 *p = drcblk + ((a & 0xfff) >> SH2_DRCBLK_DA_SHIFT); |
1887 | |
1888 | dbg(1, "%csh2 smc check @%08x", cpuid ? 's' : 'm', a); |
1889 | sh2_smc_rm_block(drcblk, p, block_tables[1 + cpuid], a); |
1890 | } |
1891 | |
52d759c3 |
1892 | void sh2_execute(SH2 *sh2c, int cycles) |
679af8a3 |
1893 | { |
52d759c3 |
1894 | sh2 = sh2c; // XXX |
1895 | |
1896 | sh2c->cycles_aim += cycles; |
1897 | cycles = sh2c->cycles_aim - sh2c->cycles_done; |
679af8a3 |
1898 | |
1899 | // cycles are kept in SHR_SR unused bits (upper 20) |
52d759c3 |
1900 | sh2c->sr &= 0x3f3; |
1901 | sh2c->sr |= cycles << 12; |
1902 | sh2_drc_dispatcher(sh2c); |
679af8a3 |
1903 | |
52d759c3 |
1904 | sh2c->cycles_done += cycles - ((signed int)sh2c->sr >> 12); |
679af8a3 |
1905 | } |
1906 | |
553c3eaa |
1907 | static void REGPARM(1) sh2_test_irq(SH2 *sh2) |
679af8a3 |
1908 | { |
6add7875 |
1909 | if (sh2->pending_level > ((sh2->sr >> 4) & 0x0f)) |
1910 | { |
1911 | if (sh2->pending_irl > sh2->pending_int_irq) |
1912 | sh2_do_irq(sh2, sh2->pending_irl, 64 + sh2->pending_irl/2); |
1913 | else { |
1914 | sh2_do_irq(sh2, sh2->pending_int_irq, sh2->pending_int_vector); |
1915 | sh2->pending_int_irq = 0; // auto-clear |
1916 | sh2->pending_level = sh2->pending_irl; |
1917 | } |
1918 | } |
679af8a3 |
1919 | } |
1920 | |
f4bb5d6b |
1921 | #if (DRC_DEBUG & 1) |
1922 | static void block_stats(void) |
1923 | { |
1924 | int c, b, i, total = 0; |
1925 | |
1926 | for (b = 0; b < ARRAY_SIZE(block_tables); b++) |
1927 | for (i = 0; i < block_counts[b]; i++) |
1928 | if (block_tables[b][i].addr != 0) |
1929 | total += block_tables[b][i].refcount; |
1930 | |
1931 | for (c = 0; c < 10; c++) { |
1932 | block_desc *blk, *maxb = NULL; |
1933 | int max = 0; |
1934 | for (b = 0; b < ARRAY_SIZE(block_tables); b++) { |
1935 | for (i = 0; i < block_counts[b]; i++) { |
1936 | blk = &block_tables[b][i]; |
1937 | if (blk->addr != 0 && blk->refcount > max) { |
1938 | max = blk->refcount; |
1939 | maxb = blk; |
1940 | } |
1941 | } |
1942 | } |
1943 | if (maxb == NULL) |
1944 | break; |
1945 | printf("%08x %9d %2.3f%%\n", maxb->addr, maxb->refcount, |
1946 | (double)maxb->refcount / total * 100.0); |
1947 | maxb->refcount = 0; |
1948 | } |
553c3eaa |
1949 | |
1950 | for (b = 0; b < ARRAY_SIZE(block_tables); b++) |
1951 | for (i = 0; i < block_counts[b]; i++) |
1952 | block_tables[b][i].refcount = 0; |
f4bb5d6b |
1953 | } |
553c3eaa |
1954 | #else |
1955 | #define block_stats() |
f4bb5d6b |
1956 | #endif |
1957 | |
553c3eaa |
1958 | void sh2_drc_flush_all(void) |
1959 | { |
1960 | block_stats(); |
1961 | flush_tcache(0); |
1962 | flush_tcache(1); |
1963 | flush_tcache(2); |
1964 | } |
1965 | |
679af8a3 |
1966 | int sh2_drc_init(SH2 *sh2) |
1967 | { |
f4bb5d6b |
1968 | if (block_tables[0] == NULL) { |
1969 | int i, cnt; |
7f5a3fc1 |
1970 | |
1971 | drc_cmn_init(); |
1972 | |
f4bb5d6b |
1973 | cnt = block_max_counts[0] + block_max_counts[1] + block_max_counts[2]; |
1974 | block_tables[0] = calloc(cnt, sizeof(*block_tables[0])); |
1975 | if (block_tables[0] == NULL) |
e898de13 |
1976 | return -1; |
1977 | |
f4bb5d6b |
1978 | memset(block_counts, 0, sizeof(block_counts)); |
1979 | tcache_bases[0] = tcache_ptrs[0] = tcache; |
1980 | |
1981 | for (i = 1; i < ARRAY_SIZE(block_tables); i++) { |
1982 | block_tables[i] = block_tables[i - 1] + block_max_counts[i - 1]; |
1983 | tcache_bases[i] = tcache_ptrs[i] = tcache_bases[i - 1] + tcache_sizes[i - 1]; |
1984 | } |
1985 | |
553c3eaa |
1986 | // tmp |
1987 | PicoOpt |= POPT_DIS_VDP_FIFO; |
1988 | |
f4bb5d6b |
1989 | #if (DRC_DEBUG & 2) |
1990 | for (i = 0; i < ARRAY_SIZE(block_tables); i++) |
1991 | tcache_dsm_ptrs[i] = tcache_bases[i]; |
1992 | #endif |
e898de13 |
1993 | #if (DRC_DEBUG & 1) |
1994 | hash_collisions = 0; |
1995 | #endif |
679af8a3 |
1996 | } |
1997 | |
f4bb5d6b |
1998 | if (hash_table == NULL) { |
1999 | hash_table = calloc(sizeof(hash_table[0]), MAX_HASH_ENTRIES); |
2000 | if (hash_table == NULL) |
2001 | return -1; |
2002 | } |
41397701 |
2003 | |
679af8a3 |
2004 | return 0; |
41397701 |
2005 | } |
2006 | |
e898de13 |
2007 | void sh2_drc_finish(SH2 *sh2) |
2008 | { |
f4bb5d6b |
2009 | if (block_tables[0] != NULL) { |
f4bb5d6b |
2010 | block_stats(); |
f4bb5d6b |
2011 | free(block_tables[0]); |
2012 | memset(block_tables, 0, sizeof(block_tables)); |
7f5a3fc1 |
2013 | |
2014 | drc_cmn_cleanup(); |
e898de13 |
2015 | } |
2016 | |
f4bb5d6b |
2017 | if (hash_table != NULL) { |
2018 | free(hash_table); |
2019 | hash_table = NULL; |
2020 | } |
e898de13 |
2021 | } |