release 1.92
[picodrive.git] / cpu / sh2 / sh2.h
CommitLineData
41397701 1#ifndef __SH2_H__\r
2#define __SH2_H__\r
3\r
e05b81fc 4#if !defined(REGPARM) && defined(__i386__) \r
5#define REGPARM(x) __attribute__((regparm(x)))\r
6#else\r
7#define REGPARM(x)\r
8#endif\r
9\r
71f68165 10// registers - matches structure order\r
11typedef enum {\r
12 SHR_R0 = 0, SHR_SP = 15,\r
13 SHR_PC, SHR_PPC, SHR_PR, SHR_SR,\r
14 SHR_GBR, SHR_VBR, SHR_MACH, SHR_MACL,\r
15} sh2_reg_e;\r
16\r
e05b81fc 17typedef struct SH2_\r
41397701 18{\r
679af8a3 19 unsigned int r[16]; // 00\r
20 unsigned int pc; // 40\r
41397701 21 unsigned int ppc;\r
41397701 22 unsigned int pr;\r
23 unsigned int sr;\r
679af8a3 24 unsigned int gbr, vbr; // 50\r
25 unsigned int mach, macl; // 58\r
41397701 26\r
bcf65fd6 27 // common\r
f0d7b1fa 28 const void *read8_map; // 60\r
f4bb5d6b 29 const void *read16_map;\r
30 const void **write8_tab;\r
31 const void **write16_tab;\r
bcf65fd6 32\r
679af8a3 33 // drc stuff\r
f0d7b1fa 34 int drc_tmp; // 70\r
e05b81fc 35 int irq_cycles;\r
23686515 36 void *p_bios; // convenience pointers\r
37 void *p_da;\r
04092e32 38 void *p_sdram; // 80\r
23686515 39 void *p_rom;\r
5686d931 40 unsigned int pdb_io_csum[2];\r
f0d7b1fa 41\r
19886062 42#define SH2_STATE_RUN (1 << 0) // to prevent recursion\r
43#define SH2_STATE_SLEEP (1 << 1)\r
44#define SH2_STATE_CPOLL (1 << 2) // polling comm regs\r
45#define SH2_STATE_VPOLL (1 << 3) // polling VDP\r
46 unsigned int state;\r
47 unsigned int poll_addr;\r
48 int poll_cycles;\r
49 int poll_cnt;\r
50\r
f0d7b1fa 51 // interpreter stuff\r
52 int icount; // cycles left in current timeslice\r
53 unsigned int ea;\r
54 unsigned int delay;\r
55 unsigned int test_irq;\r
679af8a3 56\r
6add7875 57 int pending_level; // MAX(pending_irl, pending_int_irq)\r
41397701 58 int pending_irl;\r
59 int pending_int_irq; // internal irq\r
60 int pending_int_vector;\r
e05b81fc 61 int REGPARM(2) (*irq_callback)(struct SH2_ *sh2, int level);\r
41397701 62 int is_slave;\r
63\r
ed4402a7 64 unsigned int cycles_timeslice;\r
65\r
f81107f5 66 struct SH2_ *other_sh2;\r
67\r
ed4402a7 68 // we use 68k reference cycles for easier sync\r
69 unsigned int m68krcycles_done;\r
70 unsigned int mult_m68k_to_sh2;\r
71 unsigned int mult_sh2_to_m68k;\r
f81107f5 72\r
73 unsigned char data_array[0x1000]; // cache (can be used as RAM)\r
74 unsigned int peri_regs[0x200/4]; // periphereal regs\r
41397701 75} SH2;\r
76\r
ed4402a7 77#define CYCLE_MULT_SHIFT 10\r
78#define C_M68K_TO_SH2(xsh2, c) \\r
79 ((int)((c) * (xsh2).mult_m68k_to_sh2) >> CYCLE_MULT_SHIFT)\r
80#define C_SH2_TO_M68K(xsh2, c) \\r
81 ((int)((c + 3) * (xsh2).mult_sh2_to_m68k) >> CYCLE_MULT_SHIFT)\r
82\r
f81107f5 83int sh2_init(SH2 *sh2, int is_slave, SH2 *other_sh2);\r
e898de13 84void sh2_finish(SH2 *sh2);\r
41397701 85void sh2_reset(SH2 *sh2);\r
a8fd6e37 86int sh2_irl_irq(SH2 *sh2, int level, int nested_call);\r
41397701 87void sh2_internal_irq(SH2 *sh2, int level, int vector);\r
6add7875 88void sh2_do_irq(SH2 *sh2, int level, int vector);\r
b4db550e 89void sh2_pack(const SH2 *sh2, unsigned char *buff);\r
90void sh2_unpack(SH2 *sh2, const unsigned char *buff);\r
41397701 91\r
0185b677 92int sh2_execute_drc(SH2 *sh2c, int cycles);\r
93int sh2_execute_interpreter(SH2 *sh2c, int cycles);\r
94\r
95static inline int sh2_execute(SH2 *sh2, int cycles, int use_drc)\r
96{\r
97 int ret;\r
98\r
99 sh2->cycles_timeslice = cycles;\r
100#ifdef DRC_SH2\r
101 if (use_drc)\r
102 ret = sh2_execute_drc(sh2, cycles);\r
103 else\r
104#endif\r
105 ret = sh2_execute_interpreter(sh2, cycles);\r
106\r
107 return sh2->cycles_timeslice - ret;\r
108}\r
41397701 109\r
b4db550e 110// regs, pending_int*, cycles, reserved\r
111#define SH2_STATE_SIZE ((24 + 2 + 2 + 12) * 4)\r
112\r
bcf65fd6 113// pico memhandlers\r
114// XXX: move somewhere else\r
80599a42 115unsigned int REGPARM(2) p32x_sh2_read8(unsigned int a, SH2 *sh2);\r
116unsigned int REGPARM(2) p32x_sh2_read16(unsigned int a, SH2 *sh2);\r
117unsigned int REGPARM(2) p32x_sh2_read32(unsigned int a, SH2 *sh2);\r
f81107f5 118void REGPARM(3) p32x_sh2_write8 (unsigned int a, unsigned int d, SH2 *sh2);\r
119void REGPARM(3) p32x_sh2_write16(unsigned int a, unsigned int d, SH2 *sh2);\r
120void REGPARM(3) p32x_sh2_write32(unsigned int a, unsigned int d, SH2 *sh2);\r
bcf65fd6 121\r
00faec9c 122// debug\r
123#ifdef DRC_CMP\r
124void do_sh2_trace(SH2 *current, int cycles);\r
125void do_sh2_cmp(SH2 *current);\r
126#endif\r
127\r
41397701 128#endif /* __SH2_H__ */\r