platform ps2, handle audio similar to psp

[picodrive.git] / cpu / sh2 / sh2.h

#ifndef __SH2_H__\r
#define __SH2_H__\r
\r
#include <pico/pico_types.h>\r
#include <pico/pico_port.h>\r
\r
// registers - matches structure order\r
typedef enum {\r
  SHR_R0 = 0, SHR_SP = 15,\r
  SHR_PC,  SHR_PPC, SHR_PR,   SHR_SR,\r
  SHR_GBR, SHR_VBR, SHR_MACH, SHR_MACL,\r
  SH2_REGS, // register set size\r
  SHR_T = 29, SHR_MEM = 30, SHR_TMP = 31, // drc specific pseudo regs\r
} sh2_reg_e;\r
#define	SHR_R(n)	(SHR_R0+(n))\r
\r
typedef struct SH2_\r
{\r
	// registers. this MUST correlate with enum sh2_reg_e.\r
	uint32_t	r[16] ALIGNED(32);\r
	uint32_t	pc;		// 40\r
	uint32_t	ppc;\r
	uint32_t	pr;\r
	uint32_t	sr;\r
	uint32_t	gbr, vbr;	// 50\r
	uint32_t	mach, macl;	// 58\r
\r
	// common\r
	const void	*read8_map;\r
	const void	*read16_map;\r
	const void	*read32_map;\r
	const void	**write8_tab;\r
	const void	**write16_tab;\r
	const void	**write32_tab;\r
\r
	// drc stuff\r
	int		drc_tmp;\r
	int		irq_cycles;\r
	void		*p_bios;	// convenience pointers\r
	void		*p_da;\r
	void		*p_sdram;\r
	void		*p_rom;\r
	void		*p_dram;\r
	void		*p_drcblk_da;\r
	void		*p_drcblk_ram;\r
	unsigned int	pdb_io_csum[2];\r
\r
#define SH2_STATE_RUN   (1 << 0)	// to prevent recursion\r
#define SH2_STATE_SLEEP (1 << 1)	// temporarily stopped (DMA, IO, ...)\r
#define SH2_STATE_CPOLL (1 << 2)	// polling comm regs\r
#define SH2_STATE_VPOLL (1 << 3)	// polling VDP\r
#define SH2_STATE_RPOLL (1 << 4)	// polling address in SDRAM\r
#define SH2_TIMER_RUN   (1 << 6)	// SOC WDT timer is running\r
#define SH2_IN_DRC      (1 << 7)	// DRC in use\r
	unsigned int	state;\r
	uint32_t	poll_addr;\r
	unsigned int	poll_cycles;\r
	int		poll_cnt;\r
// NB MUST be a bit unused in SH2 SR, see also cpu/sh2/compiler.c!\r
#define SH2_NO_POLLING	(1 << 10)	// poll detection control\r
	int		no_polling;\r
\r
	// DRC branch cache. size must be 2^n and <=128\r
	int rts_cache_idx;\r
	struct { uint32_t pc; void *code; } rts_cache[16];\r
	struct { uint32_t pc; void *code; } branch_cache[128];\r
\r
	// interpreter stuff\r
	int		icount;		// cycles left in current timeslice\r
	unsigned int	ea;\r
	unsigned int	delay;\r
	unsigned int	test_irq;\r
\r
	int	pending_level;		// MAX(pending_irl, pending_int_irq)\r
	int	pending_irl;\r
	int	pending_int_irq;	// internal irq\r
	int	pending_int_vector;\r
	int	REGPARM(2) (*irq_callback)(struct SH2_ *sh2, int level);\r
	int	is_slave;\r
\r
	unsigned int	cycles_timeslice;\r
\r
	struct SH2_	*other_sh2;\r
	int		(*run)(struct SH2_ *, int);\r
\r
	// we use 68k reference cycles for easier sync\r
	unsigned int	m68krcycles_done;\r
	unsigned int	mult_m68k_to_sh2;\r
	unsigned int	mult_sh2_to_m68k;\r
\r
	uint8_t		data_array[0x1000]; // cache (can be used as RAM)\r
	uint32_t	peri_regs[0x200/4]; // peripheral regs\r
} SH2;\r
\r
#define CYCLE_MULT_SHIFT 10\r
#define C_M68K_TO_SH2(xsh2, c) \\r
	(int)(((uint64_t)(c) * (xsh2)->mult_m68k_to_sh2) >> CYCLE_MULT_SHIFT)\r
#define C_SH2_TO_M68K(xsh2, c) \\r
	(int)(((uint64_t)(c+3U) * (xsh2)->mult_sh2_to_m68k) >> CYCLE_MULT_SHIFT)\r
\r
int  sh2_init(SH2 *sh2, int is_slave, SH2 *other_sh2);\r
void sh2_finish(SH2 *sh2);\r
void sh2_reset(SH2 *sh2);\r
int  sh2_irl_irq(SH2 *sh2, int level, int nested_call);\r
void sh2_internal_irq(SH2 *sh2, int level, int vector);\r
void sh2_do_irq(SH2 *sh2, int level, int vector);\r
void sh2_pack(const SH2 *sh2, unsigned char *buff);\r
void sh2_unpack(SH2 *sh2, const unsigned char *buff);\r
\r
int  sh2_execute_drc(SH2 *sh2c, int cycles);\r
int  sh2_execute_interpreter(SH2 *sh2c, int cycles);\r
\r
static __inline void sh2_execute_prepare(SH2 *sh2, int use_drc)\r
{\r
#ifdef DRC_SH2\r
  sh2->run = use_drc ? sh2_execute_drc : sh2_execute_interpreter;\r
#else\r
  sh2->run = sh2_execute_interpreter;\r
#endif\r
}\r
\r
static __inline int sh2_execute(SH2 *sh2, int cycles)\r
{\r
  int ret;\r
\r
  sh2->cycles_timeslice = cycles;\r
  ret = sh2->run(sh2, cycles);\r
\r
  return sh2->cycles_timeslice - ret;\r
}\r
\r
// regs, pending_int*, cycles, reserved\r
#define SH2_STATE_SIZE ((24 + 2 + 2 + 12) * 4)\r
\r
// pico memhandlers\r
// XXX: move somewhere else\r
u32 REGPARM(2) p32x_sh2_read8(u32 a, SH2 *sh2);\r
u32 REGPARM(2) p32x_sh2_read16(u32 a, SH2 *sh2);\r
u32 REGPARM(2) p32x_sh2_read32(u32 a, SH2 *sh2);\r
void REGPARM(3) p32x_sh2_write8 (u32 a, u32 d, SH2 *sh2);\r
void REGPARM(3) p32x_sh2_write16(u32 a, u32 d, SH2 *sh2);\r
void REGPARM(3) p32x_sh2_write32(u32 a, u32 d, SH2 *sh2);\r
\r
// debug\r
#ifdef DRC_CMP\r
void do_sh2_trace(SH2 *current, int cycles);\r
void REGPARM(1) do_sh2_cmp(SH2 *current);\r
#endif\r
\r
#endif /* __SH2_H__ */\r