drc: rm write irq check
[picodrive.git] / cpu / sh2 / sh2.h
CommitLineData
41397701 1#ifndef __SH2_H__\r
2#define __SH2_H__\r
3\r
e05b81fc 4#if !defined(REGPARM) && defined(__i386__) \r
5#define REGPARM(x) __attribute__((regparm(x)))\r
6#else\r
7#define REGPARM(x)\r
8#endif\r
9\r
71f68165 10// registers - matches structure order\r
11typedef enum {\r
12 SHR_R0 = 0, SHR_SP = 15,\r
13 SHR_PC, SHR_PPC, SHR_PR, SHR_SR,\r
14 SHR_GBR, SHR_VBR, SHR_MACH, SHR_MACL,\r
15} sh2_reg_e;\r
16\r
e05b81fc 17typedef struct SH2_\r
41397701 18{\r
679af8a3 19 unsigned int r[16]; // 00\r
20 unsigned int pc; // 40\r
41397701 21 unsigned int ppc;\r
41397701 22 unsigned int pr;\r
23 unsigned int sr;\r
679af8a3 24 unsigned int gbr, vbr; // 50\r
25 unsigned int mach, macl; // 58\r
41397701 26\r
bcf65fd6 27 // common\r
f0d7b1fa 28 const void *read8_map; // 60\r
f4bb5d6b 29 const void *read16_map;\r
30 const void **write8_tab;\r
31 const void **write16_tab;\r
bcf65fd6 32\r
679af8a3 33 // drc stuff\r
f0d7b1fa 34 int drc_tmp; // 70\r
e05b81fc 35 int irq_cycles;\r
23686515 36 void *p_bios; // convenience pointers\r
37 void *p_da;\r
04092e32 38 void *p_sdram; // 80\r
23686515 39 void *p_rom;\r
5686d931 40 unsigned int pdb_io_csum[2];\r
f0d7b1fa 41\r
42 // interpreter stuff\r
43 int icount; // cycles left in current timeslice\r
44 unsigned int ea;\r
45 unsigned int delay;\r
46 unsigned int test_irq;\r
679af8a3 47\r
6add7875 48 int pending_level; // MAX(pending_irl, pending_int_irq)\r
41397701 49 int pending_irl;\r
50 int pending_int_irq; // internal irq\r
51 int pending_int_vector;\r
e05b81fc 52 int REGPARM(2) (*irq_callback)(struct SH2_ *sh2, int level);\r
41397701 53 int is_slave;\r
54\r
ed4402a7 55 unsigned int cycles_timeslice;\r
56\r
57 // we use 68k reference cycles for easier sync\r
58 unsigned int m68krcycles_done;\r
59 unsigned int mult_m68k_to_sh2;\r
60 unsigned int mult_sh2_to_m68k;\r
41397701 61} SH2;\r
62\r
ed4402a7 63#define CYCLE_MULT_SHIFT 10\r
64#define C_M68K_TO_SH2(xsh2, c) \\r
65 ((int)((c) * (xsh2).mult_m68k_to_sh2) >> CYCLE_MULT_SHIFT)\r
66#define C_SH2_TO_M68K(xsh2, c) \\r
67 ((int)((c + 3) * (xsh2).mult_sh2_to_m68k) >> CYCLE_MULT_SHIFT)\r
68\r
679af8a3 69int sh2_init(SH2 *sh2, int is_slave);\r
e898de13 70void sh2_finish(SH2 *sh2);\r
41397701 71void sh2_reset(SH2 *sh2);\r
a8fd6e37 72int sh2_irl_irq(SH2 *sh2, int level, int nested_call);\r
41397701 73void sh2_internal_irq(SH2 *sh2, int level, int vector);\r
6add7875 74void sh2_do_irq(SH2 *sh2, int level, int vector);\r
b4db550e 75void sh2_pack(const SH2 *sh2, unsigned char *buff);\r
76void sh2_unpack(SH2 *sh2, const unsigned char *buff);\r
41397701 77\r
ed4402a7 78int sh2_execute(SH2 *sh2, int cycles);\r
41397701 79\r
b4db550e 80// regs, pending_int*, cycles, reserved\r
81#define SH2_STATE_SIZE ((24 + 2 + 2 + 12) * 4)\r
82\r
bcf65fd6 83// pico memhandlers\r
84// XXX: move somewhere else\r
80599a42 85unsigned int REGPARM(2) p32x_sh2_read8(unsigned int a, SH2 *sh2);\r
86unsigned int REGPARM(2) p32x_sh2_read16(unsigned int a, SH2 *sh2);\r
87unsigned int REGPARM(2) p32x_sh2_read32(unsigned int a, SH2 *sh2);\r
e05b81fc 88int REGPARM(3) p32x_sh2_write8 (unsigned int a, unsigned int d, SH2 *sh2);\r
89int REGPARM(3) p32x_sh2_write16(unsigned int a, unsigned int d, SH2 *sh2);\r
90int REGPARM(3) p32x_sh2_write32(unsigned int a, unsigned int d, SH2 *sh2);\r
bcf65fd6 91\r
00faec9c 92// debug\r
93#ifdef DRC_CMP\r
94void do_sh2_trace(SH2 *current, int cycles);\r
95void do_sh2_cmp(SH2 *current);\r
96#endif\r
97\r
41397701 98#endif /* __SH2_H__ */\r