[picodrive.git] / cpu / sh2 / sh2.h

#ifndef __SH2_H__\r
#define __SH2_H__\r
\r
#if !defined(REGPARM) && defined(__i386__) \r
#define REGPARM(x) __attribute__((regparm(x)))\r
#else\r
#define REGPARM(x)\r
#endif\r
\r
// registers - matches structure order\r
typedef enum {\r
  SHR_R0 = 0, SHR_SP = 15,\r
  SHR_PC,  SHR_PPC, SHR_PR,   SHR_SR,\r
  SHR_GBR, SHR_VBR, SHR_MACH, SHR_MACL,\r
} sh2_reg_e;\r
\r
typedef struct SH2_\r
{\r
	unsigned int	r[16];		// 00\r
	unsigned int	pc;		// 40\r
	unsigned int	ppc;\r
	unsigned int	pr;\r
	unsigned int	sr;\r
	unsigned int	gbr, vbr;	// 50\r
	unsigned int	mach, macl;	// 58\r
\r
	// common\r
	const void	*read8_map;	// 60\r
	const void	*read16_map;\r
	const void	**write8_tab;\r
	const void	**write16_tab;\r
\r
	// drc stuff\r
	int		drc_tmp;	// 70\r
	int		irq_cycles;\r
	void		*p_bios;	// convenience pointers\r
	void		*p_da;\r
	void		*p_sdram;	// 80\r
	void		*p_rom;\r
	unsigned int	pdb_io_csum[2];\r
\r
#define SH2_STATE_RUN   (1 << 0)	// to prevent recursion\r
#define SH2_STATE_SLEEP (1 << 1)\r
#define SH2_STATE_CPOLL (1 << 2)	// polling comm regs\r
#define SH2_STATE_VPOLL (1 << 3)	// polling VDP\r
	unsigned int	state;\r
	unsigned int	poll_addr;\r
	int		poll_cycles;\r
	int		poll_cnt;\r
\r
	// interpreter stuff\r
	int		icount;		// cycles left in current timeslice\r
	unsigned int	ea;\r
	unsigned int	delay;\r
	unsigned int	test_irq;\r
\r
	int	pending_level;		// MAX(pending_irl, pending_int_irq)\r
	int	pending_irl;\r
	int	pending_int_irq;	// internal irq\r
	int	pending_int_vector;\r
	int	REGPARM(2) (*irq_callback)(struct SH2_ *sh2, int level);\r
	int	is_slave;\r
\r
	unsigned int	cycles_timeslice;\r
\r
	// we use 68k reference cycles for easier sync\r
	unsigned int	m68krcycles_done;\r
	unsigned int	mult_m68k_to_sh2;\r
	unsigned int	mult_sh2_to_m68k;\r
} SH2;\r
\r
#define CYCLE_MULT_SHIFT 10\r
#define C_M68K_TO_SH2(xsh2, c) \\r
	((int)((c) * (xsh2).mult_m68k_to_sh2) >> CYCLE_MULT_SHIFT)\r
#define C_SH2_TO_M68K(xsh2, c) \\r
	((int)((c + 3) * (xsh2).mult_sh2_to_m68k) >> CYCLE_MULT_SHIFT)\r
\r
int  sh2_init(SH2 *sh2, int is_slave);\r
void sh2_finish(SH2 *sh2);\r
void sh2_reset(SH2 *sh2);\r
int  sh2_irl_irq(SH2 *sh2, int level, int nested_call);\r
void sh2_internal_irq(SH2 *sh2, int level, int vector);\r
void sh2_do_irq(SH2 *sh2, int level, int vector);\r
void sh2_pack(const SH2 *sh2, unsigned char *buff);\r
void sh2_unpack(SH2 *sh2, const unsigned char *buff);\r
\r
int  sh2_execute(SH2 *sh2, int cycles);\r
\r
// regs, pending_int*, cycles, reserved\r
#define SH2_STATE_SIZE ((24 + 2 + 2 + 12) * 4)\r
\r
// pico memhandlers\r
// XXX: move somewhere else\r
unsigned int REGPARM(2) p32x_sh2_read8(unsigned int a, SH2 *sh2);\r
unsigned int REGPARM(2) p32x_sh2_read16(unsigned int a, SH2 *sh2);\r
unsigned int REGPARM(2) p32x_sh2_read32(unsigned int a, SH2 *sh2);\r
int REGPARM(3) p32x_sh2_write8 (unsigned int a, unsigned int d, SH2 *sh2);\r
int REGPARM(3) p32x_sh2_write16(unsigned int a, unsigned int d, SH2 *sh2);\r
int REGPARM(3) p32x_sh2_write32(unsigned int a, unsigned int d, SH2 *sh2);\r
\r
// debug\r
#ifdef DRC_CMP\r
void do_sh2_trace(SH2 *current, int cycles);\r
void do_sh2_cmp(SH2 *current);\r
#endif\r
\r
#endif /* __SH2_H__ */\r
Commit	Line	Data
41397701	1	#ifndef __SH2_H__\r
	2	#define __SH2_H__\r
	3	\r
e05b81fc	4	#if !defined(REGPARM) && defined(__i386__) \r
	5	#define REGPARM(x) __attribute__((regparm(x)))\r
	6	#else\r
	7	#define REGPARM(x)\r
	8	#endif\r
	9	\r
71f68165	10	// registers - matches structure order\r
	11	typedef enum {\r
	12	SHR_R0 = 0, SHR_SP = 15,\r
	13	SHR_PC, SHR_PPC, SHR_PR, SHR_SR,\r
	14	SHR_GBR, SHR_VBR, SHR_MACH, SHR_MACL,\r
	15	} sh2_reg_e;\r
	16	\r
e05b81fc	17	typedef struct SH2_\r
41397701	18	{\r
679af8a3	19	unsigned int r[16]; // 00\r
679af8a3	20	unsigned int pc; // 40\r
41397701	21	unsigned int ppc;\r
41397701	22	unsigned int pr;\r
41397701	23	unsigned int sr;\r
679af8a3	24	unsigned int gbr, vbr; // 50\r
679af8a3	25	unsigned int mach, macl; // 58\r
41397701	26	\r
bcf65fd6	27	// common\r
f0d7b1fa	28	const void *read8_map; // 60\r
f4bb5d6b	29	const void *read16_map;\r
	30	const void **write8_tab;\r
	31	const void **write16_tab;\r
bcf65fd6	32	\r
679af8a3	33	// drc stuff\r
f0d7b1fa	34	int drc_tmp; // 70\r
e05b81fc	35	int irq_cycles;\r
23686515	36	void *p_bios; // convenience pointers\r
23686515	37	void *p_da;\r
04092e32	38	void *p_sdram; // 80\r
23686515	39	void *p_rom;\r
5686d931	40	unsigned int pdb_io_csum[2];\r
f0d7b1fa	41	\r
19886062	42	#define SH2_STATE_RUN (1 << 0) // to prevent recursion\r
	43	#define SH2_STATE_SLEEP (1 << 1)\r
	44	#define SH2_STATE_CPOLL (1 << 2) // polling comm regs\r
	45	#define SH2_STATE_VPOLL (1 << 3) // polling VDP\r
	46	unsigned int state;\r
	47	unsigned int poll_addr;\r
	48	int poll_cycles;\r
	49	int poll_cnt;\r
	50	\r
f0d7b1fa	51	// interpreter stuff\r
	52	int icount; // cycles left in current timeslice\r
	53	unsigned int ea;\r
	54	unsigned int delay;\r
	55	unsigned int test_irq;\r
679af8a3	56	\r
6add7875	57	int pending_level; // MAX(pending_irl, pending_int_irq)\r
41397701	58	int pending_irl;\r
	59	int pending_int_irq; // internal irq\r
	60	int pending_int_vector;\r
e05b81fc	61	int REGPARM(2) (irq_callback)(struct SH2_ sh2, int level);\r
41397701	62	int is_slave;\r
41397701	63	\r
ed4402a7	64	unsigned int cycles_timeslice;\r
	65	\r
	66	// we use 68k reference cycles for easier sync\r
	67	unsigned int m68krcycles_done;\r
	68	unsigned int mult_m68k_to_sh2;\r
	69	unsigned int mult_sh2_to_m68k;\r
41397701	70	} SH2;\r
41397701	71	\r
ed4402a7	72	#define CYCLE_MULT_SHIFT 10\r
	73	#define C_M68K_TO_SH2(xsh2, c) \\r
	74	((int)((c) * (xsh2).mult_m68k_to_sh2) >> CYCLE_MULT_SHIFT)\r
	75	#define C_SH2_TO_M68K(xsh2, c) \\r
	76	((int)((c + 3) * (xsh2).mult_sh2_to_m68k) >> CYCLE_MULT_SHIFT)\r
	77	\r
679af8a3	78	int sh2_init(SH2 *sh2, int is_slave);\r
e898de13	79	void sh2_finish(SH2 *sh2);\r
41397701	80	void sh2_reset(SH2 *sh2);\r
a8fd6e37	81	int sh2_irl_irq(SH2 *sh2, int level, int nested_call);\r
41397701	82	void sh2_internal_irq(SH2 *sh2, int level, int vector);\r
6add7875	83	void sh2_do_irq(SH2 *sh2, int level, int vector);\r
b4db550e	84	void sh2_pack(const SH2 sh2, unsigned char buff);\r
b4db550e	85	void sh2_unpack(SH2 sh2, const unsigned char buff);\r
41397701	86	\r
ed4402a7	87	int sh2_execute(SH2 *sh2, int cycles);\r
41397701	88	\r
b4db550e	89	// regs, pending_int*, cycles, reserved\r
	90	#define SH2_STATE_SIZE ((24 + 2 + 2 + 12) * 4)\r
	91	\r
bcf65fd6	92	// pico memhandlers\r
bcf65fd6	93	// XXX: move somewhere else\r
80599a42	94	unsigned int REGPARM(2) p32x_sh2_read8(unsigned int a, SH2 *sh2);\r
	95	unsigned int REGPARM(2) p32x_sh2_read16(unsigned int a, SH2 *sh2);\r
	96	unsigned int REGPARM(2) p32x_sh2_read32(unsigned int a, SH2 *sh2);\r
e05b81fc	97	int REGPARM(3) p32x_sh2_write8 (unsigned int a, unsigned int d, SH2 *sh2);\r
	98	int REGPARM(3) p32x_sh2_write16(unsigned int a, unsigned int d, SH2 *sh2);\r
	99	int REGPARM(3) p32x_sh2_write32(unsigned int a, unsigned int d, SH2 *sh2);\r
bcf65fd6	100	\r
00faec9c	101	// debug\r
	102	#ifdef DRC_CMP\r
	103	void do_sh2_trace(SH2 *current, int cycles);\r
	104	void do_sh2_cmp(SH2 *current);\r
	105	#endif\r
	106	\r
41397701	107	#endif /* __SH2_H__ */\r