[picodrive.git] / cpu / sh2 / sh2.h

#ifndef __SH2_H__\r
#define __SH2_H__\r
\r
#if !defined(REGPARM) && defined(__i386__) \r
#define REGPARM(x) __attribute__((regparm(x)))\r
#else\r
#define REGPARM(x)\r
#endif\r
\r
// registers - matches structure order\r
typedef enum {\r
  SHR_R0 = 0, SHR_SP = 15,\r
  SHR_PC,  SHR_PPC, SHR_PR,   SHR_SR,\r
  SHR_GBR, SHR_VBR, SHR_MACH, SHR_MACL,\r
} sh2_reg_e;\r
\r
typedef struct SH2_\r
{\r
	unsigned int	r[16];		// 00\r
	unsigned int	pc;		// 40\r
	unsigned int	ppc;\r
	unsigned int	pr;\r
	unsigned int	sr;\r
	unsigned int	gbr, vbr;	// 50\r
	unsigned int	mach, macl;	// 58\r
\r
	// common\r
	const void	*read8_map;	// 60\r
	const void	*read16_map;\r
	const void	**write8_tab;\r
	const void	**write16_tab;\r
\r
	// drc stuff\r
	int		drc_tmp;	// 70\r
	int		irq_cycles;\r
\r
	// interpreter stuff\r
	int		icount;		// cycles left in current timeslice\r
	unsigned int	ea;\r
	unsigned int	delay;\r
	unsigned int	test_irq;\r
\r
	int	pending_level;		// MAX(pending_irl, pending_int_irq)\r
	int	pending_irl;\r
	int	pending_int_irq;	// internal irq\r
	int	pending_int_vector;\r
	int	REGPARM(2) (*irq_callback)(struct SH2_ *sh2, int level);\r
	int	is_slave;\r
\r
	unsigned int	cycles_aim;	// subtract sh2_icount to get global counter\r
	unsigned int	cycles_done;\r
} SH2;\r
\r
extern SH2 *sh2; // active sh2. XXX: consider removing\r
\r
int  sh2_init(SH2 *sh2, int is_slave);\r
void sh2_finish(SH2 *sh2);\r
void sh2_reset(SH2 *sh2);\r
void sh2_irl_irq(SH2 *sh2, int level);\r
void sh2_internal_irq(SH2 *sh2, int level, int vector);\r
void sh2_do_irq(SH2 *sh2, int level, int vector);\r
\r
void sh2_execute(SH2 *sh2, int cycles);\r
\r
// pico memhandlers\r
// XXX: move somewhere else\r
unsigned int REGPARM(2) p32x_sh2_read8(unsigned int a, SH2 *sh2);\r
unsigned int REGPARM(2) p32x_sh2_read16(unsigned int a, SH2 *sh2);\r
unsigned int REGPARM(2) p32x_sh2_read32(unsigned int a, SH2 *sh2);\r
int REGPARM(3) p32x_sh2_write8 (unsigned int a, unsigned int d, SH2 *sh2);\r
int REGPARM(3) p32x_sh2_write16(unsigned int a, unsigned int d, SH2 *sh2);\r
int REGPARM(3) p32x_sh2_write32(unsigned int a, unsigned int d, SH2 *sh2);\r
\r
#endif /* __SH2_H__ */\r
Commit	Line	Data
41397701	1	#ifndef __SH2_H__\r
	2	#define __SH2_H__\r
	3	\r
e05b81fc	4	#if !defined(REGPARM) && defined(__i386__) \r
	5	#define REGPARM(x) __attribute__((regparm(x)))\r
	6	#else\r
	7	#define REGPARM(x)\r
	8	#endif\r
	9	\r
71f68165	10	// registers - matches structure order\r
	11	typedef enum {\r
	12	SHR_R0 = 0, SHR_SP = 15,\r
	13	SHR_PC, SHR_PPC, SHR_PR, SHR_SR,\r
	14	SHR_GBR, SHR_VBR, SHR_MACH, SHR_MACL,\r
	15	} sh2_reg_e;\r
	16	\r
e05b81fc	17	typedef struct SH2_\r
41397701	18	{\r
679af8a3	19	unsigned int r[16]; // 00\r
679af8a3	20	unsigned int pc; // 40\r
41397701	21	unsigned int ppc;\r
41397701	22	unsigned int pr;\r
41397701	23	unsigned int sr;\r
679af8a3	24	unsigned int gbr, vbr; // 50\r
679af8a3	25	unsigned int mach, macl; // 58\r
41397701	26	\r
bcf65fd6	27	// common\r
f0d7b1fa	28	const void *read8_map; // 60\r
f4bb5d6b	29	const void *read16_map;\r
	30	const void **write8_tab;\r
	31	const void **write16_tab;\r
bcf65fd6	32	\r
679af8a3	33	// drc stuff\r
f0d7b1fa	34	int drc_tmp; // 70\r
e05b81fc	35	int irq_cycles;\r
f0d7b1fa	36	\r
	37	// interpreter stuff\r
	38	int icount; // cycles left in current timeslice\r
	39	unsigned int ea;\r
	40	unsigned int delay;\r
	41	unsigned int test_irq;\r
679af8a3	42	\r
6add7875	43	int pending_level; // MAX(pending_irl, pending_int_irq)\r
41397701	44	int pending_irl;\r
	45	int pending_int_irq; // internal irq\r
	46	int pending_int_vector;\r
e05b81fc	47	int REGPARM(2) (irq_callback)(struct SH2_ sh2, int level);\r
41397701	48	int is_slave;\r
41397701	49	\r
41397701	50	unsigned int cycles_aim; // subtract sh2_icount to get global counter\r
	51	unsigned int cycles_done;\r
	52	} SH2;\r
	53	\r
f0d7b1fa	54	extern SH2 *sh2; // active sh2. XXX: consider removing\r
41397701	55	\r
679af8a3	56	int sh2_init(SH2 *sh2, int is_slave);\r
e898de13	57	void sh2_finish(SH2 *sh2);\r
41397701	58	void sh2_reset(SH2 *sh2);\r
	59	void sh2_irl_irq(SH2 *sh2, int level);\r
	60	void sh2_internal_irq(SH2 *sh2, int level, int vector);\r
6add7875	61	void sh2_do_irq(SH2 *sh2, int level, int vector);\r
41397701	62	\r
	63	void sh2_execute(SH2 *sh2, int cycles);\r
	64	\r
bcf65fd6	65	// pico memhandlers\r
bcf65fd6	66	// XXX: move somewhere else\r
80599a42	67	unsigned int REGPARM(2) p32x_sh2_read8(unsigned int a, SH2 *sh2);\r
	68	unsigned int REGPARM(2) p32x_sh2_read16(unsigned int a, SH2 *sh2);\r
	69	unsigned int REGPARM(2) p32x_sh2_read32(unsigned int a, SH2 *sh2);\r
e05b81fc	70	int REGPARM(3) p32x_sh2_write8 (unsigned int a, unsigned int d, SH2 *sh2);\r
	71	int REGPARM(3) p32x_sh2_write16(unsigned int a, unsigned int d, SH2 *sh2);\r
	72	int REGPARM(3) p32x_sh2_write32(unsigned int a, unsigned int d, SH2 *sh2);\r
bcf65fd6	73	\r
41397701	74	#endif /* __SH2_H__ */\r