be2c4208 |
1 | #include "../pico_int.h" |
2 | #include "../memory.h" |
3 | |
4 | static const char str_mars[] = "MARS"; |
5 | |
974fdb5b |
6 | struct Pico32xMem *Pico32xMem; |
7 | |
5e49c3a8 |
8 | static void bank_switch(int b); |
9 | |
acd35d4c |
10 | #define MSB8(x) ((x) >> 8) |
11 | |
266c6afa |
12 | // poll detection |
4ea707e1 |
13 | #define POLL_THRESHOLD 6 |
14 | |
266c6afa |
15 | struct poll_det { |
b78efee2 |
16 | int addr, pc, cnt, flag; |
266c6afa |
17 | }; |
b78efee2 |
18 | static struct poll_det m68k_poll, sh2_poll[2]; |
266c6afa |
19 | |
b78efee2 |
20 | static int p32x_poll_detect(struct poll_det *pd, u32 a, u32 pc, int is_vdp) |
266c6afa |
21 | { |
b78efee2 |
22 | int ret = 0, flag = pd->flag; |
23 | |
24 | if (is_vdp) |
25 | flag <<= 3; |
266c6afa |
26 | |
27 | if (a - 2 <= pd->addr && pd->addr <= a + 2 && pd->pc == pc) { |
28 | pd->cnt++; |
29 | if (pd->cnt > POLL_THRESHOLD) { |
30 | if (!(Pico32x.emu_flags & flag)) { |
31 | elprintf(EL_32X, "%s poll addr %08x @ %06x", |
32 | flag == P32XF_68KPOLL ? "m68k" : (flag == P32XF_MSH2POLL ? "msh2" : "ssh2"), a, pc); |
33 | ret = 1; |
34 | } |
35 | Pico32x.emu_flags |= flag; |
36 | } |
37 | } |
38 | else |
39 | pd->cnt = 0; |
40 | pd->addr = a; |
41 | pd->pc = pc; |
42 | |
43 | return ret; |
44 | } |
45 | |
b78efee2 |
46 | static int p32x_poll_undetect(struct poll_det *pd, int is_vdp) |
266c6afa |
47 | { |
b78efee2 |
48 | int ret = 0, flag = pd->flag; |
49 | if (is_vdp) |
50 | flag <<= 3; |
266c6afa |
51 | if (pd->cnt > POLL_THRESHOLD) |
52 | ret = 1; |
53 | pd->addr = pd->cnt = 0; |
54 | Pico32x.emu_flags &= ~flag; |
55 | return ret; |
56 | } |
57 | |
4ea707e1 |
58 | void p32x_poll_event(int is_vdp) |
59 | { |
b78efee2 |
60 | p32x_poll_undetect(&sh2_poll[0], is_vdp); |
61 | p32x_poll_undetect(&sh2_poll[1], is_vdp); |
4ea707e1 |
62 | } |
63 | |
974fdb5b |
64 | // SH2 faking |
b78efee2 |
65 | //#define FAKE_SH2 |
acd35d4c |
66 | int p32x_csum_faked; |
67 | #ifdef FAKE_SH2 |
974fdb5b |
68 | static const u16 comm_fakevals[] = { |
69 | 0x4d5f, 0x4f4b, // M_OK |
70 | 0x535f, 0x4f4b, // S_OK |
5e49c3a8 |
71 | 0x4D41, 0x5346, // MASF - Brutal Unleashed |
72 | 0x5331, 0x4d31, // Darxide |
73 | 0x5332, 0x4d32, |
74 | 0x5333, 0x4d33, |
75 | 0x0000, 0x0000, // eq for doom |
974fdb5b |
76 | 0x0002, // Mortal Kombat |
acd35d4c |
77 | // 0, // pad |
be2c4208 |
78 | }; |
acd35d4c |
79 | |
80 | static u32 sh2_comm_faker(u32 a) |
81 | { |
82 | static int f = 0; |
83 | if (a == 0x28 && !p32x_csum_faked) { |
84 | p32x_csum_faked = 1; |
85 | return *(unsigned short *)(Pico.rom + 0x18e); |
86 | } |
87 | if (f >= sizeof(comm_fakevals) / sizeof(comm_fakevals[0])) |
88 | f = 0; |
89 | return comm_fakevals[f++]; |
90 | } |
91 | #endif |
be2c4208 |
92 | |
4ea707e1 |
93 | // DMAC handling |
94 | static struct { |
95 | unsigned int sar0, dar0, tcr0; // src addr, dst addr, transfer count |
96 | unsigned int chcr0; // chan ctl |
97 | unsigned int sar1, dar1, tcr1; // same for chan 1 |
98 | unsigned int chcr1; |
99 | int pad[4]; |
100 | unsigned int dmaor; |
101 | } * dmac0; |
102 | |
103 | static void dma_68k2sh2_do(void) |
104 | { |
105 | unsigned short *dreqlen = &Pico32x.regs[0x10 / 2]; |
106 | int i; |
107 | |
108 | if (dmac0->tcr0 != *dreqlen) |
109 | elprintf(EL_32X|EL_ANOMALY, "tcr0 and dreq len differ: %d != %d", dmac0->tcr0, *dreqlen); |
110 | |
111 | for (i = 0; i < Pico32x.dmac_ptr && dmac0->tcr0 > 0; i++) { |
b78efee2 |
112 | extern void p32x_sh2_write16(u32 a, u32 d, int id); |
4ea707e1 |
113 | elprintf(EL_32X|EL_ANOMALY, "dmaw [%08x] %04x, left %d", dmac0->dar0, Pico32x.dmac_fifo[i], *dreqlen); |
b78efee2 |
114 | p32x_sh2_write16(dmac0->dar0, Pico32x.dmac_fifo[i], 0); |
4ea707e1 |
115 | dmac0->dar0 += 2; |
116 | dmac0->tcr0--; |
117 | (*dreqlen)--; |
118 | } |
119 | |
120 | Pico32x.dmac_ptr = 0; // HACK |
121 | Pico32x.regs[6 / 2] &= ~P32XS_FULL; |
122 | if (*dreqlen == 0) |
123 | Pico32x.regs[6 / 2] &= ~P32XS_68S; // transfer complete |
124 | if (dmac0->tcr0 == 0) |
125 | dmac0->chcr0 |= 2; // DMA has ended normally |
4ea707e1 |
126 | } |
127 | |
128 | // ------------------------------------------------------------------ |
b78efee2 |
129 | // 68k regs |
4ea707e1 |
130 | |
be2c4208 |
131 | static u32 p32x_reg_read16(u32 a) |
132 | { |
133 | a &= 0x3e; |
134 | |
3cf9570b |
135 | #if 0 |
974fdb5b |
136 | if ((a & 0x30) == 0x20) |
acd35d4c |
137 | return sh2_comm_faker(a); |
266c6afa |
138 | #else |
db1d3564 |
139 | if ((a & 0x30) == 0x20 && p32x_poll_detect(&m68k_poll, a, SekPc, 0)) { |
266c6afa |
140 | SekEndRun(16); |
141 | } |
acd35d4c |
142 | #endif |
3cf9570b |
143 | #ifdef FAKE_SH2 |
144 | // fake only slave for now |
145 | if (a == 0x24 || a == 0x26) |
146 | return sh2_comm_faker(a); |
147 | #endif |
db1d3564 |
148 | if ((a & 0x30) == 0x30) |
149 | return p32x_pwm_read16(a); |
974fdb5b |
150 | |
be2c4208 |
151 | return Pico32x.regs[a / 2]; |
152 | } |
153 | |
be2c4208 |
154 | static void p32x_reg_write8(u32 a, u32 d) |
155 | { |
acd35d4c |
156 | u16 *r = Pico32x.regs; |
be2c4208 |
157 | a &= 0x3f; |
158 | |
97d3f47f |
159 | // for things like bset on comm port |
160 | m68k_poll.cnt = 0; |
161 | |
acd35d4c |
162 | if (a == 1 && !(r[0] & 1)) { |
163 | r[0] |= 1; |
be2c4208 |
164 | Pico32xStartup(); |
165 | return; |
166 | } |
5e49c3a8 |
167 | |
acd35d4c |
168 | if (!(r[0] & 1)) |
5e49c3a8 |
169 | return; |
170 | |
acd35d4c |
171 | switch (a) { |
4ea707e1 |
172 | case 0: // adapter ctl |
acd35d4c |
173 | r[0] = (r[0] & 0x83) | ((d << 8) & P32XS_FM); |
174 | break; |
4ea707e1 |
175 | case 3: // irq ctl |
176 | if ((d & 1) && !(Pico32x.sh2irqi[0] & P32XI_CMD)) { |
177 | Pico32x.sh2irqi[0] |= P32XI_CMD; |
178 | p32x_update_irls(); |
179 | } |
b78efee2 |
180 | if ((d & 2) && !(Pico32x.sh2irqi[1] & P32XI_CMD)) { |
181 | Pico32x.sh2irqi[1] |= P32XI_CMD; |
182 | p32x_update_irls(); |
183 | } |
4ea707e1 |
184 | break; |
185 | case 5: // bank |
acd35d4c |
186 | d &= 7; |
4ea707e1 |
187 | if (r[4 / 2] != d) { |
188 | r[4 / 2] = d; |
acd35d4c |
189 | bank_switch(d); |
190 | } |
191 | break; |
4ea707e1 |
192 | case 7: // DREQ ctl |
97d3f47f |
193 | r[6 / 2] = (r[6 / 2] & P32XS_FULL) | (d & (P32XS_68S|P32XS_DMA|P32XS_RV)); |
4ea707e1 |
194 | break; |
5e49c3a8 |
195 | } |
196 | } |
197 | |
198 | static void p32x_reg_write16(u32 a, u32 d) |
199 | { |
acd35d4c |
200 | u16 *r = Pico32x.regs; |
201 | a &= 0x3e; |
202 | |
97d3f47f |
203 | // for things like bset on comm port |
204 | m68k_poll.cnt = 0; |
205 | |
acd35d4c |
206 | switch (a) { |
4ea707e1 |
207 | case 0x00: // adapter ctl |
acd35d4c |
208 | r[0] = (r[0] & 0x83) | (d & P32XS_FM); |
209 | return; |
4ea707e1 |
210 | case 0x10: // DREQ len |
211 | r[a / 2] = d & ~3; |
212 | return; |
213 | case 0x12: // FIFO reg |
214 | if (!(r[6 / 2] & P32XS_68S)) { |
215 | elprintf(EL_32X|EL_ANOMALY, "DREQ FIFO w16 without 68S?"); |
216 | return; |
217 | } |
218 | if (Pico32x.dmac_ptr < DMAC_FIFO_LEN) { |
219 | Pico32x.dmac_fifo[Pico32x.dmac_ptr++] = d; |
220 | if ((Pico32x.dmac_ptr & 3) == 0 && (dmac0->chcr0 & 3) == 1 && (dmac0->dmaor & 1)) |
221 | dma_68k2sh2_do(); |
222 | if (Pico32x.dmac_ptr == DMAC_FIFO_LEN) |
223 | r[6 / 2] |= P32XS_FULL; |
224 | } |
225 | break; |
acd35d4c |
226 | } |
227 | |
4ea707e1 |
228 | // DREQ src, dst |
229 | if ((a & 0x38) == 0x08) { |
230 | r[a / 2] = d; |
231 | return; |
232 | } |
233 | // comm port |
234 | else if ((a & 0x30) == 0x20 && r[a / 2] != d) { |
acd35d4c |
235 | r[a / 2] = d; |
b78efee2 |
236 | if (p32x_poll_undetect(&sh2_poll[0], 0) || p32x_poll_undetect(&sh2_poll[1], 0)) |
237 | // if some SH2 is busy waiting, it needs to see the result ASAP |
3cf9570b |
238 | SekEndRun(16); |
acd35d4c |
239 | return; |
240 | } |
db1d3564 |
241 | // PWM |
242 | else if ((a & 0x30) == 0x30) { |
243 | p32x_pwm_write16(a, d); |
244 | return; |
245 | } |
acd35d4c |
246 | |
5e49c3a8 |
247 | p32x_reg_write8(a + 1, d); |
be2c4208 |
248 | } |
249 | |
4ea707e1 |
250 | // ------------------------------------------------------------------ |
be2c4208 |
251 | // VDP regs |
252 | static u32 p32x_vdp_read16(u32 a) |
253 | { |
254 | a &= 0x0e; |
255 | |
256 | return Pico32x.vdp_regs[a / 2]; |
257 | } |
258 | |
be2c4208 |
259 | static void p32x_vdp_write8(u32 a, u32 d) |
260 | { |
974fdb5b |
261 | u16 *r = Pico32x.vdp_regs; |
be2c4208 |
262 | a &= 0x0f; |
263 | |
4ea707e1 |
264 | // for FEN checks between writes |
b78efee2 |
265 | sh2_poll[0].cnt = 0; |
4ea707e1 |
266 | |
974fdb5b |
267 | // TODO: verify what's writeable |
be2c4208 |
268 | switch (a) { |
974fdb5b |
269 | case 0x01: |
5e49c3a8 |
270 | // priority inversion is handled in palette |
271 | if ((r[0] ^ d) & P32XV_PRI) |
272 | Pico32x.dirty_pal = 1; |
974fdb5b |
273 | r[0] = (r[0] & P32XV_nPAL) | (d & 0xff); |
274 | break; |
be2c4208 |
275 | case 0x0b: |
974fdb5b |
276 | d &= 1; |
277 | Pico32x.pending_fb = d; |
278 | // if we are blanking and FS bit is changing |
4ea707e1 |
279 | if (((r[0x0a/2] & P32XV_VBLK) || (r[0] & P32XV_Mx) == 0) && ((r[0x0a/2] ^ d) & P32XV_FS)) { |
974fdb5b |
280 | r[0x0a/2] ^= 1; |
281 | Pico32xSwapDRAM(d ^ 1); |
266c6afa |
282 | elprintf(EL_32X, "VDP FS: %d", r[0x0a/2] & P32XV_FS); |
be2c4208 |
283 | } |
284 | break; |
285 | } |
286 | } |
287 | |
974fdb5b |
288 | static void p32x_vdp_write16(u32 a, u32 d) |
289 | { |
290 | p32x_vdp_write8(a | 1, d); |
291 | } |
292 | |
4ea707e1 |
293 | // ------------------------------------------------------------------ |
acd35d4c |
294 | // SH2 regs |
b78efee2 |
295 | |
296 | static u32 p32x_sh2reg_read16(u32 a, int cpuid) |
acd35d4c |
297 | { |
4ea707e1 |
298 | u16 *r = Pico32x.regs; |
299 | a &= 0xfe; // ? |
266c6afa |
300 | |
4ea707e1 |
301 | switch (a) { |
302 | case 0x00: // adapter/irq ctl |
b78efee2 |
303 | return (r[0] & P32XS_FM) | P32XS2_ADEN | Pico32x.sh2irq_mask[cpuid]; |
4ea707e1 |
304 | case 0x10: // DREQ len |
305 | return r[a / 2]; |
acd35d4c |
306 | } |
4ea707e1 |
307 | |
db1d3564 |
308 | // DREQ src, dst |
309 | if ((a & 0x38) == 0x08) |
4ea707e1 |
310 | return r[a / 2]; |
db1d3564 |
311 | // comm port |
312 | if ((a & 0x30) == 0x20) { |
313 | if (p32x_poll_detect(&sh2_poll[cpuid], a, sh2_pc(cpuid), 0)) |
314 | ash2_end_run(8); |
315 | return r[a / 2]; |
316 | } |
317 | if ((a & 0x30) == 0x30) { |
318 | sh2_poll[cpuid].cnt = 0; |
319 | return p32x_pwm_read16(a); |
320 | } |
acd35d4c |
321 | |
322 | return 0; |
323 | } |
324 | |
b78efee2 |
325 | static void p32x_sh2reg_write8(u32 a, u32 d, int cpuid) |
acd35d4c |
326 | { |
4ea707e1 |
327 | a &= 0xff; |
328 | if (a == 1) { |
b78efee2 |
329 | Pico32x.sh2irq_mask[cpuid] = d & 0x0f; |
4ea707e1 |
330 | p32x_update_irls(); |
331 | } |
acd35d4c |
332 | } |
333 | |
b78efee2 |
334 | static void p32x_sh2reg_write16(u32 a, u32 d, int cpuid) |
acd35d4c |
335 | { |
4ea707e1 |
336 | a &= 0xfe; |
acd35d4c |
337 | |
db1d3564 |
338 | // comm |
4ea707e1 |
339 | if ((a & 0x30) == 0x20 && Pico32x.regs[a/2] != d) { |
b78efee2 |
340 | Pico32x.regs[a / 2] = d; |
341 | p32x_poll_undetect(&m68k_poll, 0); |
342 | p32x_poll_undetect(&sh2_poll[cpuid ^ 1], 0); |
acd35d4c |
343 | return; |
344 | } |
db1d3564 |
345 | // PWM |
346 | else if ((a & 0x30) == 0x30) { |
347 | p32x_pwm_write16(a, d); |
348 | return; |
349 | } |
acd35d4c |
350 | |
4ea707e1 |
351 | switch (a) { |
352 | case 0x14: Pico32x.sh2irqs &= ~P32XI_VRES; goto irls; |
353 | case 0x16: Pico32x.sh2irqs &= ~P32XI_VINT; goto irls; |
354 | case 0x18: Pico32x.sh2irqs &= ~P32XI_HINT; goto irls; |
b78efee2 |
355 | case 0x1a: Pico32x.sh2irqi[cpuid] &= ~P32XI_CMD; goto irls; |
4ea707e1 |
356 | case 0x1c: Pico32x.sh2irqs &= ~P32XI_PWM; goto irls; |
357 | } |
358 | |
b78efee2 |
359 | p32x_sh2reg_write8(a | 1, d, cpuid); |
4ea707e1 |
360 | return; |
361 | |
362 | irls: |
363 | p32x_update_irls(); |
364 | } |
365 | |
b78efee2 |
366 | static u32 sh2_peripheral_read(u32 a, int id) |
4ea707e1 |
367 | { |
368 | u32 d; |
369 | a &= 0x1fc; |
97d3f47f |
370 | d = Pico32xMem->sh2_peri_regs[id][a / 4]; |
4ea707e1 |
371 | |
97d3f47f |
372 | elprintf(EL_32X, "%csh2 peri r32 [%08x] %08x @%06x", id ? 's' : 'm', a | ~0x1ff, d, sh2_pc(id)); |
4ea707e1 |
373 | return d; |
acd35d4c |
374 | } |
375 | |
b78efee2 |
376 | static void sh2_peripheral_write(u32 a, u32 d, int id) |
4ea707e1 |
377 | { |
97d3f47f |
378 | unsigned int *r = Pico32xMem->sh2_peri_regs[id]; |
b78efee2 |
379 | elprintf(EL_32X, "%csh2 peri w32 [%08x] %08x @%06x", id ? 's' : 'm', a, d, sh2_pc(id)); |
4ea707e1 |
380 | |
381 | a &= 0x1fc; |
382 | r[a / 4] = d; |
383 | |
97d3f47f |
384 | switch (a) { |
385 | // division unit: |
386 | case 0x104: // DVDNT: divident L, starts divide |
387 | elprintf(EL_32X, "%csh2 divide %08x / %08x", id ? 's' : 'm', d, r[0x100 / 4]); |
388 | if (r[0x100 / 4]) { |
389 | r[0x118 / 4] = r[0x110 / 4] = d % r[0x100 / 4]; |
390 | r[0x11c / 4] = r[0x114 / 4] = d / r[0x100 / 4]; |
391 | } |
392 | break; |
393 | case 0x114: |
394 | elprintf(EL_32X, "%csh2 divide %08x%08x / %08x @%08x", |
395 | id ? 's' : 'm', r[0x110 / 4], d, r[0x100 / 4], sh2_pc(id)); |
396 | if (r[0x100 / 4]) { |
397 | long long divident = (long long)r[0x110 / 4] << 32 | d; |
398 | // XXX: undocumented mirroring to 0x118,0x11c? |
399 | r[0x118 / 4] = r[0x110 / 4] = divident % r[0x100 / 4]; |
400 | r[0x11c / 4] = r[0x114 / 4] = divident / r[0x100 / 4]; |
401 | } |
402 | break; |
403 | } |
404 | |
4ea707e1 |
405 | if ((a == 0x1b0 || a == 0x18c) && (dmac0->chcr0 & 3) == 1 && (dmac0->dmaor & 1)) { |
406 | elprintf(EL_32X, "sh2 DMA %08x -> %08x, cnt %d, chcr %04x @%06x", |
b78efee2 |
407 | dmac0->sar0, dmac0->dar0, dmac0->tcr0, dmac0->chcr0, sh2_pc(id)); |
4ea707e1 |
408 | dmac0->tcr0 &= 0xffffff; |
409 | // DREQ is only sent after first 4 words are written. |
410 | // we do multiple of 4 words to avoid messing up alignment |
411 | if (dmac0->sar0 == 0x20004012 && Pico32x.dmac_ptr && (Pico32x.dmac_ptr & 3) == 0) { |
412 | elprintf(EL_32X, "68k -> sh2 DMA"); |
413 | dma_68k2sh2_do(); |
414 | } |
415 | } |
416 | } |
417 | |
418 | // ------------------------------------------------------------------ |
be2c4208 |
419 | // default 32x handlers |
420 | u32 PicoRead8_32x(u32 a) |
421 | { |
422 | u32 d = 0; |
423 | if ((a & 0xffc0) == 0x5100) { // a15100 |
424 | d = p32x_reg_read16(a); |
425 | goto out_16to8; |
426 | } |
427 | |
974fdb5b |
428 | if (!(Pico32x.regs[0] & 1)) |
429 | goto no_vdp; |
430 | |
431 | if ((a & 0xfff0) == 0x5180) { // a15180 |
be2c4208 |
432 | d = p32x_vdp_read16(a); |
433 | goto out_16to8; |
434 | } |
435 | |
974fdb5b |
436 | if ((a & 0xfe00) == 0x5200) { // a15200 |
437 | d = Pico32xMem->pal[(a & 0x1ff) / 2]; |
438 | goto out_16to8; |
439 | } |
440 | |
441 | no_vdp: |
be2c4208 |
442 | if ((a & 0xfffc) == 0x30ec) { // a130ec |
443 | d = str_mars[a & 3]; |
444 | goto out; |
445 | } |
446 | |
447 | elprintf(EL_UIO, "m68k unmapped r8 [%06x] @%06x", a, SekPc); |
448 | return d; |
449 | |
450 | out_16to8: |
451 | if (a & 1) |
452 | d &= 0xff; |
453 | else |
454 | d >>= 8; |
455 | |
456 | out: |
457 | elprintf(EL_32X, "m68k 32x r8 [%06x] %02x @%06x", a, d, SekPc); |
458 | return d; |
459 | } |
460 | |
461 | u32 PicoRead16_32x(u32 a) |
462 | { |
463 | u32 d = 0; |
464 | if ((a & 0xffc0) == 0x5100) { // a15100 |
465 | d = p32x_reg_read16(a); |
466 | goto out; |
467 | } |
468 | |
974fdb5b |
469 | if (!(Pico32x.regs[0] & 1)) |
470 | goto no_vdp; |
471 | |
472 | if ((a & 0xfff0) == 0x5180) { // a15180 |
be2c4208 |
473 | d = p32x_vdp_read16(a); |
474 | goto out; |
475 | } |
476 | |
974fdb5b |
477 | if ((a & 0xfe00) == 0x5200) { // a15200 |
478 | d = Pico32xMem->pal[(a & 0x1ff) / 2]; |
479 | goto out; |
480 | } |
481 | |
482 | no_vdp: |
be2c4208 |
483 | if ((a & 0xfffc) == 0x30ec) { // a130ec |
484 | d = !(a & 2) ? ('M'<<8)|'A' : ('R'<<8)|'S'; |
485 | goto out; |
486 | } |
487 | |
488 | elprintf(EL_UIO, "m68k unmapped r16 [%06x] @%06x", a, SekPc); |
489 | return d; |
490 | |
491 | out: |
492 | elprintf(EL_32X, "m68k 32x r16 [%06x] %04x @%06x", a, d, SekPc); |
493 | return d; |
494 | } |
495 | |
496 | void PicoWrite8_32x(u32 a, u32 d) |
497 | { |
498 | if ((a & 0xfc00) == 0x5000) |
499 | elprintf(EL_32X, "m68k 32x w8 [%06x] %02x @%06x", a, d & 0xff, SekPc); |
500 | |
501 | if ((a & 0xffc0) == 0x5100) { // a15100 |
502 | p32x_reg_write8(a, d); |
503 | return; |
504 | } |
505 | |
974fdb5b |
506 | if (!(Pico32x.regs[0] & 1)) |
507 | goto no_vdp; |
508 | |
509 | if ((a & 0xfff0) == 0x5180) { // a15180 |
be2c4208 |
510 | p32x_vdp_write8(a, d); |
511 | return; |
512 | } |
513 | |
974fdb5b |
514 | // TODO: verify |
515 | if ((a & 0xfe00) == 0x5200) { // a15200 |
516 | elprintf(EL_32X|EL_ANOMALY, "m68k 32x PAL w8 [%06x] %02x @%06x", a, d & 0xff, SekPc); |
517 | ((u8 *)Pico32xMem->pal)[(a & 0x1ff) ^ 1] = d; |
518 | Pico32x.dirty_pal = 1; |
519 | return; |
520 | } |
521 | |
522 | no_vdp: |
be2c4208 |
523 | elprintf(EL_UIO, "m68k unmapped w8 [%06x] %02x @%06x", a, d & 0xff, SekPc); |
524 | } |
525 | |
526 | void PicoWrite16_32x(u32 a, u32 d) |
527 | { |
528 | if ((a & 0xfc00) == 0x5000) |
529 | elprintf(EL_UIO, "m68k 32x w16 [%06x] %04x @%06x", a, d & 0xffff, SekPc); |
530 | |
531 | if ((a & 0xffc0) == 0x5100) { // a15100 |
532 | p32x_reg_write16(a, d); |
533 | return; |
534 | } |
535 | |
974fdb5b |
536 | if (!(Pico32x.regs[0] & 1)) |
537 | goto no_vdp; |
538 | |
539 | if ((a & 0xfff0) == 0x5180) { // a15180 |
be2c4208 |
540 | p32x_vdp_write16(a, d); |
541 | return; |
542 | } |
543 | |
974fdb5b |
544 | if ((a & 0xfe00) == 0x5200) { // a15200 |
545 | Pico32xMem->pal[(a & 0x1ff) / 2] = d; |
546 | Pico32x.dirty_pal = 1; |
547 | return; |
548 | } |
549 | |
550 | no_vdp: |
be2c4208 |
551 | elprintf(EL_UIO, "m68k unmapped w16 [%06x] %04x @%06x", a, d & 0xffff, SekPc); |
552 | } |
553 | |
554 | // hint vector is writeable |
555 | static void PicoWrite8_hint(u32 a, u32 d) |
556 | { |
557 | if ((a & 0xfffc) == 0x0070) { |
558 | Pico32xMem->m68k_rom[a ^ 1] = d; |
559 | return; |
560 | } |
561 | |
562 | elprintf(EL_UIO, "m68k unmapped w8 [%06x] %02x @%06x", a, d & 0xff, SekPc); |
563 | } |
564 | |
565 | static void PicoWrite16_hint(u32 a, u32 d) |
566 | { |
567 | if ((a & 0xfffc) == 0x0070) { |
568 | ((u16 *)Pico32xMem->m68k_rom)[a/2] = d; |
569 | return; |
570 | } |
571 | |
572 | elprintf(EL_UIO, "m68k unmapped w16 [%06x] %04x @%06x", a, d & 0xffff, SekPc); |
573 | } |
574 | |
974fdb5b |
575 | void Pico32xSwapDRAM(int b) |
576 | { |
577 | cpu68k_map_set(m68k_read8_map, 0x840000, 0x85ffff, Pico32xMem->dram[b], 0); |
578 | cpu68k_map_set(m68k_read16_map, 0x840000, 0x85ffff, Pico32xMem->dram[b], 0); |
579 | cpu68k_map_set(m68k_write8_map, 0x840000, 0x85ffff, Pico32xMem->dram[b], 0); |
580 | cpu68k_map_set(m68k_write16_map, 0x840000, 0x85ffff, Pico32xMem->dram[b], 0); |
581 | } |
582 | |
5e49c3a8 |
583 | static void bank_switch(int b) |
584 | { |
585 | unsigned int rs, bank; |
586 | |
587 | bank = b << 20; |
588 | if (bank >= Pico.romsize) { |
589 | elprintf(EL_32X|EL_ANOMALY, "missing bank @ %06x", bank); |
590 | return; |
591 | } |
592 | |
593 | // 32X ROM (unbanked, XXX: consider mirroring?) |
594 | rs = (Pico.romsize + M68K_BANK_MASK) & ~M68K_BANK_MASK; |
595 | rs -= bank; |
596 | if (rs > 0x100000) |
597 | rs = 0x100000; |
598 | cpu68k_map_set(m68k_read8_map, 0x900000, 0x900000 + rs - 1, Pico.rom + bank, 0); |
599 | cpu68k_map_set(m68k_read16_map, 0x900000, 0x900000 + rs - 1, Pico.rom + bank, 0); |
600 | |
601 | elprintf(EL_32X, "bank %06x-%06x -> %06x", 0x900000, 0x900000 + rs - 1, bank); |
602 | } |
603 | |
acd35d4c |
604 | // ----------------------------------------------------------------- |
605 | // SH2 |
606 | // ----------------------------------------------------------------- |
607 | |
b78efee2 |
608 | u32 p32x_sh2_read8(u32 a, int id) |
acd35d4c |
609 | { |
610 | u32 d = 0; |
4ea707e1 |
611 | |
b78efee2 |
612 | if (id == 0 && a < sizeof(Pico32xMem->sh2_rom_m)) |
acd35d4c |
613 | return Pico32xMem->sh2_rom_m[a ^ 1]; |
b78efee2 |
614 | if (id == 1 && a < sizeof(Pico32xMem->sh2_rom_s)) |
615 | return Pico32xMem->sh2_rom_s[a ^ 1]; |
acd35d4c |
616 | |
617 | if ((a & 0x0ffc0000) == 0x06000000) |
618 | return Pico32xMem->sdram[(a & 0x3ffff) ^ 1]; |
619 | |
620 | if ((a & 0x0fc00000) == 0x02000000) |
621 | if ((a & 0x003fffff) < Pico.romsize) |
622 | return Pico.rom[(a & 0x3fffff) ^ 1]; |
623 | |
b78efee2 |
624 | if ((a & ~0xfff) == 0xc0000000) |
625 | return Pico32xMem->data_array[id][(a & 0xfff) ^ 1]; |
626 | |
97d3f47f |
627 | if ((a & 0x0ffe0000) == 0x04000000) { |
628 | u8 *dram = (u8 *)Pico32xMem->dram[(Pico32x.vdp_regs[0x0a/2] & P32XV_FS) ^ 1]; |
629 | return dram[(a & 0x1ffff) ^ 1]; |
630 | } |
631 | |
acd35d4c |
632 | if ((a & 0x0fffff00) == 0x4000) { |
b78efee2 |
633 | d = p32x_sh2reg_read16(a, id); |
db1d3564 |
634 | goto out_16to8; |
acd35d4c |
635 | } |
636 | |
637 | if ((a & 0x0fffff00) == 0x4100) { |
638 | d = p32x_vdp_read16(a); |
db1d3564 |
639 | if (p32x_poll_detect(&sh2_poll[id], a, sh2_pc(id), 1)) |
640 | ash2_end_run(8); |
641 | goto out_16to8; |
acd35d4c |
642 | } |
643 | |
644 | if ((a & 0x0fffff00) == 0x4200) { |
645 | d = Pico32xMem->pal[(a & 0x1ff) / 2]; |
646 | goto out_16to8; |
647 | } |
648 | |
b78efee2 |
649 | elprintf(EL_UIO, "%csh2 unmapped r8 [%08x] %02x @%06x", |
650 | id ? 's' : 'm', a, d, sh2_pc(id)); |
acd35d4c |
651 | return d; |
652 | |
653 | out_16to8: |
654 | if (a & 1) |
655 | d &= 0xff; |
656 | else |
657 | d >>= 8; |
658 | |
b78efee2 |
659 | elprintf(EL_32X, "%csh2 r8 [%08x] %02x @%06x", |
660 | id ? 's' : 'm', a, d, sh2_pc(id)); |
acd35d4c |
661 | return d; |
662 | } |
663 | |
b78efee2 |
664 | u32 p32x_sh2_read16(u32 a, int id) |
acd35d4c |
665 | { |
666 | u32 d = 0; |
3cf9570b |
667 | |
b78efee2 |
668 | if (id == 0 && a < sizeof(Pico32xMem->sh2_rom_m)) |
acd35d4c |
669 | return *(u16 *)(Pico32xMem->sh2_rom_m + a); |
b78efee2 |
670 | if (id == 1 && a < sizeof(Pico32xMem->sh2_rom_s)) |
671 | return *(u16 *)(Pico32xMem->sh2_rom_s + a); |
acd35d4c |
672 | |
673 | if ((a & 0x0ffc0000) == 0x06000000) |
674 | return ((u16 *)Pico32xMem->sdram)[(a & 0x3ffff) / 2]; |
675 | |
676 | if ((a & 0x0fc00000) == 0x02000000) |
677 | if ((a & 0x003fffff) < Pico.romsize) |
678 | return ((u16 *)Pico.rom)[(a & 0x3fffff) / 2]; |
679 | |
b78efee2 |
680 | if ((a & ~0xfff) == 0xc0000000) |
681 | return ((u16 *)Pico32xMem->data_array[id])[(a & 0xfff) / 2]; |
682 | |
97d3f47f |
683 | if ((a & 0x0ffe0000) == 0x04000000) |
684 | return Pico32xMem->dram[(Pico32x.vdp_regs[0x0a/2] & P32XV_FS) ^ 1][(a & 0x1ffff) / 2]; |
685 | |
acd35d4c |
686 | if ((a & 0x0fffff00) == 0x4000) { |
b78efee2 |
687 | d = p32x_sh2reg_read16(a, id); |
db1d3564 |
688 | goto out; |
acd35d4c |
689 | } |
690 | |
691 | if ((a & 0x0fffff00) == 0x4100) { |
692 | d = p32x_vdp_read16(a); |
db1d3564 |
693 | if (p32x_poll_detect(&sh2_poll[id], a, sh2_pc(id), 1)) |
694 | ash2_end_run(8); |
695 | goto out; |
acd35d4c |
696 | } |
697 | |
698 | if ((a & 0x0fffff00) == 0x4200) { |
699 | d = Pico32xMem->pal[(a & 0x1ff) / 2]; |
700 | goto out; |
701 | } |
702 | |
b78efee2 |
703 | elprintf(EL_UIO, "%csh2 unmapped r16 [%08x] %04x @%06x", |
704 | id ? 's' : 'm', a, d, sh2_pc(id)); |
acd35d4c |
705 | return d; |
706 | |
707 | out: |
b78efee2 |
708 | elprintf(EL_32X, "%csh2 r16 [%08x] %04x @%06x", |
709 | id ? 's' : 'm', a, d, sh2_pc(id)); |
acd35d4c |
710 | return d; |
711 | } |
712 | |
b78efee2 |
713 | u32 p32x_sh2_read32(u32 a, int id) |
acd35d4c |
714 | { |
4ea707e1 |
715 | if ((a & 0xfffffe00) == 0xfffffe00) |
b78efee2 |
716 | return sh2_peripheral_read(a, id); |
4ea707e1 |
717 | |
acd35d4c |
718 | // elprintf(EL_UIO, "sh2 r32 [%08x] %08x @%06x", a, d, ash2_pc()); |
b78efee2 |
719 | return (p32x_sh2_read16(a, id) << 16) | p32x_sh2_read16(a + 2, id); |
acd35d4c |
720 | } |
721 | |
b78efee2 |
722 | void p32x_sh2_write8(u32 a, u32 d, int id) |
acd35d4c |
723 | { |
724 | if ((a & 0x0ffffc00) == 0x4000) |
b78efee2 |
725 | elprintf(EL_32X, "%csh2 w8 [%08x] %02x @%06x", |
726 | id ? 's' : 'm', a, d & 0xff, sh2_pc(id)); |
acd35d4c |
727 | |
728 | if ((a & 0x0ffc0000) == 0x06000000) { |
729 | Pico32xMem->sdram[(a & 0x3ffff) ^ 1] = d; |
730 | return; |
731 | } |
732 | |
266c6afa |
733 | if ((a & 0x0ffe0000) == 0x04000000) { |
734 | u8 *dram = (u8 *)Pico32xMem->dram[(Pico32x.vdp_regs[0x0a/2] & P32XV_FS) ^ 1]; |
735 | dram[(a & 0x1ffff) ^ 1] = d; |
736 | return; |
737 | } |
738 | |
b78efee2 |
739 | if ((a & ~0xfff) == 0xc0000000) { |
740 | Pico32xMem->data_array[id][(a & 0xfff) ^ 1] = d; |
741 | return; |
742 | } |
743 | |
acd35d4c |
744 | if ((a & 0x0fffff00) == 0x4100) { |
745 | p32x_vdp_write8(a, d); |
746 | return; |
747 | } |
748 | |
749 | if ((a & 0x0fffff00) == 0x4000) { |
b78efee2 |
750 | p32x_sh2reg_write8(a, d, id); |
acd35d4c |
751 | return; |
752 | } |
753 | |
b78efee2 |
754 | elprintf(EL_UIO, "%csh2 unmapped w8 [%08x] %02x @%06x", |
755 | id ? 's' : 'm', a, d & 0xff, sh2_pc(id)); |
acd35d4c |
756 | } |
757 | |
b78efee2 |
758 | void p32x_sh2_write16(u32 a, u32 d, int id) |
acd35d4c |
759 | { |
760 | if ((a & 0x0ffffc00) == 0x4000) |
b78efee2 |
761 | elprintf(EL_32X, "%csh2 w16 [%08x] %04x @%06x", |
762 | id ? 's' : 'm', a, d & 0xffff, sh2_pc(id)); |
acd35d4c |
763 | |
764 | if ((a & 0x0ffc0000) == 0x06000000) { |
765 | ((u16 *)Pico32xMem->sdram)[(a & 0x3ffff) / 2] = d; |
766 | return; |
767 | } |
768 | |
b78efee2 |
769 | if ((a & ~0xfff) == 0xc0000000) { |
770 | ((u16 *)Pico32xMem->data_array[id])[(a & 0xfff) / 2] = d; |
771 | return; |
772 | } |
773 | |
266c6afa |
774 | if ((a & 0x0ffe0000) == 0x04000000) { |
775 | Pico32xMem->dram[(Pico32x.vdp_regs[0x0a/2] & P32XV_FS) ^ 1][(a & 0x1ffff) / 2] = d; |
776 | return; |
777 | } |
778 | |
acd35d4c |
779 | if ((a & 0x0fffff00) == 0x4100) { |
780 | p32x_vdp_write16(a, d); |
781 | return; |
782 | } |
783 | |
784 | if ((a & 0x0ffffe00) == 0x4200) { |
785 | Pico32xMem->pal[(a & 0x1ff) / 2] = d; |
786 | Pico32x.dirty_pal = 1; |
787 | return; |
788 | } |
789 | |
790 | if ((a & 0x0fffff00) == 0x4000) { |
b78efee2 |
791 | p32x_sh2reg_write16(a, d, id); |
acd35d4c |
792 | return; |
793 | } |
794 | |
b78efee2 |
795 | elprintf(EL_UIO, "%csh2 unmapped w16 [%08x] %04x @%06x", |
796 | id ? 's' : 'm', a, d & 0xffff, sh2_pc(id)); |
acd35d4c |
797 | } |
798 | |
b78efee2 |
799 | void p32x_sh2_write32(u32 a, u32 d, int id) |
acd35d4c |
800 | { |
4ea707e1 |
801 | if ((a & 0xfffffe00) == 0xfffffe00) { |
b78efee2 |
802 | sh2_peripheral_write(a, d, id); |
4ea707e1 |
803 | return; |
804 | } |
805 | |
b78efee2 |
806 | p32x_sh2_write16(a, d >> 16, id); |
807 | p32x_sh2_write16(a + 2, d, id); |
acd35d4c |
808 | } |
809 | |
be2c4208 |
810 | #define HWSWAP(x) (((x) << 16) | ((x) >> 16)) |
811 | void PicoMemSetup32x(void) |
812 | { |
813 | unsigned short *ps; |
814 | unsigned int *pl; |
5e49c3a8 |
815 | unsigned int rs; |
be2c4208 |
816 | int i; |
817 | |
818 | Pico32xMem = calloc(1, sizeof(*Pico32xMem)); |
819 | if (Pico32xMem == NULL) { |
820 | elprintf(EL_STATUS, "OOM"); |
821 | return; |
822 | } |
823 | |
4ea707e1 |
824 | dmac0 = (void *)&Pico32xMem->sh2_peri_regs[0][0x180 / 4]; |
825 | |
be2c4208 |
826 | // generate 68k ROM |
827 | ps = (unsigned short *)Pico32xMem->m68k_rom; |
828 | pl = (unsigned int *)Pico32xMem->m68k_rom; |
829 | for (i = 1; i < 0xc0/4; i++) |
974fdb5b |
830 | pl[i] = HWSWAP(0x880200 + (i - 1) * 6); |
be2c4208 |
831 | |
832 | // fill with nops |
833 | for (i = 0xc0/2; i < 0x100/2; i++) |
834 | ps[i] = 0x4e71; |
835 | |
5e49c3a8 |
836 | #if 0 |
be2c4208 |
837 | ps[0xc0/2] = 0x46fc; |
838 | ps[0xc2/2] = 0x2700; // move #0x2700,sr |
839 | ps[0xfe/2] = 0x60fe; // jump to self |
5e49c3a8 |
840 | #else |
841 | ps[0xfe/2] = 0x4e75; // rts |
842 | #endif |
be2c4208 |
843 | |
844 | // fill remaining mem with ROM |
974fdb5b |
845 | memcpy(Pico32xMem->m68k_rom + 0x100, Pico.rom + 0x100, sizeof(Pico32xMem->m68k_rom) - 0x100); |
be2c4208 |
846 | |
acd35d4c |
847 | // 32X ROM |
848 | // TODO: move |
849 | { |
850 | FILE *f = fopen("32X_M_BIOS.BIN", "rb"); |
851 | int i; |
852 | if (f == NULL) { |
b78efee2 |
853 | printf("missing 32X_M_BIOS.BIN\n"); |
acd35d4c |
854 | exit(1); |
855 | } |
856 | fread(Pico32xMem->sh2_rom_m, 1, sizeof(Pico32xMem->sh2_rom_m), f); |
857 | fclose(f); |
b78efee2 |
858 | f = fopen("32X_S_BIOS.BIN", "rb"); |
859 | if (f == NULL) { |
860 | printf("missing 32X_S_BIOS.BIN\n"); |
861 | exit(1); |
862 | } |
863 | fread(Pico32xMem->sh2_rom_s, 1, sizeof(Pico32xMem->sh2_rom_s), f); |
864 | fclose(f); |
865 | // byteswap |
acd35d4c |
866 | for (i = 0; i < sizeof(Pico32xMem->sh2_rom_m); i += 2) { |
867 | int t = Pico32xMem->sh2_rom_m[i]; |
868 | Pico32xMem->sh2_rom_m[i] = Pico32xMem->sh2_rom_m[i + 1]; |
869 | Pico32xMem->sh2_rom_m[i + 1] = t; |
870 | } |
b78efee2 |
871 | for (i = 0; i < sizeof(Pico32xMem->sh2_rom_s); i += 2) { |
872 | int t = Pico32xMem->sh2_rom_s[i]; |
873 | Pico32xMem->sh2_rom_s[i] = Pico32xMem->sh2_rom_s[i + 1]; |
874 | Pico32xMem->sh2_rom_s[i + 1] = t; |
875 | } |
acd35d4c |
876 | } |
877 | |
be2c4208 |
878 | // cartridge area becomes unmapped |
879 | // XXX: we take the easy way and don't unmap ROM, |
880 | // so that we can avoid handling the RV bit. |
881 | // m68k_map_unmap(0x000000, 0x3fffff); |
882 | |
883 | // MD ROM area |
974fdb5b |
884 | rs = sizeof(Pico32xMem->m68k_rom); |
885 | cpu68k_map_set(m68k_read8_map, 0x000000, rs - 1, Pico32xMem->m68k_rom, 0); |
886 | cpu68k_map_set(m68k_read16_map, 0x000000, rs - 1, Pico32xMem->m68k_rom, 0); |
887 | cpu68k_map_set(m68k_write8_map, 0x000000, rs - 1, PicoWrite8_hint, 1); // TODO verify |
888 | cpu68k_map_set(m68k_write16_map, 0x000000, rs - 1, PicoWrite16_hint, 1); |
889 | |
890 | // DRAM area |
891 | Pico32xSwapDRAM(1); |
be2c4208 |
892 | |
893 | // 32X ROM (unbanked, XXX: consider mirroring?) |
5e49c3a8 |
894 | rs = (Pico.romsize + M68K_BANK_MASK) & ~M68K_BANK_MASK; |
895 | if (rs > 0x80000) |
896 | rs = 0x80000; |
897 | cpu68k_map_set(m68k_read8_map, 0x880000, 0x880000 + rs - 1, Pico.rom, 0); |
898 | cpu68k_map_set(m68k_read16_map, 0x880000, 0x880000 + rs - 1, Pico.rom, 0); |
be2c4208 |
899 | |
900 | // 32X ROM (banked) |
5e49c3a8 |
901 | bank_switch(0); |
b78efee2 |
902 | |
903 | // setup poll detector |
904 | m68k_poll.flag = P32XF_68KPOLL; |
905 | sh2_poll[0].flag = P32XF_MSH2POLL; |
906 | sh2_poll[1].flag = P32XF_SSH2POLL; |
be2c4208 |
907 | } |
908 | |