Commit | Line | Data |
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56f08d83 | 1 | /* |
2 | * (C) GraÅžvydas "notaz" Ignotas, 2011 | |
3 | * | |
4 | * This work is licensed under the terms of any of these licenses | |
5 | * (at your option): | |
6 | * - GNU GPL, version 2 or later. | |
7 | * - GNU LGPL, version 2.1 or later. | |
8 | * See the COPYING file in the top-level directory. | |
9 | */ | |
10 | ||
7a8d521f | 11 | #ifndef __GPULIB_GPU_H__ |
12 | #define __GPULIB_GPU_H__ | |
13 | ||
56f08d83 | 14 | #include <stdint.h> |
15 | ||
cb245e56 | 16 | //#define RAW_FB_DISPLAY |
17 | ||
a1d82827 | 18 | #define gpu_log(gpu, fmt, ...) \ |
19 | printf("%d:%03d: " fmt, *(gpu)->state.frame_count, *(gpu)->state.hcnt, ##__VA_ARGS__) | |
0b4038f8 | 20 | |
21 | //#define log_anomaly gpu_log | |
22 | #define log_anomaly(...) | |
23 | ||
6f2ee2be | 24 | #ifdef __cplusplus |
25 | extern "C" { | |
26 | #endif | |
27 | ||
56f08d83 | 28 | #define CMD_BUFFER_LEN 1024 |
29 | ||
89df80c6 PC |
30 | #if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__ |
31 | #define HTOLE32(x) __builtin_bswap32(x) | |
32 | #define HTOLE16(x) __builtin_bswap16(x) | |
33 | #define LE32TOH(x) __builtin_bswap32(x) | |
34 | #define LE16TOH(x) __builtin_bswap16(x) | |
35 | #else | |
36 | #define HTOLE32(x) (x) | |
37 | #define HTOLE16(x) (x) | |
38 | #define LE32TOH(x) (x) | |
39 | #define LE16TOH(x) (x) | |
40 | #endif | |
41 | ||
1131a875 | 42 | #undef BIT |
43 | #define BIT(x) (1u << (x)) | |
f23b103c PC |
44 | |
45 | #define PSX_GPU_STATUS_DHEIGHT BIT(19) | |
308c6e67 | 46 | #define PSX_GPU_STATUS_PAL BIT(20) |
f23b103c PC |
47 | #define PSX_GPU_STATUS_RGB24 BIT(21) |
48 | #define PSX_GPU_STATUS_INTERLACE BIT(22) | |
49 | #define PSX_GPU_STATUS_BLANKING BIT(23) | |
50 | #define PSX_GPU_STATUS_IMG BIT(27) | |
51 | #define PSX_GPU_STATUS_DMA(x) ((x) << 29) | |
52 | #define PSX_GPU_STATUS_DMA_MASK (BIT(29) | BIT(30)) | |
53 | ||
56f08d83 | 54 | struct psx_gpu { |
56f08d83 | 55 | uint32_t regs[16]; |
9ee0fd5b | 56 | uint16_t *vram; |
f23b103c | 57 | uint32_t status; |
6e9bdaef | 58 | uint32_t gp0; |
59 | uint32_t ex_regs[8]; | |
56f08d83 | 60 | struct { |
8dd855cd | 61 | int hres, vres; |
56f08d83 | 62 | int x, y, w, h; |
8dd855cd | 63 | int x1, x2; |
56f08d83 | 64 | int y1, y2; |
308c6e67 | 65 | int src_x, src_y; |
56f08d83 | 66 | } screen; |
67 | struct { | |
68 | int x, y, w, h; | |
05740673 | 69 | short int offset, is_read; |
70 | } dma, dma_start; | |
56f08d83 | 71 | int cmd_len; |
56f08d83 | 72 | uint32_t zero; |
fc84f618 | 73 | struct { |
74 | uint32_t fb_dirty:1; | |
5440b88e | 75 | uint32_t old_interlace:1; |
76 | uint32_t allow_interlace:2; | |
aafcb4dd | 77 | uint32_t blanked:1; |
0b02eb77 | 78 | uint32_t enhancement_enable:1; |
79 | uint32_t enhancement_active:1; | |
0b4038f8 | 80 | uint32_t enhancement_was_active:1; |
e223fa15 | 81 | uint32_t downscale_enable:1; |
82 | uint32_t downscale_active:1; | |
308c6e67 | 83 | uint32_t dims_changed:1; |
f9ffa42c | 84 | uint32_t show_overscan:2; |
3ece2f0c | 85 | uint32_t *frame_count; |
86 | uint32_t *hcnt; /* hsync count */ | |
deb18d24 | 87 | struct { |
88 | uint32_t addr; | |
1c72b1c2 | 89 | uint32_t cycles; |
deb18d24 | 90 | uint32_t frame; |
91 | uint32_t hcnt; | |
92 | } last_list; | |
5440b88e | 93 | uint32_t last_vram_read_frame; |
81277586 | 94 | uint32_t w_out_old, h_out_old, status_vo_old; |
9ed80467 | 95 | short screen_centering_type; |
96 | short screen_centering_type_default; | |
238696ae | 97 | short screen_centering_x; |
98 | short screen_centering_y; | |
99 | int screen_centering_h_adj; | |
fc84f618 | 100 | } state; |
101 | struct { | |
9fe27e25 | 102 | int32_t set:3; /* -1 auto, 0 off, 1-3 fixed */ |
103 | int32_t cnt:3; /* amount skipped in a row */ | |
fc84f618 | 104 | uint32_t active:1; |
fb4c6fba | 105 | uint32_t allow:1; |
fc84f618 | 106 | uint32_t frame_ready:1; |
107 | const int *advice; | |
79c4d434 | 108 | const int *force; |
109 | int *dirty; | |
fb4c6fba | 110 | uint32_t last_flip_frame; |
fbb4bfff | 111 | uint32_t pending_fill[3]; |
fc84f618 | 112 | } frameskip; |
79c4d434 | 113 | uint32_t scratch_ex_regs[8]; // for threaded rendering |
0d515420 | 114 | uint32_t cmd_buffer[CMD_BUFFER_LEN]; |
308c6e67 | 115 | void *(*get_enhancement_bufer) |
fa56d360 | 116 | (int *x, int *y, int *w, int *h, int *vram_h); |
e223fa15 | 117 | uint16_t *(*get_downscale_buffer) |
118 | (int *x, int *y, int *w, int *h, int *vram_h); | |
9ee0fd5b | 119 | void *(*mmap)(unsigned int size); |
120 | void (*munmap)(void *ptr, unsigned int size); | |
b244864a | 121 | void (*gpu_state_change)(int what, int cycles); // psx_gpu_state |
56f08d83 | 122 | }; |
123 | ||
124 | extern struct psx_gpu gpu; | |
125 | ||
126 | extern const unsigned char cmd_lengths[256]; | |
127 | ||
8412166f | 128 | int do_cmd_list(uint32_t *list, int count, |
129 | int *cycles_sum, int *cycles_last, int *last_cmd); | |
56f08d83 | 130 | |
914455e6 | 131 | struct rearmed_cbs; |
132 | ||
9394ada5 | 133 | int renderer_init(void); |
e929dec5 | 134 | void renderer_finish(void); |
5b745e5b | 135 | void renderer_sync_ecmds(uint32_t * ecmds); |
0b4038f8 | 136 | void renderer_update_caches(int x, int y, int w, int h, int state_changed); |
9394ada5 | 137 | void renderer_flush_queues(void); |
5440b88e | 138 | void renderer_set_interlace(int enable, int is_odd); |
914455e6 | 139 | void renderer_set_config(const struct rearmed_cbs *config); |
e929dec5 | 140 | void renderer_notify_res_change(void); |
79c4d434 | 141 | void renderer_notify_update_lace(int updated); |
142 | void renderer_sync(void); | |
2da2fc76 | 143 | void renderer_notify_scanout_change(int x, int y); |
9394ada5 | 144 | |
5440b88e | 145 | int vout_init(void); |
146 | int vout_finish(void); | |
f665bfda | 147 | int vout_update(void); |
aafcb4dd | 148 | void vout_blank(void); |
5440b88e | 149 | void vout_set_config(const struct rearmed_cbs *config); |
6f2ee2be | 150 | |
f060f4be | 151 | int prim_try_simplify_quad_t (void *simplified, const void *prim); |
152 | int prim_try_simplify_quad_gt(void *simplified, const void *prim); | |
153 | ||
096ec49b | 154 | /* listing these here for correct linkage if rasterizer uses c++ */ |
155 | struct GPUFreeze; | |
096ec49b | 156 | |
157 | long GPUinit(void); | |
158 | long GPUshutdown(void); | |
159 | void GPUwriteDataMem(uint32_t *mem, int count); | |
8412166f | 160 | long GPUdmaChain(uint32_t *rambase, uint32_t addr, |
161 | uint32_t *progress_addr, int32_t *cycles_last_cmd); | |
096ec49b | 162 | void GPUwriteData(uint32_t data); |
163 | void GPUreadDataMem(uint32_t *mem, int count); | |
164 | uint32_t GPUreadData(void); | |
165 | uint32_t GPUreadStatus(void); | |
166 | void GPUwriteStatus(uint32_t data); | |
167 | long GPUfreeze(uint32_t type, struct GPUFreeze *freeze); | |
168 | void GPUupdateLace(void); | |
71e413be | 169 | long GPUopen(unsigned long *disp, char *cap, char *cfg); |
096ec49b | 170 | long GPUclose(void); |
72e5023f | 171 | void GPUvBlank(int is_vblank, int lcf); |
ab88daca | 172 | void GPUgetScreenInfo(int *y, int *base_hres); |
096ec49b | 173 | void GPUrearmedCallbacks(const struct rearmed_cbs *cbs_); |
174 | ||
6f2ee2be | 175 | #ifdef __cplusplus |
176 | } | |
177 | #endif | |
7a8d521f | 178 | |
179 | #endif /* __GPULIB_GPU_H__ */ |