| Commit | Line | Data |
|---|---|---|
| 56f08d83 | 1 | /* |
| 2 | * (C) GraÅžvydas "notaz" Ignotas, 2011 | |
| 3 | * | |
| 4 | * This work is licensed under the terms of any of these licenses | |
| 5 | * (at your option): | |
| 6 | * - GNU GPL, version 2 or later. | |
| 7 | * - GNU LGPL, version 2.1 or later. | |
| 8 | * See the COPYING file in the top-level directory. | |
| 9 | */ | |
| 10 | ||
| 7a8d521f | 11 | #ifndef __GPULIB_GPU_H__ |
| 12 | #define __GPULIB_GPU_H__ | |
| 13 | ||
| 56f08d83 | 14 | #include <stdint.h> |
| 2fbb0519 | 15 | #include <string.h> |
| 16 | #include "../../include/compiler_features.h" | |
| 56f08d83 | 17 | |
| cb245e56 | 18 | //#define RAW_FB_DISPLAY |
| 19 | ||
| a1d82827 | 20 | #define gpu_log(gpu, fmt, ...) \ |
| 13942b75 | 21 | SysPrintf("%d:%03d: " fmt, *(gpu)->state.frame_count, *(gpu)->state.hcnt, ##__VA_ARGS__) |
| 0b4038f8 | 22 | |
| 2fbb0519 | 23 | #ifdef LOG_UNHANDLED |
| 24 | #define log_anomaly gpu_log | |
| 25 | #else | |
| 0b4038f8 | 26 | #define log_anomaly(...) |
| 2fbb0519 | 27 | #endif |
| 0b4038f8 | 28 | |
| 6f2ee2be | 29 | #ifdef __cplusplus |
| 30 | extern "C" { | |
| 31 | #endif | |
| 32 | ||
| 56f08d83 | 33 | #define CMD_BUFFER_LEN 1024 |
| 34 | ||
| 89df80c6 PC |
35 | #if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__ |
| 36 | #define HTOLE32(x) __builtin_bswap32(x) | |
| 37 | #define HTOLE16(x) __builtin_bswap16(x) | |
| 38 | #define LE32TOH(x) __builtin_bswap32(x) | |
| 39 | #define LE16TOH(x) __builtin_bswap16(x) | |
| 40 | #else | |
| 41 | #define HTOLE32(x) (x) | |
| 42 | #define HTOLE16(x) (x) | |
| 43 | #define LE32TOH(x) (x) | |
| 44 | #define LE16TOH(x) (x) | |
| 45 | #endif | |
| 46 | ||
| 1131a875 | 47 | #undef BIT |
| 48 | #define BIT(x) (1u << (x)) | |
| f23b103c PC |
49 | |
| 50 | #define PSX_GPU_STATUS_DHEIGHT BIT(19) | |
| 308c6e67 | 51 | #define PSX_GPU_STATUS_PAL BIT(20) |
| f23b103c PC |
52 | #define PSX_GPU_STATUS_RGB24 BIT(21) |
| 53 | #define PSX_GPU_STATUS_INTERLACE BIT(22) | |
| 54 | #define PSX_GPU_STATUS_BLANKING BIT(23) | |
| 55 | #define PSX_GPU_STATUS_IMG BIT(27) | |
| 56 | #define PSX_GPU_STATUS_DMA(x) ((x) << 29) | |
| 57 | #define PSX_GPU_STATUS_DMA_MASK (BIT(29) | BIT(30)) | |
| 58 | ||
| 7fe57395 | 59 | struct psx_gpu_async; |
| 60 | ||
| 61 | struct psx_gpu_screen { | |
| 62 | short hres, vres; | |
| 63 | short x, y, w, h; | |
| 64 | short x1, x2; | |
| 65 | short y1, y2; | |
| 66 | short src_x, src_y; | |
| 67 | }; | |
| 68 | ||
| 56f08d83 | 69 | struct psx_gpu { |
| 56f08d83 | 70 | uint32_t regs[16]; |
| 9ee0fd5b | 71 | uint16_t *vram; |
| f23b103c | 72 | uint32_t status; |
| 6e9bdaef | 73 | uint32_t gp0; |
| 212d2ac3 | 74 | uint32_t ex_regs[8]; // in native endian |
| 7fe57395 | 75 | struct psx_gpu_screen screen; |
| 56f08d83 | 76 | struct { |
| 77 | int x, y, w, h; | |
| 05740673 | 78 | short int offset, is_read; |
| 79 | } dma, dma_start; | |
| 56f08d83 | 80 | int cmd_len; |
| 56f08d83 | 81 | uint32_t zero; |
| fc84f618 | 82 | struct { |
| 83 | uint32_t fb_dirty:1; | |
| 53672084 | 84 | uint32_t fb_dirty_display_area:1; |
| 85 | uint32_t draw_display_intersect:1; | |
| 5440b88e | 86 | uint32_t old_interlace:1; |
| 87 | uint32_t allow_interlace:2; | |
| aafcb4dd | 88 | uint32_t blanked:1; |
| 26c97f25 | 89 | uint32_t vblank:1; |
| 90 | uint32_t use_alternative_flip:1; | |
| 0b02eb77 | 91 | uint32_t enhancement_enable:1; |
| 92 | uint32_t enhancement_active:1; | |
| 0b4038f8 | 93 | uint32_t enhancement_was_active:1; |
| e223fa15 | 94 | uint32_t downscale_enable:1; |
| 308c6e67 | 95 | uint32_t dims_changed:1; |
| f9ffa42c | 96 | uint32_t show_overscan:2; |
| 3ece2f0c | 97 | uint32_t *frame_count; |
| 98 | uint32_t *hcnt; /* hsync count */ | |
| deb18d24 | 99 | struct { |
| 100 | uint32_t addr; | |
| 1c72b1c2 | 101 | uint32_t cycles; |
| deb18d24 | 102 | uint32_t frame; |
| 103 | uint32_t hcnt; | |
| 104 | } last_list; | |
| 5440b88e | 105 | uint32_t last_vram_read_frame; |
| 26c97f25 | 106 | uint32_t last_adflip_frame; |
| 4bcdc006 | 107 | uint16_t w_out_old, h_out_old, src_y_old; |
| 108 | uint32_t status_vo_old; | |
| 9ed80467 | 109 | short screen_centering_type; |
| 110 | short screen_centering_type_default; | |
| 238696ae | 111 | short screen_centering_x; |
| 112 | short screen_centering_y; | |
| 113 | int screen_centering_h_adj; | |
| fc84f618 | 114 | } state; |
| 115 | struct { | |
| 9fe27e25 | 116 | int32_t set:3; /* -1 auto, 0 off, 1-3 fixed */ |
| 117 | int32_t cnt:3; /* amount skipped in a row */ | |
| fc84f618 | 118 | uint32_t active:1; |
| fb4c6fba | 119 | uint32_t allow:1; |
| fc84f618 | 120 | uint32_t frame_ready:1; |
| cf63d2c5 | 121 | uint32_t ecmds_dirty_renderer:1; |
| fc84f618 | 122 | const int *advice; |
| 79c4d434 | 123 | const int *force; |
| 124 | int *dirty; | |
| fb4c6fba | 125 | uint32_t last_flip_frame; |
| fbb4bfff | 126 | uint32_t pending_fill[3]; |
| fc84f618 | 127 | } frameskip; |
| 0d515420 | 128 | uint32_t cmd_buffer[CMD_BUFFER_LEN]; |
| 7fe57395 | 129 | struct psx_gpu_async *async; |
| 308c6e67 | 130 | void *(*get_enhancement_bufer) |
| fa56d360 | 131 | (int *x, int *y, int *w, int *h, int *vram_h); |
| e223fa15 | 132 | uint16_t *(*get_downscale_buffer) |
| 133 | (int *x, int *y, int *w, int *h, int *vram_h); | |
| 9ee0fd5b | 134 | void *(*mmap)(unsigned int size); |
| 135 | void (*munmap)(void *ptr, unsigned int size); | |
| b244864a | 136 | void (*gpu_state_change)(int what, int cycles); // psx_gpu_state |
| 56f08d83 | 137 | }; |
| 138 | ||
| 139 | extern struct psx_gpu gpu; | |
| 140 | ||
| 141 | extern const unsigned char cmd_lengths[256]; | |
| 142 | ||
| 914455e6 | 143 | struct rearmed_cbs; |
| 144 | ||
| 7fe57395 | 145 | // ex_regs: renderer should write Ex values for gpulib, never use them itself |
| 146 | int renderer_do_cmd_list(uint32_t *list, int count, uint32_t *ex_regs, | |
| 147 | int *cycles_sum, int *cycles_last, int *last_cmd); | |
| 148 | ||
| 9394ada5 | 149 | int renderer_init(void); |
| e929dec5 | 150 | void renderer_finish(void); |
| 5b745e5b | 151 | void renderer_sync_ecmds(uint32_t * ecmds); |
| 0b4038f8 | 152 | void renderer_update_caches(int x, int y, int w, int h, int state_changed); |
| 9394ada5 | 153 | void renderer_flush_queues(void); |
| 5440b88e | 154 | void renderer_set_interlace(int enable, int is_odd); |
| 914455e6 | 155 | void renderer_set_config(const struct rearmed_cbs *config); |
| 7fe57395 | 156 | void renderer_notify_screen_change(const struct psx_gpu_screen *screen); |
| 9394ada5 | 157 | |
| 5440b88e | 158 | int vout_init(void); |
| 159 | int vout_finish(void); | |
| ed92e4a7 | 160 | int vout_update(struct psx_gpu *gpu, int src_x, int src_y); |
| 161 | void vout_blank(struct psx_gpu *gpu); | |
| 5440b88e | 162 | void vout_set_config(const struct rearmed_cbs *config); |
| 6f2ee2be | 163 | |
| 7fe57395 | 164 | // helpers |
| 2fbb0519 | 165 | #define VRAM_MEM_XY(vram_, x, y) &vram_[(y) * 1024 + (x)] |
| 166 | ||
| 7fe57395 | 167 | int do_vram_copy(uint16_t *vram, const uint32_t *ex_regs, |
| 168 | const uint32_t *params, int *cpu_cycles); | |
| 169 | ||
| f060f4be | 170 | int prim_try_simplify_quad_t (void *simplified, const void *prim); |
| 171 | int prim_try_simplify_quad_gt(void *simplified, const void *prim); | |
| 172 | ||
| 2fbb0519 | 173 | void cpy_mask(uint16_t *dst, const uint16_t *src, int l, uint32_t r6); |
| 174 | ||
| 175 | static inline void do_vram_line(uint16_t *vram_, int x, int y, | |
| 176 | uint16_t *mem, int l, int is_read, uint32_t r6) | |
| 177 | { | |
| 178 | uint16_t *vram = VRAM_MEM_XY(vram_, x, y); | |
| 179 | if (unlikely(is_read)) | |
| 180 | memcpy(mem, vram, l * 2); | |
| 181 | else if (unlikely(r6)) | |
| 182 | cpy_mask(vram, mem, l, r6); | |
| 183 | else | |
| 184 | memcpy(vram, mem, l * 2); | |
| 185 | } | |
| 186 | ||
| 096ec49b | 187 | /* listing these here for correct linkage if rasterizer uses c++ */ |
| 188 | struct GPUFreeze; | |
| 096ec49b | 189 | |
| 190 | long GPUinit(void); | |
| 191 | long GPUshutdown(void); | |
| 192 | void GPUwriteDataMem(uint32_t *mem, int count); | |
| 8412166f | 193 | long GPUdmaChain(uint32_t *rambase, uint32_t addr, |
| 194 | uint32_t *progress_addr, int32_t *cycles_last_cmd); | |
| 096ec49b | 195 | void GPUwriteData(uint32_t data); |
| 196 | void GPUreadDataMem(uint32_t *mem, int count); | |
| 197 | uint32_t GPUreadData(void); | |
| 198 | uint32_t GPUreadStatus(void); | |
| 199 | void GPUwriteStatus(uint32_t data); | |
| d7c6199e | 200 | long GPUfreeze(uint32_t type, struct GPUFreeze *freeze, uint16_t **vram_ptr); |
| 71e413be | 201 | long GPUopen(unsigned long *disp, char *cap, char *cfg); |
| 096ec49b | 202 | long GPUclose(void); |
| 72e5023f | 203 | void GPUvBlank(int is_vblank, int lcf); |
| ab88daca | 204 | void GPUgetScreenInfo(int *y, int *base_hres); |
| 096ec49b | 205 | void GPUrearmedCallbacks(const struct rearmed_cbs *cbs_); |
| 206 | ||
| 7fe57395 | 207 | void SysPrintf(const char *fmt, ...); |
| 208 | ||
| 6f2ee2be | 209 | #ifdef __cplusplus |
| 210 | } | |
| 211 | #endif | |
| 7a8d521f | 212 | |
| 213 | #endif /* __GPULIB_GPU_H__ */ |