UINT32 delay;\r
UINT32 test_irq;\r
\r
- int pending_irq;\r
+ int pending_irl;\r
+ int pending_int_irq; // internal irq\r
+ int pending_int_vector;\r
void (*irq_callback)(int id, int level);\r
int is_slave;\r
\r
void sh2_reset(SH2 *sh2);\r
int sh2_execute(SH2 *sh2_, int cycles);\r
void sh2_irl_irq(SH2 *sh2, int level);\r
+void sh2_internal_irq(SH2 *sh2, int level, int vector);\r
\r
#endif /* __SH2_H__ */\r
sh2->sr = I;
}
+static void sh2_do_irq(SH2 *sh2, int level, int vector)
+{
+ sh2->irq_callback(sh2->is_slave, level);
+
+ sh2->r[15] -= 4;
+ WL(sh2->r[15], sh2->sr); /* push SR onto stack */
+ sh2->r[15] -= 4;
+ WL(sh2->r[15], sh2->pc); /* push PC onto stack */
+
+ /* set I flags in SR */
+ sh2->sr = (sh2->sr & ~I) | (level << 4);
+
+ /* fetch PC */
+ sh2->pc = RL(sh2->vbr + vector * 4);
+
+ /* 13 cycles at best */
+ sh2_icount -= 13;
+}
+
/* Execute cycles - returns number of cycles actually run */
int sh2_execute(SH2 *sh2_, int cycles)
{
if (sh2->test_irq && !sh2->delay)
{
- if (sh2->pending_irq)
- sh2_irl_irq(sh2, sh2->pending_irq);
+ if (sh2->pending_irl > sh2->pending_int_irq)
+ sh2_irl_irq(sh2, sh2->pending_irl);
+ else
+ sh2_internal_irq(sh2, sh2->pending_int_irq, sh2->pending_int_vector);
sh2->test_irq = 0;
}
sh2_icount--;
void sh2_irl_irq(SH2 *sh2, int level)
{
- int vector;
-
- sh2->pending_irq = level;
-
+ sh2->pending_irl = level;
if (level <= ((sh2->sr >> 4) & 0x0f))
- /* masked */
return;
- sh2->irq_callback(sh2->is_slave, level);
- vector = 64 + level/2;
-
- sh2->r[15] -= 4;
- WL(sh2->r[15], sh2->sr); /* push SR onto stack */
- sh2->r[15] -= 4;
- WL(sh2->r[15], sh2->pc); /* push PC onto stack */
-
- /* set I flags in SR */
- sh2->sr = (sh2->sr & ~I) | (level << 4);
+ sh2_do_irq(sh2, level, 64 + level/2);
+}
- /* fetch PC */
- sh2->pc = RL(sh2->vbr + vector * 4);
+void sh2_internal_irq(SH2 *sh2, int level, int vector)
+{
+ sh2->pending_int_irq = level;
+ sh2->pending_int_vector = vector;
+ if (level <= ((sh2->sr >> 4) & 0x0f))
+ return;
- /* 13 cycles at best */
- sh2_icount -= 13;
+ sh2_do_irq(sh2, level, vector);
+ sh2->pending_int_irq = 0; // auto-clear
}
#include "../pico_int.h"
#include "../sound/ym2612.h"
+SH2 sh2s[2];
struct Pico32x Pico32x;
static void sh2_irq_cb(int id, int level)
if (!Pico.m.pal)
Pico32x.vdp_regs[0] |= P32XV_nPAL;
+ PREG8(Pico32xMem->sh2_peri_regs[0], 4) =
+ PREG8(Pico32xMem->sh2_peri_regs[1], 4) = 0x84; // SCI SSR
+
emu_32x_startup();
}
if (is_vdp)
flag <<= 3;
- if (a - 2 <= pd->addr && pd->addr <= a + 2 && cycles - pd->cycles < pd->cyc_max) {
+ if (a - 2 <= pd->addr && pd->addr <= a + 2 && cycles - pd->cycles <= pd->cyc_max) {
pd->cnt++;
if (pd->cnt > POLL_THRESHOLD) {
if (!(Pico32x.emu_flags & flag)) {
if ((r[0] ^ d) & P32XV_PRI)
Pico32x.dirty_pal = 1;
r[0] = (r[0] & P32XV_nPAL) | (d & 0xff);
- if ((d & 3) == 3)
- elprintf(EL_32X|EL_ANOMALY, "TODO: mode3");
break;
case 0x05: // fill len
r[4 / 2] = d & 0xff;
case 0x1a: Pico32x.sh2irqi[cpuid] &= ~P32XI_CMD; goto irls;
case 0x1c:
Pico32x.sh2irqs &= ~P32XI_PWM;
- p32x_pwm_irq_check(0);
+ p32x_timers_do(0);
goto irls;
}
// ------------------------------------------------------------------
// SH2 internal peripherals
+// we keep them in little endian format
static u32 sh2_peripheral_read8(u32 a, int id)
{
u8 *r = (void *)Pico32xMem->sh2_peri_regs[id];
u32 d;
a &= 0x1ff;
- d = r[a];
- if (a == 4)
- d = 0x84; // SCI SSR
+ d = PREG8(r, a);
elprintf(EL_32X, "%csh2 peri r8 [%08x] %02x @%06x", id ? 's' : 'm', a | ~0x1ff, d, sh2_pc(id));
return d;
}
+static u32 sh2_peripheral_read16(u32 a, int id)
+{
+ u16 *r = (void *)Pico32xMem->sh2_peri_regs[id];
+ u32 d;
+
+ a &= 0x1ff;
+ d = r[(a / 2) ^ 1];
+
+ elprintf(EL_32X, "%csh2 peri r16 [%08x] %04x @%06x", id ? 's' : 'm', a | ~0x1ff, d, sh2_pc(id));
+ return d;
+}
+
static u32 sh2_peripheral_read32(u32 a, int id)
{
u32 d;
elprintf(EL_32X, "%csh2 peri w8 [%08x] %02x @%06x", id ? 's' : 'm', a, d, sh2_pc(id));
a &= 0x1ff;
- r[a] = d;
+ PREG8(r, a) = d;
+
+ // X-men SCI hack
+ if ((a == 2 && (d & 0x20)) || // transmiter enabled
+ (a == 4 && !(d & 0x80))) { // valid data in TDR
+ void *oregs = Pico32xMem->sh2_peri_regs[id ^ 1];
+ if ((PREG8(oregs, 2) & 0x50) == 0x50) { // receiver + irq enabled
+ int level = PREG8(oregs, 0x60) >> 4;
+ int vector = PREG8(oregs, 0x63) & 0x7f;
+ elprintf(EL_32X, "%csh2 SCI recv irq (%d, %d)", (id ^ 1) ? 's' : 'm', level, vector);
+ sh2_internal_irq(&sh2s[id ^ 1], level, vector);
+ }
+ }
+}
+
+static void sh2_peripheral_write16(u32 a, u32 d, int id)
+{
+ u16 *r = (void *)Pico32xMem->sh2_peri_regs[id];
+ elprintf(EL_32X, "%csh2 peri w16 [%08x] %04x @%06x", id ? 's' : 'm', a, d, sh2_pc(id));
+
+ a &= 0x1ff;
+
+ // evil WDT
+ if (a == 0x80) {
+ if ((d & 0xff00) == 0xa500) { // WTCSR
+ PREG8(r, 0x80) = d;
+ p32x_timers_recalc();
+ }
+ if ((d & 0xff00) == 0x5a00) // WTCNT
+ PREG8(r, 0x81) = d;
+ return;
+ }
+
+ r[(a / 2) ^ 1] = d;
}
static void sh2_peripheral_write32(u32 a, u32 d, int id)
goto out;
}
+ if ((a & 0xfffffe00) == 0xfffffe00)
+ return sh2_peripheral_read16(a, id);
+
elprintf(EL_UIO, "%csh2 unmapped r16 [%08x] %04x @%06x",
id ? 's' : 'm', a, d, sh2_pc(id));
return d;
return;
}
+ if ((a & 0xfffffe00) == 0xfffffe00) {
+ sh2_peripheral_write16(a, d, id);
+ return;
+ }
+
elprintf(EL_UIO, "%csh2 unmapped w16 [%08x] %04x @%06x",
id ? 's' : 'm', a, d & 0xffff, sh2_pc(id));
}
m68k_poll.flag = P32XF_68KPOLL;
m68k_poll.cyc_max = 64;
sh2_poll[0].flag = P32XF_MSH2POLL;
- sh2_poll[0].cyc_max = 16;
+ sh2_poll[0].cyc_max = 21;
sh2_poll[1].flag = P32XF_SSH2POLL;
sh2_poll[1].cyc_max = 16;
}
static int pwm_ptr;
int pwm_frame_smp_cnt;
+static int timer_line_ticks[2];
-void p32x_pwm_refresh(void)
+// timers. This includes PWM timer in 32x and internal SH2 timers
+void p32x_timers_recalc(void)
{
int cycles = Pico32x.regs[0x32 / 2];
int frame_samples;
+ int tmp, i;
cycles = (cycles - 1) & 0x0fff;
if (cycles < 500) {
frame_samples = OSC_NTSC / 7 * 3 / 60 / cycles;
pwm_line_samples = (frame_samples << 16) / scanlines_total;
+
+ // SH2 timer step
+ for (i = 0; i < 2; i++) {
+ tmp = PREG8(Pico32xMem->sh2_peri_regs[i], 0x80) & 7;
+ // Sclk cycles per timer tick
+ if (tmp)
+ cycles = 0x20 << tmp;
+ else
+ cycles = 2;
+ if (Pico.m.pal)
+ tmp = OSC_PAL / 7 * 3 / 50 / scanlines_total;
+ else
+ tmp = OSC_NTSC / 7 * 3 / 60 / scanlines_total;
+ timer_line_ticks[i] = (tmp << 16) / cycles;
+ elprintf(EL_32X, "timer_line_ticks[%d] = %.3f", i, (double)timer_line_ticks[i] / 0x10000);
+ }
}
-// irq for every sample??
-// FIXME: we need to hit more than once per line :(
-void p32x_pwm_irq_check(int new_line)
+// PWM irq for every tm samples
+void p32x_timers_do(int new_line)
{
- int tm = (Pico32x.regs[0x30 / 2] & 0x0f00) >> 8;
- if (tm == 0)
- return; // TODO: verify
-
- if (new_line)
- Pico32x.pwm_irq_sample_cnt += pwm_line_samples;
- if (Pico32x.pwm_irq_sample_cnt >= (tm << 16)) {
- Pico32x.pwm_irq_sample_cnt -= tm << 16;
- Pico32x.sh2irqs |= P32XI_PWM;
- p32x_update_irls();
+ int tm, cnt, i;
+ tm = (Pico32x.regs[0x30 / 2] & 0x0f00) >> 8;
+ if (tm != 0) {
+ if (new_line)
+ Pico32x.pwm_irq_sample_cnt += pwm_line_samples;
+ if (Pico32x.pwm_irq_sample_cnt >= (tm << 16)) {
+ Pico32x.pwm_irq_sample_cnt -= tm << 16;
+ Pico32x.sh2irqs |= P32XI_PWM;
+ p32x_update_irls();
+ }
+ }
+
+ if (!new_line)
+ return;
+
+ for (i = 0; i < 2; i++) {
+ void *pregs = Pico32xMem->sh2_peri_regs[i];
+ if (PREG8(pregs, 0x80) & 0x20) { // TME
+ cnt = PREG8(pregs, 0x81);
+ cnt += timer_line_ticks[i];
+ if (cnt >= 0x100) {
+ int level = PREG8(pregs, 0xe3) >> 4;
+ int vector = PREG8(pregs, 0xe4) & 0x7f;
+ elprintf(EL_32X, "%csh2 WDT irq (%d, %d)", i ? 's' : 'm', level, vector);
+ sh2_internal_irq(&sh2s[i], level, vector);
+ }
+ cnt &= 0xff;
+ PREG8(pregs, 0x81) = cnt;
+ }
}
}
Pico32x.regs[0x30 / 2] = d;
else if (a == 2) { // cycle
Pico32x.regs[0x32 / 2] = d & 0x0fff;
- p32x_pwm_refresh();
+ p32x_timers_recalc();
Pico32x.pwm_irq_sample_cnt = 0; // resets?
}
else if (a <= 8) {
scanlines_total = Pico.m.pal ? 312 : 262;\r
\r
if (PicoAHW & PAHW_32X)\r
- p32x_pwm_refresh();\r
+ p32x_timers_recalc();\r
}\r
\r
\r
check_cd_dma();
#endif
#ifdef PICO_32X
- p32x_pwm_irq_check(1);
+ p32x_timers_do(1);
#endif
// H-Interrupts:
check_cd_dma();
#endif
#ifdef PICO_32X
- p32x_pwm_irq_check(1);
+ p32x_timers_do(1);
#endif
// Last H-Int:
check_cd_dma();
#endif
#ifdef PICO_32X
- p32x_pwm_irq_check(1);
+ p32x_timers_do(1);
#endif
// Run scanline:
\r
#include "cpu/sh2mame/sh2.h"\r
\r
-SH2 msh2, ssh2;\r
+extern SH2 sh2s[2];\r
+#define msh2 sh2s[0]\r
+#define ssh2 sh2s[1]\r
+\r
#define ash2_end_run(after) if (sh2_icount > (after)) sh2_icount = after\r
#define ash2_cycles_done() (sh2->cycles_aim - sh2_icount)\r
\r
#define P32XI_CMD (1 << 8/2)\r
#define P32XI_PWM (1 << 6/2)\r
\r
+// peripheral reg access\r
+#define PREG8(regs,offs) ((unsigned char *)regs)[offs ^ 3]\r
+\r
// real one is 4*2, but we use more because we don't lockstep\r
#define DMAC_FIFO_LEN (4*4)\r
#define PWM_BUFF_LEN 1024 // in one channel samples\r
// 32x/pwm.c\r
unsigned int p32x_pwm_read16(unsigned int a);\r
void p32x_pwm_write16(unsigned int a, unsigned int d);\r
-void p32x_pwm_refresh(void);\r
-void p32x_pwm_irq_check(int new_line);\r
void p32x_pwm_update(int *buf32, int length, int stereo);\r
+void p32x_timers_do(int new_line);\r
+void p32x_timers_recalc(void);\r
extern int pwm_frame_smp_cnt;\r
\r
/* avoid dependency on newer glibc */\r
notaz.gp2x.de / picodrive.git / commitdiff