be2c4208 |
1 | #include "../pico_int.h" |
2 | #include "../memory.h" |
3 | |
236990cf |
4 | #if 0 |
c987bb5c |
5 | #undef ash2_end_run |
6 | #undef SekEndRun |
7 | #define ash2_end_run(x) |
8 | #define SekEndRun(x) |
9 | #endif |
10 | |
be2c4208 |
11 | static const char str_mars[] = "MARS"; |
12 | |
974fdb5b |
13 | struct Pico32xMem *Pico32xMem; |
14 | |
5e49c3a8 |
15 | static void bank_switch(int b); |
16 | |
266c6afa |
17 | // poll detection |
4ea707e1 |
18 | #define POLL_THRESHOLD 6 |
19 | |
266c6afa |
20 | struct poll_det { |
be20816c |
21 | u32 addr, cycles, cyc_max; |
22 | int cnt, flag; |
266c6afa |
23 | }; |
b78efee2 |
24 | static struct poll_det m68k_poll, sh2_poll[2]; |
266c6afa |
25 | |
be20816c |
26 | static int p32x_poll_detect(struct poll_det *pd, u32 a, u32 cycles, int is_vdp) |
266c6afa |
27 | { |
b78efee2 |
28 | int ret = 0, flag = pd->flag; |
29 | |
30 | if (is_vdp) |
31 | flag <<= 3; |
266c6afa |
32 | |
1d7a28a7 |
33 | if (a - 2 <= pd->addr && pd->addr <= a + 2 && cycles - pd->cycles <= pd->cyc_max) { |
266c6afa |
34 | pd->cnt++; |
35 | if (pd->cnt > POLL_THRESHOLD) { |
36 | if (!(Pico32x.emu_flags & flag)) { |
be20816c |
37 | elprintf(EL_32X, "%s poll addr %08x, cyc %u", |
38 | flag & (P32XF_68KPOLL|P32XF_68KVPOLL) ? "m68k" : |
39 | (flag & (P32XF_MSH2POLL|P32XF_MSH2VPOLL) ? "msh2" : "ssh2"), a, cycles - pd->cycles); |
266c6afa |
40 | ret = 1; |
41 | } |
42 | Pico32x.emu_flags |= flag; |
43 | } |
44 | } |
c987bb5c |
45 | else { |
266c6afa |
46 | pd->cnt = 0; |
c987bb5c |
47 | pd->addr = a; |
48 | } |
be20816c |
49 | pd->cycles = cycles; |
266c6afa |
50 | |
51 | return ret; |
52 | } |
53 | |
b78efee2 |
54 | static int p32x_poll_undetect(struct poll_det *pd, int is_vdp) |
266c6afa |
55 | { |
b78efee2 |
56 | int ret = 0, flag = pd->flag; |
57 | if (is_vdp) |
be20816c |
58 | flag <<= 3; // VDP only |
59 | else |
60 | flag |= flag << 3; // both |
61 | if (Pico32x.emu_flags & flag) { |
62 | elprintf(EL_32X, "poll %02x -> %02x", Pico32x.emu_flags, Pico32x.emu_flags & ~flag); |
266c6afa |
63 | ret = 1; |
be20816c |
64 | } |
266c6afa |
65 | Pico32x.emu_flags &= ~flag; |
be20816c |
66 | pd->addr = pd->cnt = 0; |
266c6afa |
67 | return ret; |
68 | } |
69 | |
87accdf7 |
70 | void p32x_poll_event(int cpu_mask, int is_vdp) |
4ea707e1 |
71 | { |
87accdf7 |
72 | if (cpu_mask & 1) |
73 | p32x_poll_undetect(&sh2_poll[0], is_vdp); |
74 | if (cpu_mask & 2) |
75 | p32x_poll_undetect(&sh2_poll[1], is_vdp); |
4ea707e1 |
76 | } |
77 | |
974fdb5b |
78 | // SH2 faking |
b78efee2 |
79 | //#define FAKE_SH2 |
acd35d4c |
80 | int p32x_csum_faked; |
81 | #ifdef FAKE_SH2 |
974fdb5b |
82 | static const u16 comm_fakevals[] = { |
83 | 0x4d5f, 0x4f4b, // M_OK |
84 | 0x535f, 0x4f4b, // S_OK |
5e49c3a8 |
85 | 0x4D41, 0x5346, // MASF - Brutal Unleashed |
86 | 0x5331, 0x4d31, // Darxide |
87 | 0x5332, 0x4d32, |
88 | 0x5333, 0x4d33, |
89 | 0x0000, 0x0000, // eq for doom |
974fdb5b |
90 | 0x0002, // Mortal Kombat |
acd35d4c |
91 | // 0, // pad |
be2c4208 |
92 | }; |
acd35d4c |
93 | |
94 | static u32 sh2_comm_faker(u32 a) |
95 | { |
96 | static int f = 0; |
97 | if (a == 0x28 && !p32x_csum_faked) { |
98 | p32x_csum_faked = 1; |
99 | return *(unsigned short *)(Pico.rom + 0x18e); |
100 | } |
101 | if (f >= sizeof(comm_fakevals) / sizeof(comm_fakevals[0])) |
102 | f = 0; |
103 | return comm_fakevals[f++]; |
104 | } |
105 | #endif |
be2c4208 |
106 | |
4ea707e1 |
107 | // DMAC handling |
108 | static struct { |
109 | unsigned int sar0, dar0, tcr0; // src addr, dst addr, transfer count |
110 | unsigned int chcr0; // chan ctl |
111 | unsigned int sar1, dar1, tcr1; // same for chan 1 |
112 | unsigned int chcr1; |
113 | int pad[4]; |
114 | unsigned int dmaor; |
115 | } * dmac0; |
116 | |
117 | static void dma_68k2sh2_do(void) |
118 | { |
119 | unsigned short *dreqlen = &Pico32x.regs[0x10 / 2]; |
120 | int i; |
121 | |
122 | if (dmac0->tcr0 != *dreqlen) |
123 | elprintf(EL_32X|EL_ANOMALY, "tcr0 and dreq len differ: %d != %d", dmac0->tcr0, *dreqlen); |
124 | |
1b3f5844 |
125 | // HACK: assume bus is busy and SH2 is halted |
126 | // XXX: use different mechanism for this, not poll det |
127 | Pico32x.emu_flags |= P32XF_MSH2POLL; // id ? P32XF_SSH2POLL : P32XF_MSH2POLL; |
128 | |
4ea707e1 |
129 | for (i = 0; i < Pico32x.dmac_ptr && dmac0->tcr0 > 0; i++) { |
b78efee2 |
130 | extern void p32x_sh2_write16(u32 a, u32 d, int id); |
be20816c |
131 | elprintf(EL_32X, "dmaw [%08x] %04x, left %d", dmac0->dar0, Pico32x.dmac_fifo[i], *dreqlen); |
b78efee2 |
132 | p32x_sh2_write16(dmac0->dar0, Pico32x.dmac_fifo[i], 0); |
4ea707e1 |
133 | dmac0->dar0 += 2; |
134 | dmac0->tcr0--; |
135 | (*dreqlen)--; |
136 | } |
137 | |
138 | Pico32x.dmac_ptr = 0; // HACK |
139 | Pico32x.regs[6 / 2] &= ~P32XS_FULL; |
140 | if (*dreqlen == 0) |
141 | Pico32x.regs[6 / 2] &= ~P32XS_68S; // transfer complete |
be20816c |
142 | if (dmac0->tcr0 == 0) { |
4ea707e1 |
143 | dmac0->chcr0 |= 2; // DMA has ended normally |
be20816c |
144 | p32x_poll_undetect(&sh2_poll[0], 0); |
145 | } |
4ea707e1 |
146 | } |
147 | |
148 | // ------------------------------------------------------------------ |
b78efee2 |
149 | // 68k regs |
4ea707e1 |
150 | |
be2c4208 |
151 | static u32 p32x_reg_read16(u32 a) |
152 | { |
153 | a &= 0x3e; |
154 | |
87accdf7 |
155 | if (a == 2) // INTM, INTS |
156 | return ((Pico32x.sh2irqi[0] & P32XI_CMD) >> 4) | ((Pico32x.sh2irqi[1] & P32XI_CMD) >> 3); |
3cf9570b |
157 | #if 0 |
974fdb5b |
158 | if ((a & 0x30) == 0x20) |
acd35d4c |
159 | return sh2_comm_faker(a); |
266c6afa |
160 | #else |
be20816c |
161 | if ((a & 0x30) == 0x20 && p32x_poll_detect(&m68k_poll, a, SekCyclesDoneT(), 0)) { |
236990cf |
162 | SekEndTimeslice(16); |
266c6afa |
163 | } |
acd35d4c |
164 | #endif |
87accdf7 |
165 | |
db1d3564 |
166 | if ((a & 0x30) == 0x30) |
167 | return p32x_pwm_read16(a); |
974fdb5b |
168 | |
be2c4208 |
169 | return Pico32x.regs[a / 2]; |
170 | } |
171 | |
be2c4208 |
172 | static void p32x_reg_write8(u32 a, u32 d) |
173 | { |
acd35d4c |
174 | u16 *r = Pico32x.regs; |
be2c4208 |
175 | a &= 0x3f; |
176 | |
97d3f47f |
177 | // for things like bset on comm port |
178 | m68k_poll.cnt = 0; |
179 | |
acd35d4c |
180 | if (a == 1 && !(r[0] & 1)) { |
181 | r[0] |= 1; |
be2c4208 |
182 | Pico32xStartup(); |
183 | return; |
184 | } |
5e49c3a8 |
185 | |
acd35d4c |
186 | if (!(r[0] & 1)) |
5e49c3a8 |
187 | return; |
188 | |
acd35d4c |
189 | switch (a) { |
4ea707e1 |
190 | case 0: // adapter ctl |
acd35d4c |
191 | r[0] = (r[0] & 0x83) | ((d << 8) & P32XS_FM); |
1b3f5844 |
192 | return; |
4ea707e1 |
193 | case 3: // irq ctl |
194 | if ((d & 1) && !(Pico32x.sh2irqi[0] & P32XI_CMD)) { |
195 | Pico32x.sh2irqi[0] |= P32XI_CMD; |
196 | p32x_update_irls(); |
87accdf7 |
197 | SekEndRun(16); |
4ea707e1 |
198 | } |
b78efee2 |
199 | if ((d & 2) && !(Pico32x.sh2irqi[1] & P32XI_CMD)) { |
200 | Pico32x.sh2irqi[1] |= P32XI_CMD; |
201 | p32x_update_irls(); |
87accdf7 |
202 | SekEndRun(16); |
b78efee2 |
203 | } |
1b3f5844 |
204 | return; |
4ea707e1 |
205 | case 5: // bank |
acd35d4c |
206 | d &= 7; |
4ea707e1 |
207 | if (r[4 / 2] != d) { |
208 | r[4 / 2] = d; |
acd35d4c |
209 | bank_switch(d); |
210 | } |
1b3f5844 |
211 | return; |
4ea707e1 |
212 | case 7: // DREQ ctl |
97d3f47f |
213 | r[6 / 2] = (r[6 / 2] & P32XS_FULL) | (d & (P32XS_68S|P32XS_DMA|P32XS_RV)); |
1b3f5844 |
214 | return; |
87accdf7 |
215 | case 0x1b: // TV |
216 | r[0x1a / 2] = d; |
1b3f5844 |
217 | return; |
218 | } |
219 | |
220 | if ((a & 0x30) == 0x20) { |
221 | u8 *r8 = (u8 *)r; |
222 | r8[a ^ 1] = d; |
236990cf |
223 | p32x_poll_undetect(&sh2_poll[0], 0); |
224 | p32x_poll_undetect(&sh2_poll[1], 0); |
225 | // if some SH2 is busy waiting, it needs to see the result ASAP |
226 | if (SekCyclesLeftNoMCD > 32) |
227 | SekEndRun(32); |
1b3f5844 |
228 | return; |
5e49c3a8 |
229 | } |
230 | } |
231 | |
232 | static void p32x_reg_write16(u32 a, u32 d) |
233 | { |
acd35d4c |
234 | u16 *r = Pico32x.regs; |
235 | a &= 0x3e; |
236 | |
97d3f47f |
237 | // for things like bset on comm port |
238 | m68k_poll.cnt = 0; |
239 | |
acd35d4c |
240 | switch (a) { |
4ea707e1 |
241 | case 0x00: // adapter ctl |
acd35d4c |
242 | r[0] = (r[0] & 0x83) | (d & P32XS_FM); |
243 | return; |
4ea707e1 |
244 | case 0x10: // DREQ len |
245 | r[a / 2] = d & ~3; |
246 | return; |
247 | case 0x12: // FIFO reg |
248 | if (!(r[6 / 2] & P32XS_68S)) { |
249 | elprintf(EL_32X|EL_ANOMALY, "DREQ FIFO w16 without 68S?"); |
250 | return; |
251 | } |
252 | if (Pico32x.dmac_ptr < DMAC_FIFO_LEN) { |
253 | Pico32x.dmac_fifo[Pico32x.dmac_ptr++] = d; |
254 | if ((Pico32x.dmac_ptr & 3) == 0 && (dmac0->chcr0 & 3) == 1 && (dmac0->dmaor & 1)) |
255 | dma_68k2sh2_do(); |
256 | if (Pico32x.dmac_ptr == DMAC_FIFO_LEN) |
257 | r[6 / 2] |= P32XS_FULL; |
258 | } |
259 | break; |
acd35d4c |
260 | } |
261 | |
4ea707e1 |
262 | // DREQ src, dst |
263 | if ((a & 0x38) == 0x08) { |
264 | r[a / 2] = d; |
265 | return; |
266 | } |
267 | // comm port |
268 | else if ((a & 0x30) == 0x20 && r[a / 2] != d) { |
acd35d4c |
269 | r[a / 2] = d; |
236990cf |
270 | p32x_poll_undetect(&sh2_poll[0], 0); |
271 | p32x_poll_undetect(&sh2_poll[1], 0); |
272 | // same as for w8 |
273 | if (SekCyclesLeftNoMCD > 32) |
274 | SekEndRun(32); |
acd35d4c |
275 | return; |
276 | } |
db1d3564 |
277 | // PWM |
278 | else if ((a & 0x30) == 0x30) { |
279 | p32x_pwm_write16(a, d); |
280 | return; |
281 | } |
acd35d4c |
282 | |
5e49c3a8 |
283 | p32x_reg_write8(a + 1, d); |
be2c4208 |
284 | } |
285 | |
4ea707e1 |
286 | // ------------------------------------------------------------------ |
be2c4208 |
287 | // VDP regs |
288 | static u32 p32x_vdp_read16(u32 a) |
289 | { |
290 | a &= 0x0e; |
291 | |
292 | return Pico32x.vdp_regs[a / 2]; |
293 | } |
294 | |
be2c4208 |
295 | static void p32x_vdp_write8(u32 a, u32 d) |
296 | { |
974fdb5b |
297 | u16 *r = Pico32x.vdp_regs; |
be2c4208 |
298 | a &= 0x0f; |
299 | |
4ea707e1 |
300 | // for FEN checks between writes |
b78efee2 |
301 | sh2_poll[0].cnt = 0; |
4ea707e1 |
302 | |
974fdb5b |
303 | // TODO: verify what's writeable |
be2c4208 |
304 | switch (a) { |
974fdb5b |
305 | case 0x01: |
5e49c3a8 |
306 | // priority inversion is handled in palette |
307 | if ((r[0] ^ d) & P32XV_PRI) |
308 | Pico32x.dirty_pal = 1; |
974fdb5b |
309 | r[0] = (r[0] & P32XV_nPAL) | (d & 0xff); |
be20816c |
310 | break; |
311 | case 0x05: // fill len |
312 | r[4 / 2] = d & 0xff; |
974fdb5b |
313 | break; |
be2c4208 |
314 | case 0x0b: |
974fdb5b |
315 | d &= 1; |
316 | Pico32x.pending_fb = d; |
317 | // if we are blanking and FS bit is changing |
4ea707e1 |
318 | if (((r[0x0a/2] & P32XV_VBLK) || (r[0] & P32XV_Mx) == 0) && ((r[0x0a/2] ^ d) & P32XV_FS)) { |
974fdb5b |
319 | r[0x0a/2] ^= 1; |
320 | Pico32xSwapDRAM(d ^ 1); |
266c6afa |
321 | elprintf(EL_32X, "VDP FS: %d", r[0x0a/2] & P32XV_FS); |
be2c4208 |
322 | } |
323 | break; |
324 | } |
325 | } |
326 | |
974fdb5b |
327 | static void p32x_vdp_write16(u32 a, u32 d) |
328 | { |
be20816c |
329 | a &= 0x0e; |
330 | if (a == 6) { // fill start |
331 | Pico32x.vdp_regs[6 / 2] = d; |
332 | return; |
333 | } |
334 | if (a == 8) { // fill data |
335 | u16 *dram = Pico32xMem->dram[(Pico32x.vdp_regs[0x0a/2] & P32XV_FS) ^ 1]; |
1b3f5844 |
336 | int len = Pico32x.vdp_regs[4 / 2] + 1; |
be20816c |
337 | a = Pico32x.vdp_regs[6 / 2]; |
338 | while (len--) { |
339 | dram[a] = d; |
340 | a = (a & 0xff00) | ((a + 1) & 0xff); |
341 | } |
342 | Pico32x.vdp_regs[6 / 2] = a; |
343 | Pico32x.vdp_regs[8 / 2] = d; |
344 | return; |
345 | } |
346 | |
974fdb5b |
347 | p32x_vdp_write8(a | 1, d); |
348 | } |
349 | |
4ea707e1 |
350 | // ------------------------------------------------------------------ |
acd35d4c |
351 | // SH2 regs |
b78efee2 |
352 | |
353 | static u32 p32x_sh2reg_read16(u32 a, int cpuid) |
acd35d4c |
354 | { |
4ea707e1 |
355 | u16 *r = Pico32x.regs; |
356 | a &= 0xfe; // ? |
266c6afa |
357 | |
4ea707e1 |
358 | switch (a) { |
359 | case 0x00: // adapter/irq ctl |
87accdf7 |
360 | return (r[0] & P32XS_FM) | Pico32x.sh2_regs[0] | Pico32x.sh2irq_mask[cpuid]; |
c987bb5c |
361 | case 0x04: // H count (often as comm too) |
362 | if (p32x_poll_detect(&sh2_poll[cpuid], a, ash2_cycles_done(), 0)) |
363 | ash2_end_run(8); |
87accdf7 |
364 | return Pico32x.sh2_regs[4 / 2]; |
4ea707e1 |
365 | case 0x10: // DREQ len |
366 | return r[a / 2]; |
acd35d4c |
367 | } |
4ea707e1 |
368 | |
db1d3564 |
369 | // DREQ src, dst |
370 | if ((a & 0x38) == 0x08) |
4ea707e1 |
371 | return r[a / 2]; |
db1d3564 |
372 | // comm port |
373 | if ((a & 0x30) == 0x20) { |
be20816c |
374 | if (p32x_poll_detect(&sh2_poll[cpuid], a, ash2_cycles_done(), 0)) |
db1d3564 |
375 | ash2_end_run(8); |
376 | return r[a / 2]; |
377 | } |
378 | if ((a & 0x30) == 0x30) { |
379 | sh2_poll[cpuid].cnt = 0; |
380 | return p32x_pwm_read16(a); |
381 | } |
acd35d4c |
382 | |
383 | return 0; |
384 | } |
385 | |
b78efee2 |
386 | static void p32x_sh2reg_write8(u32 a, u32 d, int cpuid) |
acd35d4c |
387 | { |
4ea707e1 |
388 | a &= 0xff; |
87accdf7 |
389 | switch (a) { |
390 | case 0: // FM |
391 | Pico32x.regs[0] &= ~P32XS_FM; |
392 | Pico32x.regs[0] |= (d << 8) & P32XS_FM; |
1b3f5844 |
393 | return; |
87accdf7 |
394 | case 1: // |
395 | Pico32x.sh2irq_mask[cpuid] = d & 0x8f; |
396 | Pico32x.sh2_regs[0] &= ~0x80; |
397 | Pico32x.sh2_regs[0] |= d & 0x80; |
398 | p32x_update_irls(); |
1b3f5844 |
399 | return; |
87accdf7 |
400 | case 5: // H count |
401 | Pico32x.sh2_regs[4 / 2] = d & 0xff; |
c987bb5c |
402 | p32x_poll_undetect(&sh2_poll[cpuid ^ 1], 0); |
1b3f5844 |
403 | return; |
404 | } |
405 | |
406 | if ((a & 0x30) == 0x20) { |
407 | u8 *r8 = (u8 *)Pico32x.regs; |
408 | r8[a ^ 1] = d; |
409 | p32x_poll_undetect(&m68k_poll, 0); |
410 | p32x_poll_undetect(&sh2_poll[cpuid ^ 1], 0); |
411 | return; |
4ea707e1 |
412 | } |
acd35d4c |
413 | } |
414 | |
b78efee2 |
415 | static void p32x_sh2reg_write16(u32 a, u32 d, int cpuid) |
acd35d4c |
416 | { |
4ea707e1 |
417 | a &= 0xfe; |
acd35d4c |
418 | |
db1d3564 |
419 | // comm |
4ea707e1 |
420 | if ((a & 0x30) == 0x20 && Pico32x.regs[a/2] != d) { |
b78efee2 |
421 | Pico32x.regs[a / 2] = d; |
422 | p32x_poll_undetect(&m68k_poll, 0); |
423 | p32x_poll_undetect(&sh2_poll[cpuid ^ 1], 0); |
acd35d4c |
424 | return; |
425 | } |
db1d3564 |
426 | // PWM |
427 | else if ((a & 0x30) == 0x30) { |
428 | p32x_pwm_write16(a, d); |
429 | return; |
430 | } |
acd35d4c |
431 | |
4ea707e1 |
432 | switch (a) { |
87accdf7 |
433 | case 0: // FM |
434 | Pico32x.regs[0] &= ~P32XS_FM; |
435 | Pico32x.regs[0] |= d & P32XS_FM; |
436 | break; |
4ea707e1 |
437 | case 0x14: Pico32x.sh2irqs &= ~P32XI_VRES; goto irls; |
438 | case 0x16: Pico32x.sh2irqs &= ~P32XI_VINT; goto irls; |
439 | case 0x18: Pico32x.sh2irqs &= ~P32XI_HINT; goto irls; |
b78efee2 |
440 | case 0x1a: Pico32x.sh2irqi[cpuid] &= ~P32XI_CMD; goto irls; |
be20816c |
441 | case 0x1c: |
442 | Pico32x.sh2irqs &= ~P32XI_PWM; |
1d7a28a7 |
443 | p32x_timers_do(0); |
be20816c |
444 | goto irls; |
4ea707e1 |
445 | } |
446 | |
b78efee2 |
447 | p32x_sh2reg_write8(a | 1, d, cpuid); |
4ea707e1 |
448 | return; |
449 | |
450 | irls: |
451 | p32x_update_irls(); |
452 | } |
453 | |
87accdf7 |
454 | // ------------------------------------------------------------------ |
455 | // SH2 internal peripherals |
1d7a28a7 |
456 | // we keep them in little endian format |
87accdf7 |
457 | static u32 sh2_peripheral_read8(u32 a, int id) |
458 | { |
459 | u8 *r = (void *)Pico32xMem->sh2_peri_regs[id]; |
460 | u32 d; |
461 | |
462 | a &= 0x1ff; |
1d7a28a7 |
463 | d = PREG8(r, a); |
87accdf7 |
464 | |
465 | elprintf(EL_32X, "%csh2 peri r8 [%08x] %02x @%06x", id ? 's' : 'm', a | ~0x1ff, d, sh2_pc(id)); |
466 | return d; |
467 | } |
468 | |
1d7a28a7 |
469 | static u32 sh2_peripheral_read16(u32 a, int id) |
470 | { |
471 | u16 *r = (void *)Pico32xMem->sh2_peri_regs[id]; |
472 | u32 d; |
473 | |
474 | a &= 0x1ff; |
475 | d = r[(a / 2) ^ 1]; |
476 | |
477 | elprintf(EL_32X, "%csh2 peri r16 [%08x] %04x @%06x", id ? 's' : 'm', a | ~0x1ff, d, sh2_pc(id)); |
478 | return d; |
479 | } |
480 | |
87accdf7 |
481 | static u32 sh2_peripheral_read32(u32 a, int id) |
4ea707e1 |
482 | { |
483 | u32 d; |
484 | a &= 0x1fc; |
97d3f47f |
485 | d = Pico32xMem->sh2_peri_regs[id][a / 4]; |
4ea707e1 |
486 | |
97d3f47f |
487 | elprintf(EL_32X, "%csh2 peri r32 [%08x] %08x @%06x", id ? 's' : 'm', a | ~0x1ff, d, sh2_pc(id)); |
4ea707e1 |
488 | return d; |
acd35d4c |
489 | } |
490 | |
87accdf7 |
491 | static void sh2_peripheral_write8(u32 a, u32 d, int id) |
492 | { |
493 | u8 *r = (void *)Pico32xMem->sh2_peri_regs[id]; |
494 | elprintf(EL_32X, "%csh2 peri w8 [%08x] %02x @%06x", id ? 's' : 'm', a, d, sh2_pc(id)); |
495 | |
496 | a &= 0x1ff; |
1d7a28a7 |
497 | PREG8(r, a) = d; |
498 | |
499 | // X-men SCI hack |
500 | if ((a == 2 && (d & 0x20)) || // transmiter enabled |
501 | (a == 4 && !(d & 0x80))) { // valid data in TDR |
502 | void *oregs = Pico32xMem->sh2_peri_regs[id ^ 1]; |
503 | if ((PREG8(oregs, 2) & 0x50) == 0x50) { // receiver + irq enabled |
504 | int level = PREG8(oregs, 0x60) >> 4; |
505 | int vector = PREG8(oregs, 0x63) & 0x7f; |
506 | elprintf(EL_32X, "%csh2 SCI recv irq (%d, %d)", (id ^ 1) ? 's' : 'm', level, vector); |
507 | sh2_internal_irq(&sh2s[id ^ 1], level, vector); |
508 | } |
509 | } |
510 | } |
511 | |
512 | static void sh2_peripheral_write16(u32 a, u32 d, int id) |
513 | { |
514 | u16 *r = (void *)Pico32xMem->sh2_peri_regs[id]; |
515 | elprintf(EL_32X, "%csh2 peri w16 [%08x] %04x @%06x", id ? 's' : 'm', a, d, sh2_pc(id)); |
516 | |
517 | a &= 0x1ff; |
518 | |
519 | // evil WDT |
520 | if (a == 0x80) { |
521 | if ((d & 0xff00) == 0xa500) { // WTCSR |
522 | PREG8(r, 0x80) = d; |
523 | p32x_timers_recalc(); |
524 | } |
525 | if ((d & 0xff00) == 0x5a00) // WTCNT |
526 | PREG8(r, 0x81) = d; |
527 | return; |
528 | } |
529 | |
530 | r[(a / 2) ^ 1] = d; |
87accdf7 |
531 | } |
532 | |
533 | static void sh2_peripheral_write32(u32 a, u32 d, int id) |
4ea707e1 |
534 | { |
be20816c |
535 | u32 *r = Pico32xMem->sh2_peri_regs[id]; |
b78efee2 |
536 | elprintf(EL_32X, "%csh2 peri w32 [%08x] %08x @%06x", id ? 's' : 'm', a, d, sh2_pc(id)); |
4ea707e1 |
537 | |
538 | a &= 0x1fc; |
539 | r[a / 4] = d; |
540 | |
97d3f47f |
541 | switch (a) { |
be20816c |
542 | // division unit (TODO: verify): |
97d3f47f |
543 | case 0x104: // DVDNT: divident L, starts divide |
544 | elprintf(EL_32X, "%csh2 divide %08x / %08x", id ? 's' : 'm', d, r[0x100 / 4]); |
545 | if (r[0x100 / 4]) { |
be20816c |
546 | signed int divisor = r[0x100 / 4]; |
547 | r[0x118 / 4] = r[0x110 / 4] = (signed int)d % divisor; |
548 | r[0x104 / 4] = r[0x11c / 4] = r[0x114 / 4] = (signed int)d / divisor; |
97d3f47f |
549 | } |
550 | break; |
551 | case 0x114: |
552 | elprintf(EL_32X, "%csh2 divide %08x%08x / %08x @%08x", |
553 | id ? 's' : 'm', r[0x110 / 4], d, r[0x100 / 4], sh2_pc(id)); |
554 | if (r[0x100 / 4]) { |
be20816c |
555 | signed long long divident = (signed long long)r[0x110 / 4] << 32 | d; |
556 | signed int divisor = r[0x100 / 4]; |
97d3f47f |
557 | // XXX: undocumented mirroring to 0x118,0x11c? |
be20816c |
558 | r[0x118 / 4] = r[0x110 / 4] = divident % divisor; |
559 | r[0x11c / 4] = r[0x114 / 4] = divident / divisor; |
97d3f47f |
560 | } |
561 | break; |
562 | } |
563 | |
4ea707e1 |
564 | if ((a == 0x1b0 || a == 0x18c) && (dmac0->chcr0 & 3) == 1 && (dmac0->dmaor & 1)) { |
565 | elprintf(EL_32X, "sh2 DMA %08x -> %08x, cnt %d, chcr %04x @%06x", |
b78efee2 |
566 | dmac0->sar0, dmac0->dar0, dmac0->tcr0, dmac0->chcr0, sh2_pc(id)); |
4ea707e1 |
567 | dmac0->tcr0 &= 0xffffff; |
be20816c |
568 | |
1b3f5844 |
569 | // HACK: assume 68k starts writing soon and end the timeslice |
570 | ash2_end_run(16); |
be20816c |
571 | |
4ea707e1 |
572 | // DREQ is only sent after first 4 words are written. |
573 | // we do multiple of 4 words to avoid messing up alignment |
574 | if (dmac0->sar0 == 0x20004012 && Pico32x.dmac_ptr && (Pico32x.dmac_ptr & 3) == 0) { |
575 | elprintf(EL_32X, "68k -> sh2 DMA"); |
576 | dma_68k2sh2_do(); |
577 | } |
578 | } |
579 | } |
580 | |
581 | // ------------------------------------------------------------------ |
be2c4208 |
582 | // default 32x handlers |
583 | u32 PicoRead8_32x(u32 a) |
584 | { |
585 | u32 d = 0; |
586 | if ((a & 0xffc0) == 0x5100) { // a15100 |
587 | d = p32x_reg_read16(a); |
588 | goto out_16to8; |
589 | } |
590 | |
974fdb5b |
591 | if (!(Pico32x.regs[0] & 1)) |
592 | goto no_vdp; |
593 | |
594 | if ((a & 0xfff0) == 0x5180) { // a15180 |
be2c4208 |
595 | d = p32x_vdp_read16(a); |
596 | goto out_16to8; |
597 | } |
598 | |
974fdb5b |
599 | if ((a & 0xfe00) == 0x5200) { // a15200 |
600 | d = Pico32xMem->pal[(a & 0x1ff) / 2]; |
601 | goto out_16to8; |
602 | } |
603 | |
604 | no_vdp: |
be2c4208 |
605 | if ((a & 0xfffc) == 0x30ec) { // a130ec |
606 | d = str_mars[a & 3]; |
607 | goto out; |
608 | } |
609 | |
610 | elprintf(EL_UIO, "m68k unmapped r8 [%06x] @%06x", a, SekPc); |
611 | return d; |
612 | |
613 | out_16to8: |
614 | if (a & 1) |
615 | d &= 0xff; |
616 | else |
617 | d >>= 8; |
618 | |
619 | out: |
620 | elprintf(EL_32X, "m68k 32x r8 [%06x] %02x @%06x", a, d, SekPc); |
621 | return d; |
622 | } |
623 | |
624 | u32 PicoRead16_32x(u32 a) |
625 | { |
626 | u32 d = 0; |
627 | if ((a & 0xffc0) == 0x5100) { // a15100 |
628 | d = p32x_reg_read16(a); |
629 | goto out; |
630 | } |
631 | |
974fdb5b |
632 | if (!(Pico32x.regs[0] & 1)) |
633 | goto no_vdp; |
634 | |
635 | if ((a & 0xfff0) == 0x5180) { // a15180 |
be2c4208 |
636 | d = p32x_vdp_read16(a); |
637 | goto out; |
638 | } |
639 | |
974fdb5b |
640 | if ((a & 0xfe00) == 0x5200) { // a15200 |
641 | d = Pico32xMem->pal[(a & 0x1ff) / 2]; |
642 | goto out; |
643 | } |
644 | |
645 | no_vdp: |
be2c4208 |
646 | if ((a & 0xfffc) == 0x30ec) { // a130ec |
647 | d = !(a & 2) ? ('M'<<8)|'A' : ('R'<<8)|'S'; |
648 | goto out; |
649 | } |
650 | |
651 | elprintf(EL_UIO, "m68k unmapped r16 [%06x] @%06x", a, SekPc); |
652 | return d; |
653 | |
654 | out: |
655 | elprintf(EL_32X, "m68k 32x r16 [%06x] %04x @%06x", a, d, SekPc); |
656 | return d; |
657 | } |
658 | |
659 | void PicoWrite8_32x(u32 a, u32 d) |
660 | { |
661 | if ((a & 0xfc00) == 0x5000) |
662 | elprintf(EL_32X, "m68k 32x w8 [%06x] %02x @%06x", a, d & 0xff, SekPc); |
663 | |
664 | if ((a & 0xffc0) == 0x5100) { // a15100 |
665 | p32x_reg_write8(a, d); |
666 | return; |
667 | } |
668 | |
974fdb5b |
669 | if (!(Pico32x.regs[0] & 1)) |
670 | goto no_vdp; |
671 | |
672 | if ((a & 0xfff0) == 0x5180) { // a15180 |
be2c4208 |
673 | p32x_vdp_write8(a, d); |
674 | return; |
675 | } |
676 | |
974fdb5b |
677 | // TODO: verify |
678 | if ((a & 0xfe00) == 0x5200) { // a15200 |
679 | elprintf(EL_32X|EL_ANOMALY, "m68k 32x PAL w8 [%06x] %02x @%06x", a, d & 0xff, SekPc); |
680 | ((u8 *)Pico32xMem->pal)[(a & 0x1ff) ^ 1] = d; |
681 | Pico32x.dirty_pal = 1; |
682 | return; |
683 | } |
684 | |
685 | no_vdp: |
be2c4208 |
686 | elprintf(EL_UIO, "m68k unmapped w8 [%06x] %02x @%06x", a, d & 0xff, SekPc); |
687 | } |
688 | |
689 | void PicoWrite16_32x(u32 a, u32 d) |
690 | { |
691 | if ((a & 0xfc00) == 0x5000) |
692 | elprintf(EL_UIO, "m68k 32x w16 [%06x] %04x @%06x", a, d & 0xffff, SekPc); |
693 | |
694 | if ((a & 0xffc0) == 0x5100) { // a15100 |
695 | p32x_reg_write16(a, d); |
696 | return; |
697 | } |
698 | |
974fdb5b |
699 | if (!(Pico32x.regs[0] & 1)) |
700 | goto no_vdp; |
701 | |
702 | if ((a & 0xfff0) == 0x5180) { // a15180 |
be2c4208 |
703 | p32x_vdp_write16(a, d); |
704 | return; |
705 | } |
706 | |
974fdb5b |
707 | if ((a & 0xfe00) == 0x5200) { // a15200 |
708 | Pico32xMem->pal[(a & 0x1ff) / 2] = d; |
709 | Pico32x.dirty_pal = 1; |
710 | return; |
711 | } |
712 | |
713 | no_vdp: |
be2c4208 |
714 | elprintf(EL_UIO, "m68k unmapped w16 [%06x] %04x @%06x", a, d & 0xffff, SekPc); |
715 | } |
716 | |
717 | // hint vector is writeable |
718 | static void PicoWrite8_hint(u32 a, u32 d) |
719 | { |
720 | if ((a & 0xfffc) == 0x0070) { |
721 | Pico32xMem->m68k_rom[a ^ 1] = d; |
722 | return; |
723 | } |
724 | |
725 | elprintf(EL_UIO, "m68k unmapped w8 [%06x] %02x @%06x", a, d & 0xff, SekPc); |
726 | } |
727 | |
728 | static void PicoWrite16_hint(u32 a, u32 d) |
729 | { |
730 | if ((a & 0xfffc) == 0x0070) { |
731 | ((u16 *)Pico32xMem->m68k_rom)[a/2] = d; |
732 | return; |
733 | } |
734 | |
735 | elprintf(EL_UIO, "m68k unmapped w16 [%06x] %04x @%06x", a, d & 0xffff, SekPc); |
736 | } |
737 | |
974fdb5b |
738 | void Pico32xSwapDRAM(int b) |
739 | { |
740 | cpu68k_map_set(m68k_read8_map, 0x840000, 0x85ffff, Pico32xMem->dram[b], 0); |
741 | cpu68k_map_set(m68k_read16_map, 0x840000, 0x85ffff, Pico32xMem->dram[b], 0); |
742 | cpu68k_map_set(m68k_write8_map, 0x840000, 0x85ffff, Pico32xMem->dram[b], 0); |
743 | cpu68k_map_set(m68k_write16_map, 0x840000, 0x85ffff, Pico32xMem->dram[b], 0); |
744 | } |
745 | |
5e49c3a8 |
746 | static void bank_switch(int b) |
747 | { |
748 | unsigned int rs, bank; |
749 | |
750 | bank = b << 20; |
751 | if (bank >= Pico.romsize) { |
752 | elprintf(EL_32X|EL_ANOMALY, "missing bank @ %06x", bank); |
753 | return; |
754 | } |
755 | |
756 | // 32X ROM (unbanked, XXX: consider mirroring?) |
757 | rs = (Pico.romsize + M68K_BANK_MASK) & ~M68K_BANK_MASK; |
758 | rs -= bank; |
759 | if (rs > 0x100000) |
760 | rs = 0x100000; |
761 | cpu68k_map_set(m68k_read8_map, 0x900000, 0x900000 + rs - 1, Pico.rom + bank, 0); |
762 | cpu68k_map_set(m68k_read16_map, 0x900000, 0x900000 + rs - 1, Pico.rom + bank, 0); |
763 | |
764 | elprintf(EL_32X, "bank %06x-%06x -> %06x", 0x900000, 0x900000 + rs - 1, bank); |
765 | } |
766 | |
acd35d4c |
767 | // ----------------------------------------------------------------- |
768 | // SH2 |
769 | // ----------------------------------------------------------------- |
770 | |
b78efee2 |
771 | u32 p32x_sh2_read8(u32 a, int id) |
acd35d4c |
772 | { |
773 | u32 d = 0; |
4ea707e1 |
774 | |
b78efee2 |
775 | if (id == 0 && a < sizeof(Pico32xMem->sh2_rom_m)) |
acd35d4c |
776 | return Pico32xMem->sh2_rom_m[a ^ 1]; |
b78efee2 |
777 | if (id == 1 && a < sizeof(Pico32xMem->sh2_rom_s)) |
778 | return Pico32xMem->sh2_rom_s[a ^ 1]; |
acd35d4c |
779 | |
87accdf7 |
780 | if ((a & 0xdffc0000) == 0x06000000) |
acd35d4c |
781 | return Pico32xMem->sdram[(a & 0x3ffff) ^ 1]; |
782 | |
87accdf7 |
783 | if ((a & 0xdfc00000) == 0x02000000) |
acd35d4c |
784 | if ((a & 0x003fffff) < Pico.romsize) |
785 | return Pico.rom[(a & 0x3fffff) ^ 1]; |
786 | |
b78efee2 |
787 | if ((a & ~0xfff) == 0xc0000000) |
788 | return Pico32xMem->data_array[id][(a & 0xfff) ^ 1]; |
789 | |
c987bb5c |
790 | if ((a & 0xdffc0000) == 0x04000000) { |
791 | /* XXX: overwrite readable as normal? */ |
97d3f47f |
792 | u8 *dram = (u8 *)Pico32xMem->dram[(Pico32x.vdp_regs[0x0a/2] & P32XV_FS) ^ 1]; |
793 | return dram[(a & 0x1ffff) ^ 1]; |
794 | } |
795 | |
87accdf7 |
796 | if ((a & 0xdfffff00) == 0x4000) { |
b78efee2 |
797 | d = p32x_sh2reg_read16(a, id); |
db1d3564 |
798 | goto out_16to8; |
acd35d4c |
799 | } |
800 | |
87accdf7 |
801 | if ((a & 0xdfffff00) == 0x4100) { |
acd35d4c |
802 | d = p32x_vdp_read16(a); |
be20816c |
803 | if (p32x_poll_detect(&sh2_poll[id], a, ash2_cycles_done(), 1)) |
db1d3564 |
804 | ash2_end_run(8); |
805 | goto out_16to8; |
acd35d4c |
806 | } |
807 | |
87accdf7 |
808 | if ((a & 0xdfffff00) == 0x4200) { |
acd35d4c |
809 | d = Pico32xMem->pal[(a & 0x1ff) / 2]; |
810 | goto out_16to8; |
811 | } |
812 | |
87accdf7 |
813 | if ((a & 0xfffffe00) == 0xfffffe00) |
814 | return sh2_peripheral_read8(a, id); |
815 | |
b78efee2 |
816 | elprintf(EL_UIO, "%csh2 unmapped r8 [%08x] %02x @%06x", |
817 | id ? 's' : 'm', a, d, sh2_pc(id)); |
acd35d4c |
818 | return d; |
819 | |
820 | out_16to8: |
821 | if (a & 1) |
822 | d &= 0xff; |
823 | else |
824 | d >>= 8; |
825 | |
b78efee2 |
826 | elprintf(EL_32X, "%csh2 r8 [%08x] %02x @%06x", |
827 | id ? 's' : 'm', a, d, sh2_pc(id)); |
acd35d4c |
828 | return d; |
829 | } |
830 | |
b78efee2 |
831 | u32 p32x_sh2_read16(u32 a, int id) |
acd35d4c |
832 | { |
833 | u32 d = 0; |
3cf9570b |
834 | |
b78efee2 |
835 | if (id == 0 && a < sizeof(Pico32xMem->sh2_rom_m)) |
acd35d4c |
836 | return *(u16 *)(Pico32xMem->sh2_rom_m + a); |
b78efee2 |
837 | if (id == 1 && a < sizeof(Pico32xMem->sh2_rom_s)) |
838 | return *(u16 *)(Pico32xMem->sh2_rom_s + a); |
acd35d4c |
839 | |
87accdf7 |
840 | if ((a & 0xdffc0000) == 0x06000000) |
acd35d4c |
841 | return ((u16 *)Pico32xMem->sdram)[(a & 0x3ffff) / 2]; |
842 | |
87accdf7 |
843 | if ((a & 0xdfc00000) == 0x02000000) |
acd35d4c |
844 | if ((a & 0x003fffff) < Pico.romsize) |
845 | return ((u16 *)Pico.rom)[(a & 0x3fffff) / 2]; |
846 | |
b78efee2 |
847 | if ((a & ~0xfff) == 0xc0000000) |
848 | return ((u16 *)Pico32xMem->data_array[id])[(a & 0xfff) / 2]; |
849 | |
87accdf7 |
850 | if ((a & 0xdffe0000) == 0x04000000) |
97d3f47f |
851 | return Pico32xMem->dram[(Pico32x.vdp_regs[0x0a/2] & P32XV_FS) ^ 1][(a & 0x1ffff) / 2]; |
852 | |
87accdf7 |
853 | if ((a & 0xdfffff00) == 0x4000) { |
b78efee2 |
854 | d = p32x_sh2reg_read16(a, id); |
1b3f5844 |
855 | if (!(EL_LOGMASK & EL_PWM) && (a & 0x30) == 0x30) // hide PWM |
856 | return d; |
db1d3564 |
857 | goto out; |
acd35d4c |
858 | } |
859 | |
87accdf7 |
860 | if ((a & 0xdfffff00) == 0x4100) { |
acd35d4c |
861 | d = p32x_vdp_read16(a); |
be20816c |
862 | if (p32x_poll_detect(&sh2_poll[id], a, ash2_cycles_done(), 1)) |
db1d3564 |
863 | ash2_end_run(8); |
864 | goto out; |
acd35d4c |
865 | } |
866 | |
87accdf7 |
867 | if ((a & 0xdfffff00) == 0x4200) { |
acd35d4c |
868 | d = Pico32xMem->pal[(a & 0x1ff) / 2]; |
869 | goto out; |
870 | } |
871 | |
1d7a28a7 |
872 | if ((a & 0xfffffe00) == 0xfffffe00) |
873 | return sh2_peripheral_read16(a, id); |
874 | |
b78efee2 |
875 | elprintf(EL_UIO, "%csh2 unmapped r16 [%08x] %04x @%06x", |
876 | id ? 's' : 'm', a, d, sh2_pc(id)); |
acd35d4c |
877 | return d; |
878 | |
879 | out: |
b78efee2 |
880 | elprintf(EL_32X, "%csh2 r16 [%08x] %04x @%06x", |
881 | id ? 's' : 'm', a, d, sh2_pc(id)); |
acd35d4c |
882 | return d; |
883 | } |
884 | |
b78efee2 |
885 | u32 p32x_sh2_read32(u32 a, int id) |
acd35d4c |
886 | { |
4ea707e1 |
887 | if ((a & 0xfffffe00) == 0xfffffe00) |
87accdf7 |
888 | return sh2_peripheral_read32(a, id); |
4ea707e1 |
889 | |
acd35d4c |
890 | // elprintf(EL_UIO, "sh2 r32 [%08x] %08x @%06x", a, d, ash2_pc()); |
b78efee2 |
891 | return (p32x_sh2_read16(a, id) << 16) | p32x_sh2_read16(a + 2, id); |
acd35d4c |
892 | } |
893 | |
b78efee2 |
894 | void p32x_sh2_write8(u32 a, u32 d, int id) |
acd35d4c |
895 | { |
87accdf7 |
896 | if ((a & 0xdffffc00) == 0x4000) |
b78efee2 |
897 | elprintf(EL_32X, "%csh2 w8 [%08x] %02x @%06x", |
898 | id ? 's' : 'm', a, d & 0xff, sh2_pc(id)); |
acd35d4c |
899 | |
87accdf7 |
900 | if ((a & 0xdffc0000) == 0x06000000) { |
acd35d4c |
901 | Pico32xMem->sdram[(a & 0x3ffff) ^ 1] = d; |
902 | return; |
903 | } |
904 | |
87accdf7 |
905 | if ((a & 0xdffc0000) == 0x04000000) { |
906 | u8 *dram; |
907 | if (!(a & 0x20000) || d) { |
908 | dram = (u8 *)Pico32xMem->dram[(Pico32x.vdp_regs[0x0a/2] & P32XV_FS) ^ 1]; |
909 | dram[(a & 0x1ffff) ^ 1] = d; |
87accdf7 |
910 | } |
c987bb5c |
911 | return; |
266c6afa |
912 | } |
913 | |
b78efee2 |
914 | if ((a & ~0xfff) == 0xc0000000) { |
915 | Pico32xMem->data_array[id][(a & 0xfff) ^ 1] = d; |
916 | return; |
917 | } |
918 | |
87accdf7 |
919 | if ((a & 0xdfffff00) == 0x4100) { |
acd35d4c |
920 | p32x_vdp_write8(a, d); |
921 | return; |
922 | } |
923 | |
87accdf7 |
924 | if ((a & 0xdfffff00) == 0x4000) { |
b78efee2 |
925 | p32x_sh2reg_write8(a, d, id); |
acd35d4c |
926 | return; |
927 | } |
928 | |
87accdf7 |
929 | if ((a & 0xfffffe00) == 0xfffffe00) { |
930 | sh2_peripheral_write8(a, d, id); |
931 | return; |
932 | } |
933 | |
b78efee2 |
934 | elprintf(EL_UIO, "%csh2 unmapped w8 [%08x] %02x @%06x", |
935 | id ? 's' : 'm', a, d & 0xff, sh2_pc(id)); |
acd35d4c |
936 | } |
937 | |
b78efee2 |
938 | void p32x_sh2_write16(u32 a, u32 d, int id) |
acd35d4c |
939 | { |
1b3f5844 |
940 | if ((a & 0xdffffc00) == 0x4000 && ((EL_LOGMASK & EL_PWM) || (a & 0x30) != 0x30)) // hide PWM |
b78efee2 |
941 | elprintf(EL_32X, "%csh2 w16 [%08x] %04x @%06x", |
942 | id ? 's' : 'm', a, d & 0xffff, sh2_pc(id)); |
acd35d4c |
943 | |
87accdf7 |
944 | // ignore "Associative purge space" |
945 | if ((a & 0xf8000000) == 0x40000000) |
946 | return; |
947 | |
948 | if ((a & 0xdffc0000) == 0x06000000) { |
acd35d4c |
949 | ((u16 *)Pico32xMem->sdram)[(a & 0x3ffff) / 2] = d; |
950 | return; |
951 | } |
952 | |
b78efee2 |
953 | if ((a & ~0xfff) == 0xc0000000) { |
954 | ((u16 *)Pico32xMem->data_array[id])[(a & 0xfff) / 2] = d; |
955 | return; |
956 | } |
957 | |
87accdf7 |
958 | if ((a & 0xdffc0000) == 0x04000000) { |
959 | u16 *pd = &Pico32xMem->dram[(Pico32x.vdp_regs[0x0a/2] & P32XV_FS) ^ 1][(a & 0x1ffff) / 2]; |
960 | if (!(a & 0x20000)) { |
961 | *pd = d; |
962 | return; |
963 | } |
964 | // overwrite |
965 | if (!(d & 0xff00)) d |= *pd & 0xff00; |
966 | if (!(d & 0x00ff)) d |= *pd & 0x00ff; |
967 | *pd = d; |
266c6afa |
968 | return; |
969 | } |
970 | |
87accdf7 |
971 | if ((a & 0xdfffff00) == 0x4100) { |
be20816c |
972 | sh2_poll[id].cnt = 0; // for poll before VDP accesses |
acd35d4c |
973 | p32x_vdp_write16(a, d); |
974 | return; |
975 | } |
976 | |
87accdf7 |
977 | if ((a & 0xdffffe00) == 0x4200) { |
acd35d4c |
978 | Pico32xMem->pal[(a & 0x1ff) / 2] = d; |
979 | Pico32x.dirty_pal = 1; |
980 | return; |
981 | } |
982 | |
87accdf7 |
983 | if ((a & 0xdfffff00) == 0x4000) { |
b78efee2 |
984 | p32x_sh2reg_write16(a, d, id); |
acd35d4c |
985 | return; |
986 | } |
987 | |
1d7a28a7 |
988 | if ((a & 0xfffffe00) == 0xfffffe00) { |
989 | sh2_peripheral_write16(a, d, id); |
990 | return; |
991 | } |
992 | |
b78efee2 |
993 | elprintf(EL_UIO, "%csh2 unmapped w16 [%08x] %04x @%06x", |
994 | id ? 's' : 'm', a, d & 0xffff, sh2_pc(id)); |
acd35d4c |
995 | } |
996 | |
b78efee2 |
997 | void p32x_sh2_write32(u32 a, u32 d, int id) |
acd35d4c |
998 | { |
4ea707e1 |
999 | if ((a & 0xfffffe00) == 0xfffffe00) { |
87accdf7 |
1000 | sh2_peripheral_write32(a, d, id); |
4ea707e1 |
1001 | return; |
1002 | } |
1003 | |
b78efee2 |
1004 | p32x_sh2_write16(a, d >> 16, id); |
1005 | p32x_sh2_write16(a + 2, d, id); |
acd35d4c |
1006 | } |
1007 | |
be2c4208 |
1008 | #define HWSWAP(x) (((x) << 16) | ((x) >> 16)) |
1009 | void PicoMemSetup32x(void) |
1010 | { |
1011 | unsigned short *ps; |
1012 | unsigned int *pl; |
5e49c3a8 |
1013 | unsigned int rs; |
be2c4208 |
1014 | int i; |
1015 | |
1016 | Pico32xMem = calloc(1, sizeof(*Pico32xMem)); |
1017 | if (Pico32xMem == NULL) { |
1018 | elprintf(EL_STATUS, "OOM"); |
1019 | return; |
1020 | } |
1021 | |
4ea707e1 |
1022 | dmac0 = (void *)&Pico32xMem->sh2_peri_regs[0][0x180 / 4]; |
1023 | |
be2c4208 |
1024 | // generate 68k ROM |
1025 | ps = (unsigned short *)Pico32xMem->m68k_rom; |
1026 | pl = (unsigned int *)Pico32xMem->m68k_rom; |
1027 | for (i = 1; i < 0xc0/4; i++) |
974fdb5b |
1028 | pl[i] = HWSWAP(0x880200 + (i - 1) * 6); |
be2c4208 |
1029 | |
1030 | // fill with nops |
1031 | for (i = 0xc0/2; i < 0x100/2; i++) |
1032 | ps[i] = 0x4e71; |
1033 | |
5e49c3a8 |
1034 | #if 0 |
be2c4208 |
1035 | ps[0xc0/2] = 0x46fc; |
1036 | ps[0xc2/2] = 0x2700; // move #0x2700,sr |
1037 | ps[0xfe/2] = 0x60fe; // jump to self |
5e49c3a8 |
1038 | #else |
1039 | ps[0xfe/2] = 0x4e75; // rts |
1040 | #endif |
be2c4208 |
1041 | |
1042 | // fill remaining mem with ROM |
974fdb5b |
1043 | memcpy(Pico32xMem->m68k_rom + 0x100, Pico.rom + 0x100, sizeof(Pico32xMem->m68k_rom) - 0x100); |
be2c4208 |
1044 | |
acd35d4c |
1045 | // 32X ROM |
1046 | // TODO: move |
1047 | { |
1048 | FILE *f = fopen("32X_M_BIOS.BIN", "rb"); |
1049 | int i; |
1050 | if (f == NULL) { |
b78efee2 |
1051 | printf("missing 32X_M_BIOS.BIN\n"); |
acd35d4c |
1052 | exit(1); |
1053 | } |
1054 | fread(Pico32xMem->sh2_rom_m, 1, sizeof(Pico32xMem->sh2_rom_m), f); |
1055 | fclose(f); |
b78efee2 |
1056 | f = fopen("32X_S_BIOS.BIN", "rb"); |
1057 | if (f == NULL) { |
1058 | printf("missing 32X_S_BIOS.BIN\n"); |
1059 | exit(1); |
1060 | } |
1061 | fread(Pico32xMem->sh2_rom_s, 1, sizeof(Pico32xMem->sh2_rom_s), f); |
1062 | fclose(f); |
1063 | // byteswap |
acd35d4c |
1064 | for (i = 0; i < sizeof(Pico32xMem->sh2_rom_m); i += 2) { |
1065 | int t = Pico32xMem->sh2_rom_m[i]; |
1066 | Pico32xMem->sh2_rom_m[i] = Pico32xMem->sh2_rom_m[i + 1]; |
1067 | Pico32xMem->sh2_rom_m[i + 1] = t; |
1068 | } |
b78efee2 |
1069 | for (i = 0; i < sizeof(Pico32xMem->sh2_rom_s); i += 2) { |
1070 | int t = Pico32xMem->sh2_rom_s[i]; |
1071 | Pico32xMem->sh2_rom_s[i] = Pico32xMem->sh2_rom_s[i + 1]; |
1072 | Pico32xMem->sh2_rom_s[i + 1] = t; |
1073 | } |
acd35d4c |
1074 | } |
1075 | |
be2c4208 |
1076 | // cartridge area becomes unmapped |
1077 | // XXX: we take the easy way and don't unmap ROM, |
1078 | // so that we can avoid handling the RV bit. |
1079 | // m68k_map_unmap(0x000000, 0x3fffff); |
1080 | |
1081 | // MD ROM area |
974fdb5b |
1082 | rs = sizeof(Pico32xMem->m68k_rom); |
1083 | cpu68k_map_set(m68k_read8_map, 0x000000, rs - 1, Pico32xMem->m68k_rom, 0); |
1084 | cpu68k_map_set(m68k_read16_map, 0x000000, rs - 1, Pico32xMem->m68k_rom, 0); |
1085 | cpu68k_map_set(m68k_write8_map, 0x000000, rs - 1, PicoWrite8_hint, 1); // TODO verify |
1086 | cpu68k_map_set(m68k_write16_map, 0x000000, rs - 1, PicoWrite16_hint, 1); |
1087 | |
1088 | // DRAM area |
1089 | Pico32xSwapDRAM(1); |
be2c4208 |
1090 | |
1091 | // 32X ROM (unbanked, XXX: consider mirroring?) |
5e49c3a8 |
1092 | rs = (Pico.romsize + M68K_BANK_MASK) & ~M68K_BANK_MASK; |
1093 | if (rs > 0x80000) |
1094 | rs = 0x80000; |
1095 | cpu68k_map_set(m68k_read8_map, 0x880000, 0x880000 + rs - 1, Pico.rom, 0); |
1096 | cpu68k_map_set(m68k_read16_map, 0x880000, 0x880000 + rs - 1, Pico.rom, 0); |
be2c4208 |
1097 | |
1098 | // 32X ROM (banked) |
5e49c3a8 |
1099 | bank_switch(0); |
b78efee2 |
1100 | |
1101 | // setup poll detector |
1102 | m68k_poll.flag = P32XF_68KPOLL; |
be20816c |
1103 | m68k_poll.cyc_max = 64; |
b78efee2 |
1104 | sh2_poll[0].flag = P32XF_MSH2POLL; |
1d7a28a7 |
1105 | sh2_poll[0].cyc_max = 21; |
b78efee2 |
1106 | sh2_poll[1].flag = P32XF_SSH2POLL; |
be20816c |
1107 | sh2_poll[1].cyc_max = 16; |
be2c4208 |
1108 | } |
1109 | |