32x: watchdog for Star Wars, SCI IRQs for X-men (also needs idle loop hacks)
[picodrive.git] / pico / 32x / 32x.c
CommitLineData
be2c4208 1#include "../pico_int.h"
974fdb5b 2#include "../sound/ym2612.h"
be2c4208 3
1d7a28a7 4SH2 sh2s[2];
be2c4208 5struct Pico32x Pico32x;
6
b78efee2 7static void sh2_irq_cb(int id, int level)
4ea707e1 8{
9 // diagnostic for now
b78efee2 10 elprintf(EL_32X, "%csh2 ack %d @ %08x", id ? 's' : 'm', level, sh2_pc(id));
4ea707e1 11}
12
13void p32x_update_irls(void)
14{
15 int irqs, mlvl = 0, slvl = 0;
16
17 // msh2
18 irqs = (Pico32x.sh2irqs | Pico32x.sh2irqi[0]) & ((Pico32x.sh2irq_mask[0] << 3) | P32XI_VRES);
19 while ((irqs >>= 1))
20 mlvl++;
21 mlvl *= 2;
22
23 // ssh2
24 irqs = (Pico32x.sh2irqs | Pico32x.sh2irqi[1]) & ((Pico32x.sh2irq_mask[1] << 3) | P32XI_VRES);
25 while ((irqs >>= 1))
26 slvl++;
27 slvl *= 2;
28
29 elprintf(EL_32X, "update_irls: m %d, s %d", mlvl, slvl);
30 sh2_irl_irq(&msh2, mlvl);
4ea707e1 31 sh2_irl_irq(&ssh2, slvl);
87accdf7 32 mlvl = mlvl ? 1 : 0;
33 slvl = slvl ? 1 : 0;
34 p32x_poll_event(mlvl | (slvl << 1), 0);
4ea707e1 35}
36
be2c4208 37void Pico32xStartup(void)
38{
39 elprintf(EL_STATUS|EL_32X, "32X startup");
40
41 PicoAHW |= PAHW_32X;
42 PicoMemSetup32x();
43
b78efee2 44 sh2_init(&msh2, 0);
4ea707e1 45 msh2.irq_callback = sh2_irq_cb;
acd35d4c 46 sh2_reset(&msh2);
47
b78efee2 48 sh2_init(&ssh2, 1);
4ea707e1 49 ssh2.irq_callback = sh2_irq_cb;
acd35d4c 50 sh2_reset(&ssh2);
51
be2c4208 52 if (!Pico.m.pal)
974fdb5b 53 Pico32x.vdp_regs[0] |= P32XV_nPAL;
be2c4208 54
1d7a28a7 55 PREG8(Pico32xMem->sh2_peri_regs[0], 4) =
56 PREG8(Pico32xMem->sh2_peri_regs[1], 4) = 0x84; // SCI SSR
57
974fdb5b 58 emu_32x_startup();
be2c4208 59}
60
61void Pico32xInit(void)
62{
974fdb5b 63}
64
65void PicoPower32x(void)
66{
67 memset(&Pico32x, 0, sizeof(Pico32x));
5e49c3a8 68
974fdb5b 69 Pico32x.regs[0] = 0x0082; // SH2 reset?
70 Pico32x.vdp_regs[0x0a/2] = P32XV_VBLK|P32XV_HBLK|P32XV_PEN;
87accdf7 71 Pico32x.sh2_regs[0] = P32XS2_ADEN;
be2c4208 72}
73
5e49c3a8 74void PicoUnload32x(void)
75{
76 if (Pico32xMem != NULL)
77 free(Pico32xMem);
78 Pico32xMem = NULL;
79
80 PicoAHW &= ~PAHW_32X;
81}
82
be2c4208 83void PicoReset32x(void)
84{
5e49c3a8 85 extern int p32x_csum_faked;
86 p32x_csum_faked = 0; // tmp
be2c4208 87}
88
974fdb5b 89static void p32x_start_blank(void)
90{
91 // enter vblank
92 Pico32x.vdp_regs[0x0a/2] |= P32XV_VBLK|P32XV_PEN;
93
4ea707e1 94 // FB swap waits until vblank
974fdb5b 95 if ((Pico32x.vdp_regs[0x0a/2] ^ Pico32x.pending_fb) & P32XV_FS) {
96 Pico32x.vdp_regs[0x0a/2] &= ~P32XV_FS;
97 Pico32x.vdp_regs[0x0a/2] |= Pico32x.pending_fb;
98 Pico32xSwapDRAM(Pico32x.pending_fb ^ 1);
99 }
4ea707e1 100
97d3f47f 101 Pico32x.sh2irqs |= P32XI_VINT;
102 p32x_update_irls();
87accdf7 103 p32x_poll_event(3, 1);
974fdb5b 104}
105
236990cf 106static __inline void run_m68k(int cyc)
974fdb5b 107{
4ea707e1 108 if (Pico32x.emu_flags & P32XF_68KPOLL) {
236990cf 109 SekCycleCnt += cyc;
4ea707e1 110 return;
111 }
236990cf 112#if defined(EMU_C68K)
113 PicoCpuCM68k.cycles = cyc;
974fdb5b 114 CycloneRun(&PicoCpuCM68k);
236990cf 115 SekCycleCnt += cyc - PicoCpuCM68k.cycles;
974fdb5b 116#elif defined(EMU_M68K)
236990cf 117 SekCycleCnt += m68k_execute(cyc);
974fdb5b 118#elif defined(EMU_F68K)
236990cf 119 SekCycleCnt += fm68k_emulate(cyc+1, 0, 0);
974fdb5b 120#endif
121}
122
266c6afa 123// ~1463.8, but due to cache misses and slow mem
124// it's much lower than that
be20816c 125//#define SH2_LINE_CYCLES 735
c987bb5c 126#define CYCLES_M68K2SH2(x) ((x) * 6 / 4)
266c6afa 127
974fdb5b 128#define PICO_32X
c987bb5c 129#define CPUS_RUN_SIMPLE(m68k_cycles,s68k_cycles) \
236990cf 130{ \
131 int slice; \
132 SekCycleAim += m68k_cycles; \
133 while (SekCycleCnt < SekCycleAim) { \
134 slice = SekCycleCnt; \
135 run_m68k(SekCycleAim - SekCycleCnt); \
136 slice = SekCycleCnt - slice; /* real count from 68k */ \
137 if (SekCycleCnt < SekCycleAim) \
138 elprintf(EL_32X, "slice %d", slice); \
139 if (!(Pico32x.emu_flags & (P32XF_SSH2POLL|P32XF_SSH2VPOLL))) \
140 sh2_execute(&ssh2, CYCLES_M68K2SH2(slice)); \
141 if (!(Pico32x.emu_flags & (P32XF_MSH2POLL|P32XF_MSH2VPOLL))) \
142 sh2_execute(&msh2, CYCLES_M68K2SH2(slice)); \
143 } \
144}
acd35d4c 145
c987bb5c 146#define STEP_68K 24
147#define CPUS_RUN_LOCKSTEP(m68k_cycles,s68k_cycles) \
87accdf7 148{ \
149 int i; \
c987bb5c 150 for (i = 0; i <= (m68k_cycles) - STEP_68K; i += STEP_68K) { \
236990cf 151 run_m68k(STEP_68K); \
c987bb5c 152 if (!(Pico32x.emu_flags & (P32XF_MSH2POLL|P32XF_MSH2VPOLL))) \
153 sh2_execute(&msh2, CYCLES_M68K2SH2(STEP_68K)); \
154 if (!(Pico32x.emu_flags & (P32XF_SSH2POLL|P32XF_SSH2VPOLL))) \
155 sh2_execute(&ssh2, CYCLES_M68K2SH2(STEP_68K)); \
87accdf7 156 } \
c987bb5c 157 /* last step */ \
158 i = (m68k_cycles) - i; \
236990cf 159 run_m68k(i); \
c987bb5c 160 if (!(Pico32x.emu_flags & (P32XF_MSH2POLL|P32XF_MSH2VPOLL))) \
161 sh2_execute(&msh2, CYCLES_M68K2SH2(i)); \
162 if (!(Pico32x.emu_flags & (P32XF_SSH2POLL|P32XF_SSH2VPOLL))) \
163 sh2_execute(&ssh2, CYCLES_M68K2SH2(i)); \
87accdf7 164}
165
236990cf 166#define CPUS_RUN CPUS_RUN_SIMPLE
167//#define CPUS_RUN CPUS_RUN_LOCKSTEP
87accdf7 168
974fdb5b 169#include "../pico_cmn.c"
170
171void PicoFrame32x(void)
172{
db1d3564 173 pwm_frame_smp_cnt = 0;
174
4ea707e1 175 Pico32x.vdp_regs[0x0a/2] &= ~P32XV_VBLK; // get out of vblank
db1d3564 176 if ((Pico32x.vdp_regs[0] & P32XV_Mx) != 0) // no forced blanking
177 Pico32x.vdp_regs[0x0a/2] &= ~P32XV_PEN; // no palette access
4ea707e1 178
87accdf7 179 p32x_poll_event(3, 1);
974fdb5b 180
181 PicoFrameStart();
182 PicoFrameHints();
be20816c 183 elprintf(EL_32X, "poll: %02x", Pico32x.emu_flags);
974fdb5b 184}
db1d3564 185