| eff55556 |
1 | // Pico Library - Internal Header File\r |
| cc68a136 |
2 | \r |
| 3 | // (c) Copyright 2004 Dave, All rights reserved.\r |
| db1d3564 |
4 | // (c) Copyright 2006-2009 Grazvydas "notaz" Ignotas, all rights reserved.\r |
| cc68a136 |
5 | // Free for non-commercial use.\r |
| 6 | \r |
| 7 | // For commercial use, separate licencing terms must be obtained.\r |
| 8 | \r |
| eff55556 |
9 | #ifndef PICO_INTERNAL_INCLUDED\r |
| 10 | #define PICO_INTERNAL_INCLUDED\r |
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11 | \r |
| 12 | #include <stdio.h>\r |
| 13 | #include <stdlib.h>\r |
| 14 | #include <string.h>\r |
| efcba75f |
15 | #include "pico.h"\r |
| f53f286a |
16 | #include "carthw/carthw.h"\r |
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17 | \r |
| 89fa852d |
18 | //\r |
| 19 | #define USE_POLL_DETECT\r |
| 20 | \r |
| eff55556 |
21 | #ifndef PICO_INTERNAL\r |
| 22 | #define PICO_INTERNAL\r |
| 23 | #endif\r |
| 24 | #ifndef PICO_INTERNAL_ASM\r |
| 25 | #define PICO_INTERNAL_ASM\r |
| 26 | #endif\r |
| cc68a136 |
27 | \r |
| 70357ce5 |
28 | // to select core, define EMU_C68K, EMU_M68K or EMU_F68K in your makefile or project\r |
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29 | \r |
| 30 | #ifdef __cplusplus\r |
| 31 | extern "C" {\r |
| 32 | #endif\r |
| 33 | \r |
| 34 | \r |
| 35 | // ----------------------- 68000 CPU -----------------------\r |
| 36 | #ifdef EMU_C68K\r |
| 37 | #include "../cpu/Cyclone/Cyclone.h"\r |
| 3aa1e148 |
38 | extern struct Cyclone PicoCpuCM68k, PicoCpuCS68k;\r |
| 39 | #define SekCyclesLeftNoMCD PicoCpuCM68k.cycles // cycles left for this run\r |
| 7336a99a |
40 | #define SekCyclesLeft \\r |
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41 | (((PicoAHW&1) && (PicoOpt & POPT_EN_MCD_PSYNC)) ? (SekCycleAim-SekCycleCnt) : SekCyclesLeftNoMCD)\r |
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42 | #define SekCyclesLeftS68k \\r |
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43 | ((PicoOpt & POPT_EN_MCD_PSYNC) ? (SekCycleAimS68k-SekCycleCntS68k) : PicoCpuCS68k.cycles)\r |
| ef090115 |
44 | #define SekEndTimeslice(after) PicoCpuCM68k.cycles=after\r |
| 07ceafdb |
45 | #define SekEndTimesliceS68k(after) PicoCpuCS68k.cycles=after\r |
| 3aa1e148 |
46 | #define SekPc (PicoCpuCM68k.pc-PicoCpuCM68k.membase)\r |
| 47 | #define SekPcS68k (PicoCpuCS68k.pc-PicoCpuCS68k.membase)\r |
| 48 | #define SekSetStop(x) { PicoCpuCM68k.state_flags&=~1; if (x) { PicoCpuCM68k.state_flags|=1; PicoCpuCM68k.cycles=0; } }\r |
| 49 | #define SekSetStopS68k(x) { PicoCpuCS68k.state_flags&=~1; if (x) { PicoCpuCS68k.state_flags|=1; PicoCpuCS68k.cycles=0; } }\r |
| ca61ee42 |
50 | #define SekIsStoppedS68k() (PicoCpuCS68k.state_flags&1)\r |
| 03e4f2a3 |
51 | #define SekShouldInterrupt (PicoCpuCM68k.irq > (PicoCpuCM68k.srh&7))\r |
| b542be46 |
52 | \r |
| 53 | #define SekInterrupt(i) PicoCpuCM68k.irq=i\r |
| 54 | \r |
| 03e4f2a3 |
55 | #ifdef EMU_M68K\r |
| 56 | #define EMU_CORE_DEBUG\r |
| 57 | #endif\r |
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58 | #endif\r |
| 59 | \r |
| 70357ce5 |
60 | #ifdef EMU_F68K\r |
| 61 | #include "../cpu/fame/fame.h"\r |
| b542be46 |
62 | extern M68K_CONTEXT PicoCpuFM68k, PicoCpuFS68k;\r |
| 3aa1e148 |
63 | #define SekCyclesLeftNoMCD PicoCpuFM68k.io_cycle_counter\r |
| 70357ce5 |
64 | #define SekCyclesLeft \\r |
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65 | (((PicoAHW&1) && (PicoOpt & POPT_EN_MCD_PSYNC)) ? (SekCycleAim-SekCycleCnt) : SekCyclesLeftNoMCD)\r |
| 70357ce5 |
66 | #define SekCyclesLeftS68k \\r |
| 602133e1 |
67 | ((PicoOpt & POPT_EN_MCD_PSYNC) ? (SekCycleAimS68k-SekCycleCntS68k) : PicoCpuFS68k.io_cycle_counter)\r |
| ef090115 |
68 | #define SekEndTimeslice(after) PicoCpuFM68k.io_cycle_counter=after\r |
| 07ceafdb |
69 | #define SekEndTimesliceS68k(after) PicoCpuFS68k.io_cycle_counter=after\r |
| 03e4f2a3 |
70 | #define SekPc fm68k_get_pc(&PicoCpuFM68k)\r |
| 71 | #define SekPcS68k fm68k_get_pc(&PicoCpuFS68k)\r |
| 70357ce5 |
72 | #define SekSetStop(x) { \\r |
| 03e4f2a3 |
73 | PicoCpuFM68k.execinfo &= ~FM68K_HALTED; \\r |
| 74 | if (x) { PicoCpuFM68k.execinfo |= FM68K_HALTED; PicoCpuFM68k.io_cycle_counter = 0; } \\r |
| 70357ce5 |
75 | }\r |
| 76 | #define SekSetStopS68k(x) { \\r |
| 03e4f2a3 |
77 | PicoCpuFS68k.execinfo &= ~FM68K_HALTED; \\r |
| 78 | if (x) { PicoCpuFS68k.execinfo |= FM68K_HALTED; PicoCpuFS68k.io_cycle_counter = 0; } \\r |
| 70357ce5 |
79 | }\r |
| ca61ee42 |
80 | #define SekIsStoppedS68k() (PicoCpuFS68k.execinfo&FM68K_HALTED)\r |
| 03e4f2a3 |
81 | #define SekShouldInterrupt fm68k_would_interrupt()\r |
| b542be46 |
82 | \r |
| 83 | #define SekInterrupt(irq) PicoCpuFM68k.interrupts[0]=irq\r |
| 84 | \r |
| 03e4f2a3 |
85 | #ifdef EMU_M68K\r |
| 86 | #define EMU_CORE_DEBUG\r |
| 87 | #endif\r |
| cc68a136 |
88 | #endif\r |
| 89 | \r |
| 90 | #ifdef EMU_M68K\r |
| 91 | #include "../cpu/musashi/m68kcpu.h"\r |
| 3aa1e148 |
92 | extern m68ki_cpu_core PicoCpuMM68k, PicoCpuMS68k;\r |
| cc68a136 |
93 | #ifndef SekCyclesLeft\r |
| 3aa1e148 |
94 | #define SekCyclesLeftNoMCD PicoCpuMM68k.cyc_remaining_cycles\r |
| 7336a99a |
95 | #define SekCyclesLeft \\r |
| 602133e1 |
96 | (((PicoAHW&1) && (PicoOpt & POPT_EN_MCD_PSYNC)) ? (SekCycleAim-SekCycleCnt) : SekCyclesLeftNoMCD)\r |
| 7a1f6e45 |
97 | #define SekCyclesLeftS68k \\r |
| 602133e1 |
98 | ((PicoOpt & POPT_EN_MCD_PSYNC) ? (SekCycleAimS68k-SekCycleCntS68k) : PicoCpuMS68k.cyc_remaining_cycles)\r |
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99 | #define SekEndTimeslice(after) SET_CYCLES(after)\r |
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100 | #define SekEndTimesliceS68k(after) PicoCpuMS68k.cyc_remaining_cycles=after\r |
| 3aa1e148 |
101 | #define SekPc m68k_get_reg(&PicoCpuMM68k, M68K_REG_PC)\r |
| 102 | #define SekPcS68k m68k_get_reg(&PicoCpuMS68k, M68K_REG_PC)\r |
| 7a1f6e45 |
103 | #define SekSetStop(x) { \\r |
| 3aa1e148 |
104 | if(x) { SET_CYCLES(0); PicoCpuMM68k.stopped=STOP_LEVEL_STOP; } \\r |
| 105 | else PicoCpuMM68k.stopped=0; \\r |
| 7a1f6e45 |
106 | }\r |
| 107 | #define SekSetStopS68k(x) { \\r |
| 3aa1e148 |
108 | if(x) { SET_CYCLES(0); PicoCpuMS68k.stopped=STOP_LEVEL_STOP; } \\r |
| 109 | else PicoCpuMS68k.stopped=0; \\r |
| 7a1f6e45 |
110 | }\r |
| ca61ee42 |
111 | #define SekIsStoppedS68k() (PicoCpuMS68k.stopped==STOP_LEVEL_STOP)\r |
| 03e4f2a3 |
112 | #define SekShouldInterrupt (CPU_INT_LEVEL > FLAG_INT_MASK)\r |
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113 | \r |
| 71de3cd9 |
114 | #define SekInterrupt(irq) { \\r |
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115 | void *oldcontext = m68ki_cpu_p; \\r |
| 116 | m68k_set_context(&PicoCpuMM68k); \\r |
| 117 | m68k_set_irq(irq); \\r |
| 118 | m68k_set_context(oldcontext); \\r |
| 119 | }\r |
| 120 | \r |
| cc68a136 |
121 | #endif\r |
| ef090115 |
122 | #endif // EMU_M68K\r |
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123 | \r |
| 124 | extern int SekCycleCnt; // cycles done in this frame\r |
| 125 | extern int SekCycleAim; // cycle aim\r |
| 126 | extern unsigned int SekCycleCntT; // total cycle counter, updated once per frame\r |
| 127 | \r |
| b8cbd802 |
128 | #define SekCyclesReset() { \\r |
| 129 | SekCycleCntT+=SekCycleAim; \\r |
| 130 | SekCycleCnt-=SekCycleAim; \\r |
| 131 | SekCycleAim=0; \\r |
| 132 | }\r |
| cc68a136 |
133 | #define SekCyclesBurn(c) SekCycleCnt+=c\r |
| 4b9c5888 |
134 | #define SekCyclesDone() (SekCycleAim-SekCyclesLeft) // number of cycles done in this frame (can be checked anywhere)\r |
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135 | #define SekCyclesDoneT() (SekCycleCntT+SekCyclesDone()) // total nuber of cycles done for this rom\r |
| 136 | \r |
| 137 | #define SekEndRun(after) { \\r |
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138 | SekCycleCnt -= SekCyclesLeft - (after); \\r |
| 139 | if (SekCycleCnt < 0) SekCycleCnt = 0; \\r |
| 140 | SekEndTimeslice(after); \\r |
| cc68a136 |
141 | }\r |
| 142 | \r |
| 07ceafdb |
143 | #define SekEndRunS68k(after) { \\r |
| 144 | SekCycleCntS68k -= SekCyclesLeftS68k - (after); \\r |
| 145 | if (SekCycleCntS68k < 0) SekCycleCntS68k = 0; \\r |
| 146 | SekEndTimesliceS68k(after); \\r |
| 147 | }\r |
| 148 | \r |
| cc68a136 |
149 | extern int SekCycleCntS68k;\r |
| 150 | extern int SekCycleAimS68k;\r |
| 151 | \r |
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152 | #define SekCyclesResetS68k() { \\r |
| 153 | SekCycleCntS68k-=SekCycleAimS68k; \\r |
| 154 | SekCycleAimS68k=0; \\r |
| 155 | }\r |
| 7a1f6e45 |
156 | #define SekCyclesDoneS68k() (SekCycleAimS68k-SekCyclesLeftS68k)\r |
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157 | \r |
| 03e4f2a3 |
158 | #ifdef EMU_CORE_DEBUG\r |
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159 | extern int dbg_irq_level;\r |
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160 | #undef SekEndTimeslice\r |
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161 | #undef SekCyclesBurn\r |
| 162 | #undef SekEndRun\r |
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163 | #undef SekInterrupt\r |
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164 | #define SekEndTimeslice(c)\r |
| 2270612a |
165 | #define SekCyclesBurn(c) c\r |
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166 | #define SekEndRun(c)\r |
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167 | #define SekInterrupt(irq) dbg_irq_level=irq\r |
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168 | #endif\r |
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169 | \r |
| b542be46 |
170 | // ----------------------- Z80 CPU -----------------------\r |
| 171 | \r |
| 172 | #if defined(_USE_MZ80)\r |
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173 | #include "../cpu/mz80/mz80.h"\r |
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174 | \r |
| 4b9c5888 |
175 | #define z80_run(cycles) { mz80GetElapsedTicks(1); mz80_run(cycles) }\r |
| b542be46 |
176 | #define z80_run_nr(cycles) mz80_run(cycles)\r |
| 177 | #define z80_int() mz80int(0)\r |
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178 | \r |
| 179 | #elif defined(_USE_DRZ80)\r |
| dca310c4 |
180 | #include "../cpu/DrZ80/drz80.h"\r |
| b542be46 |
181 | \r |
| 182 | extern struct DrZ80 drZ80;\r |
| 183 | \r |
| 184 | #define z80_run(cycles) ((cycles) - DrZ80Run(&drZ80, cycles))\r |
| 185 | #define z80_run_nr(cycles) DrZ80Run(&drZ80, cycles)\r |
| 4936aac1 |
186 | #define z80_int() drZ80.Z80_IRQ = 1\r |
| 4b9c5888 |
187 | \r |
| 188 | #define z80_cyclesLeft drZ80.cycles\r |
| 19954be1 |
189 | #define z80_pc() (drZ80.Z80PC - drZ80.Z80PC_BASE)\r |
| b542be46 |
190 | \r |
| 191 | #elif defined(_USE_CZ80)\r |
| dca310c4 |
192 | #include "../cpu/cz80/cz80.h"\r |
| b542be46 |
193 | \r |
| 194 | #define z80_run(cycles) Cz80_Exec(&CZ80, cycles)\r |
| 195 | #define z80_run_nr(cycles) Cz80_Exec(&CZ80, cycles)\r |
| 196 | #define z80_int() Cz80_Set_IRQ(&CZ80, 0, HOLD_LINE)\r |
| 4b9c5888 |
197 | \r |
| 198 | #define z80_cyclesLeft (CZ80.ICount - CZ80.ExtraCycles)\r |
| 19954be1 |
199 | #define z80_pc() Cz80_Get_Reg(&CZ80, CZ80_PC)\r |
| b542be46 |
200 | \r |
| 201 | #else\r |
| 202 | \r |
| 203 | #define z80_run(cycles) (cycles)\r |
| 204 | #define z80_run_nr(cycles)\r |
| 205 | #define z80_int()\r |
| b542be46 |
206 | \r |
| 207 | #endif\r |
| 208 | \r |
| 4b9c5888 |
209 | extern int z80stopCycle; /* in 68k cycles */\r |
| 210 | extern int z80_cycle_cnt; /* 'done' z80 cycles before z80_run() */\r |
| 211 | extern int z80_cycle_aim;\r |
| 212 | extern int z80_scanline;\r |
| 213 | extern int z80_scanline_cycles; /* cycles done until z80_scanline */\r |
| 214 | \r |
| 215 | #define z80_resetCycles() \\r |
| 216 | z80_cycle_cnt = z80_cycle_aim = z80_scanline = z80_scanline_cycles = 0;\r |
| 217 | \r |
| 218 | #define z80_cyclesDone() \\r |
| 219 | (z80_cycle_aim - z80_cyclesLeft)\r |
| 220 | \r |
| 221 | #define cycles_68k_to_z80(x) ((x)*957 >> 11)\r |
| 222 | \r |
| c8d1e9b6 |
223 | #define Z80_MEM_SHIFT 13\r |
| 224 | extern unsigned long z80_read_map [0x10000 >> Z80_MEM_SHIFT];\r |
| 225 | extern unsigned long z80_write_map[0x10000 >> Z80_MEM_SHIFT];\r |
| 226 | typedef unsigned char (z80_read_f)(unsigned short a);\r |
| 227 | typedef void (z80_write_f)(unsigned int a, unsigned char data);\r |
| 228 | \r |
| acd35d4c |
229 | // ----------------------- SH2 CPU -----------------------\r |
| 230 | \r |
| 231 | #include "cpu/sh2mame/sh2.h"\r |
| 232 | \r |
| 1d7a28a7 |
233 | extern SH2 sh2s[2];\r |
| 234 | #define msh2 sh2s[0]\r |
| 235 | #define ssh2 sh2s[1]\r |
| 236 | \r |
| 236990cf |
237 | #define ash2_end_run(after) if (sh2_icount > (after)) sh2_icount = after\r |
| c987bb5c |
238 | #define ash2_cycles_done() (sh2->cycles_aim - sh2_icount)\r |
| 266c6afa |
239 | \r |
| 4ea707e1 |
240 | #define sh2_pc(c) (c) ? ssh2.ppc : msh2.ppc\r |
| 241 | #define sh2_reg(c, x) (c) ? ssh2.r[x] : msh2.r[x]\r |
| 242 | #define sh2_gbr(c) (c) ? ssh2.gbr : msh2.gbr\r |
| 243 | #define sh2_vbr(c) (c) ? ssh2.vbr : msh2.vbr\r |
| 244 | #define sh2_sr(c) (c) ? ssh2.sr : msh2.sr\r |
| acd35d4c |
245 | \r |
| cc68a136 |
246 | // ---------------------------------------------------------\r |
| 247 | \r |
| 248 | // main oscillator clock which controls timing\r |
| 249 | #define OSC_NTSC 53693100\r |
| b8cbd802 |
250 | #define OSC_PAL 53203424\r |
| cc68a136 |
251 | \r |
| 252 | struct PicoVideo\r |
| 253 | {\r |
| 254 | unsigned char reg[0x20];\r |
| b8cbd802 |
255 | unsigned int command; // 32-bit Command\r |
| 256 | unsigned char pending; // 1 if waiting for second half of 32-bit command\r |
| 257 | unsigned char type; // Command type (v/c/vsram read/write)\r |
| 258 | unsigned short addr; // Read/Write address\r |
| 259 | int status; // Status bits\r |
| cc68a136 |
260 | unsigned char pending_ints; // pending interrupts: ??VH????\r |
| b8cbd802 |
261 | signed char lwrite_cnt; // VDP write count during active display line\r |
| 9761a7d0 |
262 | unsigned short v_counter; // V-counter\r |
| 263 | unsigned char pad[0x10];\r |
| cc68a136 |
264 | };\r |
| 265 | \r |
| 266 | struct PicoMisc\r |
| 267 | {\r |
| 268 | unsigned char rotate;\r |
| 269 | unsigned char z80Run;\r |
| e5503e2f |
270 | unsigned char padTHPhase[2]; // 02 phase of gamepad TH switches\r |
| 2aa27095 |
271 | unsigned short scanline; // 04 0 to 261||311\r |
| e5503e2f |
272 | char dirtyPal; // 06 Is the palette dirty (1 - change @ this frame, 2 - some time before)\r |
| 273 | unsigned char hardware; // 07 Hardware value for country\r |
| 274 | unsigned char pal; // 08 1=PAL 0=NTSC\r |
| 45f2f245 |
275 | unsigned char sram_reg; // 09 SRAM reg. See SRR_* below\r |
| e5503e2f |
276 | unsigned short z80_bank68k; // 0a\r |
| be2c4208 |
277 | unsigned short pad0;\r |
| 278 | unsigned char pad1;\r |
| 0ace9b9a |
279 | unsigned char z80_reset; // 0f z80 reset held\r |
| e5503e2f |
280 | unsigned char padDelay[2]; // 10 gamepad phase time outs, so we count a delay\r |
| 1dceadae |
281 | unsigned short eeprom_addr; // EEPROM address register\r |
| 45f2f245 |
282 | unsigned char eeprom_cycle; // EEPROM cycle number\r |
| 1dceadae |
283 | unsigned char eeprom_slave; // EEPROM slave word for X24C02 and better SRAMs\r |
| 45f2f245 |
284 | unsigned char eeprom_status;\r |
| be2c4208 |
285 | unsigned char pad2;\r |
| 053fd9b4 |
286 | unsigned short dma_xfers; // 18\r |
| 45f2f245 |
287 | unsigned char eeprom_wb[2]; // EEPROM latch/write buffer\r |
| 053fd9b4 |
288 | unsigned int frame_count; // 1c for movies and idle det\r |
| cc68a136 |
289 | };\r |
| 290 | \r |
| 291 | // some assembly stuff depend on these, do not touch!\r |
| 292 | struct Pico\r |
| 293 | {\r |
| 294 | unsigned char ram[0x10000]; // 0x00000 scratch ram\r |
| 200772b7 |
295 | union { // vram is byteswapped for easier reads when drawing\r |
| 2ec9bec5 |
296 | unsigned short vram[0x8000]; // 0x10000\r |
| 297 | unsigned char vramb[0x4000]; // VRAM in SMS mode\r |
| 298 | };\r |
| cc68a136 |
299 | unsigned char zram[0x2000]; // 0x20000 Z80 ram\r |
| 300 | unsigned char ioports[0x10];\r |
| 2ec9bec5 |
301 | unsigned char sms_io_ctl;\r |
| 302 | unsigned char pad[0xef]; // unused\r |
| cc68a136 |
303 | unsigned short cram[0x40]; // 0x22100\r |
| 304 | unsigned short vsram[0x40]; // 0x22180\r |
| 305 | \r |
| 306 | unsigned char *rom; // 0x22200\r |
| 307 | unsigned int romsize; // 0x22204\r |
| 308 | \r |
| 309 | struct PicoMisc m;\r |
| 310 | struct PicoVideo video;\r |
| 311 | };\r |
| 312 | \r |
| 313 | // sram\r |
| 45f2f245 |
314 | #define SRR_MAPPED (1 << 0)\r |
| 315 | #define SRR_READONLY (1 << 1)\r |
| 316 | \r |
| 317 | #define SRF_ENABLED (1 << 0)\r |
| 318 | #define SRF_EEPROM (1 << 1)\r |
| af37bca8 |
319 | \r |
| cc68a136 |
320 | struct PicoSRAM\r |
| 321 | {\r |
| 4ff2d527 |
322 | unsigned char *data; // actual data\r |
| 323 | unsigned int start; // start address in 68k address space\r |
| cc68a136 |
324 | unsigned int end;\r |
| 45f2f245 |
325 | unsigned char flags; // 0c: SRF_*\r |
| 1dceadae |
326 | unsigned char unused2;\r |
| cc68a136 |
327 | unsigned char changed;\r |
| 45f2f245 |
328 | unsigned char eeprom_type; // eeprom type: 0: 7bit (24C01), 2: 2 addr words (X24C02+), 3: 3 addr words\r |
| 329 | unsigned char unused3;\r |
| 1dceadae |
330 | unsigned char eeprom_bit_cl; // bit number for cl\r |
| 331 | unsigned char eeprom_bit_in; // bit number for in\r |
| 332 | unsigned char eeprom_bit_out; // bit number for out\r |
| 45f2f245 |
333 | unsigned int size;\r |
| cc68a136 |
334 | };\r |
| 335 | \r |
| 336 | // MCD\r |
| 337 | #include "cd/cd_sys.h"\r |
| 338 | #include "cd/LC89510.h"\r |
| d1df8786 |
339 | #include "cd/gfx_cd.h"\r |
| cc68a136 |
340 | \r |
| 4f265db7 |
341 | struct mcd_pcm\r |
| 342 | {\r |
| 343 | unsigned char control; // reg7\r |
| 344 | unsigned char enabled; // reg8\r |
| 345 | unsigned char cur_ch;\r |
| 346 | unsigned char bank;\r |
| 347 | int pad1;\r |
| 348 | \r |
| 4ff2d527 |
349 | struct pcm_chan // 08, size 0x10\r |
| 4f265db7 |
350 | {\r |
| 351 | unsigned char regs[8];\r |
| 4ff2d527 |
352 | unsigned int addr; // .08: played sample address\r |
| 4f265db7 |
353 | int pad;\r |
| 354 | } ch[8];\r |
| 355 | };\r |
| 356 | \r |
| c459aefd |
357 | struct mcd_misc\r |
| 358 | {\r |
| 359 | unsigned short hint_vector;\r |
| 360 | unsigned char busreq;\r |
| 51a902ae |
361 | unsigned char s68k_pend_ints;\r |
| ef090115 |
362 | unsigned int state_flags; // 04: emu state: reset_pending\r |
| 51a902ae |
363 | unsigned int counter75hz;\r |
| c9e1affc |
364 | unsigned int pad0;\r |
| 4ff2d527 |
365 | int timer_int3; // 10\r |
| 4f265db7 |
366 | unsigned int timer_stopwatch;\r |
| 6cadc2da |
367 | unsigned char bcram_reg; // 18: battery-backed RAM cart register\r |
| 368 | unsigned char pad2;\r |
| 369 | unsigned short pad3;\r |
| 370 | int pad[9];\r |
| c459aefd |
371 | };\r |
| 372 | \r |
| cc68a136 |
373 | typedef struct\r |
| 374 | {\r |
| 4ff2d527 |
375 | unsigned char bios[0x20000]; // 000000: 128K\r |
| 376 | union { // 020000: 512K\r |
| fa1e5e29 |
377 | unsigned char prg_ram[0x80000];\r |
| cc68a136 |
378 | unsigned char prg_ram_b[4][0x20000];\r |
| 379 | };\r |
| 4ff2d527 |
380 | union { // 0a0000: 256K\r |
| fa1e5e29 |
381 | struct {\r |
| 382 | unsigned char word_ram2M[0x40000];\r |
| dca310c4 |
383 | unsigned char unused0[0x20000];\r |
| fa1e5e29 |
384 | };\r |
| 385 | struct {\r |
| dca310c4 |
386 | unsigned char unused1[0x20000];\r |
| fa1e5e29 |
387 | unsigned char word_ram1M[2][0x20000];\r |
| 388 | };\r |
| 389 | };\r |
| 4ff2d527 |
390 | union { // 100000: 64K\r |
| fa1e5e29 |
391 | unsigned char pcm_ram[0x10000];\r |
| 4f265db7 |
392 | unsigned char pcm_ram_b[0x10][0x1000];\r |
| 393 | };\r |
| 4ff2d527 |
394 | unsigned char s68k_regs[0x200]; // 110000: GA, not CPU regs\r |
| 395 | unsigned char bram[0x2000]; // 110200: 8K\r |
| 396 | struct mcd_misc m; // 112200: misc\r |
| 397 | struct mcd_pcm pcm; // 112240:\r |
| 75736070 |
398 | _scd_toc TOC; // not to be saved\r |
| cc68a136 |
399 | CDD cdd;\r |
| 400 | CDC cdc;\r |
| 401 | _scd scd;\r |
| d1df8786 |
402 | Rot_Comp rot_comp;\r |
| cc68a136 |
403 | } mcd_state;\r |
| 404 | \r |
| be2c4208 |
405 | // XXX: this will need to be reworked for cart+cd support.\r |
| cc68a136 |
406 | #define Pico_mcd ((mcd_state *)Pico.rom)\r |
| 407 | \r |
| be2c4208 |
408 | // 32X\r |
| acd35d4c |
409 | #define P32XS_FM (1<<15)\r |
| 410 | #define P32XS2_ADEN (1<< 9)\r |
| 5e128c6d |
411 | #define P32XS_FULL (1<< 7) // DREQ FIFO full\r |
| 4ea707e1 |
412 | #define P32XS_68S (1<< 2)\r |
| 97d3f47f |
413 | #define P32XS_DMA (1<< 1)\r |
| 4ea707e1 |
414 | #define P32XS_RV (1<< 0)\r |
| acd35d4c |
415 | \r |
| 5e128c6d |
416 | #define P32XV_nPAL (1<<15) // VDP\r |
| acd35d4c |
417 | #define P32XV_PRI (1<< 7)\r |
| 4ea707e1 |
418 | #define P32XV_Mx (3<< 0) // display mode mask\r |
| 974fdb5b |
419 | \r |
| acd35d4c |
420 | #define P32XV_VBLK (1<<15)\r |
| 421 | #define P32XV_HBLK (1<<14)\r |
| 422 | #define P32XV_PEN (1<<13)\r |
| 423 | #define P32XV_nFEN (1<< 1)\r |
| 424 | #define P32XV_FS (1<< 0)\r |
| 974fdb5b |
425 | \r |
| db1d3564 |
426 | #define P32XP_FULL (1<<15) // PWM\r |
| 427 | #define P32XP_EMPTY (1<<14)\r |
| 428 | \r |
| 4ea707e1 |
429 | #define P32XF_68KPOLL (1 << 0)\r |
| 430 | #define P32XF_MSH2POLL (1 << 1)\r |
| 431 | #define P32XF_SSH2POLL (1 << 2)\r |
| 432 | #define P32XF_68KVPOLL (1 << 3)\r |
| 433 | #define P32XF_MSH2VPOLL (1 << 4)\r |
| 434 | #define P32XF_SSH2VPOLL (1 << 5)\r |
| 435 | \r |
| 436 | #define P32XI_VRES (1 << 14/2) // IRL/2\r |
| 437 | #define P32XI_VINT (1 << 12/2)\r |
| 438 | #define P32XI_HINT (1 << 10/2)\r |
| 439 | #define P32XI_CMD (1 << 8/2)\r |
| 440 | #define P32XI_PWM (1 << 6/2)\r |
| 441 | \r |
| 1d7a28a7 |
442 | // peripheral reg access\r |
| 443 | #define PREG8(regs,offs) ((unsigned char *)regs)[offs ^ 3]\r |
| 444 | \r |
| 4ea707e1 |
445 | // real one is 4*2, but we use more because we don't lockstep\r |
| 446 | #define DMAC_FIFO_LEN (4*4)\r |
| db1d3564 |
447 | #define PWM_BUFF_LEN 1024 // in one channel samples\r |
| 266c6afa |
448 | \r |
| be2c4208 |
449 | struct Pico32x\r |
| 450 | {\r |
| 451 | unsigned short regs[0x20];\r |
| 452 | unsigned short vdp_regs[0x10];\r |
| 87accdf7 |
453 | unsigned short sh2_regs[3];\r |
| be2c4208 |
454 | unsigned char pending_fb;\r |
| 974fdb5b |
455 | unsigned char dirty_pal;\r |
| 266c6afa |
456 | unsigned int emu_flags;\r |
| 4ea707e1 |
457 | unsigned char sh2irq_mask[2];\r |
| 458 | unsigned char sh2irqi[2]; // individual\r |
| 459 | unsigned int sh2irqs; // common irqs\r |
| 460 | unsigned short dmac_fifo[DMAC_FIFO_LEN];\r |
| 461 | unsigned int dmac_ptr;\r |
| db1d3564 |
462 | unsigned int pwm_irq_sample_cnt;\r |
| 974fdb5b |
463 | };\r |
| 464 | \r |
| 465 | struct Pico32xMem\r |
| 466 | {\r |
| 467 | unsigned char sdram[0x40000];\r |
| b78efee2 |
468 | unsigned short dram[2][0x20000/2]; // AKA fb\r |
| 469 | unsigned char m68k_rom[0x10000]; // 0x100; using M68K_BANK_SIZE\r |
| 470 | unsigned char data_array[2][0x1000]; // cache in SH2s (can be used as RAM)\r |
| acd35d4c |
471 | unsigned char sh2_rom_m[0x800];\r |
| 472 | unsigned char sh2_rom_s[0x400];\r |
| 974fdb5b |
473 | unsigned short pal[0x100];\r |
| 5e128c6d |
474 | unsigned short pal_native[0x100]; // converted to native (for renderer)\r |
| 4ea707e1 |
475 | unsigned int sh2_peri_regs[2][0x200/4]; // periphereal regs of SH2s\r |
| db1d3564 |
476 | signed short pwm[2*PWM_BUFF_LEN]; // PWM buffer for current frame\r |
| be2c4208 |
477 | };\r |
| d49b10c2 |
478 | \r |
| c8d1e9b6 |
479 | // area.c\r |
| 2aa27095 |
480 | PICO_INTERNAL void PicoAreaPackCpu(unsigned char *cpu, int is_sub);\r |
| 481 | PICO_INTERNAL void PicoAreaUnpackCpu(unsigned char *cpu, int is_sub);\r |
| fad24893 |
482 | extern void (*PicoLoadStateHook)(void);\r |
| 51a902ae |
483 | \r |
| c8d1e9b6 |
484 | // cd/area.c\r |
| eff55556 |
485 | PICO_INTERNAL int PicoCdSaveState(void *file);\r |
| 486 | PICO_INTERNAL int PicoCdLoadState(void *file);\r |
| cc68a136 |
487 | \r |
| 945c2fdc |
488 | typedef struct {\r |
| 489 | int chunk;\r |
| 490 | int size;\r |
| 491 | void *ptr;\r |
| 492 | } carthw_state_chunk;\r |
| 493 | extern carthw_state_chunk *carthw_chunks;\r |
| 494 | #define CHUNK_CARTHW 64\r |
| 495 | \r |
| bcc9eda0 |
496 | // area.c\r |
| 497 | typedef size_t (arearw)(void *p, size_t _size, size_t _n, void *file);\r |
| 498 | typedef size_t (areaeof)(void *file);\r |
| 499 | typedef int (areaseek)(void *file, long offset, int whence);\r |
| 500 | typedef int (areaclose)(void *file);\r |
| 501 | extern arearw *areaRead; // external read and write function pointers for\r |
| 502 | extern arearw *areaWrite; // gzip save state ability\r |
| 503 | extern areaeof *areaEof;\r |
| 504 | extern areaseek *areaSeek;\r |
| 505 | extern areaclose *areaClose;\r |
| 506 | \r |
| c8d1e9b6 |
507 | // cart.c\r |
| 45f2f245 |
508 | extern void (*PicoCartMemSetup)(void);\r |
| e807ac75 |
509 | extern void (*PicoCartUnloadHook)(void);\r |
| 1dceadae |
510 | \r |
| c8d1e9b6 |
511 | // debug.c\r |
| b5e5172d |
512 | int CM_compareRun(int cyc, int is_sub);\r |
| 03e4f2a3 |
513 | \r |
| c8d1e9b6 |
514 | // draw.c\r |
| eff55556 |
515 | PICO_INTERNAL void PicoFrameStart(void);\r |
| b6d7ac70 |
516 | void PicoDrawSync(int to, int blank_last_line);\r |
| 200772b7 |
517 | void BackFill(int reg7, int sh);\r |
| 974fdb5b |
518 | void FinalizeLineRGB555(int sh, int line);\r |
| b6d7ac70 |
519 | extern int DrawScanline;\r |
| f579f7b8 |
520 | #define MAX_LINE_SPRITES 29\r |
| 521 | extern unsigned char HighLnSpr[240][3 + MAX_LINE_SPRITES];\r |
| cc68a136 |
522 | \r |
| c8d1e9b6 |
523 | // draw2.c\r |
| eff55556 |
524 | PICO_INTERNAL void PicoFrameFull();\r |
| cc68a136 |
525 | \r |
| 200772b7 |
526 | // mode4.c\r |
| 527 | void PicoFrameStartMode4(void);\r |
| 528 | void PicoLineMode4(int line);\r |
| 529 | void PicoDoHighPal555M4(void);\r |
| 87b0845f |
530 | void PicoDrawSetColorFormatMode4(int which);\r |
| 200772b7 |
531 | \r |
| c8d1e9b6 |
532 | // memory.c\r |
| eff55556 |
533 | PICO_INTERNAL void PicoMemSetup(void);\r |
| af37bca8 |
534 | unsigned int PicoRead8_io(unsigned int a);\r |
| 535 | unsigned int PicoRead16_io(unsigned int a);\r |
| 536 | void PicoWrite8_io(unsigned int a, unsigned int d);\r |
| 537 | void PicoWrite16_io(unsigned int a, unsigned int d);\r |
| 538 | \r |
| 539 | // pico/memory.c\r |
| 540 | PICO_INTERNAL void PicoMemSetupPico(void);\r |
| cc68a136 |
541 | \r |
| c8d1e9b6 |
542 | // cd/memory.c\r |
| eff55556 |
543 | PICO_INTERNAL void PicoMemSetupCD(void);\r |
| 0ace9b9a |
544 | void PicoMemStateLoaded(void);\r |
| cc68a136 |
545 | \r |
| c8d1e9b6 |
546 | // pico.c\r |
| cc68a136 |
547 | extern struct Pico Pico;\r |
| 548 | extern struct PicoSRAM SRam;\r |
| 5f9a0d16 |
549 | extern int PicoPadInt[2];\r |
| cc68a136 |
550 | extern int emustatus;\r |
| 5e128c6d |
551 | extern int scanlines_total;\r |
| f8ef8ff7 |
552 | extern void (*PicoResetHook)(void);\r |
| b0677887 |
553 | extern void (*PicoLineHook)(void);\r |
| 1e6b5e39 |
554 | PICO_INTERNAL int CheckDMA(void);\r |
| 555 | PICO_INTERNAL void PicoDetectRegion(void);\r |
| 4b9c5888 |
556 | PICO_INTERNAL void PicoSyncZ80(int m68k_cycles_done);\r |
| cc68a136 |
557 | \r |
| c8d1e9b6 |
558 | // cd/pico.c\r |
| 2aa27095 |
559 | PICO_INTERNAL void PicoInitMCD(void);\r |
| e5f426aa |
560 | PICO_INTERNAL void PicoExitMCD(void);\r |
| 1cb1584b |
561 | PICO_INTERNAL void PicoPowerMCD(void);\r |
| 2aa27095 |
562 | PICO_INTERNAL int PicoResetMCD(void);\r |
| 563 | PICO_INTERNAL void PicoFrameMCD(void);\r |
| cc68a136 |
564 | \r |
| c8d1e9b6 |
565 | // pico/pico.c\r |
| 2aa27095 |
566 | PICO_INTERNAL void PicoInitPico(void);\r |
| ed367a3f |
567 | PICO_INTERNAL void PicoReratePico(void);\r |
| 9037e45d |
568 | \r |
| c8d1e9b6 |
569 | // pico/xpcm.c\r |
| ef4eb506 |
570 | PICO_INTERNAL void PicoPicoPCMUpdate(short *buffer, int length, int stereo);\r |
| 571 | PICO_INTERNAL void PicoPicoPCMReset(void);\r |
| 213c16ad |
572 | PICO_INTERNAL void PicoPicoPCMRerate(int xpcm_rate);\r |
| ef4eb506 |
573 | \r |
| c8d1e9b6 |
574 | // sek.c\r |
| 2aa27095 |
575 | PICO_INTERNAL void SekInit(void);\r |
| 576 | PICO_INTERNAL int SekReset(void);\r |
| 3aa1e148 |
577 | PICO_INTERNAL void SekState(int *data);\r |
| eff55556 |
578 | PICO_INTERNAL void SekSetRealTAS(int use_real);\r |
| 5f9a0d16 |
579 | void SekStepM68k(void);\r |
| 053fd9b4 |
580 | void SekInitIdleDet(void);\r |
| 581 | void SekFinishIdleDet(void);\r |
| cc68a136 |
582 | \r |
| c8d1e9b6 |
583 | // cd/sek.c\r |
| 2aa27095 |
584 | PICO_INTERNAL void SekInitS68k(void);\r |
| 585 | PICO_INTERNAL int SekResetS68k(void);\r |
| 586 | PICO_INTERNAL int SekInterruptS68k(int irq);\r |
| cc68a136 |
587 | \r |
| 7a93adeb |
588 | // sound/sound.c\r |
| c9e1affc |
589 | PICO_INTERNAL void cdda_start_play();\r |
| 590 | extern short cdda_out_buffer[2*1152];\r |
| 7a93adeb |
591 | extern int PsndLen_exc_cnt;\r |
| 592 | extern int PsndLen_exc_add;\r |
| 48dc74f2 |
593 | extern int timer_a_next_oflow, timer_a_step; // in z80 cycles\r |
| 594 | extern int timer_b_next_oflow, timer_b_step;\r |
| 43e6eaad |
595 | \r |
| 596 | void ym2612_sync_timers(int z80_cycles, int mode_old, int mode_new);\r |
| d2721b08 |
597 | void ym2612_pack_state(void);\r |
| 453d2a6e |
598 | void ym2612_unpack_state(void);\r |
| 4b9c5888 |
599 | \r |
| e53704e6 |
600 | #define TIMER_NO_OFLOW 0x70000000\r |
| 45a1ef71 |
601 | // tA = 72 * (1024 - NA) / M\r |
| 602 | #define TIMER_A_TICK_ZCYCLES 17203\r |
| 603 | // tB = 1152 * (256 - NA) / M\r |
| 604 | #define TIMER_B_TICK_ZCYCLES 262800 // 275251 broken, see Dai Makaimura\r |
| e53704e6 |
605 | \r |
| 4b9c5888 |
606 | #define timers_cycle() \\r |
| e53704e6 |
607 | if (timer_a_next_oflow > 0 && timer_a_next_oflow < TIMER_NO_OFLOW) \\r |
| 43e6eaad |
608 | timer_a_next_oflow -= Pico.m.pal ? 70938*256 : 59659*256; \\r |
| e53704e6 |
609 | if (timer_b_next_oflow > 0 && timer_b_next_oflow < TIMER_NO_OFLOW) \\r |
| 43e6eaad |
610 | timer_b_next_oflow -= Pico.m.pal ? 70938*256 : 59659*256; \\r |
| 611 | ym2612_sync_timers(0, ym2612.OPN.ST.mode, ym2612.OPN.ST.mode);\r |
| 4b9c5888 |
612 | \r |
| 613 | #define timers_reset() \\r |
| e53704e6 |
614 | timer_a_next_oflow = timer_b_next_oflow = TIMER_NO_OFLOW; \\r |
| 48dc74f2 |
615 | timer_a_step = TIMER_A_TICK_ZCYCLES * 1024; \\r |
| 616 | timer_b_step = TIMER_B_TICK_ZCYCLES * 256;\r |
| 43e6eaad |
617 | \r |
| 7a93adeb |
618 | \r |
| c8d1e9b6 |
619 | // videoport.c\r |
| eff55556 |
620 | PICO_INTERNAL_ASM void PicoVideoWrite(unsigned int a,unsigned short d);\r |
| 621 | PICO_INTERNAL_ASM unsigned int PicoVideoRead(unsigned int a);\r |
| 9761a7d0 |
622 | PICO_INTERNAL_ASM unsigned int PicoVideoRead8(unsigned int a);\r |
| 5de27868 |
623 | extern int (*PicoDmaHook)(unsigned int source, int len, unsigned short **srcp, unsigned short **limitp);\r |
| cc68a136 |
624 | \r |
| c8d1e9b6 |
625 | // misc.c\r |
| eff55556 |
626 | PICO_INTERNAL_ASM void memcpy16(unsigned short *dest, unsigned short *src, int count);\r |
| 627 | PICO_INTERNAL_ASM void memcpy16bswap(unsigned short *dest, void *src, int count);\r |
| 628 | PICO_INTERNAL_ASM void memcpy32(int *dest, int *src, int count); // 32bit word count\r |
| 629 | PICO_INTERNAL_ASM void memset32(int *dest, int c, int count);\r |
| cc68a136 |
630 | \r |
| 45f2f245 |
631 | // eeprom.c\r |
| 632 | void EEPROM_write8(unsigned int a, unsigned int d);\r |
| 633 | void EEPROM_write16(unsigned int d);\r |
| 634 | unsigned int EEPROM_read(void);\r |
| 635 | \r |
| c8d1e9b6 |
636 | // z80 functionality wrappers\r |
| 637 | PICO_INTERNAL void z80_init(void);\r |
| 638 | PICO_INTERNAL void z80_pack(unsigned char *data);\r |
| 639 | PICO_INTERNAL void z80_unpack(unsigned char *data);\r |
| 640 | PICO_INTERNAL void z80_reset(void);\r |
| 641 | PICO_INTERNAL void z80_exit(void);\r |
| c8d1e9b6 |
642 | \r |
| 643 | // cd/misc.c\r |
| eff55556 |
644 | PICO_INTERNAL_ASM void wram_2M_to_1M(unsigned char *m);\r |
| 645 | PICO_INTERNAL_ASM void wram_1M_to_2M(unsigned char *m);\r |
| 646 | \r |
| 647 | // cd/buffering.c\r |
| 648 | PICO_INTERNAL void PicoCDBufferRead(void *dest, int lba);\r |
| 649 | \r |
| 650 | // sound/sound.c\r |
| 9d917eea |
651 | PICO_INTERNAL void PsndReset(void);\r |
| 4b9c5888 |
652 | PICO_INTERNAL void PsndDoDAC(int line_to);\r |
| 9d917eea |
653 | PICO_INTERNAL void PsndClear(void);\r |
| 7b3f44c6 |
654 | PICO_INTERNAL void PsndGetSamples(int y);\r |
| 2ec9bec5 |
655 | PICO_INTERNAL void PsndGetSamplesMS(void);\r |
| 4b9c5888 |
656 | extern int PsndDacLine;\r |
| cc68a136 |
657 | \r |
| 3e49ffd0 |
658 | // sms.c\r |
| 659 | void PicoPowerMS(void);\r |
| 2ec9bec5 |
660 | void PicoResetMS(void);\r |
| 3e49ffd0 |
661 | void PicoMemSetupMS(void);\r |
| 662 | void PicoFrameMS(void);\r |
| 87b0845f |
663 | void PicoFrameDrawOnlyMS(void);\r |
| 3e49ffd0 |
664 | \r |
| be2c4208 |
665 | // 32x/32x.c\r |
| 666 | extern struct Pico32x Pico32x;\r |
| 667 | void Pico32xInit(void);\r |
| 974fdb5b |
668 | void PicoPower32x(void);\r |
| be2c4208 |
669 | void PicoReset32x(void);\r |
| 974fdb5b |
670 | void Pico32xStartup(void);\r |
| 5e49c3a8 |
671 | void PicoUnload32x(void);\r |
| 974fdb5b |
672 | void PicoFrame32x(void);\r |
| 4ea707e1 |
673 | void p32x_update_irls(void);\r |
| be2c4208 |
674 | \r |
| 675 | // 32x/memory.c\r |
| 974fdb5b |
676 | struct Pico32xMem *Pico32xMem;\r |
| be2c4208 |
677 | unsigned int PicoRead8_32x(unsigned int a);\r |
| 678 | unsigned int PicoRead16_32x(unsigned int a);\r |
| 679 | void PicoWrite8_32x(unsigned int a, unsigned int d);\r |
| 680 | void PicoWrite16_32x(unsigned int a, unsigned int d);\r |
| 681 | void PicoMemSetup32x(void);\r |
| 974fdb5b |
682 | void Pico32xSwapDRAM(int b);\r |
| 87accdf7 |
683 | void p32x_poll_event(int cpu_mask, int is_vdp);\r |
| 974fdb5b |
684 | \r |
| 685 | // 32x/draw.c\r |
| 686 | void FinalizeLine32xRGB555(int sh, int line);\r |
| be2c4208 |
687 | \r |
| db1d3564 |
688 | // 32x/pwm.c\r |
| 689 | unsigned int p32x_pwm_read16(unsigned int a);\r |
| 690 | void p32x_pwm_write16(unsigned int a, unsigned int d);\r |
| db1d3564 |
691 | void p32x_pwm_update(int *buf32, int length, int stereo);\r |
| 1d7a28a7 |
692 | void p32x_timers_do(int new_line);\r |
| 693 | void p32x_timers_recalc(void);\r |
| db1d3564 |
694 | extern int pwm_frame_smp_cnt;\r |
| 695 | \r |
| 45f2f245 |
696 | /* avoid dependency on newer glibc */\r |
| 697 | static __inline int isspace_(int c)\r |
| 698 | {\r |
| 699 | return (0x09 <= c && c <= 0x0d) || c == ' ';\r |
| 700 | }\r |
| 701 | \r |
| b8cbd802 |
702 | // emulation event logging\r |
| 703 | #ifndef EL_LOGMASK\r |
| 704 | #define EL_LOGMASK 0\r |
| 705 | #endif\r |
| 706 | \r |
| 017512f2 |
707 | #define EL_HVCNT 0x00000001 /* hv counter reads */\r |
| 708 | #define EL_SR 0x00000002 /* SR reads */\r |
| 709 | #define EL_INTS 0x00000004 /* ints and acks */\r |
| 43e6eaad |
710 | #define EL_YMTIMER 0x00000008 /* ym2612 timer stuff */\r |
| 017512f2 |
711 | #define EL_INTSW 0x00000010 /* log irq switching on/off */\r |
| 712 | #define EL_ASVDP 0x00000020 /* VDP accesses during active scan */\r |
| 713 | #define EL_VDPDMA 0x00000040 /* VDP DMA transfers and their timing */\r |
| 714 | #define EL_BUSREQ 0x00000080 /* z80 busreq r/w or reset w */\r |
| 715 | #define EL_Z80BNK 0x00000100 /* z80 i/o through bank area */\r |
| 716 | #define EL_SRAMIO 0x00000200 /* sram i/o */\r |
| 717 | #define EL_EEPROM 0x00000400 /* eeprom debug */\r |
| 718 | #define EL_UIO 0x00000800 /* unmapped i/o */\r |
| 719 | #define EL_IO 0x00001000 /* all i/o */\r |
| 720 | #define EL_CDPOLL 0x00002000 /* MCD: log poll detection */\r |
| 721 | #define EL_SVP 0x00004000 /* SVP stuff */\r |
| fa22af4c |
722 | #define EL_PICOHW 0x00008000 /* Pico stuff */\r |
| 053fd9b4 |
723 | #define EL_IDLE 0x00010000 /* idle loop det. */\r |
| af37bca8 |
724 | #define EL_CDREGS 0x00020000 /* MCD: register access */\r |
| 725 | #define EL_CDREG3 0x00040000 /* MCD: register 3 only */\r |
| be2c4208 |
726 | #define EL_32X 0x00080000\r |
| 1b3f5844 |
727 | #define EL_PWM 0x00100000 /* 32X PWM stuff (LOTS of output) */\r |
| 017512f2 |
728 | \r |
| 729 | #define EL_STATUS 0x40000000 /* status messages */\r |
| 730 | #define EL_ANOMALY 0x80000000 /* some unexpected conditions (during emulation) */\r |
| b8cbd802 |
731 | \r |
| 732 | #if EL_LOGMASK\r |
| 7d0143a2 |
733 | extern void lprintf(const char *fmt, ...);\r |
| b8cbd802 |
734 | #define elprintf(w,f,...) \\r |
| 735 | { \\r |
| 736 | if ((w) & EL_LOGMASK) \\r |
| 7d0143a2 |
737 | lprintf("%05i:%03i: " f "\n",Pico.m.frame_count,Pico.m.scanline,##__VA_ARGS__); \\r |
| b8cbd802 |
738 | }\r |
| dca310c4 |
739 | #elif defined(_MSC_VER)\r |
| 740 | #define elprintf\r |
| b8cbd802 |
741 | #else\r |
| 742 | #define elprintf(w,f,...)\r |
| 743 | #endif\r |
| 744 | \r |
| dca310c4 |
745 | #ifdef _MSC_VER\r |
| 746 | #define cdprintf\r |
| 747 | #else\r |
| 748 | #define cdprintf(x...)\r |
| 749 | #endif\r |
| 750 | \r |
| 3e49ffd0 |
751 | #if defined(__GNUC__) && __GNUC__ >= 4 && __GNUC_MINOR__ >= 3\r |
| c8d1e9b6 |
752 | #define MEMH_FUNC __attribute__((aligned(4)))\r |
| 753 | #else\r |
| 754 | #define MEMH_FUNC\r |
| 755 | #endif\r |
| 756 | \r |
| 5e89f0f5 |
757 | #ifdef __GNUC__\r |
| 758 | #define NOINLINE __attribute__((noinline))\r |
| 759 | #else\r |
| 760 | #define NOINLINE\r |
| 761 | #endif\r |
| 762 | \r |
| f8af9634 |
763 | #ifdef __cplusplus\r |
| 764 | } // End of extern "C"\r |
| 765 | #endif\r |
| 766 | \r |
| eff55556 |
767 | #endif // PICO_INTERNAL_INCLUDED\r |
| 768 | \r |
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