[pcsx_rearmed.git] / libpcsxcore / new_dynarec / linkage_arm.S

/* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
 *   linkage_arm.s for PCSX                                                *
 *   Copyright (C) 2009-2011 Ari64                                         *
 *   Copyright (C) 2010-2013 Gražvydas "notaz" Ignotas                     *
 *                                                                         *
 *   This program is free software; you can redistribute it and/or modify  *
 *   it under the terms of the GNU General Public License as published by  *
 *   the Free Software Foundation; either version 2 of the License, or     *
 *   (at your option) any later version.                                   *
 *                                                                         *
 *   This program is distributed in the hope that it will be useful,       *
 *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
 *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
 *   GNU General Public License for more details.                          *
 *                                                                         *
 *   You should have received a copy of the GNU General Public License     *
 *   along with this program; if not, write to the                         *
 *   Free Software Foundation, Inc.,                                       *
 *   51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.          *
 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */

#include "arm_features.h"
#include "new_dynarec_config.h"
#include "linkage_offsets.h"


#ifdef __MACH__
#define dynarec_local		ESYM(dynarec_local)
#define ndrc_add_jump_out	ESYM(ndrc_add_jump_out)
#define ndrc_try_restore_block	ESYM(ndrc_try_restore_block)
#define ndrc_get_addr_ht	ESYM(ndrc_get_addr_ht)
#define ndrc_get_addr_ht_param	ESYM(ndrc_get_addr_ht_param)
#define ndrc_write_invalidate_one ESYM(ndrc_write_invalidate_one)
#define gen_interupt		ESYM(gen_interupt)
#define gteCheckStallRaw	ESYM(gteCheckStallRaw)
#define psxException		ESYM(psxException)
#endif

	.bss
	.align	4
	.global dynarec_local
	.type	dynarec_local, %object
	.size	dynarec_local, LO_dynarec_local_size
dynarec_local:
	.space	LO_dynarec_local_size

#define DRC_VAR_(name, vname, size_) \
	vname = dynarec_local + LO_##name; \
	.global vname; \
	.type	vname, %object; \
	.size	vname, size_

#define DRC_VAR(name, size_) \
	DRC_VAR_(name, ESYM(name), size_)

DRC_VAR(next_interupt, 4)
DRC_VAR(cycle_count, 4)
DRC_VAR(last_count, 4)
DRC_VAR(pending_exception, 4)
DRC_VAR(stop, 4)
DRC_VAR(branch_target, 4)
DRC_VAR(address, 4)
DRC_VAR(hack_addr, 4)
DRC_VAR(psxRegs, LO_psxRegs_end - LO_psxRegs)

/* psxRegs */
@DRC_VAR(reg, 128)
DRC_VAR(lo, 4)
DRC_VAR(hi, 4)
DRC_VAR(reg_cop0, 128)
DRC_VAR(reg_cop2d, 128)
DRC_VAR(reg_cop2c, 128)
DRC_VAR(pcaddr, 4)
@DRC_VAR(code, 4)
@DRC_VAR(cycle, 4)
@DRC_VAR(interrupt, 4)
@DRC_VAR(intCycle, 256)

DRC_VAR(rcnts, 7*4*4)
DRC_VAR(inv_code_start, 4)
DRC_VAR(inv_code_end, 4)
DRC_VAR(mem_rtab, 4)
DRC_VAR(mem_wtab, 4)
DRC_VAR(psxH_ptr, 4)
DRC_VAR(zeromem_ptr, 4)
DRC_VAR(invc_ptr, 4)
DRC_VAR(scratch_buf_ptr, 4)
DRC_VAR(ram_offset, 4)
DRC_VAR(mini_ht, 256)


	.syntax unified
	.text
	.align	2

#ifndef HAVE_ARMV5
.macro blx rd
	mov	lr, pc
	bx	\rd
.endm
#endif

.macro load_varadr reg var
#if defined(HAVE_ARMV7) && defined(TEXRELS_FORBIDDEN)
	movw	\reg, #:lower16:(\var-(1678f+8))
	movt	\reg, #:upper16:(\var-(1678f+8))
1678:
	add	\reg, pc
#elif defined(HAVE_ARMV7) && !defined(__PIC__)
	movw	\reg, #:lower16:\var
	movt	\reg, #:upper16:\var
#else
	ldr	\reg, =\var
#endif
.endm

.macro load_varadr_ext reg var
#if defined(HAVE_ARMV7) && defined(TEXRELS_FORBIDDEN)
	movw	\reg, #:lower16:(ptr_\var-(1678f+8))
	movt	\reg, #:upper16:(ptr_\var-(1678f+8))
1678:
	ldr	\reg, [pc, \reg]
#else
	load_varadr \reg \var
#endif
.endm

.macro mov_16 reg imm
#ifdef HAVE_ARMV7
	movw	\reg, #\imm
#else
	mov	\reg, #(\imm & 0x00ff)
	orr	\reg, #(\imm & 0xff00)
#endif
.endm

.macro mov_24 reg imm
#ifdef HAVE_ARMV7
	movw	\reg, #(\imm & 0xffff)
	movt	\reg, #(\imm >> 16)
#else
	mov	\reg, #(\imm & 0x0000ff)
	orr	\reg, #(\imm & 0x00ff00)
	orr	\reg, #(\imm & 0xff0000)
#endif
.endm

FUNCTION(dyna_linker):
	/* r0 = virtual target address */
	/* r1 = pointer to an instruction to patch */
#ifndef NO_WRITE_EXEC
	ldr	r7, [r1]
	mov	r4, r0
	add	r6, r7, #2
	mov	r5, r1
	lsl	r6, r6, #8
	/* must not compile - that might expire the caller block */
	mov	r1, #0
	bl	ndrc_get_addr_ht_param

	movs	r8, r0
	beq	0f
	add	r6, r5, r6, asr #6  /* old target */
	teq	r0, r6
	moveq	pc, r0 /* Stale i-cache */
	mov	r0, r4
	mov	r1, r6
	bl	ndrc_add_jump_out

	sub	r2, r8, r5
	and	r1, r7, #0xff000000
	lsl	r2, r2, #6
	sub	r1, r1, #2
	add	r1, r1, r2, lsr #8
	str	r1, [r5]
	mov	pc, r8
0:
	mov	r0, r4
#else
	/* XXX: should be able to do better than this... */
#endif
	bl	ndrc_get_addr_ht
	mov	pc, r0
	.size	dyna_linker, .-dyna_linker

	.align	2
FUNCTION(jump_vaddr_r1):
	mov	r0, r1
	b	jump_vaddr_r0
	.size	jump_vaddr_r1, .-jump_vaddr_r1
FUNCTION(jump_vaddr_r2):
	mov	r0, r2
	b	jump_vaddr_r0
	.size	jump_vaddr_r2, .-jump_vaddr_r2
FUNCTION(jump_vaddr_r3):
	mov	r0, r3
	b	jump_vaddr_r0
	.size	jump_vaddr_r3, .-jump_vaddr_r3
FUNCTION(jump_vaddr_r4):
	mov	r0, r4
	b	jump_vaddr_r0
	.size	jump_vaddr_r4, .-jump_vaddr_r4
FUNCTION(jump_vaddr_r5):
	mov	r0, r5
	b	jump_vaddr_r0
	.size	jump_vaddr_r5, .-jump_vaddr_r5
FUNCTION(jump_vaddr_r6):
	mov	r0, r6
	b	jump_vaddr_r0
	.size	jump_vaddr_r6, .-jump_vaddr_r6
FUNCTION(jump_vaddr_r8):
	mov	r0, r8
	b	jump_vaddr_r0
	.size	jump_vaddr_r8, .-jump_vaddr_r8
FUNCTION(jump_vaddr_r9):
	mov	r0, r9
	b	jump_vaddr_r0
	.size	jump_vaddr_r9, .-jump_vaddr_r9
FUNCTION(jump_vaddr_r10):
	mov	r0, r10
	b	jump_vaddr_r0
	.size	jump_vaddr_r10, .-jump_vaddr_r10
FUNCTION(jump_vaddr_r12):
	mov	r0, r12
	b	jump_vaddr_r0
	.size	jump_vaddr_r12, .-jump_vaddr_r12
FUNCTION(jump_vaddr_r7):
	add	r0, r7, #0
	.size	jump_vaddr_r7, .-jump_vaddr_r7
FUNCTION(jump_vaddr_r0):
	bl	ndrc_get_addr_ht
	mov	pc, r0
	.size	jump_vaddr_r0, .-jump_vaddr_r0

	.align	2
FUNCTION(cc_interrupt):
	ldr	r0, [fp, #LO_last_count]
	mov	r1, #0
	add	r10, r0, r10
	str	r1, [fp, #LO_pending_exception]
	str	r10, [fp, #LO_cycle]		/* PCSX cycles */
@@	str	r10, [fp, #LO_reg_cop0+36]	/* Count - not on PSX */
	mov	r10, lr

	add	r0, fp, #(LO_psxRegs + 34*4)    /* CP0 */
	bl	gen_interupt
	mov	lr, r10
	ldr	r10, [fp, #LO_cycle]
	ldr	r0, [fp, #LO_next_interupt]
	ldr	r1, [fp, #LO_pending_exception]
	ldr	r2, [fp, #LO_stop]
	str	r0, [fp, #LO_last_count]
	sub	r10, r10, r0
	tst	r2, r2
	ldmfdne	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, ip, pc}
	tst	r1, r1
	moveq	pc, lr
	ldr	r0, [fp, #LO_pcaddr]
	bl	ndrc_get_addr_ht
	mov	pc, r0
	.size	cc_interrupt, .-cc_interrupt

	.align	2
FUNCTION(jump_overflow_ds):
	mov	r0, #(12<<2)  /* R3000E_Ov */
	mov	r1, #1
	b	call_psxException
FUNCTION(jump_overflow):
	mov	r0, #(12<<2)
	mov	r1, #0
	b	call_psxException
FUNCTION(jump_break_ds):
	mov	r0, #(9<<2)  /* R3000E_Bp */
	mov	r1, #1
	b	call_psxException
FUNCTION(jump_break):
	mov	r0, #(9<<2)
	mov	r1, #0
	b	call_psxException
FUNCTION(jump_syscall_ds):
	mov	r0, #(8<<2)  /* R3000E_Syscall */
	mov	r1, #2
	b	call_psxException
FUNCTION(jump_syscall):
	mov	r0, #(8<<2)
	mov	r1, #0

call_psxException:
	ldr	r3, [fp, #LO_last_count]
	str	r2, [fp, #LO_pcaddr]
	add	r10, r3, r10
	str	r10, [fp, #LO_cycle]            /* PCSX cycles */
	add	r2, fp, #(LO_psxRegs + 34*4)    /* CP0 */
	bl	psxException

	/* note: psxException might do recursive recompiler call from it's HLE code,
	 * so be ready for this */
FUNCTION(jump_to_new_pc):
	ldr	r1, [fp, #LO_next_interupt]
	ldr	r10, [fp, #LO_cycle]
	ldr	r0, [fp, #LO_pcaddr]
	sub	r10, r10, r1
	str	r1, [fp, #LO_last_count]
	bl	ndrc_get_addr_ht
	mov	pc, r0
	.size	jump_to_new_pc, .-jump_to_new_pc

	.align	2
FUNCTION(new_dyna_leave):
	ldr	r0, [fp, #LO_last_count]
	add	r12, fp, #28
	add	r10, r0, r10
	str	r10, [fp, #LO_cycle]
	ldmfd	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, ip, pc}
	.size	new_dyna_leave, .-new_dyna_leave

	.align	2
FUNCTION(invalidate_addr_r0):
	stmia	fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
	b	invalidate_addr_call
	.size	invalidate_addr_r0, .-invalidate_addr_r0
	.align	2
FUNCTION(invalidate_addr_r1):
	stmia	fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
	mov	r0, r1
	b	invalidate_addr_call
	.size	invalidate_addr_r1, .-invalidate_addr_r1
	.align	2
FUNCTION(invalidate_addr_r2):
	stmia	fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
	mov	r0, r2
	b	invalidate_addr_call
	.size	invalidate_addr_r2, .-invalidate_addr_r2
	.align	2
FUNCTION(invalidate_addr_r3):
	stmia	fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
	mov	r0, r3
	b	invalidate_addr_call
	.size	invalidate_addr_r3, .-invalidate_addr_r3
	.align	2
FUNCTION(invalidate_addr_r4):
	stmia	fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
	mov	r0, r4
	b	invalidate_addr_call
	.size	invalidate_addr_r4, .-invalidate_addr_r4
	.align	2
FUNCTION(invalidate_addr_r5):
	stmia	fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
	mov	r0, r5
	b	invalidate_addr_call
	.size	invalidate_addr_r5, .-invalidate_addr_r5
	.align	2
FUNCTION(invalidate_addr_r6):
	stmia	fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
	mov	r0, r6
	b	invalidate_addr_call
	.size	invalidate_addr_r6, .-invalidate_addr_r6
	.align	2
FUNCTION(invalidate_addr_r7):
	stmia	fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
	mov	r0, r7
	b	invalidate_addr_call
	.size	invalidate_addr_r7, .-invalidate_addr_r7
	.align	2
FUNCTION(invalidate_addr_r8):
	stmia	fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
	mov	r0, r8
	b	invalidate_addr_call
	.size	invalidate_addr_r8, .-invalidate_addr_r8
	.align	2
FUNCTION(invalidate_addr_r9):
	stmia	fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
	mov	r0, r9
	b	invalidate_addr_call
	.size	invalidate_addr_r9, .-invalidate_addr_r9
	.align	2
FUNCTION(invalidate_addr_r10):
	stmia	fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
	mov	r0, r10
	b	invalidate_addr_call
	.size	invalidate_addr_r10, .-invalidate_addr_r10
	.align	2
FUNCTION(invalidate_addr_r12):
	stmia	fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
	mov	r0, r12
	.size	invalidate_addr_r12, .-invalidate_addr_r12
	.align	2
invalidate_addr_call:
	ldr	r12, [fp, #LO_inv_code_start]
	ldr	lr, [fp, #LO_inv_code_end]
	cmp	r0, r12
	cmpcs   lr, r0
	blcc	ndrc_write_invalidate_one
	ldmia	fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, pc}
	.size	invalidate_addr_call, .-invalidate_addr_call

	.align	2
FUNCTION(new_dyna_start):
	/* ip is stored to conform EABI alignment */
	stmfd	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, ip, lr}
	mov	fp, r0 /* dynarec_local */
	ldr	r0, [fp, #LO_pcaddr]
	bl	ndrc_get_addr_ht
	ldr	r1, [fp, #LO_next_interupt]
	ldr	r10, [fp, #LO_cycle]
	str	r1, [fp, #LO_last_count]
	sub	r10, r10, r1
	mov	pc, r0
	.size	new_dyna_start, .-new_dyna_start

/* --------------------------------------- */

.align	2

.macro pcsx_read_mem readop tab_shift
	/* r0 = address, r1 = handler_tab, r2 = cycles */
	lsl	r3, r0, #20
	lsr	r3, #(20+\tab_shift)
	ldr	r12, [fp, #LO_last_count]
	ldr	r1, [r1, r3, lsl #2]
	add	r2, r2, r12
	lsls	r1, #1
.if \tab_shift == 1
	lsl	r3, #1
	\readop	r0, [r1, r3]
.else
	\readop	r0, [r1, r3, lsl #\tab_shift]
.endif
	movcc	pc, lr
	str	r2, [fp, #LO_cycle]
	bx	r1
.endm

FUNCTION(jump_handler_read8):
	add     r1, #0x1000/4*4 + 0x1000/2*4 @ shift to r8 part
	pcsx_read_mem ldrbcc, 0

FUNCTION(jump_handler_read16):
	add     r1, #0x1000/4*4              @ shift to r16 part
	pcsx_read_mem ldrhcc, 1

FUNCTION(jump_handler_read32):
	pcsx_read_mem ldrcc, 2


.macro memhandler_post
	ldr	r0, [fp, #LO_next_interupt]
	ldr	r2, [fp, #LO_cycle]        @ memhandlers can modify cc, like dma
	str	r0, [fp, #LO_last_count]
	sub	r0, r2, r0
.endm

.macro pcsx_write_mem wrtop tab_shift
	/* r0 = address, r1 = data, r2 = cycles, r3 = handler_tab */
	lsl	r12,r0, #20
	lsr	r12, #(20+\tab_shift)
	ldr	r3, [r3, r12, lsl #2]
	str	r0, [fp, #LO_address]      @ some handlers still need it..
	lsls	r3, #1
	mov     r0, r2                     @ cycle return in case of direct store
.if \tab_shift == 1
	lsl	r12, #1
	\wrtop	r1, [r3, r12]
.else
	\wrtop	r1, [r3, r12, lsl #\tab_shift]
.endif
	movcc	pc, lr
	ldr	r12, [fp, #LO_last_count]
	mov     r0, r1
	add	r2, r2, r12
	str	r2, [fp, #LO_cycle]

	str	lr, [fp, #LO_saved_lr]
	blx	r3
	ldr	lr, [fp, #LO_saved_lr]

	memhandler_post
	bx	lr
.endm

FUNCTION(jump_handler_write8):
	add     r3, #0x1000/4*4 + 0x1000/2*4 @ shift to r8 part
	pcsx_write_mem strbcc, 0

FUNCTION(jump_handler_write16):
	add     r3, #0x1000/4*4              @ shift to r16 part
	pcsx_write_mem strhcc, 1

FUNCTION(jump_handler_write32):
	pcsx_write_mem strcc, 2

FUNCTION(jump_handler_write_h):
	/* r0 = address, r1 = data, r2 = cycles, r3 = handler */
	ldr	r12, [fp, #LO_last_count]
	str	r0, [fp, #LO_address]      @ some handlers still need it..
	add	r2, r2, r12
	mov     r0, r1
	str	r2, [fp, #LO_cycle]

	str	lr, [fp, #LO_saved_lr]
	blx	r3
	ldr	lr, [fp, #LO_saved_lr]

	memhandler_post
	bx	lr

FUNCTION(jump_handle_swl):
	/* r0 = address, r1 = data, r2 = cycles */
	ldr	r3, [fp, #LO_mem_wtab]
	mov	r12,r0,lsr #12
	ldr	r3, [r3, r12, lsl #2]
	lsls	r3, #1
	bcs	4f
	add	r3, r0, r3
	mov	r0, r2
	tst	r3, #2
	beq	101f
	tst	r3, #1
	beq	2f
3:
	str	r1, [r3, #-3]
	bx	lr
2:
	lsr	r2, r1, #8
	lsr	r1, #24
	strh	r2, [r3, #-2]
	strb	r1, [r3]
	bx	lr
101:
	tst	r3, #1
	lsrne	r1, #16		@ 1
	lsreq	r12, r1, #24	@ 0
	strhne	r1, [r3, #-1]
	strbeq	r12, [r3]
	bx	lr
4:
	mov	r0, r2
@	b	abort
	bx	lr		@ TODO?


FUNCTION(jump_handle_swr):
	/* r0 = address, r1 = data, r2 = cycles */
	ldr	r3, [fp, #LO_mem_wtab]
	mov	r12,r0,lsr #12
	ldr	r3, [r3, r12, lsl #2]
	lsls	r3, #1
	bcs	4f
	add	r3, r0, r3
	and	r12,r3, #3
	mov	r0, r2
	cmp	r12,#2
	strbgt	r1, [r3]	@ 3
	strheq	r1, [r3]	@ 2
	cmp	r12,#1
	strlt	r1, [r3]	@ 0
	bxne	lr
	lsr	r2, r1, #8	@ 1
	strb	r1, [r3]
	strh	r2, [r3, #1]
	bx	lr
4:
	mov	r0, r2
@	b	abort
	bx	lr		@ TODO?


.macro rcntx_read_mode0 num
	/* r0 = address, r2 = cycles */
	ldr	r3, [fp, #LO_rcnts+6*4+7*4*\num] @ cycleStart
	mov	r0, r2, lsl #16
	sub	r0, r0, r3, lsl #16
	lsr	r0, #16
	bx	lr
.endm

FUNCTION(rcnt0_read_count_m0):
	rcntx_read_mode0 0

FUNCTION(rcnt1_read_count_m0):
	rcntx_read_mode0 1

FUNCTION(rcnt2_read_count_m0):
	rcntx_read_mode0 2

FUNCTION(rcnt0_read_count_m1):
	/* r0 = address, r2 = cycles */
	ldr	r3, [fp, #LO_rcnts+6*4+7*4*0] @ cycleStart
	mov_16	r1, 0x3334
	sub	r2, r2, r3
	mul	r0, r1, r2		@ /= 5
	lsr	r0, #16
	bx	lr

FUNCTION(rcnt1_read_count_m1):
	/* r0 = address, r2 = cycles */
	ldr	r3, [fp, #LO_rcnts+6*4+7*4*1]
	mov_24	r1, 0x1e6cde
	sub	r2, r2, r3
	umull	r3, r0, r1, r2		@ ~ /= hsync_cycles, max ~0x1e6cdd
	bx	lr

FUNCTION(rcnt2_read_count_m1):
	/* r0 = address, r2 = cycles */
	ldr	r3, [fp, #LO_rcnts+6*4+7*4*2]
	mov	r0, r2, lsl #16-3
	sub	r0, r0, r3, lsl #16-3
	lsr	r0, #16			@ /= 8
	bx	lr

FUNCTION(call_gteStall):
	/* r0 = op_cycles, r1 = cycles */
	ldr	r2, [fp, #LO_last_count]
	str	lr, [fp, #LO_saved_lr]
	add	r1, r1, r2
	str	r1, [fp, #LO_cycle]
	add	r1, fp, #LO_psxRegs
	bl	gteCheckStallRaw
	ldr	lr, [fp, #LO_saved_lr]
	add	r10, r10, r0
	bx	lr

#ifdef HAVE_ARMV6

FUNCTION(get_reg):
	ldr	r12, [r0]
	and	r1, r1, #0xff
	ldr	r2, [r0, #4]
	orr	r1, r1, r1, lsl #8
	ldr	r3, [r0, #8]
	orr	r1, r1, r1, lsl #16   @ searched char in every byte
	ldrb    r0, [r0, #12]         @ last byte
	eor	r12, r12, r1
	eor	r2, r2, r1
	eor	r3, r3, r1
	cmp     r0, r1, lsr #24
	mov	r0, #12
	mvn	r1, #0                @ r1=~0
	bxeq	lr
	orr	r3, r3, #0xff000000   @ EXCLUDE_REG
	uadd8	r0, r12, r1           @ add and set GE bits when not 0 (match)
	mov	r12, #0
	sel	r0, r12, r1           @ 0 if no match, else ff in some byte
	uadd8	r2, r2, r1
	sel	r2, r12, r1
	uadd8	r3, r3, r1
	sel	r3, r12, r1
	mov	r12, #3
	clz     r0, r0                @ 0, 8, 16, 24 or 32
	clz     r2, r2
	clz     r3, r3
	sub	r0, r12, r0, lsr #3   @ 3, 2, 1, 0 or -1
	sub	r2, r12, r2, lsr #3
	sub	r3, r12, r3, lsr #3
	orr	r2, r2, #4
	orr	r3, r3, #8
	and	r0, r0, r2
	and	r0, r0, r3
	bx	lr

#endif /* HAVE_ARMV6 */

@ vim:filetype=armasm
Commit	Line	Data
57871462	1	/* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
7e605697	2	* linkage_arm.s for PCSX *
0bbd1454	3	* Copyright (C) 2009-2011 Ari64 *
b1f89e6f	4	* Copyright (C) 2010-2013 Gražvydas "notaz" Ignotas *
57871462	5	* *
	6	* This program is free software; you can redistribute it and/or modify *
	7	* it under the terms of the GNU General Public License as published by *
	8	* the Free Software Foundation; either version 2 of the License, or *
	9	* (at your option) any later version. *
	10	* *
	11	* This program is distributed in the hope that it will be useful, *
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of *
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
	14	* GNU General Public License for more details. *
	15	* *
	16	* You should have received a copy of the GNU General Public License *
	17	* along with this program; if not, write to the *
	18	* Free Software Foundation, Inc., *
	19	* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. *
	20	* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
b021ee75	21
665f33e1	22	#include "arm_features.h"
d148d265	23	#include "new_dynarec_config.h"
b1f89e6f	24	#include "linkage_offsets.h"
	25
	26
	27	#ifdef __MACH__
	28	#define dynarec_local ESYM(dynarec_local)
104df9d3	29	#define ndrc_add_jump_out ESYM(ndrc_add_jump_out)
398d6924	30	#define ndrc_try_restore_block ESYM(ndrc_try_restore_block)
104df9d3	31	#define ndrc_get_addr_ht ESYM(ndrc_get_addr_ht)
104df9d3	32	#define ndrc_get_addr_ht_param ESYM(ndrc_get_addr_ht_param)
9b495f6e	33	#define ndrc_write_invalidate_one ESYM(ndrc_write_invalidate_one)
b1f89e6f	34	#define gen_interupt ESYM(gen_interupt)
81dbbf4c	35	#define gteCheckStallRaw ESYM(gteCheckStallRaw)
d1150cd6	36	#define psxException ESYM(psxException)
b1f89e6f	37	#endif
f95a77f7	38
57871462	39	.bss
57871462	40	.align 4
b1f89e6f	41	.global dynarec_local
57871462	42	.type dynarec_local, %object
b1f89e6f	43	.size dynarec_local, LO_dynarec_local_size
57871462	44	dynarec_local:
b1f89e6f	45	.space LO_dynarec_local_size
	46
	47	#define DRC_VAR_(name, vname, size_) \
	48	vname = dynarec_local + LO_##name; \
	49	.global vname; \
	50	.type vname, %object; \
	51	.size vname, size_
	52
	53	#define DRC_VAR(name, size_) \
	54	DRC_VAR_(name, ESYM(name), size_)
	55
	56	DRC_VAR(next_interupt, 4)
	57	DRC_VAR(cycle_count, 4)
	58	DRC_VAR(last_count, 4)
	59	DRC_VAR(pending_exception, 4)
	60	DRC_VAR(stop, 4)
687b4580	61	DRC_VAR(branch_target, 4)
b1f89e6f	62	DRC_VAR(address, 4)
7f94b097	63	DRC_VAR(hack_addr, 4)
b1f89e6f	64	DRC_VAR(psxRegs, LO_psxRegs_end - LO_psxRegs)
f95a77f7	65
f95a77f7	66	/* psxRegs */
7c3a5182	67	@DRC_VAR(reg, 128)
b1f89e6f	68	DRC_VAR(lo, 4)
	69	DRC_VAR(hi, 4)
	70	DRC_VAR(reg_cop0, 128)
	71	DRC_VAR(reg_cop2d, 128)
	72	DRC_VAR(reg_cop2c, 128)
	73	DRC_VAR(pcaddr, 4)
	74	@DRC_VAR(code, 4)
	75	@DRC_VAR(cycle, 4)
	76	@DRC_VAR(interrupt, 4)
	77	@DRC_VAR(intCycle, 256)
	78
	79	DRC_VAR(rcnts, 744)
687b4580	80	DRC_VAR(inv_code_start, 4)
687b4580	81	DRC_VAR(inv_code_end, 4)
b1f89e6f	82	DRC_VAR(mem_rtab, 4)
	83	DRC_VAR(mem_wtab, 4)
	84	DRC_VAR(psxH_ptr, 4)
	85	DRC_VAR(zeromem_ptr, 4)
687b4580	86	DRC_VAR(invc_ptr, 4)
c6d5790c	87	DRC_VAR(scratch_buf_ptr, 4)
37387d8b	88	DRC_VAR(ram_offset, 4)
b1f89e6f	89	DRC_VAR(mini_ht, 256)
63cb0298	90
57871462	91
b861c0a9	92	.syntax unified
	93	.text
	94	.align 2
	95
665f33e1	96	#ifndef HAVE_ARMV5
	97	.macro blx rd
	98	mov lr, pc
	99	bx \rd
	100	.endm
	101	#endif
	102
c67af2ac	103	.macro load_varadr reg var
0e4ad319	104	#if defined(HAVE_ARMV7) && defined(TEXRELS_FORBIDDEN)
1f4e070a	105	movw \reg, #:lower16:(\var-(1678f+8))
1f4e070a	106	movt \reg, #:upper16:(\var-(1678f+8))
b861c0a9	107	1678:
b861c0a9	108	add \reg, pc
0e4ad319	109	#elif defined(HAVE_ARMV7) && !defined(__PIC__)
	110	movw \reg, #:lower16:\var
	111	movt \reg, #:upper16:\var
c67af2ac	112	#else
274c4243	113	ldr \reg, =\var
c67af2ac	114	#endif
274c4243	115	.endm
274c4243	116
b861c0a9	117	.macro load_varadr_ext reg var
0e4ad319	118	#if defined(HAVE_ARMV7) && defined(TEXRELS_FORBIDDEN)
1f4e070a	119	movw \reg, #:lower16:(ptr_\var-(1678f+8))
1f4e070a	120	movt \reg, #:upper16:(ptr_\var-(1678f+8))
b861c0a9	121	1678:
	122	ldr \reg, [pc, \reg]
	123	#else
	124	load_varadr \reg \var
	125	#endif
	126	.endm
	127
b1be1eee	128	.macro mov_16 reg imm
8f2bb0cb	129	#ifdef HAVE_ARMV7
b1be1eee	130	movw \reg, #\imm
c67af2ac	131	#else
b1be1eee	132	mov \reg, #(\imm & 0x00ff)
b1be1eee	133	orr \reg, #(\imm & 0xff00)
c67af2ac	134	#endif
b1be1eee	135	.endm
	136
	137	.macro mov_24 reg imm
8f2bb0cb	138	#ifdef HAVE_ARMV7
b1be1eee	139	movw \reg, #(\imm & 0xffff)
b1be1eee	140	movt \reg, #(\imm >> 16)
c67af2ac	141	#else
b1be1eee	142	mov \reg, #(\imm & 0x0000ff)
	143	orr \reg, #(\imm & 0x00ff00)
	144	orr \reg, #(\imm & 0xff0000)
c67af2ac	145	#endif
b1be1eee	146	.endm
b1be1eee	147
104df9d3	148	FUNCTION(dyna_linker):
	149	/* r0 = virtual target address */
	150	/* r1 = pointer to an instruction to patch */
d148d265	151	#ifndef NO_WRITE_EXEC
104df9d3	152	ldr r7, [r1]
	153	mov r4, r0
	154	add r6, r7, #2
	155	mov r5, r1
	156	lsl r6, r6, #8
	157	/* must not compile - that might expire the caller block */
	158	mov r1, #0
	159	bl ndrc_get_addr_ht_param
	160
	161	movs r8, r0
	162	beq 0f
	163	add r6, r5, r6, asr #6 /* old target */
398d6924	164	teq r0, r6
398d6924	165	moveq pc, r0 /* Stale i-cache */
398d6924	166	mov r0, r4
76f71c27	167	mov r1, r6
104df9d3	168	bl ndrc_add_jump_out
104df9d3	169
76f71c27	170	sub r2, r8, r5
57871462	171	and r1, r7, #0xff000000
	172	lsl r2, r2, #6
	173	sub r1, r1, #2
	174	add r1, r1, r2, lsr #8
	175	str r1, [r5]
76f71c27	176	mov pc, r8
104df9d3	177	0:
398d6924	178	mov r0, r4
d148d265	179	#else
d148d265	180	/* XXX: should be able to do better than this... */
d148d265	181	#endif
104df9d3	182	bl ndrc_get_addr_ht
57871462	183	mov pc, r0
4bdc30ab	184	.size dyna_linker, .-dyna_linker
7139f3c8	185
57871462	186	.align 2
5c6457c3	187	FUNCTION(jump_vaddr_r1):
57871462	188	mov r0, r1
104df9d3	189	b jump_vaddr_r0
57871462	190	.size jump_vaddr_r1, .-jump_vaddr_r1
5c6457c3	191	FUNCTION(jump_vaddr_r2):
57871462	192	mov r0, r2
104df9d3	193	b jump_vaddr_r0
57871462	194	.size jump_vaddr_r2, .-jump_vaddr_r2
5c6457c3	195	FUNCTION(jump_vaddr_r3):
57871462	196	mov r0, r3
104df9d3	197	b jump_vaddr_r0
57871462	198	.size jump_vaddr_r3, .-jump_vaddr_r3
5c6457c3	199	FUNCTION(jump_vaddr_r4):
57871462	200	mov r0, r4
104df9d3	201	b jump_vaddr_r0
57871462	202	.size jump_vaddr_r4, .-jump_vaddr_r4
5c6457c3	203	FUNCTION(jump_vaddr_r5):
57871462	204	mov r0, r5
104df9d3	205	b jump_vaddr_r0
57871462	206	.size jump_vaddr_r5, .-jump_vaddr_r5
5c6457c3	207	FUNCTION(jump_vaddr_r6):
57871462	208	mov r0, r6
104df9d3	209	b jump_vaddr_r0
57871462	210	.size jump_vaddr_r6, .-jump_vaddr_r6
5c6457c3	211	FUNCTION(jump_vaddr_r8):
57871462	212	mov r0, r8
104df9d3	213	b jump_vaddr_r0
57871462	214	.size jump_vaddr_r8, .-jump_vaddr_r8
5c6457c3	215	FUNCTION(jump_vaddr_r9):
57871462	216	mov r0, r9
104df9d3	217	b jump_vaddr_r0
57871462	218	.size jump_vaddr_r9, .-jump_vaddr_r9
5c6457c3	219	FUNCTION(jump_vaddr_r10):
57871462	220	mov r0, r10
104df9d3	221	b jump_vaddr_r0
57871462	222	.size jump_vaddr_r10, .-jump_vaddr_r10
5c6457c3	223	FUNCTION(jump_vaddr_r12):
57871462	224	mov r0, r12
104df9d3	225	b jump_vaddr_r0
57871462	226	.size jump_vaddr_r12, .-jump_vaddr_r12
5c6457c3	227	FUNCTION(jump_vaddr_r7):
57871462	228	add r0, r7, #0
57871462	229	.size jump_vaddr_r7, .-jump_vaddr_r7
104df9d3	230	FUNCTION(jump_vaddr_r0):
104df9d3	231	bl ndrc_get_addr_ht
57871462	232	mov pc, r0
104df9d3	233	.size jump_vaddr_r0, .-jump_vaddr_r0
7139f3c8	234
57871462	235	.align 2
5c6457c3	236	FUNCTION(cc_interrupt):
b1f89e6f	237	ldr r0, [fp, #LO_last_count]
57871462	238	mov r1, #0
57871462	239	add r10, r0, r10
b1f89e6f	240	str r1, [fp, #LO_pending_exception]
b1f89e6f	241	str r10, [fp, #LO_cycle] /* PCSX cycles */
b4ab351d	242	@@ str r10, [fp, #LO_reg_cop0+36] /* Count - not on PSX */
57871462	243	mov r10, lr
398d6924	244
6d75addf	245	add r0, fp, #(LO_psxRegs + 344) / CP0 */
57871462	246	bl gen_interupt
57871462	247	mov lr, r10
b1f89e6f	248	ldr r10, [fp, #LO_cycle]
	249	ldr r0, [fp, #LO_next_interupt]
	250	ldr r1, [fp, #LO_pending_exception]
	251	ldr r2, [fp, #LO_stop]
	252	str r0, [fp, #LO_last_count]
57871462	253	sub r10, r10, r0
57871462	254	tst r2, r2
b861c0a9	255	ldmfdne sp!, {r4, r5, r6, r7, r8, r9, sl, fp, ip, pc}
57871462	256	tst r1, r1
57871462	257	moveq pc, lr
b1f89e6f	258	ldr r0, [fp, #LO_pcaddr]
104df9d3	259	bl ndrc_get_addr_ht
57871462	260	mov pc, r0
57871462	261	.size cc_interrupt, .-cc_interrupt
7139f3c8	262
57871462	263	.align 2
a5cd72d0	264	FUNCTION(jump_overflow_ds):
	265	mov r0, #(12<<2) /* R3000E_Ov */
	266	mov r1, #1
	267	b call_psxException
	268	FUNCTION(jump_overflow):
	269	mov r0, #(12<<2)
	270	mov r1, #0
	271	b call_psxException
d1150cd6	272	FUNCTION(jump_break_ds):
a5cd72d0	273	mov r0, #(9<<2) /* R3000E_Bp */
d1150cd6	274	mov r1, #1
	275	b call_psxException
	276	FUNCTION(jump_break):
a5cd72d0	277	mov r0, #(9<<2)
d1150cd6	278	mov r1, #0
	279	b call_psxException
	280	FUNCTION(jump_syscall_ds):
a5cd72d0	281	mov r0, #(8<<2) /* R3000E_Syscall */
bc7c5acb	282	mov r1, #2
d1150cd6	283	b call_psxException
5c6457c3	284	FUNCTION(jump_syscall):
a5cd72d0	285	mov r0, #(8<<2)
d1150cd6	286	mov r1, #0
	287
	288	call_psxException:
	289	ldr r3, [fp, #LO_last_count]
	290	str r2, [fp, #LO_pcaddr]
	291	add r10, r3, r10
6d75addf	292	str r10, [fp, #LO_cycle] /* PCSX cycles */
6d75addf	293	add r2, fp, #(LO_psxRegs + 344) / CP0 */
d1150cd6	294	bl psxException
7139f3c8	295
b1f89e6f	296	/* note: psxException might do recursive recompiler call from it's HLE code,
7139f3c8	297	* so be ready for this */
3968e69e	298	FUNCTION(jump_to_new_pc):
b1f89e6f	299	ldr r1, [fp, #LO_next_interupt]
	300	ldr r10, [fp, #LO_cycle]
	301	ldr r0, [fp, #LO_pcaddr]
822b27d1	302	sub r10, r10, r1
b1f89e6f	303	str r1, [fp, #LO_last_count]
104df9d3	304	bl ndrc_get_addr_ht
7139f3c8	305	mov pc, r0
3968e69e	306	.size jump_to_new_pc, .-jump_to_new_pc
0d16cda2	307
7139f3c8	308	.align 2
5c6457c3	309	FUNCTION(new_dyna_leave):
b1f89e6f	310	ldr r0, [fp, #LO_last_count]
7139f3c8	311	add r12, fp, #28
7139f3c8	312	add r10, r0, r10
b1f89e6f	313	str r10, [fp, #LO_cycle]
b021ee75	314	ldmfd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, ip, pc}
7139f3c8	315	.size new_dyna_leave, .-new_dyna_leave
7139f3c8	316
0bbd1454	317	.align 2
5c6457c3	318	FUNCTION(invalidate_addr_r0):
5df0e313	319	stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
0bbd1454	320	b invalidate_addr_call
	321	.size invalidate_addr_r0, .-invalidate_addr_r0
	322	.align 2
5c6457c3	323	FUNCTION(invalidate_addr_r1):
5df0e313	324	stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
9be4ba64	325	mov r0, r1
0bbd1454	326	b invalidate_addr_call
	327	.size invalidate_addr_r1, .-invalidate_addr_r1
	328	.align 2
5c6457c3	329	FUNCTION(invalidate_addr_r2):
5df0e313	330	stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
9be4ba64	331	mov r0, r2
0bbd1454	332	b invalidate_addr_call
	333	.size invalidate_addr_r2, .-invalidate_addr_r2
	334	.align 2
5c6457c3	335	FUNCTION(invalidate_addr_r3):
5df0e313	336	stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
9be4ba64	337	mov r0, r3
0bbd1454	338	b invalidate_addr_call
	339	.size invalidate_addr_r3, .-invalidate_addr_r3
	340	.align 2
5c6457c3	341	FUNCTION(invalidate_addr_r4):
5df0e313	342	stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
9be4ba64	343	mov r0, r4
0bbd1454	344	b invalidate_addr_call
	345	.size invalidate_addr_r4, .-invalidate_addr_r4
	346	.align 2
5c6457c3	347	FUNCTION(invalidate_addr_r5):
5df0e313	348	stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
9be4ba64	349	mov r0, r5
0bbd1454	350	b invalidate_addr_call
	351	.size invalidate_addr_r5, .-invalidate_addr_r5
	352	.align 2
5c6457c3	353	FUNCTION(invalidate_addr_r6):
5df0e313	354	stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
9be4ba64	355	mov r0, r6
0bbd1454	356	b invalidate_addr_call
	357	.size invalidate_addr_r6, .-invalidate_addr_r6
	358	.align 2
5c6457c3	359	FUNCTION(invalidate_addr_r7):
5df0e313	360	stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
9be4ba64	361	mov r0, r7
0bbd1454	362	b invalidate_addr_call
	363	.size invalidate_addr_r7, .-invalidate_addr_r7
	364	.align 2
5c6457c3	365	FUNCTION(invalidate_addr_r8):
5df0e313	366	stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
9be4ba64	367	mov r0, r8
0bbd1454	368	b invalidate_addr_call
	369	.size invalidate_addr_r8, .-invalidate_addr_r8
	370	.align 2
5c6457c3	371	FUNCTION(invalidate_addr_r9):
5df0e313	372	stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
9be4ba64	373	mov r0, r9
0bbd1454	374	b invalidate_addr_call
	375	.size invalidate_addr_r9, .-invalidate_addr_r9
	376	.align 2
5c6457c3	377	FUNCTION(invalidate_addr_r10):
5df0e313	378	stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
9be4ba64	379	mov r0, r10
0bbd1454	380	b invalidate_addr_call
	381	.size invalidate_addr_r10, .-invalidate_addr_r10
	382	.align 2
5c6457c3	383	FUNCTION(invalidate_addr_r12):
5df0e313	384	stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
9be4ba64	385	mov r0, r12
0bbd1454	386	.size invalidate_addr_r12, .-invalidate_addr_r12
0bbd1454	387	.align 2
b1f89e6f	388	invalidate_addr_call:
	389	ldr r12, [fp, #LO_inv_code_start]
	390	ldr lr, [fp, #LO_inv_code_end]
9be4ba64	391	cmp r0, r12
9be4ba64	392	cmpcs lr, r0
9b495f6e	393	blcc ndrc_write_invalidate_one
5df0e313	394	ldmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, pc}
0bbd1454	395	.size invalidate_addr_call, .-invalidate_addr_call
0bbd1454	396
57871462	397	.align 2
5c6457c3	398	FUNCTION(new_dyna_start):
b021ee75	399	/* ip is stored to conform EABI alignment */
b021ee75	400	stmfd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, ip, lr}
be516ebe	401	mov fp, r0 /* dynarec_local */
b1f89e6f	402	ldr r0, [fp, #LO_pcaddr]
104df9d3	403	bl ndrc_get_addr_ht
b1f89e6f	404	ldr r1, [fp, #LO_next_interupt]
	405	ldr r10, [fp, #LO_cycle]
	406	str r1, [fp, #LO_last_count]
7139f3c8	407	sub r10, r10, r1
7139f3c8	408	mov pc, r0
57871462	409	.size new_dyna_start, .-new_dyna_start
7139f3c8	410
7e605697	411	/* --------------------------------------- */
7139f3c8	412
7e605697	413	.align 2
c6c3b1b3	414
	415	.macro pcsx_read_mem readop tab_shift
	416	/* r0 = address, r1 = handler_tab, r2 = cycles */
	417	lsl r3, r0, #20
	418	lsr r3, #(20+\tab_shift)
b1f89e6f	419	ldr r12, [fp, #LO_last_count]
c6c3b1b3	420	ldr r1, [r1, r3, lsl #2]
	421	add r2, r2, r12
	422	lsls r1, #1
	423	.if \tab_shift == 1
	424	lsl r3, #1
	425	\readop r0, [r1, r3]
	426	.else
	427	\readop r0, [r1, r3, lsl #\tab_shift]
	428	.endif
	429	movcc pc, lr
b1f89e6f	430	str r2, [fp, #LO_cycle]
c6c3b1b3	431	bx r1
	432	.endm
	433
5c6457c3	434	FUNCTION(jump_handler_read8):
c6c3b1b3	435	add r1, #0x1000/44 + 0x1000/24 @ shift to r8 part
b861c0a9	436	pcsx_read_mem ldrbcc, 0
c6c3b1b3	437
5c6457c3	438	FUNCTION(jump_handler_read16):
c6c3b1b3	439	add r1, #0x1000/4*4 @ shift to r16 part
10858959	440	pcsx_read_mem ldrhcc, 1
c6c3b1b3	441
5c6457c3	442	FUNCTION(jump_handler_read32):
c6c3b1b3	443	pcsx_read_mem ldrcc, 2
c6c3b1b3	444
b96d3df7	445
9b9af0d1	446	.macro memhandler_post
	447	ldr r0, [fp, #LO_next_interupt]
	448	ldr r2, [fp, #LO_cycle] @ memhandlers can modify cc, like dma
	449	str r0, [fp, #LO_last_count]
	450	sub r0, r2, r0
	451	.endm
	452
b96d3df7	453	.macro pcsx_write_mem wrtop tab_shift
	454	/* r0 = address, r1 = data, r2 = cycles, r3 = handler_tab */
	455	lsl r12,r0, #20
	456	lsr r12, #(20+\tab_shift)
	457	ldr r3, [r3, r12, lsl #2]
b1f89e6f	458	str r0, [fp, #LO_address] @ some handlers still need it..
b96d3df7	459	lsls r3, #1
9b9af0d1	460	mov r0, r2 @ cycle return in case of direct store
b96d3df7	461	.if \tab_shift == 1
	462	lsl r12, #1
	463	\wrtop r1, [r3, r12]
	464	.else
	465	\wrtop r1, [r3, r12, lsl #\tab_shift]
	466	.endif
	467	movcc pc, lr
b1f89e6f	468	ldr r12, [fp, #LO_last_count]
b96d3df7	469	mov r0, r1
b96d3df7	470	add r2, r2, r12
b1f89e6f	471	str r2, [fp, #LO_cycle]
9b9af0d1	472
9b9af0d1	473	str lr, [fp, #LO_saved_lr]
b96d3df7	474	blx r3
9b9af0d1	475	ldr lr, [fp, #LO_saved_lr]
b96d3df7	476
9b9af0d1	477	memhandler_post
687b4580	478	bx lr
b96d3df7	479	.endm
b96d3df7	480
5c6457c3	481	FUNCTION(jump_handler_write8):
b96d3df7	482	add r3, #0x1000/44 + 0x1000/24 @ shift to r8 part
b861c0a9	483	pcsx_write_mem strbcc, 0
b96d3df7	484
5c6457c3	485	FUNCTION(jump_handler_write16):
b96d3df7	486	add r3, #0x1000/4*4 @ shift to r16 part
b861c0a9	487	pcsx_write_mem strhcc, 1
b96d3df7	488
5c6457c3	489	FUNCTION(jump_handler_write32):
b96d3df7	490	pcsx_write_mem strcc, 2
b96d3df7	491
5c6457c3	492	FUNCTION(jump_handler_write_h):
b96d3df7	493	/* r0 = address, r1 = data, r2 = cycles, r3 = handler */
b1f89e6f	494	ldr r12, [fp, #LO_last_count]
b1f89e6f	495	str r0, [fp, #LO_address] @ some handlers still need it..
b96d3df7	496	add r2, r2, r12
b96d3df7	497	mov r0, r1
b1f89e6f	498	str r2, [fp, #LO_cycle]
9b9af0d1	499
9b9af0d1	500	str lr, [fp, #LO_saved_lr]
b96d3df7	501	blx r3
9b9af0d1	502	ldr lr, [fp, #LO_saved_lr]
b96d3df7	503
9b9af0d1	504	memhandler_post
687b4580	505	bx lr
b96d3df7	506
5c6457c3	507	FUNCTION(jump_handle_swl):
b96d3df7	508	/* r0 = address, r1 = data, r2 = cycles */
b1f89e6f	509	ldr r3, [fp, #LO_mem_wtab]
b96d3df7	510	mov r12,r0,lsr #12
	511	ldr r3, [r3, r12, lsl #2]
	512	lsls r3, #1
	513	bcs 4f
	514	add r3, r0, r3
	515	mov r0, r2
	516	tst r3, #2
	517	beq 101f
	518	tst r3, #1
	519	beq 2f
	520	3:
	521	str r1, [r3, #-3]
	522	bx lr
	523	2:
	524	lsr r2, r1, #8
	525	lsr r1, #24
	526	strh r2, [r3, #-2]
	527	strb r1, [r3]
	528	bx lr
	529	101:
	530	tst r3, #1
	531	lsrne r1, #16 @ 1
	532	lsreq r12, r1, #24 @ 0
b861c0a9	533	strhne r1, [r3, #-1]
b861c0a9	534	strbeq r12, [r3]
b96d3df7	535	bx lr
	536	4:
	537	mov r0, r2
63cb0298	538	@ b abort
b96d3df7	539	bx lr @ TODO?
	540
	541
5c6457c3	542	FUNCTION(jump_handle_swr):
b96d3df7	543	/* r0 = address, r1 = data, r2 = cycles */
b1f89e6f	544	ldr r3, [fp, #LO_mem_wtab]
b96d3df7	545	mov r12,r0,lsr #12
	546	ldr r3, [r3, r12, lsl #2]
	547	lsls r3, #1
	548	bcs 4f
	549	add r3, r0, r3
	550	and r12,r3, #3
	551	mov r0, r2
	552	cmp r12,#2
b861c0a9	553	strbgt r1, [r3] @ 3
b861c0a9	554	strheq r1, [r3] @ 2
b96d3df7	555	cmp r12,#1
	556	strlt r1, [r3] @ 0
	557	bxne lr
	558	lsr r2, r1, #8 @ 1
	559	strb r1, [r3]
	560	strh r2, [r3, #1]
	561	bx lr
	562	4:
	563	mov r0, r2
63cb0298	564	@ b abort
b96d3df7	565	bx lr @ TODO?
	566
	567
b1be1eee	568	.macro rcntx_read_mode0 num
b1be1eee	569	/* r0 = address, r2 = cycles */
b1f89e6f	570	ldr r3, [fp, #LO_rcnts+64+74*\num] @ cycleStart
b1be1eee	571	mov r0, r2, lsl #16
b861c0a9	572	sub r0, r0, r3, lsl #16
b1be1eee	573	lsr r0, #16
	574	bx lr
	575	.endm
	576
5c6457c3	577	FUNCTION(rcnt0_read_count_m0):
b1be1eee	578	rcntx_read_mode0 0
b1be1eee	579
5c6457c3	580	FUNCTION(rcnt1_read_count_m0):
b1be1eee	581	rcntx_read_mode0 1
b1be1eee	582
5c6457c3	583	FUNCTION(rcnt2_read_count_m0):
b1be1eee	584	rcntx_read_mode0 2
b1be1eee	585
5c6457c3	586	FUNCTION(rcnt0_read_count_m1):
b1be1eee	587	/* r0 = address, r2 = cycles */
b1f89e6f	588	ldr r3, [fp, #LO_rcnts+64+74*0] @ cycleStart
b1be1eee	589	mov_16 r1, 0x3334
	590	sub r2, r2, r3
	591	mul r0, r1, r2 @ /= 5
	592	lsr r0, #16
	593	bx lr
	594
5c6457c3	595	FUNCTION(rcnt1_read_count_m1):
b1be1eee	596	/* r0 = address, r2 = cycles */
b1f89e6f	597	ldr r3, [fp, #LO_rcnts+64+74*1]
b1be1eee	598	mov_24 r1, 0x1e6cde
	599	sub r2, r2, r3
	600	umull r3, r0, r1, r2 @ ~ /= hsync_cycles, max ~0x1e6cdd
	601	bx lr
	602
5c6457c3	603	FUNCTION(rcnt2_read_count_m1):
b1be1eee	604	/* r0 = address, r2 = cycles */
b1f89e6f	605	ldr r3, [fp, #LO_rcnts+64+74*2]
b1be1eee	606	mov r0, r2, lsl #16-3
b861c0a9	607	sub r0, r0, r3, lsl #16-3
b1be1eee	608	lsr r0, #16 @ /= 8
	609	bx lr
	610
81dbbf4c	611	FUNCTION(call_gteStall):
	612	/* r0 = op_cycles, r1 = cycles */
	613	ldr r2, [fp, #LO_last_count]
	614	str lr, [fp, #LO_saved_lr]
	615	add r1, r1, r2
	616	str r1, [fp, #LO_cycle]
	617	add r1, fp, #LO_psxRegs
	618	bl gteCheckStallRaw
	619	ldr lr, [fp, #LO_saved_lr]
	620	add r10, r10, r0
	621	bx lr
	622
cdc2da64	623	#ifdef HAVE_ARMV6
	624
	625	FUNCTION(get_reg):
	626	ldr r12, [r0]
	627	and r1, r1, #0xff
	628	ldr r2, [r0, #4]
	629	orr r1, r1, r1, lsl #8
	630	ldr r3, [r0, #8]
	631	orr r1, r1, r1, lsl #16 @ searched char in every byte
	632	ldrb r0, [r0, #12] @ last byte
	633	eor r12, r12, r1
	634	eor r2, r2, r1
	635	eor r3, r3, r1
	636	cmp r0, r1, lsr #24
	637	mov r0, #12
	638	mvn r1, #0 @ r1=~0
	639	bxeq lr
	640	orr r3, r3, #0xff000000 @ EXCLUDE_REG
	641	uadd8 r0, r12, r1 @ add and set GE bits when not 0 (match)
	642	mov r12, #0
	643	sel r0, r12, r1 @ 0 if no match, else ff in some byte
	644	uadd8 r2, r2, r1
	645	sel r2, r12, r1
	646	uadd8 r3, r3, r1
	647	sel r3, r12, r1
	648	mov r12, #3
	649	clz r0, r0 @ 0, 8, 16, 24 or 32
	650	clz r2, r2
	651	clz r3, r3
	652	sub r0, r12, r0, lsr #3 @ 3, 2, 1, 0 or -1
	653	sub r2, r12, r2, lsr #3
	654	sub r3, r12, r3, lsr #3
	655	orr r2, r2, #4
	656	orr r3, r3, #8
	657	and r0, r0, r2
	658	and r0, r0, r3
	659	bx lr
	660
	661	#endif /* HAVE_ARMV6 */
	662
7e605697	663	@ vim:filetype=armasm