[pcsx_rearmed.git] / libpcsxcore / new_dynarec / linkage_arm64.S

/* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
 *   linkage_arm.s for PCSX                                                *
 *   Copyright (C) 2009-2011 Ari64                                         *
 *   Copyright (C) 2021 notaz                                              *
 *                                                                         *
 *   This program is free software; you can redistribute it and/or modify  *
 *   it under the terms of the GNU General Public License as published by  *
 *   the Free Software Foundation; either version 2 of the License, or     *
 *   (at your option) any later version.                                   *
 *                                                                         *
 *   This program is distributed in the hope that it will be useful,       *
 *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
 *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
 *   GNU General Public License for more details.                          *
 *                                                                         *
 *   You should have received a copy of the GNU General Public License     *
 *   along with this program; if not, write to the                         *
 *   Free Software Foundation, Inc.,                                       *
 *   51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.          *
 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */

#include "arm_features.h"
#include "new_dynarec_config.h"
#include "assem_arm64.h"
#include "linkage_offsets.h"

#if (LO_mem_wtab & 7)
#error misligned pointers
#endif

.bss
	.align	4
	.global dynarec_local
	.type	dynarec_local, %object
	.size	dynarec_local, LO_dynarec_local_size
dynarec_local:
	.space	LO_dynarec_local_size

#define DRC_VAR_(name, vname, size_) \
	vname = dynarec_local + LO_##name; \
	.global vname; \
	.type	vname, %object; \
	.size	vname, size_

#define DRC_VAR(name, size_) \
	DRC_VAR_(name, ESYM(name), size_)

DRC_VAR(next_interupt, 4)
DRC_VAR(cycle_count, 4)
DRC_VAR(last_count, 4)
DRC_VAR(pending_exception, 4)
DRC_VAR(stop, 4)
DRC_VAR(branch_target, 4)
DRC_VAR(address, 4)
DRC_VAR(hack_addr, 4)
DRC_VAR(psxRegs, LO_psxRegs_end - LO_psxRegs)

/* psxRegs */
#DRC_VAR(reg, 128)
DRC_VAR(lo, 4)
DRC_VAR(hi, 4)
DRC_VAR(reg_cop0, 128)
DRC_VAR(reg_cop2d, 128)
DRC_VAR(reg_cop2c, 128)
DRC_VAR(pcaddr, 4)
#DRC_VAR(code, 4)
#DRC_VAR(cycle, 4)
#DRC_VAR(interrupt, 4)
#DRC_VAR(intCycle, 256)

DRC_VAR(rcnts, 7*4*4)
DRC_VAR(inv_code_start, 4)
DRC_VAR(inv_code_end, 4)
DRC_VAR(mem_rtab, 8)
DRC_VAR(mem_wtab, 8)
DRC_VAR(psxH_ptr, 8)
DRC_VAR(invc_ptr, 8)
DRC_VAR(zeromem_ptr, 8)
DRC_VAR(scratch_buf_ptr, 8)
DRC_VAR(ram_offset, 8)
DRC_VAR(mini_ht, 256)


	.text
	.align	2

FUNCTION(dyna_linker):
	/* r0 = virtual target address */
	/* r1 = instruction to patch */
	bl	ndrc_get_addr_ht
	br	x0
	.size	dyna_linker, .-dyna_linker

	.align	2
FUNCTION(cc_interrupt):
	ldr	w0, [rFP, #LO_last_count]
	add	rCC, w0, rCC
	str	wzr, [rFP, #LO_pending_exception]
	str	rCC, [rFP, #LO_cycle]		/* PCSX cycles */
#	str	rCC, [rFP, #LO_reg_cop0+36]	/* Count */
	mov	x21, lr
1:
	add	x0, rFP, #(LO_psxRegs + 34*4)   /* CP0 */
	bl	gen_interupt
	mov	lr, x21
	ldr	rCC, [rFP, #LO_cycle]
	ldr	w0, [rFP, #LO_next_interupt]
	ldr	w1, [rFP, #LO_pending_exception]
	ldr	w2, [rFP, #LO_stop]
	str	w0, [rFP, #LO_last_count]
	sub	rCC, rCC, w0
	cbnz	w2, new_dyna_leave
	cbnz	w1, 2f
	ret
2:
	ldr	w0, [rFP, #LO_pcaddr]
	bl	ndrc_get_addr_ht
	br	x0
	.size	cc_interrupt, .-cc_interrupt

	.align	2
FUNCTION(jump_overflow_ds):
	mov	w0, #(12<<2)  /* R3000E_Ov */
	mov	w1, #1
	b	call_psxException
FUNCTION(jump_overflow):
	mov	w0, #(12<<2)
	mov	w1, #0
	b	call_psxException
FUNCTION(jump_break_ds):
	mov	w0, #(9<<2)  /* R3000E_Bp */
	mov	w1, #1
	b	call_psxException
FUNCTION(jump_break):
	mov	w0, #(9<<2)
	mov	w1, #0
	b	call_psxException
FUNCTION(jump_syscall_ds):
	mov	w0, #(8<<2)  /* R3000E_Syscall */
	mov	w1, #2
	b	call_psxException
FUNCTION(jump_syscall):
	mov	w0, #(8<<2)
	mov	w1, #0

call_psxException:
	ldr	w3, [rFP, #LO_last_count]
	str	w2, [rFP, #LO_pcaddr]
	add	rCC, w3, rCC
	str	rCC, [rFP, #LO_cycle]           /* PCSX cycles */
	add	x2, rFP, #(LO_psxRegs + 34*4)   /* CP0 */
	bl	psxException

	/* note: psxException might do recursive recompiler call from it's HLE code,
	 * so be ready for this */
FUNCTION(jump_to_new_pc):
	ldr	w1, [rFP, #LO_next_interupt]
	ldr	rCC, [rFP, #LO_cycle]
	ldr	w0, [rFP, #LO_pcaddr]
	sub	rCC, rCC, w1
	str	w1, [rFP, #LO_last_count]
	bl	ndrc_get_addr_ht
	br	x0
	.size	jump_to_new_pc, .-jump_to_new_pc

	/* stack must be aligned by 16, and include space for save_regs() use */
	.align	2
FUNCTION(new_dyna_start):
	stp	x29, x30, [sp, #-SSP_ALL]!
	ldr	w1,  [x0, #LO_next_interupt]
	ldr	w2,  [x0, #LO_cycle]
	stp	x19, x20, [sp, #16*1]
	stp	x21, x22, [sp, #16*2]
	stp	x23, x24, [sp, #16*3]
	stp	x25, x26, [sp, #16*4]
	stp	x27, x28, [sp, #16*5]
	mov	rFP, x0
	ldr	w0,  [rFP, #LO_pcaddr]
	str	w1,  [rFP, #LO_last_count]
	sub	rCC, w2, w1
	bl	ndrc_get_addr_ht
	br	x0
	.size	new_dyna_start, .-new_dyna_start

	.align	2
FUNCTION(new_dyna_leave):
	ldr	w0,  [rFP, #LO_last_count]
	add	rCC, rCC, w0
	str	rCC, [rFP, #LO_cycle]
	ldp	x19, x20, [sp, #16*1]
	ldp	x21, x22, [sp, #16*2]
	ldp	x23, x24, [sp, #16*3]
	ldp	x25, x26, [sp, #16*4]
	ldp	x27, x28, [sp, #16*5]
	ldp	x29, x30, [sp], #SSP_ALL
	ret
	.size	new_dyna_leave, .-new_dyna_leave

/* --------------------------------------- */

.align	2

.macro memhandler_pre
	/* w0 = adddr/data, x1 = rhandler, w2 = cycles, x3 = whandler */
	ldr	w4, [rFP, #LO_last_count]
	add	w4, w4, w2
	str	w4, [rFP, #LO_cycle]
.endm

.macro memhandler_post
	ldr	w0, [rFP, #LO_next_interupt]
	ldr	w2, [rFP, #LO_cycle]        // memhandlers can modify cc, like dma
	str	w0, [rFP, #LO_last_count]
	sub	w0, w2, w0
.endm

FUNCTION(do_memhandler_pre):
	memhandler_pre
	ret

FUNCTION(do_memhandler_post):
	memhandler_post
	ret

.macro pcsx_read_mem readop tab_shift
	/* w0 = address, x1 = handler_tab, w2 = cycles */
	ubfm	w4, w0, #\tab_shift, #11
	ldr	x3, [x1, w4, uxtw #3]
	adds	x3, x3, x3
	bcs	0f
	\readop	w0, [x3, w4, uxtw #\tab_shift]
	ret
0:
	stp	xzr, x30, [sp, #-16]!
	memhandler_pre
	blr	x3
.endm

FUNCTION(jump_handler_read8):
	add     x1, x1, #0x1000/4*8 + 0x1000/2*8  /* shift to r8 part */
	pcsx_read_mem ldrb, 0
	b	handler_read_end

FUNCTION(jump_handler_read16):
	add     x1, x1, #0x1000/4*8               /* shift to r16 part */
	pcsx_read_mem ldrh, 1
	b	handler_read_end

FUNCTION(jump_handler_read32):
	pcsx_read_mem ldr, 2

handler_read_end:
	ldp	xzr, x30, [sp], #16
	ret

.macro pcsx_write_mem wrtop movop tab_shift
	/* w0 = address, w1 = data, w2 = cycles, x3 = handler_tab */
	ubfm	w4, w0, #\tab_shift, #11
	ldr	x3, [x3, w4, uxtw #3]
	adds	x3, x3, x3
	bcs	0f
	mov	w0, w2                    /* cycle return */
	\wrtop	w1, [x3, w4, uxtw #\tab_shift]
	ret
0:
	stp	xzr, x30, [sp, #-16]!
	str	w0, [rFP, #LO_address]    /* some handlers still need it... */
	\movop	w0, w1
	memhandler_pre
	blr	x3
.endm

FUNCTION(jump_handler_write8):
	add     x3, x3, #0x1000/4*8 + 0x1000/2*8  /* shift to r8 part */
	pcsx_write_mem strb uxtb 0
	b	handler_write_end

FUNCTION(jump_handler_write16):
	add     x3, x3, #0x1000/4*8               /* shift to r16 part */
	pcsx_write_mem strh uxth 1
	b	handler_write_end

FUNCTION(jump_handler_write32):
	pcsx_write_mem str mov 2

handler_write_end:
	memhandler_post
	ldp	xzr, x30, [sp], #16
	ret

FUNCTION(jump_handle_swl):
	/* w0 = address, w1 = data, w2 = cycles */
	ldr	x3, [rFP, #LO_mem_wtab]
	orr	w4, wzr, w0, lsr #12
	ldr	x3, [x3, w4, uxtw #3]
	adds	x3, x3, x3
	bcs	4f
	add	x3, x0, x3
	mov	w0, w2
	tbz	x3, #1, 10f	// & 2
	tbz	x3, #0, 2f	// & 1
3:
	stur	w1, [x3, #-3]
	ret
2:
	lsr	w2, w1, #8
	lsr	w1, w1, #24
	sturh	w2, [x3, #-2]
	strb	w1, [x3]
	ret
10:
	tbz	x3, #0, 0f	// & 1
1:
	lsr	w1, w1, #16
	sturh	w1, [x3, #-1]
	ret
0:
	lsr	w2, w1, #24
	strb	w2, [x3]
	ret
4:
	mov	w0, w2		// todo
	bl	abort
	ret

FUNCTION(jump_handle_swr):
	/* w0 = address, w1 = data, w2 = cycles */
	ldr	x3, [rFP, #LO_mem_wtab]
	orr	w4, wzr, w0, lsr #12
	ldr	x3, [x3, w4, uxtw #3]
	adds	x3, x3, x3
	bcs	4f
	add	x3, x0, x3
	mov	w0, w2
	tbz	x3, #1, 10f	// & 2
	tbz	x3, #0, 2f	// & 1
3:
	strb	w1, [x3]
	ret
2:
	strh	w1, [x3]
	ret
10:
	tbz	x3, #0, 0f	// & 1
1:
	lsr	w2, w1, #8
	strb	w1, [x3]
	sturh	w2, [x3, #1]
	ret
0:
	str	w1, [x3]
	ret
4:
	mov	w0, w2		// todo
	bl	abort
	ret

FUNCTION(call_gteStall):
	/* w0 = op_cycles, w1 = cycles */
	ldr	w2, [rFP, #LO_last_count]
	str	lr, [rFP, #LO_saved_lr]
	add	w1, w1, w2
	str	w1, [rFP, #LO_cycle]
	add	x1, rFP, #LO_psxRegs
	bl	gteCheckStallRaw
	ldr	lr, [rFP, #LO_saved_lr]
	add	rCC, rCC, w0
	ret
Commit	Line	Data
be516ebe	1	/* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
	2	* linkage_arm.s for PCSX *
	3	* Copyright (C) 2009-2011 Ari64 *
	4	* Copyright (C) 2021 notaz *
	5	* *
	6	* This program is free software; you can redistribute it and/or modify *
	7	* it under the terms of the GNU General Public License as published by *
	8	* the Free Software Foundation; either version 2 of the License, or *
	9	* (at your option) any later version. *
	10	* *
	11	* This program is distributed in the hope that it will be useful, *
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of *
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
	14	* GNU General Public License for more details. *
	15	* *
	16	* You should have received a copy of the GNU General Public License *
	17	* along with this program; if not, write to the *
	18	* Free Software Foundation, Inc., *
	19	* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. *
	20	* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
	21
	22	#include "arm_features.h"
	23	#include "new_dynarec_config.h"
	24	#include "assem_arm64.h"
	25	#include "linkage_offsets.h"
	26
39b71d9a	27	#if (LO_mem_wtab & 7)
	28	#error misligned pointers
	29	#endif
	30
be516ebe	31	.bss
	32	.align 4
	33	.global dynarec_local
	34	.type dynarec_local, %object
	35	.size dynarec_local, LO_dynarec_local_size
	36	dynarec_local:
	37	.space LO_dynarec_local_size
	38
	39	#define DRC_VAR_(name, vname, size_) \
	40	vname = dynarec_local + LO_##name; \
	41	.global vname; \
	42	.type vname, %object; \
	43	.size vname, size_
	44
	45	#define DRC_VAR(name, size_) \
	46	DRC_VAR_(name, ESYM(name), size_)
	47
	48	DRC_VAR(next_interupt, 4)
	49	DRC_VAR(cycle_count, 4)
	50	DRC_VAR(last_count, 4)
	51	DRC_VAR(pending_exception, 4)
	52	DRC_VAR(stop, 4)
687b4580	53	DRC_VAR(branch_target, 4)
be516ebe	54	DRC_VAR(address, 4)
7f94b097	55	DRC_VAR(hack_addr, 4)
be516ebe	56	DRC_VAR(psxRegs, LO_psxRegs_end - LO_psxRegs)
	57
	58	/* psxRegs */
7c3a5182	59	#DRC_VAR(reg, 128)
be516ebe	60	DRC_VAR(lo, 4)
	61	DRC_VAR(hi, 4)
	62	DRC_VAR(reg_cop0, 128)
	63	DRC_VAR(reg_cop2d, 128)
	64	DRC_VAR(reg_cop2c, 128)
	65	DRC_VAR(pcaddr, 4)
	66	#DRC_VAR(code, 4)
	67	#DRC_VAR(cycle, 4)
	68	#DRC_VAR(interrupt, 4)
	69	#DRC_VAR(intCycle, 256)
	70
	71	DRC_VAR(rcnts, 744)
be516ebe	72	DRC_VAR(inv_code_start, 4)
be516ebe	73	DRC_VAR(inv_code_end, 4)
687b4580	74	DRC_VAR(mem_rtab, 8)
	75	DRC_VAR(mem_wtab, 8)
	76	DRC_VAR(psxH_ptr, 8)
	77	DRC_VAR(invc_ptr, 8)
	78	DRC_VAR(zeromem_ptr, 8)
	79	DRC_VAR(scratch_buf_ptr, 8)
37387d8b	80	DRC_VAR(ram_offset, 8)
be516ebe	81	DRC_VAR(mini_ht, 256)
be516ebe	82
	83
	84	.text
	85	.align 2
	86
be516ebe	87	FUNCTION(dyna_linker):
	88	/* r0 = virtual target address */
	89	/* r1 = instruction to patch */
104df9d3	90	bl ndrc_get_addr_ht
4bdc30ab	91	br x0
be516ebe	92	.size dyna_linker, .-dyna_linker
be516ebe	93
be516ebe	94	.align 2
be516ebe	95	FUNCTION(cc_interrupt):
d1e4ebd9	96	ldr w0, [rFP, #LO_last_count]
d1e4ebd9	97	add rCC, w0, rCC
d1e4ebd9	98	str wzr, [rFP, #LO_pending_exception]
d1e4ebd9	99	str rCC, [rFP, #LO_cycle] /* PCSX cycles */
d1e4ebd9	100	# str rCC, [rFP, #LO_reg_cop0+36] /* Count */
d1e4ebd9	101	mov x21, lr
d1e4ebd9	102	1:
6d75addf	103	add x0, rFP, #(LO_psxRegs + 344) / CP0 */
d1e4ebd9	104	bl gen_interupt
	105	mov lr, x21
	106	ldr rCC, [rFP, #LO_cycle]
	107	ldr w0, [rFP, #LO_next_interupt]
	108	ldr w1, [rFP, #LO_pending_exception]
	109	ldr w2, [rFP, #LO_stop]
	110	str w0, [rFP, #LO_last_count]
	111	sub rCC, rCC, w0
	112	cbnz w2, new_dyna_leave
	113	cbnz w1, 2f
	114	ret
	115	2:
	116	ldr w0, [rFP, #LO_pcaddr]
104df9d3	117	bl ndrc_get_addr_ht
d1e4ebd9	118	br x0
be516ebe	119	.size cc_interrupt, .-cc_interrupt
be516ebe	120
be516ebe	121	.align 2
a5cd72d0	122	FUNCTION(jump_overflow_ds):
	123	mov w0, #(12<<2) /* R3000E_Ov */
	124	mov w1, #1
	125	b call_psxException
	126	FUNCTION(jump_overflow):
	127	mov w0, #(12<<2)
	128	mov w1, #0
	129	b call_psxException
d1150cd6	130	FUNCTION(jump_break_ds):
a5cd72d0	131	mov w0, #(9<<2) /* R3000E_Bp */
d1150cd6	132	mov w1, #1
	133	b call_psxException
	134	FUNCTION(jump_break):
a5cd72d0	135	mov w0, #(9<<2)
d1150cd6	136	mov w1, #0
	137	b call_psxException
	138	FUNCTION(jump_syscall_ds):
a5cd72d0	139	mov w0, #(8<<2) /* R3000E_Syscall */
bc7c5acb	140	mov w1, #2
d1150cd6	141	b call_psxException
be516ebe	142	FUNCTION(jump_syscall):
a5cd72d0	143	mov w0, #(8<<2)
d1150cd6	144	mov w1, #0
	145
	146	call_psxException:
	147	ldr w3, [rFP, #LO_last_count]
	148	str w2, [rFP, #LO_pcaddr]
	149	add rCC, w3, rCC
6d75addf	150	str rCC, [rFP, #LO_cycle] /* PCSX cycles */
6d75addf	151	add x2, rFP, #(LO_psxRegs + 344) / CP0 */
d1150cd6	152	bl psxException
be516ebe	153
be516ebe	154	/* note: psxException might do recursive recompiler call from it's HLE code,
be516ebe	155	* so be ready for this */
3968e69e	156	FUNCTION(jump_to_new_pc):
81dbbf4c	157	ldr w1, [rFP, #LO_next_interupt]
	158	ldr rCC, [rFP, #LO_cycle]
	159	ldr w0, [rFP, #LO_pcaddr]
3968e69e	160	sub rCC, rCC, w1
81dbbf4c	161	str w1, [rFP, #LO_last_count]
104df9d3	162	bl ndrc_get_addr_ht
be516ebe	163	br x0
3968e69e	164	.size jump_to_new_pc, .-jump_to_new_pc
be516ebe	165
687b4580	166	/* stack must be aligned by 16, and include space for save_regs() use */
be516ebe	167	.align 2
be516ebe	168	FUNCTION(new_dyna_start):
687b4580	169	stp x29, x30, [sp, #-SSP_ALL]!
be516ebe	170	ldr w1, [x0, #LO_next_interupt]
	171	ldr w2, [x0, #LO_cycle]
	172	stp x19, x20, [sp, #16*1]
	173	stp x21, x22, [sp, #16*2]
	174	stp x23, x24, [sp, #16*3]
	175	stp x25, x26, [sp, #16*4]
	176	stp x27, x28, [sp, #16*5]
	177	mov rFP, x0
	178	ldr w0, [rFP, #LO_pcaddr]
	179	str w1, [rFP, #LO_last_count]
	180	sub rCC, w2, w1
104df9d3	181	bl ndrc_get_addr_ht
be516ebe	182	br x0
	183	.size new_dyna_start, .-new_dyna_start
	184
	185	.align 2
	186	FUNCTION(new_dyna_leave):
	187	ldr w0, [rFP, #LO_last_count]
	188	add rCC, rCC, w0
	189	str rCC, [rFP, #LO_cycle]
	190	ldp x19, x20, [sp, #16*1]
	191	ldp x21, x22, [sp, #16*2]
	192	ldp x23, x24, [sp, #16*3]
	193	ldp x25, x26, [sp, #16*4]
	194	ldp x27, x28, [sp, #16*5]
687b4580	195	ldp x29, x30, [sp], #SSP_ALL
be516ebe	196	ret
	197	.size new_dyna_leave, .-new_dyna_leave
	198
	199	/* --------------------------------------- */
	200
	201	.align 2
	202
d1e4ebd9	203	.macro memhandler_pre
	204	/* w0 = adddr/data, x1 = rhandler, w2 = cycles, x3 = whandler */
	205	ldr w4, [rFP, #LO_last_count]
	206	add w4, w4, w2
	207	str w4, [rFP, #LO_cycle]
	208	.endm
	209
	210	.macro memhandler_post
9b9af0d1	211	ldr w0, [rFP, #LO_next_interupt]
	212	ldr w2, [rFP, #LO_cycle] // memhandlers can modify cc, like dma
	213	str w0, [rFP, #LO_last_count]
	214	sub w0, w2, w0
d1e4ebd9	215	.endm
	216
	217	FUNCTION(do_memhandler_pre):
	218	memhandler_pre
	219	ret
	220
	221	FUNCTION(do_memhandler_post):
	222	memhandler_post
	223	ret
	224
	225	.macro pcsx_read_mem readop tab_shift
	226	/* w0 = address, x1 = handler_tab, w2 = cycles */
d1e4ebd9	227	ubfm w4, w0, #\tab_shift, #11
	228	ldr x3, [x1, w4, uxtw #3]
	229	adds x3, x3, x3
	230	bcs 0f
	231	\readop w0, [x3, w4, uxtw #\tab_shift]
	232	ret
	233	0:
3968e69e	234	stp xzr, x30, [sp, #-16]!
d1e4ebd9	235	memhandler_pre
	236	blr x3
	237	.endm
	238
be516ebe	239	FUNCTION(jump_handler_read8):
3968e69e	240	add x1, x1, #0x1000/48 + 0x1000/28 /* shift to r8 part */
d1e4ebd9	241	pcsx_read_mem ldrb, 0
d1e4ebd9	242	b handler_read_end
be516ebe	243
be516ebe	244	FUNCTION(jump_handler_read16):
3968e69e	245	add x1, x1, #0x1000/48 / shift to r16 part */
d1e4ebd9	246	pcsx_read_mem ldrh, 1
d1e4ebd9	247	b handler_read_end
be516ebe	248
be516ebe	249	FUNCTION(jump_handler_read32):
d1e4ebd9	250	pcsx_read_mem ldr, 2
	251
	252	handler_read_end:
	253	ldp xzr, x30, [sp], #16
	254	ret
	255
	256	.macro pcsx_write_mem wrtop movop tab_shift
	257	/* w0 = address, w1 = data, w2 = cycles, x3 = handler_tab */
d1e4ebd9	258	ubfm w4, w0, #\tab_shift, #11
d1e4ebd9	259	ldr x3, [x3, w4, uxtw #3]
d1e4ebd9	260	adds x3, x3, x3
d1e4ebd9	261	bcs 0f
	262	mov w0, w2 /* cycle return */
	263	\wrtop w1, [x3, w4, uxtw #\tab_shift]
	264	ret
	265	0:
3968e69e	266	stp xzr, x30, [sp, #-16]!
3968e69e	267	str w0, [rFP, #LO_address] /* some handlers still need it... */
d1e4ebd9	268	\movop w0, w1
	269	memhandler_pre
	270	blr x3
	271	.endm
be516ebe	272
be516ebe	273	FUNCTION(jump_handler_write8):
3968e69e	274	add x3, x3, #0x1000/48 + 0x1000/28 /* shift to r8 part */
d1e4ebd9	275	pcsx_write_mem strb uxtb 0
d1e4ebd9	276	b handler_write_end
be516ebe	277
be516ebe	278	FUNCTION(jump_handler_write16):
3968e69e	279	add x3, x3, #0x1000/48 / shift to r16 part */
d1e4ebd9	280	pcsx_write_mem strh uxth 1
d1e4ebd9	281	b handler_write_end
be516ebe	282
be516ebe	283	FUNCTION(jump_handler_write32):
d1e4ebd9	284	pcsx_write_mem str mov 2
be516ebe	285
d1e4ebd9	286	handler_write_end:
	287	memhandler_post
	288	ldp xzr, x30, [sp], #16
	289	ret
be516ebe	290
be516ebe	291	FUNCTION(jump_handle_swl):
3968e69e	292	/* w0 = address, w1 = data, w2 = cycles */
81dbbf4c	293	ldr x3, [rFP, #LO_mem_wtab]
48ce2528	294	orr w4, wzr, w0, lsr #12
3968e69e	295	ldr x3, [x3, w4, uxtw #3]
	296	adds x3, x3, x3
	297	bcs 4f
	298	add x3, x0, x3
	299	mov w0, w2
	300	tbz x3, #1, 10f // & 2
	301	tbz x3, #0, 2f // & 1
	302	3:
	303	stur w1, [x3, #-3]
	304	ret
	305	2:
	306	lsr w2, w1, #8
	307	lsr w1, w1, #24
	308	sturh w2, [x3, #-2]
	309	strb w1, [x3]
	310	ret
	311	10:
	312	tbz x3, #0, 0f // & 1
	313	1:
	314	lsr w1, w1, #16
	315	sturh w1, [x3, #-1]
	316	ret
	317	0:
	318	lsr w2, w1, #24
	319	strb w2, [x3]
	320	ret
	321	4:
	322	mov w0, w2 // todo
be516ebe	323	bl abort
3968e69e	324	ret
be516ebe	325
be516ebe	326	FUNCTION(jump_handle_swr):
3968e69e	327	/* w0 = address, w1 = data, w2 = cycles */
81dbbf4c	328	ldr x3, [rFP, #LO_mem_wtab]
48ce2528	329	orr w4, wzr, w0, lsr #12
3968e69e	330	ldr x3, [x3, w4, uxtw #3]
	331	adds x3, x3, x3
	332	bcs 4f
	333	add x3, x0, x3
	334	mov w0, w2
	335	tbz x3, #1, 10f // & 2
	336	tbz x3, #0, 2f // & 1
	337	3:
	338	strb w1, [x3]
	339	ret
	340	2:
	341	strh w1, [x3]
	342	ret
	343	10:
	344	tbz x3, #0, 0f // & 1
	345	1:
	346	lsr w2, w1, #8
	347	strb w1, [x3]
	348	sturh w2, [x3, #1]
	349	ret
	350	0:
	351	str w1, [x3]
	352	ret
	353	4:
	354	mov w0, w2 // todo
be516ebe	355	bl abort
3968e69e	356	ret
be516ebe	357
81dbbf4c	358	FUNCTION(call_gteStall):
	359	/* w0 = op_cycles, w1 = cycles */
	360	ldr w2, [rFP, #LO_last_count]
	361	str lr, [rFP, #LO_saved_lr]
	362	add w1, w1, w2
	363	str w1, [rFP, #LO_cycle]
	364	add x1, rFP, #LO_psxRegs
	365	bl gteCheckStallRaw
	366	ldr lr, [rFP, #LO_saved_lr]
	367	add rCC, rCC, w0
	368	ret
	369