57871462 |
1 | /* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * |
2 | * Mupen64plus - new_dynarec.c * |
3 | * Copyright (C) 2009-2010 Ari64 * |
4 | * * |
5 | * This program is free software; you can redistribute it and/or modify * |
6 | * it under the terms of the GNU General Public License as published by * |
7 | * the Free Software Foundation; either version 2 of the License, or * |
8 | * (at your option) any later version. * |
9 | * * |
10 | * This program is distributed in the hope that it will be useful, * |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of * |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * |
13 | * GNU General Public License for more details. * |
14 | * * |
15 | * You should have received a copy of the GNU General Public License * |
16 | * along with this program; if not, write to the * |
17 | * Free Software Foundation, Inc., * |
18 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * |
19 | * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */ |
20 | |
21 | #include <stdlib.h> |
22 | #include <stdint.h> //include for uint64_t |
23 | #include <assert.h> |
24 | |
25 | #include "../recomp.h" |
26 | #include "../recomph.h" //include for function prototypes |
27 | #include "../macros.h" |
28 | #include "../r4300.h" |
29 | #include "../ops.h" |
30 | #include "../interupt.h" |
31 | |
32 | #include "../../memory/memory.h" |
33 | |
34 | #include <sys/mman.h> |
35 | |
36 | #ifdef __i386__ |
37 | #include "assem_x86.h" |
38 | #endif |
39 | #ifdef __x86_64__ |
40 | #include "assem_x64.h" |
41 | #endif |
42 | #ifdef __arm__ |
43 | #include "assem_arm.h" |
44 | #endif |
45 | |
46 | #define MAXBLOCK 4096 |
47 | #define MAX_OUTPUT_BLOCK_SIZE 262144 |
48 | #define CLOCK_DIVIDER 2 |
49 | |
50 | struct regstat |
51 | { |
52 | signed char regmap_entry[HOST_REGS]; |
53 | signed char regmap[HOST_REGS]; |
54 | uint64_t was32; |
55 | uint64_t is32; |
56 | uint64_t wasdirty; |
57 | uint64_t dirty; |
58 | uint64_t u; |
59 | uint64_t uu; |
60 | u_int wasconst; |
61 | u_int isconst; |
62 | uint64_t constmap[HOST_REGS]; |
63 | }; |
64 | |
65 | struct ll_entry |
66 | { |
67 | u_int vaddr; |
68 | u_int reg32; |
69 | void *addr; |
70 | struct ll_entry *next; |
71 | }; |
72 | |
73 | u_int start; |
74 | u_int *source; |
75 | u_int pagelimit; |
76 | char insn[MAXBLOCK][10]; |
77 | u_char itype[MAXBLOCK]; |
78 | u_char opcode[MAXBLOCK]; |
79 | u_char opcode2[MAXBLOCK]; |
80 | u_char bt[MAXBLOCK]; |
81 | u_char rs1[MAXBLOCK]; |
82 | u_char rs2[MAXBLOCK]; |
83 | u_char rt1[MAXBLOCK]; |
84 | u_char rt2[MAXBLOCK]; |
85 | u_char us1[MAXBLOCK]; |
86 | u_char us2[MAXBLOCK]; |
87 | u_char dep1[MAXBLOCK]; |
88 | u_char dep2[MAXBLOCK]; |
89 | u_char lt1[MAXBLOCK]; |
90 | int imm[MAXBLOCK]; |
91 | u_int ba[MAXBLOCK]; |
92 | char likely[MAXBLOCK]; |
93 | char is_ds[MAXBLOCK]; |
94 | uint64_t unneeded_reg[MAXBLOCK]; |
95 | uint64_t unneeded_reg_upper[MAXBLOCK]; |
96 | uint64_t branch_unneeded_reg[MAXBLOCK]; |
97 | uint64_t branch_unneeded_reg_upper[MAXBLOCK]; |
98 | uint64_t p32[MAXBLOCK]; |
99 | uint64_t pr32[MAXBLOCK]; |
100 | signed char regmap_pre[MAXBLOCK][HOST_REGS]; |
101 | signed char regmap[MAXBLOCK][HOST_REGS]; |
102 | signed char regmap_entry[MAXBLOCK][HOST_REGS]; |
103 | uint64_t constmap[MAXBLOCK][HOST_REGS]; |
104 | uint64_t known_value[HOST_REGS]; |
105 | u_int known_reg; |
106 | struct regstat regs[MAXBLOCK]; |
107 | struct regstat branch_regs[MAXBLOCK]; |
108 | u_int needed_reg[MAXBLOCK]; |
109 | uint64_t requires_32bit[MAXBLOCK]; |
110 | u_int wont_dirty[MAXBLOCK]; |
111 | u_int will_dirty[MAXBLOCK]; |
112 | int ccadj[MAXBLOCK]; |
113 | int slen; |
114 | u_int instr_addr[MAXBLOCK]; |
115 | u_int link_addr[MAXBLOCK][3]; |
116 | int linkcount; |
117 | u_int stubs[MAXBLOCK*3][8]; |
118 | int stubcount; |
119 | u_int literals[1024][2]; |
120 | int literalcount; |
121 | int is_delayslot; |
122 | int cop1_usable; |
123 | u_char *out; |
124 | struct ll_entry *jump_in[4096]; |
125 | struct ll_entry *jump_out[4096]; |
126 | struct ll_entry *jump_dirty[4096]; |
127 | u_int hash_table[65536][4] __attribute__((aligned(16))); |
128 | char shadow[1048576] __attribute__((aligned(16))); |
129 | void *copy; |
130 | int expirep; |
131 | u_int using_tlb; |
132 | u_int stop_after_jal; |
133 | extern u_char restore_candidate[512]; |
134 | extern int cycle_count; |
135 | |
136 | /* registers that may be allocated */ |
137 | /* 1-31 gpr */ |
138 | #define HIREG 32 // hi |
139 | #define LOREG 33 // lo |
140 | #define FSREG 34 // FPU status (FCSR) |
141 | #define CSREG 35 // Coprocessor status |
142 | #define CCREG 36 // Cycle count |
143 | #define INVCP 37 // Pointer to invalid_code |
144 | #define TEMPREG 38 |
145 | #define FTEMP 38 // FPU temporary register |
146 | #define PTEMP 39 // Prefetch temporary register |
147 | #define TLREG 40 // TLB mapping offset |
148 | #define RHASH 41 // Return address hash |
149 | #define RHTBL 42 // Return address hash table address |
150 | #define RTEMP 43 // JR/JALR address register |
151 | #define MAXREG 43 |
152 | #define AGEN1 44 // Address generation temporary register |
153 | #define AGEN2 45 // Address generation temporary register |
154 | #define MGEN1 46 // Maptable address generation temporary register |
155 | #define MGEN2 47 // Maptable address generation temporary register |
156 | #define BTREG 48 // Branch target temporary register |
157 | |
158 | /* instruction types */ |
159 | #define NOP 0 // No operation |
160 | #define LOAD 1 // Load |
161 | #define STORE 2 // Store |
162 | #define LOADLR 3 // Unaligned load |
163 | #define STORELR 4 // Unaligned store |
164 | #define MOV 5 // Move |
165 | #define ALU 6 // Arithmetic/logic |
166 | #define MULTDIV 7 // Multiply/divide |
167 | #define SHIFT 8 // Shift by register |
168 | #define SHIFTIMM 9// Shift by immediate |
169 | #define IMM16 10 // 16-bit immediate |
170 | #define RJUMP 11 // Unconditional jump to register |
171 | #define UJUMP 12 // Unconditional jump |
172 | #define CJUMP 13 // Conditional branch (BEQ/BNE/BGTZ/BLEZ) |
173 | #define SJUMP 14 // Conditional branch (regimm format) |
174 | #define COP0 15 // Coprocessor 0 |
175 | #define COP1 16 // Coprocessor 1 |
176 | #define C1LS 17 // Coprocessor 1 load/store |
177 | #define FJUMP 18 // Conditional branch (floating point) |
178 | #define FLOAT 19 // Floating point unit |
179 | #define FCONV 20 // Convert integer to float |
180 | #define FCOMP 21 // Floating point compare (sets FSREG) |
181 | #define SYSCALL 22// SYSCALL |
182 | #define OTHER 23 // Other |
183 | #define SPAN 24 // Branch/delay slot spans 2 pages |
184 | #define NI 25 // Not implemented |
185 | |
186 | /* stubs */ |
187 | #define CC_STUB 1 |
188 | #define FP_STUB 2 |
189 | #define LOADB_STUB 3 |
190 | #define LOADH_STUB 4 |
191 | #define LOADW_STUB 5 |
192 | #define LOADD_STUB 6 |
193 | #define LOADBU_STUB 7 |
194 | #define LOADHU_STUB 8 |
195 | #define STOREB_STUB 9 |
196 | #define STOREH_STUB 10 |
197 | #define STOREW_STUB 11 |
198 | #define STORED_STUB 12 |
199 | #define STORELR_STUB 13 |
200 | #define INVCODE_STUB 14 |
201 | |
202 | /* branch codes */ |
203 | #define TAKEN 1 |
204 | #define NOTTAKEN 2 |
205 | #define NULLDS 3 |
206 | |
207 | // asm linkage |
208 | int new_recompile_block(int addr); |
209 | void *get_addr_ht(u_int vaddr); |
210 | void invalidate_block(u_int block); |
211 | void invalidate_addr(u_int addr); |
212 | void remove_hash(int vaddr); |
213 | void jump_vaddr(); |
214 | void dyna_linker(); |
215 | void dyna_linker_ds(); |
216 | void verify_code(); |
217 | void verify_code_vm(); |
218 | void verify_code_ds(); |
219 | void cc_interrupt(); |
220 | void fp_exception(); |
221 | void fp_exception_ds(); |
222 | void jump_syscall(); |
223 | void jump_eret(); |
224 | |
225 | // TLB |
226 | void TLBWI_new(); |
227 | void TLBWR_new(); |
228 | void read_nomem_new(); |
229 | void read_nomemb_new(); |
230 | void read_nomemh_new(); |
231 | void read_nomemd_new(); |
232 | void write_nomem_new(); |
233 | void write_nomemb_new(); |
234 | void write_nomemh_new(); |
235 | void write_nomemd_new(); |
236 | void write_rdram_new(); |
237 | void write_rdramb_new(); |
238 | void write_rdramh_new(); |
239 | void write_rdramd_new(); |
240 | extern u_int memory_map[1048576]; |
241 | |
242 | // Needed by assembler |
243 | void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32); |
244 | void wb_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty); |
245 | void wb_needed_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr); |
246 | void load_all_regs(signed char i_regmap[]); |
247 | void load_needed_regs(signed char i_regmap[],signed char next_regmap[]); |
248 | void load_regs_entry(int t); |
249 | void load_all_consts(signed char regmap[],int is32,u_int dirty,int i); |
250 | |
251 | int tracedebug=0; |
252 | |
253 | //#define DEBUG_CYCLE_COUNT 1 |
254 | |
255 | void nullf() {} |
256 | //#define assem_debug printf |
257 | //#define inv_debug printf |
258 | #define assem_debug nullf |
259 | #define inv_debug nullf |
260 | |
261 | void tlb_hacks() |
262 | { |
263 | // Goldeneye hack |
264 | if (strncmp((char *) ROM_HEADER->nom, "GOLDENEYE",9) == 0) |
265 | { |
266 | u_int addr; |
267 | int n; |
268 | switch (ROM_HEADER->Country_code&0xFF) |
269 | { |
270 | case 0x45: // U |
271 | addr=0x34b30; |
272 | break; |
273 | case 0x4A: // J |
274 | addr=0x34b70; |
275 | break; |
276 | case 0x50: // E |
277 | addr=0x329f0; |
278 | break; |
279 | default: |
280 | // Unknown country code |
281 | addr=0; |
282 | break; |
283 | } |
284 | u_int rom_addr=(u_int)rom; |
285 | #ifdef ROM_COPY |
286 | // Since memory_map is 32-bit, on 64-bit systems the rom needs to be |
287 | // in the lower 4G of memory to use this hack. Copy it if necessary. |
288 | if((void *)rom>(void *)0xffffffff) { |
289 | munmap(ROM_COPY, 67108864); |
290 | if(mmap(ROM_COPY, 12582912, |
291 | PROT_READ | PROT_WRITE, |
292 | MAP_FIXED | MAP_PRIVATE | MAP_ANONYMOUS, |
293 | -1, 0) <= 0) {printf("mmap() failed\n");} |
294 | memcpy(ROM_COPY,rom,12582912); |
295 | rom_addr=(u_int)ROM_COPY; |
296 | } |
297 | #endif |
298 | if(addr) { |
299 | for(n=0x7F000;n<0x80000;n++) { |
300 | memory_map[n]=(((u_int)(rom_addr+addr-0x7F000000))>>2)|0x40000000; |
301 | } |
302 | } |
303 | } |
304 | } |
305 | |
306 | // Get address from virtual address |
307 | // This is called from the recompiled JR/JALR instructions |
308 | void *get_addr(u_int vaddr) |
309 | { |
310 | u_int page=(vaddr^0x80000000)>>12; |
311 | u_int vpage=page; |
312 | if(page>262143&&tlb_LUT_r[vaddr>>12]) page=(tlb_LUT_r[vaddr>>12]^0x80000000)>>12; |
313 | if(page>2048) page=2048+(page&2047); |
314 | if(vpage>262143&&tlb_LUT_r[vaddr>>12]) vpage&=2047; // jump_dirty uses a hash of the virtual address instead |
315 | if(vpage>2048) vpage=2048+(vpage&2047); |
316 | struct ll_entry *head; |
317 | //printf("TRACE: count=%d next=%d (get_addr %x,page %d)\n",Count,next_interupt,vaddr,page); |
318 | head=jump_in[page]; |
319 | while(head!=NULL) { |
320 | if(head->vaddr==vaddr&&head->reg32==0) { |
321 | //printf("TRACE: count=%d next=%d (get_addr match %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr); |
322 | int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF]; |
323 | ht_bin[3]=ht_bin[1]; |
324 | ht_bin[2]=ht_bin[0]; |
325 | ht_bin[1]=(int)head->addr; |
326 | ht_bin[0]=vaddr; |
327 | return head->addr; |
328 | } |
329 | head=head->next; |
330 | } |
331 | head=jump_dirty[vpage]; |
332 | while(head!=NULL) { |
333 | if(head->vaddr==vaddr&&head->reg32==0) { |
334 | //printf("TRACE: count=%d next=%d (get_addr match dirty %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr); |
335 | // Don't restore blocks which are about to expire from the cache |
336 | if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) |
337 | if(verify_dirty(head->addr)) { |
338 | //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]); |
339 | invalid_code[vaddr>>12]=0; |
340 | memory_map[vaddr>>12]|=0x40000000; |
341 | if(vpage<2048) { |
342 | if(tlb_LUT_r[vaddr>>12]) { |
343 | invalid_code[tlb_LUT_r[vaddr>>12]>>12]=0; |
344 | memory_map[tlb_LUT_r[vaddr>>12]>>12]|=0x40000000; |
345 | } |
346 | restore_candidate[vpage>>3]|=1<<(vpage&7); |
347 | } |
348 | else restore_candidate[page>>3]|=1<<(page&7); |
349 | int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF]; |
350 | if(ht_bin[0]==vaddr) { |
351 | ht_bin[1]=(int)head->addr; // Replace existing entry |
352 | } |
353 | else |
354 | { |
355 | ht_bin[3]=ht_bin[1]; |
356 | ht_bin[2]=ht_bin[0]; |
357 | ht_bin[1]=(int)head->addr; |
358 | ht_bin[0]=vaddr; |
359 | } |
360 | return head->addr; |
361 | } |
362 | } |
363 | head=head->next; |
364 | } |
365 | //printf("TRACE: count=%d next=%d (get_addr no-match %x)\n",Count,next_interupt,vaddr); |
366 | int r=new_recompile_block(vaddr); |
367 | if(r==0) return get_addr(vaddr); |
368 | // Execute in unmapped page, generate pagefault execption |
369 | Status|=2; |
370 | Cause=(vaddr<<31)|0x8; |
371 | EPC=(vaddr&1)?vaddr-5:vaddr; |
372 | BadVAddr=(vaddr&~1); |
373 | Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0); |
374 | EntryHi=BadVAddr&0xFFFFE000; |
375 | return get_addr_ht(0x80000000); |
376 | } |
377 | // Look up address in hash table first |
378 | void *get_addr_ht(u_int vaddr) |
379 | { |
380 | //printf("TRACE: count=%d next=%d (get_addr_ht %x)\n",Count,next_interupt,vaddr); |
381 | int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF]; |
382 | if(ht_bin[0]==vaddr) return (void *)ht_bin[1]; |
383 | if(ht_bin[2]==vaddr) return (void *)ht_bin[3]; |
384 | return get_addr(vaddr); |
385 | } |
386 | |
387 | void *get_addr_32(u_int vaddr,u_int flags) |
388 | { |
389 | //printf("TRACE: count=%d next=%d (get_addr_32 %x,flags %x)\n",Count,next_interupt,vaddr,flags); |
390 | int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF]; |
391 | if(ht_bin[0]==vaddr) return (void *)ht_bin[1]; |
392 | if(ht_bin[2]==vaddr) return (void *)ht_bin[3]; |
393 | u_int page=(vaddr^0x80000000)>>12; |
394 | u_int vpage=page; |
395 | if(page>262143&&tlb_LUT_r[vaddr>>12]) page=(tlb_LUT_r[vaddr>>12]^0x80000000)>>12; |
396 | if(page>2048) page=2048+(page&2047); |
397 | if(vpage>262143&&tlb_LUT_r[vaddr>>12]) vpage&=2047; // jump_dirty uses a hash of the virtual address instead |
398 | if(vpage>2048) vpage=2048+(vpage&2047); |
399 | struct ll_entry *head; |
400 | head=jump_in[page]; |
401 | while(head!=NULL) { |
402 | if(head->vaddr==vaddr&&(head->reg32&flags)==0) { |
403 | //printf("TRACE: count=%d next=%d (get_addr_32 match %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr); |
404 | if(head->reg32==0) { |
405 | int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF]; |
406 | if(ht_bin[0]==-1) { |
407 | ht_bin[1]=(int)head->addr; |
408 | ht_bin[0]=vaddr; |
409 | }else if(ht_bin[2]==-1) { |
410 | ht_bin[3]=(int)head->addr; |
411 | ht_bin[2]=vaddr; |
412 | } |
413 | //ht_bin[3]=ht_bin[1]; |
414 | //ht_bin[2]=ht_bin[0]; |
415 | //ht_bin[1]=(int)head->addr; |
416 | //ht_bin[0]=vaddr; |
417 | } |
418 | return head->addr; |
419 | } |
420 | head=head->next; |
421 | } |
422 | head=jump_dirty[vpage]; |
423 | while(head!=NULL) { |
424 | if(head->vaddr==vaddr&&(head->reg32&flags)==0) { |
425 | //printf("TRACE: count=%d next=%d (get_addr_32 match dirty %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr); |
426 | // Don't restore blocks which are about to expire from the cache |
427 | if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) |
428 | if(verify_dirty(head->addr)) { |
429 | //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]); |
430 | invalid_code[vaddr>>12]=0; |
431 | memory_map[vaddr>>12]|=0x40000000; |
432 | if(vpage<2048) { |
433 | if(tlb_LUT_r[vaddr>>12]) { |
434 | invalid_code[tlb_LUT_r[vaddr>>12]>>12]=0; |
435 | memory_map[tlb_LUT_r[vaddr>>12]>>12]|=0x40000000; |
436 | } |
437 | restore_candidate[vpage>>3]|=1<<(vpage&7); |
438 | } |
439 | else restore_candidate[page>>3]|=1<<(page&7); |
440 | if(head->reg32==0) { |
441 | int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF]; |
442 | if(ht_bin[0]==-1) { |
443 | ht_bin[1]=(int)head->addr; |
444 | ht_bin[0]=vaddr; |
445 | }else if(ht_bin[2]==-1) { |
446 | ht_bin[3]=(int)head->addr; |
447 | ht_bin[2]=vaddr; |
448 | } |
449 | //ht_bin[3]=ht_bin[1]; |
450 | //ht_bin[2]=ht_bin[0]; |
451 | //ht_bin[1]=(int)head->addr; |
452 | //ht_bin[0]=vaddr; |
453 | } |
454 | return head->addr; |
455 | } |
456 | } |
457 | head=head->next; |
458 | } |
459 | //printf("TRACE: count=%d next=%d (get_addr_32 no-match %x,flags %x)\n",Count,next_interupt,vaddr,flags); |
460 | int r=new_recompile_block(vaddr); |
461 | if(r==0) return get_addr(vaddr); |
462 | // Execute in unmapped page, generate pagefault execption |
463 | Status|=2; |
464 | Cause=(vaddr<<31)|0x8; |
465 | EPC=(vaddr&1)?vaddr-5:vaddr; |
466 | BadVAddr=(vaddr&~1); |
467 | Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0); |
468 | EntryHi=BadVAddr&0xFFFFE000; |
469 | return get_addr_ht(0x80000000); |
470 | } |
471 | |
472 | void clear_all_regs(signed char regmap[]) |
473 | { |
474 | int hr; |
475 | for (hr=0;hr<HOST_REGS;hr++) regmap[hr]=-1; |
476 | } |
477 | |
478 | signed char get_reg(signed char regmap[],int r) |
479 | { |
480 | int hr; |
481 | for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&®map[hr]==r) return hr; |
482 | return -1; |
483 | } |
484 | |
485 | // Find a register that is available for two consecutive cycles |
486 | signed char get_reg2(signed char regmap1[],signed char regmap2[],int r) |
487 | { |
488 | int hr; |
489 | for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&®map1[hr]==r&®map2[hr]==r) return hr; |
490 | return -1; |
491 | } |
492 | |
493 | int count_free_regs(signed char regmap[]) |
494 | { |
495 | int count=0; |
496 | int hr; |
497 | for(hr=0;hr<HOST_REGS;hr++) |
498 | { |
499 | if(hr!=EXCLUDE_REG) { |
500 | if(regmap[hr]<0) count++; |
501 | } |
502 | } |
503 | return count; |
504 | } |
505 | |
506 | void dirty_reg(struct regstat *cur,signed char reg) |
507 | { |
508 | int hr; |
509 | if(!reg) return; |
510 | for (hr=0;hr<HOST_REGS;hr++) { |
511 | if((cur->regmap[hr]&63)==reg) { |
512 | cur->dirty|=1<<hr; |
513 | } |
514 | } |
515 | } |
516 | |
517 | // If we dirty the lower half of a 64 bit register which is now being |
518 | // sign-extended, we need to dump the upper half. |
519 | // Note: Do this only after completion of the instruction, because |
520 | // some instructions may need to read the full 64-bit value even if |
521 | // overwriting it (eg SLTI, DSRA32). |
522 | static void flush_dirty_uppers(struct regstat *cur) |
523 | { |
524 | int hr,reg; |
525 | for (hr=0;hr<HOST_REGS;hr++) { |
526 | if((cur->dirty>>hr)&1) { |
527 | reg=cur->regmap[hr]; |
528 | if(reg>=64) |
529 | if((cur->is32>>(reg&63))&1) cur->regmap[hr]=-1; |
530 | } |
531 | } |
532 | } |
533 | |
534 | void set_const(struct regstat *cur,signed char reg,uint64_t value) |
535 | { |
536 | int hr; |
537 | if(!reg) return; |
538 | for (hr=0;hr<HOST_REGS;hr++) { |
539 | if(cur->regmap[hr]==reg) { |
540 | cur->isconst|=1<<hr; |
541 | cur->constmap[hr]=value; |
542 | } |
543 | else if((cur->regmap[hr]^64)==reg) { |
544 | cur->isconst|=1<<hr; |
545 | cur->constmap[hr]=value>>32; |
546 | } |
547 | } |
548 | } |
549 | |
550 | void clear_const(struct regstat *cur,signed char reg) |
551 | { |
552 | int hr; |
553 | if(!reg) return; |
554 | for (hr=0;hr<HOST_REGS;hr++) { |
555 | if((cur->regmap[hr]&63)==reg) { |
556 | cur->isconst&=~(1<<hr); |
557 | } |
558 | } |
559 | } |
560 | |
561 | int is_const(struct regstat *cur,signed char reg) |
562 | { |
563 | int hr; |
564 | if(!reg) return 1; |
565 | for (hr=0;hr<HOST_REGS;hr++) { |
566 | if((cur->regmap[hr]&63)==reg) { |
567 | return (cur->isconst>>hr)&1; |
568 | } |
569 | } |
570 | return 0; |
571 | } |
572 | uint64_t get_const(struct regstat *cur,signed char reg) |
573 | { |
574 | int hr; |
575 | if(!reg) return 0; |
576 | for (hr=0;hr<HOST_REGS;hr++) { |
577 | if(cur->regmap[hr]==reg) { |
578 | return cur->constmap[hr]; |
579 | } |
580 | } |
581 | printf("Unknown constant in r%d\n",reg); |
582 | exit(1); |
583 | } |
584 | |
585 | // Least soon needed registers |
586 | // Look at the next ten instructions and see which registers |
587 | // will be used. Try not to reallocate these. |
588 | void lsn(u_char hsn[], int i, int *preferred_reg) |
589 | { |
590 | int j; |
591 | int b=-1; |
592 | for(j=0;j<9;j++) |
593 | { |
594 | if(i+j>=slen) { |
595 | j=slen-i-1; |
596 | break; |
597 | } |
598 | if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000) |
599 | { |
600 | // Don't go past an unconditonal jump |
601 | j++; |
602 | break; |
603 | } |
604 | } |
605 | for(;j>=0;j--) |
606 | { |
607 | if(rs1[i+j]) hsn[rs1[i+j]]=j; |
608 | if(rs2[i+j]) hsn[rs2[i+j]]=j; |
609 | if(rt1[i+j]) hsn[rt1[i+j]]=j; |
610 | if(rt2[i+j]) hsn[rt2[i+j]]=j; |
611 | if(itype[i+j]==STORE || itype[i+j]==STORELR) { |
612 | // Stores can allocate zero |
613 | hsn[rs1[i+j]]=j; |
614 | hsn[rs2[i+j]]=j; |
615 | } |
616 | // On some architectures stores need invc_ptr |
617 | #if defined(HOST_IMM8) |
618 | if(itype[i+j]==STORE || itype[i+j]==STORELR || (opcode[i+j]&0x3b)==0x39) { |
619 | hsn[INVCP]=j; |
620 | } |
621 | #endif |
622 | if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP)) |
623 | { |
624 | hsn[CCREG]=j; |
625 | b=j; |
626 | } |
627 | } |
628 | if(b>=0) |
629 | { |
630 | if(ba[i+b]>=start && ba[i+b]<(start+slen*4)) |
631 | { |
632 | // Follow first branch |
633 | int t=(ba[i+b]-start)>>2; |
634 | j=7-b;if(t+j>=slen) j=slen-t-1; |
635 | for(;j>=0;j--) |
636 | { |
637 | if(rs1[t+j]) if(hsn[rs1[t+j]]>j+b+2) hsn[rs1[t+j]]=j+b+2; |
638 | if(rs2[t+j]) if(hsn[rs2[t+j]]>j+b+2) hsn[rs2[t+j]]=j+b+2; |
639 | //if(rt1[t+j]) if(hsn[rt1[t+j]]>j+b+2) hsn[rt1[t+j]]=j+b+2; |
640 | //if(rt2[t+j]) if(hsn[rt2[t+j]]>j+b+2) hsn[rt2[t+j]]=j+b+2; |
641 | } |
642 | } |
643 | // TODO: preferred register based on backward branch |
644 | } |
645 | // Delay slot should preferably not overwrite branch conditions or cycle count |
646 | if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)) { |
647 | if(rs1[i-1]) if(hsn[rs1[i-1]]>1) hsn[rs1[i-1]]=1; |
648 | if(rs2[i-1]) if(hsn[rs2[i-1]]>1) hsn[rs2[i-1]]=1; |
649 | hsn[CCREG]=1; |
650 | // ...or hash tables |
651 | hsn[RHASH]=1; |
652 | hsn[RHTBL]=1; |
653 | } |
654 | // Coprocessor load/store needs FTEMP, even if not declared |
655 | if(itype[i]==C1LS) { |
656 | hsn[FTEMP]=0; |
657 | } |
658 | // Load L/R also uses FTEMP as a temporary register |
659 | if(itype[i]==LOADLR) { |
660 | hsn[FTEMP]=0; |
661 | } |
662 | // Also 64-bit SDL/SDR |
663 | if(opcode[i]==0x2c||opcode[i]==0x2d) { |
664 | hsn[FTEMP]=0; |
665 | } |
666 | // Don't remove the TLB registers either |
667 | if(itype[i]==LOAD || itype[i]==LOADLR || itype[i]==STORE || itype[i]==STORELR || itype[i]==C1LS ) { |
668 | hsn[TLREG]=0; |
669 | } |
670 | // Don't remove the miniht registers |
671 | if(itype[i]==UJUMP||itype[i]==RJUMP) |
672 | { |
673 | hsn[RHASH]=0; |
674 | hsn[RHTBL]=0; |
675 | } |
676 | } |
677 | |
678 | // We only want to allocate registers if we're going to use them again soon |
679 | int needed_again(int r, int i) |
680 | { |
681 | int j; |
682 | int b=-1; |
683 | int rn=10; |
684 | int hr; |
685 | u_char hsn[MAXREG+1]; |
686 | int preferred_reg; |
687 | |
688 | memset(hsn,10,sizeof(hsn)); |
689 | lsn(hsn,i,&preferred_reg); |
690 | |
691 | if(i>0&&(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)) |
692 | { |
693 | if(ba[i-1]<start || ba[i-1]>start+slen*4-4) |
694 | return 0; // Don't need any registers if exiting the block |
695 | } |
696 | for(j=0;j<9;j++) |
697 | { |
698 | if(i+j>=slen) { |
699 | j=slen-i-1; |
700 | break; |
701 | } |
702 | if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000) |
703 | { |
704 | // Don't go past an unconditonal jump |
705 | j++; |
706 | break; |
707 | } |
708 | if(itype[i+j]==SYSCALL||((source[i+j]&0xfc00003f)==0x0d)) |
709 | { |
710 | break; |
711 | } |
712 | } |
713 | for(;j>=1;j--) |
714 | { |
715 | if(rs1[i+j]==r) rn=j; |
716 | if(rs2[i+j]==r) rn=j; |
717 | if((unneeded_reg[i+j]>>r)&1) rn=10; |
718 | if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP)) |
719 | { |
720 | b=j; |
721 | } |
722 | } |
723 | /* |
724 | if(b>=0) |
725 | { |
726 | if(ba[i+b]>=start && ba[i+b]<(start+slen*4)) |
727 | { |
728 | // Follow first branch |
729 | int o=rn; |
730 | int t=(ba[i+b]-start)>>2; |
731 | j=7-b;if(t+j>=slen) j=slen-t-1; |
732 | for(;j>=0;j--) |
733 | { |
734 | if(!((unneeded_reg[t+j]>>r)&1)) { |
735 | if(rs1[t+j]==r) if(rn>j+b+2) rn=j+b+2; |
736 | if(rs2[t+j]==r) if(rn>j+b+2) rn=j+b+2; |
737 | } |
738 | else rn=o; |
739 | } |
740 | } |
741 | }*/ |
742 | for(hr=0;hr<HOST_REGS;hr++) { |
743 | if(hr!=EXCLUDE_REG) { |
744 | if(rn<hsn[hr]) return 1; |
745 | } |
746 | } |
747 | return 0; |
748 | } |
749 | |
750 | // Try to match register allocations at the end of a loop with those |
751 | // at the beginning |
752 | int loop_reg(int i, int r, int hr) |
753 | { |
754 | int j,k; |
755 | for(j=0;j<9;j++) |
756 | { |
757 | if(i+j>=slen) { |
758 | j=slen-i-1; |
759 | break; |
760 | } |
761 | if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000) |
762 | { |
763 | // Don't go past an unconditonal jump |
764 | j++; |
765 | break; |
766 | } |
767 | } |
768 | k=0; |
769 | if(i>0){ |
770 | if(itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP) |
771 | k--; |
772 | } |
773 | for(;k<j;k++) |
774 | { |
775 | if(r<64&&((unneeded_reg[i+k]>>r)&1)) return hr; |
776 | if(r>64&&((unneeded_reg_upper[i+k]>>r)&1)) return hr; |
777 | if(i+k>=0&&(itype[i+k]==UJUMP||itype[i+k]==CJUMP||itype[i+k]==SJUMP||itype[i+k]==FJUMP)) |
778 | { |
779 | if(ba[i+k]>=start && ba[i+k]<(start+i*4)) |
780 | { |
781 | int t=(ba[i+k]-start)>>2; |
782 | int reg=get_reg(regs[t].regmap_entry,r); |
783 | if(reg>=0) return reg; |
784 | //reg=get_reg(regs[t+1].regmap_entry,r); |
785 | //if(reg>=0) return reg; |
786 | } |
787 | } |
788 | } |
789 | return hr; |
790 | } |
791 | |
792 | |
793 | // Allocate every register, preserving source/target regs |
794 | void alloc_all(struct regstat *cur,int i) |
795 | { |
796 | int hr; |
797 | |
798 | for(hr=0;hr<HOST_REGS;hr++) { |
799 | if(hr!=EXCLUDE_REG) { |
800 | if(((cur->regmap[hr]&63)!=rs1[i])&&((cur->regmap[hr]&63)!=rs2[i])&& |
801 | ((cur->regmap[hr]&63)!=rt1[i])&&((cur->regmap[hr]&63)!=rt2[i])) |
802 | { |
803 | cur->regmap[hr]=-1; |
804 | cur->dirty&=~(1<<hr); |
805 | } |
806 | // Don't need zeros |
807 | if((cur->regmap[hr]&63)==0) |
808 | { |
809 | cur->regmap[hr]=-1; |
810 | cur->dirty&=~(1<<hr); |
811 | } |
812 | } |
813 | } |
814 | } |
815 | |
816 | |
817 | void div64(int64_t dividend,int64_t divisor) |
818 | { |
819 | lo=dividend/divisor; |
820 | hi=dividend%divisor; |
821 | //printf("TRACE: ddiv %8x%8x %8x%8x\n" ,(int)reg[HIREG],(int)(reg[HIREG]>>32) |
822 | // ,(int)reg[LOREG],(int)(reg[LOREG]>>32)); |
823 | } |
824 | void divu64(uint64_t dividend,uint64_t divisor) |
825 | { |
826 | lo=dividend/divisor; |
827 | hi=dividend%divisor; |
828 | //printf("TRACE: ddivu %8x%8x %8x%8x\n",(int)reg[HIREG],(int)(reg[HIREG]>>32) |
829 | // ,(int)reg[LOREG],(int)(reg[LOREG]>>32)); |
830 | } |
831 | |
832 | void mult64(uint64_t m1,uint64_t m2) |
833 | { |
834 | unsigned long long int op1, op2, op3, op4; |
835 | unsigned long long int result1, result2, result3, result4; |
836 | unsigned long long int temp1, temp2, temp3, temp4; |
837 | int sign = 0; |
838 | |
839 | if (m1 < 0) |
840 | { |
841 | op2 = -m1; |
842 | sign = 1 - sign; |
843 | } |
844 | else op2 = m1; |
845 | if (m2 < 0) |
846 | { |
847 | op4 = -m2; |
848 | sign = 1 - sign; |
849 | } |
850 | else op4 = m2; |
851 | |
852 | op1 = op2 & 0xFFFFFFFF; |
853 | op2 = (op2 >> 32) & 0xFFFFFFFF; |
854 | op3 = op4 & 0xFFFFFFFF; |
855 | op4 = (op4 >> 32) & 0xFFFFFFFF; |
856 | |
857 | temp1 = op1 * op3; |
858 | temp2 = (temp1 >> 32) + op1 * op4; |
859 | temp3 = op2 * op3; |
860 | temp4 = (temp3 >> 32) + op2 * op4; |
861 | |
862 | result1 = temp1 & 0xFFFFFFFF; |
863 | result2 = temp2 + (temp3 & 0xFFFFFFFF); |
864 | result3 = (result2 >> 32) + temp4; |
865 | result4 = (result3 >> 32); |
866 | |
867 | lo = result1 | (result2 << 32); |
868 | hi = (result3 & 0xFFFFFFFF) | (result4 << 32); |
869 | if (sign) |
870 | { |
871 | hi = ~hi; |
872 | if (!lo) hi++; |
873 | else lo = ~lo + 1; |
874 | } |
875 | } |
876 | |
877 | void multu64(uint64_t m1,uint64_t m2) |
878 | { |
879 | unsigned long long int op1, op2, op3, op4; |
880 | unsigned long long int result1, result2, result3, result4; |
881 | unsigned long long int temp1, temp2, temp3, temp4; |
882 | |
883 | op1 = m1 & 0xFFFFFFFF; |
884 | op2 = (m1 >> 32) & 0xFFFFFFFF; |
885 | op3 = m2 & 0xFFFFFFFF; |
886 | op4 = (m2 >> 32) & 0xFFFFFFFF; |
887 | |
888 | temp1 = op1 * op3; |
889 | temp2 = (temp1 >> 32) + op1 * op4; |
890 | temp3 = op2 * op3; |
891 | temp4 = (temp3 >> 32) + op2 * op4; |
892 | |
893 | result1 = temp1 & 0xFFFFFFFF; |
894 | result2 = temp2 + (temp3 & 0xFFFFFFFF); |
895 | result3 = (result2 >> 32) + temp4; |
896 | result4 = (result3 >> 32); |
897 | |
898 | lo = result1 | (result2 << 32); |
899 | hi = (result3 & 0xFFFFFFFF) | (result4 << 32); |
900 | |
901 | //printf("TRACE: dmultu %8x%8x %8x%8x\n",(int)reg[HIREG],(int)(reg[HIREG]>>32) |
902 | // ,(int)reg[LOREG],(int)(reg[LOREG]>>32)); |
903 | } |
904 | |
905 | uint64_t ldl_merge(uint64_t original,uint64_t loaded,u_int bits) |
906 | { |
907 | if(bits) { |
908 | original<<=64-bits; |
909 | original>>=64-bits; |
910 | loaded<<=bits; |
911 | original|=loaded; |
912 | } |
913 | else original=loaded; |
914 | return original; |
915 | } |
916 | uint64_t ldr_merge(uint64_t original,uint64_t loaded,u_int bits) |
917 | { |
918 | if(bits^56) { |
919 | original>>=64-(bits^56); |
920 | original<<=64-(bits^56); |
921 | loaded>>=bits^56; |
922 | original|=loaded; |
923 | } |
924 | else original=loaded; |
925 | return original; |
926 | } |
927 | |
928 | #ifdef __i386__ |
929 | #include "assem_x86.c" |
930 | #endif |
931 | #ifdef __x86_64__ |
932 | #include "assem_x64.c" |
933 | #endif |
934 | #ifdef __arm__ |
935 | #include "assem_arm.c" |
936 | #endif |
937 | |
938 | // Add virtual address mapping to linked list |
939 | void ll_add(struct ll_entry **head,int vaddr,void *addr) |
940 | { |
941 | struct ll_entry *new_entry; |
942 | new_entry=malloc(sizeof(struct ll_entry)); |
943 | assert(new_entry!=NULL); |
944 | new_entry->vaddr=vaddr; |
945 | new_entry->reg32=0; |
946 | new_entry->addr=addr; |
947 | new_entry->next=*head; |
948 | *head=new_entry; |
949 | } |
950 | |
951 | // Add virtual address mapping for 32-bit compiled block |
952 | void ll_add_32(struct ll_entry **head,int vaddr,u_int reg32,void *addr) |
953 | { |
954 | struct ll_entry *new_entry; |
955 | new_entry=malloc(sizeof(struct ll_entry)); |
956 | assert(new_entry!=NULL); |
957 | new_entry->vaddr=vaddr; |
958 | new_entry->reg32=reg32; |
959 | new_entry->addr=addr; |
960 | new_entry->next=*head; |
961 | *head=new_entry; |
962 | } |
963 | |
964 | // Check if an address is already compiled |
965 | // but don't return addresses which are about to expire from the cache |
966 | void *check_addr(u_int vaddr) |
967 | { |
968 | u_int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF]; |
969 | if(ht_bin[0]==vaddr) { |
970 | if(((ht_bin[1]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) |
971 | if(isclean(ht_bin[1])) return (void *)ht_bin[1]; |
972 | } |
973 | if(ht_bin[2]==vaddr) { |
974 | if(((ht_bin[3]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) |
975 | if(isclean(ht_bin[3])) return (void *)ht_bin[3]; |
976 | } |
977 | u_int page=(vaddr^0x80000000)>>12; |
978 | if(page>262143&&tlb_LUT_r[vaddr>>12]) page=(tlb_LUT_r[vaddr>>12]^0x80000000)>>12; |
979 | if(page>2048) page=2048+(page&2047); |
980 | struct ll_entry *head; |
981 | head=jump_in[page]; |
982 | while(head!=NULL) { |
983 | if(head->vaddr==vaddr&&head->reg32==0) { |
984 | if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) { |
985 | // Update existing entry with current address |
986 | if(ht_bin[0]==vaddr) { |
987 | ht_bin[1]=(int)head->addr; |
988 | return head->addr; |
989 | } |
990 | if(ht_bin[2]==vaddr) { |
991 | ht_bin[3]=(int)head->addr; |
992 | return head->addr; |
993 | } |
994 | // Insert into hash table with low priority. |
995 | // Don't evict existing entries, as they are probably |
996 | // addresses that are being accessed frequently. |
997 | if(ht_bin[0]==-1) { |
998 | ht_bin[1]=(int)head->addr; |
999 | ht_bin[0]=vaddr; |
1000 | }else if(ht_bin[2]==-1) { |
1001 | ht_bin[3]=(int)head->addr; |
1002 | ht_bin[2]=vaddr; |
1003 | } |
1004 | return head->addr; |
1005 | } |
1006 | } |
1007 | head=head->next; |
1008 | } |
1009 | return 0; |
1010 | } |
1011 | |
1012 | void remove_hash(int vaddr) |
1013 | { |
1014 | //printf("remove hash: %x\n",vaddr); |
1015 | int *ht_bin=hash_table[(((vaddr)>>16)^vaddr)&0xFFFF]; |
1016 | if(ht_bin[2]==vaddr) { |
1017 | ht_bin[2]=ht_bin[3]=-1; |
1018 | } |
1019 | if(ht_bin[0]==vaddr) { |
1020 | ht_bin[0]=ht_bin[2]; |
1021 | ht_bin[1]=ht_bin[3]; |
1022 | ht_bin[2]=ht_bin[3]=-1; |
1023 | } |
1024 | } |
1025 | |
1026 | void ll_remove_matching_addrs(struct ll_entry **head,int addr,int shift) |
1027 | { |
1028 | struct ll_entry *next; |
1029 | while(*head) { |
1030 | if(((u_int)((*head)->addr)>>shift)==(addr>>shift) || |
1031 | ((u_int)((*head)->addr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift)) |
1032 | { |
1033 | inv_debug("EXP: Remove pointer to %x (%x)\n",(int)(*head)->addr,(*head)->vaddr); |
1034 | remove_hash((*head)->vaddr); |
1035 | next=(*head)->next; |
1036 | free(*head); |
1037 | *head=next; |
1038 | } |
1039 | else |
1040 | { |
1041 | head=&((*head)->next); |
1042 | } |
1043 | } |
1044 | } |
1045 | |
1046 | // Remove all entries from linked list |
1047 | void ll_clear(struct ll_entry **head) |
1048 | { |
1049 | struct ll_entry *cur; |
1050 | struct ll_entry *next; |
1051 | if(cur=*head) { |
1052 | *head=0; |
1053 | while(cur) { |
1054 | next=cur->next; |
1055 | free(cur); |
1056 | cur=next; |
1057 | } |
1058 | } |
1059 | } |
1060 | |
1061 | // Dereference the pointers and remove if it matches |
1062 | void ll_kill_pointers(struct ll_entry *head,int addr,int shift) |
1063 | { |
1064 | while(head) { |
1065 | int ptr=get_pointer(head->addr); |
1066 | inv_debug("EXP: Lookup pointer to %x at %x (%x)\n",(int)ptr,(int)head->addr,head->vaddr); |
1067 | if(((ptr>>shift)==(addr>>shift)) || |
1068 | (((ptr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift))) |
1069 | { |
1070 | inv_debug("EXP: Kill pointer at %x (%x)\n",(int)head->addr,head->vaddr); |
1071 | kill_pointer(head->addr); |
1072 | } |
1073 | head=head->next; |
1074 | } |
1075 | } |
1076 | |
1077 | // This is called when we write to a compiled block (see do_invstub) |
1078 | int invalidate_page(u_int page) |
1079 | { |
1080 | int modified=0; |
1081 | struct ll_entry *head; |
1082 | struct ll_entry *next; |
1083 | head=jump_in[page]; |
1084 | jump_in[page]=0; |
1085 | while(head!=NULL) { |
1086 | inv_debug("INVALIDATE: %x\n",head->vaddr); |
1087 | remove_hash(head->vaddr); |
1088 | next=head->next; |
1089 | free(head); |
1090 | head=next; |
1091 | } |
1092 | head=jump_out[page]; |
1093 | jump_out[page]=0; |
1094 | while(head!=NULL) { |
1095 | inv_debug("INVALIDATE: kill pointer to %x (%x)\n",head->vaddr,(int)head->addr); |
1096 | kill_pointer(head->addr); |
1097 | modified=1; |
1098 | next=head->next; |
1099 | free(head); |
1100 | head=next; |
1101 | } |
1102 | return modified; |
1103 | } |
1104 | void invalidate_block(u_int block) |
1105 | { |
1106 | int modified; |
1107 | u_int page,vpage; |
1108 | page=vpage=block^0x80000; |
1109 | if(page>262143&&tlb_LUT_r[block]) page=(tlb_LUT_r[block]^0x80000000)>>12; |
1110 | if(page>2048) page=2048+(page&2047); |
1111 | if(vpage>262143&&tlb_LUT_r[block]) vpage&=2047; // jump_dirty uses a hash of the virtual address instead |
1112 | if(vpage>2048) vpage=2048+(vpage&2047); |
1113 | inv_debug("INVALIDATE: %x (%d)\n",block<<12,page); |
1114 | //inv_debug("invalid_code[block]=%d\n",invalid_code[block]); |
1115 | u_int first,last; |
1116 | first=last=page; |
1117 | struct ll_entry *head; |
1118 | head=jump_dirty[vpage]; |
1119 | //printf("page=%d vpage=%d\n",page,vpage); |
1120 | while(head!=NULL) { |
1121 | u_int start,end; |
1122 | if(vpage>2047||(head->vaddr>>12)==block) { // Ignore vaddr hash collision |
1123 | get_bounds((int)head->addr,&start,&end); |
1124 | //printf("start: %x end: %x\n",start,end); |
1125 | if(page<2048&&start>=0x80000000&&end<0x80800000) { |
1126 | if(((start-(u_int)rdram)>>12)<=page&&((end-1-(u_int)rdram)>>12)>=page) { |
1127 | if((((start-(u_int)rdram)>>12)&2047)<first) first=((start-(u_int)rdram)>>12)&2047; |
1128 | if((((end-1-(u_int)rdram)>>12)&2047)>last) last=((end-1-(u_int)rdram)>>12)&2047; |
1129 | } |
1130 | } |
1131 | if(page<2048&&(signed int)start>=(signed int)0xC0000000&&(signed int)end>=(signed int)0xC0000000) { |
1132 | if(((start+memory_map[start>>12]-(u_int)rdram)>>12)<=page&&((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)>=page) { |
1133 | if((((start+memory_map[start>>12]-(u_int)rdram)>>12)&2047)<first) first=((start+memory_map[start>>12]-(u_int)rdram)>>12)&2047; |
1134 | if((((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)&2047)>last) last=((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)&2047; |
1135 | } |
1136 | } |
1137 | } |
1138 | head=head->next; |
1139 | } |
1140 | //printf("first=%d last=%d\n",first,last); |
1141 | modified=invalidate_page(page); |
1142 | assert(first+5>page); // NB: this assumes MAXBLOCK<=4096 (4 pages) |
1143 | assert(last<page+5); |
1144 | // Invalidate the adjacent pages if a block crosses a 4K boundary |
1145 | while(first<page) { |
1146 | invalidate_page(first); |
1147 | first++; |
1148 | } |
1149 | for(first=page+1;first<last;first++) { |
1150 | invalidate_page(first); |
1151 | } |
1152 | |
1153 | // Don't trap writes |
1154 | invalid_code[block]=1; |
1155 | // If there is a valid TLB entry for this page, remove write protect |
1156 | if(tlb_LUT_w[block]) { |
1157 | assert(tlb_LUT_r[block]==tlb_LUT_w[block]); |
1158 | // CHECK: Is this right? |
1159 | memory_map[block]=((tlb_LUT_w[block]&0xFFFFF000)-(block<<12)+(unsigned int)rdram-0x80000000)>>2; |
1160 | u_int real_block=tlb_LUT_w[block]>>12; |
1161 | invalid_code[real_block]=1; |
1162 | if(real_block>=0x80000&&real_block<0x80800) memory_map[real_block]=((u_int)rdram-0x80000000)>>2; |
1163 | } |
1164 | else if(block>=0x80000&&block<0x80800) memory_map[block]=((u_int)rdram-0x80000000)>>2; |
1165 | #ifdef __arm__ |
1166 | if(modified) |
1167 | __clear_cache((void *)BASE_ADDR,(void *)BASE_ADDR+(1<<TARGET_SIZE_2)); |
1168 | #endif |
1169 | #ifdef USE_MINI_HT |
1170 | memset(mini_ht,-1,sizeof(mini_ht)); |
1171 | #endif |
1172 | } |
1173 | void invalidate_addr(u_int addr) |
1174 | { |
1175 | invalidate_block(addr>>12); |
1176 | } |
1177 | void invalidate_all_pages() |
1178 | { |
1179 | u_int page,n; |
1180 | for(page=0;page<4096;page++) |
1181 | invalidate_page(page); |
1182 | for(page=0;page<1048576;page++) |
1183 | if(!invalid_code[page]) { |
1184 | restore_candidate[(page&2047)>>3]|=1<<(page&7); |
1185 | restore_candidate[((page&2047)>>3)+256]|=1<<(page&7); |
1186 | } |
1187 | #ifdef __arm__ |
1188 | __clear_cache((void *)BASE_ADDR,(void *)BASE_ADDR+(1<<TARGET_SIZE_2)); |
1189 | #endif |
1190 | #ifdef USE_MINI_HT |
1191 | memset(mini_ht,-1,sizeof(mini_ht)); |
1192 | #endif |
1193 | // TLB |
1194 | for(page=0;page<0x100000;page++) { |
1195 | if(tlb_LUT_r[page]) { |
1196 | memory_map[page]=((tlb_LUT_r[page]&0xFFFFF000)-(page<<12)+(unsigned int)rdram-0x80000000)>>2; |
1197 | if(!tlb_LUT_w[page]||!invalid_code[page]) |
1198 | memory_map[page]|=0x40000000; // Write protect |
1199 | } |
1200 | else memory_map[page]=-1; |
1201 | if(page==0x80000) page=0xC0000; |
1202 | } |
1203 | tlb_hacks(); |
1204 | } |
1205 | |
1206 | // Add an entry to jump_out after making a link |
1207 | void add_link(u_int vaddr,void *src) |
1208 | { |
1209 | u_int page=(vaddr^0x80000000)>>12; |
1210 | if(page>262143&&tlb_LUT_r[vaddr>>12]) page=(tlb_LUT_r[vaddr>>12]^0x80000000)>>12; |
1211 | if(page>4095) page=2048+(page&2047); |
1212 | inv_debug("add_link: %x -> %x (%d)\n",(int)src,vaddr,page); |
1213 | ll_add(jump_out+page,vaddr,src); |
1214 | //int ptr=get_pointer(src); |
1215 | //inv_debug("add_link: Pointer is to %x\n",(int)ptr); |
1216 | } |
1217 | |
1218 | // If a code block was found to be unmodified (bit was set in |
1219 | // restore_candidate) and it remains unmodified (bit is clear |
1220 | // in invalid_code) then move the entries for that 4K page from |
1221 | // the dirty list to the clean list. |
1222 | void clean_blocks(u_int page) |
1223 | { |
1224 | struct ll_entry *head; |
1225 | inv_debug("INV: clean_blocks page=%d\n",page); |
1226 | head=jump_dirty[page]; |
1227 | while(head!=NULL) { |
1228 | if(!invalid_code[head->vaddr>>12]) { |
1229 | // Don't restore blocks which are about to expire from the cache |
1230 | if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) { |
1231 | u_int start,end; |
1232 | if(verify_dirty((int)head->addr)) { |
1233 | //printf("Possibly Restore %x (%x)\n",head->vaddr, (int)head->addr); |
1234 | u_int i; |
1235 | u_int inv=0; |
1236 | get_bounds((int)head->addr,&start,&end); |
1237 | if(start-(u_int)rdram<0x800000) { |
1238 | for(i=(start-(u_int)rdram+0x80000000)>>12;i<=(end-1-(u_int)rdram+0x80000000)>>12;i++) { |
1239 | inv|=invalid_code[i]; |
1240 | } |
1241 | } |
1242 | if((signed int)head->vaddr>=(signed int)0xC0000000) { |
1243 | u_int addr = (head->vaddr+(memory_map[head->vaddr>>12]<<2)); |
1244 | //printf("addr=%x start=%x end=%x\n",addr,start,end); |
1245 | if(addr<start||addr>=end) inv=1; |
1246 | } |
1247 | else if((signed int)head->vaddr>=(signed int)0x80800000) { |
1248 | inv=1; |
1249 | } |
1250 | if(!inv) { |
1251 | void * clean_addr=(void *)get_clean_addr((int)head->addr); |
1252 | if((((u_int)clean_addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) { |
1253 | u_int ppage=page; |
1254 | if(page<2048&&tlb_LUT_r[head->vaddr>>12]) ppage=(tlb_LUT_r[head->vaddr>>12]^0x80000000)>>12; |
1255 | inv_debug("INV: Restored %x (%x/%x)\n",head->vaddr, (int)head->addr, (int)clean_addr); |
1256 | //printf("page=%x, addr=%x\n",page,head->vaddr); |
1257 | //assert(head->vaddr>>12==(page|0x80000)); |
1258 | ll_add_32(jump_in+ppage,head->vaddr,head->reg32,clean_addr); |
1259 | int *ht_bin=hash_table[((head->vaddr>>16)^head->vaddr)&0xFFFF]; |
1260 | if(!head->reg32) { |
1261 | if(ht_bin[0]==head->vaddr) { |
1262 | ht_bin[1]=(int)clean_addr; // Replace existing entry |
1263 | } |
1264 | if(ht_bin[2]==head->vaddr) { |
1265 | ht_bin[3]=(int)clean_addr; // Replace existing entry |
1266 | } |
1267 | } |
1268 | } |
1269 | } |
1270 | } |
1271 | } |
1272 | } |
1273 | head=head->next; |
1274 | } |
1275 | } |
1276 | |
1277 | |
1278 | void mov_alloc(struct regstat *current,int i) |
1279 | { |
1280 | // Note: Don't need to actually alloc the source registers |
1281 | if((~current->is32>>rs1[i])&1) { |
1282 | //alloc_reg64(current,i,rs1[i]); |
1283 | alloc_reg64(current,i,rt1[i]); |
1284 | current->is32&=~(1LL<<rt1[i]); |
1285 | } else { |
1286 | //alloc_reg(current,i,rs1[i]); |
1287 | alloc_reg(current,i,rt1[i]); |
1288 | current->is32|=(1LL<<rt1[i]); |
1289 | } |
1290 | clear_const(current,rs1[i]); |
1291 | clear_const(current,rt1[i]); |
1292 | dirty_reg(current,rt1[i]); |
1293 | } |
1294 | |
1295 | void shiftimm_alloc(struct regstat *current,int i) |
1296 | { |
1297 | clear_const(current,rs1[i]); |
1298 | clear_const(current,rt1[i]); |
1299 | if(opcode2[i]<=0x3) // SLL/SRL/SRA |
1300 | { |
1301 | if(rt1[i]) { |
1302 | if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]); |
1303 | else lt1[i]=rs1[i]; |
1304 | alloc_reg(current,i,rt1[i]); |
1305 | current->is32|=1LL<<rt1[i]; |
1306 | dirty_reg(current,rt1[i]); |
1307 | } |
1308 | } |
1309 | if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA |
1310 | { |
1311 | if(rt1[i]) { |
1312 | if(rs1[i]) alloc_reg64(current,i,rs1[i]); |
1313 | alloc_reg64(current,i,rt1[i]); |
1314 | current->is32&=~(1LL<<rt1[i]); |
1315 | dirty_reg(current,rt1[i]); |
1316 | } |
1317 | } |
1318 | if(opcode2[i]==0x3c) // DSLL32 |
1319 | { |
1320 | if(rt1[i]) { |
1321 | if(rs1[i]) alloc_reg(current,i,rs1[i]); |
1322 | alloc_reg64(current,i,rt1[i]); |
1323 | current->is32&=~(1LL<<rt1[i]); |
1324 | dirty_reg(current,rt1[i]); |
1325 | } |
1326 | } |
1327 | if(opcode2[i]==0x3e) // DSRL32 |
1328 | { |
1329 | if(rt1[i]) { |
1330 | alloc_reg64(current,i,rs1[i]); |
1331 | if(imm[i]==32) { |
1332 | alloc_reg64(current,i,rt1[i]); |
1333 | current->is32&=~(1LL<<rt1[i]); |
1334 | } else { |
1335 | alloc_reg(current,i,rt1[i]); |
1336 | current->is32|=1LL<<rt1[i]; |
1337 | } |
1338 | dirty_reg(current,rt1[i]); |
1339 | } |
1340 | } |
1341 | if(opcode2[i]==0x3f) // DSRA32 |
1342 | { |
1343 | if(rt1[i]) { |
1344 | alloc_reg64(current,i,rs1[i]); |
1345 | alloc_reg(current,i,rt1[i]); |
1346 | current->is32|=1LL<<rt1[i]; |
1347 | dirty_reg(current,rt1[i]); |
1348 | } |
1349 | } |
1350 | } |
1351 | |
1352 | void shift_alloc(struct regstat *current,int i) |
1353 | { |
1354 | if(rt1[i]) { |
1355 | if(opcode2[i]<=0x07) // SLLV/SRLV/SRAV |
1356 | { |
1357 | if(rs1[i]) alloc_reg(current,i,rs1[i]); |
1358 | if(rs2[i]) alloc_reg(current,i,rs2[i]); |
1359 | alloc_reg(current,i,rt1[i]); |
1360 | if(rt1[i]==rs2[i]) alloc_reg_temp(current,i,-1); |
1361 | current->is32|=1LL<<rt1[i]; |
1362 | } else { // DSLLV/DSRLV/DSRAV |
1363 | if(rs1[i]) alloc_reg64(current,i,rs1[i]); |
1364 | if(rs2[i]) alloc_reg(current,i,rs2[i]); |
1365 | alloc_reg64(current,i,rt1[i]); |
1366 | current->is32&=~(1LL<<rt1[i]); |
1367 | if(opcode2[i]==0x16||opcode2[i]==0x17) // DSRLV and DSRAV need a temporary register |
1368 | alloc_reg_temp(current,i,-1); |
1369 | } |
1370 | clear_const(current,rs1[i]); |
1371 | clear_const(current,rs2[i]); |
1372 | clear_const(current,rt1[i]); |
1373 | dirty_reg(current,rt1[i]); |
1374 | } |
1375 | } |
1376 | |
1377 | void alu_alloc(struct regstat *current,int i) |
1378 | { |
1379 | if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU |
1380 | if(rt1[i]) { |
1381 | if(rs1[i]&&rs2[i]) { |
1382 | alloc_reg(current,i,rs1[i]); |
1383 | alloc_reg(current,i,rs2[i]); |
1384 | } |
1385 | else { |
1386 | if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]); |
1387 | if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]); |
1388 | } |
1389 | alloc_reg(current,i,rt1[i]); |
1390 | } |
1391 | current->is32|=1LL<<rt1[i]; |
1392 | } |
1393 | if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU |
1394 | if(rt1[i]) { |
1395 | if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1)) |
1396 | { |
1397 | alloc_reg64(current,i,rs1[i]); |
1398 | alloc_reg64(current,i,rs2[i]); |
1399 | alloc_reg(current,i,rt1[i]); |
1400 | } else { |
1401 | alloc_reg(current,i,rs1[i]); |
1402 | alloc_reg(current,i,rs2[i]); |
1403 | alloc_reg(current,i,rt1[i]); |
1404 | } |
1405 | } |
1406 | current->is32|=1LL<<rt1[i]; |
1407 | } |
1408 | if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR |
1409 | if(rt1[i]) { |
1410 | if(rs1[i]&&rs2[i]) { |
1411 | alloc_reg(current,i,rs1[i]); |
1412 | alloc_reg(current,i,rs2[i]); |
1413 | } |
1414 | else |
1415 | { |
1416 | if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]); |
1417 | if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]); |
1418 | } |
1419 | alloc_reg(current,i,rt1[i]); |
1420 | if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1)) |
1421 | { |
1422 | if(!((current->uu>>rt1[i])&1)) { |
1423 | alloc_reg64(current,i,rt1[i]); |
1424 | } |
1425 | if(get_reg(current->regmap,rt1[i]|64)>=0) { |
1426 | if(rs1[i]&&rs2[i]) { |
1427 | alloc_reg64(current,i,rs1[i]); |
1428 | alloc_reg64(current,i,rs2[i]); |
1429 | } |
1430 | else |
1431 | { |
1432 | // Is is really worth it to keep 64-bit values in registers? |
1433 | #ifdef NATIVE_64BIT |
1434 | if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]); |
1435 | if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg64(current,i,rs2[i]); |
1436 | #endif |
1437 | } |
1438 | } |
1439 | current->is32&=~(1LL<<rt1[i]); |
1440 | } else { |
1441 | current->is32|=1LL<<rt1[i]; |
1442 | } |
1443 | } |
1444 | } |
1445 | if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU |
1446 | if(rt1[i]) { |
1447 | if(rs1[i]&&rs2[i]) { |
1448 | if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) { |
1449 | alloc_reg64(current,i,rs1[i]); |
1450 | alloc_reg64(current,i,rs2[i]); |
1451 | alloc_reg64(current,i,rt1[i]); |
1452 | } else { |
1453 | alloc_reg(current,i,rs1[i]); |
1454 | alloc_reg(current,i,rs2[i]); |
1455 | alloc_reg(current,i,rt1[i]); |
1456 | } |
1457 | } |
1458 | else { |
1459 | alloc_reg(current,i,rt1[i]); |
1460 | if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) { |
1461 | // DADD used as move, or zeroing |
1462 | // If we have a 64-bit source, then make the target 64 bits too |
1463 | if(rs1[i]&&!((current->is32>>rs1[i])&1)) { |
1464 | if(get_reg(current->regmap,rs1[i])>=0) alloc_reg64(current,i,rs1[i]); |
1465 | alloc_reg64(current,i,rt1[i]); |
1466 | } else if(rs2[i]&&!((current->is32>>rs2[i])&1)) { |
1467 | if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]); |
1468 | alloc_reg64(current,i,rt1[i]); |
1469 | } |
1470 | if(opcode2[i]>=0x2e&&rs2[i]) { |
1471 | // DSUB used as negation - 64-bit result |
1472 | // If we have a 32-bit register, extend it to 64 bits |
1473 | if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]); |
1474 | alloc_reg64(current,i,rt1[i]); |
1475 | } |
1476 | } |
1477 | } |
1478 | if(rs1[i]&&rs2[i]) { |
1479 | current->is32&=~(1LL<<rt1[i]); |
1480 | } else if(rs1[i]) { |
1481 | current->is32&=~(1LL<<rt1[i]); |
1482 | if((current->is32>>rs1[i])&1) |
1483 | current->is32|=1LL<<rt1[i]; |
1484 | } else if(rs2[i]) { |
1485 | current->is32&=~(1LL<<rt1[i]); |
1486 | if((current->is32>>rs2[i])&1) |
1487 | current->is32|=1LL<<rt1[i]; |
1488 | } else { |
1489 | current->is32|=1LL<<rt1[i]; |
1490 | } |
1491 | } |
1492 | } |
1493 | clear_const(current,rs1[i]); |
1494 | clear_const(current,rs2[i]); |
1495 | clear_const(current,rt1[i]); |
1496 | dirty_reg(current,rt1[i]); |
1497 | } |
1498 | |
1499 | void imm16_alloc(struct regstat *current,int i) |
1500 | { |
1501 | if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]); |
1502 | else lt1[i]=rs1[i]; |
1503 | if(rt1[i]) alloc_reg(current,i,rt1[i]); |
1504 | if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU |
1505 | current->is32&=~(1LL<<rt1[i]); |
1506 | if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) { |
1507 | // TODO: Could preserve the 32-bit flag if the immediate is zero |
1508 | alloc_reg64(current,i,rt1[i]); |
1509 | alloc_reg64(current,i,rs1[i]); |
1510 | } |
1511 | clear_const(current,rs1[i]); |
1512 | clear_const(current,rt1[i]); |
1513 | } |
1514 | else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU |
1515 | if((~current->is32>>rs1[i])&1) alloc_reg64(current,i,rs1[i]); |
1516 | current->is32|=1LL<<rt1[i]; |
1517 | clear_const(current,rs1[i]); |
1518 | clear_const(current,rt1[i]); |
1519 | } |
1520 | else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI |
1521 | if(((~current->is32>>rs1[i])&1)&&opcode[i]>0x0c) { |
1522 | if(rs1[i]!=rt1[i]) { |
1523 | if(needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]); |
1524 | alloc_reg64(current,i,rt1[i]); |
1525 | current->is32&=~(1LL<<rt1[i]); |
1526 | } |
1527 | } |
1528 | else current->is32|=1LL<<rt1[i]; // ANDI clears upper bits |
1529 | if(is_const(current,rs1[i])) { |
1530 | int v=get_const(current,rs1[i]); |
1531 | if(opcode[i]==0x0c) set_const(current,rt1[i],v&imm[i]); |
1532 | if(opcode[i]==0x0d) set_const(current,rt1[i],v|imm[i]); |
1533 | if(opcode[i]==0x0e) set_const(current,rt1[i],v^imm[i]); |
1534 | } |
1535 | else clear_const(current,rt1[i]); |
1536 | } |
1537 | else if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU |
1538 | if(is_const(current,rs1[i])) { |
1539 | int v=get_const(current,rs1[i]); |
1540 | set_const(current,rt1[i],v+imm[i]); |
1541 | } |
1542 | else clear_const(current,rt1[i]); |
1543 | current->is32|=1LL<<rt1[i]; |
1544 | } |
1545 | else { |
1546 | set_const(current,rt1[i],((long long)((short)imm[i]))<<16); // LUI |
1547 | current->is32|=1LL<<rt1[i]; |
1548 | } |
1549 | dirty_reg(current,rt1[i]); |
1550 | } |
1551 | |
1552 | void load_alloc(struct regstat *current,int i) |
1553 | { |
1554 | clear_const(current,rt1[i]); |
1555 | //if(rs1[i]!=rt1[i]&&needed_again(rs1[i],i)) clear_const(current,rs1[i]); // Does this help or hurt? |
1556 | if(!rs1[i]) current->u&=~1LL; // Allow allocating r0 if it's the source register |
1557 | if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]); |
1558 | if(rt1[i]) { |
1559 | alloc_reg(current,i,rt1[i]); |
1560 | if(opcode[i]==0x27||opcode[i]==0x37) // LWU/LD |
1561 | { |
1562 | current->is32&=~(1LL<<rt1[i]); |
1563 | alloc_reg64(current,i,rt1[i]); |
1564 | } |
1565 | else if(opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR |
1566 | { |
1567 | current->is32&=~(1LL<<rt1[i]); |
1568 | alloc_reg64(current,i,rt1[i]); |
1569 | alloc_all(current,i); |
1570 | alloc_reg64(current,i,FTEMP); |
1571 | } |
1572 | else current->is32|=1LL<<rt1[i]; |
1573 | dirty_reg(current,rt1[i]); |
1574 | // If using TLB, need a register for pointer to the mapping table |
1575 | if(using_tlb) alloc_reg(current,i,TLREG); |
1576 | // LWL/LWR need a temporary register for the old value |
1577 | if(opcode[i]==0x22||opcode[i]==0x26) |
1578 | { |
1579 | alloc_reg(current,i,FTEMP); |
1580 | alloc_reg_temp(current,i,-1); |
1581 | } |
1582 | } |
1583 | else |
1584 | { |
1585 | // Load to r0 (dummy load) |
1586 | // but we still need a register to calculate the address |
1587 | alloc_reg_temp(current,i,-1); |
1588 | } |
1589 | } |
1590 | |
1591 | void store_alloc(struct regstat *current,int i) |
1592 | { |
1593 | clear_const(current,rs2[i]); |
1594 | if(!(rs2[i])) current->u&=~1LL; // Allow allocating r0 if necessary |
1595 | if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]); |
1596 | alloc_reg(current,i,rs2[i]); |
1597 | if(opcode[i]==0x2c||opcode[i]==0x2d||opcode[i]==0x3f) { // 64-bit SDL/SDR/SD |
1598 | alloc_reg64(current,i,rs2[i]); |
1599 | if(rs2[i]) alloc_reg(current,i,FTEMP); |
1600 | } |
1601 | // If using TLB, need a register for pointer to the mapping table |
1602 | if(using_tlb) alloc_reg(current,i,TLREG); |
1603 | #if defined(HOST_IMM8) |
1604 | // On CPUs without 32-bit immediates we need a pointer to invalid_code |
1605 | else alloc_reg(current,i,INVCP); |
1606 | #endif |
1607 | if(opcode[i]==0x2c||opcode[i]==0x2d) { // 64-bit SDL/SDR |
1608 | alloc_reg(current,i,FTEMP); |
1609 | } |
1610 | // We need a temporary register for address generation |
1611 | alloc_reg_temp(current,i,-1); |
1612 | } |
1613 | |
1614 | void c1ls_alloc(struct regstat *current,int i) |
1615 | { |
1616 | //clear_const(current,rs1[i]); // FIXME |
1617 | clear_const(current,rt1[i]); |
1618 | if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]); |
1619 | alloc_reg(current,i,CSREG); // Status |
1620 | alloc_reg(current,i,FTEMP); |
1621 | if(opcode[i]==0x35||opcode[i]==0x3d) { // 64-bit LDC1/SDC1 |
1622 | alloc_reg64(current,i,FTEMP); |
1623 | } |
1624 | // If using TLB, need a register for pointer to the mapping table |
1625 | if(using_tlb) alloc_reg(current,i,TLREG); |
1626 | #if defined(HOST_IMM8) |
1627 | // On CPUs without 32-bit immediates we need a pointer to invalid_code |
1628 | else if((opcode[i]&0x3b)==0x39) // SWC1/SDC1 |
1629 | alloc_reg(current,i,INVCP); |
1630 | #endif |
1631 | // We need a temporary register for address generation |
1632 | alloc_reg_temp(current,i,-1); |
1633 | } |
1634 | |
1635 | #ifndef multdiv_alloc |
1636 | void multdiv_alloc(struct regstat *current,int i) |
1637 | { |
1638 | // case 0x18: MULT |
1639 | // case 0x19: MULTU |
1640 | // case 0x1A: DIV |
1641 | // case 0x1B: DIVU |
1642 | // case 0x1C: DMULT |
1643 | // case 0x1D: DMULTU |
1644 | // case 0x1E: DDIV |
1645 | // case 0x1F: DDIVU |
1646 | clear_const(current,rs1[i]); |
1647 | clear_const(current,rs2[i]); |
1648 | if(rs1[i]&&rs2[i]) |
1649 | { |
1650 | if((opcode2[i]&4)==0) // 32-bit |
1651 | { |
1652 | current->u&=~(1LL<<HIREG); |
1653 | current->u&=~(1LL<<LOREG); |
1654 | alloc_reg(current,i,HIREG); |
1655 | alloc_reg(current,i,LOREG); |
1656 | alloc_reg(current,i,rs1[i]); |
1657 | alloc_reg(current,i,rs2[i]); |
1658 | current->is32|=1LL<<HIREG; |
1659 | current->is32|=1LL<<LOREG; |
1660 | dirty_reg(current,HIREG); |
1661 | dirty_reg(current,LOREG); |
1662 | } |
1663 | else // 64-bit |
1664 | { |
1665 | current->u&=~(1LL<<HIREG); |
1666 | current->u&=~(1LL<<LOREG); |
1667 | current->uu&=~(1LL<<HIREG); |
1668 | current->uu&=~(1LL<<LOREG); |
1669 | alloc_reg64(current,i,HIREG); |
1670 | //if(HOST_REGS>10) alloc_reg64(current,i,LOREG); |
1671 | alloc_reg64(current,i,rs1[i]); |
1672 | alloc_reg64(current,i,rs2[i]); |
1673 | alloc_all(current,i); |
1674 | current->is32&=~(1LL<<HIREG); |
1675 | current->is32&=~(1LL<<LOREG); |
1676 | dirty_reg(current,HIREG); |
1677 | dirty_reg(current,LOREG); |
1678 | } |
1679 | } |
1680 | else |
1681 | { |
1682 | // Multiply by zero is zero. |
1683 | // MIPS does not have a divide by zero exception. |
1684 | // The result is undefined, we return zero. |
1685 | alloc_reg(current,i,HIREG); |
1686 | alloc_reg(current,i,LOREG); |
1687 | current->is32|=1LL<<HIREG; |
1688 | current->is32|=1LL<<LOREG; |
1689 | dirty_reg(current,HIREG); |
1690 | dirty_reg(current,LOREG); |
1691 | } |
1692 | } |
1693 | #endif |
1694 | |
1695 | void cop0_alloc(struct regstat *current,int i) |
1696 | { |
1697 | if(opcode2[i]==0) // MFC0 |
1698 | { |
1699 | if(rt1[i]) { |
1700 | clear_const(current,rt1[i]); |
1701 | alloc_all(current,i); |
1702 | alloc_reg(current,i,rt1[i]); |
1703 | current->is32|=1LL<<rt1[i]; |
1704 | dirty_reg(current,rt1[i]); |
1705 | } |
1706 | } |
1707 | else if(opcode2[i]==4) // MTC0 |
1708 | { |
1709 | if(rs1[i]){ |
1710 | clear_const(current,rs1[i]); |
1711 | alloc_reg(current,i,rs1[i]); |
1712 | alloc_all(current,i); |
1713 | } |
1714 | else { |
1715 | alloc_all(current,i); // FIXME: Keep r0 |
1716 | current->u&=~1LL; |
1717 | alloc_reg(current,i,0); |
1718 | } |
1719 | } |
1720 | else |
1721 | { |
1722 | // TLBR/TLBWI/TLBWR/TLBP/ERET |
1723 | assert(opcode2[i]==0x10); |
1724 | alloc_all(current,i); |
1725 | } |
1726 | } |
1727 | |
1728 | void cop1_alloc(struct regstat *current,int i) |
1729 | { |
1730 | alloc_reg(current,i,CSREG); // Load status |
1731 | if(opcode2[i]<3) // MFC1/DMFC1/CFC1 |
1732 | { |
1733 | assert(rt1[i]); |
1734 | clear_const(current,rt1[i]); |
1735 | if(opcode2[i]==1) { |
1736 | alloc_reg64(current,i,rt1[i]); // DMFC1 |
1737 | current->is32&=~(1LL<<rt1[i]); |
1738 | }else{ |
1739 | alloc_reg(current,i,rt1[i]); // MFC1/CFC1 |
1740 | current->is32|=1LL<<rt1[i]; |
1741 | } |
1742 | dirty_reg(current,rt1[i]); |
1743 | alloc_reg_temp(current,i,-1); |
1744 | } |
1745 | else if(opcode2[i]>3) // MTC1/DMTC1/CTC1 |
1746 | { |
1747 | if(rs1[i]){ |
1748 | clear_const(current,rs1[i]); |
1749 | if(opcode2[i]==5) |
1750 | alloc_reg64(current,i,rs1[i]); // DMTC1 |
1751 | else |
1752 | alloc_reg(current,i,rs1[i]); // MTC1/CTC1 |
1753 | alloc_reg_temp(current,i,-1); |
1754 | } |
1755 | else { |
1756 | current->u&=~1LL; |
1757 | alloc_reg(current,i,0); |
1758 | alloc_reg_temp(current,i,-1); |
1759 | } |
1760 | } |
1761 | } |
1762 | void fconv_alloc(struct regstat *current,int i) |
1763 | { |
1764 | alloc_reg(current,i,CSREG); // Load status |
1765 | alloc_reg_temp(current,i,-1); |
1766 | } |
1767 | void float_alloc(struct regstat *current,int i) |
1768 | { |
1769 | alloc_reg(current,i,CSREG); // Load status |
1770 | alloc_reg_temp(current,i,-1); |
1771 | } |
1772 | void fcomp_alloc(struct regstat *current,int i) |
1773 | { |
1774 | alloc_reg(current,i,CSREG); // Load status |
1775 | alloc_reg(current,i,FSREG); // Load flags |
1776 | dirty_reg(current,FSREG); // Flag will be modified |
1777 | alloc_reg_temp(current,i,-1); |
1778 | } |
1779 | |
1780 | void syscall_alloc(struct regstat *current,int i) |
1781 | { |
1782 | alloc_cc(current,i); |
1783 | dirty_reg(current,CCREG); |
1784 | alloc_all(current,i); |
1785 | current->isconst=0; |
1786 | } |
1787 | |
1788 | void delayslot_alloc(struct regstat *current,int i) |
1789 | { |
1790 | switch(itype[i]) { |
1791 | case UJUMP: |
1792 | case CJUMP: |
1793 | case SJUMP: |
1794 | case RJUMP: |
1795 | case FJUMP: |
1796 | case SYSCALL: |
1797 | case SPAN: |
1798 | assem_debug("jump in the delay slot. this shouldn't happen.\n");//exit(1); |
1799 | printf("Disabled speculative precompilation\n"); |
1800 | stop_after_jal=1; |
1801 | break; |
1802 | case IMM16: |
1803 | imm16_alloc(current,i); |
1804 | break; |
1805 | case LOAD: |
1806 | case LOADLR: |
1807 | load_alloc(current,i); |
1808 | break; |
1809 | case STORE: |
1810 | case STORELR: |
1811 | store_alloc(current,i); |
1812 | break; |
1813 | case ALU: |
1814 | alu_alloc(current,i); |
1815 | break; |
1816 | case SHIFT: |
1817 | shift_alloc(current,i); |
1818 | break; |
1819 | case MULTDIV: |
1820 | multdiv_alloc(current,i); |
1821 | break; |
1822 | case SHIFTIMM: |
1823 | shiftimm_alloc(current,i); |
1824 | break; |
1825 | case MOV: |
1826 | mov_alloc(current,i); |
1827 | break; |
1828 | case COP0: |
1829 | cop0_alloc(current,i); |
1830 | break; |
1831 | case COP1: |
1832 | cop1_alloc(current,i); |
1833 | break; |
1834 | case C1LS: |
1835 | c1ls_alloc(current,i); |
1836 | break; |
1837 | case FCONV: |
1838 | fconv_alloc(current,i); |
1839 | break; |
1840 | case FLOAT: |
1841 | float_alloc(current,i); |
1842 | break; |
1843 | case FCOMP: |
1844 | fcomp_alloc(current,i); |
1845 | break; |
1846 | } |
1847 | } |
1848 | |
1849 | // Special case where a branch and delay slot span two pages in virtual memory |
1850 | static void pagespan_alloc(struct regstat *current,int i) |
1851 | { |
1852 | current->isconst=0; |
1853 | current->wasconst=0; |
1854 | regs[i].wasconst=0; |
1855 | alloc_all(current,i); |
1856 | alloc_cc(current,i); |
1857 | dirty_reg(current,CCREG); |
1858 | if(opcode[i]==3) // JAL |
1859 | { |
1860 | alloc_reg(current,i,31); |
1861 | dirty_reg(current,31); |
1862 | } |
1863 | if(opcode[i]==0&&(opcode2[i]&0x3E)==8) // JR/JALR |
1864 | { |
1865 | alloc_reg(current,i,rs1[i]); |
1866 | if (rt1[i]==31) { |
1867 | alloc_reg(current,i,31); |
1868 | dirty_reg(current,31); |
1869 | } |
1870 | } |
1871 | if((opcode[i]&0x2E)==4) // BEQ/BNE/BEQL/BNEL |
1872 | { |
1873 | if(rs1[i]) alloc_reg(current,i,rs1[i]); |
1874 | if(rs2[i]) alloc_reg(current,i,rs2[i]); |
1875 | if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1)) |
1876 | { |
1877 | if(rs1[i]) alloc_reg64(current,i,rs1[i]); |
1878 | if(rs2[i]) alloc_reg64(current,i,rs2[i]); |
1879 | } |
1880 | } |
1881 | else |
1882 | if((opcode[i]&0x2E)==6) // BLEZ/BGTZ/BLEZL/BGTZL |
1883 | { |
1884 | if(rs1[i]) alloc_reg(current,i,rs1[i]); |
1885 | if(!((current->is32>>rs1[i])&1)) |
1886 | { |
1887 | if(rs1[i]) alloc_reg64(current,i,rs1[i]); |
1888 | } |
1889 | } |
1890 | else |
1891 | if(opcode[i]==0x11) // BC1 |
1892 | { |
1893 | alloc_reg(current,i,FSREG); |
1894 | alloc_reg(current,i,CSREG); |
1895 | } |
1896 | //else ... |
1897 | } |
1898 | |
1899 | add_stub(int type,int addr,int retaddr,int a,int b,int c,int d,int e) |
1900 | { |
1901 | stubs[stubcount][0]=type; |
1902 | stubs[stubcount][1]=addr; |
1903 | stubs[stubcount][2]=retaddr; |
1904 | stubs[stubcount][3]=a; |
1905 | stubs[stubcount][4]=b; |
1906 | stubs[stubcount][5]=c; |
1907 | stubs[stubcount][6]=d; |
1908 | stubs[stubcount][7]=e; |
1909 | stubcount++; |
1910 | } |
1911 | |
1912 | // Write out a single register |
1913 | void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32) |
1914 | { |
1915 | int hr; |
1916 | for(hr=0;hr<HOST_REGS;hr++) { |
1917 | if(hr!=EXCLUDE_REG) { |
1918 | if((regmap[hr]&63)==r) { |
1919 | if((dirty>>hr)&1) { |
1920 | if(regmap[hr]<64) { |
1921 | emit_storereg(r,hr); |
1922 | if((is32>>regmap[hr])&1) { |
1923 | emit_sarimm(hr,31,hr); |
1924 | emit_storereg(r|64,hr); |
1925 | } |
1926 | }else{ |
1927 | emit_storereg(r|64,hr); |
1928 | } |
1929 | } |
1930 | } |
1931 | } |
1932 | } |
1933 | } |
1934 | |
1935 | int mchecksum() |
1936 | { |
1937 | //if(!tracedebug) return 0; |
1938 | int i; |
1939 | int sum=0; |
1940 | for(i=0;i<2097152;i++) { |
1941 | unsigned int temp=sum; |
1942 | sum<<=1; |
1943 | sum|=(~temp)>>31; |
1944 | sum^=((u_int *)rdram)[i]; |
1945 | } |
1946 | return sum; |
1947 | } |
1948 | int rchecksum() |
1949 | { |
1950 | int i; |
1951 | int sum=0; |
1952 | for(i=0;i<64;i++) |
1953 | sum^=((u_int *)reg)[i]; |
1954 | return sum; |
1955 | } |
1956 | int fchecksum() |
1957 | { |
1958 | int i; |
1959 | int sum=0; |
1960 | for(i=0;i<64;i++) |
1961 | sum^=((u_int *)reg_cop1_fgr_64)[i]; |
1962 | return sum; |
1963 | } |
1964 | void rlist() |
1965 | { |
1966 | int i; |
1967 | printf("TRACE: "); |
1968 | for(i=0;i<32;i++) |
1969 | printf("r%d:%8x%8x ",i,((int *)(reg+i))[1],((int *)(reg+i))[0]); |
1970 | printf("\n"); |
1971 | printf("TRACE: "); |
1972 | for(i=0;i<32;i++) |
1973 | printf("f%d:%8x%8x ",i,((int*)reg_cop1_simple[i])[1],*((int*)reg_cop1_simple[i])); |
1974 | printf("\n"); |
1975 | } |
1976 | |
1977 | void enabletrace() |
1978 | { |
1979 | tracedebug=1; |
1980 | } |
1981 | |
1982 | void memdebug(int i) |
1983 | { |
1984 | //printf("TRACE: count=%d next=%d (checksum %x) lo=%8x%8x\n",Count,next_interupt,mchecksum(),(int)(reg[LOREG]>>32),(int)reg[LOREG]); |
1985 | //printf("TRACE: count=%d next=%d (rchecksum %x)\n",Count,next_interupt,rchecksum()); |
1986 | //rlist(); |
1987 | //if(tracedebug) { |
1988 | //if(Count>=-2084597794) { |
1989 | if((signed int)Count>=-2084597794&&(signed int)Count<0) { |
1990 | //if(0) { |
1991 | printf("TRACE: count=%d next=%d (checksum %x)\n",Count,next_interupt,mchecksum()); |
1992 | //printf("TRACE: count=%d next=%d (checksum %x) Status=%x\n",Count,next_interupt,mchecksum(),Status); |
1993 | //printf("TRACE: count=%d next=%d (checksum %x) hi=%8x%8x\n",Count,next_interupt,mchecksum(),(int)(reg[HIREG]>>32),(int)reg[HIREG]); |
1994 | rlist(); |
1995 | #ifdef __i386__ |
1996 | printf("TRACE: %x\n",(&i)[-1]); |
1997 | #endif |
1998 | #ifdef __arm__ |
1999 | int j; |
2000 | printf("TRACE: %x \n",(&j)[10]); |
2001 | printf("TRACE: %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x\n",(&j)[1],(&j)[2],(&j)[3],(&j)[4],(&j)[5],(&j)[6],(&j)[7],(&j)[8],(&j)[9],(&j)[10],(&j)[11],(&j)[12],(&j)[13],(&j)[14],(&j)[15],(&j)[16],(&j)[17],(&j)[18],(&j)[19],(&j)[20]); |
2002 | #endif |
2003 | //fflush(stdout); |
2004 | } |
2005 | //printf("TRACE: %x\n",(&i)[-1]); |
2006 | } |
2007 | |
2008 | void tlb_debug(u_int cause, u_int addr, u_int iaddr) |
2009 | { |
2010 | printf("TLB Exception: instruction=%x addr=%x cause=%x\n",iaddr, addr, cause); |
2011 | } |
2012 | |
2013 | void alu_assemble(int i,struct regstat *i_regs) |
2014 | { |
2015 | if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU |
2016 | if(rt1[i]) { |
2017 | signed char s1,s2,t; |
2018 | t=get_reg(i_regs->regmap,rt1[i]); |
2019 | if(t>=0) { |
2020 | s1=get_reg(i_regs->regmap,rs1[i]); |
2021 | s2=get_reg(i_regs->regmap,rs2[i]); |
2022 | if(rs1[i]&&rs2[i]) { |
2023 | assert(s1>=0); |
2024 | assert(s2>=0); |
2025 | if(opcode2[i]&2) emit_sub(s1,s2,t); |
2026 | else emit_add(s1,s2,t); |
2027 | } |
2028 | else if(rs1[i]) { |
2029 | if(s1>=0) emit_mov(s1,t); |
2030 | else emit_loadreg(rs1[i],t); |
2031 | } |
2032 | else if(rs2[i]) { |
2033 | if(s2>=0) { |
2034 | if(opcode2[i]&2) emit_neg(s2,t); |
2035 | else emit_mov(s2,t); |
2036 | } |
2037 | else { |
2038 | emit_loadreg(rs2[i],t); |
2039 | if(opcode2[i]&2) emit_neg(t,t); |
2040 | } |
2041 | } |
2042 | else emit_zeroreg(t); |
2043 | } |
2044 | } |
2045 | } |
2046 | if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU |
2047 | if(rt1[i]) { |
2048 | signed char s1l,s2l,s1h,s2h,tl,th; |
2049 | tl=get_reg(i_regs->regmap,rt1[i]); |
2050 | th=get_reg(i_regs->regmap,rt1[i]|64); |
2051 | if(tl>=0) { |
2052 | s1l=get_reg(i_regs->regmap,rs1[i]); |
2053 | s2l=get_reg(i_regs->regmap,rs2[i]); |
2054 | s1h=get_reg(i_regs->regmap,rs1[i]|64); |
2055 | s2h=get_reg(i_regs->regmap,rs2[i]|64); |
2056 | if(rs1[i]&&rs2[i]) { |
2057 | assert(s1l>=0); |
2058 | assert(s2l>=0); |
2059 | if(opcode2[i]&2) emit_subs(s1l,s2l,tl); |
2060 | else emit_adds(s1l,s2l,tl); |
2061 | if(th>=0) { |
2062 | #ifdef INVERTED_CARRY |
2063 | if(opcode2[i]&2) {if(s1h!=th) emit_mov(s1h,th);emit_sbb(th,s2h);} |
2064 | #else |
2065 | if(opcode2[i]&2) emit_sbc(s1h,s2h,th); |
2066 | #endif |
2067 | else emit_add(s1h,s2h,th); |
2068 | } |
2069 | } |
2070 | else if(rs1[i]) { |
2071 | if(s1l>=0) emit_mov(s1l,tl); |
2072 | else emit_loadreg(rs1[i],tl); |
2073 | if(th>=0) { |
2074 | if(s1h>=0) emit_mov(s1h,th); |
2075 | else emit_loadreg(rs1[i]|64,th); |
2076 | } |
2077 | } |
2078 | else if(rs2[i]) { |
2079 | if(s2l>=0) { |
2080 | if(opcode2[i]&2) emit_negs(s2l,tl); |
2081 | else emit_mov(s2l,tl); |
2082 | } |
2083 | else { |
2084 | emit_loadreg(rs2[i],tl); |
2085 | if(opcode2[i]&2) emit_negs(tl,tl); |
2086 | } |
2087 | if(th>=0) { |
2088 | #ifdef INVERTED_CARRY |
2089 | if(s2h>=0) emit_mov(s2h,th); |
2090 | else emit_loadreg(rs2[i]|64,th); |
2091 | if(opcode2[i]&2) { |
2092 | emit_adcimm(-1,th); // x86 has inverted carry flag |
2093 | emit_not(th,th); |
2094 | } |
2095 | #else |
2096 | if(opcode2[i]&2) { |
2097 | if(s2h>=0) emit_rscimm(s2h,0,th); |
2098 | else { |
2099 | emit_loadreg(rs2[i]|64,th); |
2100 | emit_rscimm(th,0,th); |
2101 | } |
2102 | }else{ |
2103 | if(s2h>=0) emit_mov(s2h,th); |
2104 | else emit_loadreg(rs2[i]|64,th); |
2105 | } |
2106 | #endif |
2107 | } |
2108 | } |
2109 | else { |
2110 | emit_zeroreg(tl); |
2111 | if(th>=0) emit_zeroreg(th); |
2112 | } |
2113 | } |
2114 | } |
2115 | } |
2116 | if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU |
2117 | if(rt1[i]) { |
2118 | signed char s1l,s1h,s2l,s2h,t; |
2119 | if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1)) |
2120 | { |
2121 | t=get_reg(i_regs->regmap,rt1[i]); |
2122 | //assert(t>=0); |
2123 | if(t>=0) { |
2124 | s1l=get_reg(i_regs->regmap,rs1[i]); |
2125 | s1h=get_reg(i_regs->regmap,rs1[i]|64); |
2126 | s2l=get_reg(i_regs->regmap,rs2[i]); |
2127 | s2h=get_reg(i_regs->regmap,rs2[i]|64); |
2128 | if(rs2[i]==0) // rx<r0 |
2129 | { |
2130 | assert(s1h>=0); |
2131 | if(opcode2[i]==0x2a) // SLT |
2132 | emit_shrimm(s1h,31,t); |
2133 | else // SLTU (unsigned can not be less than zero) |
2134 | emit_zeroreg(t); |
2135 | } |
2136 | else if(rs1[i]==0) // r0<rx |
2137 | { |
2138 | assert(s2h>=0); |
2139 | if(opcode2[i]==0x2a) // SLT |
2140 | emit_set_gz64_32(s2h,s2l,t); |
2141 | else // SLTU (set if not zero) |
2142 | emit_set_nz64_32(s2h,s2l,t); |
2143 | } |
2144 | else { |
2145 | assert(s1l>=0);assert(s1h>=0); |
2146 | assert(s2l>=0);assert(s2h>=0); |
2147 | if(opcode2[i]==0x2a) // SLT |
2148 | emit_set_if_less64_32(s1h,s1l,s2h,s2l,t); |
2149 | else // SLTU |
2150 | emit_set_if_carry64_32(s1h,s1l,s2h,s2l,t); |
2151 | } |
2152 | } |
2153 | } else { |
2154 | t=get_reg(i_regs->regmap,rt1[i]); |
2155 | //assert(t>=0); |
2156 | if(t>=0) { |
2157 | s1l=get_reg(i_regs->regmap,rs1[i]); |
2158 | s2l=get_reg(i_regs->regmap,rs2[i]); |
2159 | if(rs2[i]==0) // rx<r0 |
2160 | { |
2161 | assert(s1l>=0); |
2162 | if(opcode2[i]==0x2a) // SLT |
2163 | emit_shrimm(s1l,31,t); |
2164 | else // SLTU (unsigned can not be less than zero) |
2165 | emit_zeroreg(t); |
2166 | } |
2167 | else if(rs1[i]==0) // r0<rx |
2168 | { |
2169 | assert(s2l>=0); |
2170 | if(opcode2[i]==0x2a) // SLT |
2171 | emit_set_gz32(s2l,t); |
2172 | else // SLTU (set if not zero) |
2173 | emit_set_nz32(s2l,t); |
2174 | } |
2175 | else{ |
2176 | assert(s1l>=0);assert(s2l>=0); |
2177 | if(opcode2[i]==0x2a) // SLT |
2178 | emit_set_if_less32(s1l,s2l,t); |
2179 | else // SLTU |
2180 | emit_set_if_carry32(s1l,s2l,t); |
2181 | } |
2182 | } |
2183 | } |
2184 | } |
2185 | } |
2186 | if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR |
2187 | if(rt1[i]) { |
2188 | signed char s1l,s1h,s2l,s2h,th,tl; |
2189 | tl=get_reg(i_regs->regmap,rt1[i]); |
2190 | th=get_reg(i_regs->regmap,rt1[i]|64); |
2191 | if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1)&&th>=0) |
2192 | { |
2193 | assert(tl>=0); |
2194 | if(tl>=0) { |
2195 | s1l=get_reg(i_regs->regmap,rs1[i]); |
2196 | s1h=get_reg(i_regs->regmap,rs1[i]|64); |
2197 | s2l=get_reg(i_regs->regmap,rs2[i]); |
2198 | s2h=get_reg(i_regs->regmap,rs2[i]|64); |
2199 | if(rs1[i]&&rs2[i]) { |
2200 | assert(s1l>=0);assert(s1h>=0); |
2201 | assert(s2l>=0);assert(s2h>=0); |
2202 | if(opcode2[i]==0x24) { // AND |
2203 | emit_and(s1l,s2l,tl); |
2204 | emit_and(s1h,s2h,th); |
2205 | } else |
2206 | if(opcode2[i]==0x25) { // OR |
2207 | emit_or(s1l,s2l,tl); |
2208 | emit_or(s1h,s2h,th); |
2209 | } else |
2210 | if(opcode2[i]==0x26) { // XOR |
2211 | emit_xor(s1l,s2l,tl); |
2212 | emit_xor(s1h,s2h,th); |
2213 | } else |
2214 | if(opcode2[i]==0x27) { // NOR |
2215 | emit_or(s1l,s2l,tl); |
2216 | emit_or(s1h,s2h,th); |
2217 | emit_not(tl,tl); |
2218 | emit_not(th,th); |
2219 | } |
2220 | } |
2221 | else |
2222 | { |
2223 | if(opcode2[i]==0x24) { // AND |
2224 | emit_zeroreg(tl); |
2225 | emit_zeroreg(th); |
2226 | } else |
2227 | if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR |
2228 | if(rs1[i]){ |
2229 | if(s1l>=0) emit_mov(s1l,tl); |
2230 | else emit_loadreg(rs1[i],tl); |
2231 | if(s1h>=0) emit_mov(s1h,th); |
2232 | else emit_loadreg(rs1[i]|64,th); |
2233 | } |
2234 | else |
2235 | if(rs2[i]){ |
2236 | if(s2l>=0) emit_mov(s2l,tl); |
2237 | else emit_loadreg(rs2[i],tl); |
2238 | if(s2h>=0) emit_mov(s2h,th); |
2239 | else emit_loadreg(rs2[i]|64,th); |
2240 | } |
2241 | else{ |
2242 | emit_zeroreg(tl); |
2243 | emit_zeroreg(th); |
2244 | } |
2245 | } else |
2246 | if(opcode2[i]==0x27) { // NOR |
2247 | if(rs1[i]){ |
2248 | if(s1l>=0) emit_not(s1l,tl); |
2249 | else{ |
2250 | emit_loadreg(rs1[i],tl); |
2251 | emit_not(tl,tl); |
2252 | } |
2253 | if(s1h>=0) emit_not(s1h,th); |
2254 | else{ |
2255 | emit_loadreg(rs1[i]|64,th); |
2256 | emit_not(th,th); |
2257 | } |
2258 | } |
2259 | else |
2260 | if(rs2[i]){ |
2261 | if(s2l>=0) emit_not(s2l,tl); |
2262 | else{ |
2263 | emit_loadreg(rs2[i],tl); |
2264 | emit_not(tl,tl); |
2265 | } |
2266 | if(s2h>=0) emit_not(s2h,th); |
2267 | else{ |
2268 | emit_loadreg(rs2[i]|64,th); |
2269 | emit_not(th,th); |
2270 | } |
2271 | } |
2272 | else { |
2273 | emit_movimm(-1,tl); |
2274 | emit_movimm(-1,th); |
2275 | } |
2276 | } |
2277 | } |
2278 | } |
2279 | } |
2280 | else |
2281 | { |
2282 | // 32 bit |
2283 | if(tl>=0) { |
2284 | s1l=get_reg(i_regs->regmap,rs1[i]); |
2285 | s2l=get_reg(i_regs->regmap,rs2[i]); |
2286 | if(rs1[i]&&rs2[i]) { |
2287 | assert(s1l>=0); |
2288 | assert(s2l>=0); |
2289 | if(opcode2[i]==0x24) { // AND |
2290 | emit_and(s1l,s2l,tl); |
2291 | } else |
2292 | if(opcode2[i]==0x25) { // OR |
2293 | emit_or(s1l,s2l,tl); |
2294 | } else |
2295 | if(opcode2[i]==0x26) { // XOR |
2296 | emit_xor(s1l,s2l,tl); |
2297 | } else |
2298 | if(opcode2[i]==0x27) { // NOR |
2299 | emit_or(s1l,s2l,tl); |
2300 | emit_not(tl,tl); |
2301 | } |
2302 | } |
2303 | else |
2304 | { |
2305 | if(opcode2[i]==0x24) { // AND |
2306 | emit_zeroreg(tl); |
2307 | } else |
2308 | if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR |
2309 | if(rs1[i]){ |
2310 | if(s1l>=0) emit_mov(s1l,tl); |
2311 | else emit_loadreg(rs1[i],tl); // CHECK: regmap_entry? |
2312 | } |
2313 | else |
2314 | if(rs2[i]){ |
2315 | if(s2l>=0) emit_mov(s2l,tl); |
2316 | else emit_loadreg(rs2[i],tl); // CHECK: regmap_entry? |
2317 | } |
2318 | else emit_zeroreg(tl); |
2319 | } else |
2320 | if(opcode2[i]==0x27) { // NOR |
2321 | if(rs1[i]){ |
2322 | if(s1l>=0) emit_not(s1l,tl); |
2323 | else { |
2324 | emit_loadreg(rs1[i],tl); |
2325 | emit_not(tl,tl); |
2326 | } |
2327 | } |
2328 | else |
2329 | if(rs2[i]){ |
2330 | if(s2l>=0) emit_not(s2l,tl); |
2331 | else { |
2332 | emit_loadreg(rs2[i],tl); |
2333 | emit_not(tl,tl); |
2334 | } |
2335 | } |
2336 | else emit_movimm(-1,tl); |
2337 | } |
2338 | } |
2339 | } |
2340 | } |
2341 | } |
2342 | } |
2343 | } |
2344 | |
2345 | void imm16_assemble(int i,struct regstat *i_regs) |
2346 | { |
2347 | if (opcode[i]==0x0f) { // LUI |
2348 | if(rt1[i]) { |
2349 | signed char t; |
2350 | t=get_reg(i_regs->regmap,rt1[i]); |
2351 | //assert(t>=0); |
2352 | if(t>=0) { |
2353 | if(!((i_regs->isconst>>t)&1)) |
2354 | emit_movimm(imm[i]<<16,t); |
2355 | } |
2356 | } |
2357 | } |
2358 | if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU |
2359 | if(rt1[i]) { |
2360 | signed char s,t; |
2361 | t=get_reg(i_regs->regmap,rt1[i]); |
2362 | s=get_reg(i_regs->regmap,rs1[i]); |
2363 | if(rs1[i]) { |
2364 | //assert(t>=0); |
2365 | //assert(s>=0); |
2366 | if(t>=0) { |
2367 | if(!((i_regs->isconst>>t)&1)) { |
2368 | if(s<0) { |
2369 | if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t); |
2370 | emit_addimm(t,imm[i],t); |
2371 | }else{ |
2372 | if(!((i_regs->wasconst>>s)&1)) |
2373 | emit_addimm(s,imm[i],t); |
2374 | else |
2375 | emit_movimm(constmap[i][s]+imm[i],t); |
2376 | } |
2377 | } |
2378 | } |
2379 | } else { |
2380 | if(t>=0) { |
2381 | if(!((i_regs->isconst>>t)&1)) |
2382 | emit_movimm(imm[i],t); |
2383 | } |
2384 | } |
2385 | } |
2386 | } |
2387 | if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU |
2388 | if(rt1[i]) { |
2389 | signed char sh,sl,th,tl; |
2390 | th=get_reg(i_regs->regmap,rt1[i]|64); |
2391 | tl=get_reg(i_regs->regmap,rt1[i]); |
2392 | sh=get_reg(i_regs->regmap,rs1[i]|64); |
2393 | sl=get_reg(i_regs->regmap,rs1[i]); |
2394 | if(tl>=0) { |
2395 | if(rs1[i]) { |
2396 | assert(sh>=0); |
2397 | assert(sl>=0); |
2398 | if(th>=0) { |
2399 | emit_addimm64_32(sh,sl,imm[i],th,tl); |
2400 | } |
2401 | else { |
2402 | emit_addimm(sl,imm[i],tl); |
2403 | } |
2404 | } else { |
2405 | emit_movimm(imm[i],tl); |
2406 | if(th>=0) emit_movimm(((signed int)imm[i])>>31,th); |
2407 | } |
2408 | } |
2409 | } |
2410 | } |
2411 | else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU |
2412 | if(rt1[i]) { |
2413 | //assert(rs1[i]!=0); // r0 might be valid, but it's probably a bug |
2414 | signed char sh,sl,t; |
2415 | t=get_reg(i_regs->regmap,rt1[i]); |
2416 | sh=get_reg(i_regs->regmap,rs1[i]|64); |
2417 | sl=get_reg(i_regs->regmap,rs1[i]); |
2418 | //assert(t>=0); |
2419 | if(t>=0) { |
2420 | if(rs1[i]>0) { |
2421 | if(sh<0) assert((i_regs->was32>>rs1[i])&1); |
2422 | if(sh<0||((i_regs->was32>>rs1[i])&1)) { |
2423 | if(opcode[i]==0x0a) { // SLTI |
2424 | if(sl<0) { |
2425 | if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t); |
2426 | emit_slti32(t,imm[i],t); |
2427 | }else{ |
2428 | emit_slti32(sl,imm[i],t); |
2429 | } |
2430 | } |
2431 | else { // SLTIU |
2432 | if(sl<0) { |
2433 | if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t); |
2434 | emit_sltiu32(t,imm[i],t); |
2435 | }else{ |
2436 | emit_sltiu32(sl,imm[i],t); |
2437 | } |
2438 | } |
2439 | }else{ // 64-bit |
2440 | assert(sl>=0); |
2441 | if(opcode[i]==0x0a) // SLTI |
2442 | emit_slti64_32(sh,sl,imm[i],t); |
2443 | else // SLTIU |
2444 | emit_sltiu64_32(sh,sl,imm[i],t); |
2445 | } |
2446 | }else{ |
2447 | // SLTI(U) with r0 is just stupid, |
2448 | // nonetheless examples can be found |
2449 | if(opcode[i]==0x0a) // SLTI |
2450 | if(0<imm[i]) emit_movimm(1,t); |
2451 | else emit_zeroreg(t); |
2452 | else // SLTIU |
2453 | { |
2454 | if(imm[i]) emit_movimm(1,t); |
2455 | else emit_zeroreg(t); |
2456 | } |
2457 | } |
2458 | } |
2459 | } |
2460 | } |
2461 | else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI |
2462 | if(rt1[i]) { |
2463 | signed char sh,sl,th,tl; |
2464 | th=get_reg(i_regs->regmap,rt1[i]|64); |
2465 | tl=get_reg(i_regs->regmap,rt1[i]); |
2466 | sh=get_reg(i_regs->regmap,rs1[i]|64); |
2467 | sl=get_reg(i_regs->regmap,rs1[i]); |
2468 | if(tl>=0 && !((i_regs->isconst>>tl)&1)) { |
2469 | if(opcode[i]==0x0c) //ANDI |
2470 | { |
2471 | if(rs1[i]) { |
2472 | if(sl<0) { |
2473 | if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl); |
2474 | emit_andimm(tl,imm[i],tl); |
2475 | }else{ |
2476 | if(!((i_regs->wasconst>>sl)&1)) |
2477 | emit_andimm(sl,imm[i],tl); |
2478 | else |
2479 | emit_movimm(constmap[i][sl]&imm[i],tl); |
2480 | } |
2481 | } |
2482 | else |
2483 | emit_zeroreg(tl); |
2484 | if(th>=0) emit_zeroreg(th); |
2485 | } |
2486 | else |
2487 | { |
2488 | if(rs1[i]) { |
2489 | if(sl<0) { |
2490 | if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl); |
2491 | } |
2492 | if(th>=0) { |
2493 | if(sh<0) { |
2494 | emit_loadreg(rs1[i]|64,th); |
2495 | }else{ |
2496 | emit_mov(sh,th); |
2497 | } |
2498 | } |
2499 | if(opcode[i]==0x0d) //ORI |
2500 | if(sl<0) { |
2501 | emit_orimm(tl,imm[i],tl); |
2502 | }else{ |
2503 | if(!((i_regs->wasconst>>sl)&1)) |
2504 | emit_orimm(sl,imm[i],tl); |
2505 | else |
2506 | emit_movimm(constmap[i][sl]|imm[i],tl); |
2507 | } |
2508 | if(opcode[i]==0x0e) //XORI |
2509 | if(sl<0) { |
2510 | emit_xorimm(tl,imm[i],tl); |
2511 | }else{ |
2512 | if(!((i_regs->wasconst>>sl)&1)) |
2513 | emit_xorimm(sl,imm[i],tl); |
2514 | else |
2515 | emit_movimm(constmap[i][sl]^imm[i],tl); |
2516 | } |
2517 | } |
2518 | else { |
2519 | emit_movimm(imm[i],tl); |
2520 | if(th>=0) emit_zeroreg(th); |
2521 | } |
2522 | } |
2523 | } |
2524 | } |
2525 | } |
2526 | } |
2527 | |
2528 | void shiftimm_assemble(int i,struct regstat *i_regs) |
2529 | { |
2530 | if(opcode2[i]<=0x3) // SLL/SRL/SRA |
2531 | { |
2532 | if(rt1[i]) { |
2533 | signed char s,t; |
2534 | t=get_reg(i_regs->regmap,rt1[i]); |
2535 | s=get_reg(i_regs->regmap,rs1[i]); |
2536 | //assert(t>=0); |
2537 | if(t>=0){ |
2538 | if(rs1[i]==0) |
2539 | { |
2540 | emit_zeroreg(t); |
2541 | } |
2542 | else |
2543 | { |
2544 | if(s<0&&i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t); |
2545 | if(imm[i]) { |
2546 | if(opcode2[i]==0) // SLL |
2547 | { |
2548 | emit_shlimm(s<0?t:s,imm[i],t); |
2549 | } |
2550 | if(opcode2[i]==2) // SRL |
2551 | { |
2552 | emit_shrimm(s<0?t:s,imm[i],t); |
2553 | } |
2554 | if(opcode2[i]==3) // SRA |
2555 | { |
2556 | emit_sarimm(s<0?t:s,imm[i],t); |
2557 | } |
2558 | }else{ |
2559 | // Shift by zero |
2560 | if(s>=0 && s!=t) emit_mov(s,t); |
2561 | } |
2562 | } |
2563 | } |
2564 | //emit_storereg(rt1[i],t); //DEBUG |
2565 | } |
2566 | } |
2567 | if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA |
2568 | { |
2569 | if(rt1[i]) { |
2570 | signed char sh,sl,th,tl; |
2571 | th=get_reg(i_regs->regmap,rt1[i]|64); |
2572 | tl=get_reg(i_regs->regmap,rt1[i]); |
2573 | sh=get_reg(i_regs->regmap,rs1[i]|64); |
2574 | sl=get_reg(i_regs->regmap,rs1[i]); |
2575 | if(tl>=0) { |
2576 | if(rs1[i]==0) |
2577 | { |
2578 | emit_zeroreg(tl); |
2579 | if(th>=0) emit_zeroreg(th); |
2580 | } |
2581 | else |
2582 | { |
2583 | assert(sl>=0); |
2584 | assert(sh>=0); |
2585 | if(imm[i]) { |
2586 | if(opcode2[i]==0x38) // DSLL |
2587 | { |
2588 | if(th>=0) emit_shldimm(sh,sl,imm[i],th); |
2589 | emit_shlimm(sl,imm[i],tl); |
2590 | } |
2591 | if(opcode2[i]==0x3a) // DSRL |
2592 | { |
2593 | emit_shrdimm(sl,sh,imm[i],tl); |
2594 | if(th>=0) emit_shrimm(sh,imm[i],th); |
2595 | } |
2596 | if(opcode2[i]==0x3b) // DSRA |
2597 | { |
2598 | emit_shrdimm(sl,sh,imm[i],tl); |
2599 | if(th>=0) emit_sarimm(sh,imm[i],th); |
2600 | } |
2601 | }else{ |
2602 | // Shift by zero |
2603 | if(sl!=tl) emit_mov(sl,tl); |
2604 | if(th>=0&&sh!=th) emit_mov(sh,th); |
2605 | } |
2606 | } |
2607 | } |
2608 | } |
2609 | } |
2610 | if(opcode2[i]==0x3c) // DSLL32 |
2611 | { |
2612 | if(rt1[i]) { |
2613 | signed char sl,tl,th; |
2614 | tl=get_reg(i_regs->regmap,rt1[i]); |
2615 | th=get_reg(i_regs->regmap,rt1[i]|64); |
2616 | sl=get_reg(i_regs->regmap,rs1[i]); |
2617 | if(th>=0||tl>=0){ |
2618 | assert(tl>=0); |
2619 | assert(th>=0); |
2620 | assert(sl>=0); |
2621 | emit_mov(sl,th); |
2622 | emit_zeroreg(tl); |
2623 | if(imm[i]>32) |
2624 | { |
2625 | emit_shlimm(th,imm[i]&31,th); |
2626 | } |
2627 | } |
2628 | } |
2629 | } |
2630 | if(opcode2[i]==0x3e) // DSRL32 |
2631 | { |
2632 | if(rt1[i]) { |
2633 | signed char sh,tl,th; |
2634 | tl=get_reg(i_regs->regmap,rt1[i]); |
2635 | th=get_reg(i_regs->regmap,rt1[i]|64); |
2636 | sh=get_reg(i_regs->regmap,rs1[i]|64); |
2637 | if(tl>=0){ |
2638 | assert(sh>=0); |
2639 | emit_mov(sh,tl); |
2640 | if(th>=0) emit_zeroreg(th); |
2641 | if(imm[i]>32) |
2642 | { |
2643 | emit_shrimm(tl,imm[i]&31,tl); |
2644 | } |
2645 | } |
2646 | } |
2647 | } |
2648 | if(opcode2[i]==0x3f) // DSRA32 |
2649 | { |
2650 | if(rt1[i]) { |
2651 | signed char sh,tl; |
2652 | tl=get_reg(i_regs->regmap,rt1[i]); |
2653 | sh=get_reg(i_regs->regmap,rs1[i]|64); |
2654 | if(tl>=0){ |
2655 | assert(sh>=0); |
2656 | emit_mov(sh,tl); |
2657 | if(imm[i]>32) |
2658 | { |
2659 | emit_sarimm(tl,imm[i]&31,tl); |
2660 | } |
2661 | } |
2662 | } |
2663 | } |
2664 | } |
2665 | |
2666 | #ifndef shift_assemble |
2667 | void shift_assemble(int i,struct regstat *i_regs) |
2668 | { |
2669 | printf("Need shift_assemble for this architecture.\n"); |
2670 | exit(1); |
2671 | } |
2672 | #endif |
2673 | |
2674 | void load_assemble(int i,struct regstat *i_regs) |
2675 | { |
2676 | int s,th,tl,addr,map=-1; |
2677 | int offset; |
2678 | int jaddr=0; |
2679 | int memtarget,c=0; |
2680 | u_int hr,reglist=0; |
2681 | th=get_reg(i_regs->regmap,rt1[i]|64); |
2682 | tl=get_reg(i_regs->regmap,rt1[i]); |
2683 | s=get_reg(i_regs->regmap,rs1[i]); |
2684 | offset=imm[i]; |
2685 | for(hr=0;hr<HOST_REGS;hr++) { |
2686 | if(i_regs->regmap[hr]>=0) reglist|=1<<hr; |
2687 | } |
2688 | if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG); |
2689 | if(s>=0) { |
2690 | c=(i_regs->wasconst>>s)&1; |
2691 | memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80800000; |
2692 | if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1; |
2693 | } |
2694 | if(offset||s<0||c) addr=tl; |
2695 | else addr=s; |
2696 | //printf("load_assemble: c=%d\n",c); |
2697 | //if(c) printf("load_assemble: const=%x\n",(int)constmap[i][s]+offset); |
2698 | // FIXME: Even if the load is a NOP, we should check for pagefaults... |
2699 | if(tl>=0) { |
2700 | //assert(tl>=0); |
2701 | //assert(rt1[i]); |
2702 | reglist&=~(1<<tl); |
2703 | if(th>=0) reglist&=~(1<<th); |
2704 | if(!using_tlb) { |
2705 | if(!c) { |
2706 | //#define R29_HACK 1 |
2707 | #ifdef R29_HACK |
2708 | // Strmnnrmn's speed hack |
2709 | if(rs1[i]!=29||start<0x80001000||start>=0x80800000) |
2710 | #endif |
2711 | { |
2712 | emit_cmpimm(addr,0x800000); |
2713 | jaddr=(int)out; |
2714 | #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK |
2715 | // Hint to branch predictor that the branch is unlikely to be taken |
2716 | if(rs1[i]>=28) |
2717 | emit_jno_unlikely(0); |
2718 | else |
2719 | #endif |
2720 | emit_jno(0); |
2721 | } |
2722 | } |
2723 | }else{ // using tlb |
2724 | int x=0; |
2725 | if (opcode[i]==0x20||opcode[i]==0x24) x=3; // LB/LBU |
2726 | if (opcode[i]==0x21||opcode[i]==0x25) x=2; // LH/LHU |
2727 | map=get_reg(i_regs->regmap,TLREG); |
2728 | assert(map>=0); |
2729 | map=do_tlb_r(addr,tl,map,x,-1,-1,c,constmap[i][s]+offset); |
2730 | do_tlb_r_branch(map,c,constmap[i][s]+offset,&jaddr); |
2731 | } |
2732 | if (opcode[i]==0x20) { // LB |
2733 | if(!c||memtarget) { |
2734 | #ifdef HOST_IMM_ADDR32 |
2735 | if(c) |
2736 | emit_movsbl_tlb((constmap[i][s]+offset)^3,map,tl); |
2737 | else |
2738 | #endif |
2739 | { |
2740 | //emit_xorimm(addr,3,tl); |
2741 | //gen_tlb_addr_r(tl,map); |
2742 | //emit_movsbl_indexed((int)rdram-0x80000000,tl,tl); |
2743 | int x=0; |
2744 | if(!c) emit_xorimm(addr,3,tl); |
2745 | else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset); |
2746 | emit_movsbl_indexed_tlb(x,tl,map,tl); |
2747 | } |
2748 | if(jaddr) |
2749 | add_stub(LOADB_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist); |
2750 | } |
2751 | else |
2752 | inline_readstub(LOADB_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist); |
2753 | } |
2754 | if (opcode[i]==0x21) { // LH |
2755 | if(!c||memtarget) { |
2756 | #ifdef HOST_IMM_ADDR32 |
2757 | if(c) |
2758 | emit_movswl_tlb((constmap[i][s]+offset)^2,map,tl); |
2759 | else |
2760 | #endif |
2761 | { |
2762 | int x=0; |
2763 | if(!c) emit_xorimm(addr,2,tl); |
2764 | else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset); |
2765 | //#ifdef |
2766 | //emit_movswl_indexed_tlb(x,tl,map,tl); |
2767 | //else |
2768 | if(map>=0) { |
2769 | gen_tlb_addr_r(tl,map); |
2770 | emit_movswl_indexed(x,tl,tl); |
2771 | }else |
2772 | emit_movswl_indexed((int)rdram-0x80000000+x,tl,tl); |
2773 | } |
2774 | if(jaddr) |
2775 | add_stub(LOADH_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist); |
2776 | } |
2777 | else |
2778 | inline_readstub(LOADH_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist); |
2779 | } |
2780 | if (opcode[i]==0x23) { // LW |
2781 | if(!c||memtarget) { |
2782 | //emit_readword_indexed((int)rdram-0x80000000,addr,tl); |
2783 | #ifdef HOST_IMM_ADDR32 |
2784 | if(c) |
2785 | emit_readword_tlb(constmap[i][s]+offset,map,tl); |
2786 | else |
2787 | #endif |
2788 | emit_readword_indexed_tlb(0,addr,map,tl); |
2789 | if(jaddr) |
2790 | add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist); |
2791 | } |
2792 | else |
2793 | inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist); |
2794 | } |
2795 | if (opcode[i]==0x24) { // LBU |
2796 | if(!c||memtarget) { |
2797 | #ifdef HOST_IMM_ADDR32 |
2798 | if(c) |
2799 | emit_movzbl_tlb((constmap[i][s]+offset)^3,map,tl); |
2800 | else |
2801 | #endif |
2802 | { |
2803 | //emit_xorimm(addr,3,tl); |
2804 | //gen_tlb_addr_r(tl,map); |
2805 | //emit_movzbl_indexed((int)rdram-0x80000000,tl,tl); |
2806 | int x=0; |
2807 | if(!c) emit_xorimm(addr,3,tl); |
2808 | else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset); |
2809 | emit_movzbl_indexed_tlb(x,tl,map,tl); |
2810 | } |
2811 | if(jaddr) |
2812 | add_stub(LOADBU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist); |
2813 | } |
2814 | else |
2815 | inline_readstub(LOADBU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist); |
2816 | } |
2817 | if (opcode[i]==0x25) { // LHU |
2818 | if(!c||memtarget) { |
2819 | #ifdef HOST_IMM_ADDR32 |
2820 | if(c) |
2821 | emit_movzwl_tlb((constmap[i][s]+offset)^2,map,tl); |
2822 | else |
2823 | #endif |
2824 | { |
2825 | int x=0; |
2826 | if(!c) emit_xorimm(addr,2,tl); |
2827 | else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset); |
2828 | //#ifdef |
2829 | //emit_movzwl_indexed_tlb(x,tl,map,tl); |
2830 | //#else |
2831 | if(map>=0) { |
2832 | gen_tlb_addr_r(tl,map); |
2833 | emit_movzwl_indexed(x,tl,tl); |
2834 | }else |
2835 | emit_movzwl_indexed((int)rdram-0x80000000+x,tl,tl); |
2836 | if(jaddr) |
2837 | add_stub(LOADHU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist); |
2838 | } |
2839 | } |
2840 | else |
2841 | inline_readstub(LOADHU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist); |
2842 | } |
2843 | if (opcode[i]==0x27) { // LWU |
2844 | assert(th>=0); |
2845 | if(!c||memtarget) { |
2846 | //emit_readword_indexed((int)rdram-0x80000000,addr,tl); |
2847 | #ifdef HOST_IMM_ADDR32 |
2848 | if(c) |
2849 | emit_readword_tlb(constmap[i][s]+offset,map,tl); |
2850 | else |
2851 | #endif |
2852 | emit_readword_indexed_tlb(0,addr,map,tl); |
2853 | if(jaddr) |
2854 | add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist); |
2855 | } |
2856 | else { |
2857 | inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist); |
2858 | } |
2859 | emit_zeroreg(th); |
2860 | } |
2861 | if (opcode[i]==0x37) { // LD |
2862 | if(!c||memtarget) { |
2863 | //gen_tlb_addr_r(tl,map); |
2864 | //if(th>=0) emit_readword_indexed((int)rdram-0x80000000,addr,th); |
2865 | //emit_readword_indexed((int)rdram-0x7FFFFFFC,addr,tl); |
2866 | #ifdef HOST_IMM_ADDR32 |
2867 | if(c) |
2868 | emit_readdword_tlb(constmap[i][s]+offset,map,th,tl); |
2869 | else |
2870 | #endif |
2871 | emit_readdword_indexed_tlb(0,addr,map,th,tl); |
2872 | if(jaddr) |
2873 | add_stub(LOADD_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist); |
2874 | } |
2875 | else |
2876 | inline_readstub(LOADD_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist); |
2877 | } |
2878 | //emit_storereg(rt1[i],tl); // DEBUG |
2879 | } |
2880 | //if(opcode[i]==0x23) |
2881 | //if(opcode[i]==0x24) |
2882 | //if(opcode[i]==0x23||opcode[i]==0x24) |
2883 | /*if(opcode[i]==0x21||opcode[i]==0x23||opcode[i]==0x24) |
2884 | { |
2885 | //emit_pusha(); |
2886 | save_regs(0x100f); |
2887 | emit_readword((int)&last_count,ECX); |
2888 | #ifdef __i386__ |
2889 | if(get_reg(i_regs->regmap,CCREG)<0) |
2890 | emit_loadreg(CCREG,HOST_CCREG); |
2891 | emit_add(HOST_CCREG,ECX,HOST_CCREG); |
2892 | emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG); |
2893 | emit_writeword(HOST_CCREG,(int)&Count); |
2894 | #endif |
2895 | #ifdef __arm__ |
2896 | if(get_reg(i_regs->regmap,CCREG)<0) |
2897 | emit_loadreg(CCREG,0); |
2898 | else |
2899 | emit_mov(HOST_CCREG,0); |
2900 | emit_add(0,ECX,0); |
2901 | emit_addimm(0,2*ccadj[i],0); |
2902 | emit_writeword(0,(int)&Count); |
2903 | #endif |
2904 | emit_call((int)memdebug); |
2905 | //emit_popa(); |
2906 | restore_regs(0x100f); |
2907 | }/**/ |
2908 | } |
2909 | |
2910 | #ifndef loadlr_assemble |
2911 | void loadlr_assemble(int i,struct regstat *i_regs) |
2912 | { |
2913 | printf("Need loadlr_assemble for this architecture.\n"); |
2914 | exit(1); |
2915 | } |
2916 | #endif |
2917 | |
2918 | void store_assemble(int i,struct regstat *i_regs) |
2919 | { |
2920 | int s,th,tl,map=-1; |
2921 | int addr,temp; |
2922 | int offset; |
2923 | int jaddr=0,jaddr2,type; |
2924 | int memtarget,c=0; |
2925 | int agr=AGEN1+(i&1); |
2926 | u_int hr,reglist=0; |
2927 | th=get_reg(i_regs->regmap,rs2[i]|64); |
2928 | tl=get_reg(i_regs->regmap,rs2[i]); |
2929 | s=get_reg(i_regs->regmap,rs1[i]); |
2930 | temp=get_reg(i_regs->regmap,agr); |
2931 | if(temp<0) temp=get_reg(i_regs->regmap,-1); |
2932 | offset=imm[i]; |
2933 | if(s>=0) { |
2934 | c=(i_regs->wasconst>>s)&1; |
2935 | memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80800000; |
2936 | if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1; |
2937 | } |
2938 | assert(tl>=0); |
2939 | assert(temp>=0); |
2940 | for(hr=0;hr<HOST_REGS;hr++) { |
2941 | if(i_regs->regmap[hr]>=0) reglist|=1<<hr; |
2942 | } |
2943 | if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG); |
2944 | if(offset||s<0||c) addr=temp; |
2945 | else addr=s; |
2946 | if(!using_tlb) { |
2947 | if(!c) { |
2948 | #ifdef R29_HACK |
2949 | // Strmnnrmn's speed hack |
2950 | memtarget=1; |
2951 | if(rs1[i]!=29||start<0x80001000||start>=0x80800000) |
2952 | #endif |
2953 | emit_cmpimm(addr,0x800000); |
2954 | #ifdef DESTRUCTIVE_SHIFT |
2955 | if(s==addr) emit_mov(s,temp); |
2956 | #endif |
2957 | #ifdef R29_HACK |
2958 | if(rs1[i]!=29||start<0x80001000||start>=0x80800000) |
2959 | #endif |
2960 | { |
2961 | jaddr=(int)out; |
2962 | #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK |
2963 | // Hint to branch predictor that the branch is unlikely to be taken |
2964 | if(rs1[i]>=28) |
2965 | emit_jno_unlikely(0); |
2966 | else |
2967 | #endif |
2968 | emit_jno(0); |
2969 | } |
2970 | } |
2971 | }else{ // using tlb |
2972 | int x=0; |
2973 | if (opcode[i]==0x28) x=3; // SB |
2974 | if (opcode[i]==0x29) x=2; // SH |
2975 | map=get_reg(i_regs->regmap,TLREG); |
2976 | assert(map>=0); |
2977 | map=do_tlb_w(addr,temp,map,x,c,constmap[i][s]+offset); |
2978 | do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr); |
2979 | } |
2980 | |
2981 | if (opcode[i]==0x28) { // SB |
2982 | if(!c||memtarget) { |
2983 | int x=0; |
2984 | if(!c) emit_xorimm(addr,3,temp); |
2985 | else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset); |
2986 | //gen_tlb_addr_w(temp,map); |
2987 | //emit_writebyte_indexed(tl,(int)rdram-0x80000000,temp); |
2988 | emit_writebyte_indexed_tlb(tl,x,temp,map,temp); |
2989 | } |
2990 | type=STOREB_STUB; |
2991 | } |
2992 | if (opcode[i]==0x29) { // SH |
2993 | if(!c||memtarget) { |
2994 | int x=0; |
2995 | if(!c) emit_xorimm(addr,2,temp); |
2996 | else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset); |
2997 | //#ifdef |
2998 | //emit_writehword_indexed_tlb(tl,x,temp,map,temp); |
2999 | //#else |
3000 | if(map>=0) { |
3001 | gen_tlb_addr_w(temp,map); |
3002 | emit_writehword_indexed(tl,x,temp); |
3003 | }else |
3004 | emit_writehword_indexed(tl,(int)rdram-0x80000000+x,temp); |
3005 | } |
3006 | type=STOREH_STUB; |
3007 | } |
3008 | if (opcode[i]==0x2B) { // SW |
3009 | if(!c||memtarget) |
3010 | //emit_writeword_indexed(tl,(int)rdram-0x80000000,addr); |
3011 | emit_writeword_indexed_tlb(tl,0,addr,map,temp); |
3012 | type=STOREW_STUB; |
3013 | } |
3014 | if (opcode[i]==0x3F) { // SD |
3015 | if(!c||memtarget) { |
3016 | if(rs2[i]) { |
3017 | assert(th>=0); |
3018 | //emit_writeword_indexed(th,(int)rdram-0x80000000,addr); |
3019 | //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,addr); |
3020 | emit_writedword_indexed_tlb(th,tl,0,addr,map,temp); |
3021 | }else{ |
3022 | // Store zero |
3023 | //emit_writeword_indexed(tl,(int)rdram-0x80000000,temp); |
3024 | //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,temp); |
3025 | emit_writedword_indexed_tlb(tl,tl,0,addr,map,temp); |
3026 | } |
3027 | } |
3028 | type=STORED_STUB; |
3029 | } |
3030 | if(jaddr) { |
3031 | add_stub(type,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist); |
3032 | } else if(!memtarget) { |
3033 | inline_writestub(type,i,constmap[i][s]+offset,i_regs->regmap,rs2[i],ccadj[i],reglist); |
3034 | } |
3035 | if(!using_tlb) { |
3036 | if(!c||memtarget) { |
3037 | #ifdef DESTRUCTIVE_SHIFT |
3038 | // The x86 shift operation is 'destructive'; it overwrites the |
3039 | // source register, so we need to make a copy first and use that. |
3040 | addr=temp; |
3041 | #endif |
3042 | #if defined(HOST_IMM8) |
3043 | int ir=get_reg(i_regs->regmap,INVCP); |
3044 | assert(ir>=0); |
3045 | emit_cmpmem_indexedsr12_reg(ir,addr,1); |
3046 | #else |
3047 | emit_cmpmem_indexedsr12_imm((int)invalid_code,addr,1); |
3048 | #endif |
3049 | jaddr2=(int)out; |
3050 | emit_jne(0); |
3051 | add_stub(INVCODE_STUB,jaddr2,(int)out,reglist|(1<<HOST_CCREG),addr,0,0,0); |
3052 | } |
3053 | } |
3054 | //if(opcode[i]==0x2B || opcode[i]==0x3F) |
3055 | //if(opcode[i]==0x2B || opcode[i]==0x28) |
3056 | //if(opcode[i]==0x2B || opcode[i]==0x29) |
3057 | //if(opcode[i]==0x2B) |
3058 | /*if(opcode[i]==0x2B || opcode[i]==0x28 || opcode[i]==0x29 || opcode[i]==0x3F) |
3059 | { |
3060 | //emit_pusha(); |
3061 | save_regs(0x100f); |
3062 | emit_readword((int)&last_count,ECX); |
3063 | #ifdef __i386__ |
3064 | if(get_reg(i_regs->regmap,CCREG)<0) |
3065 | emit_loadreg(CCREG,HOST_CCREG); |
3066 | emit_add(HOST_CCREG,ECX,HOST_CCREG); |
3067 | emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG); |
3068 | emit_writeword(HOST_CCREG,(int)&Count); |
3069 | #endif |
3070 | #ifdef __arm__ |
3071 | if(get_reg(i_regs->regmap,CCREG)<0) |
3072 | emit_loadreg(CCREG,0); |
3073 | else |
3074 | emit_mov(HOST_CCREG,0); |
3075 | emit_add(0,ECX,0); |
3076 | emit_addimm(0,2*ccadj[i],0); |
3077 | emit_writeword(0,(int)&Count); |
3078 | #endif |
3079 | emit_call((int)memdebug); |
3080 | //emit_popa(); |
3081 | restore_regs(0x100f); |
3082 | }/**/ |
3083 | } |
3084 | |
3085 | void storelr_assemble(int i,struct regstat *i_regs) |
3086 | { |
3087 | int s,th,tl; |
3088 | int temp; |
3089 | int temp2; |
3090 | int offset; |
3091 | int jaddr=0,jaddr2; |
3092 | int case1,case2,case3; |
3093 | int done0,done1,done2; |
3094 | int memtarget,c=0; |
3095 | u_int hr,reglist=0; |
3096 | th=get_reg(i_regs->regmap,rs2[i]|64); |
3097 | tl=get_reg(i_regs->regmap,rs2[i]); |
3098 | s=get_reg(i_regs->regmap,rs1[i]); |
3099 | temp=get_reg(i_regs->regmap,-1); |
3100 | offset=imm[i]; |
3101 | if(s>=0) { |
3102 | c=(i_regs->isconst>>s)&1; |
3103 | memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80800000; |
3104 | if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1; |
3105 | } |
3106 | assert(tl>=0); |
3107 | for(hr=0;hr<HOST_REGS;hr++) { |
3108 | if(i_regs->regmap[hr]>=0) reglist|=1<<hr; |
3109 | } |
3110 | if(tl>=0) { |
3111 | assert(temp>=0); |
3112 | if(!using_tlb) { |
3113 | if(!c) { |
3114 | emit_cmpimm(s<0||offset?temp:s,0x800000); |
3115 | if(!offset&&s!=temp) emit_mov(s,temp); |
3116 | jaddr=(int)out; |
3117 | emit_jno(0); |
3118 | } |
3119 | else |
3120 | { |
3121 | if(!memtarget||!rs1[i]) { |
3122 | jaddr=(int)out; |
3123 | emit_jmp(0); |
3124 | } |
3125 | } |
3126 | if((u_int)rdram!=0x80000000) |
3127 | emit_addimm_no_flags((u_int)rdram-(u_int)0x80000000,temp); |
3128 | }else{ // using tlb |
3129 | int map=get_reg(i_regs->regmap,TLREG); |
3130 | assert(map>=0); |
3131 | map=do_tlb_w(c||s<0||offset?temp:s,temp,map,0,c,constmap[i][s]+offset); |
3132 | if(!c&&!offset&&s>=0) emit_mov(s,temp); |
3133 | do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr); |
3134 | if(!jaddr&&!memtarget) { |
3135 | jaddr=(int)out; |
3136 | emit_jmp(0); |
3137 | } |
3138 | gen_tlb_addr_w(temp,map); |
3139 | } |
3140 | |
3141 | if (opcode[i]==0x2C||opcode[i]==0x2D) { // SDL/SDR |
3142 | temp2=get_reg(i_regs->regmap,FTEMP); |
3143 | if(!rs2[i]) temp2=th=tl; |
3144 | } |
3145 | |
3146 | emit_testimm(temp,2); |
3147 | case2=(int)out; |
3148 | emit_jne(0); |
3149 | emit_testimm(temp,1); |
3150 | case1=(int)out; |
3151 | emit_jne(0); |
3152 | // 0 |
3153 | if (opcode[i]==0x2A) { // SWL |
3154 | emit_writeword_indexed(tl,0,temp); |
3155 | } |
3156 | if (opcode[i]==0x2E) { // SWR |
3157 | emit_writebyte_indexed(tl,3,temp); |
3158 | } |
3159 | if (opcode[i]==0x2C) { // SDL |
3160 | emit_writeword_indexed(th,0,temp); |
3161 | if(rs2[i]) emit_mov(tl,temp2); |
3162 | } |
3163 | if (opcode[i]==0x2D) { // SDR |
3164 | emit_writebyte_indexed(tl,3,temp); |
3165 | if(rs2[i]) emit_shldimm(th,tl,24,temp2); |
3166 | } |
3167 | done0=(int)out; |
3168 | emit_jmp(0); |
3169 | // 1 |
3170 | set_jump_target(case1,(int)out); |
3171 | if (opcode[i]==0x2A) { // SWL |
3172 | // Write 3 msb into three least significant bytes |
3173 | if(rs2[i]) emit_rorimm(tl,8,tl); |
3174 | emit_writehword_indexed(tl,-1,temp); |
3175 | if(rs2[i]) emit_rorimm(tl,16,tl); |
3176 | emit_writebyte_indexed(tl,1,temp); |
3177 | if(rs2[i]) emit_rorimm(tl,8,tl); |
3178 | } |
3179 | if (opcode[i]==0x2E) { // SWR |
3180 | // Write two lsb into two most significant bytes |
3181 | emit_writehword_indexed(tl,1,temp); |
3182 | } |
3183 | if (opcode[i]==0x2C) { // SDL |
3184 | if(rs2[i]) emit_shrdimm(tl,th,8,temp2); |
3185 | // Write 3 msb into three least significant bytes |
3186 | if(rs2[i]) emit_rorimm(th,8,th); |
3187 | emit_writehword_indexed(th,-1,temp); |
3188 | if(rs2[i]) emit_rorimm(th,16,th); |
3189 | emit_writebyte_indexed(th,1,temp); |
3190 | if(rs2[i]) emit_rorimm(th,8,th); |
3191 | } |
3192 | if (opcode[i]==0x2D) { // SDR |
3193 | if(rs2[i]) emit_shldimm(th,tl,16,temp2); |
3194 | // Write two lsb into two most significant bytes |
3195 | emit_writehword_indexed(tl,1,temp); |
3196 | } |
3197 | done1=(int)out; |
3198 | emit_jmp(0); |
3199 | // 2 |
3200 | set_jump_target(case2,(int)out); |
3201 | emit_testimm(temp,1); |
3202 | case3=(int)out; |
3203 | emit_jne(0); |
3204 | if (opcode[i]==0x2A) { // SWL |
3205 | // Write two msb into two least significant bytes |
3206 | if(rs2[i]) emit_rorimm(tl,16,tl); |
3207 | emit_writehword_indexed(tl,-2,temp); |
3208 | if(rs2[i]) emit_rorimm(tl,16,tl); |
3209 | } |
3210 | if (opcode[i]==0x2E) { // SWR |
3211 | // Write 3 lsb into three most significant bytes |
3212 | emit_writebyte_indexed(tl,-1,temp); |
3213 | if(rs2[i]) emit_rorimm(tl,8,tl); |
3214 | emit_writehword_indexed(tl,0,temp); |
3215 | if(rs2[i]) emit_rorimm(tl,24,tl); |
3216 | } |
3217 | if (opcode[i]==0x2C) { // SDL |
3218 | if(rs2[i]) emit_shrdimm(tl,th,16,temp2); |
3219 | // Write two msb into two least significant bytes |
3220 | if(rs2[i]) emit_rorimm(th,16,th); |
3221 | emit_writehword_indexed(th,-2,temp); |
3222 | if(rs2[i]) emit_rorimm(th,16,th); |
3223 | } |
3224 | if (opcode[i]==0x2D) { // SDR |
3225 | if(rs2[i]) emit_shldimm(th,tl,8,temp2); |
3226 | // Write 3 lsb into three most significant bytes |
3227 | emit_writebyte_indexed(tl,-1,temp); |
3228 | if(rs2[i]) emit_rorimm(tl,8,tl); |
3229 | emit_writehword_indexed(tl,0,temp); |
3230 | if(rs2[i]) emit_rorimm(tl,24,tl); |
3231 | } |
3232 | done2=(int)out; |
3233 | emit_jmp(0); |
3234 | // 3 |
3235 | set_jump_target(case3,(int)out); |
3236 | if (opcode[i]==0x2A) { // SWL |
3237 | // Write msb into least significant byte |
3238 | if(rs2[i]) emit_rorimm(tl,24,tl); |
3239 | emit_writebyte_indexed(tl,-3,temp); |
3240 | if(rs2[i]) emit_rorimm(tl,8,tl); |
3241 | } |
3242 | if (opcode[i]==0x2E) { // SWR |
3243 | // Write entire word |
3244 | emit_writeword_indexed(tl,-3,temp); |
3245 | } |
3246 | if (opcode[i]==0x2C) { // SDL |
3247 | if(rs2[i]) emit_shrdimm(tl,th,24,temp2); |
3248 | // Write msb into least significant byte |
3249 | if(rs2[i]) emit_rorimm(th,24,th); |
3250 | emit_writebyte_indexed(th,-3,temp); |
3251 | if(rs2[i]) emit_rorimm(th,8,th); |
3252 | } |
3253 | if (opcode[i]==0x2D) { // SDR |
3254 | if(rs2[i]) emit_mov(th,temp2); |
3255 | // Write entire word |
3256 | emit_writeword_indexed(tl,-3,temp); |
3257 | } |
3258 | set_jump_target(done0,(int)out); |
3259 | set_jump_target(done1,(int)out); |
3260 | set_jump_target(done2,(int)out); |
3261 | if (opcode[i]==0x2C) { // SDL |
3262 | emit_testimm(temp,4); |
3263 | done0=(int)out; |
3264 | emit_jne(0); |
3265 | emit_andimm(temp,~3,temp); |
3266 | emit_writeword_indexed(temp2,4,temp); |
3267 | set_jump_target(done0,(int)out); |
3268 | } |
3269 | if (opcode[i]==0x2D) { // SDR |
3270 | emit_testimm(temp,4); |
3271 | done0=(int)out; |
3272 | emit_jeq(0); |
3273 | emit_andimm(temp,~3,temp); |
3274 | emit_writeword_indexed(temp2,-4,temp); |
3275 | set_jump_target(done0,(int)out); |
3276 | } |
3277 | if(!c||!memtarget) |
3278 | add_stub(STORELR_STUB,jaddr,(int)out,0,(int)i_regs,rs2[i],ccadj[i],reglist); |
3279 | } |
3280 | if(!using_tlb) { |
3281 | emit_addimm_no_flags((u_int)0x80000000-(u_int)rdram,temp); |
3282 | #if defined(HOST_IMM8) |
3283 | int ir=get_reg(i_regs->regmap,INVCP); |
3284 | assert(ir>=0); |
3285 | emit_cmpmem_indexedsr12_reg(ir,temp,1); |
3286 | #else |
3287 | emit_cmpmem_indexedsr12_imm((int)invalid_code,temp,1); |
3288 | #endif |
3289 | jaddr2=(int)out; |
3290 | emit_jne(0); |
3291 | add_stub(INVCODE_STUB,jaddr2,(int)out,reglist|(1<<HOST_CCREG),temp,0,0,0); |
3292 | } |
3293 | /* |
3294 | emit_pusha(); |
3295 | //save_regs(0x100f); |
3296 | emit_readword((int)&last_count,ECX); |
3297 | if(get_reg(i_regs->regmap,CCREG)<0) |
3298 | emit_loadreg(CCREG,HOST_CCREG); |
3299 | emit_add(HOST_CCREG,ECX,HOST_CCREG); |
3300 | emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG); |
3301 | emit_writeword(HOST_CCREG,(int)&Count); |
3302 | emit_call((int)memdebug); |
3303 | emit_popa(); |
3304 | //restore_regs(0x100f); |
3305 | /**/ |
3306 | } |
3307 | |
3308 | void c1ls_assemble(int i,struct regstat *i_regs) |
3309 | { |
3310 | int s,th,tl; |
3311 | int temp,ar; |
3312 | int map=-1; |
3313 | int offset; |
3314 | int c=0; |
3315 | int jaddr,jaddr2=0,jaddr3,type; |
3316 | int agr=AGEN1+(i&1); |
3317 | u_int hr,reglist=0; |
3318 | th=get_reg(i_regs->regmap,FTEMP|64); |
3319 | tl=get_reg(i_regs->regmap,FTEMP); |
3320 | s=get_reg(i_regs->regmap,rs1[i]); |
3321 | temp=get_reg(i_regs->regmap,agr); |
3322 | if(temp<0) temp=get_reg(i_regs->regmap,-1); |
3323 | offset=imm[i]; |
3324 | assert(tl>=0); |
3325 | assert(rs1[i]>0); |
3326 | assert(temp>=0); |
3327 | for(hr=0;hr<HOST_REGS;hr++) { |
3328 | if(i_regs->regmap[hr]>=0) reglist|=1<<hr; |
3329 | } |
3330 | if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG); |
3331 | if (opcode[i]==0x31||opcode[i]==0x35) // LWC1/LDC1 |
3332 | { |
3333 | // Loads use a temporary register which we need to save |
3334 | reglist|=1<<temp; |
3335 | } |
3336 | if (opcode[i]==0x39||opcode[i]==0x3D) // SWC1/SDC1 |
3337 | ar=temp; |
3338 | else // LWC1/LDC1 |
3339 | ar=tl; |
3340 | //if(s<0) emit_loadreg(rs1[i],ar); //address_generation does this now |
3341 | //else c=(i_regs->wasconst>>s)&1; |
3342 | if(s>=0) c=(i_regs->wasconst>>s)&1; |
3343 | // Check cop1 unusable |
3344 | if(!cop1_usable) { |
3345 | signed char rs=get_reg(i_regs->regmap,CSREG); |
3346 | assert(rs>=0); |
3347 | emit_testimm(rs,0x20000000); |
3348 | jaddr=(int)out; |
3349 | emit_jeq(0); |
3350 | add_stub(FP_STUB,jaddr,(int)out,i,rs,(int)i_regs,is_delayslot,0); |
3351 | cop1_usable=1; |
3352 | } |
3353 | if (opcode[i]==0x39) { // SWC1 (get float address) |
3354 | emit_readword((int)®_cop1_simple[(source[i]>>16)&0x1f],tl); |
3355 | } |
3356 | if (opcode[i]==0x3D) { // SDC1 (get double address) |
3357 | emit_readword((int)®_cop1_double[(source[i]>>16)&0x1f],tl); |
3358 | } |
3359 | // Generate address + offset |
3360 | if(!using_tlb) { |
3361 | if(!c) |
3362 | emit_cmpimm(offset||c||s<0?ar:s,0x800000); |
3363 | } |
3364 | else |
3365 | { |
3366 | map=get_reg(i_regs->regmap,TLREG); |
3367 | assert(map>=0); |
3368 | if (opcode[i]==0x31||opcode[i]==0x35) { // LWC1/LDC1 |
3369 | map=do_tlb_r(offset||c||s<0?ar:s,ar,map,0,-1,-1,c,constmap[i][s]+offset); |
3370 | } |
3371 | if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1 |
3372 | map=do_tlb_w(offset||c||s<0?ar:s,ar,map,0,c,constmap[i][s]+offset); |
3373 | } |
3374 | } |
3375 | if (opcode[i]==0x39) { // SWC1 (read float) |
3376 | emit_readword_indexed(0,tl,tl); |
3377 | } |
3378 | if (opcode[i]==0x3D) { // SDC1 (read double) |
3379 | emit_readword_indexed(4,tl,th); |
3380 | emit_readword_indexed(0,tl,tl); |
3381 | } |
3382 | if (opcode[i]==0x31) { // LWC1 (get target address) |
3383 | emit_readword((int)®_cop1_simple[(source[i]>>16)&0x1f],temp); |
3384 | } |
3385 | if (opcode[i]==0x35) { // LDC1 (get target address) |
3386 | emit_readword((int)®_cop1_double[(source[i]>>16)&0x1f],temp); |
3387 | } |
3388 | if(!using_tlb) { |
3389 | if(!c) { |
3390 | jaddr2=(int)out; |
3391 | emit_jno(0); |
3392 | } |
3393 | else if(((signed int)(constmap[i][s]+offset))>=(signed int)0x80800000) { |
3394 | jaddr2=(int)out; |
3395 | emit_jmp(0); // inline_readstub/inline_writestub? Very rare case |
3396 | } |
3397 | #ifdef DESTRUCTIVE_SHIFT |
3398 | if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1 |
3399 | if(!offset&&!c&&s>=0) emit_mov(s,ar); |
3400 | } |
3401 | #endif |
3402 | }else{ |
3403 | if (opcode[i]==0x31||opcode[i]==0x35) { // LWC1/LDC1 |
3404 | do_tlb_r_branch(map,c,constmap[i][s]+offset,&jaddr2); |
3405 | } |
3406 | if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1 |
3407 | do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr2); |
3408 | } |
3409 | } |
3410 | if (opcode[i]==0x31) { // LWC1 |
3411 | //if(s>=0&&!c&&!offset) emit_mov(s,tl); |
3412 | //gen_tlb_addr_r(ar,map); |
3413 | //emit_readword_indexed((int)rdram-0x80000000,tl,tl); |
3414 | #ifdef HOST_IMM_ADDR32 |
3415 | if(c) emit_readword_tlb(constmap[i][s]+offset,map,tl); |
3416 | else |
3417 | #endif |
3418 | emit_readword_indexed_tlb(0,offset||c||s<0?tl:s,map,tl); |
3419 | type=LOADW_STUB; |
3420 | } |
3421 | if (opcode[i]==0x35) { // LDC1 |
3422 | assert(th>=0); |
3423 | //if(s>=0&&!c&&!offset) emit_mov(s,tl); |
3424 | //gen_tlb_addr_r(ar,map); |
3425 | //emit_readword_indexed((int)rdram-0x80000000,tl,th); |
3426 | //emit_readword_indexed((int)rdram-0x7FFFFFFC,tl,tl); |
3427 | #ifdef HOST_IMM_ADDR32 |
3428 | if(c) emit_readdword_tlb(constmap[i][s]+offset,map,th,tl); |
3429 | else |
3430 | #endif |
3431 | emit_readdword_indexed_tlb(0,offset||c||s<0?tl:s,map,th,tl); |
3432 | type=LOADD_STUB; |
3433 | } |
3434 | if (opcode[i]==0x39) { // SWC1 |
3435 | //emit_writeword_indexed(tl,(int)rdram-0x80000000,temp); |
3436 | emit_writeword_indexed_tlb(tl,0,offset||c||s<0?temp:s,map,temp); |
3437 | type=STOREW_STUB; |
3438 | } |
3439 | if (opcode[i]==0x3D) { // SDC1 |
3440 | assert(th>=0); |
3441 | //emit_writeword_indexed(th,(int)rdram-0x80000000,temp); |
3442 | //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,temp); |
3443 | emit_writedword_indexed_tlb(th,tl,0,offset||c||s<0?temp:s,map,temp); |
3444 | type=STORED_STUB; |
3445 | } |
3446 | if(!using_tlb) { |
3447 | if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1 |
3448 | #ifndef DESTRUCTIVE_SHIFT |
3449 | temp=offset||c||s<0?ar:s; |
3450 | #endif |
3451 | #if defined(HOST_IMM8) |
3452 | int ir=get_reg(i_regs->regmap,INVCP); |
3453 | assert(ir>=0); |
3454 | emit_cmpmem_indexedsr12_reg(ir,temp,1); |
3455 | #else |
3456 | emit_cmpmem_indexedsr12_imm((int)invalid_code,temp,1); |
3457 | #endif |
3458 | jaddr3=(int)out; |
3459 | emit_jne(0); |
3460 | add_stub(INVCODE_STUB,jaddr3,(int)out,reglist|(1<<HOST_CCREG),temp,0,0,0); |
3461 | } |
3462 | } |
3463 | if(jaddr2) add_stub(type,jaddr2,(int)out,i,offset||c||s<0?ar:s,(int)i_regs,ccadj[i],reglist); |
3464 | if (opcode[i]==0x31) { // LWC1 (write float) |
3465 | emit_writeword_indexed(tl,0,temp); |
3466 | } |
3467 | if (opcode[i]==0x35) { // LDC1 (write double) |
3468 | emit_writeword_indexed(th,4,temp); |
3469 | emit_writeword_indexed(tl,0,temp); |
3470 | } |
3471 | //if(opcode[i]==0x39) |
3472 | /*if(opcode[i]==0x39||opcode[i]==0x31) |
3473 | { |
3474 | emit_pusha(); |
3475 | emit_readword((int)&last_count,ECX); |
3476 | if(get_reg(i_regs->regmap,CCREG)<0) |
3477 | emit_loadreg(CCREG,HOST_CCREG); |
3478 | emit_add(HOST_CCREG,ECX,HOST_CCREG); |
3479 | emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG); |
3480 | emit_writeword(HOST_CCREG,(int)&Count); |
3481 | emit_call((int)memdebug); |
3482 | emit_popa(); |
3483 | }/**/ |
3484 | } |
3485 | |
3486 | #ifndef multdiv_assemble |
3487 | void multdiv_assemble(int i,struct regstat *i_regs) |
3488 | { |
3489 | printf("Need multdiv_assemble for this architecture.\n"); |
3490 | exit(1); |
3491 | } |
3492 | #endif |
3493 | |
3494 | void mov_assemble(int i,struct regstat *i_regs) |
3495 | { |
3496 | //if(opcode2[i]==0x10||opcode2[i]==0x12) { // MFHI/MFLO |
3497 | //if(opcode2[i]==0x11||opcode2[i]==0x13) { // MTHI/MTLO |
3498 | assert(rt1[i]>0); |
3499 | if(rt1[i]) { |
3500 | signed char sh,sl,th,tl; |
3501 | th=get_reg(i_regs->regmap,rt1[i]|64); |
3502 | tl=get_reg(i_regs->regmap,rt1[i]); |
3503 | //assert(tl>=0); |
3504 | if(tl>=0) { |
3505 | sh=get_reg(i_regs->regmap,rs1[i]|64); |
3506 | sl=get_reg(i_regs->regmap,rs1[i]); |
3507 | if(sl>=0) emit_mov(sl,tl); |
3508 | else emit_loadreg(rs1[i],tl); |
3509 | if(th>=0) { |
3510 | if(sh>=0) emit_mov(sh,th); |
3511 | else emit_loadreg(rs1[i]|64,th); |
3512 | } |
3513 | } |
3514 | } |
3515 | } |
3516 | |
3517 | #ifndef fconv_assemble |
3518 | void fconv_assemble(int i,struct regstat *i_regs) |
3519 | { |
3520 | printf("Need fconv_assemble for this architecture.\n"); |
3521 | exit(1); |
3522 | } |
3523 | #endif |
3524 | |
3525 | #if 0 |
3526 | void float_assemble(int i,struct regstat *i_regs) |
3527 | { |
3528 | printf("Need float_assemble for this architecture.\n"); |
3529 | exit(1); |
3530 | } |
3531 | #endif |
3532 | |
3533 | void syscall_assemble(int i,struct regstat *i_regs) |
3534 | { |
3535 | signed char ccreg=get_reg(i_regs->regmap,CCREG); |
3536 | assert(ccreg==HOST_CCREG); |
3537 | assert(!is_delayslot); |
3538 | emit_movimm(start+i*4,EAX); // Get PC |
3539 | emit_addimm(HOST_CCREG,CLOCK_DIVIDER*ccadj[i],HOST_CCREG); // CHECK: is this right? There should probably be an extra cycle... |
3540 | emit_jmp((int)jump_syscall); |
3541 | } |
3542 | |
3543 | void ds_assemble(int i,struct regstat *i_regs) |
3544 | { |
3545 | is_delayslot=1; |
3546 | switch(itype[i]) { |
3547 | case ALU: |
3548 | alu_assemble(i,i_regs);break; |
3549 | case IMM16: |
3550 | imm16_assemble(i,i_regs);break; |
3551 | case SHIFT: |
3552 | shift_assemble(i,i_regs);break; |
3553 | case SHIFTIMM: |
3554 | shiftimm_assemble(i,i_regs);break; |
3555 | case LOAD: |
3556 | load_assemble(i,i_regs);break; |
3557 | case LOADLR: |
3558 | loadlr_assemble(i,i_regs);break; |
3559 | case STORE: |
3560 | store_assemble(i,i_regs);break; |
3561 | case STORELR: |
3562 | storelr_assemble(i,i_regs);break; |
3563 | case COP0: |
3564 | cop0_assemble(i,i_regs);break; |
3565 | case COP1: |
3566 | cop1_assemble(i,i_regs);break; |
3567 | case C1LS: |
3568 | c1ls_assemble(i,i_regs);break; |
3569 | case FCONV: |
3570 | fconv_assemble(i,i_regs);break; |
|