[pcsx_rearmed.git] / libpcsxcore / psxcounters.c

/***************************************************************************
 *   Copyright (C) 2010 by Blade_Arma                                      *
 *                                                                         *
 *   This program is free software; you can redistribute it and/or modify  *
 *   it under the terms of the GNU General Public License as published by  *
 *   the Free Software Foundation; either version 2 of the License, or     *
 *   (at your option) any later version.                                   *
 *                                                                         *
 *   This program is distributed in the hope that it will be useful,       *
 *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
 *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
 *   GNU General Public License for more details.                          *
 *                                                                         *
 *   You should have received a copy of the GNU General Public License     *
 *   along with this program; if not, write to the                         *
 *   Free Software Foundation, Inc.,                                       *
 *   51 Franklin Street, Fifth Floor, Boston, MA 02111-1307 USA.           *
 ***************************************************************************/

/*
 * Internal PSX counters.
 */

#include "psxcounters.h"
#include "psxevents.h"
#include "gpu.h"
//#include "debug.h"
#define DebugVSync()

/******************************************************************************/

enum
{
    RcSyncModeEnable  = 0x0001, // 0
    Rc01BlankPause    = 0 << 1, // 1,2
    Rc01UnblankReset  = 1 << 1, // 1,2
    Rc01UnblankReset2 = 2 << 1, // 1,2
    Rc2Stop           = 0 << 1, // 1,2
    Rc2Stop2          = 3 << 1, // 1,2
    RcCountToTarget   = 0x0008, // 3
    RcIrqOnTarget     = 0x0010, // 4
    RcIrqOnOverflow   = 0x0020, // 5
    RcIrqRegenerate   = 0x0040, // 6
    RcUnknown7        = 0x0080, // 7    ?
    Rc0PixelClock     = 0x0100, // 8    fake implementation
    Rc1HSyncClock     = 0x0100, // 8
    Rc2Unknown8       = 0x0100, // 8    ?
    Rc0Unknown9       = 0x0200, // 9    ?
    Rc1Unknown9       = 0x0200, // 9    ?
    Rc2OneEighthClock = 0x0200, // 9
    RcUnknown10       = 0x0400, // 10   ?
    RcCountEqTarget   = 0x0800, // 11
    RcOverflow        = 0x1000, // 12
    RcUnknown13       = 0x2000, // 13   ? (always zero)
    RcUnknown14       = 0x4000, // 14   ? (always zero)
    RcUnknown15       = 0x8000, // 15   ? (always zero)
};

#define CounterQuantity           ( 4 )
//static const u32 CounterQuantity  = 4;

static const u32 CountToOverflow  = 0;
static const u32 CountToTarget    = 1;

static const u32 HSyncTotal[]     = { 263, 314 };
#define VBlankStart 240 // todo: depend on the actual GPU setting

#define VERBOSE_LEVEL 0

/******************************************************************************/
#ifdef DRC_DISABLE
Rcnt rcnts[ CounterQuantity ];
#endif
u32 hSyncCount = 0;
u32 frame_counter = 0;
static u32 hsync_steps = 0;

u32 psxNextCounter = 0, psxNextsCounter = 0;

/******************************************************************************/

static inline
u32 lineCycles(void)
{
    if (Config.PsxType)
        return PSXCLK / 50 / HSyncTotal[1];
    else
        return PSXCLK / 60 / HSyncTotal[0];
}

static inline
void setIrq( u32 irq )
{
    psxHu32ref(0x1070) |= SWAPu32(irq);
}

static
void verboseLog( u32 level, const char *str, ... )
{
#if VERBOSE_LEVEL > 0
    if( level <= VERBOSE_LEVEL )
    {
        va_list va;
        char buf[ 4096 ];

        va_start( va, str );
        vsprintf( buf, str, va );
        va_end( va );

        printf( "%s", buf );
        fflush( stdout );
    }
#endif
}

/******************************************************************************/

static inline
void _psxRcntWcount( u32 index, u32 value )
{
    value &= 0xffff;

    rcnts[index].cycleStart  = psxRegs.cycle;
    rcnts[index].cycleStart -= value * rcnts[index].rate;

    // TODO: <=.
    if( value < rcnts[index].target )
    {
        rcnts[index].cycle = rcnts[index].target * rcnts[index].rate;
        rcnts[index].counterState = CountToTarget;
    }
    else
    {
        rcnts[index].cycle = 0x10000 * rcnts[index].rate;
        rcnts[index].counterState = CountToOverflow;
    }
}

static inline
u32 _psxRcntRcount( u32 index )
{
    u32 count;

    count  = psxRegs.cycle;
    count -= rcnts[index].cycleStart;
    if (rcnts[index].rate > 1)
        count /= rcnts[index].rate;

    if( count > 0x10000 )
    {
        verboseLog( 1, "[RCNT %i] rcount > 0x10000: %x\n", index, count );
    }
    count &= 0xffff;

    return count;
}

static
void _psxRcntWmode( u32 index, u32 value )
{
    rcnts[index].mode = value;

    switch( index )
    {
        case 0:
            if( value & Rc0PixelClock )
            {
                rcnts[index].rate = 5;
            }
            else
            {
                rcnts[index].rate = 1;
            }
        break;
        case 1:
            if( value & Rc1HSyncClock )
            {
                rcnts[index].rate = lineCycles();
            }
            else
            {
                rcnts[index].rate = 1;
            }
        break;
        case 2:
            if( value & Rc2OneEighthClock )
            {
                rcnts[index].rate = 8;
            }
            else
            {
                rcnts[index].rate = 1;
            }

            // TODO: wcount must work.
            if( (value & 7) == (RcSyncModeEnable | Rc2Stop) ||
                (value & 7) == (RcSyncModeEnable | Rc2Stop2) )
            {
                rcnts[index].rate = 0xffffffff;
            }
        break;
    }
}

/******************************************************************************/

static
void psxRcntSet()
{
    s32 countToUpdate;
    u32 i;

    psxNextsCounter = psxRegs.cycle;
    psxNextCounter  = 0x7fffffff;

    for( i = 0; i < CounterQuantity; ++i )
    {
        countToUpdate = rcnts[i].cycle - (psxNextsCounter - rcnts[i].cycleStart);

        if( countToUpdate < 0 )
        {
            psxNextCounter = 0;
            break;
        }

        if( countToUpdate < (s32)psxNextCounter )
        {
            psxNextCounter = countToUpdate;
        }
    }

    set_event(PSXINT_RCNT, psxNextCounter);
}

/******************************************************************************/

static
void psxRcntReset( u32 index )
{
    u32 rcycles;

    rcnts[index].mode |= RcUnknown10;

    if( rcnts[index].counterState == CountToTarget )
    {
        rcycles = psxRegs.cycle - rcnts[index].cycleStart;
        if( rcnts[index].mode & RcCountToTarget )
        {
            rcycles -= rcnts[index].target * rcnts[index].rate;
            rcnts[index].cycleStart = psxRegs.cycle - rcycles;
        }
        else
        {
            rcnts[index].cycle = 0x10000 * rcnts[index].rate;
            rcnts[index].counterState = CountToOverflow;
        }

        if( rcnts[index].mode & RcIrqOnTarget )
        {
            if( (rcnts[index].mode & RcIrqRegenerate) || (!rcnts[index].irqState) )
            {
                verboseLog( 3, "[RCNT %i] irq\n", index );
                setIrq( rcnts[index].irq );
                rcnts[index].irqState = 1;
            }
        }

        rcnts[index].mode |= RcCountEqTarget;

        if( rcycles < 0x10000 * rcnts[index].rate )
            return;
    }

    if( rcnts[index].counterState == CountToOverflow )
    {
        rcycles = psxRegs.cycle - rcnts[index].cycleStart;
        rcycles -= 0x10000 * rcnts[index].rate;

        rcnts[index].cycleStart = psxRegs.cycle - rcycles;

        if( rcycles < rcnts[index].target * rcnts[index].rate )
        {
            rcnts[index].cycle = rcnts[index].target * rcnts[index].rate;
            rcnts[index].counterState = CountToTarget;
        }

        if( rcnts[index].mode & RcIrqOnOverflow )
        {
            if( (rcnts[index].mode & RcIrqRegenerate) || (!rcnts[index].irqState) )
            {
                verboseLog( 3, "[RCNT %i] irq\n", index );
                setIrq( rcnts[index].irq );
                rcnts[index].irqState = 1;
            }
        }

        rcnts[index].mode |= RcOverflow;
    }
}

static void scheduleRcntBase(void)
{
    // Schedule next call, in hsyncs
    if (hSyncCount < VBlankStart)
        hsync_steps = VBlankStart - hSyncCount;
    else
        hsync_steps = HSyncTotal[Config.PsxType] - hSyncCount;

    if (hSyncCount + hsync_steps == HSyncTotal[Config.PsxType])
    {
        rcnts[3].cycle = Config.PsxType ? PSXCLK / 50 : PSXCLK / 60;
    }
    else
    {
        // clk / 50 / 314 ~= 2157.25
        // clk / 60 / 263 ~= 2146.31
        u32 mult = Config.PsxType ? 8836089 : 8791293;
        rcnts[3].cycle = hsync_steps * mult >> 12;
    }
}

void psxRcntUpdate()
{
    u32 cycle, cycles_passed;

    cycle = psxRegs.cycle;

    // rcnt 0.
    cycles_passed = cycle - rcnts[0].cycleStart;
    while( cycles_passed >= rcnts[0].cycle )
    {
        if (((rcnts[0].mode & 7) == (RcSyncModeEnable | Rc01UnblankReset) ||
             (rcnts[0].mode & 7) == (RcSyncModeEnable | Rc01UnblankReset2))
            && cycles_passed > lineCycles())
        {
            u32 q = cycles_passed / (lineCycles() + 1u);
            rcnts[0].cycleStart += q * lineCycles();
            break;
        }
        else
            psxRcntReset( 0 );

        cycles_passed = cycle - rcnts[0].cycleStart;
    }

    // rcnt 1.
    while( cycle - rcnts[1].cycleStart >= rcnts[1].cycle )
    {
        psxRcntReset( 1 );
    }

    // rcnt 2.
    while( cycle - rcnts[2].cycleStart >= rcnts[2].cycle )
    {
        psxRcntReset( 2 );
    }

    // rcnt base.
    if( cycle - rcnts[3].cycleStart >= rcnts[3].cycle )
    {
        hSyncCount += hsync_steps;

        // VSync irq.
        if( hSyncCount == VBlankStart )
        {
            HW_GPU_STATUS &= SWAP32(~PSXGPU_LCF);
            GPU_vBlank( 1, 0 );
            setIrq( 0x01 );

            EmuUpdate();
            GPU_updateLace();

            if( SPU_async )
            {
                SPU_async( cycle, 1 );
            }
        }
        
        // Update lace.
        if( hSyncCount >= HSyncTotal[Config.PsxType] )
        {
            u32 status, field = 0;
            rcnts[3].cycleStart += Config.PsxType ? PSXCLK / 50 : PSXCLK / 60;
            hSyncCount = 0;
            frame_counter++;

            gpuSyncPluginSR();
            status = SWAP32(HW_GPU_STATUS) | PSXGPU_FIELD;
            if ((status & PSXGPU_ILACE_BITS) == PSXGPU_ILACE_BITS) {
                field = frame_counter & 1;
                status |= field << 31;
                status ^= field << 13;
            }
            HW_GPU_STATUS = SWAP32(status);
            GPU_vBlank(0, field);
            if ((s32)(psxRegs.gpuIdleAfter - psxRegs.cycle) < 0)
                psxRegs.gpuIdleAfter = psxRegs.cycle - 1; // prevent overflow

            if ((rcnts[0].mode & 7) == (RcSyncModeEnable | Rc01UnblankReset) ||
                (rcnts[0].mode & 7) == (RcSyncModeEnable | Rc01UnblankReset2))
            {
                rcnts[0].cycleStart = rcnts[3].cycleStart;
            }

            if ((rcnts[1].mode & 7) == (RcSyncModeEnable | Rc01UnblankReset) ||
                (rcnts[1].mode & 7) == (RcSyncModeEnable | Rc01UnblankReset2))
            {
                rcnts[1].cycleStart = rcnts[3].cycleStart;
            }
            else if (rcnts[1].mode & Rc1HSyncClock)
            {
                // adjust to remove the rounding error
                _psxRcntWcount(1, (psxRegs.cycle - rcnts[1].cycleStart) / rcnts[1].rate);
            }
        }

        scheduleRcntBase();
    }

    psxRcntSet();

#if 0 //ndef NDEBUG
    DebugVSync();
#endif
}

/******************************************************************************/

void psxRcntWcount( u32 index, u32 value )
{
    verboseLog( 2, "[RCNT %i] wcount: %x\n", index, value );

    _psxRcntWcount( index, value );
    psxRcntSet();
}

void psxRcntWmode( u32 index, u32 value )
{
    verboseLog( 1, "[RCNT %i] wmode: %x\n", index, value );

    _psxRcntWmode( index, value );
    _psxRcntWcount( index, 0 );

    rcnts[index].irqState = 0;
    psxRcntSet();
}

void psxRcntWtarget( u32 index, u32 value )
{
    verboseLog( 1, "[RCNT %i] wtarget: %x\n", index, value );

    rcnts[index].target = value;

    _psxRcntWcount( index, _psxRcntRcount( index ) );
    psxRcntSet();
}

/******************************************************************************/

u32 psxRcntRcount0()
{
    u32 index = 0;
    u32 count;

    if ((rcnts[0].mode & 7) == (RcSyncModeEnable | Rc01UnblankReset) ||
        (rcnts[0].mode & 7) == (RcSyncModeEnable | Rc01UnblankReset2))
    {
        count = psxRegs.cycle - rcnts[index].cycleStart;
        //count = ((16u * count) % (16u * PSXCLK / 60 / 263)) / 16u;
        count = count % lineCycles();
        rcnts[index].cycleStart = psxRegs.cycle - count;
    }
    else
        count = _psxRcntRcount( index );

    verboseLog( 2, "[RCNT 0] rcount: %04x m: %04x\n", count, rcnts[index].mode);

    return count;
}

u32 psxRcntRcount1()
{
    u32 index = 1;
    u32 count;

    count = _psxRcntRcount( index );

    verboseLog( 2, "[RCNT 1] rcount: %04x m: %04x\n", count, rcnts[index].mode);

    return count;
}

u32 psxRcntRcount2()
{
    u32 index = 2;
    u32 count;

    count = _psxRcntRcount( index );

    verboseLog( 2, "[RCNT 2] rcount: %04x m: %04x\n", count, rcnts[index].mode);

    return count;
}

u32 psxRcntRmode( u32 index )
{
    u16 mode;

    mode = rcnts[index].mode;
    rcnts[index].mode &= 0xe7ff;

    verboseLog( 2, "[RCNT %i] rmode: %x\n", index, mode );

    return mode;
}

u32 psxRcntRtarget( u32 index )
{
    verboseLog( 2, "[RCNT %i] rtarget: %x\n", index, rcnts[index].target );

    return rcnts[index].target;
}

/******************************************************************************/

void psxRcntInit()
{
    s32 i;

    // rcnt 0.
    rcnts[0].rate   = 1;
    rcnts[0].irq    = 0x10;

    // rcnt 1.
    rcnts[1].rate   = 1;
    rcnts[1].irq    = 0x20;

    // rcnt 2.
    rcnts[2].rate   = 1;
    rcnts[2].irq    = 0x40;

    // rcnt base.
    rcnts[3].rate   = 1;

    for( i = 0; i < CounterQuantity; ++i )
    {
        _psxRcntWcount( i, 0 );
    }

    hSyncCount = 0;
    hsync_steps = 1;

    scheduleRcntBase();
    psxRcntSet();
}

/******************************************************************************/

s32 psxRcntFreeze( void *f, s32 Mode )
{
    u32 spuSyncCount = 0;
    u32 count;
    s32 i;

    gzfreeze( &rcnts, sizeof(Rcnt) * CounterQuantity );
    gzfreeze( &hSyncCount, sizeof(hSyncCount) );
    gzfreeze( &spuSyncCount, sizeof(spuSyncCount) );
    gzfreeze( &psxNextCounter, sizeof(psxNextCounter) );
    gzfreeze( &psxNextsCounter, sizeof(psxNextsCounter) );

    if (Mode == 0)
    {
        rcnts[3].rate = 1;
        for( i = 0; i < CounterQuantity - 1; ++i )
        {
            _psxRcntWmode( i, rcnts[i].mode );
            count = (psxRegs.cycle - rcnts[i].cycleStart) / rcnts[i].rate;
            if (count > 0x1000)
                _psxRcntWcount( i, count & 0xffff );
        }
        scheduleRcntBase();
        psxRcntSet();
    }

    return 0;
}

/******************************************************************************/
// vim:ts=4:shiftwidth=4:expandtab
Commit	Line	Data
ef79bbde P	1	/***************************************************************************
	2	* Copyright (C) 2010 by Blade_Arma *
	3	* *
	4	* This program is free software; you can redistribute it and/or modify *
	5	* it under the terms of the GNU General Public License as published by *
	6	* the Free Software Foundation; either version 2 of the License, or *
	7	* (at your option) any later version. *
	8	* *
	9	* This program is distributed in the hope that it will be useful, *
	10	* but WITHOUT ANY WARRANTY; without even the implied warranty of *
	11	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
	12	* GNU General Public License for more details. *
	13	* *
	14	* You should have received a copy of the GNU General Public License *
	15	* along with this program; if not, write to the *
	16	* Free Software Foundation, Inc., *
	17	* 51 Franklin Street, Fifth Floor, Boston, MA 02111-1307 USA. *
	18	***************************************************************************/
	19
	20	/*
	21	* Internal PSX counters.
	22	*/
	23
	24	#include "psxcounters.h"
9a0a61d2	25	#include "psxevents.h"
ddbaf678	26	#include "gpu.h"
7d7672a5	27	//#include "debug.h"
7d7672a5	28	#define DebugVSync()
ef79bbde P	29
	30	/******************************************************************************/
	31
ef79bbde P	32	enum
ef79bbde P	33	{
11d23573	34	RcSyncModeEnable = 0x0001, // 0
	35	Rc01BlankPause = 0 << 1, // 1,2
	36	Rc01UnblankReset = 1 << 1, // 1,2
	37	Rc01UnblankReset2 = 2 << 1, // 1,2
	38	Rc2Stop = 0 << 1, // 1,2
	39	Rc2Stop2 = 3 << 1, // 1,2
ef79bbde P	40	RcCountToTarget = 0x0008, // 3
	41	RcIrqOnTarget = 0x0010, // 4
	42	RcIrqOnOverflow = 0x0020, // 5
	43	RcIrqRegenerate = 0x0040, // 6
	44	RcUnknown7 = 0x0080, // 7 ?
	45	Rc0PixelClock = 0x0100, // 8 fake implementation
	46	Rc1HSyncClock = 0x0100, // 8
	47	Rc2Unknown8 = 0x0100, // 8 ?
	48	Rc0Unknown9 = 0x0200, // 9 ?
	49	Rc1Unknown9 = 0x0200, // 9 ?
	50	Rc2OneEighthClock = 0x0200, // 9
	51	RcUnknown10 = 0x0400, // 10 ?
	52	RcCountEqTarget = 0x0800, // 11
	53	RcOverflow = 0x1000, // 12
	54	RcUnknown13 = 0x2000, // 13 ? (always zero)
	55	RcUnknown14 = 0x4000, // 14 ? (always zero)
	56	RcUnknown15 = 0x8000, // 15 ? (always zero)
	57	};
	58
	59	#define CounterQuantity ( 4 )
	60	//static const u32 CounterQuantity = 4;
	61
	62	static const u32 CountToOverflow = 0;
	63	static const u32 CountToTarget = 1;
	64
1351a8fb	65	static const u32 HSyncTotal[] = { 263, 314 };
1351a8fb	66	#define VBlankStart 240 // todo: depend on the actual GPU setting
ef79bbde	67
9f7ee52e	68	#define VERBOSE_LEVEL 0
ef79bbde P	69
ef79bbde P	70	/******************************************************************************/
41e82ad4	71	#ifdef DRC_DISABLE
b1be1eee	72	Rcnt rcnts[ CounterQuantity ];
41e82ad4	73	#endif
24de2dd4	74	u32 hSyncCount = 0;
24de2dd4	75	u32 frame_counter = 0;
61ef5cf4	76	static u32 hsync_steps = 0;
ef79bbde P	77
	78	u32 psxNextCounter = 0, psxNextsCounter = 0;
	79
	80	/******************************************************************************/
	81
1351a8fb	82	static inline
	83	u32 lineCycles(void)
	84	{
	85	if (Config.PsxType)
	86	return PSXCLK / 50 / HSyncTotal[1];
	87	else
	88	return PSXCLK / 60 / HSyncTotal[0];
	89	}
	90
ef79bbde P	91	static inline
	92	void setIrq( u32 irq )
	93	{
	94	psxHu32ref(0x1070) \|= SWAPu32(irq);
	95	}
	96
	97	static
9f7ee52e	98	void verboseLog( u32 level, const char *str, ... )
ef79bbde	99	{
9f7ee52e	100	#if VERBOSE_LEVEL > 0
3cf51e08	101	if( level <= VERBOSE_LEVEL )
ef79bbde P	102	{
	103	va_list va;
	104	char buf[ 4096 ];
	105
	106	va_start( va, str );
	107	vsprintf( buf, str, va );
	108	va_end( va );
	109
ab948f7e	110	printf( "%s", buf );
ef79bbde P	111	fflush( stdout );
ef79bbde P	112	}
9f7ee52e	113	#endif
ef79bbde P	114	}
	115
	116	/******************************************************************************/
	117
	118	static inline
	119	void _psxRcntWcount( u32 index, u32 value )
	120	{
20bfbac0	121	value &= 0xffff;
ef79bbde P	122
	123	rcnts[index].cycleStart = psxRegs.cycle;
	124	rcnts[index].cycleStart -= value * rcnts[index].rate;
	125
	126	// TODO: <=.
	127	if( value < rcnts[index].target )
	128	{
	129	rcnts[index].cycle = rcnts[index].target * rcnts[index].rate;
	130	rcnts[index].counterState = CountToTarget;
	131	}
	132	else
	133	{
8ca6b0a6	134	rcnts[index].cycle = 0x10000 * rcnts[index].rate;
ef79bbde P	135	rcnts[index].counterState = CountToOverflow;
	136	}
	137	}
	138
	139	static inline
	140	u32 _psxRcntRcount( u32 index )
	141	{
	142	u32 count;
	143
	144	count = psxRegs.cycle;
	145	count -= rcnts[index].cycleStart;
61ef5cf4	146	if (rcnts[index].rate > 1)
61ef5cf4	147	count /= rcnts[index].rate;
ef79bbde	148
8ca6b0a6	149	if( count > 0x10000 )
ef79bbde	150	{
8ca6b0a6	151	verboseLog( 1, "[RCNT %i] rcount > 0x10000: %x\n", index, count );
ef79bbde	152	}
8ca6b0a6	153	count &= 0xffff;
ef79bbde P	154
	155	return count;
	156	}
	157
a29f182f	158	static
	159	void _psxRcntWmode( u32 index, u32 value )
	160	{
	161	rcnts[index].mode = value;
	162
	163	switch( index )
	164	{
	165	case 0:
	166	if( value & Rc0PixelClock )
	167	{
	168	rcnts[index].rate = 5;
	169	}
	170	else
	171	{
	172	rcnts[index].rate = 1;
	173	}
	174	break;
	175	case 1:
	176	if( value & Rc1HSyncClock )
	177	{
1351a8fb	178	rcnts[index].rate = lineCycles();
a29f182f	179	}
	180	else
	181	{
	182	rcnts[index].rate = 1;
	183	}
	184	break;
	185	case 2:
	186	if( value & Rc2OneEighthClock )
	187	{
	188	rcnts[index].rate = 8;
	189	}
	190	else
	191	{
	192	rcnts[index].rate = 1;
	193	}
	194
	195	// TODO: wcount must work.
11d23573	196	if( (value & 7) == (RcSyncModeEnable \| Rc2Stop) \|\|
11d23573	197	(value & 7) == (RcSyncModeEnable \| Rc2Stop2) )
a29f182f	198	{
	199	rcnts[index].rate = 0xffffffff;
	200	}
	201	break;
	202	}
	203	}
	204
ef79bbde P	205	/******************************************************************************/
	206
	207	static
	208	void psxRcntSet()
	209	{
	210	s32 countToUpdate;
	211	u32 i;
	212
	213	psxNextsCounter = psxRegs.cycle;
	214	psxNextCounter = 0x7fffffff;
	215
	216	for( i = 0; i < CounterQuantity; ++i )
	217	{
	218	countToUpdate = rcnts[i].cycle - (psxNextsCounter - rcnts[i].cycleStart);
	219
	220	if( countToUpdate < 0 )
	221	{
	222	psxNextCounter = 0;
	223	break;
	224	}
	225
	226	if( countToUpdate < (s32)psxNextCounter )
	227	{
	228	psxNextCounter = countToUpdate;
	229	}
	230	}
5b8c000f	231
9a0a61d2	232	set_event(PSXINT_RCNT, psxNextCounter);
ef79bbde P	233	}
	234
	235	/******************************************************************************/
	236
	237	static
	238	void psxRcntReset( u32 index )
	239	{
8ca6b0a6	240	u32 rcycles;
ef79bbde	241
53c361f0	242	rcnts[index].mode \|= RcUnknown10;
53c361f0	243
ef79bbde P	244	if( rcnts[index].counterState == CountToTarget )
ef79bbde P	245	{
8ca6b0a6	246	rcycles = psxRegs.cycle - rcnts[index].cycleStart;
ef79bbde	247	if( rcnts[index].mode & RcCountToTarget )
8ca6b0a6	248	{
	249	rcycles -= rcnts[index].target * rcnts[index].rate;
	250	rcnts[index].cycleStart = psxRegs.cycle - rcycles;
	251	}
	252	else
	253	{
	254	rcnts[index].cycle = 0x10000 * rcnts[index].rate;
	255	rcnts[index].counterState = CountToOverflow;
	256	}
ef79bbde P	257
	258	if( rcnts[index].mode & RcIrqOnTarget )
	259	{
	260	if( (rcnts[index].mode & RcIrqRegenerate) \|\| (!rcnts[index].irqState) )
	261	{
8ca6b0a6	262	verboseLog( 3, "[RCNT %i] irq\n", index );
ef79bbde P	263	setIrq( rcnts[index].irq );
	264	rcnts[index].irqState = 1;
	265	}
	266	}
	267
	268	rcnts[index].mode \|= RcCountEqTarget;
53c361f0	269
8ca6b0a6	270	if( rcycles < 0x10000 * rcnts[index].rate )
53c361f0	271	return;
ef79bbde	272	}
53c361f0	273
53c361f0	274	if( rcnts[index].counterState == CountToOverflow )
ef79bbde	275	{
8ca6b0a6	276	rcycles = psxRegs.cycle - rcnts[index].cycleStart;
	277	rcycles -= 0x10000 * rcnts[index].rate;
	278
	279	rcnts[index].cycleStart = psxRegs.cycle - rcycles;
ef79bbde	280
8ca6b0a6	281	if( rcycles < rcnts[index].target * rcnts[index].rate )
	282	{
	283	rcnts[index].cycle = rcnts[index].target * rcnts[index].rate;
	284	rcnts[index].counterState = CountToTarget;
	285	}
ef79bbde P	286
	287	if( rcnts[index].mode & RcIrqOnOverflow )
	288	{
	289	if( (rcnts[index].mode & RcIrqRegenerate) \|\| (!rcnts[index].irqState) )
	290	{
8ca6b0a6	291	verboseLog( 3, "[RCNT %i] irq\n", index );
ef79bbde P	292	setIrq( rcnts[index].irq );
	293	rcnts[index].irqState = 1;
	294	}
	295	}
	296
	297	rcnts[index].mode \|= RcOverflow;
	298	}
ef79bbde P	299	}
ef79bbde P	300
ff2c2822	301	static void scheduleRcntBase(void)
	302	{
	303	// Schedule next call, in hsyncs
	304	if (hSyncCount < VBlankStart)
	305	hsync_steps = VBlankStart - hSyncCount;
	306	else
	307	hsync_steps = HSyncTotal[Config.PsxType] - hSyncCount;
	308
	309	if (hSyncCount + hsync_steps == HSyncTotal[Config.PsxType])
	310	{
	311	rcnts[3].cycle = Config.PsxType ? PSXCLK / 50 : PSXCLK / 60;
	312	}
	313	else
	314	{
	315	// clk / 50 / 314 ~= 2157.25
	316	// clk / 60 / 263 ~= 2146.31
	317	u32 mult = Config.PsxType ? 8836089 : 8791293;
	318	rcnts[3].cycle = hsync_steps * mult >> 12;
	319	}
	320	}
	321
ef79bbde P	322	void psxRcntUpdate()
ef79bbde P	323	{
11d23573	324	u32 cycle, cycles_passed;
ef79bbde P	325
	326	cycle = psxRegs.cycle;
	327
	328	// rcnt 0.
11d23573	329	cycles_passed = cycle - rcnts[0].cycleStart;
11d23573	330	while( cycles_passed >= rcnts[0].cycle )
ef79bbde	331	{
11d23573	332	if (((rcnts[0].mode & 7) == (RcSyncModeEnable \| Rc01UnblankReset) \|\|
11d23573	333	(rcnts[0].mode & 7) == (RcSyncModeEnable \| Rc01UnblankReset2))
1351a8fb	334	&& cycles_passed > lineCycles())
11d23573	335	{
1351a8fb	336	u32 q = cycles_passed / (lineCycles() + 1u);
1351a8fb	337	rcnts[0].cycleStart += q * lineCycles();
11d23573	338	break;
	339	}
	340	else
	341	psxRcntReset( 0 );
	342
	343	cycles_passed = cycle - rcnts[0].cycleStart;
ef79bbde P	344	}
	345
	346	// rcnt 1.
e7851504	347	while( cycle - rcnts[1].cycleStart >= rcnts[1].cycle )
ef79bbde P	348	{
	349	psxRcntReset( 1 );
	350	}
	351
	352	// rcnt 2.
e7851504	353	while( cycle - rcnts[2].cycleStart >= rcnts[2].cycle )
ef79bbde P	354	{
	355	psxRcntReset( 2 );
	356	}
	357
	358	// rcnt base.
	359	if( cycle - rcnts[3].cycleStart >= rcnts[3].cycle )
	360	{
61ef5cf4	361	hSyncCount += hsync_steps;
ef79bbde	362
ef79bbde	363	// VSync irq.
0486fdc9	364	if( hSyncCount == VBlankStart )
ef79bbde	365	{
086adfff	366	HW_GPU_STATUS &= SWAP32(~PSXGPU_LCF);
72e5023f	367	GPU_vBlank( 1, 0 );
8bbbd091	368	setIrq( 0x01 );
	369
	370	EmuUpdate();
	371	GPU_updateLace();
d618a240	372
	373	if( SPU_async )
	374	{
	375	SPU_async( cycle, 1 );
	376	}
ef79bbde P	377	}
ef79bbde P	378
d014a471	379	// Update lace.
d014a471	380	if( hSyncCount >= HSyncTotal[Config.PsxType] )
ef79bbde	381	{
1351a8fb	382	u32 status, field = 0;
ff2c2822	383	rcnts[3].cycleStart += Config.PsxType ? PSXCLK / 50 : PSXCLK / 60;
ef79bbde	384	hSyncCount = 0;
ddbaf678	385	frame_counter++;
ef79bbde	386
0486fdc9	387	gpuSyncPluginSR();
db57cbb8	388	status = SWAP32(HW_GPU_STATUS) \| PSXGPU_FIELD;
	389	if ((status & PSXGPU_ILACE_BITS) == PSXGPU_ILACE_BITS) {
	390	field = frame_counter & 1;
	391	status \|= field << 31;
	392	status ^= field << 13;
	393	}
	394	HW_GPU_STATUS = SWAP32(status);
	395	GPU_vBlank(0, field);
f8896d18	396	if ((s32)(psxRegs.gpuIdleAfter - psxRegs.cycle) < 0)
f8896d18	397	psxRegs.gpuIdleAfter = psxRegs.cycle - 1; // prevent overflow
11d23573	398
1351a8fb	399	if ((rcnts[0].mode & 7) == (RcSyncModeEnable \| Rc01UnblankReset) \|\|
	400	(rcnts[0].mode & 7) == (RcSyncModeEnable \| Rc01UnblankReset2))
	401	{
	402	rcnts[0].cycleStart = rcnts[3].cycleStart;
	403	}
	404
	405	if ((rcnts[1].mode & 7) == (RcSyncModeEnable \| Rc01UnblankReset) \|\|
	406	(rcnts[1].mode & 7) == (RcSyncModeEnable \| Rc01UnblankReset2))
	407	{
	408	rcnts[1].cycleStart = rcnts[3].cycleStart;
	409	}
	410	else if (rcnts[1].mode & Rc1HSyncClock)
11d23573	411	{
1351a8fb	412	// adjust to remove the rounding error
1351a8fb	413	_psxRcntWcount(1, (psxRegs.cycle - rcnts[1].cycleStart) / rcnts[1].rate);
11d23573	414	}
ef79bbde	415	}
61ef5cf4	416
ff2c2822	417	scheduleRcntBase();
ef79bbde P	418	}
ef79bbde P	419
95df1a04	420	psxRcntSet();
95df1a04	421
7a8d521f	422	#if 0 //ndef NDEBUG
ef79bbde	423	DebugVSync();
61ef5cf4	424	#endif
ef79bbde P	425	}
	426
	427	/******************************************************************************/
	428
	429	void psxRcntWcount( u32 index, u32 value )
	430	{
	431	verboseLog( 2, "[RCNT %i] wcount: %x\n", index, value );
	432
ef79bbde P	433	_psxRcntWcount( index, value );
	434	psxRcntSet();
	435	}
	436
	437	void psxRcntWmode( u32 index, u32 value )
	438	{
	439	verboseLog( 1, "[RCNT %i] wmode: %x\n", index, value );
	440
a29f182f	441	_psxRcntWmode( index, value );
ef79bbde	442	_psxRcntWcount( index, 0 );
a29f182f	443
a29f182f	444	rcnts[index].irqState = 0;
ef79bbde P	445	psxRcntSet();
	446	}
	447
	448	void psxRcntWtarget( u32 index, u32 value )
	449	{
	450	verboseLog( 1, "[RCNT %i] wtarget: %x\n", index, value );
	451
ef79bbde P	452	rcnts[index].target = value;
	453
	454	_psxRcntWcount( index, _psxRcntRcount( index ) );
	455	psxRcntSet();
	456	}
	457
	458	/******************************************************************************/
	459
11d23573	460	u32 psxRcntRcount0()
	461	{
	462	u32 index = 0;
	463	u32 count;
	464
	465	if ((rcnts[0].mode & 7) == (RcSyncModeEnable \| Rc01UnblankReset) \|\|
	466	(rcnts[0].mode & 7) == (RcSyncModeEnable \| Rc01UnblankReset2))
	467	{
	468	count = psxRegs.cycle - rcnts[index].cycleStart;
1351a8fb	469	//count = ((16u * count) % (16u * PSXCLK / 60 / 263)) / 16u;
1351a8fb	470	count = count % lineCycles();
11d23573	471	rcnts[index].cycleStart = psxRegs.cycle - count;
	472	}
	473	else
	474	count = _psxRcntRcount( index );
	475
	476	verboseLog( 2, "[RCNT 0] rcount: %04x m: %04x\n", count, rcnts[index].mode);
	477
	478	return count;
	479	}
	480
	481	u32 psxRcntRcount1()
	482	{
	483	u32 index = 1;
	484	u32 count;
	485
	486	count = _psxRcntRcount( index );
	487
	488	verboseLog( 2, "[RCNT 1] rcount: %04x m: %04x\n", count, rcnts[index].mode);
	489
	490	return count;
	491	}
	492
	493	u32 psxRcntRcount2()
ef79bbde	494	{
11d23573	495	u32 index = 2;
ef79bbde P	496	u32 count;
ef79bbde P	497
ef79bbde P	498	count = _psxRcntRcount( index );
ef79bbde P	499
11d23573	500	verboseLog( 2, "[RCNT 2] rcount: %04x m: %04x\n", count, rcnts[index].mode);
ef79bbde P	501
	502	return count;
	503	}
	504
	505	u32 psxRcntRmode( u32 index )
	506	{
	507	u16 mode;
	508
ef79bbde P	509	mode = rcnts[index].mode;
	510	rcnts[index].mode &= 0xe7ff;
	511
	512	verboseLog( 2, "[RCNT %i] rmode: %x\n", index, mode );
	513
	514	return mode;
	515	}
	516
	517	u32 psxRcntRtarget( u32 index )
	518	{
	519	verboseLog( 2, "[RCNT %i] rtarget: %x\n", index, rcnts[index].target );
	520
	521	return rcnts[index].target;
	522	}
	523
	524	/******************************************************************************/
	525
	526	void psxRcntInit()
	527	{
	528	s32 i;
	529
	530	// rcnt 0.
	531	rcnts[0].rate = 1;
	532	rcnts[0].irq = 0x10;
	533
	534	// rcnt 1.
	535	rcnts[1].rate = 1;
	536	rcnts[1].irq = 0x20;
	537
	538	// rcnt 2.
	539	rcnts[2].rate = 1;
	540	rcnts[2].irq = 0x40;
	541
	542	// rcnt base.
	543	rcnts[3].rate = 1;
ef79bbde P	544
	545	for( i = 0; i < CounterQuantity; ++i )
	546	{
	547	_psxRcntWcount( i, 0 );
	548	}
	549
c62b43c9	550	hSyncCount = 0;
61ef5cf4	551	hsync_steps = 1;
c62b43c9	552
1351a8fb	553	scheduleRcntBase();
ef79bbde P	554	psxRcntSet();
	555	}
	556
	557	/******************************************************************************/
	558
496d88d4	559	s32 psxRcntFreeze( void *f, s32 Mode )
ef79bbde	560	{
d618a240	561	u32 spuSyncCount = 0;
d0af6d75	562	u32 count;
a29f182f	563	s32 i;
a29f182f	564
41e82ad4	565	gzfreeze( &rcnts, sizeof(Rcnt) * CounterQuantity );
ef79bbde P	566	gzfreeze( &hSyncCount, sizeof(hSyncCount) );
	567	gzfreeze( &spuSyncCount, sizeof(spuSyncCount) );
	568	gzfreeze( &psxNextCounter, sizeof(psxNextCounter) );
	569	gzfreeze( &psxNextsCounter, sizeof(psxNextsCounter) );
	570
61ef5cf4	571	if (Mode == 0)
a29f182f	572	{
e43c9382	573	rcnts[3].rate = 1;
b34d6a80	574	for( i = 0; i < CounterQuantity - 1; ++i )
d0af6d75	575	{
a29f182f	576	_psxRcntWmode( i, rcnts[i].mode );
d0af6d75	577	count = (psxRegs.cycle - rcnts[i].cycleStart) / rcnts[i].rate;
	578	if (count > 0x1000)
	579	_psxRcntWcount( i, count & 0xffff );
	580	}
ff2c2822	581	scheduleRcntBase();
a29f182f	582	psxRcntSet();
a29f182f	583	}
4f55097d	584
ef79bbde P	585	return 0;
	586	}
	587
	588	/******************************************************************************/
ff2c2822	589	// vim:ts=4:shiftwidth=4:expandtab